VIN
LX
BOOT
ENB
TSET
GND
VBIAS
FB
+42
V
220 µF
25 V
ESR
VOUT
COUT
3.3 V / 3 A
6.34 kΩ
R1
L 1
D1 R2
2 kΩ
0.22 µF
0.01 µF
CBOOT
CIN2 CIN1
RTSET
63.4 kΩ
68 µH
220 µF
50 V
A8498
Efficiency vs. Output Current
70.0
72.0
74.0
76.0
78.0
80.0
82.0
84.0
86.0
88.0
90.0
0 500 1000 1500 2000 2500 3000
I
OUT
(mA)
Efficiency %
VOUT (V)
5
3.3
Circuit for 42 V step down to 3.3 V at 3 A. Efficiency data from circuit shown in left panel. Data is for reference only.
Approximate Scale 1:1
A8498
The A8498 is a step down regulator that will handle a wide
input operating voltage range.
The A8498 is supplied in a low-profile 8-lead SOIC with
exposed pad (package LJ). Applications include:
• Applications with 8 to 50 V input voltage range needing
buck regulator for 3.0 A output current
• Consumer equipment power
• Uninterruptible power supplies (lead acid battery
charger)
• Automotive telematics: 9 to 16 V input, with higher
voltage protection
• 12 V lighter-powered applications (portable DVD, etc.)
• Point of Sale (POS) applications
• Industrial applications with 24 or 36 V bus
A8498-DS, Rev. 7
• 8 to 50 V input range
• Integrated DMOS switch
• Adjustable fixed off-time
• Highly efficient
• Adjustable 0.8 to 24 V output
Wide Input Voltage 3.0 A Step Down Regulator
Typical Application
Package: 8-Lead SOIC with Exposed Ther-
mal Pad (suffix LJ)
FEATURES AND BENEFITS DESCRIPTION
Wide Input Voltage 3.0 A Step Down Regulator
A8498
2
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Absolute Maximum Ratings
Characteristic Symbol Conditions Min. Typ. Max. Units
Load Supply Voltage, VIN pin VIN – – 50 V
Input Voltage, VBIAS pin VBIAS –0.3 – 7 V
Switching Voltage VS–1 – – V
Input Voltage Range, ENB pin VENB –0.3 – 7 V
Operating Ambient Temperature Range TA –20 – 85 °C
Junction Temperature TJ(max) – – 150 °C
Storage Temperature TS–55 – 150 °C
*Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specied current ratings, or a
junction temperature, TJ, of 150°C.
Package Thermal Characteristics*
Package RθJA
(°C/W) PCB
LJ 35 4-layer
* Additional information is available on the Allegro website.
Ordering Information
Use the following complete part numbers when ordering:
Part NumberaPackingbDescription
A8498SLJTR-T 13 in. reel, 3000 pieces/reel LJ package, SOIC surface mount with
exposed thermal pad
aLeadframe plating 100% matte tin.
bContact Allegro for additional packing options.
SPECIFICATIONS
Wide Input Voltage 3.0 A Step Down Regulator
A8498
3
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Block Diagram
+
–
+
–
+–
Switch PWM Control
µC
Soft Start
Ramp Generation
COMP
0.8 V
Boot Charge
VBIAS is connected to VOUT
when V
OUT
target is between
3.3 and 5 V
D1
L1
VIN
COUT
VOUT
ESR
VBB UVLO
TSD
Switch
Disable
Bias Supply
I_Peak I_Demand
Clamp
Error
BOOT
ENB
TSET
GND
VIN
LX
FB
VBIAS
Package LJ, 8-Pin SOIC Pin Out Diagram
1
2
3
4
8
7
6
5
BOOT
ENB
TSET
GND
VIN
LX
VBIAS
FB
Pad
Terminal List Table
Number Name Description
1 BOOT Gate drive boost node
2 ENB On/off control; logic input
3 TSET Off-time setting
4 GND Ground
5 FB Feedback for adjustable regulator
6 VBIAS Bias supply input
7 LX Buck switching node
8 VIN Supply input
Wide Input Voltage 3.0 A Step Down Regulator
A8498
4
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Characteristics Symbol Test Conditions Min. Typ. Max. Units
VIN Quiescent Current IVIN(Q)
VENB = LOW, VIN = 42 V, VBIAS = 3.2 V,
VFB = 1.5 V (not switching) – 0.90 1.35 mA
VENB = LOW, VIN = 42 V, VBIAS < 3 V,
VFB = 1.5 V – 4.4 6.35 mA
VENB = HIGH – – 100 µA
VBIAS Input Current IBIAS VBIAS = VOUT – 3.5 5 mA
Buck Switch On Resistance RDS(on)
TA = 25°C, IOUT = 3 A – 450 – mΩ
TA = 125°C, IOUT = 3 A – 650 – mΩ
Fixed Off-Time Proportion Based on calculated value –15 – 15 %
Feedback Voltage VFB 0.784 0.8 0.816 V
Output Voltage Regulation VOUT IOUT = 0 mA to 3 A –3 – 3 %
Feedback Input Bias Current IFB –400 –100 100 nA
Soft Start Time tss 5 10 15 ms
Buck Switch Current Limit ICL
VFB > 0.4 V 3.5 – 5 A
VFB < 0.4 V 0.5 – 1.5 A
ENB Open Circuit Voltage VOC Output disabled 2.0 – 7 V
ENB Input Voltage Threshold VENB(0) LOW level input (Logic 0), output enabled – – 1.0 V
ENB Input Current IENB(0) VENB = 0 V –10 – –1 µA
VIN Undervoltage Threshold VUVLO VIN rising 6.6 6.9 7.2 V
VIN Undervoltage Hysteresis VUVLO(hys) VIN falling 0.7 – 1.1 V
Thermal Shutdown Temperature TJTSD Temperature increasing – 165 – °C
Thermal Shutdown Hysteresis TJTSD(hys) Recovery = TJTSD – TJTSD(hys) – 15 – °C
1Negative current is dened as coming out of (sourcing) the specied device pin.
2Specications over the junction temperature range of 0ºC to 125ºC are assured by design and characterization.
ELECTRICAL CHARACTERISTICS1,2 at TA = 25°C, VIN = 8 to 50 V (unless noted otherwise)
Wide Input Voltage 3.0 A Step Down Regulator
A8498
5
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
FUNCTIONAL DESCRIPTION
The A8498 is a fixed off-time, current-mode–controlled buck
switching regulator. The regulator requires an external clamping
diode, inductor, and filter capacitor, and operates in both continu-
ous and discontinuous modes. An internal blanking circuit is used
to filter out transients resulting from the reverse recovery of the
external clamp diode. Typical blanking time is 200 ns.
The value of a resistor between the TSET pin and ground deter-
mines the fixed off-time (see graph in the tOFF section).
VOUT. The output voltage is adjustable from 0.8 to 24 V, based on
the combination of the value of the external resistor divider and
the internal 0.8 V ±2% reference. The voltage can be calculated
with the following formula:
VOUT = VFB × (1 + R1/R2) (1)
Light Load Regulation
To maintain voltage regulation during light load conditions, the
switching regulator enters a cycle-skipping mode. As the output
current decreases, there remains some energy that is stored during
the power switch minimum on-time. In order to prevent the out-
put voltage from rising, the regulator skips cycles once it reaches
the minimum on-time, effectively making the off-time larger.
Soft Start
An internal ramp generator and counter allow the output to
slowly ramp up. This limits the maximum demand on the external
power supply by controlling the inrush current required to charge
the external capacitor and any dc load at startup. Internally, the
ramp is set to 10 ms nominal rise time. During soft start, current
limit is 3.5 A minimum.
The following conditions are required to trigger a soft start:
• VIN > 6 V
• ENB pin input falling edge
• Reset of a TSD (thermal shut down) event
VBIAS
To improve overall system efficiency, the regulator output, VOUT,
is connected to the VBIAS input to supply the operating bias cur-
rent during normal operating conditions. During startup the cir-
cuitry is run off of the VIN supply. VBIAS should be connected
to VOUT when the VOUT target level is between 3.3 and 5 V. If
the output voltage is less than 3.3 V, then the A8498 can operate
with an internal supply and pay a penalty in efficiency, as the bias
current will come from the high voltage supply, VIN. VBIAS can
also be supplied with an external voltage source. No power-up
sequencing is required for normal operation.
ON/OFF Control
The ENB pin is externally pulled to ground to enable the device
and begin the soft start sequence. When the ENB is open cir-
cuited, the switcher is disabled and the output decays to 0 V.
Protection
The buck switch will be disabled under one or more of the fol-
lowing fault conditions:
• VIN < 6 V
• ENB pin = open circuit
• TSD fault
When the device comes out of a TSD fault, it will go into a soft
start to limit inrush current.
tOFF
The value of a resistor between the TSET pin and ground deter-
mines the fixed off-time. The formula to calculate tOFF (µs) is:
,
tOFF RTSET
=
10.2 × 10
9
1–0.03 V
BIAS
(2)
where RTSET (kΩ) is the value of the resistor. Results are shown
in the following graph:
0
20
40
60
80
100
120
140
160
180
200
12 345678 910111213141516
Off-Time Setting versus Resistor Value
R
TSET
(kΩ)
t
OFF
(µs)
V
BIAS
= 5 V
V
BIAS
= 3.3 V
Wide Input Voltage 3.0 A Step Down Regulator
A8498
6
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
tON.
From the volt-second balance of the inductor, the turn-on time,
ton , can be calculated approximately by the equation:
=
t
ON
(VOUT + Vf + IOUT RL) tOFF
VIN – IOUT RDS(on) – IOUT RL – VOUT
(3)
where
Vf is the voltage drop across the external Schottky diode,
RL is the winding resistance of the inductor, and
RDS(on) is the on-resistance of the switching MOSFET.
The switching frequency is calculated as follows:
=
f
SW
1
tON + tOFF
(4)
Shorted Load
If the voltage on the FB pin falls below 0.4 V, the regulator will
invoke a 1.5 A typical overcurrent limit to handle the shorted
load condition at the regulator output. For low output voltages
at power up and in the case of a shorted output, the offtime is
extended to prevent loss of control of the current limit due to the
minimum on-time of the switcher.
The extension of the off-time is based on the value of the TSET
multiplier and the FB voltage, as shown in the following table:
VFB (V) TSET Multi-
plier
< 0.16 8 × tOFF
< 0.32 4 × tOFF
< 0.5 2 × tOFF
> 0.5 tOFF
Wide Input Voltage 3.0 A Step Down Regulator
A8498
7
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
COMPONENT SELECTION
L1
The inductor must be rated to handle the total load current. The
value should be chosen to keep the ripple current to a reasonable
value. The ripple current, IRIPPLE, can be calculated by:
IRIPPLE = VL(OFF) × tOFF / L (5)
VL(OFF) = VOUT + Vf + IL(AV) × RL (6)
Example:
Given VOUT = 5 V, Vf = 0.55 V, VIN = 42 V, ILOAD = 0.5 A, power
inductor with L = 180 µH and RL = 0.5 Ω Rdc at 55°C, tOFF =
7 µs, and RDS(on) = 0.5 Ω.
Substituting into equation 6:
VL(OFF) = 5 V + 0.55 V+ 0.5 A × 0.5 Ω = 5.8 V
Substituting into equation 5:
IRIPPLE = 5.8 V × 7 µs / 180 µH = 225 mA
The switching frequency, fSW, can then be estimated by:
fSW = 1 / ( tON + tOFF ) (7)
tON = IRIPPLE × L / VL(ON) (8)
VL(ON) = VIN – IL(AV) × RDS(on) – IL(AV) × RL– VOUT (9)
Substituting into equation 9:
VL(ON) = 42 V – 0.5 A × 0.5 Ω – 0.5 A × 0.5 Ω – 5 V = 36.5 V
Substituting into equation 8:
tON = 225 mA × 180 µH / 36.5 V = 1.11 µs
Substituting into equation 7:
fSW = 1 / (7 µs +1.11 µs) = 123 kHz
Higher inductor values can be chosen to lower the ripple cur-
rent. This may be an option if it is required to increase the total
maximum current available above that drawn from the switching
regulator. The maximum total current available, ILOAD(MAX) , is:
ILOAD(MAX) = ICL(min) – IRIPPLE / 2 (10)
where ICL(min) is 3.5 A, from the Electrical Chracteristics table.
D1
The Schottky catch diode should be rated to handle 1.2 times the
maximum load current. The voltage rating should be higher than
the maximum input voltage expected during all operating condi-
tions. The duty cycle for high input voltages can be very close to
100%.
COUT
The main consideration in selecting an output capacitor is volt-
age ripple on the output. For electrolytic output capacitors, a
low-ESR type is recommended.
The peak-to-peak output voltage ripple is simply IRIPPLE × ESR.
Note that increasing the inductor value can decrease the ripple
current. The ESR should be in the range from 50 to 500 mΩ.
Wide Input Voltage 3.0 A Step Down Regulator
A8498
8
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
RTSET Selection
Correct selection of RTSET values will ensure that minimum on
time of the switcher is not violated and prevent the switcher from
cycle skipping. For a given VIN to VOUT ratio, the RTSET value
must be greater than or equal to the value defined by the curve in
the plot below.
Note. The curve represents the minimum RTSET value. When
calculating RTSET , be sure to use VIN(max) / VOUT(min). Resistor
tolerance should also be considered, so that under no operating
conditions the resistance on the TSET pin is allowed to go below
the minimum value.
FB Resistor Selection
The impedance of the FB network should be kept low to improve
noise immunity. Large value resistors can pick up noise gener-
ated by the inductor, which can affect voltage regulation of the
switcher.
RTSET (kΩ)
V
IN / V
OUT
Violation of
Minimum On-Time
Safe Operating Area
Minimum Value of R
TSET
13.0
12.5
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
70.0
67.5
65.0
62.5
60.0
57.5
55.0
52.5
50.0
47.5
45.0
42.5
40.0
37.5
35.0
32.5
30.0
27.5
25.0
22.5
20.0
17.5
15.0
12.5
10.0
Recommended Components
Component
VIN = 42 V
(Through Hole)
VIN = 24 V
(SMD)
VIN = 12 V
(SMD)
Description Part Number Description Part Number Description Part Number
Inductor Sumida, 68 μH RCH1216BNP-680K 47 µH, 53 mΩ, 3.9 A, ±20% CDRH127/LDNP-470MC 33 µH, 53 mΩ, 3.9 A,
±20% CDRH127/LDNP-330MC
Diode
NIEC Schottky
Barrier, 60 V,
TO-252AA
NSQ03A06 Schottky, 30V, 3A, SMA B330 Schottky, 20 V, 3 A,
SMA B320
CBOOT Ceramic X7A,
0.01 μF, 100 V Generic Ceramic, X7R, ±10%,
0.01 µF / 50 V
C0603C103K5RACTU
(Kemet)
Ceramic, X7R, ±10%,
0.01 µF / 50 V
C0603C103K5RACTU
(Kemet)
CIN1 Ceramic X7A,
0.22 μF, 50 V Generic Ceramic, X7R, ±10%,
0.1 µF / 50 V
GRM188R71H104KA93D
(Murata)
Ceramic, X7R, ±10%,
0.1 µF / 50 V
GRM188R71H104KA93D
(Murata)
CIN2 Rubycon ZL,
220 μF, 50 V
50-ZL-220-M-10
X 16
Aluminum electrolytic,
35 V / 82 µF, 930 mA
ripple current
35V-ZAV-820-8 X 12 (two)
Aluminum electrolytic,
35 V / 82 µF, 930 mA
ripple current
35V-ZAV-820-8 X 12 (two)
COUT Rubycon ZL,
220 μF, 25 V
25-ZL-220-M-8 X
11.5
Aluminum electrolytic ,
6.3 V / 330 µF, 450 mA
ripple current
EEVFC0J331P
(Panasonic)
Aluminum electrolytic,
6.3 V / 330 µF, 450 mA
ripple current
EEVFC0J331P
(Panasonic)
R1
2.55 kΩ at VOUT = 1.8 V
6.34 kΩ at VOUT = 3.3 V
10.5 kΩ at VOUT = 5.0 V
2.55 kΩ at VOUT = 1.8 V
6.34 kΩ at VOUT = 3.3 V
10.5 kΩ at VOUT = 5.0 V
2.55 kΩ at VOUT = 1.8 V
6.34 kΩ at VOUT = 3.3 V
10.5 kΩ at VOUT = 5.0 V
R2 2 kΩ 2 kΩ 2 kΩ
RTSET 63.4 kΩ 47.5 kΩ 35.2 kΩ
Wide Input Voltage 3.0 A Step Down Regulator
A8498
9
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package LJ 8-Pin SOIC with Exposed Thermal Pad
For Reference Only – Not for Tooling Use
(Reference MS-012BA)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
3.30
2
1
8
C
1.27
5.602.41
1.75
0.65
2.41 NOM
3.30 NOM
C
1.27 BSC
A
B
C
B
21
8
C
SEATING
PLANE
C0.10
8X
0.25 BSC
1.04 REF
1.70 MAX
4.90 ±0.10
3.90 ±0.10 6.00 ±0.20
0.51
0.31 0.15
0.00
0.25
0.17
1.27
0.40
8°
0°
A
Branded Face SEATING PLANE
GAUGE PLANE
PCB Layout Reference View
Terminal #1 mark area
Exposed thermal pad (bottom surface)
Reference land pattern layout (reference IPC7351 SOIC127P600X175-9AM);
all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
PACKAGE OUTLINE DRAWING
Wide Input Voltage 3.0 A Step Down Regulator
A8498
10
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Copyright ©2006-2016, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Revision History
Revision Revision Date Description of Revision
6 September 10, 2014 Revised ICL Max. spec.
7 July 7, 2016 Revised VENB Max. spec.
