CY27EE16FZEXCT - Cypress Semiconductor

1 PLL In-System Programmable Clock Generat

with Individual 16K EEPRO

CY27EE16Z

Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600

Document #: 38-07440 Rev. *B Revised June 30, 2003

Features Benefits

• 18 kbits of EEPROM

16 kbits independent scratch

2 kbits dedicated to clocking functions

Higher level of integration and reduced component count by

combin ing EEPROM and PLL . Indepen dent EEPROM may be used

for scratch memory, or to store up to eight clock configurations

• Integrated, phase-locked loop with programmable P

and Q counters, output dividers, and optional

analog VCXO, digital VCXO, spread spectrum for

EMI reduction

High-performance PLL enables control of output frequencies that are

customizable to support a wide range of applications

• In system programma ble through I2C Serial

Programming Interface (SPI). Both the SRAM and

non-volatile EEPROM memory bits are program-

mable with the 3.3V supply

Familiar industry standard eases programming effort and enables

update of data stored in 16K EEPROM scratchpad and 2K EEPROM

clock control block while CY27EE16ZE is installed in system

• Low-jitter, high-accuracy outputs Meets c ritical timing requirements in complex system designs

• VCXO with analog adjust Write Protect (WP pin) can be programmed to serve as an analog

control voltage for a VCXO.The VCXO function is still available with

a DCXO, or dig itally controlled (through SPI) crystal oscillator if the

pin is functi oni ng as WP

• 3.3V Operation (optional 2.5V outputs) Meets indust ry-standard voltage platforms

• 20-lead Exposed Pad, EP-TSSOP Industry standard packaging saves on board space

Part Number Outputs Input Frequency Range Output Frequency Range

CY27EE16ZE 6 1 – 167 MHz (Driven Clock Input) {Commercial}

1 –150 MHz (Driven Clock Input) {Industrial}

8 – 30 MHz (Crystal Reference) {Comm. or Ind.}

80 kHz – 200 MHz (3.3V) {Commercial}

80 kHz –167 MHz (3.3V) {Industrial}

80 kHz –167 MHz (2.5V) {Commercial}

80 kHz – 150 MHz (2.5V) {Industrial}

Logic Block Diagram

XIN

XOUT

CLOCK2

OUTPUT

DIVIDERS

PLL

OSC

CLOCK1

QVCO

VDD VSS

CLOCK3

Pin Configurations

SCL

SDAT

8x2k EEPROM

Memory Array

Clock

Configuration

Output

Crosspoint

Switch

Array

CLOCK5

CLOCK4

CLOCK6

[I2C- SPI:]

20-pin EP-TSSOP

AVDD AVSSVDDL VSSL

CY27EE16ZE

PDM/OE

XIN

XOUT

VDD

CLOCK6

CLOCK5

AVDD

VCXO/WP

SDAT

VSS

AVSS

CLOCK4

VSSL

VDDL

CLOCK1

SCL

CLOCK2

CLOCK3

OE/PDM

VDDL

VCX/WP

CY27EE16Z

Document #: 38-07440 Rev. *B Page 2 of 17

Functional Description

The CY27EE16ZE integrates a 16-kbit EEPROM scratchpad

and a clock generator that features Cypress’s programmable

clock core. An industry standard I2C serial programming

interface (SPI) is used to program the scratchpad and clock

core.

16-kbit EEPROM

The 16-kbit EEPROM scratchpad is organized in eight blocks

x 256 words x 8 bits. Each of the eight 2-kbit EEPROM

scratchpad blocks, a 2-kbit clock configuration EEPROM

block, and a 2-kbit volatile clock configuration SRAM block,

have their own 7-bit device address. The device address is

combined with a Read/Write bit as the LSB and is sent after

each start bi t.

Clock Features

The programmable clock core is configured with the following

features:

•Cryst al Osci llator: Programmabl e drive and load, suppo rt

for external references up to 166 MHz. See "Reference

Frequency (REF)", page 5

•VCXO: Analog or digital control

•Inputs and I/Os: Programmable input muxes drive write

protect (WP), analog VCXO control, output enable (OE),

and power down mode (PDM) functions

•PLL: Programmable P, Q, offset, and loop filter parameters.

Outputs: Six outputs and two programmable linear dividers.

The output swing of CLOCK1 through CLOCK4 is set by VDDL

(2.5V or 3.3V). The output swing of CLOCK5 and CLOCK6 is

set by VDD (3.3V).

Clock configuration is stored in a dedicated 2-kbit block of

nonvol atile EEPROM and a 2-kbit block of volatile SRAM . The

SPI is used to write new configuration data to the on-chip

programmable registers that are defined within the clock

configuration memory blocks. Other, custom configurations,

that include custom VCXO, Spread Spectrum for EMI

reduction, Fractional N and frequency select pins (FS) are

programmable; contact factory for details.

Write Protect (WP) – Active HIGH

The default clock configuration of the CY27EE16ZE has pin

17 configured as WP. When a logical HIGH level input is

asserted on this pin, the write protect feature (WP) will inhibit

writing to the EEPROM. This protects EEPROM bits from

being changed, while allowing full read access to EEPROM.

Wr iting to SRAM is allowed w ith WP enab led. When th is pin is

held at a logical LOW level, WP is disabled and data can be

written to EEPROM.

Analog Adjust for Voltage Controlled Crystal Oscillator

(VCXO)

Pin 17 can be programmed, with the SPI, to function as the

analog control for the VCXO. Then, pi n 17 provide s ± 150 ppm

adjustment of the crystal oscillator frequency (in order to use

the VCXO , the c ryst al mus t have a min imum of ± 1 50 ppm pull

range an d meet the pullable cryst al speci fications as shown in

Table 15 on page 12). The crystal oscillator fr equency is pulled

lower by at least 1 50 ppm whe n 0V is app lied to VC XO, pulled

higher by at le ast 150 ppm wh en VDD is ap plied to VC XO. The

oscillator frequency will have a linear dependence on the

volt ag e lev el appl ied to pin 17, VCXO , w ithin a ran ge fro m 0V

to VDD. See section "Device Addressing", page 10 for more

information.

Note:

1.Float XOUT if XIN is externally driven.

Table 1. Pin Description

Name Pin Number Description

XIN 1Reference crystal input

VDD 2, 19 3.3V voltage supply

CLOCK6 3Clock output 6

AVDD 43.3V analog voltage supply

SDAT 5Data input for serial programming

AVSS 6Analog ground

VSSL 7Output ground

CLOCK1 8Clock output 1

CLOCK2 9Clock output 2

OE/PDM 10 Output enable or power-down mode enable

VDDL 11,14 Output voltage supply

CLOCK3 12 Clock output 3

SCL 13 Clock signal input for serial programming

CLOCK4 15 Clock output 4

VSS 16 Ground

VCXO/WP 17 Analog control input for VCXO or write protect (user-configurable)

CLOCK5 18 Clock output 5

XOUT[1] 20 Reference crystal output

CY27EE16Z

Document #: 38-07440 Rev. *B Page 3 of 17

Output Enable (OE) – Active HIGH

The default clock co nfig ura t io n has pi n 10 prog ram me d as an

Output Enable (OE). This pin enables the divider bank clock

outputs when HIGH, and disables divider bank clock outputs

when LO W.

Power-down Mode (PDM) – Active LOW

The Power-down Mode (PDM) function is available when pin

10 of the C Y27EE16ZE is configur ed as PDM. When the PDM

signal pulled LOW, all clock components are shut down and

the part enters a low-power state. To configure pin 10 of the

CY27EE16ZE as PDM, see "Power-down Mode (PDM) and

Output Enable (OE) Registers for Pin 10", page 7.

Serial Programming Interface (SPI)

The SPI uses industry-standard signaling in both standard and

fast modes to program the 8 x 2 kbit EPPROM blocks of

scratchpad, the 2-kbit EEPROM dedicated to clock configu-

ration, and the 2-kbit SRAM block. See sections beginning

with "Using the Serial Programming Interface (SPI)", page 3

for more information.

Default Start-up Condit ion for CY27EE16ZE

The default (programmed) condition of the 8 x 256 bit

EEPRO M blocks (scratchpad) in the device as shipped from

the facto ry, are blank a nd un program med. In th is c ondition , a ll

bits are set to 0.

The def aul t cloc k con fig uration is:

•the cryst al o scillator c ircuit i s acti ve.

•CLOCK1 outputs REF frequency .

•All other outputs are three-stated.

•WP c ontrol on pin 17.

•OE control on pin 10.

This default clock configuration is typically customized to meet

the needs of a specific application. It provides a clock signal

upon power-on, to facilitate in-system programming. Alterna-

tively, the CY27EE16ZE may be programmed with a different

clock configuration prior to placement of the CY27EE16ZE in

systems. While you can develop your own subroutine to

program any or all of the individual registers described in the

following pages, it may be easier to use CyClocksRT™ to

produce the required register setting file.

Using the Serial Progr ammi ng Interface (SPI)

The CY27EE16ZE provides an industry-standard serial

programming interface for volatile and nonvolatile, in-system

programming of unique frequencies and options. Serial

programming and reprogramming allows for quick design

changes and product enhancements, eliminates inventory of

old design parts, and simplifies manufacturing.

The CY27EE16ZE is a group of ten slave devices with

addresses as shown in Figure 1. The serial programming

interface address of the CY27EE16ZE clock configuration

2-kbit EEPROM block is 69H. The serial programming

interface address of the CY27EE16ZE clock configuration

2-kb it SRAM block is 68 H. Shou ld th ere b e a co nfl ic t with an y

other devices in your syst em, all device addresses can also be

changed using CyberClocks. Registers in the clock configu-

ration 2-kbit SRAM memory block are written, when the user

wants to update the clock configu ration for on-the-fly changes.

Registers in the clock configuration EEPROM block are

written, if the user wants to update the clock configuration so

that it is saved and used again after power-up or reset.

All programmable registers in the CY27EE16ZE are

addressed with eight bits and contain eight bits of data. Table 2

list s the specif ic register def initions and their allowa ble values.

See section "Serial Programming Interface Timing", page 12,

for a detailed description.

1st

EE block

256 x 8 bits

Address:

1000000

4th

EE block

256 x 8 bits

Address:

1000011

3rd

EE block

256 x 8 bits

Address:

1000010

2nd

EE block

256 x 8 bits

Address:

1000001

clock config.

EE block

256 x 8 bits

Address:

1101000

clock config.

SRAM

256 x 8 bits

Address:

1101001

5th

EE block

256 x 8 bits

Address:

1000100

8th

EE block

256 x 8 bits

Address:

1000111

7th

EE block

256 x 8 bits

Address:

1000110

6th

EE block

256 x 8 bits

Address:

1000101

Figure 1. Device Addresses for EEPROM Scratchpad and Clock Configuration Blocks

CY27EE16Z

Document #: 38-07440 Rev. *B Page 4 of 17

CY27EE16ZE Frequency Calculati on and

The CY27EE16ZE is an extremely flexible clock generator

with four basic variables that can be used to determine the final

output frequency. They are the input reference frequency

(REF ), the interna lly calc ulated P and Q divide rs, and the po st

divider, which can be a fixed or calculated value. There are

three ba sic formulas for determini ng the final outp ut frequency

of a CY27EE16ZE-based design. Any one of these three

formulas may be used:

CLK = ((REF * P)/Q)/Post Divider

CLK = REF/Post Divider

CLK = REF

The basic PLL block diagram is shown in Figure 2. Each o f the

six clock outputs on the CY27EE16ZE has a total of seven

output o ptions available to it. There are six post divider opt ions

availa ble : /2 (two of thes e), /3, /4, /DIV1N and /DIV2 N. DIV1N

and DIV2N are independently calculated and are applied to

individual output groups. The post divider options can be

applie d to the c alculated V CO frequency ((REF*P)/Q) o r to the

reference frequency directly.

In addition to the six post divider output options, the seventh

option by pas ses the PLL and p asses the referenc e frequency

directly to the crosspoint switch matrix.

Table 2. Summary Table – CY27EE16ZE Programmable Registers

RegisterDescription D7D6D5D4D3D2D1D0

09H CLKOE control 0 CLOCK6 CLOCK5 0 CLOCK4 CLOCK3 CLOCK2 CLOCK1

OCH DIV1SRC mux and

DIV1N divider DIV1SRC DIV1N(6) DIV1N(5) DIV1N(4) DIV1N(3) DIV1N(2) DIV1N(1) DIV1N(0)

10H Input Pin Control

Registers OESrc OE0PadS

el[1] OE0PadS

el[0] OE1PadS

el[1] OE1PadS

el[0] PDMEna-

ble PDMPad-

Sel[1] PDMPad-

Sel[0]

11H Write Prote ct

Registers MemWP WPSrc WPPad-

Sel[2] WPPad-

Sel[1] WPPad-

Sel[0]

12H Input crystal oscillator

drive contro l FTAAd-

drSrc(1)

default=0

FTAAd-

drSrc(0)

default=0

XCapSrc

default=1 XDRV(1) XDRV(0) 0 0 0

13H Input load capacitor

control Cap-

Load(7) Cap-

Load(6) Cap-

Load(5) Cap-

Load(4) Cap-

Load(3) Cap-

Load(2) Cap-

Load(1) Cap-

Load(0)

14H ADC Register ADCEn-

able AD-

CBypCnt ADC-

Cnt[2] ADC-

Cnt[1] ADC-

Cnt[0] ADCFilt[1] ADCFilt[0] 0

40H Charge Pump and PB

counter 1 1 0 Pump(2) Pump(1) Pump(0) PB(9) PB(8)

41H PB(7) PB(6) PB(5) PB(4) PB(3) PB(2) PB(1) PB(0)

42H PO counter, Q

counter PO Q(6) Q(5) Q(4) Q(3) Q(2) Q(1) Q(0)

44H Crosspoint switch

matrix control CLKSRC2

for

CLOCK1

CLKSRC1

for

CLOCK1

CLKSRC0

for

CLOCK1

CLKSRC2

for

CLOCK2

CLKSRC1

for

CLOCK2

CLKSRC0

for

CLOCK2

CLKSRC2

for

CLOCK3

CLKSRC1

for

CLOCK3

45H CLKSRC0

for

CLOCK3

CLKSRC2

for

CLOCK4

CLKSRC1

for

CLOCK4

CLKSRC0

for

CLOCK4

1 1 1 CLKSRC2

for

CLOCK5

46H CLKSRC1

for

CLOCK5

CLKSRC0

for

CLOCK5

CLKSRC2

for

CLOCK6

CLKSRC1

for

CLOCK6

CLKSRC0

for

CLOCK6

111

47H DIV2SRC mux and

DIV2N divider DIV2SRC DIV2N(6) DIV2N(5) DIV2N(4) DIV2N(3) DIV2N(2) DIV2N(1) DIV2N(0)

CY27EE16Z

Document #: 38-07440 Rev. *B Page 5 of 17

Reference Frequency (REF)

The reference frequency can be a crystal or a driven

frequ ency . For cry stals, the frequ ency range must be betwe en

8 MHz and 30 MHz. For a driven frequency, the frequency

range must be between 1 MHz and 167 MHz (Commercial

Temp.) or 150 MHz (Industrial Temp.).

Using a Crystal as the Reference Input

The input crystal oscillator of the CY27EE16ZE is an important

feature because of the flexibility it allows the user in selecting

a crys t al as a re ferenc e freque ncy s ource . Th e inpu t osci llator

has programmable gain, allowing for maximum compatibility

with a reference crystal, regardless of manufacturer, process,

performance and quality.

Programmable Crystal Input Oscillator Gain Settings

The Input crystal oscillator gain (XDRV) is controlled by two

bits in register 12H, and are set according to Table 3. The

parameters controlling the gain are the crystal frequency, the

internal crystal parasitic resistance (ESR, available from the

manufacturer), and the CapLoad setting during crystal

start-up.

Bits 3 and 4 of register 12H control the input crystal oscillator

gain setting. Bit 4 is the MSB of the setting, and bit 3 is the

LSB. The setting is programmed according to Table 3.

All other bits in the register are reserved and should be

progr ammed LOW. See Table 4 for bit locations and values.

(Q+2) VCO

(2(PB+4)+PO)

CLOCK1

CLOCK2

CLOCK3

CLOCK4

CLOCK5

CLOCK6

CLKSRC

Crosspoint

Switch Matrix

[44H]

[44H,45H]

[45H]

[46H]

DIV2CLK

REF PFD

Divider Bank 1

[45H,46h]

DIV1SRC [OCH]

DIV2SRC [47H]

Divider Bank 2

DIV1N [OCH]

DIV2N [47H]

DIV1CLK

/DIV1N

[42H]

[40H], [41H], [42H]

/DIV2N

Qtotal

Ptotal

CLKOE [09H] Figure 2. Basic Block Diagram of CY27EE16ZE PLL

Table 3. Programmable Crystal Input Oscillator Gain Settings

Calculated CapLoad Value 00H – 20H 20H – 30H 30H – 40H

Crystal ESR 30Ω60Ω30Ω60Ω30Ω60Ω

Crystal Input

Frequency 8 – 15 MHz 000101100110

15 – 20 MHz 011001101010

20 – 25 MHz 01 10 10 10 10 11

25 – 30 MHz 10 10 10 11 11 N/A

Table 4. Register Map for Input Crystal Oscillator Gain Setting

Address D7 D6 D5 D4 D3 D2 D1 D0

12H FTAAddrSrc(1)

default=0 FTAAddrSrc(0)

default=0 XCapSrc

default=1 XDRV(1) XDRV(0) 0 0 0

CY27EE16Z

Document #: 38-07440 Rev. *B Page 6 of 17

Using an External Clock as th e Reference Input

The CY27EE16ZE can also accept an external clock as

reference, with speeds up to 167 MHz (or 150 MHz at Indus-

trial Temp.). With an external clock, the XDRV (register 12H)

bits must be set according to Table 5.

Input Load Cap a cito rs

Input load capacitors allow the user to set the load capacitance

of the C Y27EE16 ZE to mat ch the input l oad ca pacitance fro m

a crys t al . The value of th e i npu t lo ad c apacitor s is de term in ed

by 8 bits in a programmable register [13H]. The proper

CapLoad register setting is determined by the formula:

CapLoad = (CL– CBRD – CCHIP)/0.09375 pF

where:

•C

L = specified load capacitance of your crystal.

•C

BRD = the total board capacitance, due to external capac-

itors and board trace capacitance. In CyClocksRT , this value

defaults to 2 pF.

•C

CHIP = 6 pF.

• 0.09375 pF = the s tep resoluti on a vai la ble due to the 8- bit

In Cyc lock sRT, o nly th e crysta l capaci tance (C L) is specified.

CCHIP is set to 6 pF, and CBRD defaults to 2 pF. If your board

capacitance is higher or lower than 2 pF, the formula above

can be used to calculate a new CapLoad value and

programmed into register 13H.

In CyClo cksRT, enter t he cry stal ca pacita nce (CL). The value

of CapLoad will be determined a utomatically and programmed

into the CY27EE16ZE. Through the SDA T a nd SCLK pins, the

value ca n be adjusted up or down if your boa rd cap acita nce is

greater or less than 2 pF. For an external clock source,

CapLoad defaults to 1. See Table 6 for CapLoad bit locations

and v alues.

The inp ut load cap acit ors are pl aced o n the CY 27EE16ZE d ie

to reduc e extern al com ponen t cost. These cap aci tors are true

parallel-plate capacitors, designed to reduce the frequency

shift that occurs when non-linear load capacitance is affected

by load, bias, supply and temperature changes

DCXO/VCXO

The default clock configuration of the CY27EE16ZE has 256

stored values that are used to adjust the frequency of the

crystal oscillator , by changing the load capacitance. In order to

use these stored values, the clock configuration must be

reprogrammed to enable the DCXO or VCXO feature.

To Configure for DCXO Operation

1. FTAAddrScr[1:0], Register 12H[7:6] = 00 (default configu-

ration = 00)

2. XCapSrc, Register 12H[5] = 0

3. XDRV[1:0], Regis ter 12H[4 :3] = (see Table 3)

4. ADCEnable, Register 14H[7] = 0

5. ADCBypCnt, Register 14H[6] = 0

6. ADCCnt[2:0], Register 14H[5:3] = 000

7. ADCFilt[1:0], Register 14H[2:1] = 00

Once the clock configuration block is programmed for DCXO

operation, the SPI may be used to dynamically change the

capacitor load value on the crystal. A change in crystal load

capacitance corresponds with a change in the reference

frequency. Thus, the crystal oscillator frequency can be

adjusted from –150 ppm of the nominal frequency value to

+150 ppm of the nominal frequ ency value. “Nominal frequency

– 150 p pm” is a chieved by writ ing 0000 0000 into the CapLo ad

writing 11111111 into the CapLoad register

Configure for VCXO Operation

To configure the VCXO for analog control clock configuration

registers must be written to as follows:

1. FTAAddrSrc[1:0], Register 12H[7:6] = 01

2. XCapSrc, Register 12H[5] = 0

3. XDRV[1:0], Regis ter 12H[4 :3] = (see Table 3)

4. ADCEnable, Register 14H[7] = 1

5. ADCBypCnt, Register 14H[6] = 0

6. ADCCnt[2:0], = 001

7. ADCFilt[1:0], Register 14H[2:1]= 10

8. WPSrc, Register 11H[3] = 1

Table 5. Programmable External Reference Input Oscillator Drive Settings

Reference Frequency 1 – 25 MHz 25 – 50 MHz 50 – 90 MHz 90 – 167 MHz

Drive Setting 00 01 10 11

Table 6. Input Load Cap a citor Register Bit Setting

AddressD7D6D5D4D3D2D1D0

13H CapLoad(7) CapLoad(6) CapLoad(5) CapLoad(4) CapLoad(3) CapLoad(2) CapLoad(1) CapLoad(0)

CY27EE16Z

Document #: 38-07440 Rev. *B Page 7 of 17

Power-down Mode (PDM) and Output Enable

(OE) Registers for Pin 10

In the default clock configuration, pin 10 is configured as OE,

and not configured as PDM. As such, the Power-down mode

is not available unless the clock core is modified.

To Configure for PDM

To configur e pin 10 fo r PDM, use the SPI to write the following:

1. PDMEnable, Register 10H[2] = 1

2. PDMPad Sel [1:0 ], Reg ister 10H [1 :0] =10

3. OESrc, Register 10H[7] = 1 (to redirect control of output

enable to memory, register 40H[7:6], and thereby enable

both divider banks).

Now , when the PDM signal (an active LOW signal) is asserted,

all of the c lock componen t s are shut dow n and th e pa rt enter s

a low-pow er state.

The serial port and EE blocks will still be available. These

circuits automatically go into a low-power stat e when not being

used , but will draw power when a c tive.

Note: For default factory programmed devices, Register

40H[7:6] may be programmed to 00. In this case Register

40H[7 :6] must be programmed to 11 in order for clock output s

to be enabled.

To Configure for OE

To reconfigure pin 10 as OE again, so that pin 10 controls

enable /di sab le of the out put di vid er b an k, use th e SPI to write

the foll owin g:

1. OESrc, Register 10H[7] = 0

2. OE0PadSel[1:0], Register 10H[6:5] =10

3. OE1PadSel[1:0], Register 10H[4:3] =10

4. PDMEnable, Register 10H[2] = 0

5. Mem WP, Register 11H[4] = 0

6. WPSrc, Register 11H[3] = 1

W rite Protect (WP) Registers

To reconf igure p in 17 as W P, to control enab le/dis able of wri te

protection, use the SPI to write the following:

WPSrc, Register 11H[3] = 0

WPPadSel[2:0], Regist er 11H[2:0] = 100

When active (WP = 1), WP prevents the control logic for the

EE from initiating a erase/program cycle for any of the

EEPROM blocks (16-Kbit scratchpad and clock configuration

block). All serial shift ing works as normal.

PLL Frequency, Q Counter

The first counter is known as the Q counter. The Q counter

divides REF by its calculated value. Q is a 7 bit divider with a

maximum value of 127 and minimum value of 0. The primary

value of Q is determined by 7 bits in register 42H (6..0), but 2

is added to this register value to achieve the total Q, or Qtotal.

Qtotal is defined by the formula:

Qtotal = Q + 2.

The minimum value of Qtotal is 2. Th e maxi mum val ue of Q total

is 12 9. Register 42H is defined in Table 7.

Stable opera tion o f the CY27 EE16Z E cannot be g uarante ed if

REF/Qtotal falls below 250 kHz. Qtotal bit locations and values

are defined in Table 7.

PLL Frequency, P Counter

The next counter definition is the P (product) counter. The P

counte r is multipl ied with the (REF/Q total) value to achieve the

VCO frequency. The product counter, defined as Ptotal, is

made up of two in ternal variables, PB and PO . The formula for

calculat ing Ptotal is:

Ptotal = (2(PB + 4) + PO)

PB is a 10-bit variable, defined by registers 40H(1:0) and

41H(7:0). The 2 LSBs of register 40H are the two MSBs of

variable PB. Bits 4..2 of register 40H are used to determine the

charge pump settings (see section, "Charge Pump Settings

[40H(2..0)]", page 8”). The 3 MSBs of register 40H are preset

and reserved and cannot be changed.

PO is a single bit variable, defined in register 42H(7). This

allows for odd numbers in Ptotal.

The remai nin g 7 bits of 42H are us ed to defi ne the Q counter,

as shown in Table 7.

The mi nimu m value of Ptotal is 8. The maximum value of Ptotal

is 2055. To achieve the minimum value of Ptotal, PB and PO

should both be programmed to 0. To achieve the maximum

value of Ptotal, PB should be programmed to 1023, and PO

should be programmed to 1.

Stable opera tion o f the CY27 EE16Z E cannot be g uarante ed if

the value of (Ptotal*(REF/Qtotal)) is above 400 MHz or below

100 MHz. Registers 40H, 41H and 42H are defined in Table 8.

Table 7. Q Counter Register Definition

42H PO Q(6) Q(5) Q(4) Q(3) Q(2) Q(1) Q(0)

Table 8. P Counter Register Definition

Address D7 D6 D5 D4 D3 D2 D1 D0

40H 1 1 0 Pump(2) Pump(1) Pump(0) PB(9) PB(8)

41H PB(7) PB(6) PB(5) PB(4) PB(3) PB(2) PB(1) PB(0)

42H PO Q(6) Q(5) Q(4) Q(3) Q(2) Q(1) Q(0)

CY27EE16Z

Document #: 38-07440 Rev. *B Page 8 of 17

PLL Post Divider Options

The output of the VCO is routed through two independent

muxes, then to two divider banks to determine the final clock

output frequency. The mux determines if the clock signal

feeding into the divider banks is th e calculated VCO frequ ency

or REF. There are 2 selec t muxes ( DIV1SRC and DIV2 SRC)

and 2 divider banks (Divider Bank 1 and Divider Bank 2) used

to determine this clock signal. The clock signals passing

through DIV1SRC and DIV2SRC are referred to as DIV1CLK

and DIV2CLK, re spectively.

The divider banks hav e 4 unique divid er opt ion s av ail abl e: /2,

/3, /4, and /DIVxN. DIVxN is a variable that can be indepen-

dently programmed (DIV1N and DIV2N) for each of the 2

divider banks. The minimum value of DIVxN is 4. The

maximum value of DIVxN is 127. A value of DIVxN below 4 is

not guarant eed to work properly.

DIV1SRC is a single bit variable, controlled by register OCH.

The remaining 7 bits of register OCH determine the value of

post divider DIV1N.

DIV2SRC is a single bit variable, controlled by register 47H.

The remaining 7 bits of register 47H determine the value of

post divider DIV2N.

Regis te r OCH and 47H are define d in Table 9.

Charge Pump Settings [40H(2..0)]

The corre ct pump se tting is imp ortant fo r PLL stab ility. Charge

pump s ettings are cont rolled by bi ts (4..2) of register 40H , and

are dependent on internal variable PB (see section "[00H to

08H] – Reserved [0AH to 0BH] – Reserved [0DH to 0FH]

–Res erv ed [15 H to 3FH] –Reserve d [43H] –R e se rve d [48H to

FFH] –Reserved", page 9). Table 10 summarizes the proper

charge pump settings, based on Ptotal. See Table 11, "Register

40H Change Pump Bit Settings", page 8, for register 40H bit

locations.

Although using Table 11 will guarantee stability, it is recom-

mended to use the Print Previ ew function in CyberClocks ™ to

determine the ideal charge pump settings for optimal jitter

performance.

PLL stability cannot be guaranteed for Ptotal valu es bel ow 16

and above 1023. If Ptotal values above 1023 are needed, use

CyberClocks to determine the best charge pump setting.

Table 9. PLL Post Divider Options

AddressD7D6D5D4D3D2D1D0

OCH DIV1SRC DIV1N(6) DIV1N(5) DIV1N(4) DIV1N(3) DIV1N(2) DIV1N(1) DIV1N(0)

47H DIV2SRC DIV2N(6) DIV2N(5) DIV2N(4) DIV2N(3) DIV2N(2) DIV2N(1) DIV2N(0)

Table 10. Charge Pump Settings

Charge Pump Se tting

– Pump(2..0) Calculated Ptotal

000 16 – 44

001 45 – 479

010 480 – 639

011 640 – 799

100 800 – 1023

101, 1 10, 1 11 Do Not Use – devic e will be unst able

Table 11. Register 40H Change Pump Bit Settings

AddressD7D6D5D4D3D2D1D0

40H 1 1 0 Pump(2) Pump(1) Pump(0) PB(9) PB(8)

CY27EE16Z

Document #: 38-07440 Rev. *B Page 9 of 17

Clock Output Settings

CLKSRC - Clock Output Crosspoint Switch Matrix

[44H(7..0)], [45H(7..0)], [46H(7..0)]

Every cl oc k ou tput can be de fin ed to com e fro m on e of s ev en

unique frequency sources. The CLKSRC(2..0) crosspoint

switch matrix defines which source is attached to each

indivi dual cl ock output. CLK SRC(2..0 ) is set in Re gister s 44H,

45H, and 46H. The remainder of registers 45H(3:1) and

46H(2 :0) m us t be wr itt en with the val ues s t ated in the re gis ter

table when writing register values 45H(7:4), 45H(0), and

46H(7:3).

When DIV1N is divisible by 4, then CLKSRC(0,1,0) is

guaranteed to be rising edge phase-aligned with

CLKSRC(0,0,1). When DIV1N is 6, then CLKSRC(0,1,1) is

guaranteed to be rising edge phase-aligned with

CLKSRC(0,0,1).

When DIV2N is divisible by 4, then CLKSRC(1,0,1) is

guaranteed to be rising edge phase-aligned with

CLKSRC(1,0,0). When DIV2N is divisible by 8, then

CLKSRC(1,1,0) is guaranteed to be rising edge phase-aligned

with CLKSRC(1,0,0).

CLKOE - Clock Output Enable Control [09H(7..0)]

Each clock output has its own output enable, CLKOE,

controlled by register 09H(7..0). To enable an output, set the

corresponding CLKOE bit to 1. CLKOE settings are in

Table 14.

Test, Reserved, and Blank Registers

Writing to any of the following registers will cause the part to

exhibit abnormal behavior:

[00H to 08H] – Reserved

[0AH to 0BH] – Reserved

[0DH to 0FH] –Res erv ed

[15H to 3FH] –Reserved

[43H] –Res erv ed

[48H to FFH] –Reserved

Table 12. Clock Output Settings – Clock Source CLKSRC[2:0]

CLKSRC2 CLKSRC1 CLKSRC0 Definition and Notes

0 0 0 Reference Input

0 0 1 DIV1CLK/DIV1N. DIV1N is defined by register [OCH]. Allowable values for DIV1N are

4 to 127. If Divider Bank 1 is not being used, set DIV1N to 8

0 1 0 DIV1CLK/2. Fixed /2 divider option. If this option is used, DIV1N must be divisible by 4.

0 1 1 DIV1CLK/3. Fixed /3 divider option. If this option is used, set DIV1N to 6.

1 0 0 DIV2CLK/DIV2N. DIV2N is defined by Register [47H]. Allowable values for DIV2N are

4 to 127. If Divider Bank 2 is not being used, set DIV2N to 8.

1 0 1 DIV2CLK/2. Fixed /2 divider option. If this option is used, DIV2N must be divisible by 4.

1 1 0 DIV2CLK/4. Fixed /4 divider option. If this option is used, DIV2N must be divisible by 8.

1 1 1 Reserved – Do not use

Table 13. CLKSRC Registers

Address D7 D6 D5 D4 D3 D2 D1 D0

44H CLKSRC2

for CLOCK1 CLKSRC1

for CLOCK1 CLKSRC0

for CLOCK1 CLKSRC2

for CLOCK2 CLKSRC1

for CLOCK2 CLKSRC0

for CLOCK2 CLKSRC2

for CLOCK3 CLKSRC1

for CLOCK3

45H CLKSRC0

for CLOCK3 CLKSRC2

for CLOCK4 CLKSRC1

for CLOCK4 CLKSRC0

for CLOCK4 1 1 1 CLKSRC2

for CLOCK5

46H CLKSRC1

for CLOCK5 CLKSRC0

for CLOCK5 CLKSRC2

for CLOCK6 CLKSRC1

for CLOCK6 CLKSRC0

for CLOCK6 111

Table 14. CLKOE Bit Setting

Address D7 D6 D5 D4 D3 D2 D1

09H 0 CLKOE for

CLOCK6 CLKOE for

CLOCK5 0 CLKOE for

CLOCK4 CLKOE for

CLOCK3 CLKOE for

CLOCK2 CLKOE for

CLOCK1

CY27EE16Z

Document #: 38-07440 Rev. *B Page 10 of 17

Serial Programming Interface (SPI) Prot ocol

and Timing

The CY27EE16ZE utilizes a 2-serial-wire interface SDAT and

SCLK that operates up to 400 kbits/sec in Read or W rite mode.

The basic Write serial format is as follows:

Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock

Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit

Data; A CK; 8-bi t Data in MA+1 if de sired; ACK; 8-b it Data i n

MA+2; ACK; etc. until STOP Bit. The basic serial format is

illustrated in Figure 4.

Data Valid

Data is vali d when the clock is HIGH, and may only be transi-

tioned when the clock is LOW as illustrated in Figure 5.

Data Frame

Every new data frame is indicated by a start and stop

sequence, as illustrated in Figure 6.

Start Sequence – Start Frame is indicated by SDAT going

LOW when SCLK is HIGH. Every time a start signal is given,

the next 8-bit data must be the device address (7 bits) and a

R/W bit, foll owed by regis ter address (8 b its) and regis ter data

(8 bits).

Stop Sequence – Stop Frame is indicated by SDAT going

HIGH when SCLK is HIGH. A Stop Frame frees the bus for

writing to another part on the same bus or writing to another

random register address.

Acknowledge Pulse

During Write Mode the CY27EE16ZE will respond with an

Acknow ledge pulse af ter every 8 bit s. This is ac complis hed by

pulling the SDAT line LOW during the N*9th clock cycle as

illust rated in Figure 7. (N = the number of bytes transmitted).

During Read Mode the acknowledge pulse after the data

packet is sent is generated by the master.

Device Addressing

The first four bits of the device address word for the eight

EEPROM scratchpad blocks are 1000. The 5th, 6th, and 7th

bits are the ad dress bits (A2, A1, A0 resp ectively) for the slices

of 2K EEPROM. The first seven bits of the device address

word for t he cl ock c on fig urati on EEPROM blo ck ar e 11010 00.

The first seven bits of the device address word for the clock

configuration SRAM block are 1101001. The final bit of the

address specifies the operation (HIGH/1 = Read, LOW/0 =

Write)

W rite Operations

Writing Individual Bytes

A valid write operation must have a full 8-bit word address after

the device address word, which is followed by an acknowl-

edgment b it from the EEPROM (ac k = 0/LOW). The next 8 bits

must con tain the dat a word intended for storage. After the data

word is received, the EEPROM responds with another

acknowledge bit (ack = 0/LOW), and the device that is

address in g the EEPROM m ust end the wri te s equ enc e wi th a

stop condition. The EEPROM now enters an internal write

process transferring the data received to nonvolatile memory.

During , and until compl etion of, thi s internal writ e proc ess, t he

EEPROM will not respond to other commands.

Writing Multiple Bytes

The CY27EE16ZE is capable of receiving up to 16 consec-

utive written bytes. In order to write more than one byte at a

time, the device addressing the EEPROM does not end the

write sequence with a stop condition. Instead, the device can

send up to fifteen more bytes of data to be stored. After each

byte, the EEPROM responds with an acknowledge bit, just like

after the first byte. The EEPROM will accept data until the

acknowledge bit is responded to by the stop condition, at

which time it enters the internal write process as described in

the section above. When receiving multiple bytes, the

CY27EE16ZE internally increments the address of the last 4

bits i n t he address w ord. Afte r 1 6 b yt es are w rit ten, th at incre-

menting brings it back to the first word that was written. If more

than 16 bytes are written, the CY27EE16ZE will overwrite the

first bytes written.

Read Operations

Read operations are initiated the same way as Write opera-

tions except that the R/W bit of the slave address is set to ‘1’

(HIGH). There are three basic read operations: current

address read, random read, and sequential read.

Current Address Read

The CY27EE16ZE has an onboard address counter that

retai ns 1 m ore than the add ress o f the las t wor d access . If the

last word written or read was word ‘n,’ then a current address

read opera t io n woul d retu rn the val ue stored in location ‘n+1’.

When the CY27EE16ZE receives the slave address with the

R/W bit set to a ‘1,’ the CY27EE16ZE issues an acknowledge

and transmits the 8-bit word. The master device does not

acknowledge the transfer, but does generate a STOP

condition, which causes the CY27EE16ZE to stop trans-

mission.

Random Read

Through random read operat ions, the mas ter may ac cess any

memory location. To perform this type of read operation, first

the word address must be set. This is accomplished by

sending the address to the CY27EE16ZE as part of a write

operation. After the word address is sent, the master

generate s a START condition f ollowing the a cknowledge. This

termina tes the w rite op eration be fore any da t a i s sto red in the

address, but not before the internal address pointer is set.

Next the master reissues the control byte with the R/W byte

set to ‘1.’ Th e CY2 7EE16ZE t hen is sues an ac knowl edge a nd

transmits the 8-bit word. The master device does not

acknowledge the transfer, but does generate a STOP

condition which causes the CY27EE16ZE to stop trans-

mission.

CY27EE16Z

Document #: 38-07440 Rev. *B Page 11 of 17

Sequential Read

Sequential read operations follow the same process as

random reads except that the master issues an acknowledge

instea d of a STOP condi tion after transmissio n of the first 8-bit

data word. This action results in an incrementing of the internal

address pointer , and su bsequently ou tput of the next 8-bit data

word. By continuing to issue acknowledges instead of STOP

condit ion s, the ma ster ma y serial ly read the en tire con tent s of

the 16-kbit EEPROM scratchpad memory. When the internal

address pointer points to the FFH word of a EEPROM block,

after the nex t increm ent, the po inter will po int to the 00H w ord

of the next block. After incrementing to the FFH word of the

eighth block, the next increment will point the pointer to the

00H word of the 1st EEPROM block. Similarly, sequential

reads within either the EEPROM or SRAM c lock c onfigu ration

blocks will wrap within the block to the first word of the same

block after reaching the end of either block.

SCL

START

Condition

SDAT

STOP

Data may Address or

Acknowledge

Valid be changed Condition

Figure 3. Data Transfer Sequence on the Serial Bus

SDAT Write

Start Signal

Device

Address

7-bit

R/W = 0

1 Bit

8-bit

Address

Slave

1 Bit

ACK Slave

1 Bit

ACK

8-bit

Data

Stop Sign al

Multiple

Contiguous

Registers

Slave

1 Bit

ACK

8-bit

Data

(XXH) (XXH) (XXH+1)

Slave

1 Bit

ACK

8-bit

Data

(XXH+2)

Slave

1 Bit

ACK

8-bit

Data

(XXH)

Slave

1 Bit

ACK

8-bit

Data

(X0H)

Slave

1 Bit

ACK Slave

1 Bit

ACK

SDAT Read

Start Signal

Device

Address

7-bit

R/W = 1

1 Bit

8-bit

Data

Slave

1 Bit

ACK Slave

1 Bit

ACK

Stop Signal

SDAT Read

Start Signal

Device

Address

7-bit

R/W = 0

1 Bit

8-bit

Address

Slave

1 Bit

ACK Slave

1 Bit

ACK

7-bit

Device

Stop Signal

Multiple

Contiguous

Registers

Master

1 Bit

ACK

8-bit

Data

Master

1 Bit

ACK

(XXH) (XXH)

Master

1 Bit

ACK

8-bit

Data

(XXH+1)

Master

1 Bit

ACK

8-bit

Data

(8FFH)

Master

1 Bit

ACK

8-bit

Data

(000H)

Master

1 Bit

ACK Master

1 Bit

ACK

Current

Address

Read

16 byte wrap

Address

+R/W=1

Repeated

Start bit

Figure 4. Data Frame Architecture

CY27EE16Z

Document #: 38-07440 Rev. *B Page 12 of 17

Serial Programming Interface Timing

Thermal Land Pad on PWB: Layout

Requirement for 20-lead Exposed Pad TSSOP

In order to achieve power dissipation and maintain junction

temperature within specified limits there must be an exposed

landing pad placed under the package, and the exposed pad

on t he bott om of t he p acka ge mu st be solder ed t o this landi ng

pad. This is typically achieved by placing a dense array of

thermal via that conn ects th e landing pa d to the ground plane.

In order to meet the power dissipation specification of 40 °C/W ,

Amkor soldered the exposed pad to a thermal land pad, and

place d t he rma l via on a 1 .2- mm pi tch (x an d y ) in t h e the r ma l

land pad. For more information about this package, see,

“Application Notes for Surface Mount Assembly of Amkor’s

Thermally/Electrically Enhanced Leadframe Based

Packages.” Amkor Technology, December 2001.

SDAT

SCLK

Data Valid

Transition

to next Bit

CLKLOW

CLKHIGH

VIH

VIL

tSU

tDH

Figure 5. Dat a Valid and Data Transition Periods

Figure 6. Start and Stop Frame

Figure 7. Frame Format (Device Address, R/W, Register Address, Register Data)

SDAT

SCLK

START Transition

to next Bit STOP

SDAT

SCLK

DA6 DA5 DA0 R/W ACK RA7 RA6 RA1 RA0 ACK STOP

START ACK D7 D6 D1 D0

+++

Table 15. Pullable Crystal Specifications

Parameter Description Min. Typ. Max. Unit

CRYSTALLoad Load Capacitance 14 pF

C0/C1 240

ESR 35 W

ToOperating Temperature (Commercial) 0 70 °C

ToOperating Temperature (Industrial) –40 85 °C

Accinit Initial Accuracy ±30 ppm

Stability Temperature plus Aging Stability ±80 ppm

CY27EE16Z

Document #: 38-07440 Rev. *B Page 13 of 17

Absolute Maximum Conditions

Recommended Operating Condit ions

DC Electrical Specifications

DC Electrical Specifications – 2.5V Outputs

Parameter Description Min. Max. Unit

VDD Supply Voltage –0.5 7.0 V

TSStorage Te mpe ratu re –65 125 °C

TJJunction Temperature –40 100 °C

Logic Inputs VSS – 0.5 VDD + 0.5 V

I2C interface (SDAT and SCL) –0.5 5.5 V

Digital Outputs referred to VDD VSS – 0. 5 VDD + 0.5 V

Electr o-Static D isc ha rge 2000 V

VCXO Analog Input –0.5 VDD + 0.5 V

Endurance (@ 25 °C) 1,000,000 (100k/page) writes

Data retention 10 yrs

Parameter Description Min. Typ. Max. Unit

VDD Operating Voltage 3.135 3.3 3.465 V

VDDL Operating Voltage 2.375 2.5, 3.3 3.465 V

TAAmbient Temperature, Indu st rial grade –40 85 °C

TAAmbient Temperature, Comm erc ia l grade 0 70 °C

CLOAD Max. Load Capacitance 15 pF

tPU Power-up time for all VDD’s to reach minimum specified voltage

(power ramps must be monotonic) 0.05 500 ms

Parameter Name Description Min. Typ. Max. Unit

IOH Output High Current[2] VOH = VDD – 0.5, VDD = 3.3V 12 24 mA

IOL Output Low Current[2] VOL = 0.5, VDD = 3.3V 12 24 mA

VIH Input High Voltage CMOS levels 0.7 * VDD V

VIL Input Low Voltage CMOS levels 0.3 * VDD V

CIN Input Capacitance[2, 3] 7pF

IIZ Input Leakage Current Except XTAL pins 10 µA

f∆XO VCXO Pullability Range[2] +150 ppm

VVCXO VCXO Input Range[2] 0V

DD V

fVBW VCXO Input Bandwidth[2] DC 200 kHz

IVDD Supply Current 45 mA

ISB Supply Current - Power

Down Mode Enabled Current drawn while part is in

standby. 540 µA

Parameter Name Description Min. Typ. Max. Unit

IOH2.5 Output High Current[2, 4] VOH = VDD – 0.5, VDD = 3.3 V, VDDL = 2.5V 12 24 mA

IOL2.5 Output Low Current[2, 4] VOL = 0.5, VDD = 3.3 V, V DDL=2.5V 12 24 mA

Notes:

2.Guarant eed by desig n, not 100 % tested.

3.Crystal must meet Table 15 specifications.

4.VDD is only specified and characterized at 3.3V + 5%. VDDL may be powered at any value between 3.465 and 2.375.

CY27EE16Z

Document #: 38-07440 Rev. *B Page 14 of 17

AC Electrical Specifications (VDD = 3.3V)

Parameter[5] Name Description Min. Typ. Max. Unit

DC Clock Output Duty Cycle fOUT < 150 MHz

fOUT > 150 MHz, or fOUT = fREF

See Figure 8

40 50

50 55

60 %

ERORising Edge Rate Output Clock Edge Rate, Measured from 20%

to 80% of VDD, CLOAD = 15 pF See Figure 9.0.8 1.4 V/ns

EFOFalling Edge Rate Output Clock Edge Rate, Measured from 80%

to 20% of VDD, CLOAD = 15 pF See Figure 9.0.8 1.4 V/ns

t5Output to Output Skew For related clock outputs 250 ps

t9Clock Jitter Maximum absolute jitter (EEPROM quiet)

(during EEPROM reads)

(during EEPROM writes)

250

300

350

t10 PLL Lock Time 60 ms

tVDDramp Power Supply Ramp Ramp time from 1.5V to 2.5V[6] 15 ms

tVDDpowerdown Power Supply Power

Down after Write W ait time after a write to EEPROM is initiate d

by the stop bit until VDD fails below 2.5V 20 ms

Memory Section Specifications

FSCL SCL input frequency 400 kHz

tL Clock Pulse Low CLKLOW, 20–80% of VDD 1.2 µs

tHClock Pulse High CLKHIGH, 80–20% of VDD 0.6 µs

tSP Noise Suppress ion Time Square nois e spike on i nput 50 n s

tAA Clock Low to Data Out

Valid 0.1 0.9 µs

tBUFF T i me the bu s mus t be f ree

before a new transmission

may start

1.2 µs

tHDSTART Start Hold Time 0.6 µs

tSUSTART Start Set-up Time 0.6 µs

tDH Data in Hold Time 0 ms

tSU Data in Set-up time 100 ns

tRI Inputs rise time 300 ns

tFI Inputs fall time 300 ns

tSUSTOP Stop Set-up Time 0.6 µs

tDH Data Out Hold Time 50 ns

tWR Write Cycle Time 20 ms

Test and Measurement Set-up

Notes:

5.Not 100% tested.

6.The power supply voltage must increase monotonically from 0 to 2.5V; once VDD reaches 1.5V, it must ramp to 2.5V within 15 ms.

0.1 µF

VDD CLK out

CLOAD

GND

OUTPUTS

CY27EE16Z

Document #: 38-07440 Rev. *B Page 15 of 17

Voltage and Timing Definitions

Ordering Information

Figure 8. Duty Cycle Definition; DC = t2/t1

Figure 9. Rise and Fall Time Definitions: ER = 0.6 x V

/ t3, EF = 0.6 x V

/ t4

Ordering Code Programmed At Package Name Package Type Operating

Range Operating

Voltage

CY27EE16ZEC-XXX[7] Factory

Programmed Z20.173E 20-pin Exposed Pad TSSOP Commercial 3.3V

CY27EE16ZEC-XXXT[7] Factory

Programmed Z20.173E 20-pin Exposed Pad TSSOP –

Tape and Reel Commercial 3.3V

CY27EE16ZEI-XXX[7] Factory

Programmed Z20.173E 20-pin Exposed Pad TSSOP Industrial 3.3V

CY27EE16ZEI-XXXT[7] Factory

Programmed Z20.173E 20-pin Exposed Pad TSSOP –

Tape and Reel Industrial 3.3V

CY27EE16FZEC Field

Programmed Z20.173E 20-pin Exposed Pad TSSOP Commercial 3.3V

CY27EE16FZECT Field

Programmed Z20.173E 20-pin Exposed Pad TSSOP –

Tape and Reel Commercial 3.3V

CY27EE16FZEI Field

Programmed Z20.173E 20-pin Exposed Pad TSSOP Industrial 3.3V

CY27EE16FZEIT Field

Programmed Z20.173E 20-pin Exposed Pad TSSOP

–Tape and Reel Industrial 3.3V

Note:

7.The CY2 7EE16ZEC-XXX, CY27EE1 6ZEC-XXXT, CY27EE16ZEI-XXX a nd CY27EE16ZEI-XXXT are factory-p rogrammed configurations. Fa ctory programming

is available for high-volume design opportunities of 100Ku/year or more in production. For more details, contact your local Cypress field application engineer

or Cypress sales representative.

CY27EE16Z

Document #: 38-07440 Rev. *B Page 16 of 17

Package Drawing and Dimensions

Purchase of I2C component s from Cy press, or one of i ts sublic ensed Associat ed Compa nies, conve ys a license under the Philip s

I2C Patent Right s to use these compon ents in an I2C system, provided that the system conforms to the I2C S tanda rd Specificati on

as defined by Philips. All product and company names mentioned in this document may be the trademarks of their respective

holders. CyberClocks and CyClocksRT are trademarks of Cypress Semiconductor.

20-Lead Thin Shrunk Small Outline Package (4.40-mm Body)—EPAD Z20.173E

51-85168-**

CY27EE16Z

Document #: 38-07440 Rev. *B Page 17 of 17

Document History Page

Document Title: CY27EE16ZE 1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM

Document Number: 38-07440

REV. ECN NO. Issue

Date Orig. of

Change Description of Change

** 116411 10/01/02 CKN New Dat a Shee t

*A 121903 12/14/02 RBI Power-up requirements added to Operating Co nditions information

*B 127953 07/01/03 IJATMP Removed PRELIMINARY from all pages

Changed 18 bits to 18 kbits on first page

Added Note after last paragraph titled “To configure for PDM”

Changed Registers under “Write Protect (WP) Registers”

Added note to Ordering Information table to clarify factory-programmable