DATA SH EET
Product specification
Supersedes data of July 1994
File under Integrated Circuits, IC02
1997 Nov 04
INTEGRATED CIRCUITS
TDA9855
I2C-bus controlled BTSC
stereo/SAP decoder and audio
processor
1997 Nov 04 2
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
FEATURES
•Quasi alignment-free BTSC stereo decoder due to
automatic adjustment of channel separation via I2C-bus
•High integration level with automatically tuned
integrated filters
•Input level adjustment I2C-bus controlled
•Alignment-free SAP processing
•dbx noise reduction circuit
•I2C-bus transceiver.
Audio processor
•Selector for internal and external signals (line in)
•Automatic volume level control
•Subwoofer or surround output with separate volume
control
•Volume control
•Special loudness characteristic automatically controlled
in combination with volume setting
•Bass and treble control
•Audio signal zero-crossing detection between any
volume step switching
•Mute control at audio signal zero-crossing.
GENERAL DESCRIPTION
The TDA9855 is a bipolar-integrated BTSC stereo/SAP
decoder with hi-fi audio processor (I2C-bus controlled) for
application in TV sets.
ORDERING INFORMATION
LICENSE INFORMATION
A license is required for the use of this product. For further information, please contact
TYPE NUMBER PACKAGE
NAME DESCRIPTION VERSION
TDA9855 SDIP52 plastic shrink dual in-line package; 52 leads (600 mil) SOT247-1
TDA9855WP PLCC68 plastic leaded chip carrier; 68 leads SOT188-2
COMPANY BRANCH ADDRESS
THAT Corporation Licensing Operations 734 Forest St.
Marlborough, MA 01752
USA
Tel.: (508) 229-2500
Fax: (508) 229-2590
Tokyo Office 405 Palm House, 1-20-2 Honmachi
Shibuya-ku, Tokyo 151
Japan
Tel.: (03) 3378-0915
Fax: (03) 3374-5191
1997 Nov 04 3
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VCC supply voltage 8.0 8.5 9.0 V
ICC supply current 50 75 95 mA
VCOMP(rms) input signal voltage (RMS value) 100% modulation L + R;
fi= 300 Hz −250 −mV
VoR,L(rms) output signal voltage (RMS value) 100% modulation L + R;
fi= 300 Hz −500 −mV
GLA input level adjustment control maximum gain −4−dB
maximum attenuation −−3.5 −dB
αcs stereo channel separation fL= 300 Hz; fR= 3 kHz 25 35 −dB
THDL,R total harmonic distortion L + R fi= 1 kHz −0.2 −%
VI, O(rms) signal handling (RMS value) THD < 0.5% 2 −−V
AVL control range −15 −+6 dB
Gcvolume control range −71 −+16 dB
LBmaximum loudness boost fi=40Hz −17 −dB
Gbass bass control range fi=40Hz −12 −+16.5 dB
Gtreble treble control range fi= 15 kHz −12 −+12 dB
Gssubwoofer control range fi=40Hz −14 −+14 dB
S/N signal-to-noise ratio line out (mono); Vo= 0.5 V (RMS)
CCIR noise weighting filter
(peak value) −60 −dB
DIN noise weighting filter
(RMS value) −73 −dBA
audio section; Vo= 2 V (RMS);
gain = 0 dB
CCIR noise weighting filter
(peak value) −94 −dB
DIN noise weighting filter
(RMS value) −107 −dBA
1997 Nov 04 4
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
BLOCK DIAGRAM
handbook, full pagewidth
STEREO DECODER VOLUME
RIGHT
LOUDNESS
CONTROL
BASS
RIGHT
CONTROL
TREBLE
RIGHT
CONTROL
SUBWOOFER
MATRIX,
VOLUME
SURROUND
ZERO
CROSSING
TDA9855
EFFECTS
AUTOMATIC
VOLUME AND
LEVEL CONTROL
INPUT
SELECT
DEMATRIX
+
LINEOUT
SELECT
STEREO
/SAP
SWITCH
INPUT
LEVEL
ADJUST
SAP
DEMODULATOR DBX
STEREO
ADJUST SUPPLY LOGIC,
I2C-
TRANCEIVER
VOLUME
LEFT
LOUDNESS
CONTROL
TREBLE
LEFT
CONTROL
C2
31
(40)
29 (38)
32
(41) 33
(43) 34
(46) 35
(47) 36
(48) 37
(49) 38
(50) 41
(54) 39
(51) 40
(52) 10
(14) 42
(55) 43
(56) 44
(57) 45
(58) 46
(59) 51
(67) 50
(66) 52
(68)
CERAMIC
RESONATOR
MURATA
CSB503F58
Q1
C3 C4 C5
C16
C28
C6
VCC
C20
C7 C10
LOR LIR
LOL LIL
C37 C27
External Input Left
(EIL)
External Input Right
(EIR)
C1
COMP
(31)
24
C17 C18 C19 C25C24
C23C22
R6
R7
C21
C8 C9
VIR
C45
C11 R2 R3
C12 C14
OUTR
C36
C35
C40 OUTS
C39 OUTL
BASS
LEFT
CONTROL
C33
MHA837
C32
C31
R5
R4
C30
C29
VIL
MAD SDA SCL
C15 C34
C49
C47
C26 D1
VCC
R1 C13
(63) 47
(65) 49
(5) 4
(7) 6
(1)
1
(4)
3
(3)
2
(11)
7
(12)
8
(13)
9
(36)
27
(35)
28
(6)
5
(15)
11
(39)
30
(37)
28
(18)
13
(19)
14
(16)
12
(20)
15
(21)
16
(22)
17
(23)
18
(27)
21 (24)
19
(25)
20
(29)
22
(30)
23
(33,
34)
25
Fig.1 Block diagram.
The numbers given in parenthesis refer to the TDA9855WP version.
1997 Nov 04 5
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Component list
Electrolytic capacitors ±20%; foil or ceramic capacitors ±10%; resistors ±5%; unless otherwise specified; see Fig.1.
COMPONENTS VALUE TYPE REMARK
C1 10 µF electrolytic 63 V
C2 470 nF foil −
C3 4.7 µF electrolytic 63 V
C4 220 nF foil −
C5 10 µF electrolytic 63 V; Ileak <1.5 µA
C6 2.2 µF electrolytic 16 V
C7 4.7 µF electrolytic 16 V
C8 15 nF foil ±5%
C9 15 nF foil ±5%
C10 2.2 µF electrolytic 63 V
C11 8.2 nF foil or ceramic ±5% SMD 2220/1206
C12 150 nF foil ±5%
C13 33 nF foil ±5%
C14 5.6 nF foil or ceramic ±5% SMD 2220/1206
C15 100 µF electrolytic 16 V
C16 4.7 µF electrolytic 63 V
C17 4.7 µF electrolytic 63 V
C18 100 nF foil
C19 10 µF electrolytic 63 V
C20 4.7 µF electrolytic 63 V
C21 47 nF foil ±5%
C22 1 µF electrolytic 63 V
C23 1 µF electrolytic 63 V
C24 10 µF electrolytic 63 V ±10%
C25 10 µF electrolytic 63 V ±10%
C26 2.2 µF electrolytic 16 V
C27 2.2 µF electrolytic 63 V
C28 4.7 µF electrolytic 63 V ±10%
C29 2.2 µF electrolytic 16 V
C30 8.2 nF foil or ceramic ±5% SMD 2220/1206
C31 150 nF foil ±5%
C32 33 nF foil ±5%
C33 5.6 nF foil or ceramic ±5% SMD 2220/1206
C34 100 µF electrolytic 16 V
C35 150 nF foil ±5%
C36 4.7 µF electrolytic 16 V
C37 4.7 µF electrolytic 16 V
C39 4.7 µF electrolytic 16 V
C40 4.7 µF electrolytic 16 V
1997 Nov 04 6
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
PINNING
C45 2.2 µF electrolytic 16 V
C47 220 µF electrolytic 25 V
C49 100 nF foil or ceramic SMD 1206
D1 −−general purpose diode
R1 2.2 kΩ− −
R2 20 kΩ− −
R3 2.2 kΩ− −
R4 20 kΩ− −
R5 2.2 kΩ− −
R6 8.2 kΩ− ±2%
R7 160 Ω− ±2%
Q1 CSB503F58 radial leads
CSB503JF958 alternative as SMD
SYMBOL PINS DESCRIPTION
PLCC68 SDIP52
TL 1 1 treble control capacitor, left channel
n.c. 2 −not connected
B1L 3 2 bass control capacitor, left channel
B2L 4 3 bass control capacitor, left channel
OUTS 5 4 output subwoofer or output surround sound
MAD 6 5 programmable address bit (module address)
OUTL 7 6 output, left channel
n.c. 8 to 10 −not connected
LDL 11 7 input loudness, left channel
VIL 12 8 input volume control, left channel
EOL 13 9 output effects, left channel
CAV 14 10 automatic volume control capacitor
Vref 15 11 reference voltage 0.5VCC
LIL 16 12 input line, left channel
n.c. 17 −not connected
AVL 18 13 input automatic volume control, left channel
SOL 19 14 output selector, left channel
LOL 20 15 output line control, left channel
CTW 21 16 capacitor timing wideband for dbx
CTS 22 17 capacitor timing spectral for dbx
CW23 18 capacitor wideband for dbx
CS24 19 capacitor spectral for dbx
VEO 25 20 variable emphasis output for dbx
COMPONENTS VALUE TYPE REMARK
1997 Nov 04 7
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
n.c. 26 −not connected
VEI 27 21 variable emphasis input for dbx
n.c. 28 −not connected
CNR 29 22 capacitor noise reduction for dbx
CM30 23 capacitor mute for SAP
CDEC 31 24 capacitor DC-decoupling for SAP
n.c. 32 −not connected
AGND 33 −analog ground
DGND 34 −digital ground
GND −25 ground
SDA 35 26 serial data input/output (I2C-bus)
SCL 36 27 serial clock input (I2C-bus)
VCC 37 28 supply voltage
COMP 38 29 composite input signal
VCAP 39 30 capacitor for electronic filtering of supply
CP1 40 31 capacitor for pilot detector
CP2 41 32 capacitor for pilot detector
n.c. 42 −not connected
CPH 43 33 capacitor for phase detector
n.c. 44, 45 −not connected
CADJ 46 34 capacitor for filter adjustment
CER 47 35 ceramic resonator
CMO 48 36 capacitor DC-decoupling mono
CSS 49 37 capacitor DC-decoupling stereo/SAP
LOR 50 38 output line control, right channel
SOR 51 39 output selector, right channel
AVR 52 40 input automatic volume control, right channel
n.c. 53 −not connected
LIR 54 41 input line control, right channel
CPS2 55 42 capacitor 2 pseudo function
CPS1 56 43 capacitor 1 pseudo function
EOR 57 44 output effects, right channel
VIR 58 45 input volume control, right channel
LDR 59 46 input loudness, right channel
n.c. 60 to 62 −not connected
OUTR 63 47 output, right channel
n.c. 64 48 not connected
SW 65 49 filter capacitor for subwoofer
SYMBOL PINS DESCRIPTION
PLCC68 SDIP52
1997 Nov 04 8
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
B2R 66 50 bass control capacitor, right channel
B1R 67 51 bass control capacitor, right channel
TR 68 52 treble control capacitor
SYMBOL PINS DESCRIPTION
PLCC68 SDIP52
Fig.2 Pin configuration (PLCC version).
handbook, full pagewidth
TDA9855H
MHA836
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
Vref
n.c.
LDL
VIL
EOL
CAV
LIL
n.c.
AVL
SOL
LOL
CTW
CTS
CW
CS
VEO
n.c.
n.c.
LDR
VIR
EOR
CPS1
CPS2
LIR
n.c.
AVR
SOR
LOR
CSS
CMO
CER
CADJ
n.c.
n.c.
TL
n.c.
B1L
B2L
OUTS
MAD
OUTL
n.c.
n.c.
TR
B1R
B2R
SW
n.c.
OUTR
n.c.
n.c.
VEI
n.c.
CNR
CM
CDEC
n.c.
AGND
DGND
SDA
SCL
VCC
COMP
VCAP
CP1
CP2
n.c.
CPH
1997 Nov 04 9
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Fig.3 Pin configuration (SDIP version).
handbook, halfpage
TDA9855
MHA835
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
TL TR
B1L B1R
B2L B2R
OUTS SW
MAD n.c.
OUTL OUTR
LDL LDR
VIL VIR
EOL EOR
CAV CPS1
Vref CPS2
LIL LIR
AVL AVR
SOL SOR
LOL LOR
CTW CSS
CTS CMO
CWCER
CsCADJ
VEO CPH
VEI CP2
CNR CP1
CMVCAP
CDEC COMP
GND VCC
SDA SCL
FUNCTIONAL DESCRIPTION
Decoder
INPUT LEVEL ADJUSTMENT
The composite input signal is fed to the input level
adjustment stage. In order to compensate tolerances of
the FM demodulator which supplied the composite input
signal, the TDA9855 provides an input level adjustment
stage. The control range is from−3.5 to +4.0 dB in steps of
0.5 dB. The subaddress control 3 of Tables 5 and 6 and
the level adjust setting of Table 22 allows an optimum
signal adjustment during the set alignment in the
production line. This value has to be stored in a
non-volatile memory. The maximum input signal voltage is
2 V (RMS).
STEREO DECODER
The output signal of the level adjustment stage is coupled
to a low-pass filter which suppresses the baseband noise
above 125 kHz. The composite signal is then fed into a
pilot detector/pilot cancellation circuit and into the MPX
demodulator. The main L + R signal passes a 75 µs fixed
de-emphasis filter and is fed into the dematrix circuit.
The decoded sub-signal L −R is sent to the stereo/SAP
switch. To generate the pilot signal the stereo demodulator
uses a PLL circuit including a ceramic resonator.
The stereo channel separation can be adjusted by an
automatic procedure or manually. For a detailed
description see Section “Adjustment procedure”.
The stereo identification can be read by the I2C-bus
(see Table 2). Two different pilot thresholds can be
selected via the I2C-bus (see Table 24).
SAP DEMODULATOR
The composite signal is fed from the output of the input
level adjustment stage to the SAP demodulator circuit
through a 5fH (fH= horizontal frequency) band-pass filter.
The demodulator level is automatically controlled.
The SAP demodulator includes internal noise and field
strength detectors that mute the SAP output in the event of
insufficient signal conditions. The SAP identification signal
can be read by the I2C-bus (see Table 2).
SWITCH
The stereo/SAP switch feeds either the L −R signal or the
SAP demodulator output signal via the internal dbx noise
reduction circuit to the dematrix/line out select circuit.
Table 21 shows the different switch modes provided at the
output pins LOR and LOL.
1997 Nov 04 10
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
dbx DECODER
The circuit includes all blocks required for the noise
reduction system in accordance with the BTSC system
specification. The output signal is fed through a 73 µs fixed
de-emphasis circuit to the dematrix block.
INTEGRATED FILTERS
The filter functions necessary for stereo and SAP
demodulation and part of the dbx filter circuits are provided
on-chip using transconductor circuits. The required filter
accuracy is attained by an automatic filter alignment
circuit.
Audio processor
SELECTOR
The selector allows selecting either the internal line out
signals LOR or LOL (dematrix output) or the external line
in signals LIR and LIL and combines the left and right
signals in several modes (see Table 12). The input signal
capability of the line inputs (LIR/LIL) is 2 V (RMS).
The output of the selector is AC-coupled to the automatic
volume level control circuit via pins SOR/SOL and
AVR/AVL to avoid offset voltages.
AUTOMATIC VOLUME LEVEL CONTROL
The automatic volume level stage controls its output
voltage to a constant level of typically 200 mV (RMS) from
an input voltage range of 0.1 to 1.1 V (RMS). The circuit
adjusts variations in modulation during broadcasting and
due to changes in the programme material. The function
can be switched off. To avoid audible ‘plops’ during the
permanent operation of the AVL circuit a soft blending
scheme has been applied between the different gain
stages. A capacitor (4.7 µF) at pin CAV determines the
attack and decay time constants. In addition the ratio of
attack and decay time can be changed via the I2C-bus
(see notes 7 and 8 of Chapter “Characteristics”).
EFFECTS
The audio processor section offers the following mode
selections: linear stereo, pseudo stereo, spatial stereo and
forced mono.The spatial mode provides an antiphase
crosstalk of 30% or 52% (switchable via the I2C-bus;
see Table 18).
VOLUME/LOUDNESS
The volume control range is from +16 dB to −71 dB in
steps of 1 dB and ends with a mute step (see Table 8).
Balance control is achieved by the independent volume
control of each channel. The volume control blocks
operate in combination with the loudness control. The filter
is linear when maximum gain for volume control is
selected. The filter characteristic changes automatically
over a range of 28 dB down to a setting of −12 dB.
At −12 dB volume control the maximum loudness boost is
obtained. The filter characteristic is determined by external
components. The proposed application provides a
maximum boost of 17 dB for bass and 4.5 dB for treble.
The loudness may be switched on or off via I2C-bus
control (see Table 14). The left and right volume control
stages include two independent zero-crossing detectors.
In the zero-crossing mode a change in volume is
automatically activated but not executed. The execution is
enabled at the next zero-crossing of the signal. If a new
volume step is activated before the previous one has been
processed, the previous value will be executed first, and
then the new value will be activated. If no zero-crossing
occurs the next volume transmission will enforce the last
activated volume setting.
The zero-crossing mode is realized between adjoining
steps and between any steps, but not from any step to
mute. In this case the GMU bit is required for use. In case
only one channel has to be muted, two steps are
necessary. The first step is a transmission of any step to
−71 dB and the second step is the −71 dB step to mute
mode. The step of −71 dB to mute mode has no
zero-crossing but this is not relevant. This procedure has
to be provided by software.
BASS CONTROL
A single external 33 nF capacitor for each channel in
combination with a linear operational amplifier and internal
resistors provides a bass control range of +16.5 to −12 dB
in steps of 1.5 dB at low frequencies (40 Hz). Internally the
basic step width is 3 dB, with intermediate steps obtained
by a toggle function that provides an additional 1.5 dB
boost or attenuation (see Table 9). It should be noted that
both loudness and bass control together result in a
maximum bass boost of 34.5 dB for low volume steps.
TREBLE CONTROL
The adjustable range of the treble control stage is from
−12 to +12 dB in steps of 3 dB. The filter characteristic is
determined by an external 5.6 nF capacitor for each
channel. The logic circuitry is arranged in a way that the
same data words (06H to 16H) can be used for both tone
controls if a bass control range from −12 to +12 dB and a
treble control range from −12 to +12 dB with 3 dB steps
are used (see Tables 9 and 10).
1997 Nov 04 11
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
SUBWOOFER;SURROUND SOUND CONTROL
The subwoofer or the surround mode can be activated with
the control bit SUR (see Table 6). A low bit provides an
output signal 1⁄2(L + R) in subwoofer mode, a high bit
selects surround mode and provides an output signal
1⁄2(L −R). The signal is fed through a volume control stage
with a range from +14 to −14 dB in 2 dB steps on top of the
main channel control to the output pin OUTS. The last
setting is the mute position (see Table 11). The capacitor
C35 at pin SW provides a 230 Hz low-pass filter in
subwoofer mode. In surround mode this capacitor should
be disconnected. If balance is not in mid position the
selected left and right output levels will be combined.
MUTE
The mute function can be activated independently with the
last step of volume or subwoofer/surround control at the
left, right or centre output. By setting the general mute bit
GMU via the I2C-bus all audio part outputs are muted.
All channels include an independent zero-crossing
detector. The zero-crossing mute feature can be selected
via bit TZCM:
TZCM = 0: forced mute with direct execution
TZCM = 1: execution in time with signal zero-crossing.
In the zero-crossing mode a change of the GMU bit is
activated but not executed. The execution is enabled at
the next zero-crossing of the signal. To avoid a large delay
of mute switching, when very low frequencies are
processed, or the output signal amplitude is lower than the
DC offset voltage, the following I2C-bus transmissions are
needed:
A first transmission for mute execution
A second transmission approximately 100 ms later,
which must switch the zero-crossing mode to forced
mute (TZCM = 0)
A third transmission to reactivate the zero-crossing
mode (TZCM = 1). This transmission can take place
immediately, but must follow before the next mute
execution.
Adjustment procedure
COMPOSITE INPUT LEVEL ADJUSTMENT
Apply the composite signal (from the FM demodulator)
with 100% modulation (25 kHz deviation) L + R;
fi= 300 Hz. Set input level control via the I2C-bus
monitoring line output (500 mV ±20 mV). Store the setting
in a non-volatile memory. Adjustment of the spectral and
wideband expander is performed via the stereo channel
separation adjust.
AUTOMATIC ADJUSTMENT PROCEDURE
•Capacitors of external inputs EIL and EIR must be
grounded
•Composite input signal L = 300 Hz, R = 3.1 kHz,
14% modulation for each channel; volume gain +16 dB
via the I2C-bus; to avoid annoying sound level set GMU
bit to logic 1 during adjustment procedure
•Effects, AVL, loudness off
•Selector setting SC0, SC1 and SC2 = 0, 0, 0
(see Table 12)
•Line out setting bits: STEREO = 1, SAP = 0
(see Table 21)
•Start adjustment by transmission ADJ = 1 in register
ALI3; the decoder will align itself
•After 1 second, stop alignment by transmitting ADJ = 0
in register ALI3 read the alignment data by an I2C-bus
read operation from ALR1 and ALR2
(see Chapter “I2C-bus protocol”) and store it in a
non-volatile memory; the alignment procedure
overwrites the previous data stored in ALI1 and ALI2
•Disconnect the capacitors of external inputs from
ground.
MANUAL ADJUSTMENT
Manual adjustment is necessary when no dual tone
generator is available (e.g. for service).
•Spectral and wideband data have to be set to 10000
(middle position for adjustment range)
•Composite input L = 300 Hz; 14% modulation
•Adjust channel separation by varying wideband data
•Composite input L = 3 kHz; 14% modulation
•Adjust channel separation by varying spectral data
•Iterative spectral/wideband operation for optimum
adjustment
•Store data in non-volatile memory.
After every power-on, the alignment data and the input
level adjustment data must be loaded from the non-volatile
memory.
TIMING CURRENT FOR RELEASE RATE
Due to possible internal and external spreading, the timing
current can be adjusted via the I2C-bus (see Table 25) as
recommended by dbx.
1997 Nov 04 12
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Requirements for the composite input signal to ensure correct system performance
Notes
1. Low-ohmic preferred, otherwise the signal loss and spreading at COMP, caused by Zo and the composite input
impedance (see Chapter “Characteristics”, Section INPUT LEVEL ADJUSTMENT CONTROL) must be taken into
account.
2. In order to prevent clipping at over-modulation (maximum deviation in the BTSC system for 100% modulation is
73 kHz).
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
COMPL+R(rms) composite input level for 100%
modulation L + R;
25 kHz deviation;
fi= 300 Hz; RMS value
measured at pin COMP 162 250 363 mV
∆COMP composite input level
spreading under operating
conditions
Tamb =−20 to +70 °C; aging;
power supply influence −0.5 −+0.5 dB
Zooutput impedance note 1 −low-ohmic 5 kΩ
flf low frequency roll-off 25 kHz deviation L + R; −2dB −− 5Hz
f
hf high frequency roll-off 25 kHz deviation L + R; −2 dB 100 −−kHz
THDL,R total harmonic distortion L + R fi= 1 kHz; 25 kHz deviation −− 0.5 %
fi= 1 kHz; 125 kHz deviation;
note 2 −− 1.5 %
S/N signal-to-noise ratio
L + R/noise CCIR 468-2 weighted quasi
peak; L + R; 25 kHz deviation;
fi= 1 kHz; 75 µs de-emphasis
critical picture modulation 44 −−dB
with sync only 54 −−dB
αSB side band suppression mono
into unmodulated SAP carrier;
SAP carrier/side band
mono signal: 25 kHz deviation,
fi= 1 kHz; side band: SAP
carrier frequency ±1 kHz
46 −−dB
αSP spectral spurious attenuation
L + R/spurious 50 Hz to 100 kHz;
mainly n ×fH; no de-emphasis;
L + R; 25 kHz deviation,
f = 1 kHz as reference
40 −−dB
1997 Nov 04 13
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Notes
1. Human body model: C = 100 pF; R = 1.5 kΩ.
2. Charge device model: C = 200 pF; R = 0 Ω.
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage 0 9.5 V
Vnvoltage of all other pins with respect to pin
GND 0V
CC V
Tamb operating ambient temperature −20 +70 °C
Tstg storage temperature −65 +150 °C
Vesd electrostatic handling note 1 −2000 +2000 V
note 2 −300 +300 V
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth(j-a) thermal resistance from junction to ambient in free air
SOT247-1 43 K/W
SOT188-2 38 K/W
1997 Nov 04 14
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
CHARACTERISTICS
All voltages are measured relative to GND; VCC = 8.5 V; source resistance Rs≤600 Ω; output load RL≥10 kΩ;
CL≤2.5 nF; AC-coupled; fi= 1 kHz; Tamb =25°C; volume gain control Gc= 0 dB; bass linear; treble linear;
loudness off; AVL off; effects linear; composite input signal in accordance with BTSC standard; see Fig.1;
unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
General
VCC supply voltage 8.0 8.5 9.0 V
ICC supply current 50 75 95 mA
VDC DC voltage at signal handling
pins −1⁄2VCC −V
Decoder section
INPUT LEVEL ADJUSTMENT CONTROL
GLA input level adjustment control maximum gain −4.0 −dB
maximum attenuation −−3.5 −dB
Gstep step resolution −0.5 −dB
Vi(rms) maximum input voltage level
(RMS value) 2−−V
Z
iinput impedance 29.5 35 40.5 kΩ
STEREO DECODER
MPXL+R(rms) input voltage level for 100%
modulation L + R; 25 kHz
deviation (RMS value)
input level adjusted via I2C-bus
(L + R; fi= 300 Hz);
monitoring line out
−250 −mV
MPXL−Rinput voltage level for 100%
modulation L −R; 50 kHz
deviation (peak value)
−707 −mV
MPX(max) maximum headroom for L + R,
L, R fmod < 15 kHz; THD < 15% for
75 µs equivalent input
modulation
9−−dB
MPXpilot(rms) nominal stereo pilot voltage
level (RMS value) −50 −mV
STon(rms) pilot threshold voltage stereo
on (RMS value) data STS = 1 −− 35 mV
data STS = 0 −− 30 mV
SToff(rms) pilot threshold voltage stereo
off (RMS value) data STS = 1 15 −−mV
data STS = 0 10 −−mV
hys hysteresis −2.5 −dB
OUTL+R output voltage level for 100%
modulation L + R at LINE OUT input level adjusted via I2C-bus
(L + R; fi= 300 Hz);
monitoring LINE OUT
480 500 520 mV
1997 Nov 04 15
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
αcs stereo channel separation L/R
at LINE OUT aligned with dual tone 14%
modulation; see Section
“Adjustment procedure” in
Chapter “Functional
description”
fL= 300 Hz; fR= 3 kHz 25 35 −dB
fL= 300 Hz; fR= 8 kHz 20 30 −dB
fL= 300 Hz; fR= 10 kHz 15 25 −dB
fL, R L, R frequency response 14% modulation;
fref = 300 Hz L or R
fi=50Hzto11kHz −3−−dB
fi= 12 kHz −−3−dB
THDL,R total harmonic distortion L, R
at LINE OUT modulation L or R
1% to 100%; fi= 1 kHz −0.2 1.0 %
S/N signal-to-noise ratio mono mode; CCIR 468-2
weighted; quasi peak;
500 mV output signal
50 60 −dB
STEREO DECODER,OSCILLATOR (VCXO); note 1
fonominal VCXO output
frequency (32fH)with nominal ceramic
resonator −503.5 −kHz
fof spread of free-running
frequency with nominal ceramic
resonator 500.0 −507.0 kHz
∆fHcapture range frequency
(nominal pilot) ±190 ±265 −Hz
SAP DEMODULATOR; note 2
SAPi(rms) nominal SAP carrier input
voltage level (RMS value) 15 kHz frequency deviation of
intercarrier −150 −mV
SAPon(rms) pilot threshold voltage SAP on
(RMS value) −− 85 mV
SAPoff(rms) pilot threshold voltage SAP off
(RMS value) 35 −−mV
SAPhys hysteresis −2−dB
SAPLEV SAP output voltage level at
LINE OUT LINE OUT (LOL, LOR) in
position SAP/SAP;
fmod = 300 Hz;
100% modulation
−500 −mV
fres frequency response 14% modulation;
50 Hz to 8 kHz; fref = 300 Hz −3−−dB
THD total harmonic distortion fi= 1 kHz −0.5 2.0 %
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1997 Nov 04 16
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
LINE OUT AT PINS LOL AND LOR
Vo(rms) nominal output voltage
(RMS value) 100% modulation −500 −mV
HEADooutput headroom 9 −−dB
Zooutput impedance −80 120 Ω
VODC output voltage 0.45VCC 0.5VCC 0.55VCC V
RLoutput load resistance 5 −−kΩ
C
Loutput load capacitance −− 2.5 nF
αct idle crosstalk L, R into SAP 100% modulation; fi= 1 kHz;
L or R; line out switched to
SAP/SAP
50 −−dB
idle crosstalk SAP into L, R 100% modulation; fi= 1 kHz;
SAP; line out switched to
stereo
50 −−dB
∆VST-SAP output voltage difference if
switched from L, R to SAP 250 Hz to 6.3 kHz −− 3dB
dbx NOISE REDUCTION CIRCUIT
tadj stereo adjustment time see Section “Adjustment
procedure” in Chapter
“Functional description”
−− 1s
I
snominal timing current for
nominal release rate of
spectral RMS detector
Is can be measured at pin 17
(pin 22) via current meter
connected to 1⁄2VCC +1V
−24 −µA
∆I
sspread of timing current −− 15 %
Is(range) timing current adjustment
range 7 steps via I2C-bus −±30 −%
Ittiming current for release rate
of wideband RMS detector −1⁄3Is−µA
Relrate nominal RMS detector
release rate nominal timing current and
external capacitor values
wideband −125 −dB/s
spectral −381 −dB/s
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1997 Nov 04 17
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Audio part
CIRCUIT SECTION FROM PINS LIL AND LIR TO PINS OUTL, OUTR AND OUTS; note 3
B roll-off frequencies C6,C
7
,C
10,C
26,C
27 and
C29 = 2.2 µF; Zi=Z
i(min)
low frequency (−3 dB) −− 20 Hz
high frequency (−0.5 dB) 20 −−kHz
THD total harmonic distortion Vi= 1 V (RMS); Gc= 0 dB;
AVL on −0.2 0.5 %
Vi= 2 V (RMS); Gc= 0 dB;
AVL on −0.2 0.5 %
Vi= 1 V (RMS); Gc= 0 dB;
AVL off −0.05 −%
Vi= 2 V (RMS); Gc= 0 dB;
AVL off −0.02 −%
PSRR power supply ripple rejection Vr(rms) < 200 mV; fi= 100 Hz 47 50 −dB
αBcrosstalk between bus inputs
and signal outputs notes 4 and 5 −110 −dB
Vno noise output voltage CCIR 468-2 weighted;
quasi peak −40 80 µV
measured in dBA −8−µV
α
cs channel separation Vi=1V; f
i= 1 kHz 75 −−dB
Vi=1V; f
i= 12.5 kHz 75 −−dB
SELECTOR (FROM PINS LOL, LOR, LIL AND LIR TO PINS SOL AND SOR)
Ziinput impedance 16 20 24 kΩ
αsinput isolation of one selected
source to any other input f = 1 kHz; Vi=1V 86 96 −dB
f = 12.5 kHz; Vi=1V 80 96 −dB
Vi(rms) maximum input voltage
(RMS value) THD <0.5% 2 2.3 −V
Voffset DC offset voltage at selector
output by selection of any
inputs
−− 25 mV
Zooutput impedance −80 120 Ω
RLoutput load resistance (AC) 5 −−kΩ
C
Loutput load capacitance −− 2.5 nF
Gcvoltage gain, selector −0−dB
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1997 Nov 04 18
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
AUTOMATIC VOLUME LEVEL CONTROL (AVL)
Ziinput impedance 8.8 11.0 13.2 kΩ
Vi(rms) maximum input voltage
(RMS value) THD < 0.2% 2 −−V
G
vgain, maximum boost 5 6 7 dB
maximum attenuation 14 15 16 dB
Gstep equivalent step width between
the input stages
(soft switching system)
−1.5 −dB
Vi(rms) input level at maximum boost
(RMS value) see Fig.4 −0.1 −V
input level at maximum
attenuation (RMS value) see Fig.4 −1.125 −V
Vo(rms) output level in AVL operation
(RMS value) see Fig.4 160 200 250 mV
VDC(OFF) DC offset between different
gain steps voltage at pin CAV
6.50 to 6.33 V or
6.33 to 6.11 V or
6.11 to 5.33 V or
5.33 to 2.60 V; note 6
−− 6mV
R
att discharge resistors for attack
time constant AT1 = 0; AT2 = 0; note 7 340 420 520 Ω
AT1 = 1; AT2 = 0; note 7 590 730 910 Ω
AT1 = 0; AT2 = 1; note 7 0.96 1.2 1.5 kΩ
AT1 = 1; AT2 = 1; note 7 1.7 2.1 2.6 kΩ
Idec charge current for decay time normal mode; CCD = 0; note 8 1.6 2.0 2.4 µA
EFFECT CONTROLS
αspat1 anti-phase crosstalk by spatial
effect −52 −%
αspat2 −30 −%
ϕphase shift by pseudo-stereo see Fig.5 −− −−
V
OLUME TONE CONTROL PART (INPUT PINS VIL AND VIR TO PINS OUTX AND OUTS)
Zivolume input impedance 8.0 10.0 12.0 kΩ
Zooutput impedance −80 120 Ω
RLoutput load resistance (AC) 5 −−kΩ
C
Loutput load capacitance −− 2.5 nF
Vi(rms) maximum input voltage
(RMS value) THD < 0.5% 2.0 2.15 −V
Vno noise output voltage CCIR 468-2 weighted;
quasi peak
Gc=16dB −110 220 µV
Gc=0dB −33 50 µV
mute position −10 −µV
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1997 Nov 04 19
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Gctotal continuous control range maximum boost −16 −dB
maximum attenuation −71 −dB
Gstep step resolution −1−dB
step error between any
adjoining step −− 0.5 dB
∆Gaattenuator set error Gc= +16 to −50 dB −− 2dB
G
c
=−51 to −71 dB −− 3dB
∆G
tgain tracking error Gc= +16 to −50 dB −− 2dB
α
mmute attenuation 80 −−dB
VDC(OFF) DC step offset between any
adjacent step Gc= +16 to 0 dB −0.2 10.0 mV
Gc=0to−71 dB −− 5mV
DC step offset between any
step to mute Gc= +16 to +1 dB −215mV
G
c
=0to−71 dB −110mV
LOUDNESS CONTROL PART
LBmaximum loudness boost loudness on; referred to
loudness off; boost is
determined by external
components; see Fig.6
fi=40Hz −17 −dB
fi= 10 kHz −4.5 −dB
BASS CONTROL (see Fig.7)
Gbass bass control maximum boost fi= 40 Hz 15.5 16.5 17.5 dB
maximum attenuation fi=40Hz 11 12 13 dB
G
step step resolution fi=40Hz −1.5 −dB
step error between any
adjoining step −− 0.5 dB
VDC(OFF) DC step offset between any
adjacent step −− 15 mV
TREBLE CONTROL (see Fig.8)
Gtreble treble control maximum boost fi= 15 kHz 11 12 13 dB
maximum attenuation fi= 15 kHz 11 12 13 dB
maximum boost fi> 15 kHz −− 15 dB
Gstep step resolution fi= 15 kHz −3−dB
step error between any
adjoining step −− 0.5 dB
VDC(OFF) DC step offset between any
adjacent step −− 10 mV
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1997 Nov 04 20
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
SUBWOOFER OR SURROUND CONTROL
Gssubwoofer control maximum boost; fi=40Hz1214 16dB
maximum attenuation;
fi=40Hz 12 14 16 dB
Gstep step resolution −2−dB
αmmute attenuation 60 −−dB
VDC(OFF) DC step offset between any
adjacent step Gs= 0 to +14 dB −− 10 mV
Gs=0to−14 dB −− 5mV
DC step offset between any
step to mute Gs= +2 to +14 dB without
input offset (pin SW connected
to Vref)
−− 15 mV
Gs= +2 to +14 dB inclusive
offset from OUTR, OUTL −− 50 mV
Gs=0to−14 dB −− 10 mV
RFinternal resistor for low-pass
filter with external capacitor at
pin SW
45 6kΩ
L+R
REJ common mode rejection in
surround sound at pin OUTS mono signal at VIL/VIR;
f = 1 kHz; Vi=1V;
balance = 0 dB
26 36 −dB
MUTING AT POWER SUPPLY DROP FOR OUTL, OUTR AND OUTS
VCC-DROP supply drop for mute active −VCAP −0.7 −V
POWER-ON RESET; note 9
VRESET(STA) start of reset voltage increasing supply voltage −− 2.5 V
decreasing supply voltage 4.2 5 5.8 V
VRESET(END) end of reset voltage increasing supply voltage 5.2 6 6.8 V
Digital part (I2C-bus pins); note 10
VIH HIGH-level input voltage 3 −VCC V
VIL LOW-level input voltage −0.3 −+1.5 V
IIH HIGH-level input current −10 −+10 µA
IIL LOW-level input current −10 −+10 µA
VOL LOW-level output voltage IIL =3mA −− 0.4 V
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1997 Nov 04 21
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Notes to the characteristics
1. The oscillator is designed to operate together with a MURATA resonator CSB503F58 for TDA9855. Change of the
resonator supplier is possible, but the resonator specification must be close to CSB503F58 for TDA9855.
2. The internal SAP carrier level is determined by the composite input level and the level adjustment gain.
3. Select in to input line control.
4. Crosstalk:
5. The transmission contains:
a) Total initialization with MAD and SAD for volume and 11 DATA words, see also definition of characteristics
b) Clock frequency = 50 kHz
c) Repetition burst rate = 400 Hz
d) Maximum bus signal amplitude = 5 V (p-p).
6. The listed pin voltage corresponds with typical gain steps of +6 dB, +3 dB, 0 dB, −6 dB and −15 dB.
7. Attack time constant = CAV ×Ratt.
8.
Example: CAV = 4.7 µF; Idec =2µA; Gv1 =−9 dB; Gv2 =+6dB→ decay time results in 4.14 s.
9. When reset is active the GMU-bit (general mute) and the LMU-bit (LINE OUT mute) is set and the I2C-bus receiver
is in the reset position.
10. The AC characteristics are in accordance with the I2C-bus specification. The maximum clock frequency is 100 kHz.
Information about the I2C-bus can be found in the brochure
“The I
2
C-bus and how to use it”
(order number 9398 393 40011).
20 logVbus(p-p)
Vo(rms)
---------------------
Decay time
CAV 0.76 V×10
Gv1
–20
------------- 10
Gv2
–20
-------------
–
I
dec
-----------------------------------------------------------------------------------
=
1997 Nov 04 22
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
I2C-BUS PROTOCOL
I2C-bus format to read (slave transmits data)
Table 1 Explanation of I2C-bus format to read (slave transmits data)
Table 2 Definition of the transmitted bytes after read condition
Table 3 Function of the bits in Table 2
The master generates an acknowledge when it has received the first data word ALR1, then the slave transmits the next
data word ALR2. Afterwards the master generates an acknowledge, then the slave begins transmitting the first data word
ALR1 etc. until the master generates no acknowledge and transmits a STOP condition.
S SLAVE ADDRESS R/W A DATA MA DATA P
NAME DESCRIPTION
S START condition; generated by the master
Standard SLAVE ADDRESS 101 101 1 pin MAD not connected
Pin programmable SLAVE ADDRESS 101 101 0 pin MAD connected to ground
R/W logic 1 (read); generated by the master
A acknowledge; generated by the slave
DATA slave transmits an 8-bit data word
MA acknowledge; generated by the master
P STOP condition; generated by the master
FUNCTION BYTE MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0
Alignment read 1 ALR1 Y SAPP STP A14 A13 A12 A11 A10
Alignment read 2 ALR2 Y SAPP STP A24 A23 A22 A21 A20
BITS FUNCTION
STP stereo pilot identification (stereo received = 1)
SAPP SAP pilot identification (SAP received = 1)
A1X to A2X stereo alignment read data
A1X for wideband expander
A2X for spectral expander
Y indefinite
1997 Nov 04 23
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
I2C-bus format to write (slave receives data)
Table 4 Explanation of I2C-bus format to write (slave receives data)
If more than 1 byte of DATA is transmitted, then auto-increment is performed, starting from the transmitted subaddress
and auto-increment of subaddress in accordance with the order of Table 5 is performed.
Table 5 Subaddress second byte after slave address
S SLAVE ADDRESS R/W A SUBADDRESS A DATA A P
NAME DESCRIPTION
S START condition
Standard SLAVE ADDRESS 101 101 1 pin MAD not connected
Pin programmable SLAVE ADDRESS 101 101 0 pin MAD connected to ground
R/W logic 0 (write)
A acknowledge; generated by the slave
SUBADDRESS (SAD) see Table 5
DATA see Table 6
P STOP condition
FUNCTION REGISTER MSB LSB HEX
D7 D6 D5 D4 D3 D2 D1 D0
Volume right VR 0 0 0 0 000000
Volume left VL 0 0 0 0 000101
Bass BA 0 0 0 0 001002
Treble TR 0 0 0 0 001103
Subwoofer SW 0 0 0 0 010004
Control 1 CON1 0 0 0 0 010105
Control 2 CON2 0 0 0 0 011006
Control 3 CON3 0 0 0 0 011107
Alignment 1 ALI1 0 0 0 0 100008
Alignment 2 ALI2 0 0 0 0 100109
Alignment 3 ALI3 0 0 0 0 10100A
1997 Nov 04 24
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Table 6 Definition of third byte after slave address
Table 7 Function of the bits in Table 6
FUNCTION REGISTER MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0
Volume right VR 0 VR6 VR5 VR4 VR3 VR2 VR1 VR0
Volume left VL 0 VL6 VL5 VL4 VL3 VL2 VL1 VL0
Bass BA 0 0 0 BA4 BA3 BA2 BA1 BA0
Treble TR 0 0 0 TR4 TR3 TR2 TR1 0
Subwoofer SW 0 0 SW5 SW4 SW3 SW2 0 0
Control 1 CON1 GMU AVLON LOFF X SUR SC2 SC1 SC0
Control 2 CON2 SAP STEREO TZCM VZCM LMU EF2 EF1 EF0
Control 3 CON3 0 0 0 0 L3 L2 L1 L0
Alignment 1 ALI1 0 0 0 A14 A13 A12 A11 A10
Alignment 2 ALI2 STS 0 0 A24 A23 A22 A21 A20
Alignment 3 ALI3 ADJ AT1 AT2 0 1 TC2 TC1 TC0
BITS FUNCTION
VR0 to VR6 volume control right
VL0 to VL6 volume control left
BA0 to BA4 bass control
TR1 to TR3 treble control
SW2 to SW5 subwoofer, surround control
GMU mute control for outputs OUTL, OUTR and OUTS (generate mute)
AVLON AVL on/off
LOFF switch loudness on/off
X don’t care bit
SUR surround/subwoofer SUR = 1 →1⁄2(L −R); SUR = 0 →1⁄2(L + R)
SC0 to SC2 selection between line in and line out
STEREO, SAP mode selection for line out
TZCM zero-crossing mode in mute operation (treble and subwoofer/surround output stage)
VZCM zero-crossing mode in volume operation
LMU mute control for dematrix + line out select
EF0 to EF2 selection between mono, stereo linear, spatial stereo and pseudo mode
L0 to L3 input level adjustment
ADJ stereo adjustment on/off
A1X stereo alignment data for wideband expander
A2X stereo alignment data for spectral expander
AT1 and AT2 attack time at AVL
TC0 to TC2 timing current alignment data
STS stereo level switch
1997 Nov 04 25
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Table 8 Volume setting in registers VR and VL
Gc
(dB)
DATA
D6
V6 D5
V5 D4
V4 D3
V3 D2
V2 D1
V1 D0
V0 HEX
1611111117F
1511111107E
1411111017D
1311111007C
1211110117B
1111110107A
10111100179
9111100078
8111011177
7111011076
6111010175
5111010074
4111001173
3111001072
2111000171
1111000070
011011116F
−111011106E
−211011016D
−311011006C
−411010116B
−511010106A
−6110100169
−7110100068
−8110011167
−9110011066
−10110010165
−11110010064
−12110001163
−13110001062
−14110000161
−15110000060
−1610111115F
−1710111105E
−1810111015D
−1910111005C
−2010110115B
−2110110105A
1997 Nov 04 26
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
−22101100159
−23101100058
−24101011157
−25101011056
−26101010155
−27101010054
−28101001153
−29101001052
−30101000151
−31101000050
−3210011114F
−3310011104E
−3410011014D
−3510011004C
−3610010114B
−3710010104A
−38100100149
−39100100048
−40100011147
−41100011046
−42100010145
−43100010044
−44100001143
−45100001042
−46100000141
−47100000040
−4801111113F
−4901111103E
−5001111013D
−5101111003C
−5201110113B
−5301110103A
−54011100139
−55011100038
−56011011137
−57011011036
−58011010135
−59011010034
−60011001133
G
c
(dB)
DATA
D6
V6 D5
V5 D4
V4 D3
V3 D2
V2 D1
V1 D0
V0 HEX
1997 Nov 04 27
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Table 9 Bass setting in register BA
−61011001032
−62011000131
−63011000030
−6401011112F
−6501011102E
−6601011012D
−6701011002C
−6801010112B
−6901010102A
−70010100129
−71010100028
Mute 0 1 0011127
G
bass
(dB)
DATA
D4
BA4 D3
BA3 D2
BA2 D1
BA1 D0
BA0 HEX
16.5 1100119
15.0 1100018
13.5 1011117
12.0 1011016
10.5 1010115
9.01010014
7.51001113
6.01001012
4.51000111
3.01000010
1.5011110F
0011100E
−1.5011010D
−3.0011000C
−4.5010110B
−6.0010100A
−7.50100109
−9.00100008
−10.5 0011107
−12.0 0011006
G
c
(dB)
DATA
D6
V6 D5
V5 D4
V4 D3
V3 D2
V2 D1
V1 D0
V0 HEX
1997 Nov 04 28
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Table 10 Treble setting in register TR
Table 11 Subwoofer/surround setting in register SW
Gtreble
(dB)
DATA
D4
TR4 D3
TR3 D2
TR2 D1
TR1 HEX
12101116
9101014
6100112
3100010
001110E
−301100C
−601010A
−9010008
−12001106
G
s
(dB)
DATA
D5
SW5 D4
SW4 D3
SW3 D2
SW2 HEX
1411113C
12111038
10110134
8110030
610112C
4101028
2100124
0100020
−201111C
−4011018
−6010114
−8010010
−1000110C
−12001008
−14000104
Mute 000000
Table 12 Selector setting in register CON1
Note
1. Input connected to outputs SOR and SOL.
Table 13 SUR bit setting in register CON1
Table 14 LOFF bit setting in register CON1
Table 15 AVLON bit setting in register CON1
FUNCTION(1) DATA
D2
SC2 D1
SC1 D0
SC0
Inputs LOR and LOL 0 0 0
Inputs LOR and LOR 0 0 1
Inputs LOL and LOL 0 1 0
Inputs LOL and LOR 0 1 1
Inputs LIR and LIL 1 0 0
Inputs LIR and LIR 1 0 1
Inputs LIL and LIL 1 1 0
Inputs LIL and LIR 1 1 1
FUNCTION DATA D3
Surround sound 1
Subwoofer 0
CHARACTERISTIC DATA D5
With loudness 0
Linear 1
FUNCTION DATA D6
Automatic volume control off 0
Automatic volume control on 1
1997 Nov 04 29
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Table 16 Mute setting in register CON1
Table 17 Mute setting in register CON2
Table 18 Effects setting in register CON2
Table 19 Zero-crossing detection setting in register CON2
Table 20 Zero-crossing detection setting in register CON2
FUNCTION DATA D7
GMU
Forced mute at OUTR, OUTL and OUTS 1
Audio processor controlled outputs 0
FUNCTION DATA D3
LMU
Forced mute at LOR and LOL 1
Stereo processor controlled outputs 0
FUNCTION DATA
D2
EF2 D1
EF1 D0
EF0
Stereo linear on 000
Pseudo on 001
Spatial stereo; 30% anti-phase crosstalk 0 1 0
Spatial stereo; 50% anti-phase crosstalk 0 1 1
Forced mono 1 1 1
FUNCTION DATA D5
TZCM
Direct mute control 0
Mute control delayed until the next zero-crossing 1
FUNCTION DATA D4
VZCM
Direct volume control 0
Volume control delayed until the next zero-crossing 1
1997 Nov 04 30
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Table 21 Switch setting at line out
Table 22 Input level adjust setting in register CON3
LINE OUT SIGNALS AT DATA
TRANSMISSION STATUS
INTERNAL SWITCH, READABLE BITS IN
REGISTER ALR1, ALR2: D6 (SAPP), D5 (STP)
SETTING BITS IN
REGISTER CON2
LOL LOR D7
SAP D6
STEREO
SAP SAP SAP received 1 1
Mute mute no SAP received 1 1
Left right STEREO received 0 1
Mono mono no STEREO received 0 1
Mono SAP SAP received 1 0
Mono mute no SAP received 1 0
Mono mono independent 0 0
Gl
(dB)
DATA
D3
L3 D2
L2 D1
L1 D0
L0 HEX
4.011110F
3.511100E
3.011010D
2.511000C
2.010110B
1.510100A
1.0100109
0.5100008
0011107
−0.5011006
−1.0010105
−1.5010004
−2.0001103
−2.5001002
−3.0000101
−3.5000000
1997 Nov 04 31
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Table 23 Alignment data for expander in read register ALR1 and ALR2 and in write register ALI1 and ALI2
Table 24 STS bit setting in register ALI2 (pilot threshold stereo on)
FUNCTION DATA
D4
AX4 D3
AX3 D2
AX2 D1
AX1 D0
AX0
Gain increase 11111
11110
11101
11100
11011
11010
11001
11000
10111
10110
10101
10100
10011
10010
10001
Nominal gain 10000
01111
Gain decrease 01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
FUNCTION DATA D7
STon(rms) ≤35 mV 1
STon(rms) ≤30 mV 0
1997 Nov 04 32
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Table 25 Timing current setting in register ALI3
Table 26 AVL attack time setting in register ALI3
IS RANGE DATA
D2
TC2 D1
TC1 D0
TC0
+30% 1 0 0
+20% 1 0 1
+10% 1 1 0
Nominal 0 1 1
−10% 0 1 0
−20% 0 0 1
−30% 0 0 0
Ratt
(Ω)
DATA
D6
AT1 D5
AT2
420 0 0
730 1 0
1200 0 1
2100 1 1
Table 27 ADJ bit setting in register ALI3
FUNCTION DATA D7
Stereo decoder operation mode 0
Auto adjustment of channel separation 1
Fig.4 Automatic volume level control diagram.
AVL measured at pin EOL/EOR.
Y1 axis output level in AVL operation with typically 200 mV.
Y2 axis VCAV DC voltage at pin CAV corresponds with typical gain steps in range of +6 to −15 dB.
(1) VCAV
(2) Vo max(rms)
(3) Vo min(rms)
handbook, full pagewidth
MHA312
10
7
VCAV
(V)
6
5
4
3
2
1
1VI(rms) (V)
10−1
300
250
200
160
10−2
100
Vo(rms)
(mV) (1)
(2)
(3)
1997 Nov 04 33
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Table 28 Explanation of curves in Fig.5
CURVE CAPACITANCE AT PIN CPS1
(nF) CAPACITANCE AT PIN CPS2
(nF) EFFECT
1 15 15 normal
2 5.6 47 intensified
3 5.6 68 more intensified
Fig.5 Pseudo (phase in degrees) as a function of frequency (left output).
(1) see Table 28.
(2) see Table 28.
(3) see Table 28.
handbook, full pagewidth
−400
0
(1)
(2)
(3)
phase
(degree)
−300
−200
−100
MHA311
102103104f (Hz) 105
10
1997 Nov 04 34
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Fig.6 Volume control with loudness (including low roll-off frequency).
handbook, full pagewidth
−35
MHA844
10 102
20 103104
−25
−15
−5
5
15
25
Gc
(dB)
f (Hz)
16
14
9
4
−1
−6
−11
−16
−21
−26
−31
−36
parameter: volume gain setting (dB)
Fig.7 Bass control.
handbook, full pagewidth
−15
Gbass
(dB)
f (Hz)
MHA843
10 20 102103104
−12
−9
−6
−3
0
3
6
9
12
15
18
21
1997 Nov 04 35
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Fig.8 Treble control.
handbook, full pagewidth
15
12
MHA845
102200 103104105
9
6
3
0
−3
−6
−9
−12
−15
Gtreble
(dB)
f (Hz)
Fig.9 Noise as function of gain in dBA (RMS value).
handbook, halfpage
−80
60
40
20
0−60 20−40 −20 0
MHA842
gain (dBA)
noise
(µV)
1997 Nov 04 36
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Fig.10 Level diagram.
handbook, full pagewidth
POWER
STAGE
gain volume = 16 dB (Gv(max))
LIL
LIR TDA9855
G = 20 dB
P(max) = 40 W at 4 Ω
MHA841
VI = 200 mV; AVL off
or
VI = 100 to 1250 mV; AVL on
VO = 1.26 V for P(max)
4 dB margin for power peaks
All values given are in RMS value.
1997 Nov 04 37
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
APPLICATION HINTS
Selection of input signals by using the zero-crossing mute mode (see Fig.11)
A selection between the internal signal path and the external input LIL/LIR produces a modulation click depending on the
difference of the signal values at the time of switching.
At t1 the maximum possible difference between signals is 7 V (p-p) and gives a large click. Using the zero-crossing
detector no modulation click is audible.
For example: The selection is enabled at t1, the microcontroller sets the zero-crossing bit (TZCM = 1) and then the mute
bit (GMU = 1) via the I2C-bus. The output signal follows the input A signal, until the next zero-crossing occurs and then
activates mute.
After a fixed delay time before t2, the microcontroller has to send the forced mute mode (TZCM = 0) and the return to the
zero-crossing mode (TZCM = 1) to be sure that mute is enabled.
The output signal remains muted until the next signal zero-crossing of input B occurs, and then follows that signal.
The delay time t2−t1 is e.g. 40 ms. The zero-crossing function is working at the lowest frequency of 40 Hz.
Fig.11 Zero-crossing function; only one channel shown.
handbook, full pagewidth
V
t
t1
4
0
−1
−2
−3
−4
1
2
3
t2
MED436
(1)
(2)
(3)
(1) Input A (internal signal).
(2) Output.
(3) Input B (external input signal).
1997 Nov 04 38
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Loudness filter calculation example
Figure 12 shows the basic loudness circuit with an
external low-pass filter application. R1 allows an
attenuation range of 21 dB while the boost is determined
by the gain stage V1. Both result in a loudness control
range of +16 to −12 dB.
Defining fref as the frequency where the level does not
change while switching loudness on/off. The external
resistor R3 for fref →∞ can be calculated as:
. With Gv=−21 dB and R1 = 33 kΩ,
R3 = 3.2 kΩ is generated.
For the low-pass filter characteristic the value of the
external capacitor C1 can be determined by setting a
specific boost for a defined frequency and referring the
gain to Gv at fref as indicated above.
For example: 3 dB boost at f = 1 kHz
Gv=G
v(ref) + 3 dB = −18 dB; f = 1 kHz and C1 = 100 nF.
If a loudness characteristic with additional high frequency
boost is desired, an additional high-pass section has to be
included in the external filter circuit as indicated in the
block diagram. A filter configuration that provides
AC coupling avoids offset voltage problems.
Figure 13 shows an example of the loudness circuit with
bass and treble boost.
R3 R1 10
Gv
20
-------
110
G
v
20
-------
–
---------------------
=
1
jωC1()
--------------------- R1 R3+()10
Gv
20
------- R3–×
110
G
v
20
-------
–
--------------------------------------------------------------
=
Fig.12 Basic loudness circuit.
handbook, halfpage
MHA838
V1
R2
R1
33 kΩ
VIX
LOX
CKVL
C1
R3
Fig.13 Loudness circuit with bass and treble boost.
handbook, halfpage
MHA839
V1
R2
R1
33 kΩ
VIX
LOX
20 kΩ
2.2 kΩ
220 nF
8.2 nF
150
nF
1997 Nov 04 39
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Fig.14 Turn-on/off power supply circuit diagram.
handbook, full pagewidth
28
6
47
301125
41
12 TDA9855
4.7
kΩ470
µF
VP+8.5 V to
oscilloscope
outputs to
oscilloscope
100
µF2 × 5 kΩ
100
µF
2 × 600 Ω
2 × 220 nF
inputs
2 × 4.7 µF
VCC
8.5 V
MHA840
Fig.15 Turn-on/off behaviour.
handbook, full pagewidth
5
10
001234
MED433
2
4
6
8
t (s)
(V)
(1)
(2)
(1) VCC.
(2) VO.
1997 Nov 04 40
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
INTERNAL PIN CONFIGURATIONS
The pin numbers refer to the SDIP-version.
Fig.16 Pin 1: treble control capacitor, left;
pin 52: treble control capacitor, right.
handbook, halfpage
MHA846
1
2.4 kΩ
4.25 V
+
+
Fig.17 Pin 2: bass control capacitor input, left;
pin 51: bass control capacitor input, right.
handbook, halfpage
2
4.25 V
3.64 kΩ
7.79 kΩ
4.25 V
+
MHA847
Fig.18 Pin 3: bass control capacitor output, left;
pin 50: bass control capacitor output, right.
handbook, halfpage
34.25 V
80 Ω
+
MHA848
Fig.19 Pin 4: output subwoofer;
pin 6: output, left channel;
pin 14: output selector, left channel;
pin 39: output selector, right channel;
pin 47: output, right channel.
handbook, halfpage
44.25 V
80 Ω
+
MHA849
1997 Nov 04 41
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Fig.20 Pin 5: MAD (I2C-bus address switch).
handbook, halfpage
MHA850
5
1.8 kΩ
+
Fig.21 Pin 7: input loudness, left; pin 46: input loudness, right.
handbook, halfpage
MHA851
74.25 V
1.33 kΩ+
Fig.22 Pin 8: input volume, left; pin 45: input volume, right.
handbook, halfpage
MHA852
84.25 V
10.58 kΩ4.8 kΩ
+
1997 Nov 04 42
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Fig.23 Pin 9: output effects, left;
pin 44: output effects, right.
handbook, halfpage
MHA853
94.25 V
15
kΩ6.8
kΩ
+
Fig.24 Pin 10: automatic volume control capacitor.
handbook, halfpage
MHA854
10
+
Fig.25 Pin 11: reference voltage 0.5VCC.
handbook, halfpage
MHA855
11
+
3.4 kΩ
3.4 kΩ
Fig.26 Pin 12: line input, left;
pin 41: line input, right.
handbook, halfpage
MHA856
12 4.25 V
20 kΩ20 kΩ
+
1997 Nov 04 43
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Fig.27 Pin 13: input automatic volume control, left;
pin 40: input automatic volume control, right.
handbook, halfpage
MHA857
1.75 kΩ
4.25 V
1
2
3
+
13
8
Fig.28 Pin 15: line output, left;
pin 38: line output, right.
handbook, halfpage
MHA858
15 4.25 V
5 kΩ
+
Fig.29 Pin 16: timing capacitor wideband for dbx;
pin 17: timing capacitor spectral for dbx.
handbook, halfpage
16
+
MHA859
Fig.30 Pin 18: capacitor wideband for dbx;
pin 19: capacitor spectral for dbx.
handbook, halfpage
MHA860
18
6 kΩ
4.25 V
+
1997 Nov 04 44
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Fig.31 Pin 20: variable emphasis out for dbx.
handbook, halfpage
MHA861
20
+
Fig.32 Pin 21: variable emphasis in for dbx.
handbook, halfpage
MHA862
21
600 Ω
+
Fig.33 Pin 22: capacitor noise reduction for dbx.
handbook, halfpage
MHA863
22
10 kΩ
4.25 V
+
Fig.34 Pin 23: capacitor mute for SAP.
handbook, halfpage
MHA864
23
+
Fig.35 Pin 24: capacitor DC decoupling for SAP.
handbook, halfpage
MHA865
24
+4.25 V
20 kΩ20 kΩ
Fig.36 Pin 26: SDA (I2C-bus data input/output).
handbook, halfpage
MHA866
26 5 V
1.8 kΩ
1997 Nov 04 45
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Fig.37 Pin 27: SCL (I2C-bus clock).
handbook, halfpage
MHA867
27
5 V
1.8 kΩ
Fig.38 Pin 28: supply voltage.
handbook, halfpage
MHA868
28 apply 8.5 V to this pin
Fig.39 Pin 29: input composite signal.
handbook, halfpage
MHA869
4.25 V
+
29
30 kΩ
Fig.40 Pin 30: smoothing capacitor for supply.
handbook, halfpage
MHA870
4.7
kΩ300 Ω
5 kΩ
+30
Fig.41 Pin 31: capacitor for pilot detector.
handbook, halfpage
MHA871
3.5 kΩ
+31 4.25 V
Fig.42 Pin 32: capacitor for pilot detector.
handbook, halfpage
MHA872
3.5
kΩ3.5
kΩ
+32 4.25 V
1997 Nov 04 46
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
Fig.43 Pin 33: capacitor for phase detector.
handbook, halfpage
MHA873
+33 4.25 V
10 kΩ10 kΩ
Fig.44 Pin 34: capacitor for filter adjust.
handbook, halfpage
MHA874
+34
Fig.45 Pin 35: ceramic resonator.
handbook, halfpage
MHA875
3 kΩ
+35
Fig.46 Pin 36: capacitor DC decoupling mono;
pin 37: capacitor DC decoupling stereo/SAP.
handbook, halfpage
MHA876
4.25 V
10 kΩ10 kΩ
+36
Fig.47 Pin 43: capacitor 1 pseudo function;
pin 42: capacitor 2 pseudo function.
handbook, halfpage
MHA877
4.25 V
15 kΩ
+43
Fig.48 Pin 49: capacitor subwoofer.
handbook, halfpage
MHA878
4.25 V
1
2
3
+
49
8
10 kΩ10 kΩ
1997 Nov 04 47
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
PACKAGE OUTLINES
UNIT b1cEe M
H
L
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm
DIMENSIONS (mm are the original dimensions)
SOT247-1 90-01-22
95-03-11
bmax.
w
ME
e1
1.3
0.8 0.53
0.40 0.32
0.23 47.9
47.1 14.0
13.7 3.2
2.8 0.181.778 15.24 15.80
15.24 17.15
15.90 1.73
5.08 0.51 4.0
MH
c(e )
1
ME
A
L
seating plane
A1
wM
b1
D
A2
Z
52
1
27
26
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
(1) (1)
D(1)
Z
e
A
max. 12
A
min. A
max.
SDIP52: plastic shrink dual in-line package; 52 leads (600 mil) SOT247-1
1997 Nov 04 48
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
Note
1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.
SOT188-2
4460
68
1
9
10 26
43
27
61
detail X
(A )
3
bp
wM
A1
AA4
Lp
b1
βk1
k
X
y
e
E
B
D
H
E
H
vMB
D
ZD
A
ZE
e
vMA
pin 1 index
112E10 MO-047AC
0 5 10 mm
scale
92-11-17
95-03-11
PLCC68: plastic leaded chip carrier; 68 leads SOT188-2
UNIT A A
min. max. max. max. max.
1A4bpE(1) (1) (1)
eH
EZ
ywv β
mm 4.57
4.19 0.51 3.30 0.53
0.33
0.021
0.013
1.27 0.51 2.16 45o
0.18 0.100.18
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
D(1)
24.33
24.13
HD
25.27
25.02
E
Z
2.16
D
b1
0.81
0.66
k
1.22
1.07
k1
0.180
0.165 0.020 0.13
A3
0.25
0.01 0.05 0.020 0.085
0.007 0.0040.007
Lp
1.44
1.02
0.057
0.040
0.958
0.950
24.33
24.13
0.958
0.950 0.995
0.985
25.27
25.02
0.995
0.985
eE
eD
23.62
22.61
0.930
0.890
23.62
22.61
0.930
0.890 0.085
0.032
0.026 0.048
0.042
E
e
inches
D
e
1997 Nov 04 49
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“IC Package Databook”
(order code 9398 652 90011).
SDIP
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
PLCC
REFLOW SOLDERING
Reflow soldering techniques are suitable for all PLCC
packages.
The choice of heating method may be influenced by larger
PLCC packages (44 leads, or more). If infrared or vapour
phase heating is used and the large packages are not
absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our
“Quality
Reference Handbook”
(order code 9398 510 63011).
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
WAVE SOLDERING
Wave soldering techniques can be used for all PLCC
packages if the following conditions are observed:
•A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
•The longitudinal axis of the package footprint must be
parallel to the solder flow.
•The package footprint must incorporate solder thieves at
the downstream corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
1997 Nov 04 50
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Nov 04 51
Philips Semiconductors Product specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor TDA9855
NOTES
Internet: http://www.semiconductors.philips.com
Philips Semiconductors – a worldwide company
© Philips Electronics N.V. 1997 SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
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Tel. +31 40 27 82785, Fax. +31 40 27 88399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494
South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 829 1849
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 3 301 6312, Fax. +34 3 301 4107
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 632 2000, Fax. +46 8 632 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2686, Fax. +41 1 481 7730
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010,
Fax. +43 160 101 1210
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773
Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 0044
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580920
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240
Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Middle East: see Italy
Printed in The Netherlands 547047/1200/03/pp52 Date of release: 1997 Nov 04 Document order number: 9397 750 02446
