TAS-Si2k Lar 512K x 8 SRAM DIL.M Syntaq SYS8512FK-85/10/12/15 524,286 x 8 CMOS Static RAM Module Issue 1.7 : JUNE 1994 Features ~~ Description Access Times of 85 32 Pin 0.6" Dual-In-Line package with The SYS8512FK is plastic 4M Static RAM Module housed in a standard 32 pin Dual-In-Line package organised as 51 2K x8. The module utilises SRAMSs JEDEC compatible pinout. housed in SOP packages, and uses double sided 5 Volt Supply + 10%. surface mounttechniques, buried decoder and dual Ce Low Power Dissipation: board construction to achieve a very high density module. The module has Chip Select, Write Enable and Output Enable control inputs; the Output Enabie pin allows faster access times than address access | during a Read Cycle. Average (min cycle) 605mW (maximum). Standby (CMOS) 44 mW (maximum). Completely Static Operation. * Equal Access and Cycie Times. All inputs and Outputs Directly TTL Compatible. e On-board Supply Decoupling Capacitors. _) parce Pin Functions Address Inputs AO -A18 Data Input/Output DO - D7 Chip Select Input cs Read/Write input = WE Output Enable Input OE Power (+5V) Ve Ground GND Block Diagram * 00-7 WE | | OE || [| | TOBK x8 | [128K x8] | 128K xs) | 126K x SRAM SRAM SRAM SRAM a Ais | cs 4s L eee Operation Truth Table m BMY be agit gh Os a * 8 cs | OF WE DATA PINS SUPPLY CURRENT | MODE H | x xX High Impedance Ispi. spe | Standby cr jot H Data Out loos loce Read Lc foe L Data In leer s loce Write L | H L Data In lec1 lee Write Notes: H=Vin : L=Vn : X = Vin OF VitISSUE 17 JUNE 1994 SYS8512FK-B5/10/12/15 (Absolute Maximum Ratings) po] Voltage on any pin relative to V.. V, -0.5V to+7 V Power Dissipation P, 1 Ww Storage Temperature Tere 755 to +150 C Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (2) V, can be -3.5V pulse of less than 20ns. OTP Te eae OF age oR ge hy BE ES [Recommended Operating Conditions, ne | min | max | | Supply Voltage Voc 4.5 5.5 Vv Input High Voltage Vi 2.2 - 0.6 Vv Input Low Voltage Vy 03 - 0.8 V Operating Temperature T, 0 - 70 C T,, 40 - 85 C (I) DC Electrical Charactoristios i650. Y:2%) Voo=5V+/-10%, Ta=0 to 700 Parameter iSym Test Condition min | typ: max | Uni /P Leakage Current AO~A16,OE) |, OV-Viy- Voc - - | +8 | pA | Output Leakage Current = DO~D7> I. i TB = Viz, Vio= GND 10 Voc - - , #8] UA Operating Supply Current log | CSS Vy slg = OMA, Vy - Vay = Voo72-1V - 18 | 36 | mA Average Supply Current TTL levels 1... | Min. Cycle, CS = Vy. Viy = Va Moer2- AV : 60 | 90 | mA CMOS levels! Icc2 Min Cycle CS-0.2V Vin=0.2V/Vec-0.2 - | 24 | 40) mA Standby Supply Current TTL levels; !,, TS = Voo-2.1V, Vi > Viv = Voor 1V - 5 | 12 | mA\- CMOS levels | log, | C5 = Vocr0.2V, 0.2 = Va," Vggr0.2V - /02 | 8| mA -L Part) |,,, | As above - 10 | 500) pA -P Part| |,,, | As above - 10 | 300 | pA Output Voltage Vo ily =2-1mA . - | 04) V Voy | low = 21.0mA 2.4 -| -|v Typical values are at V,.=5.0V,T,=25C and specified loading. Capacitance calculated, not measured Unit Parameter | iP vO Test Condition V..= OV Vi = OV V_.= OV Symbol! max nce (CS, A17, A18 citance (other citance * Input pulse levels: OV to 3.0V VOPin . 645 * Input rise and fall times: S5ns mane * Input and Output timing reference levels: 1.5V 100pF 1-76V * Output load: see diagram *V,,=5V210% 1SYS8512FK-85/10/12/15 ISSUE 17 JUNE 1994 Electrical Characteristics &:Recammended, AC Operating Conditions: -12 15 Parameter Sym | min max | min max | min = max| min max) Unit Read Cycle Time t. | 85 - |100 - (120 - |150 -|ns Address Access Time tas - 85 | - 100 - 120 - 150 | ns Chip Select Access Time tacos - 85 ' - 100 - 120 - 150 | ns Output Enable to Output Valid ty, - 55 - 60 - 70 - _ 85 | ns Output Hold from Address Change |t,,, 10 - 10 - 10 : 10 - | ns Chip Selection to Outputin LowZ it,,@ | 10 - 10 - 10 ve] 10 - | ns Output Enable to Output in LowZ /t,, @ 5 - 5 - 5 - 5 - | ns Chip Deselection to O/P in HighZ [t.,, @ 0 30 0 35 a) 0 55 ons Output Disable to Output in High Z't. @ 0 30: 0 35 | 0 45 0 55 _ ons Notes (1) WE is High for Read Cycle. 2) t,, and t,, are defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. These parameters are sampled and not 100% tested. (Read Cycie Timing Waveform? = . tre Address x xX t AA OE \ / \ ZL toe ton \ tow - / cs ; A LZ . lacs J t ouz . touz Dout Data Valid t cuzISSUE 17 JUNE 1994 SYS8512FK-85/10/12/15 cose any Reg en Lem H 3, e 12. | 15 Parameter min max | min max; Unit Write Cycie Time 120 - 150 - | ns Chip Selection to Endof Write | ty, 80 - 90 - | 100 - 110 - | ns Address Valid to End of Write | taw 80 - 90 - | 100 - 1110 -_ ns Address Setup Time tac 0 - 0 - 0 - . 0 - ins Write Pulse Width twp 65 - | 75 - | 85 - | 95 - | ns Write Recovery Time twa 5 - 5 - 10 - | 15 - | ns Write to Output in High Z tw? 0 30 0 35 QO =40 0 45 | ns Data to Write Time Overlap tow 35 - | 40 - | 45 - | 50 - | ns Data Hold from Write Time arn) - 0 - ) - | 0 - | ns Output active from end ofwrite | ty, 5 - 5 - 5 - | 5 - | ns Address OE Dout Din rr cle No? Yi Address Dout Din (9)SYS8512FK-85/10/12/15 ISSUE 17 JUNE 1994 (C-Characteristics Notes (1) A write occurs during the overlap (he) ) of alow CS and z a low WE. (2) t,, is measured from the earlier of CS or WE going high to the end of write cycle. 3) t,, S Measured from the address valid to the beginning of write. ) ) ( (4 t Is measured from the earliest of CS or WE | going high to the end of write. (5) During this period, I/O pins are in the output state. Input signals out of phase must not be applied. (6) if CS goes low simultaneously with WE going low or after WE going low , outputs remain in a high impedance state. (7) Dou, is in the same phase as written data of this write cycle. (8) Dy, is the read data of next address. (9) If CS is low during this period, I/O pins are in the output state, and inputs out of phase must not be applied to I/O pins 0) This parameter is sampled and not 100% tested. (1 (11) t,,, is defined as the time at which the outputs achieve open circuit conditions and is not referenced to output voltage levels. This parameter is sampled and not 100% tested. -P Part | Parameter Sym Test Condition | min typ max | min typ max | Unit V,, for Data Retention Vor CS - V,,-0.2V 2.0 - - 2.0 - - | V Data Retention Current V.,= 3.0V, CS$V,,-0.2V lecon: | Top = 0C to 40C - 9 100 - 9 15 | pA locorme | Top= Ty - 9 200 - 9 120 | pA locors | Fop= Tw - - 280 . - 200 | pA Chip Deselect to Data Retention Time toor See Retention Waveform 0 - - 0 - - | ns Operation Recovery Time | t, See Retention Waveform 5 - - 3 0 - - | ms Notes (1) Typical figures are measured at 25C. (2) This parameter is guaranteed not tested. DATA RETENTION MOD CS V 6 0.2V