DATA SH EET
Product specification
File under Integrated Circuits, IC06 September 1993
INTEGRATED CIRCUITS
74HC/HCT04
Hex inverter
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
September 1993 2
Philips Semiconductors Product specification
Hex inverter 74HC/HCT04
FEATURES
•Output capability: standard
•ICC category: SSI
GENERAL DESCRIPTION
The 74HC/HCT04 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT04 provide six inverting buffers.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr= tf= 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PDin µW):
PD= CPD ×VCC2×fi+∑(CL×VCC2×fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
Σ(CL×VCC2×fo) = sum of outputs
CL= output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC −1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPHL/ tPLH propagation delay nA to nY CL= 15 pF; VCC =5V 7 8 ns
C
Iinput capacitance 3.5 3.5 pF
CPD power dissipation capacitance per gate notes 1 and 2 21 24 pF
September 1993 3
Philips Semiconductors Product specification
Hex inverter 74HC/HCT04
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 3, 5, 9, 11, 13 1A to 6A data inputs
2, 4, 6, 8, 10, 12 1Y to 6Y data outputs
7 GND ground (0 V)
14 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
Fig.4 Functional diagram. Fig.5 Logic diagram
(one inverter).
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
INPUT OUTPUT
nA nY
L
HH
L
September 1993 4
Philips Semiconductors Product specification
Hex inverter 74HC/HCT04
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: SSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr= tf= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V) WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nA to nY 25
9
7
85
17
14
105
21
18
130
26
22 ns 2.0
4.5
6.0 Fig.6
tTHL/ tTLH output transition
time 19
7
6
75
15
13
95
19
16
110
22
19 ns 2.0
4.5
6.0 Fig.6
September 1993 5
Philips Semiconductors Product specification
Hex inverter 74HC/HCT04
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: SSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per unit, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr= tf= 6 ns; CL= 50 pF
AC WAVEFORMS
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
INPUT UNIT LOAD COEFFICIENT
nA 1.20
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nA to nY 10 19 24 29 ns 4.5 Fig.6
tTHL/ tTLH output transition
time 7 15 19 22 ns 4.5 Fig.6
Fig.6 Waveforms showing the data input (nA) to data output (nY) propagation delays and the output transition
times.
(1) HC : VM= 50%; VI= GND to VCC
HCT: VM= 1.3 V; VI= GND to 3 V
