PIC16F1824-I/P - MICROCHIP TECHNOLOGY

 2010-2011 Microchip Technology Inc. Preliminary DS41419C

PIC16(L)F1824/1828

Data Sheet

14/20-Pin Flash Microcontrollers with

nanoWatt Technology

DS41419C-page 2 Preliminary  2010-2011 Microchip Technology Inc.

Information contained in this publication regarding device

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and may be superseded by updates. It is your responsibility to

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intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

PIC32 logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT,

chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,

dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,

FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,

Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,

MPLINK, mTouch, Omniscient Code Generation, PICC,

PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,

rfLAB, Select Mode, Total Endurance, TSHARC,

UniWinDriver, WiperLock and ZENA are trademarks of

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countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-61341-621-1

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 3

High-Performance RISC CPU:

• Only 49 Instructions to Learn:

- All single-cycle instructions except branches

• Operating Speed:

- DC – 32 MHz oscillator/clock input

- DC – 125 ns instruction cycle

• Up to 8 Kbytes Linear Program Memory

addressing

• Up to 256 bytes Linear Data Memory Addressing

• Interrupt Capability with Automatic Context

Saving

• 16-Level Deep Hardware Stack with Optional

Overflow/Underflow Reset

• Direct, Indirect and Relative Addressing modes:

- Two full 16-bit File Select Registers (FSRs)

- FSRs can read program and data memory

Flexible Oscillator Structure:

• Precision 32 MHz Internal Oscillator Block:

- Factory calibrated to ± 1%, typical

- Software selectable frequencies range of

31 kHz to 32 MHz

• 31 kHz Low-Power Internal Oscillator

• Four Crystal modes up to 32 MHz

• Three External Clock modes up to 32 MHz

• 4X Phase Lock Loop (PLL)

• Fail-Safe Clock Monitor:

- Allows for safe shutdown if peripheral clock

stops

• Two-Speed Oscillator Start-up

• Reference Clock module:

- Programmable clock output frequency and

duty-cycle

Special Microcontroller Features:

• 1.8V-5.5V operation – PIC16F1824/1828

• 1.8V-3.6V operation – PIC16LF1824/1828

• Self-Programmable under Software Control

• Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

• Programmable Brown-out Reset (BOR)

• Extended Watchdog Timer (WDT)

• In-Circuit Serial Programming™ (ICSP™) via

two pins

• In-Circuit Debug (ICD) via Two Pins

• Enhanced Low-Voltage Programming (LVP)

• Operating Voltage Range:

- 1.8V-5.5V (PIC16F1824/1828)

- 1.8V-3.6V (PIC16LF1824/1828)

• Programmable Code Protection

• Power-Saving Sleep mode

Extreme Low-Power Management

PIC16LF1824/1828 with nanoWatt XLP:

• Sleep mode: 20 nA

• Watchdog Timer: 500 nA

• Timer1 Oscillator: 600 nA @ 32 kHz

Analog Features:

• Analog-to-Digital Converter (ADC) module:

- 10-bit resolution, up to 12 channels

- Auto acquisition capability

- Conversion available during Sleep

• Analog Comparator module:

- Two rail-to-rail analog comparators

- Power mode control

- Software controllable hysteresis

• Voltage Reference module:

- Fixed Voltage Reference (FVR) with 1.024V,

2.048V and 4.096V output levels

- 5-bit rail-to-rail resistive DAC with positive

and negative reference selection

Peripheral Highlights:

• Up to 17 I/O Pins and 1 Input Only Pin:

- High current sink/source 25 mA/25 mA

- Programmable weak pull-ups

- Programmable interrupt-on-change pins

• Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

- Dedicated, low-power 32 kHz oscillator driver

• Three Timer2-types: 8-Bit Timer/Counter with 8-Bit

Period Register, Prescaler and Postscaler

• Two Capture, Compare, PWM (CCP) modules

• Two Enhanced CCP (ECCP) modules:

- Software selectable time bases

- Auto-shutdown and auto-restart

- PWM steering

• Master Synchronous Serial Port (MSSP) with SPI

and I2CTM with:

- 7-bit address masking

- SMBus/PMBusTM compatibility

• Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART) module

• mTouch™ Sensing Oscillator module:

- Up to 12 input channels

• Data Signal Modulator module:

- Selectable modulator and carrier sources

PIC16(L)F1824/1828

14/20-Pin Flash Microcontrollers with nanoWatt Technology

PIC16(L)F1824/1828

DS41419C-page 4 Preliminary  2010-2011 Microchip Technology Inc.

Peripheral Highlights (Continued):

•SR Latch:

- Multiple Set/Reset input options

- Emulates 555 Timer applications

PIC16(L)F1824/1828 Family Types

Device

Program

Memory

Data

Memory

I/O’s(1)

10-bit ADC (ch)

CapSense (ch)

Comparators

Timers (8/16-bit)

EUSART

MSSP

ECCP (Full-Bridge)

ECCP (Half-Bridge)

CCP

SR Latch

Words

SRAM

(bytes)

Data EEPROM

(bytes)

PIC16LF1824 4K 256256128824/111112Yes

PIC16F1824 4K 256 256 12 8 8 2 4/1 1 1 1 1 2 Yes

PIC16LF1828 4K 25625618121224/111112Yes

PIC16F1828 4K 256 256 18 12 12 24/1 1 1 1 1 2 Yes

Note 1: One pin is input only.

PIC16(L)F1824/1828

DS41419C-page 5 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 1: 14-PIN DIAGRAM FOR PIC16(L)F1824

PDIP, SOIC, TSSOP

PIC16(L)F1824

VDD

CCP2(1)/P2A(1)/T1CKI/T1OSI/OSC1/CLKIN/RA5

T1G(1)/P2B(1)/SDO(1)/CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4

MCLR/VPP/T1G(1)/SS(1)/RA3

MDCIN2/DT(1)/RX(1)/CCP1/P1A/RC5

MDOUT/CK(1)/TX(1)/P1B/SRNQ/C2OUT/RC4

MDMIN/SS(1)/P1C(1)/CCP2(1)/P2A(1)/C12IN3-/CPS7/AN7/RC3

VSS

RA0/AN0/CPS0/C1IN+/VREF-/DACOUT/TX(1)/CK(1)/ICSPDAT

RA1/AN1/CPS1/C12IN0-/VREF+/SRI/RX(1)/DT(1)/ICSPCLK

RA2/AN2/CPS2/T0CKI/INT/C1OUT/SRQ/CCP3/FLT0

RC0/AN4/CPS4/C2IN+/SCL/SCK/P1D(1)

RC1/AN5/CPS5/C12IN1-/SDA/SDI/P1C(1)/CCP4

RC2/AN6/CPS6/C12IN2-/P1D(1)/P2B(1)/SDO(1)/MDCIN1

Note 1: Pin function is selectable via the APFCON0 or APFCON1 registers.

PIC16(L)F1824/1828

DS41419C-page 6 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 2: 16-PIN DIAGRAM FOR PIC16(L)F1824

PIC16(L)F1824

VDD

VSS

CCP2(1)/P2A(1)/T1CKI/T1OSI/OSC1/CLKIN/RA5

T1G(1)/P2B(1)/SDO(1)/CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4

MCLR/VPP/T1G(1)/SS(1)/RA3

MDCIN2/DT(1)/RX(1)/CCP1/P1A/RC5

RA0/AN0/CPS0/C1IN+/VREF-/DACOUT/TX(1)/CK(1)/ICSPDAT/ICDDAT

RA1/AN1/CPS1/C12IN0-/VREF+/SRI/RX(1)/DT(1)/ICSPCLK/ICDCLK

RA2/AN2/CPS2/T0CKI/INT/C1OUT/SRQ/CCP3//FLT0

RC0/AN4/CPS4/C2IN+/SCL/SCK/P1D(1)

RC4/C2OUT/SRNQ/P1B/TX(1)/CK(1)/MDOUT

RC3/AN7/CPS7/C12IN3-/P2A(1)/CCP2(1)/P1C(1)/MDMIN/SS(1)

RC2/AN6/CPS6/C12IN2-/P1D(1)/P2B(1)/SDO(1)/MDCIN1

RC1/AN5/CPS5/C12IN1-/SDA/SDI/P1C(1)/CCP4

QFN

Note 1: Pin function is selectable via the APFCON0 or APFCON1 registers.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 7

PIC16(L)F1824/1828

TABLE 1: 14-PIN AND 16-PIN ALLOCATION TABLE (PIC16(L)F1824)

I/O

14-Pin PDIP/SOIC/TSSOP

16-Pin QFN

A/D

Reference

Cap Sense

Comparator

SR Latch

Timers

ECCP

EUSART

MSSP

Interrupt

Modulator

Pull-up

Basic

RA0 13 12 AN0 VREF-

DACOUT

CPS0 C1IN+ — — — TX(1)

CK(1) —IOC — Y ICSPDAT

ICDDAT

RA1 12 11 AN1 VREF+ CPS1 C12IN0- SRI — — RX(1)

DT(1) — IOC — Y ICSPCLK

ICDCLK

RA2 11 10 AN2 —CPS2 C1OUT SRQ T0CKI CCP3

FLT0

— — INT/

IOC

— Y —

RA3 4 3 — — — — — T1G(1) ——

SS(1) IOC — Y MCLR

VPP

RA4 3 2 AN3 —CPS3 — — T1G(1)

T1OSO

P2B(1) —SDO(1) IOC — Y OSC2

CLKOUT

CLKR

RA5 2 1 — — — — — T1CKI

T1OSI

CCP2

P2A(1) ——IOC—YOSC1

CLKIN

RC0 10 9AN4 —CPS4 C2IN+ — — P1D(1) —SCL

SCK

— — Y —

RC1 9 8 AN5 — CPS5 C12IN1- — — CCP4

P1C(1) —SDA

SDI

——Y—

RC2 8 7 AN6 —CPS6 C12IN2- — — P1D(1)

P2B(1) —SDO(1) —MDCIN1 Y —

RC3 7 6 AN7 — CPS7 C12IN3- — — CCP2(1)

P1C(1)

P2A(1)

—SS

(1) —MDMINY —

RC4 6 5 — — — C2OUT SRNQ —P1B TX(1)

CK(1) — — MDOUT Y —

RC5 5 4 — — — — — — CCP1

P1A

RX(1)

DT(1) — — MDCIN2 Y —

VDD 116 — — — — — — — — — — — — VDD

VSS 14 13 — — — — — — — — — — — — VSS

Note 1: Pin function is selectable via the APFCON0 or APFCON1 registers.

PIC16(L)F1824/1828

DS41419C-page 8 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 3: 20-PIN DIAGRAM FOR PIC16(L)F1828

PDIP, SOIC, SSOP

PIC16(L)F1828

VDD

CCP2(1)/P2A(1)/T1CKI/T1OSI/OSC1/CLKIN/RA5

T1G(1)/P2B(1)/CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4

MCLR/VPP/T1G(1)/RA3

MDCIN2/DT(1)/RX(1)/P1A/CCP1/RC5

MDOUT/CK(1)/TX(1)/P1B/SRNQ/C2OUT/RC4

MDMIN/P2A(1)/CCP2(1)/P1C(1)/C12IN3-/CPS7/AN7/RC3

VSS

RA0/AN0/CPS0/C1IN+/VREF-/DACOUT/ICSPDAT/ICDDAT

RA1/AN1/CPS1/C12IN0-/VREF+/SRI/ICSPCLK/ICDCLK

RA2/AN2/CPS2/T0CKI/INT/C1OUT/SRQ/CCP3/FLT0

RC0/AN4/CPS4/C2IN+/P1D(1)

RC2/AN6/CPS6/C12IN2-/P1D(1)/P2B(1)/MDCIN1

SS/CCP4/CPS8/AN8/RC6

SDO/CPS9/AN9/RC7

CK(1)/TX(1)/RB7

RB4/AN10/CPS10/SDA1/SDI1

RB5/AN11/CPS11/RX(1)/DT(1)

RB6/SCL1/SCK1

RC1/AN5/CPS5/C12IN1-/P1C(1)

Note 1: Pin function is selectable via the APFCON0 or APFCON1 registers.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 9

PIC16(L)F1824/1828

FIGURE 4: PIC16(L)F1828 20-PIN QFN

16 10

MCLR/VPP/T1G(1)/RA3

RC7/AN9/CPS9/SDO

RB7/TX(1)/CK(1)

RB4/AN10/CPS10/SDA1/SDI1

RB5/AN11/CPS11/RX(1)/DT(1)

RB6/SCL1/SCK1

RC1/AN5/CPS5/C12IN1-/P1C(1)

RC0/AN4/CPS4/C2IN+/P1D(1)

RA2/AN2/CPS2/T0CKI/INT/C1OUT/SRQ/CCP3/FLT0

Vss

VDD

T1G(1)/P2B(1)/CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4

QFN

CCP2(1)/P2A(1)/T1CKI/T1OS1/OSC1/CLKIN/RA5

RA1/AN1/CPS1/C12IN0-/VREF+/SRI/ICSPCLK/ICDCLK

PIC16(L)F1828

RC2/AN6/CPS6/C12IN2-/P1D(1)/P2B(1)/MDCIN1

Note 1: Pin function is selectable via the APFCON0 or APFCON1 registers.

MDMIN/P2A(1)/CCP2(1)/P1C(1)/C12IN3-/CPS7/AN7/RC3

MDOUT/CK(1)/TX(1)/P1B/SRNQ/C2OUT/RC4

MDCIN2/DT(1)/RX(1)/P1A/CCP1/RC5

SS/CCP4/CPS8/AN8/RC6

ICDDAT/ICSPDAT/DACOUT/VREF-/C1IN+/CPS0/AN0/RA0

PIC16(L)F1824/1828

DS41419C-page 10 Preliminary  2010-2011 Microchip Technology Inc.

TABLE 2: 20-PIN ALLOCATION TABLE (PIC16(L)F1828)

I/O

20-Pin DIP/SOIC/SSOP

20-Pin QFN

A/D

Reference

Cap Sense

Comparator

SR Latch

Timers

CCP

EUSART

SSP

Interrupt

Modulator

Pull-up

Basic

RA0 19 16 AN0 VREF-

DACOUT

CPS0 C1IN+ — — — — — IOC — Y ICSPDAT/

ICDDAT

RA1 18 15 AN1 VREF+CPS1 C12IN0- SRI — — — — IOC — Y ICSPCLK/

ICDCLK

RA2 17 14 AN2 —CPS2 C1OUT SRQ T0CKI CCP3

FLT0

— — INT/

IOC

— Y —

RA3 4 1 — — — — T1G(1) — — — IOC — Y(4) MCLR

VPP

RA4 320 AN3 —CPS3 — — T1G(1)

T1OSO

P2B(1) ——IOC — Y OSC2

CLKOUT

CLKR

RA5 219 — — — — — T1CKI

T1OSI

CCP2(1)

P2A(1) — — IOC — Y OSC1

CLKIN

RB4 13 10 AN10 —CPS10 — — — — SDA1

SDI1

IOC — Y —

RB5 12 9AN11 —CPS11 — — — — RX(1)

DT(1) —IOC — Y —

RB6 11 8 — — — — — — — — SCL1

SCK1

IOC — Y —

RB7 10 7 — — — — — — — TX(1)

CK(1) —IOC — Y —

RC0 16 13 AN4 —CPS4 C2IN+ — — P1D(1) ——— — Y —

RC1 15 12 AN5 —CPS5 C12IN1- ——P1C

(1) — — — — Y —

RC2 14 11 AN6 —CPS6 C12IN2- — — P1D(1)

P2B(1) — — — MDCIN1 Y —

RC3 7 4 AN7 —CPS7 C12IN3- — — P1C(1)

CCP2(1)

P2A(1)

— — —MDMIN Y —

RC4 6 3 — — — C2OUT SRNQ —P1B TX(1)

CK(1) — — MDOUT Y —

RC5 5 2 — — — — — — CCP1

P1A

RX(1)

DT(1) —— MDCIN2 Y —

RC6 8 5 AN8 —CPS8 — — — CCP4 —SS — — Y —

RC7 9 6 AN9 —CPS9 — — — — — SDO — — Y —

VDD 118 — — — — — — — — — — — — VDD

Vss 20 17 — — — — — — — — — — — — VSS

Note 1: Pin function is selectable via the APFCON0 or APFCON1 registers.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 11

PIC16(L)F1824/1828

Table of Contents

1.0 Device Overview ........................................................................................................................................................................ 13

2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 21

3.0 Memory Organization ................................................................................................................................................................. 23

4.0 Device Configuration.................................................................................................................................................................. 51

5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 57

6.0 Reference Clock Module ............................................................................................................................................................ 75

7.0 Resets ........................................................................................................................................................................................ 79

8.0 Interrupts .................................................................................................................................................................................... 87

9.0 Power-Down Mode (Sleep) ...................................................................................................................................................... 101

10.0 Watchdog Timer (WDT) ........................................................................................................................................................... 103

11.0 Data EEPROM and Flash Program Memory Control ............................................................................................................... 107

12.0 I/O Ports ................................................................................................................................................................................... 121

13.0 Interrupt-on-Change ................................................................................................................................................................. 141

14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 145

15.0 Temperature Indicator Module ................................................................................................................................................. 147

16.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 149

17.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 163

18.0 SR Latch................................................................................................................................................................................... 169

19.0 Comparator Module.................................................................................................................................................................. 175

20.0 Timer0 Module ......................................................................................................................................................................... 185

21.0 Timer1 Module ......................................................................................................................................................................... 189

22.0 Timer2/4/6 Modules.................................................................................................................................................................. 201

23.0 Data Signal Modulator (DSM) .................................................................................................................................................. 205

24.0 Capture/Compare/PWM Module .............................................................................................................................................. 215

25.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 243

26.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 297

27.0 Capacitive Sensing Module...................................................................................................................................................... 325

28.0 In-Circuit Serial Programming™ (ICSP™) ................................................................................................................................ 333

29.0 Instruction Set Summary.......................................................................................................................................................... 337

30.0 Electrical Specifications............................................................................................................................................................ 351

31.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 383

32.0 Development Support............................................................................................................................................................... 385

33.0 Packaging Information.............................................................................................................................................................. 389

Appendix A: Revision History............................................................................................................................................................. 409

Appendix B: Device Differences ........................................................................................................................................................ 409

Index .................................................................................................................................................................................................. 411

The Microchip Web Site..................................................................................................................................................................... 419

Customer Change Notification Service .............................................................................................................................................. 419

Customer Support .............................................................................................................................................................................. 419

Reader Response .............................................................................................................................................................................. 420

Product Identification System ............................................................................................................................................................ 421

PIC16(L)F1824/1828

DS41419C-page 12 Preliminary  2010-2011 Microchip Technology Inc.

TO OUR VALUED CUSTOMERS

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To determine if an errata sheet exists for a particular device, please check with one of the following:

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Customer Notification System

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 13

PIC16(L)F1824/1828

1.0 DEVICE OVERVIEW

The PIC16(L)F1824/1828 are described within this data

sheet. They are available in 14/20 pin packages.

Figure 1-1 shows a block diagram of the

PIC16(L)F1824/1828 devices. Tables 1-2 and 1-3 show

the pinout descriptions.

Reference Table 1 -1 for peripherals available per

device.

TABLE 1-1: DEVICE PERIPHERAL

SUMMARY

Peripheral

PIC16(L)F1824

PIC16(L)F1828

ADC ●●

Capacitive Sensing Module (CSM) ●●

Data EEPROM ●●

Digital-to-Analog Converter (DAC) ●●

Digital Signal Modulator (DSM) ●●

EUSART ●●

Fixed Voltage Reference (FVR) ●●

SR Latch ●●

Capture/Compare/PWM Modules

ECCP1 ●●

ECCP2 ●●

CCP3 ●●

CCP4 ●●

Comparators

C1 ●●

C2 ●●

Master Synchronous Serial Ports

MSSP ●●

Timers

Timer0 ●●

Timer1 ●●

Timer2 ●●

Timer4 ●●

Timer6 ●●

PIC16(L)F1824/1828

DS41419C-page 14 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 1-1: PIC16(L)F1824/1828 BLOCK DIAGRAM

PORTB(3)

PORTC

Note 1: See applicable chapters for more information on peripherals.

2: See Ta b le 1 - 1 for peripherals available on specific devices.

3: PIC16(L)F1828 only.

CPU

Program

Flash Memory

EEPROM

RAM

Timing

Generation

INTRC

Oscillator

MCLR

(Figure 2-1)

Clock

CLKR

Reference

OSC1/CLKIN

OSC2/CLKOUT

EUSART

Comparators

MSSP

Timer2Timer1 Timer4Timer0

ECCP1

ADC

10-Bit

ECCP2 CCP3 CCP4

Timer6

Latch

PORTA

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 15

PIC16(L)F1824/1828

TABLE 1-2: PIC16(L)F1824 PINOUT DESCRIPTION

Name Function Input

Type

Output

Type Description

RA0/AN0/CPS0/C1IN+/VREF-/

DACOUT/TX(1)/CK(1)/

ICSPDAT/ICDDAT

RA0 TTL CMOS General purpose I/O.

AN0 AN — A/D Channel 0 input.

CPS0 AN — Capacitive sensing input 0.

C1IN+ AN — Comparator C1 positive input.

VREF- AN — A/D and DAC Negative Voltage Reference input.

DACOUT — AN Digital-to-Analog Converter output.

TX — CMOS USART asynchronous transmit.

CK ST CMOS USART synchronous clock.

ICSPDAT ST CMOS ICSP™ Data I/O.

ICDDAT ST CMOS In-Circuit Data I/O.

RA1/AN1/CPS1/C12IN0-/VREF+/

SRI/RX(1)/DT(1)/ICSPCLK/

ICDCLK

RA1 TTL CMOS General purpose I/O.

AN1 AN — A/D Channel 1 input.

CPS1 AN — Capacitive sensing input 1.

C12IN0- AN — Comparator C1 or C2 negative input.

VREF+ AN — A/D and DAC Positive Voltage Reference input.

SRI ST — SR latch input.

RX ST — USART asynchronous input.

DT ST CMOS USART synchronous data.

ICSPCLK ST — Serial Programming Clock.

ICDCLK ST — In-Circuit Debug Clock.

RA2/AN2/CPS2/T0CKI/INT/

C1OUT/SRQ/CCP3/FLT0

RA2 TTL CMOS General purpose I/O.

AN2 AN — A/D Channel 2 input.

CPS2 AN — Capacitive sensing input 2.

T0CKI ST — Timer0 clock input.

INT ST — External interrupt.

C1OUT — CMOS Comparator C1 output.

SRQ — CMOS SR latch non-inverting output.

CCP3 ST CMOS Capture/Compare/PWM 3.

FLT0 ST — ECCP Auto-Shutdown Fault input.

RA3/SS(1)/T1G(1)/VPP/MCLR RA3 TTL — General purpose input.

SS ST — Slave Select input.

T1G ST — Timer1 Gate input.

VPP HV — Programming voltage.

MCLR ST — Master Clear with internal pull-up.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C

HV = High Voltage XTAL = Crystal levels

Note 1: Pin functions can be moved using the APFCONO and APFCON1 registers (Register 12-1 and Register 12-2).

2: Default function location.

PIC16(L)F1824/1828

DS41419C-page 16 Preliminary  2010-2011 Microchip Technology Inc.

RA4/AN3/CPS3/OSC2/

CLKOUT/T1OSO/CLKR/

SDO(1)/P2B(1)/T1G(1,2)

RA4 TTL CMOS General purpose I/O.

AN3 AN — A/D Channel 3 input.

CPS3 AN — Capacitive sensing input 3.

OSC2 — CMOS Comparator C2 output.

CLKOUT — CMOS FOSC/4 output.

T1OSO XTAL XTAL Timer1 oscillator connection.

CLKR — CMOS Clock Reference output.

SDO — CMOS SPI data output.

P2B — CMOS PWM output.

T1G ST — Timer1 Gate input.

RA5/CLKIN/OSC1/T1OSI/

T1CKI/P2A(1)/CCP2(1)

RA5 TTL CMOS General purpose I/O.

CLKIN CMOS — External clock input (EC mode).

OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).

T1OSI XTAL XTAL Timer1 oscillator connection.

T1CKI ST — Timer1 clock input.

P2A — CMOS PWM output.

CCP2 ST CMOS Capture/Compare/PWM 2.

RC0/AN4/CPS4/C2IN+/SCL/

SCK/P1D(1)

RC0 TTL CMOS General purpose I/O.

AN4 AN — A/D Channel 4 input.

CPS4 AN — Capacitive sensing input 4.

C2IN+ AN — Comparator C2 positive input.

SCL I2CODI

2C™ clock.

SCK ST CMOS SPI clock.

P1D — CMOS PWM output.

RC1/AN5/CPS5/C12IN1-/SDA/

SDI/P1C(1)/CCP4

RC1 TTL CMOS General purpose I/O.

AN5 AN — A/D Channel 5 input.

CPS5 AN — Capacitive sensing input 5.

C12IN1- AN — Comparator C1 or C2 negative input.

SDA I2CODI

2C data input/output.

SDI CMOS — SPI data input.

P1C — CMOS PWM output.

CCP4 AN — Capacitive sensing input 4.

RC2/AN6/CPS6/C12IN2-/

P1D(1,2)/P2B(1,2)/SDO(1,2)/

MDCIN1

RC2 TTL CMOS General purpose I/O.

AN6 AN — A/D Channel 6 input.

CPS6 AN — Capacitive sensing input 6.

C12IN2- AN — Comparator C1 or C2 negative input.

P1D — CMOS PWM output.

P2B — CMOS PWM output.

SDO — CMOS SPI data output.

MDCIN1 ST — Modulator Carrier Input 1.

TABLE 1-2: PIC16(L)F1824 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type

Output

Type Description

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C

HV = High Voltage XTAL = Crystal levels

Note 1: Pin functions can be moved using the APFCONO and APFCON1 registers (Register 12-1 and Register 12-2).

2: Default function location.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 17

PIC16(L)F1824/1828

RC3/AN7/CPS7/C12IN3-/

P2A(1,2)/CCP2(1,2)/P1C(1,2)/

SS(1,2)/MDMIN

RC3 TTL CMOS General purpose I/O.

AN7 AN — A/D Channel 7 input.

CPS7 AN — Capacitive sensing input 7.

C12IN3- AN — Comparator C1 or C2 negative input.

P2A — CMOS PWM output.

CCP2 AN — Capacitive sensing input 2.

P1C — CMOS PWM output.

SS ST — Slave Select input.

MDMIN — CMOS Modulator source input.

RC4/C2OUT/SRNQ/P1B/TX(1,2)/

CK(1,2)/MDOUT

RC4 TTL CMOS General purpose I/O.

C2OUT — CMOS Comparator C2 output.

SRNQ — CMOS SR latch inverting output.

P1B — CMOS PWM output.

TX — CMOS USART asynchronous transmit.

CK ST CMOS USART synchronous clock.

MDOUT — CMOS Modulator output.

RC5/P1A/CCP1/RX(1,2)/DT(1,2)/

MDCIN2

RC5 TTL CMOS General purpose I/O.

P1A — CMOS PWM output.

CCP1 ST CMOS Capture/Compare/PWM 1.

RX ST — USART asynchronous input.

DT ST CMOS USART synchronous data.

MDCIN2 ST — Modulator Carrier Input 2.

VDD VDD Power — Positive supply.

VSS VSS Power — Ground reference.

TABLE 1-2: PIC16(L)F1824 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type

Output

Type Description

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C

HV = High Voltage XTAL = Crystal levels

Note 1: Pin functions can be moved using the APFCONO and APFCON1 registers (Register 12-1 and Register 12-2).

2: Default function location.

PIC16(L)F1824/1828

DS41419C-page 18 Preliminary  2010-2011 Microchip Technology Inc.

TABLE 1-3: PIC16(L)F1828 PINOUT DESCRIPTION

Name Function Input

Type

Output

Type Description

RA0/AN0/CPS0/C1IN+/VREF-/

DACOUT/ICSPDAT/ICDDAT

RA0 TTL CMOS General purpose I/O.

AN0 AN — A/D Channel 0 input.

CPS0 AN — Capacitive sensing input 0.

C1IN+ AN — Comparator C1 positive input.

VREF- AN — A/D and DAC Negative Voltage Reference input.

DACOUT — AN Digital-to-Analog Converter output.

ICSPDAT ST CMOS ICSP™ Data I/O.

ICDDAT ST CMOS In-Circuit Data I/O.

RA1/AN1/CPS1/C12IN0-/VREF+/

SRI/ICSPCLK/ICDCLK

RA1 TTL CMOS General purpose I/O.

AN1 AN — A/D Channel 1 input.

CPS1 AN — Capacitive sensing input 1.

C12IN0- AN — Comparator C1 or C2 negative input.

VREF+ AN — A/D and DAC Positive Voltage Reference input.

SRI ST — SR latch input.

ICSPCLK ST — Serial Programming Clock.

ICDCLK ST — In-Circuit Debug Clock.

RA2/AN2/CPS2/T0CKI/INT/

C1OUT/SRQ/CCP3/FLT0

RA2 TTL CMOS General purpose I/O.

AN2 AN — A/D Channel 2 input.

CPS2 AN — Capacitive sensing input 2.

T0CKI ST — Timer0 clock input.

INT ST — External interrupt.

C1OUT — CMOS Comparator C1 output.

SRQ — CMOS SR latch non-inverting output.

CCP3 ST CMOS Capture/Compare/PWM 3.

FLT0 ST — ECCP Auto-Shutdown Fault input.

RA3/T1G(1)/VPP/MCLR RA3 TTL — General purpose input.

T1G ST — Timer1 Gate input.

VPP HV — Programming voltage.

MCLR ST — Master Clear with internal pull-up.

RA4/AN3/CPS3/OSC2/

CLKOUT/T1OSO/CLKR/P2B(1)/

T1G(1,2)

RA4 TTL CMOS General purpose I/O.

AN3 AN — A/D Channel 3 input.

CPS3 AN — Capacitive sensing input 3.

OSC2 — CMOS Comparator C2 output.

CLKOUT — CMOS FOSC/4 output.

T1OSO XTAL XTAL Timer1 oscillator connection.

CLKR — CMOS Clock Reference output.

P2B — CMOS PWM output.

T1G ST — Timer1 Gate input.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C

HV = High Voltage XTAL = Crystal levels

Note 1: Pin functions can be moved using the APFCONO and APFCON1 registers (Register 12-1 and Register 12-2).

2: Default function location.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 19

PIC16(L)F1824/1828

RA5/CLKIN/OSC1/T1OSI/

T1CKI/P2A(1)/CCP2(1)

RA5 TTL CMOS General purpose I/O.

CLKIN CMOS — External clock input (EC mode).

OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).

T1OSI XTAL XTAL Timer1 oscillator connection.

T1CKI ST — Timer1 clock input.

P2A — CMOS PWM output.

CCP2 ST CMOS Capture/Compare/PWM 2.

RB4/AN10/CPS10/SDA1/SDI1 RB4 TTL CMOS General purpose I/O.

AN10 AN — A/D Channel 10 input.

CPS10 AN — Capacitive sensing input 10.

SDA1 I2CODI

2C data input/output.

SDI1 CMOS — SPI data input.

RB5/AN11/CPS11/RX(1,2)/DT(1,2) RB5 TTL CMOS General purpose I/O.

AN11 AN — A/D Channel 11 input.

CPS11 AN — Capacitive sensing input 11.

RX ST — USART asynchronous input.

DT ST CMOS USART synchronous data.

RB6/SCL1/SCK1 RB6 TTL CMOS General purpose I/O.

SCL1 I2CODI

2C™ clock 1.

SCK1 ST CMOS SPI clock 1.

RB7/TX(1,2)/CK(1,2) RB7 TTL CMOS General purpose I/O.

TX — CMOS USART asynchronous transmit.

CK ST CMOS USART synchronous clock.

RC0/AN4/CPS4/C2IN+/P1D(1) RC0 TTL CMOS General purpose I/O.

AN4 AN — A/D Channel 4 input.

CPS4 AN — Capacitive sensing input 4.

C2IN+ AN — Comparator C2 positive input.

P1D — CMOS PWM output.

RC1/AN5/CPS5/C12IN1-/P1C(1) RC1 TTL CMOS General purpose I/O.

AN5 AN — A/D Channel 5 input.

CPS5 AN — Capacitive sensing input 5.

C12IN1- AN — Comparator C1 or C2 negative input.

P1C — CMOS PWM output.

RC2/AN6/CPS6/C12IN2-/

P1D(1,2)/P2B(1,2)/MDCIN1

RC2 TTL CMOS General purpose I/O.

AN6 AN — A/D Channel 6 input.

CPS6 AN — Capacitive sensing input 6.

C12IN2- AN — Comparator C1 or C2 negative input.

P1D — CMOS PWM output.

P2B — CMOS PWM output.

MDCIN1 ST — Modulator Carrier Input 1.

TABLE 1-3: PIC16(L)F1828 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type

Output

Type Description

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C

HV = High Voltage XTAL = Crystal levels

Note 1: Pin functions can be moved using the APFCONO and APFCON1 registers (Register 12-1 and Register 12-2).

2: Default function location.

PIC16(L)F1824/1828

DS41419C-page 20 Preliminary  2010-2011 Microchip Technology Inc.

RC3/AN7/CPS7/C12IN3-/

P2A(1,2)/CCP2(1,2)/P1C(1,2)/

MDMIN

RC3 TTL CMOS General purpose I/O.

AN7 AN — A/D Channel 7 input.

CPS7 AN — Capacitive sensing input 7.

C12IN3- AN — Comparator C1 or C2 negative input.

P2A — CMOS PWM output.

CCP2 AN — Capacitive sensing input 2.

P1C — CMOS PWM output.

MDMIN — CMOS Modulator source input.

RC4/C2OUT/SRNQ/P1B/TX(1)/

CK(1)/MDOUT

RC4 TTL CMOS General purpose I/O.

C2OUT — CMOS Comparator C2 output.

SRNQ — CMOS SR latch inverting output.

P1B — CMOS PWM output.

TX — CMOS USART asynchronous transmit.

CK ST CMOS USART synchronous clock.

MDOUT — CMOS Modulator output.

RC5/P1A/CCP1/RX(1)/DT(1)/

MDCIN2

RC5 TTL CMOS General purpose I/O.

P1A — CMOS PWM output.

CCP1 ST CMOS Capture/Compare/PWM 1.

RX ST — USART asynchronous input.

DT ST CMOS USART synchronous data.

MDCIN2 ST — Modulator Carrier Input 2.

RC6/AN8/CPS8/CCP4/SS RC6 TTL CMOS General purpose I/O.

AN8 AN — A/D Channel 8 input.

CPS8 AN — Capacitive sensing input 8.

CCP4 AN — Capacitive sensing input 4.

SS ST — Slave Select input.

RC7/AN9/CPS9/SDO RC7 TTL CMOS General purpose I/O.

AN9 AN — A/D Channel 9 input.

CPS9 AN — Capacitive sensing input 9.

SDO — CMOS SPI data output.

VDD VDD Power — Positive supply.

VSS VSS Power — Ground reference.

TABLE 1-3: PIC16(L)F1828 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type

Output

Type Description

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C

HV = High Voltage XTAL = Crystal levels

Note 1: Pin functions can be moved using the APFCONO and APFCON1 registers (Register 12-1 and Register 12-2).

2: Default function location.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 21

PIC16(L)F1824/1828

2.0 ENHANCED MID-RANGE CPU

This family of devices contain an enhanced mid-range

8-bit CPU core. The CPU has 49 instructions. Interrupt

capability includes automatic context saving. The

hardware stack is 16 levels deep and has Overflow and

Underflow Reset capability. Direct, Indirect, and

Relative Addressing modes are available. Two File

Select Registers (FSRs) provide the ability to read

program and data memory.

• Automatic Interrupt Context Saving

• 16-level Stack with Overflow and Underflow

• File Select Registers

• Instruction Set

2.1 Automatic Interrupt Context

Saving

During interrupts, certain registers are automatically

saved in shadow registers and restored when returning

from the interrupt. This saves stack space and user

code. See Section 8.5 “Automatic Context Saving”,

for more information.

2.2 16-level Stack with Overflow and

Underflow

These devices have an external stack memory 15 bits

wide and 16 words deep. A Stack Overflow or Under-

flow will set the appropriate bit (STKOVF or STKUNF)

in the PCON register, and if enabled will cause a soft-

ware Reset. See section Section 3.4 “Stack” for more

details.

2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs

can access all file registers and program memory,

which allows one data pointer for all memory. When an

FSR points to program memory, there is one additional

instruction cycle in instructions using INDF to allow the

data to be fetched. General purpose memory can now

also be addressed linearly, providing the ability to

access contiguous data larger than 80 bytes. There are

also new instructions to support the FSRs. See

Section 3.5 “Indirect Addressing” for more details.

2.4 Instruction Set

There are 49 instructions for the enhanced mid-range

CPU to support the features of the CPU. See

Section 29.0 “Instruction Set Summary” for more

details.

PIC16(L)F1824/1828

DS41419C-page 22 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 2-1: CORE BLOCK DIAGRAM

Data Bus 8

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr 7

Addr MUX

FSR reg

STATUS reg

MUX

ALU

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

VDD

Brown-out

Reset

VSS

Internal

Oscillator

Block

Configuration

Data Bus 8

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr 7

Addr MUX

FSR reg

STATUS reg

MUX

ALU

W reg

Instruction

Decode &

Control

Timing

Generation

VDD

VSS

Internal

Oscillator

Block

Configuration

15 Data Bus 8

Program

Bus

Instruction Reg

Program Counter

16-Level Stack

(15-bit)

Direct Addr 7

RAM Addr

Addr MUX

Indirect

Addr

FSR0 Reg

STATUS Reg

MUX

ALU

Instruction

Decode and

Control

Timing

Generation

VDD

VSS

Internal

Oscillator

Block

Configuration

Flash

Program

Memory RAM

FSR regFSR reg

FSR1 Reg

MUX

Program Memory

Read (PMR)

FSR regFSR reg

BSR Reg

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 23

PIC16(L)F1824/1828

3.0 MEMORY ORGANIZATION

These devices contain the following types of memory:

• Program Memory

- Configuration Words

- Device ID

-User ID

- Flash Program Memory

• Data Memory

- Core Registers

- Special Function Registers

- General Purpose RAM

- Common RAM

• Data EEPROM memory(1)

The following features are associated with access and

control of program memory and data memory:

• PCL and PCLATH

•Stack

• Indirect Addressing

3.1 Program Memory Organization

The enhanced mid-range core has a 15-bit program

counter capable of addressing a 32K x 14 program

memory space. Table 3-1 shows the memory sizes

implemented for the PIC16(L)F1824/1828 family.

Accessing a location above these boundaries will cause

a wrap-around within the implemented memory space.

The Reset vector is at 0000h and the interrupt vector is

at 0004h (see Figure 3-1).

Note 1: The data EEPROM memory and the

method to access Flash memory through

the EECON registers is described in

Section 11.0 “Data EEPROM and Flash

Program Memory Control”.

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device Program Memory Space (Words) Last Program Memory Address

PIC16(L)F1824/1828 4,096 0FFFh

PIC16(L)F1824/1828

DS41419C-page 24 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 3-1: PROGRAM MEMORY MAP

AND STACK FOR

PIC16(L)F1824/1828

3.1.1 READING PROGRAM MEMORY AS

DATA

There are two methods of accessing constants in pro-

gram memory. The first method is to use tables of

RETLW instructions. The second method is to set an

FSR to point to the program memory.

3.1.1.1 RETLW Instruction

The RETLW instruction can be used to provide access

to tables of constants. The recommended way to create

such a table is shown in Example 3-1.

EXAMPLE 3-1: RETLW INSTRUCTION

The BRW instruction makes this type of table very sim-

ple to implement. If your code must remain portable

with previous generations of microcontrollers, then the

BRW instruction is not available so the older table read

method must be used.

PC<14:0>

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

07FFh

Wraps to Page 0

0800h

CALL, CALLW

RETURN, RETLW

Interrupt, RETFIE

Rollover to Page 0

Rollover to Page 1 7FFFh

Page 1

0FFFh

1000h

constants

BRW ;Add Index in W to

;program counter to

;select data

RETLW DATA0 ;Index0 data

RETLW DATA1 ;Index1 data

RETLW DATA2

RETLW DATA3

my_function

;… LOTS OF CODE…

MOVLW DATA_INDEX

call constants

;… THE CONSTANT IS IN W

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 25

PIC16(L)F1824/1828

3.1.1.2 Indirect Read with FSR

The program memory can be accessed as data by set-

ting bit 7 of the FSRxH register and reading the match-

ing INDFx register. The MOVIW instruction will place the

lower 8 bits of the addressed word in the W register.

Writes to the program memory cannot be performed via

the INDF registers. Instructions that access the pro-

gram memory via the FSR require one extra instruction

cycle to complete. Example 3-2 demonstrates access-

ing the program memory via an FSR.

The HIGH directive will set bit<7> if a label points to a

location in program memory.

EXAMPLE 3-2: ACCESSING PROGRAM

MEMORY VIA FSR

3.2 Data Memory Organization

The data memory is partitioned in 32 memory banks

with 128 bytes in a bank. Each bank consists of

(Figure 3-2):

• 12 core registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of common RAM

The active bank is selected by writing the bank number

into the Bank Select Register (BSR). Unimplemented

memory will read as ‘0’. All data memory can be

accessed either directly (via instructions that use the

file registers) or indirectly via the two File Select

Registers (FSR). See Section 3.5 “Indirect

Addressing” for more information.

3.2.1 CORE REGISTERS

The core registers contain the registers that directly

affect the basic operation. The core registers occupy

the first 12 addresses of every data memory bank

(addresses x00h/x08h through x0Bh/x8Bh). These

registers are listed in Table 3-2 below. For detailed

information, see Tab l e 3- 3 .

TABLE 3-2: CORE REGISTERS

constants

RETLW DATA0 ;Index0 data

RETLW DATA1 ;Index1 data

RETLW DATA2

RETLW DATA3

my_function

;… LOTS OF CODE…

MOVLW LOW constants

MOVWF FSR1L

MOVLW HIGH constants

MOVWF FSR1H

MOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W

Addresses BANKx

x00h or x80h INDF0

x01h or x81h INDF1

x02h or x82h PCL

x03h or x83h STATUS

x04h or x84h FSR0L

x05h or x85h FSR0H

x06h or x86h FSR1L

x07h or x87h FSR1H

x08h or x88h BSR

x09h or x89h WREG

x0Ah or x8Ah PCLATH

x0Bh or x8Bh INTCON

PIC16(L)F1824/1828

DS41419C-page 26 Preliminary  2010-2011 Microchip Technology Inc.

3.2.1.1 STATUS Register

The STATUS register, shown in Register 3-1, contains:

• the arithmetic status of the ALU

• the Reset status

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For example, CLRF STATUS will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not

affecting any Status bits (Refer to Section 29.0

“Instruction Set Summary”).

Note 1: The C and DC bits operate as Borrow

and Digit Borrow out bits, respectively, in

subtraction.

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u

— — — TO PD ZDC

(1) C(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-5 Unimplemented: Read as ‘0’

bit 4 TO: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction

0 = A WDT time-out occurred

bit 3 PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)

1 = A carry-out from the 4th low-order bit of the result occurred

0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order

bit of the source register.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 27

PIC16(L)F1824/1828

3.2.2 SPECIAL FUNCTION REGISTER

The Special Function Registers are registers used by

the application to control the desired operation of

peripheral functions in the device. The Special Function

Registers occupy the 20 bytes after the core registers

of every data memory bank (addresses x0Ch/x8Ch

through x1Fh/x9Fh). The registers associated with the

operation of the peripherals are described in the appro-

priate peripheral chapter of this data sheet.

3.2.3 GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory

bank. The Special Function Registers occupy the 20

bytes after the core registers of every data memory

bank (addresses x0Ch/x8Ch through x1Fh/x9Fh)

3.2.3.1 Linear Access to GPR

The general purpose RAM can be accessed in a

non-banked method via the FSRs. This can simplify

access to large memory structures. See Section 3.5.2

“Linear Data Memory” for more information.

3.2.4 COMMON RAM

There are 16 bytes of common RAM accessible from all

banks.

FIGURE 3-2: BANKED MEMORY

PARTITIONING

3.2.5 DEVICE MEMORY MAPS

The memory maps for the device family are as shown

in Table 3-3.

TABLE 3-3: MEMORY MAP TABLES

Device Banks Table No.

PIC16(L)F1824/1828 0-7 Table 3-4

8-15 Table 3-5

16-23 Table 3-6

24-31 Table 3-7

31 Table 3-8

0Bh

0Ch

1Fh

20h

6Fh

70h

7Fh

00h

Common RAM

(16 bytes)

General Purpose RAM

(80 bytes maximum)

Core Registers

(12 bytes)

Special Function Registers

(20 bytes maximum)

Memory Region

7-bit Bank Offset

PIC16(L)F1824/1828

DS41419C-page 28 Preliminary  2010-2011 Microchip Technology Inc.

TABLE 3-4: PIC16F1824/PIC16F1828 MEMORY MAP, BANKS 0-7

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h INDF0 080h INDF0 100h INDF0 180h INDF0 200h INDF0 280h INDF0 300h INDF0 380h INDF0

001h INDF1 081h INDF1 101h INDF1 181h INDF1 201h INDF1 281h INDF1 301h INDF1 381h INDF1

002h PCL 082h PCL 102h PCL 182h PCL 202h PCL 282h PCL 302h PCL 382h PCL

003h STATUS 083h STATUS 103h STATUS 183h STATUS 203h STATUS 283h STATUS 303h STATUS 383h STATUS

004h FSR0L 084h FSR0L 104h FSR0L 184h FSR0L 204h FSR0L 284h FSR0L 304h FSR0L 384h FSR0L

005h FSR0H 085h FSR0H 105h FSR0H 185h FSR0H 205h FSR0H 285h FSR0H 305h FSR0H 385h FSR0H

006h FSR1L 086h FSR1L 106h FSR1L 186h FSR1L 206h FSR1L 286h FSR1L 306h FSR1L 386h FSR1L

007h FSR1H 087h FSR1H 107h FSR1H 187h FSR1H 207h FSR1H 287h FSR1H 307h FSR1H 387h FSR1H

008h BSR 088h BSR 108h BSR 188h BSR 208h BSR 288h BSR 308h BSR 388h BSR

009h WREG 089h WREG 109h WREG 189h WREG 209h WREG 289h WREG 309h WREG 389h WREG

00Ah PCLATH 08Ah PCLATH 10Ah PCLATH 18Ah PCLATH 20Ah PCLATH 28Ah PCLATH 30Ah PCLATH 38Ah PCLATH

00Bh INTCON 08Bh INTCON 10Bh INTCON 18Bh INTCON 20Bh INTCON 28Bh INTCON 30Bh INTCON 38Bh INTCON

00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch — 30Ch — 38Ch INLVLA

00Dh PORTB(1) 08Dh TRISB(1) 10Dh LATB(1) 18Dh ANSELB(1) 20Dh WPUB(1) 28Dh — 30Dh — 38Dh INLVLB(1)

00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh WPUC 28Eh —30Eh—38EhINLVLC

00Fh —08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—

010h —090h—110h—190h—210h—290h— 310h — 390h —

011h PIR1 091h PIE1 111h CM1CON0 191h EEADRL 211h SSP1BUF 291h CCPR1L 311h CCPR3L 391h IOCAP

012h PIR2 092h PIE2 112h CM1CON1 192h EEADRH 212h SSP1ADD 292h CCPR1H 312h CCPR3H 392h IOCAN

013h PIR3 093h PIE3 113h CM2CON0 193h EEDATL 213h SSP1MSK 293h CCP1CON 313h CCP3CON 393h IOCAF

014h —094h— 114h CM2CON1 194h EEDATH 214h SSP1STAT 294h PWM1CON 314h —394h IOCBP(1)

015h TMR0 095h OPTION 115h CMOUT 195h EECON1 215h SSP1CON 295h CCP1AS 315h —395h IOCBN(1)

016h TMR1L 096h PCON 116h BORCON 196h EECON2 216h SSP1CON2 296h PSTR1CON 316h —396h IOCBF(1)

017h TMR1H 097h WDTCON 117h FVRCON 197h —217h

SSP1CON3 297h — 317h —397h —

018h T1CON 098h OSCTUNE 118h DACCON0 198h —218h—298h CCPR2L 318h CCPR4L 398h —

019h T1GCON 099h OSCCON 119h DACCON1 199h RCREG 219h —299h

CCPR2H 319h CCPR4H 399h —

01Ah TMR2 09Ah OSCSTAT 11Ah SRCON0 19Ah TXREG 21Ah —29Ah

CCP2CON 31Ah CCP4CON 39Ah CLKRCON

01Bh PR2 09Bh ADRESL 11Bh SRCON1 19Bh SPBRGL 21Bh —29Bh

PWM2CON 31Bh —39Bh —

01Ch T2CON 09Ch ADRESH 11Ch — 19Ch SPBRGH 21Ch — 29Ch CCP2AS 31Ch —39Ch MDCON

01Dh — 09Dh ADCON0 11Dh APFCON0 19Dh RCSTA 21Dh —29Dh PSTR2CON 31Dh —39Dh MDSRC

01Eh CPSCON0 09Eh ADCON1 11Eh APFCON1 19Eh TXSTA 21Eh —29Eh CCPTMRS0 31Eh —39Eh MDCARL

01Fh CPSCON1 09Fh —11Fh— 19Fh BAUDCON 21Fh —29Fh CCPTMRS1 31Fh —39Fh MDCARH

020h

General

Purpose

96 Bytes

0A0h

General

Purpose

80 Bytes

120h

General

Purpose

80 Bytes

1A0h

Unimplemented

Read as ‘0’

220h

Unimplemented

Read as ‘0’

2A0h

Unimplemented

Read as ‘0’

320h

Unimplemented

Read as ‘0’

3A0h

Unimplemented

Read as ‘0’

06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh

070h 0F0h

Accesses

70h – 7Fh

170h

Accesses

70h – 7Fh

1F0h

Accesses

70h – 7Fh

270h

Accesses

70h – 7Fh

2F0h

Accesses

70h – 7Fh

370h

Accesses

70h – 7Fh

3F0h

Accesses

70h – 7Fh

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

Legend: = Unimplemented data memory locations, read as ‘0’.

Note 1: Available only on PIC16(L)F1828.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 29

PIC16(L)F1824/1828

TABLE 3-5: PIC16F1824/PIC16F1828 MEMORY MAP, BANKS 8-15

BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15

400h INDF0 480h INDF0 500h INDF0 580h INDF0 600h INDF0 680h INDF0 700h INDF0 780h INDF0

401h INDF1 481h INDF1 501h INDF1 581h INDF1 601h INDF1 681h INDF1 701h INDF1 781h INDF1

402h PCL 482h PCL 502h PCL 582h PCL 602h PCL 682h PCL 702h PCL 782h PCL

403h STATUS 483h STATUS 503h STATUS 583h STATUS 603h STATUS 683h STATUS 703h STATUS 783h STATUS

404h FSR0L 484h FSR0L 504h FSR0L 584h FSR0L 604h FSR0L 684h FSR0L 704h FSR0L 784h FSR0L

405h FSR0H 485h FSR0H 505h FSR0H 585h FSR0H 605h FSR0H 685h FSR0H 705h FSR0H 785h FSR0H

406h FSR1L 486h FSR1L 506h FSR1L 586h FSR1L 606h FSR1L 686h FSR1L 706h FSR1L 786h FSR1L

407h FSR1H 487h FSR1H 507h FSR1H 587h FSR1H 607h FSR1H 687h FSR1H 707h FSR1H 787h FSR1H

408h BSR 488h BSR 508h BSR 588h BSR 608h BSR 688h BSR 708h BSR 788h BSR

409h WREG 489h WREG 509h WREG 589h WREG 609h WREG 689h WREG 709h WREG 789h WREG

40Ah PCLATH 48Ah PCLATH 50Ah PCLATH 58Ah PCLATH 60Ah PCLATH 68Ah PCLATH 70Ah PCLATH 78Ah PCLATH

40Bh INTCON 48Bh INTCON 50Bh INTCON 58Bh INTCON 60Bh INTCON 68Bh INTCON 70Bh INTCON 78Bh INTCON

40Ch — 48Ch — 50Ch — 58Ch — 60Ch — 68Ch — 70Ch — 78Ch —

40Dh — 48Dh — 50Dh — 58Dh — 60Dh — 68Dh — 70Dh — 78Dh —

40Eh —48Eh—50Eh—58Eh—60Eh—68Eh—70Eh—78Eh—

40Fh —48Fh—50Fh—58Fh—60Fh—68Fh—70Fh—78Fh—

410h —490h—510h—590h—610h—690h— 710h — 790h —

411h —491h—511h—591h—611h—691h—711h— 791h —

412h —492h—512h—592h—612h—692h— 712h — 792h —

413h —493h—513h—593h—613h—693h— 713h — 793h —

414h —494h—514h—594h—614h—694h— 714h — 794h —

415h TMR4 495h —515h—595h—615h—695h— 715h — 795h —

416h PR4 496h —516h—596h—616h—696h— 716h — 796h —

417h T4CON 497h —517h—597h—617h—697h— 717h — 797h —

418h —498h—518h—598h—618h—698h— 718h — 798h —

419h —499h—519h—599h—619h—699h— 719h — 799h —

41Ah —49Ah—51Ah—59Ah—61Ah—69Ah—71Ah—79Ah—

41Bh —49Bh—51Bh—59Bh—61Bh—69Bh—71Bh—79Bh—

41Ch TMR6 49Ch — 51Ch — 59Ch — 61Ch — 69Ch — 71Ch — 79Ch —

41Dh PR6 49Dh — 51Dh — 59Dh — 61Dh — 69Dh — 71Dh — 79Dh —

41Eh T6CON 49Eh —51Eh—59Eh—61Eh—69Eh—71Eh—79Eh—

41Fh —49Fh—51Fh—59Fh—61Fh—69Fh—71Fh—79Fh—

420h

Unimplemented

Read as ‘0’

4A0h

Unimplemented

Read as ‘0’

520h

Unimplemented

Read as ‘0’

5A0h

Unimplemented

Read as ‘0’

620h

Unimplemented

Read as ‘0’

6A0h

Unimplemented

Read as ‘0’

720h

Unimplemented

Read as ‘0’

7A0h

Unimplemented

Read as ‘0’

46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh

470h

Accesses

70h – 7Fh

4F0h

Accesses

70h – 7Fh

570h

Accesses

70h – 7Fh

5F0h

Accesses

70h – 7Fh

670h

Accesses

70h – 7Fh

6F0h

Accesses

70h – 7Fh

770h

Accesses

70h – 7Fh

7F0h

Accesses

70h – 7Fh

47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh

Legend: = Unimplemented data memory locations, read as ‘0’.

PIC16(L)F1824/1828

DS41419C-page 30 Preliminary  2010-2011 Microchip Technology Inc.

TABLE 3-6: PIC16(L)F1824/1828 MEMORY MAP, BANKS 16-23

Legend: = Unimplemented data memory locations, read as ‘0’.

BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23

800h INDF0 880h INDF0 900h INDF0 980h INDF0 A00h INDF0 A80h INDF0 B00h INDF0 B80h INDF0

801h INDF1 881h INDF1 901h INDF1 981h INDF1 A01h INDF1 A81h INDF1 B01h INDF1 B81h INDF1

802h PCL 882h PCL 902h PCL 982h PCL A02h PCL A82h PCL B02h PCL B82h PCL

803h STATUS 883h STATUS 903h STATUS 983h STATUS A03h STATUS A83h STATUS B03h STATUS B83h STATUS

804h FSR0L 884h FSR0L 904h FSR0L 984h FSR0L A04h FSR0L A84h FSR0L B04h FSR0L B84h FSR0L

805h FSR0H 885h FSR0H 905h FSR0H 985h FSR0H A05h FSR0H A85h FSR0H B05h FSR0H B85h FSR0H

806h FSR1L 886h FSR1L 906h FSR1L 986h FSR1L A06h FSR1L A86h FSR1L B06h FSR1L B86h FSR1L

807h FSR1H 887h FSR1H 907h FSR1H 987h FSR1H A07h FSR1H A87h FSR1H B07h FSR1H B87h FSR1H

808h BSR 888h BSR 908h BSR 988h BSR A08h BSR A88h BSR B08h BSR B88h BSR

809h WREG 889h WREG 909h WREG 989h WREG A09h WREG A89h WREG B09h WREG B89h WREG

80Ah PCLATH 88Ah PCLATH 90Ah PCLATH 98Ah PCLATH A0Ah PCLATH A8Ah PCLATH B0Ah PCLATH B8Ah PCLATH

80Bh INTCON 88Bh INTCON 90Bh INTCON 98Bh INTCON A0Bh INTCON A8Bh INTCON B0Bh INTCON B8Bh INTCON

80Ch — 88Ch — 90Ch — 98Ch —A0Ch—A8Ch—B0Ch—B8Ch—

80Dh — 88Dh — 90Dh — 98Dh —A0Dh—A8Dh—B0Dh—B8Dh—

80Eh —88Eh—90Eh—98Eh—A0Eh—A8Eh—B0Eh—B8Eh—

80Fh —88Fh—90Fh—98Fh—A0Fh—A8Fh—B0Fh—B8Fh—

810h —890h—910h—990h—A10h—A90h—B10h—B90h—

811h —891h—911h—991h—A11h—A91h—B11h—B91h—

812h —892h—912h—992h—A12h—A92h—B12h—B92h—

813h —893h—913h—993h—A13h—A93h—B13h—B93h—

814h —894h—914h—994h—A14h—A94h—B14h—B94h—

815h —895h—915h—995h—A15h—A95h—B15h—B95h—

816h —896h—916h—996h—A16h—A96h—B16h—B96h—

817h —897h—917h—997h—A17h—A97h—B17h—B97h—

818h —898h—918h—998h—A18h—A98h—B18h—B98h—

819h —899h—919h—999h—A19h—A99h—B19h—B99h—

81Ah —89Ah—91Ah—99Ah—A1Ah—A9Ah—B1Ah—B9Ah—

81Bh —89Bh—91Bh—99Bh—A1Bh—A9Bh—B1Bh—B9Bh—

81Ch — 89Ch — 91Ch — 99Ch —A1Ch—A9Ch—B1Ch—B9Ch—

81Dh — 89Dh — 91Dh — 99Dh —A1Dh—A9Dh—B1Dh—B9Dh—

81Eh —89Eh—91Eh—99Eh—A1Eh—A9Eh—B1Eh—B9Eh—

81Fh —89Fh—91Fh—99Fh—A1Fh—A9Fh—B1Fh—B9Fh—

820h

Unimplemented

Read as ‘0’

8A0h

Unimplemented

Read as ‘0’

920h

Unimplemented

Read as ‘0’

9A0h

Unimplemented

Read as ‘0’

A20h

Unimplemented

Read as ‘0’

AA0h

Unimplemented

Read as ‘0’

B20h

Unimplemented

Read as ‘0’

BA0h

Unimplemented

Read as ‘0’

86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh

870h

Accesses

70h – 7Fh

8F0h

Accesses

70h – 7Fh

970h

Accesses

70h – 7Fh

9F0h

Accesses

70h – 7Fh

A70h

Accesses

70h – 7Fh

AF0h

Accesses

70h – 7Fh

B70h

Accesses

70h – 7Fh

BF0h

Accesses

70h – 7Fh

87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 31

PIC16(L)F1824/1828

TABLE 3-7: PIC16(L)F1824/1828 MEMORY MAP, BANKS 24-31

Legend: = Unimplemented data memory locations, read as ‘0’.

BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31

C00h INDF0 C80h INDF0 D00h INDF0 D80h INDF0 E00h INDF0 E80h INDF0 F00h INDF0 F80h INDF0

C01h INDF1 C81h INDF1 D01h INDF1 D81h INDF1 E01h INDF1 E81h INDF1 F01h INDF1 F81h INDF1

C02h PCL C82h PCL D02h PCL D82h PCL E02h PCL E82h PCL F02h PCL F82h PCL

C03h STATUS C83h STATUS D03h STATUS D83h STATUS E03h STATUS E83h STATUS F03h STATUS F83h STATUS

C04h FSR0L C84h FSR0L D04h FSR0L D84h FSR0L E04h FSR0L E84h FSR0L F04h FSR0L F84h FSR0L

C05h FSR0H C85h FSR0H D05h FSR0H D85h FSR0H E05h FSR0H E85h FSR0H F05h FSR0H F85h FSR0H

C06h FSR1L C86h FSR1L D06h FSR1L D86h FSR1L E06h FSR1L E86h FSR1L F06h FSR1L F86h FSR1L

C07h FSR1H C87h FSR1H D07h FSR1H D87h FSR1H E07h FSR1H E87h FSR1H F07h FSR1H F87h FSR1H

C08h BSR C88h BSR D08h BSR D88h BSR E08h BSR E88h BSR F08h BSR F88h BSR

C09h WREG C89h WREG D09h WREG D89h WREG E09h WREG E89h WREG F09h WREG F89h WREG

C0Ah PCLATH C8Ah PCLATH D0Ah PCLATH D8Ah PCLATH E0Ah PCLATH E8Ah PCLATH F0Ah PCLATH F8Ah PCLATH

C0Bh INTCON C8Bh INTCON D0Bh INTCON D8Bh INTCON E0Bh INTCON E8Bh INTCON F0Bh INTCON F8Bh INTCON

C0Ch —C8Ch—D0Ch—D8Ch—E0Ch—E8Ch—F0Ch—F8Ch

See Ta b le 3 - 8 for

details

C0Dh —C8Dh—D0Dh—D8Dh—E0Dh—E8Dh—F0Dh—F8Dh

C0Eh —C8Eh—D0Eh—D8Eh—E0Eh—E8Eh—F0Eh—F8Eh

C0Fh —C8Fh—D0Fh—D8Fh—E0Fh—E8Fh—F0Fh—F8Fh

C10h —C90h—D10h—D90h—E10h—E90h—F10h—F90h

C11h —C91h—D11h—D91h—E11h—E91h—F11h—F91h

C12h —C92h—D12h—D92h—E12h—E92h—F12h—F92h

C13h —C93h—D13h—D93h—E13h—E93h—F13h—F93h

C14h —C94h—D14h—D94h—E14h—E94h—F14h—F94h

C15h —C95h—D15h—D95h—E15h—E95h—F15h—F95h

C16h —C96h—D16h—D96h—E16h—E96h—F16h—F96h

C17h —C97h—D17h—D97h—E17h—E97h—F17h—F97h

C18h —C98h—D18h—D98h—E18h—E98h—F18h—F98h

C19h —C99h—D19h—D99h—E19h—E99h—F19h—F99h

C1Ah —C9Ah—D1Ah—D9Ah—E1Ah—E9Ah—F1Ah—F9Ah

C1Bh —C9Bh—D1Bh—D9Bh—E1Bh—E9Bh—F1Bh—F9Bh

C1Ch —C9Ch—D1Ch—D9Ch—E1Ch—E9Ch—F1Ch—F9Ch

C1Dh —C9Dh—D1Dh—D9Dh—E1Dh—E9Dh—F1Dh—F9Dh

C1Eh —C9Eh—D1Eh—D9Eh—E1Eh—E9Eh—F1Eh—F9Eh

C1Fh —C9Fh—D1Fh—D9Fh—E1Fh—E9Fh—F1Fh—F9Fh

C20h

Unimplemented

Read as ‘0’

CA0h

Unimplemented

Read as ‘0’

D20h

Unimplemented

Read as ‘0’

DA0h

Unimplemented

Read as ‘0’

E20h

Unimplemented

Read as ‘0’

EA0h

Unimplemented

Read as ‘0’

F20h

Unimplemented

Read as ‘0’

FA0h

C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh

C70h

Accesses

70h – 7Fh

CF0h

Accesses

70h – 7Fh

D70h

Accesses

70h – 7Fh

DF0h

Accesses

70h – 7Fh

E70h

Accesses

70h – 7Fh

EF0h

Accesses

70h – 7Fh

F70h

Accesses

70h – 7Fh

FF0h

Accesses

70h – 7Fh

CFFh CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh

PIC16(L)F1824/1828

DS41419C-page 32 Preliminary  2010-2011 Microchip Technology Inc.

TABLE 3-8: PIC16(L)F1824/1828 MEMORY

MAP, BANK 31

3.2.6 SPECIAL FUNCTION REGISTERS

SUMMARY

The Special Function Register Summary for the device

family are as follows:

Legend: = Unimplemented data memory locations,

read as ‘0’.

Bank 31

FA0h

FE3h

Unimplemented

Read as ‘0’

FE4h STATUS_SHAD

FE5h WREG_SHAD

FE6h BSR_SHAD

FE7h PCLATH_SHAD

FE8h FSR0L_SHAD

FE9h FSR0H_SHAD

FEAh FSR1L_SHAD

FEBh FSR1H_SHAD

FECh —

FEDh STKPTR

FEEh TOSL

FEFh TOSH

Device Bank(s) Page No.

PIC16(L)F1824/1828

033

134

235

336

437

538

639

740

841

9-30 42

31 43

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 33

PIC16(L)F1824/1828

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on all

other

Resets

Bank 0

000h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

001h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

002h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

003h(1) STATUS — — —TOPD ZDCC---1 1000 ---q quuu

004h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

005h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

006h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

007h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

008h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000

009h(1) WREG Working Register 0000 0000 uuuu uuuu

00Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

00Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u

00Ch PORTA —— RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --xx xxxx

00Dh PORTB(2) RB7 RB6 RB5 RB4 — — — — xxxx ---- xxxx ----

00Eh PORTC RC7(2) RC6(2) RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx xxxx xxxx

00Fh —Unimplemented — —

010h —Unimplemented — —

011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

012h PIR2 OSFIF C2IF C1IF EEIF BCL1IF —— CCP2IF 0000 0--0 0000 0--0

013h PIR3 —— CCP4IF CCP3IF TMR6IF —TMR4IF—--00 0-0- --00 0-0-

014h —Unimplemented — —

015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu

016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

018h T1CON TMR1CS1 TMR1CS0 T1CKPS<1:0> T1OSCEN T1SYNC —TMR1ON0000 00-0 uuuu uu-u

019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

DONE

T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu

01Ah TMR2 Timer2 Module Register 0000 0000 0000 0000

01Bh PR2 Timer2 Period Register 1111 1111 1111 1111

01Ch T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000

01Dh —Unimplemented — —

01Eh CPSCON0 CPSON CPSRM —— CPSRNG<1:0> CPSOUT T0XCS 00-- 0000 00-- 0000

01Fh CPSCON1 — — — — CPSCH<3:2> CPSCH<1:0> ---- 0000 ---- 0000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from any bank.

2: PIC16(L)F1828 only.

3: PIC16(L)F1824 only.

PIC16(L)F1824/1828

DS41419C-page 34 Preliminary  2010-2011 Microchip Technology Inc.

Bank 1

080h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

081h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

082h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

083h(1) STATUS — — —TOPD ZDCC---1 1000 ---q quuu

084h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

085h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

086h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

087h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

088h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000

089h(1) WREG Working Register 0000 0000 uuuu uuuu

08Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

08Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u

08Ch TRISA —— TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

08Dh TRISB(2) TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ----

08Eh TRISC TRISC7(2) TRISC6(2) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

08Fh —Unimplemented — —

090h —Unimplemented — —

091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

092h PIE2 OSFIE C2IE C1IE EEIE BCL1IE —— CCP2IE 0000 0--0 0000 0--0

093h PIE3 —— CCP4IE CCP3IE TMR6IE —TMR4IE—--00 0-0- --00 0-0-

094h —Unimplemented — —

095h

OPTION_REG

WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 1111 1111 1111 1111

096h PCON STKOVF STKUNF ——RMCLRRI POR BOR 00-- 11qq qq-- qquu

097h WDTCON —— WDTPS<4:0> SWDTEN --01 0110 --01 0110

098h OSCTUNE —— TUN<5:0> --00 0000 --00 0000

099h OSCCON SPLLEN IRCF<3:0> —SCS<1:0>0011 1-00 0011 1-00

09Ah OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 10q0 0q00 qqqq qq0q

09Bh ADRESL A/D Result Register Low xxxx xxxx uuuu uuuu

09Ch ADRESH A/D Result Register High xxxx xxxx uuuu uuuu

09Dh ADCON0 — CHS<4:0>

GO/DONE

ADON -000 0000 -000 0000

09Eh ADCON1 ADFM ADCS<2:0> — ADNREF

ADPREF<1:0>

0000 -000 0000 -000

09Fh —Unimplemented — —

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on all

other

Resets

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from any bank.

2: PIC16(L)F1828 only.

3: PIC16(L)F1824 only.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 35

PIC16(L)F1824/1828

Bank 2

100h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

101h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

102h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

103h(1) STATUS — — —TOPD ZDCC---1 1000 ---q quuu

104h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

105h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

106h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

107h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

108h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000

109h(1) WREG Working Register 0000 0000 uuuu uuuu

10Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

10Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u

10Ch LATA ——LATA5LATA4—LATA2LATA1LATA0--xx -xxx --uu -uuu

10Dh LATB(2) LATB7 LATB6 LATB5 LATB4 — — — — xxxx ---- xxxx ----

10Eh LATC LATC7(2) LATC6(2) LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu

10Fh —Unimplemented — —

110h —Unimplemented — —

111h CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 0000 -100 0000 -100

112h CM1CON1 C1INTP C1INTN C1PCH<1:0> —— C1NCH1 C1NCH0 0000 ---0 0000 ---0

113h CM2CON0 C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC 0000 -100 0000 -100

114h CM2CON1 C2INTP C2INTN C2PCH<1:0> —— C2NCH<1:0> 0000 --00 0000 --00

115h CMOUT — — — — — —MC2OUTMC1OUT---- --00 ---- --00

116h BORCON SBOREN — — — — — — BORRDY 1--- ---q u--- ---u

117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000

118h DACCON0 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS 000- 00-0 000- 00-0

119h DACCON1 — — — DACR<4:0> ---0 0000 ---0 0000

11Ah SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 0000 0000 0000 0000

11Bh SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 0000 0000

11Ch —Unimplemented — —

11Dh APFCON0 RXDTSEL SDOSEL(3) SSSEL(3) — T1GSEL TXCKSEL — — 000- 0000 000- 0000

11Eh APFCON1 — — — — P1DSEL P1CSEL P2BSEL CCP2SEL --00 0000 --00 0000

11Fh —Unimplemented — —

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on all

other

Resets

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from any bank.

2: PIC16(L)F1828 only.

3: PIC16(L)F1824 only.

PIC16(L)F1824/1828

DS41419C-page 36 Preliminary  2010-2011 Microchip Technology Inc.

Bank 3

180h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

181h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

182h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

183h(1) STATUS — — —TOPD ZDCC---1 1000 ---q quuu

184h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

185h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

186h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

187h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

188h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000

189h(1) WREG Working Register 0000 0000 uuuu uuuu

18Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

18Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u

18Ch ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 ---1 -111 ---1 -111

18Dh ANSELB(2) ANSB7 ANSB6 ANSB5 ANSB4 — — — — 1111 ---- 1111 ----

18Eh ANSELC ANSC7(2) ANSC6(2) —— ANSC3 ANSC2 ANSC1 ANSC0 11-- 1111 11-- 1111

18Fh —Unimplemented — —

190h —Unimplemented — —

191h EEADRL EEPROM/Program Memory Address Register Low Byte 0000 0000 0000 0000

192h EEADRH — EEPROM/Program Memory Address Register High Byte -000 0000 -000 0000

193h EEDATL EEPROM / Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu

194h EEDATH —— EEPROM / Program Memory Read Data Register High Byte --xx xxxx --uu uuuu

195h EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000

196h EECON2 EEPROM control register 2 0000 0000 0000 0000

197h —Unimplemented — —

198h —Unimplemented — —

199h RCREG USART Receive Data Register 0000 0000 0000 0000

19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000

19Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 0000

19Ch SPBRGH Baud Rate Generator Data Register High 0000 0000 0000 0000

19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010

19Fh BAUDCON ABDOVF RCIDL — SCKP BRG16 —WUEABDEN01-0 0-00 01-0 0-00

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on all

other

Resets

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from any bank.

2: PIC16(L)F1828 only.

3: PIC16(L)F1824 only.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 37

PIC16(L)F1824/1828

Bank 4

200h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

201h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

202h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

203h(1) STATUS — — —TOPD ZDCC---1 1000 ---q quuu

204h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

205h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

206h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

207h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

208h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000

209h(1) WREG Working Register 0000 0000 uuuu uuuu

20Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

20Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u

20Ch WPUA —— WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 1111

20Dh WPUB(2) WPUB7 WPUB6 WPUB5 WPUB4 — — — — 1111 ---- 1111 ----

20Eh WPUC WPUC7(2) WPUC6(2) WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 1111 1111 1111 1111

20Fh —Unimplemented — —

210h —Unimplemented — —

211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu

212h SSP1ADD ADD<7:0> 0000 0000 0000 0000

213h SSP1MSK MSK<7:0> 1111 1111 1111 1111

214h SSP1STAT SMP CKE D/A PSR/WUA BF 0000 0000 0000 0000

215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000

216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000

217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000

218h —Unimplemented — —

219h —Unimplemented — —

21Ah —Unimplemented — —

21Bh —Unimplemented — —

21Ch —Unimplemented — —

21Dh —Unimplemented — —

21Eh —Unimplemented — —

21Fh —Unimplemented — —

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on all

other

Resets

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from any bank.

2: PIC16(L)F1828 only.

3: PIC16(L)F1824 only.

PIC16(L)F1824/1828

DS41419C-page 38 Preliminary  2010-2011 Microchip Technology Inc.

Bank 5

280h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

281h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

282h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

283h(1) STATUS — — —TOPD ZDCC---1 1000 ---q quuu

284h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

285h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

286h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

287h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

288h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000

289h(1) WREG Working Register 0000 0000 uuuu uuuu

28Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

28Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u

28Ch —Unimplemented — —

28Dh —Unimplemented — —

28Eh —Unimplemented — —

28Fh —Unimplemented — —

290h —Unimplemented — —

291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu

292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu

293h CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 0000 0000 0000 0000

294h PWM1CON P1RSEN P1DC<6:0> 0000 0000 0000 0000

295h CCP1AS CCP1ASE CCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 0000 0000 0000 0000

296h PSTR1CON — — — STR1SYNC STR1D STR1C STR1B STR1A ---0 0001 ---0 0001

297h —Unimplemented — —

298h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu

299h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu

29Ah CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 0000 0000

29Bh PWM2CON P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 0000 0000

29Ch CCP2AS CCP2ASE CCP2AS2 CCP2AS1 CCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 0000 0000

29Dh PSTR2CON — — — STR2SYNC STR2D STR2C STR2B STR2A ---0 0001 ---0 0001

29Eh CCPTMRS C4TSEL1 C4TSEL0 C3TSEL1 C3TSEL0 C2TSEL1 C2TSEL0 C1TSEL1 C1TSEL0 0000 0000 0000 0000

29Fh —Unimplemented — —

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on all

other

Resets

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from any bank.

2: PIC16(L)F1828 only.

3: PIC16(L)F1824 only.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 39

PIC16(L)F1824/1828

Bank 6

300h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

301h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

302h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

303h(1) STATUS — — —TOPD ZDCC---1 1000 ---q quuu

304h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

305h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

306h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

307h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

308h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000

309h(1) WREG Working Register 0000 0000 uuuu uuuu

30Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

30Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u

30Ch —Unimplemented — —

30Dh —Unimplemented — —

30Eh —Unimplemented — —

30Fh —Unimplemented — —

310h —Unimplemented — —

311h CCPR3L Capture/Compare/PWM Register 3 (LSB) xxxx xxxx uuuu uuuu

312h CCPR3H Capture/Compare/PWM Register 3 (MSB) xxxx xxxx uuuu uuuu

313h CCP3CON —— DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 --00 0000

314h —Unimplemented — —

315h —Unimplemented — —

316h —Unimplemented — —

317h —Unimplemented — —

318h CCPR4L Capture/Compare/PWM Register 4 (LSB) xxxx xxxx uuuu uuuu

319h CCPR4H Capture/Compare/PWM Register 4 (MSB) xxxx xxxx uuuu uuuu

31Ah CCP4CON —— DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000 --00 0000

31Bh —Unimplemented — —

31Ch —Unimplemented — —

31Dh —Unimplemented — —

31Eh —Unimplemented — —

31Fh —Unimplemented — —

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on all

other

Resets

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from any bank.

2: PIC16(L)F1828 only.

3: PIC16(L)F1824 only.

PIC16(L)F1824/1828

DS41419C-page 40 Preliminary  2010-2011 Microchip Technology Inc.

Bank 7

380h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

381h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

382h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

383h(1) STATUS — — —TOPD ZDCC---1 1000 ---q quuu

384h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

385h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

386h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

387h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

388h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000

389h(1) WREG Working Register 0000 0000 uuuu uuuu

38Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

38Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u

38Ch INLVLA —— INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 --00 0100 --00 0100

38Dh INLVLB(2) INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — — 0000 ---- 0000 ----

38Eh INLVLC INLVLC7(2) INLVLC6(2) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 11xx xxxx 11xx xxxx

38Fh —Unimplemented — —

390h —Unimplemented — —

391h IOCAP —— IOCAP5 IOCAP4 IOCAP3

IOCAP2 IOCAP1 IOCAP0

--00 0000 --00 0000

392h IOCAN —— IOCAN5 IOCAN4 IOCAN3

IOCAN2 IOCAN1 IOCAN0

--00 0000 --00 0000

393h IOCAF —— IOCAF5 IOCAF4 IOCAF3

IOCAF2 IOCAF1 IOCAF0

--00 0000 --00 0000

394h IOCBP(2) IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — — 0000 ---- 0000 ----

395h IOCBN(2) IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — — 0000 ---- 0000 ----

396h IOCBF(2) IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — — 0000 ---- 0000 ----

397h —Unimplemented — —

398h —Unimplemented — —

399h —Unimplemented — —

39Ah CLKRCON CLKREN CLKROE CLKRSLR CLKRDC<1:0>

CLKRDIV

<2:0> 0011 0000 0011 0000

39Bh —Unimplemented — —

39Ch MDCON MDEN MDOE MDSLR MDOPOL MDOUT — —

MDBIT

0010 ---0 0010 ---0

39Dh MDSRC MDMSODIS — — —

MDMS<3:0>

x--- xxxx u--- uuuu

39Eh MDCARL MDCLODIS MDCLPOL MDCLSYNC —

MDCL<3:0>

xxx- xxxx uuu- uuuu

39Fh MDCARH MDCHODIS MDCHPOL MDCHSYNC —

MDCH<3:0>

xxx- xxxx uuu- uuuu

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on all

other

Resets

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from any bank.

2: PIC16(L)F1828 only.

3: PIC16(L)F1824 only.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 41

PIC16(L)F1824/1828

Bank 8

400h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

401h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

402h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

403h(1) STATUS — — —TOPD ZDCC---1 1000 ---q quuu

404h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

405h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

406h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

407h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

408h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000

409h(1) WREG Working Register 0000 0000 uuuu uuuu

40Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

40Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u

40Ch —Unimplemented — —

40Dh —Unimplemented — —

40Eh —Unimplemented — —

40Fh —Unimplemented — —

410h —Unimplemented — —

411h —Unimplemented — —

412h —Unimplemented — —

413h —Unimplemented — —

414h —Unimplemented — —

415h TMR4 Timer4 Module Register 0000 0000 0000 0000

416h PR4 Timer4 Period Register 1111 1111 1111 1111

417h T4CON — T4OUTPS<3:0> TMR4ON T4CKPS<1:0> -000 0000 -000 0000

418h —Unimplemented — —

419h —Unimplemented — —

41Ah —Unimplemented — —

41Bh —Unimplemented — —

41Ch TMR6 Timer6 Module Register 0000 0000 0000 0000

41Dh PR6 Timer6 Period Register 1111 1111 1111 1111

41Eh T6CON — T6OUTPS<3:0> TMR6ON T6CKPS<1:0> -000 0000 -000 0000

41Fh —Unimplemented — —

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on all

other

Resets

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from any bank.

2: PIC16(L)F1828 only.

3: PIC16(L)F1824 only.

PIC16(L)F1824/1828

DS41419C-page 42 Preliminary  2010-2011 Microchip Technology Inc.

Banks 9-30

x00h/

x80h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

x00h/

x81h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

x02h/

x82h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

x03h/

x83h(1) STATUS — — —TOPD ZDCC---1 1000 ---q quuu

x04h/

x84h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

x05h/

x85h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

x06h/

x86h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

x07h/

x87h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

x08h/

x88h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000

x09h/

x89h(1) WREG Working Register 0000 0000 uuuu uuuu

x0Ah/

x8Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

x0Bh/

x8Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u

x0Ch/

x8Ch

—

x1Fh/

x9Fh

—Unimplemented — —

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on all

other

Resets

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from any bank.

2: PIC16(L)F1828 only.

3: PIC16(L)F1824 only.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 43

PIC16(L)F1824/1828

Bank 31

F80h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

F81h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

F82h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

F83h(1) STATUS — — —TOPD ZDCC---1 1000 ---q quuu

F84h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

F85h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

F86h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

F87h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

F88h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000

F89h(1) WREG Working Register 0000 0000 uuuu uuuu

F8Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

F8Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u

F8Ch

—

FE3h

—Unimplemented — —

FE4h STATUS_

SHAD

— — — — —ZDCC---- -xxx ---- -uuu

FE5h WREG_

SHAD

Working Register Shadow 0000 0000 uuuu uuuu

FE6h BSR_

SHAD

— — — Bank Select Register Shadow ---x xxxx ---u uuuu

FE7h PCLATH_

SHAD

— Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu

FE8h FSR0L_

SHAD

Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu

FE9h FSR0H_

SHAD

Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu

FEAh FSR1L_

SHAD

Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu

FEBh FSR1H_

SHAD

Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu

FECh —Unimplemented — —

FEDh STKPTR — — — Current Stack pointer ---1 1111 ---1 1111

FEEh TOSL Top-of-Stack Low byte xxxx xxxx uuuu uuuu

FEFh TOSH — Top-of-Stack High byte -xxx xxxx -uuu uuuu

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on all

other

Resets

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from any bank.

2: PIC16(L)F1828 only.

3: PIC16(L)F1824 only.

PIC16(L)F1824/1828

DS41419C-page 44 Preliminary  2010-2011 Microchip Technology Inc.

3.3 PCL and PCLATH

The Program Counter (PC) is 15 bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC<14:8>) is not directly

readable or writable and comes from PCLATH. On any

Reset, the PC is cleared. Figure 3-3 shows the five

situations for the loading of the PC.

FIGURE 3-3: LOADING OF PC IN

DIFFERENT SITUATIONS

3.3.1 MODIFYING PCL

Executing any instruction with the PCL register as the

destination simultaneously causes the Program Coun-

ter PC<14:8> bits (PCH) to be replaced by the contents

of the PCLATH register. This allows the entire contents

of the program counter to be changed by writing the

desired upper 7 bits to the PCLATH register. When the

lower 8 bits are written to the PCL register, all 15 bits of

the program counter will change to the values con-

tained in the PCLATH register and those being written

to the PCL register.

3.3.2 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset to

the program counter (ADDWF PCL). When performing a

table read using a computed GOTO method, care should

be exercised if the table location crosses a PCL memory

boundary (each 256-byte block). Refer to Application

Note AN556, “Implementing a Table Read” (DS00556).

3.3.3 COMPUTED FUNCTION CALLS

A computed function CALL allows programs to maintain

tables of functions and provide another way to execute

state machines or look-up tables. When performing a

table read using a computed function CALL, care

should be exercised if the table location crosses a PCL

memory boundary (each 256-byte block).

If using the CALL instruction, the PCH<2:0> and PCL

registers are loaded with the operand of the CALL

instruction. PCH<6:3> is loaded with PCLATH<6:3>.

The CALLW instruction enables computed calls by com-

bining PCLATH and W to form the destination address.

A computed CALLW is accomplished by loading the W

The PCL register is loaded with the value of W and

PCH is loaded with PCLATH.

3.3.4 BRANCHING

The branching instructions add an offset to the PC.

This allows relocatable code and code that crosses

page boundaries. There are two forms of branching,

BRW and BRA. The PC will have incremented to fetch

the next instruction in both cases. When using either

branching instruction, a PCL memory boundary may be

crossed.

If using BRW, load the W register with the desired

unsigned address and execute BRW. The entire PC will

be loaded with the address PC + 1 + W.

If using BRA, the entire PC will be loaded with PC + 1 +,

the signed value of the operand of the BRA instruction.

PCLPCH 0

06 7

ALU Result

PCLATH

PCLPCH 0

06 4

OPCODE <10:0>

PCLATH

PCLPCH 0

06 7

PCLATH

Instruction with

PCL as

Destination

GOTO, CALL

CALLW

PCL

PCH 0

PC + W

BRW

PCLPCH 0

PC + OPCODE <8:0>

BRA

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 45

PIC16(L)F1824/1828

3.4 Stack

All devices have a 16-level x 15-bit wide hardware

stack (refer to Figures 3-4 through 3-7). The stack

space is not part of either program or data space. The

PC is PUSHed onto the stack when CALL or CALLW

instructions are executed or an interrupt causes a

branch. The stack is POPed in the event of a RETURN,

RETLW or a RETFIE instruction execution. PCLATH is

not affected by a PUSH or POP operation.

The stack operates as a circular buffer if the STVREN

bit = 0 (Configuration Word 2). This means that after

the stack has been PUSHed sixteen times, the seven-

teenth PUSH overwrites the value that was stored from

the first PUSH. The eighteenth PUSH overwrites the

second PUSH (and so on). The STKOVF and STKUNF

flag bits will be set on an Overflow/Underflow, regard-

less of whether the Reset is enabled.

3.4.1 ACCESSING THE STACK

The stack is available through the TOSH, TOSL and

STKPTR registers. STKPTR is the current value of the

Stack Pointer. TOSH:TOSL register pair points to the

TOP of the stack. Both registers are read/writable. TOS

is split into TOSH and TOSL due to the 15-bit size of the

PC. To access the stack, adjust the value of STKPTR,

which will position TOSH:TOSL, then read/write to

TOSH:TOSL. STKPTR is 5 bits to allow detection of

overflow and underflow.

During normal program operation, CALL, CALLW and

Interrupts will increment STKPTR while RETLW,

RETURN, and RETFIE will decrement STKPTR. At any

time STKPTR can be inspected to see how much stack

is left. The STKPTR always points at the currently used

place on the stack. Therefore, a CALL or CALLW will

increment the STKPTR and then write the PC, and a

return will unload the PC and then decrement STKPTR.

Reference Figure 3-4 through Figure 3-7 for examples

of accessing the stack.

FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1

Note 1: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, CALLW, RETURN, RETLW and

RETFIE instructions or the vectoring to

an interrupt address.

Note: Care should be taken when modifying the

STKPTR while interrupts are enabled.

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

0x0000

STKPTR = 0x1F

Initial Stack Configuration:

After Reset, the stack is empty. The

empty stack is initialized so the Stack

Pointer is pointing at 0x1F. If the Stack

Overflow/Underflow Reset is enabled, the

TOSH/TOSL registers will return ‘0’. If

the Stack Overflow/Underflow Reset is

disabled, the TOSH/TOSL registers will

return the contents of stack address 0x0F.

0x1F STKPTR = 0x1F

Stack Reset Disabled

(STVREN = 0)

Stack Reset Enabled

(STVREN = 1)

TOSH:TOSL

PIC16(L)F1824/1828

DS41419C-page 46 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2

FIGURE 3-6: ACCESSING THE STACK EXAMPLE 3

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

Return Address0x00 STKPTR = 0x00

This figure shows the stack configuration

after the first CALL or a single interrupt.

If a RETURN instruction is executed, the

return address will be placed in the

Program Counter and the Stack Pointer

decremented to the empty state (0x1F).

TOSH:TOSL

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

Return Address0x06

Return Address0x05

Return Address0x04

Return Address0x03

Return Address0x02

Return Address0x01

Return Address0x00

STKPTR = 0x06

After seven CALLs or six CALLs and an

interrupt, the stack looks like the figure

on the left. A series of RETURN instructions

will repeatedly place the return addresses

into the Program Counter and pop the stack.

TOSH:TOSL

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PIC16(L)F1824/1828

FIGURE 3-7: ACCESSING THE STACK EXAMPLE 4

3.4.2 OVERFLOW/UNDERFLOW RESET

If the STVREN bit in Configuration Word 2 is set to ‘1’,

the device will be reset if the stack is PUSHed beyond

the sixteenth level or POPed beyond the first level,

setting the appropriate bits (STKOVF or STKUNF,

respectively) in the PCON register.

3.5 Indirect Addressing

The INDFn registers are not physical registers. Any

instruction that accesses an INDFn register actually

accesses the register at the address specified by the

File Select Registers (FSR). If the FSRn address

specifies one of the two INDFn registers, the read will

return ‘0’ and the write will not occur (though Status bits

may be affected). The FSRn register value is created

by the pair FSRnH and FSRnL.

The FSR registers form a 16-bit address that allows an

addressing space with 65536 locations. These locations

are divided into three memory regions:

• Traditional Data Memory

• Linear Data Memory

• Program Flash Memory

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

Return Address0x00 STKPTR = 0x10

When the stack is full, the next CALL or

an interrupt will set the Stack Pointer to

0x10. This is identical to address 0x00

so the stack will wrap and overwrite the

return address at 0x00. If the Stack

Overflow/Underflow Reset is enabled, a

Reset will occur and location 0x00 will

not be overwritten.

Return Address

TOSH:TOSL

PIC16(L)F1824/1828

DS41419C-page 48 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 3-8: INDIRECT ADDRESSING

0x0000

0x0FFF

Traditional

FSR

Address

Range

Data Memory

0x1000 Reserved

Linear

Data Memory

Reserved

0x2000

0x29AF

0x29B0

0x7FFF

0x8000

0xFFFF

0x0000

0x0FFF

0x0000

0x7FFF

Program

Flash Memory

Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.

0x1FFF

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 49

PIC16(L)F1824/1828

3.5.1 TRADITIONAL DATA MEMORY

The traditional data memory is a region from FSR

address 0x000 to FSR address 0xFFF. The addresses

correspond to the absolute addresses of all SFR, GPR

and common registers.

FIGURE 3-9: TRADITIONAL DATA MEMORY MAP

Indirect AddressingDirect Addressing

Bank Select Location Select

4 BSR 6 0

From Opcode FSRxL70

Bank Select Location Select

0000 0001 0010 1111

0x00

0x7F

Bank 0 Bank 1 Bank 2 Bank 31

0FSRxH70

0000

PIC16(L)F1824/1828

DS41419C-page 50 Preliminary  2010-2011 Microchip Technology Inc.

3.5.2 LINEAR DATA MEMORY

The linear data memory is the region from FSR

address 0x2000 to FSR address 0x29AF. This region is

a virtual region that points back to the 80-byte blocks of

GPR memory in all the banks.

Unimplemented memory reads as 0x00. Use of the

linear data memory region allows buffers to be larger

than 80 bytes because incrementing the FSR beyond

one bank will go directly to the GPR memory of the next

bank.

The 16 bytes of common memory are not included in

the linear data memory region.

FIGURE 3-10: LINEAR DATA MEMORY

MAP

3.5.3 PROGRAM FLASH MEMORY

To make constant data access easier, the entire

program Flash memory is mapped to the upper half of

the FSR address space. When the MSB of FSRnH is

set, the lower 15 bits are the address in program

memory which will be accessed through INDF. Only the

lower 8 bits of each memory location is accessible via

INDF. Writing to the program Flash memory cannot be

accomplished via the FSR/INDF interface. All

instructions that access program Flash memory via the

FSR/INDF interface will require one additional

instruction cycle to complete.

FIGURE 3-11: PROGRAM FLASH

MEMORY MAP

Location Select 0x2000

FSRnH FSRnL

0x020

Bank 0

0x06F

0x0A0

Bank 1

0x0EF

0x120

Bank 2

0x16F

0xF20

Bank 30

0xF6F

0x29AF

Location Select 0x8000

FSRnH FSRnL

0x0000

0x7FFF

0xFFFF

Program

Flash

Memory

(low 8

bits)

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 51

PIC16(L)F1824/1828

4.0 DEVICE CONFIGURATION

Device Configuration consists of Configuration Word 1

and Configuration Word 2, Code Protection and Device

ID.

4.1 Configuration Words

There are several Configuration Word bits that allow

different oscillator and memory protection options.

These are implemented as Configuration Word 1 at

8007h and Configuration Word 2 at 8008h.

Note: The DEBUG bit in Configuration Word is

managed automatically by device

development tools including debuggers

and programmers. For normal device

operation, this bit should be maintained as

a ‘1’.

PIC16(L)F1824/1828

DS41419C-page 52 Preliminary  2010-2011 Microchip Technology Inc.

R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1

FCMEN IESO CLKOUTEN BOREN1 BOREN0 CPD

bit 13 bit 8

R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1

CP MCLRE PWRTE WDTE1 WDTE0 FOSC2 FOSC1 FOSC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared P = Programmable bit

bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit

1 = Fail-Safe Clock Monitor is enabled

0 = Fail-Safe Clock Monitor is disabled

bit 12 IESO: Internal External Switchover bit

1 = Internal/External Switchover mode is enabled

0 = Internal/External Switchover mode is disabled

bit 11 CLKOUTEN: Clock Out Enable bit

If FOSC Configuration bits are set to LP, XT, HS modes:

This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin.

All other FOSC modes:

1 = CLKOUT function is disabled. I/O function on the CLKOUT pin.

0 = CLKOUT function is enabled on the CLKOUT pin

bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits(1)

11 = BOR enabled

10 = BOR enabled during operation and disabled in Sleep

01 = BOR controlled by SBOREN bit of the BORCON register

00 = BOR disabled

bit 8 CPD: Data Code Protection bit(2)

1 = Data memory code protection is disabled

0 = Data memory code protection is enabled

bit 7 CP: Code Protection bit(3)

1 = Program memory code protection is disabled

0 = Program memory code protection is enabled

bit 6 MCLRE: RA3/MCLR/VPP Pin Function Select bit

If LVP bit = 1:

This bit is ignored.

If LVP bit = 0:

1 =MCLR

/VPP pin function is MCLR; Weak pull-up enabled.

0 =MCLR

/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUA register.

bit 5 PWRTE: Power-up Timer Enable bit(1)

1 = PWRT disabled

0 = PWRT enabled

bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit

11 = WDT enabled

10 = WDT enabled while running and disabled in Sleep

01 = WDT controlled by the SWDTEN bit in the WDTCON register

00 = WDT disabled

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.

2: The entire data EEPROM will be erased when the code protection is turned off during an erase.

3: The entire program memory will be erased when the code protection is turned off.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 53

PIC16(L)F1824/1828

bit 2-0 FOSC<2:0>: Oscillator Selection bits

111 = ECH: External Clock, High-Power mode (4-32 MHz): device clock supplied to CLKIN pin

110 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN

101 = ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin

100 = INTOSC oscillator: I/O function on CLKIN pin

011 = EXTRC oscillator: External RC circuit connected to CLKIN pin

010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins

001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins

000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.

2: The entire data EEPROM will be erased when the code protection is turned off during an erase.

3: The entire program memory will be erased when the code protection is turned off.

PIC16(L)F1824/1828

DS41419C-page 54 Preliminary  2010-2011 Microchip Technology Inc.

R/P-1/1 R/P-1/1 U-1 R/P-1/1 R/P-1/1 R/P-1/1

LVP(1) DEBUG(2) — BORV STVREN PLLEN

bit 13 bit 8

U-1 U-1 U-1 R-1 U-1 U-1 R/P-1/1 R/P-1/1

— — — Reserved —— WRT1 WRT0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared P = Programmable bit

bit 13 LVP: Low-Voltage Programming Enable bit(1)

1 = Low-voltage programming enabled

0 = High-voltage on MCLR must be used for programming

bit 12 DEBUG: In-Circuit Debugger Mode bit(2)

1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins

0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger

bit 11 Unimplemented: Read as ‘1’

bit 10 BORV: Brown-out Reset Voltage Selection bit

1 = Brown-out Reset voltage set to 1.9V (typical)

0 = Brown-out Reset voltage set to 2.7V (typical)

bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit

1 = Stack Overflow or Underflow will cause a Reset

0 = Stack Overflow or Underflow will not cause a Reset

bit 8 PLLEN: PLL Enable bit

1 = 4xPLL enabled

0 = 4xPLL disabled

bit 7-5 Unimplemented: Read as ‘1’

bit 4 Reserved: This location should be programmed to a ‘1’

bit 3-2 Unimplemented: Read as ‘1’

bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits

11 = Write protection off

10 = 000h to 1FFh write-protected, 200h to 7FFh may be modified by EECON control

01 = 000h to 3FFh write-protected, 400h to 7FFh may be modified by EECON control

00 = 000h to 7FFh write-protected, no addresses may be modified by EECON control

Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.

2: The DEBUG bit in Configuration Word is managed automatically by device development tools including debuggers and

programmers. For normal device operation, this bit should be maintained as a ‘1’.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 55

PIC16(L)F1824/1828

4.2 Code Protection

Code protection allows the device to be protected from

unauthorized access. Program memory protection and

data EEPROM protection are controlled independently.

Internal access to the program memory and data

EEPROM are unaffected by any code protection

setting.

4.2.1 PROGRAM MEMORY PROTECTION

The entire program memory space is protected from

external reads and writes by the CP bit in Configuration

Word 1. When CP = 0, external reads and writes of

program memory are inhibited and a read will return all

‘0’s. The CPU can continue to read program memory,

regardless of the protection bit settings. Writing the

program memory is dependent upon the write

protection setting. See Section 4.3 “Write

Protection” for more information.

4.2.2 DATA EEPROM PROTECTION

The entire data EEPROM is protected from external

reads and writes by the CPD bit. When CPD = 0,

external reads and writes of data EEPROM are

inhibited. The CPU can continue to read and write data

EEPROM regardless of the protection bit settings.

4.3 Write Protection

Write protection allows the device to be protected from

unintended self-writes. Applications, such as

bootloader software, can be protected while allowing

other regions of the program memory to be modified.

The WRT<1:0> bits in Configuration Word 2 define the

size of the program memory block that is protected.

4.4 User ID

Four memory locations (8000h-8003h) are designated as

ID locations where the user can store checksum or other

code identification numbers. These locations are

readable and writable during normal execution. See

Section 11.5 “User ID, Device ID and Configuration

Word Access” for more information on accessing these

memory locations. For more information on checksum

calculation, see the “PIC16F/LF182X/PIC12F/LF1822

Memory Programming Specification” (DS41390).

PIC16(L)F1824/1828

DS41419C-page 56 Preliminary  2010-2011 Microchip Technology Inc.

4.5 Device ID and Revision ID

The memory location 8006h is where the Device ID and

Revision ID are stored. The upper nine bits hold the

Device ID. The lower five bits hold the Revision ID. See

Section 11.5 “User ID, Device ID and Configuration

Word Access” for more information on accessing

these memory locations.

Development tools, such as device programmers and

debuggers, may be used to read the Device ID and

Revision ID.

RRRRRR

DEV<8:3>

bit 13 bit 8

RRRRRRRR

DEV<2:0> REV<4:0>

bit 7 bit 0

Legend: U = Unimplemented bit, read as ‘0’

R = Readable bit W = Writable bit ‘0’ = Bit is cleared

-n = Value at POR ‘1’ = Bit is set x = Bit is unknown

bit 13-5 DEV<8:0>: Device ID bits

100111010 = PIC16F1824

100111110 = PIC16F1828

101000010 = PIC16LF1824

101000110 = PIC16LF1828

bit 4-0 REV<4:0>: Revision ID bits

These bits are used to identify the revision.

Note 1: This location cannot be written.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 57

PIC16(L)F1824/1828

5.0 OSCILLATOR MODULE (WITH

FAIL-SAFE CLOCK MONITOR)

5.1 Overview

The oscillator module has a wide variety of clock

sources and selection features that allow it to be used

in a wide range of applications while maximizing perfor-

mance and minimizing power consumption. Figure 5-1

illustrates a block diagram of the oscillator module.

Clock sources can be supplied from external oscillators,

quartz crystal resonators, ceramic resonators and

Resistor-Capacitor (RC) circuits. In addition, the system

clock source can be supplied from one of two internal

oscillators and PLL circuits, with a choice of speeds

selectable via software. Additional clock features

include:

• Selectable system clock source between external

or internal sources via software.

• Two-Speed Start-up mode, which minimizes

latency between external oscillator start-up and

code execution.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP,

XT, HS, EC or RC modes) and switch

automatically to the internal oscillator.

• Oscillator Start-up Timer (OST) ensures stability

of crystal oscillator sources

The oscillator module can be configured in one of eight

clock modes.

1. ECL – External Clock Low-Power mode

(0 MHz to 0.5 MHz)

2. ECM – External Clock Medium-Power mode

(0.5 MHz to 4 MHz)

3. ECH – External Clock High-Power mode

(4 MHz to 32 MHz)

4. LP – 32 kHz Low-Power Crystal mode.

5. XT – Medium Gain Crystal or Ceramic Resonator

Oscillator mode (up to 4 MHz)

6. HS – High Gain Crystal or Ceramic Resonator

mode (4 MHz to 20 MHz)

7. RC – External Resistor-Capacitor (RC).

8. INTOSC – Internal oscillator (31 kHz to 32 MHz).

Clock Source modes are selected by the FOSC<2:0>

bits in the Configuration Word 1. The FOSC bits

determine the type of oscillator that will be used when

the device is first powered.

The EC clock mode relies on an external logic level

signal as the device clock source. The LP, XT, and HS

clock modes require an external crystal or resonator to

be connected to the device. Each mode is optimized for

a different frequency range. The RC clock mode

requires an external resistor and capacitor to set the

oscillator frequency.

The INTOSC internal oscillator block produces low,

medium, and high frequency clock sources, designated

LFINTOSC, MFINTOSC, and HFINTOSC. (see

Internal Oscillator Block, Figure 5-1). A wide selection

of device clock frequencies may be derived from these

three clock sources.

PIC16(L)F1824/1828

DS41419C-page 58 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 5-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

4 x PLL

FOSC<2:0>

Oscillator

T1OSCEN

Enable

Oscillator

T1OSO

T1OSI

Clock Source Option

for other modules

OSC1

OSC2

Sleep

LP, XT, HS, RC, EC

T1OSC CPU and

Postscaler

MUX

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

250 kHz

500 kHz

IRCF<3:0>

31 kHz

500 kHz

Source

Internal

Oscillator

Block

WDT, PWRT, Fail-Safe Clock Monitor

16 MHz

Internal Oscillator

(HFINTOSC)

Clock

Control

SCS<1:0>

HFPLL

31 kHz (LFINTOSC)

Two-Speed Start-up and other modules

Oscillator

31 kHz

Source

500 kHz

(MFINTOSC)

125 kHz

31.25 kHz

62.5 kHz

FOSC<2:0> = 100

Peripherals

Sleep

External

Timer1

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 59

PIC16(L)F1824/1828

5.2 Clock Source Types

Clock sources can be classified as external or internal.

External clock sources rely on external circuitry for the

clock source to function. Examples are: oscillator mod-

ules (EC mode), quartz crystal resonators or ceramic

resonators (LP, XT and HS modes) and Resis-

tor-Capacitor (RC) mode circuits.

Internal clock sources are contained internally within

the oscillator module. The internal oscillator block has

two internal oscillators and a dedicated Phase-Locked

Loop (HFPLL) that are used to generate three internal

system clock sources: the 16 MHz High-Frequency

Internal Oscillator (HFINTOSC), 500 kHz (MFINTOSC)

and the 31 kHz Low-Frequency Internal Oscillator

(LFINTOSC).

The system clock can be selected between external or

internal clock sources via the System Clock Select

(SCS) bits in the OSCCON register. See Section 5.3

“Clock Switching” for additional information.

5.2.1 EXTERNAL CLOCK SOURCES

An external clock source can be used as the device

system clock by performing one of the following

actions:

• Program the FOSC<2:0> bits in the Configuration

Word 1 to select an external clock source that will

be used as the default system clock upon a

device Reset.

• Write the SCS<1:0> bits in the OSCCON register

to switch the system clock source to:

- Timer1 Oscillator during run-time, or

- An external clock source determined by the

value of the FOSC bits.

See Section 5.3 “Clock Switching”for more informa-

tion.

5.2.1.1 EC Mode

The External Clock (EC) mode allows an externally

generated logic level signal to be the system clock

source. When operating in this mode, an external clock

source is connected to the OSC1 input.

OSC2/CLKOUT is available for general purpose I/O or

CLKOUT. Figure 5-2 shows the pin connections for EC

mode.

EC mode has 3 power modes to select from through

Configuration Word 1:

• High power, 4-32 MHz (FOSC = 111)

• Medium power, 0.5-4 MHz (FOSC = 110)

• Low power, 0-0.5 MHz (FOSC = 101)

The Oscillator Start-up Timer (OST) is disabled when

EC mode is selected. Therefore, there is no delay in

operation after a Power-on Reset (POR) or wake-up

from Sleep. Because the PIC® MCU design is fully

static, stopping the external clock input will have the

effect of halting the device while leaving all data intact.

Upon restarting the external clock, the device will

resume operation as if no time had elapsed.

FIGURE 5-2: EXTERNAL CLOCK (EC)

MODE OPERATION

5.2.1.2 LP, XT, HS Modes

The LP, XT and HS modes support the use of quartz

crystal resonators or ceramic resonators connected to

OSC1 and OSC2 (Figure 5-3). The three modes select

a low, medium or high gain setting of the internal

inverter-amplifier to support various resonator types

and speed.

LP Oscillator mode selects the lowest gain setting of

the internal inverter-amplifier. LP mode current

consumption is the least of the three modes. This mode

is designed to drive only 32.768 kHz tuning-fork type

crystals (watch crystals).

XT Oscillator mode selects the intermediate gain

setting of the internal inverter-amplifier. XT mode

current consumption is the medium of the three modes.

This mode is best suited to drive resonators with a

medium drive level specification.

HS Oscillator mode selects the highest gain setting of

the internal inverter-amplifier. HS mode current

consumption is the highest of the three modes. This

mode is best suited for resonators that require a high

drive setting.

Figure 5-3 and Figure 5-4 show typical circuits for

quartz crystal and ceramic resonators, respectively.

OSC1/CLKIN

OSC2/CLKOUT

Clock from

Ext. System

PIC® MCU

FOSC/4 or I/O(1)

Note 1: Output depends upon CLKOUTEN bit of the

Configuration Word 1.

PIC16(L)F1824/1828

DS41419C-page 60 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 5-3: QUARTZ CRYSTAL

OPERATION (LP, XT OR

HS MODE)

FIGURE 5-4: CERAMIC RESONATOR

OPERATION

(XT OR HS MODE)

5.2.1.3 Oscillator Start-up Timer (OST)

If the oscillator module is configured for LP, XT or HS

modes, the Oscillator Start-up Timer (OST) counts

1024 oscillations from OSC1. This occurs following a

Power-on Reset (POR) and when the Power-up Timer

(PWRT) has expired (if configured), or a wake-up from

Sleep. During this time, the program counter does not

increment and program execution is suspended. The

OST ensures that the oscillator circuit, using a quartz

crystal resonator or ceramic resonator, has started and

is providing a stable system clock to the oscillator

module.

In order to minimize latency between external oscillator

start-up and code execution, the Two-Speed Clock

Start-up mode can be selected (see Section 5.4

“Two-Speed Clock Start-up Mode”).

5.2.1.4 4xPLL

The oscillator module contains a 4xPLL that can be

used with both external and internal clock sources to

provide a system clock source. The input frequency for

the 4xPLL must fall within specifications. See the PLL

Clock Timing Specifications in Section 30.0

“Electrical Specifications”.

The 4xPLL may be enabled for use by one of two

methods:

1. Program the PLLEN bit in Configuration Word 2

to a ‘1’.

2. Write the SPLLEN bit in the OSCCON register to

a ‘1’. If the PLLEN bit in Configuration Word 2 is

programmed to a ‘1’, then the value of SPLLEN

is ignored.

Note 1: Quartz crystal characteristics vary

according to type, package and

manufacturer. The user should consult the

manufacturer data sheets for specifications

and recommended application.

2: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC® and PIC®

Devices” (DS00826)

• AN849, “Basic PIC® Oscillator Design”

(DS00849)

• AN943, “Practical PIC® Oscillator

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work”

(DS00949)

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

2: The value of RF varies with the Oscillator mode

selected (typically between 2 M to 10 M.

Quartz

RS(1)

OSC1/CLKIN

RF(2) Sleep

To Internal

Logic

PIC® MCU

Crystal

OSC2/CLKOUT

Note 1: A series resistor (RS) may be required for

ceramic resonators with low drive level.

2: The value of RF varies with the Oscillator mode

selected (typically between 2 M to 10 M.

3: An additional parallel feedback resistor (RP)

may be required for proper ceramic resonator

operation.

C2 Ceramic RS(1)

OSC1/CLKIN

RF(2) Sleep

To Internal

Logic

PIC® MCU

RP(3)

Resonator

OSC2/CLKOUT

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 61

PIC16(L)F1824/1828

5.2.1.5 TIMER1 Oscillator

The Timer1 Oscillator is a separate crystal oscillator

that is associated with the Timer1 peripheral. It is opti-

mized for timekeeping operations with a 32.768 kHz

crystal connected between the T1OSO and T1OSI

device pins.

The Timer1 Oscillator can be used as an alternate sys-

tem clock source and can be selected during run-time

using clock switching. Refer to Section 5.3 “Clock

Switching” for more information.

FIGURE 5-5: QUARTZ CRYSTAL

OPERATION (TIMER1

OSCILLATOR)

5.2.1.6 External RC Mode

The external Resistor-Capacitor (RC) modes support

the use of an external RC circuit. This allows the

designer maximum flexibility in frequency choice while

keeping costs to a minimum when clock accuracy is not

required.

The RC circuit connects to OSC1. OSC2/CLKOUT is

available for general purpose I/O or CLKOUT. The

function of the OSC2/CLKOUT pin is determined by the

state of the CLKOUTEN bit in Configuration Word 1.

Figure 5-6 shows the external RC mode connections.

FIGURE 5-6: EXTERNAL RC MODES

The RC oscillator frequency is a function of the supply

voltage, the resistor (REXT) and capacitor (CEXT) values

and the operating temperature. Other factors affecting

the oscillator frequency are:

• threshold voltage variation

• component tolerances

• packaging variations in capacitance

The user also needs to take into account variation due

to tolerance of external RC components used.

Note 1: Quartz crystal characteristics vary

according to type, package and

manufacturer. The user should consult the

manufacturer data sheets for specifications

and recommended application.

2: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC® and PIC®

Devices” (DS00826)

• AN849, “Basic PIC® Oscillator Design”

(DS00849)

• AN943, “Practical PIC® Oscillator

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work”

(DS00949)

• TB097, “Interfacing a Micro Crystal

MS1V-T1K 32.768 kHz Tuning Fork

Crystal to a PIC16F690/SS” (DS91097)

• AN1288, “Design Practices for

Low-Power External Oscillators”

(DS01288)

32.768 kHz

T1OSI

To Internal

Logic

PIC® MCU

Crystal

T1OSO

Quartz

OSC2/CLKOUT

CEXT

REXT

PIC® MCU

OSC1/CLKIN

FOSC/4 or

Internal

Clock

VDD

VSS

Recommended values: 10 k  REXT  100 k, <3V

3 k  REXT  100 k, 3-5V

CEXT > 20 pF, 2-5V

Note 1: Output depends upon CLKOUTEN bit of the

Configuration Word 1.

I/O(1)

PIC16(L)F1824/1828

DS41419C-page 62 Preliminary  2010-2011 Microchip Technology Inc.

5.2.2 INTERNAL CLOCK SOURCES

The device may be configured to use the internal oscil-

lator block as the system clock by performing one of the

following actions:

• Program the FOSC<2:0> bits in Configuration

Word 1 to select the INTOSC clock source, which

will be used as the default system clock upon a

device Reset.

• Write the SCS<1:0> bits in the OSCCON register

to switch the system clock source to the internal

oscillator during run-time. See Section 5.3

“Clock Switching”for more information.

In INTOSC mode, OSC1/CLKIN is available for general

purpose I/O. OSC2/CLKOUT is available for general

purpose I/O or CLKOUT.

The function of the OSC2/CLKOUT pin is determined

by the state of the CLKOUTEN bit in Configuration

Word 1.

The internal oscillator block has two independent

oscillators and a dedicated Phase-Locked Loop,

HFPLL that can produce one of three internal system

clock sources.

1. The HFINTOSC (High-Frequency Internal

Oscillator) is factory calibrated and operates at

16 MHz. The HFINTOSC source is generated

from the 500 kHz MFINTOSC source and the

dedicated Phase-Locked Loop, HFPLL. The

frequency of the HFINTOSC can be

user-adjusted via software using the OSCTUNE

2. The MFINTOSC (Medium-Frequency Internal

Oscillator) is factory calibrated and operates at

500 kHz. The frequency of the MFINTOSC can

be user-adjusted via software using the

OSCTUNE register (Register 5-3).

3. The LFINTOSC (Low-Frequency Internal

Oscillator) is uncalibrated and operates at

31 kHz.

5.2.2.1 HFINTOSC

The High-Frequency Internal Oscillator (HFINTOSC) is

a factory calibrated 16 MHz internal clock source. The

frequency of the HFINTOSC can be altered via

software using the OSCTUNE register (Register 5-3).

The output of the HFINTOSC connects to a postscaler

and multiplexer (see Figure 5-1). One of nine

frequencies derived from the HFINTOSC can be

selected via software using the IRCF<3:0> bits of the

OSCCON register. See Section 5.2.2.7 “Internal

Oscillator Clock Switch Timing” for more information.

The HFINTOSC is enabled by:

• Configure the IRCF<3:0> bits of the OSCCON

•FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the

OSCCON register to ‘1x’.

The High-Frequency Internal Oscillator Ready bit

(HFIOFR) of the OSCSTAT register indicates when the

HFINTOSC is running and can be utilized.

The High-Frequency Internal Oscillator Status Locked

bit (HFIOFL) of the OSCSTAT register indicates when

the HFINTOSC is running within 2% of its final value.

The High-Frequency Internal Oscillator Status Stable

bit (HFIOFS) of the OSCSTAT register indicates when

the HFINTOSC is running within 0.5% of its final value.

5.2.2.2 MFINTOSC

The Medium-Frequency Internal Oscillator

(MFINTOSC) is a factory calibrated 500 kHz internal

clock source. The frequency of the MFINTOSC can be

altered via software using the OSCTUNE register

(Register 5-3).

The output of the MFINTOSC connects to a postscaler

and multiplexer (see Figure 5-1). One of nine

frequencies derived from the MFINTOSC can be

selected via software using the IRCF<3:0> bits of the

OSCCON register. See Section 5.2.2.7 “Internal

Oscillator Clock Switch Timing” for more information.

The MFINTOSC is enabled by:

• Configure the IRCF<3:0> bits of the OSCCON

•FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the

OSCCON register to ‘1x’

The Medium-Frequency Internal Oscillator Ready bit

(MFIOFR) of the OSCSTAT register indicates when the

MFINTOSC is running and can be utilized.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 63

PIC16(L)F1824/1828

5.2.2.3 Internal Oscillator Frequency

Adjustment

The 500 kHz internal oscillator is factory calibrated.

This internal oscillator can be adjusted in software by

writing to the OSCTUNE register (Register 5-3). Since

the HFINTOSC and MFINTOSC clock sources are

derived from the 500 kHz internal oscillator a change in

the OSCTUNE register value will apply to both.

The default value of the OSCTUNE register is ‘0’. The

value is a 6-bit two’s complement number. A value of

1Fh will provide an adjustment to the maximum

frequency. A value of 20h will provide an adjustment to

the minimum frequency.

When the OSCTUNE register is modified, the oscillator

frequency will begin shifting to the new frequency. Code

execution continues during this shift. There is no

indication that the shift has occurred.

OSCTUNE does not affect the LFINTOSC frequency.

Operation of features that depend on the LFINTOSC

clock source frequency, such as the Power-up Timer

(PWRT), Watchdog Timer (WDT), Fail-Safe Clock

Monitor (FSCM) and peripherals, are not affected by the

change in frequency.

5.2.2.4 LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is

an uncalibrated 31 kHz internal clock source.

The output of the LFINTOSC connects to a postscaler

and multiplexer (see Figure 5-1). Select 31 kHz, via

software, using the IRCF<3:0> bits of the OSCCON

Clock Switch Timing” for more information. The

LFINTOSC is also the frequency for the Power-up Timer

(PWRT), Watchdog Timer (WDT) and Fail-Safe Clock

Monitor (FSCM).

The LFINTOSC is enabled by selecting 31 kHz

(IRCF<3:0> bits of the OSCCON register = 000) as the

system clock source (SCS bits of the OSCCON

enabled:

• Configure the IRCF<3:0> bits of the OSCCON

•FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the

OSCCON register to ‘1x’

Peripherals that use the LFINTOSC are:

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

• Fail-Safe Clock Monitor (FSCM)

The Low-Frequency Internal Oscillator Ready bit

(LFIOFR) of the OSCSTAT register indicates when the

LFINTOSC is running and can be utilized.

5.2.2.5 Internal Oscillator Frequency

Selection

The system clock speed can be selected via software

using the Internal Oscillator Frequency Select bits

IRCF<3:0> of the OSCCON register.

The output of the 16 MHz HFINTOSC and 31 kHz

LFINTOSC connects to a postscaler and multiplexer

(see Figure 5-1). The Internal Oscillator Frequency

Select bits IRCF<3:0> of the OSCCON register select

the frequency output of the internal oscillators. One of

the following frequencies can be selected via software:

• 32 MHz (requires 4xPLL)

•16 MHz

•8 MHz

•4 MHz

•2 MHz

•1 MHz

• 500 kHz (Default after Reset)

•250 kHz

•125 kHz

•62.5 kHz

•31.25 kHz

• 31 kHz (LFINTOSC)

The IRCF<3:0> bits of the OSCCON register allow

duplicate selections for some frequencies. These dupli-

cate choices can offer system design trade-offs. Lower

power consumption can be obtained when changing

oscillator sources for a given frequency. Faster transi-

tion times can be obtained between frequency changes

that use the same oscillator source.

Note: Following any Reset, the IRCF<3:0> bits

of the OSCCON register are set to ‘0111’

and the frequency selection is set to

500 kHz. The user can modify the IRCF

bits to select a different frequency.

PIC16(L)F1824/1828

DS41419C-page 64 Preliminary  2010-2011 Microchip Technology Inc.

5.2.2.6 32 MHz Internal Oscillator

Frequency Selection

The Internal Oscillator Block can be used with the

4xPLL associated with the External Oscillator Block to

produce a 32 MHz internal system clock source. The

following settings are required to use the 32 MHz inter-

nal clock source:

• The FOSC bits in Configuration Word 1 must be

set to use the INTOSC source as the device sys-

tem clock (FOSC<2:0> = 100).

• The SCS bits in the OSCCON register must be

cleared to use the clock determined by

FOSC<2:0> in Configuration Word 1

(SCS<1:0> = 00).

• The IRCF bits in the OSCCON register must be

set to the 8 MHz HFINTOSC set to use

(IRCF<3:0> = 1110).

• The SPLLEN bit in the OSCCON register must be

set to enable the 4xPLL, or the PLLEN bit of the

Configuration Word 2 must be programmed to a

‘1’.

The 4xPLL is not available for use with the internal

oscillator when the SCS bits of the OSCCON register

are set to ‘1x’. The SCS bits must be set to ‘00’ to use

the 4xPLL with the internal oscillator.

5.2.2.7 Internal Oscillator Clock Switch

Timing

When switching between the HFINTOSC, MFINTOSC

and the LFINTOSC, the new oscillator may already be

shut down to save power (see Figure 5-7). If this is the

case, there is a delay after the IRCF<3:0> bits of the

OSCCON register are modified before the frequency

selection takes place. The OSCSTAT register will

reflect the current active status of the HFINTOSC,

MFINTOSC and LFINTOSC oscillators. The sequence

of a frequency selection is as follows:

1. IRCF<3:0> bits of the OSCCON register are

modified.

2. If the new clock is shut down, a clock start-up

delay is started.

3. Clock switch circuitry waits for a falling edge of

the current clock.

4. The current clock is held low and the clock

switch circuitry waits for a rising edge in the new

clock.

5. The new clock is now active.

6. The OSCSTAT register is updated as required.

7. Clock switch is complete.

See Figure 5-7 for more details.

If the internal oscillator speed is switched between two

clocks of the same source, there is no start-up delay

before the new frequency is selected. Clock switching

time delays are shown in Table 5-1.

Start-up delay specifications are located in the

oscillator tables of Section 30.0 “Electrical

Specifications”.

Note: When using the PLLEN bit of the

Configuration Word 2, the 4xPLL cannot

be disabled by software and the 8 MHz

HFINTOSC option will no longer be

available.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 65

PIC16(L)F1824/1828

FIGURE 5-7: INTERNAL OSCILLATOR SWITCH TIMING

HFINTOSC/

LFINTOSC

IRCF <3:0>

System Clock

HFINTOSC/

LFINTOSC

IRCF <3:0>

System Clock

00

Start-up Time 2-cycle Sync Running

2-cycle Sync Running

HFINTOSC/ LFINTOSC (FSCM and WDT disabled)

HFINTOSC/ LFINTOSC (Either FSCM or WDT enabled)

LFINTOSC

HFINTOSC/

IRCF <3:0>

System Clock

= 0 0

Start-up Time 2-cycle Sync Running

LFINTOSC HFINTOSC/MFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled

MFINTOSC

PIC16(L)F1824/1828

DS41419C-page 66 Preliminary  2010-2011 Microchip Technology Inc.

5.3 Clock Switching

The system clock source can be switched between

external and internal clock sources via software using

the System Clock Select (SCS) bits of the OSCCON

using the SCS bits:

• Default system oscillator determined by FOSC

bits in Configuration Word 1

• Timer1 32 kHz crystal oscillator

• Internal Oscillator Block (INTOSC)

5.3.1 SYSTEM CLOCK SELECT (SCS)

BITS

The System Clock Select (SCS) bits of the OSCCON

the CPU and peripherals.

• When the SCS bits of the OSCCON register = 00,

the system clock source is determined by value of

the FOSC<2:0> bits in the Configuration Word 1.

• When the SCS bits of the OSCCON register = 01,

the system clock source is the Timer1 oscillator.

• When the SCS bits of the OSCCON register = 1x,

the system clock source is chosen by the internal

oscillator frequency selected by the IRCF<3:0>

bits of the OSCCON register. After a Reset, the

SCS bits of the OSCCON register are always

cleared.

When switching between clock sources, a delay is

required to allow the new clock to stabilize. These oscil-

lator delays are shown in Table 5-1.

5.3.2 OSCILLATOR START-UP TIME-OUT

STATUS (OSTS) BIT

The Oscillator Start-up Time-out Status (OSTS) bit of

the OSCSTAT register indicates whether the system

clock is running from the external clock source, as

defined by the FOSC<2:0> bits in the Configuration

Word 1, or from the internal clock source. In particular,

OSTS indicates that the Oscillator Start-up Timer

(OST) has timed out for LP, XT or HS modes. The OST

does not reflect the status of the Timer1 Oscillator.

5.3.3 TIMER1 OSCILLATOR

The Timer1 Oscillator is a separate crystal oscillator

associated with the Timer1 peripheral. It is optimized

for timekeeping operations with a 32.768 kHz crystal

connected between the T1OSO and T1OSI device

pins.

The Timer1 oscillator is enabled using the T1OSCEN

control bit in the T1CON register. See Section 21.0

“Timer1 Module with Gate Control” for more

information about the Timer1 peripheral.

5.3.4 TIMER1 OSCILLATOR READY

(T1OSCR) BIT

The user must ensure that the Timer1 Oscillator is

ready to be used before it is selected as a system clock

source. The Timer1 Oscillator Ready (T1OSCR) bit of

the OSCSTAT register indicates whether the Timer1

oscillator is ready to be used. After the T1OSCR bit is

set, the SCS bits can be configured to select the Timer1

oscillator.

Note: Any automatic clock switch, which may

occur from Two-Speed Start-up or

Fail-Safe Clock Monitor, does not update

the SCS bits of the OSCCON register. The

user can monitor the OSTS bit of the

OSCSTAT register to determine the

current system clock source.

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5.4 Two-Speed Clock Start-up Mode

Two-Speed Start-up mode provides additional power

savings by minimizing the latency between external

oscillator start-up and code execution. In applications

that make heavy use of the Sleep mode, Two-Speed

Start-up will remove the external oscillator start-up

time from the time spent awake and can reduce the

overall power consumption of the device. This mode

allows the application to wake-up from Sleep, perform

a few instructions using the INTOSC internal oscillator

block as the clock source and go back to Sleep without

waiting for the external oscillator to become stable.

Two-Speed Start-up provides benefits when the oscil-

lator module is configured for LP, XT, or HS modes.

The Oscillator Start-up Timer (OST) is enabled for

these modes and must count 1024 oscillations before

the oscillator can be used as the system clock source.

If the oscillator module is configured for any mode

other than LP, XT or HS mode, then Two-Speed

Start-up is disabled. This is because the external clock

oscillator does not require any stabilization time after

POR or an exit from Sleep.

If the OST count reaches 1024 before the device

enters Sleep mode, the OSTS bit of the OSCSTAT reg-

ister is set and program execution switches to the

external oscillator. However, the system may never

operate from the external oscillator if the time spent

awake is very short.

5.4.1 TWO-SPEED START-UP MODE

CONFIGURATION

Two-Speed Start-up mode is configured by the

following settings:

• IESO (of the Configuration Word 1) = 1; Inter-

nal/External Switchover bit (Two-Speed Start-up

mode enabled).

• SCS (of the OSCCON register) = 00.

• FOSC<2:0> bits in the Configuration Word 1

configured for LP, XT or HS mode.

Two-Speed Start-up mode is entered after:

• Power-on Reset (POR) and, if enabled, after

Power-up Timer (PWRT) has expired, or

• Wake-up from Sleep.

TABLE 5-1: OSCILLATOR SWITCHING DELAYS

Note: Executing a SLEEP instruction will abort

the oscillator start-up time and will cause

the OSTS bit of the OSCSTAT register to

remain clear.

Switch From Switch To Frequency Oscillator Delay

Sleep/POR

LFINTOSC(1)

MFINTOSC(1)

HFINTOSC(1)

31 kHz

31.25 kHz-500 kHz

31.25kHz-16MHz

Oscillator Warm-up Delay (TWARM)

Sleep/POR EC, RC(1) DC – 32 MHz 2 cycles

LFINTOSC EC, RC(1) DC – 32 MHz 1 cycle of each

Sleep/POR Timer1 Oscillator

LP, XT, HS(1) 32 kHz-20 MHz 1024 Clock Cycles (OST)

Any clock source MFINTOSC(1)

HFINTOSC(1)

31.25 kHz-500 kHz

31.25kHz-16MHz 2s (approx.)

Any clock source LFINTOSC(1) 31 kHz 1 cycle of each

Any clock source Timer1 Oscillator 32 kHz 1024 Clock Cycles (OST)

PLL inactive PLL active 16-32 MHz 2 ms (approx.)

Note 1: PLL inactive.

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5.4.2 TWO-SPEED START-UP

SEQUENCE

1. Wake-up from Power-on Reset or Sleep.

2. Instructions begin execution by the internal

oscillator at the frequency set in the IRCF<3:0>

bits of the OSCCON register.

3. OST enabled to count 1024 clock cycles.

4. OST timed out, wait for falling edge of the

internal oscillator.

5. OSTS is set.

6. System clock held low until the next falling edge

of new clock (LP, XT or HS mode).

7. System clock is switched to external clock

source.

5.4.3 CHECKING TWO-SPEED CLOCK

STATUS

Checking the state of the OSTS bit of the OSCSTAT

from the external clock source, as defined by the

FOSC<2:0> bits in the Configuration Word 1, or the

internal oscillator.

FIGURE 5-8: TWO-SPEED START-UP

0 1 1022 1023

PC + 1

TOSTT

INTOSC

OSC1

OSC2

Program Counter

System Clock

PC - N PC

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5.5 Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) allows the device

to continue operating should the external oscillator fail.

The FSCM can detect oscillator failure any time after

the Oscillator Start-up Timer (OST) has expired. The

FSCM is enabled by setting the FCMEN bit in the

Configuration Word 1. The FSCM is applicable to all

external Oscillator modes (LP, XT, HS, EC, Timer1

Oscillator and RC).

FIGURE 5-9: FSCM BLOCK DIAGRAM

5.5.1 FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by

comparing the external oscillator to the FSCM sample

clock. The sample clock is generated by dividing the

LFINTOSC by 64. See Figure 5-9. Inside the fail

detector block is a latch. The external clock sets the

latch on each falling edge of the external clock. The

sample clock clears the latch on each rising edge of the

sample clock. A failure is detected when an entire

half-cycle of the sample clock elapses before the

external clock goes low.

5.5.2 FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the

device clock to an internal clock source and sets the bit

flag OSFIF of the PIR2 register. Setting this flag will

generate an interrupt if the OSFIE bit of the PIE2

steps to mitigate the problems that may arise from a

failed clock. The system clock will continue to be

sourced from the internal clock source until the device

firmware successfully restarts the external oscillator

and switches back to external operation.

The internal clock source chosen by the FSCM is

determined by the IRCF<3:0> bits of the OSCCON

configured before a failure occurs.

5.5.3 FAIL-SAFE CONDITION CLEARING

The Fail-Safe condition is cleared after a Reset,

executing a SLEEP instruction or changing the SCS bits

of the OSCCON register. When the SCS bits are

changed, the OST is restarted. While the OST is

running, the device continues to operate from the

INTOSC selected in OSCCON. When the OST times

out, the Fail-Safe condition is cleared and the device

will be operating from the external clock source. The

Fail-Safe condition must be cleared before the OSFIF

flag can be cleared.

5.5.4 RESET OR WAKE-UP FROM SLEEP

The FSCM is designed to detect an oscillator failure

after the Oscillator Start-up Timer (OST) has expired.

The OST is used after waking up from Sleep and after

any type of Reset. The OST is not used with the EC or

RC Clock modes so that the FSCM will be active as

soon as the Reset or wake-up has completed. When

the FSCM is enabled, the Two-Speed Start-up is also

enabled. Therefore, the device will always be executing

code while the OST is operating.

External

LFINTOSC ÷ 64

31 kHz

(~32 s)

488 Hz

(~2 ms)

Clock Monitor

Latch

Clock

Failure

Detected

Oscillator

Clock

Sample Clock

Note: Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active

during oscillator start-up (i.e., after exiting

Reset or Sleep). After an appropriate

amount of time, the user should check the

Status bits in the OSCSTAT register to

verify the oscillator start-up and that the

system clock switchover has successfully

completed.

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FIGURE 5-10: FSCM TIMING DIAGRAM

OSCFIF

System

Clock

Output

Sample Clock

Failure

Detected

Oscillator

Failure

Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

(Q)

Te s t Test Test

Clock Monitor Output

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5.6 Oscillator Control Registers

R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0

SPLLEN IRCF<3:0> —SCS<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 SPLLEN: Software PLL Enable bit

If PLLEN in Configuration Word 1 = 1:

SPLLEN bit is ignored. 4xPLL is always enabled (subject to oscillator requirements)

If PLLEN in Configuration Word 1 = 0:

1 = 4xPLL Is enabled

0 = 4xPLL is disabled

bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits

000x =31kHz LF

0010 = 31.25 kHz MF

0011 = 31.25 kHz HF(1)

0100 = 62.5 kHz MF

0101 = 125 kHz MF

0110 = 250 kHz MF

0111 = 500 kHz MF (default upon Reset)

1000 = 125 kHz HF(1)

1001 = 250 kHz HF(1)

1010 = 500 kHz HF(1)

1011 =1MHz HF

1100 =2MHz HF

1101 =4MHz HF

1110 = 8 MHz or 32 MHz HF(see Section 5.2.2.1 “HFINTOSC”)

1111 = 16 MHz HF

bit 2 Unimplemented: Read as ‘0’

bit 1-0 SCS<1:0>: System Clock Select bits

1x = Internal oscillator block

01 = Timer1 oscillator

00 = Clock determined by FOSC<2:0> in Configuration Word 1.

Note 1: Duplicate frequency derived from HFINTOSC.

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R-1/q R-0/q R-q/q R-0/q R-0/q R-q/q R-0/0 R-0/q

T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional

bit 7 T1OSCR: Timer1 Oscillator Ready bit

If T1OSCEN = 1:

1 = Timer1 oscillator is ready

0 = Timer1 oscillator is not ready

If T1OSCEN = 0:

1 = Timer1 clock source is always ready

bit 6 PLLR 4xPLL Ready bit

1 = 4xPLL is ready

0 = 4xPLL is not ready

bit 5 OSTS: Oscillator Start-up Time-out Status bit

1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Word 1

0 = Running from an internal oscillator (FOSC<2:0> = 100)

bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit

1 = HFINTOSC is ready

0 = HFINTOSC is not ready

bit 3 HFIOFL: High-Frequency Internal Oscillator Locked bit

1 = HFINTOSC is at least 2% accurate

0 = HFINTOSC is not 2% accurate

bit 2 MFIOFR: Medium-Frequency Internal Oscillator Ready bit

1 = MFINTOSC is ready

0 = MFINTOSC is not ready

bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit

1 = LFINTOSC is ready

0 = LFINTOSC is not ready

bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit

1 = HFINTOSC is at least 0.5% accurate

0 = HFINTOSC is not 0.5% accurate

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TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

TABLE 5-3: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

—— TUN<5:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 TUN<4:0>: Frequency Tuning bits

011111 = Maximum frequency

011110 =

•

000001 =

000000 = Oscillator module is running at the factory-calibrated frequency.

111111 =

•

100000 = Minimum frequency

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

OSCCON SPLLEN IRCF<3:0> —SCS<1:0>71

OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 72

OSCTUNE ——TUN<5:0>73

PIE2 OSFIE C2IE C1IE EEIE BCL1IE — — CCP2IE 95

PIR2 OSFIF C2IF C1IF EEIF BCL1IF — — CCP2IF 98

T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC —TMR1ON 197

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register

on Page

CONFIG1 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> CPD 52

7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

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NOTES:

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6.0 REFERENCE CLOCK MODULE

The reference clock module provides the ability to send

a divided clock to the clock output pin of the device

(CLKR) and provide a secondary internal clock source

to the modulator module. This module is available in all

oscillator configurations and allows the user to select a

greater range of clock submultiples to drive external

devices in the application. The reference clock module

includes the following features:

• System clock is the source

• Available in all oscillator configurations

• Programmable clock divider

• Output enable to a port pin

• Selectable duty cycle

• Slew rate control

The reference clock module is controlled by the

CLKRCON register (Register 6-1) and is enabled when

setting the CLKREN bit. To output the divided clock sig-

nal to the CLKR port pin, the CLKROE bit must be set.

The CLKRDIV<2:0> bits enable the selection of 8 dif-

ferent clock divider options. The CLKRDC<1:0> bits

can be used to modify the duty cycle of the output

clock(1). The CLKRSLR bit controls slew rate limiting.

For information on using the reference clock output

with the modulator module, see Section 23.0 “Data

Signal Modulator”.

6.1 Slew Rate

The slew rate limitation on the output port pin can be

disabled. The Slew Rate limitation can be removed by

clearing the CLKRSLR bit in the CLKRCON register.

6.2 Effects of a Reset

Upon any device Reset, the reference clock module is

disabled. The user’s firmware is responsible for

initializing the module before enabling the output. The

registers are reset to their default values.

6.3 Conflicts with the CLKR pin

There are two cases when the reference clock output

signal cannot be output to the CLKR pin, if:

• LP, XT, or HS oscillator mode is selected.

• CLKOUT function is enabled.

Even if either of these cases are true, the module can

still be enabled and the reference clock signal may be

used in conjunction with the modulator module.

6.3.1 OSCILLATOR MODES

If LP, XT, or HS oscillator modes are selected, the

OSC2/CLKR pin must be used as an oscillator input pin

and the CLKR output cannot be enabled. See

Section 5.2 “Clock Source Types” for more informa-

tion on different oscillator modes.

6.3.2 CLKOUT FUNCTION

The CLKOUT function has a higher priority than the ref-

erence clock module. Therefore, if the CLKOUT func-

tion is enabled by the CLKOUTEN bit in Configuration

Word 1, FOSC/4 will always be output on the port pin.

Reference Section 4.0 “Device Configuration” for

more information.

6.4 Operation During Sleep

As the reference clock module relies on the system

clock as its source, and the system clock is disabled in

Sleep, the module does not function in Sleep, even if

an external clock source or the Timer1 clock source is

configured as the system clock. The module outputs

will remain in their current state until the device exits

Sleep.

Note 1: If the base clock rate is selected without

a divider, the output clock will always

have a duty cycle equal to that of the

source clock, unless a 0% duty cycle is

selected. If the clock divider is set to base

clock/2, then 25% and 75% duty cycle

accuracy will be dependent upon the

source clock.

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DS41419C-page 76 Preliminary  2010-2011 Microchip Technology Inc.

R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

CLKREN CLKROE CLKRSLR CLKRDC<1:0> CLKRDIV<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 CLKREN: Reference Clock Module Enable bit

1 = Reference Clock module is enabled

0 = Reference Clock module is disabled

bit 6 CLKROE: Reference Clock Output Enable bit(3)

1 = Reference Clock output is enabled on CLKR pin

0 = Reference Clock output disabled on CLKR pin

bit 5 CLKRSLR: Reference Clock Slew Rate Control Limiting Enable bit

1 = Slew Rate limiting is enabled

0 = Slew Rate limiting is disabled

bit 4-3 CLKRDC<1:0>: Reference Clock Duty Cycle bits

11 = Clock outputs duty cycle of 75%

10 = Clock outputs duty cycle of 50%

01 = Clock outputs duty cycle of 25%

00 = Clock outputs duty cycle of 0%

bit 2-0 CLKRDIV<2:0> Reference Clock Divider bits

111 = Base clock value divided by 128

110 = Base clock value divided by 64

101 = Base clock value divided by 32

100 = Base clock value divided by 16

011 = Base clock value divided by 8

010 = Base clock value divided by 4

001 = Base clock value divided by 2(1)

000 = Base clock value(2)

Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle.

2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0%

is selected.

3: To route CLKR to pin, CLKOUTEN of Configuration Word 1 = 1 is required. CLKOUTEN of Configuration

Word 1 = 0 will result in FOSC/4. See Section 6.3 “Conflicts with the CLKR pin” for details.

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TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH REFERENCE CLOCK SOURCES

TABLE 6-2: SUMMARY OF CONFIGURATION WORD WITH REFERENCE CLOCK SOURCES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

CLKRCON CLKREN CLKROE CLKRSLR CLKRDC1 CLKRDC0

CLKRDIV2 CLKRDIV1 CLKRDIV0

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources.

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register

on Page

CONFIG1 13:8 — — FCMEN IESO CLKOUTEN BOREN1 BOREN0 CPD 52

7:0 CP MCLRE PWRTE WDTE1 WDTE0 FOSC2 FOSC1 FOSC0

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources.

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NOTES:

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7.0 RESETS

There are multiple ways to reset this device:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

•MCLR

Reset

•WDT Reset

•RESET instruction

• Stack Overflow

• Stack Underflow

• Programming mode exit

To allow VDD to stabilize, an optional Power-up Timer

can be enabled to extend the Reset time after a BOR

or POR event.

A simplified block diagram of the On-Chip Reset Circuit

is shown in Figure 7-1.

FIGURE 7-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External Reset

MCLR

VDD

WDT

Time-out

Power-on

Reset

LFINTOSC

PWRT

64 ms

PWRTEN

Brown-out

Reset

BOR

RESET Instruction

Stack

Pointer

Stack Overflow/Underflow Reset

Sleep

MCLRE

Enable

Device

Reset

Zero

Programming Mode Exit

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7.1 Power-on Reset (POR)

The POR circuit holds the device in Reset until VDD has

reached an acceptable level for minimum operation.

Slow rising VDD, fast operating speeds or analog

performance may require greater than minimum VDD.

The PWRT, BOR or MCLR features can be used to

extend the start-up period until all device operation

conditions have been met.

7.1.1 POWER-UP TIMER (PWRT)

The Power-up Timer provides a nominal 64 ms time-

out on POR or Brown-out Reset.

The device is held in Reset as long as PWRT is active.

The PWRT delay allows additional time for the VDD to

rise to an acceptable level. The Power-up Timer is

enabled by clearing the PWRTE bit in Configuration

Word 1.

The Power-up Timer starts after the release of the POR

and BOR.

For additional information, refer to Application Note

AN607, “Power-up Trouble Shooting” (DS00607).

7.2 Brown-Out Reset (BOR)

The BOR circuit holds the device in Reset when VDD

reaches a selectable minimum level. Between the

POR and BOR, complete voltage range coverage for

execution protection can be implemented.

The Brown-out Reset module has four operating

modes controlled by the BOREN<1:0> bits in Configu-

ration Word 1. The four operating modes are:

• BOR is always on

• BOR is off when in Sleep

• BOR is controlled by software

• BOR is always off

Refer to Tab le 7 -3 for more information.

The Brown-out Reset voltage level is selectable by

configuring the BORV bit in Configuration Word 2.

A VDD noise rejection filter prevents the BOR from trig-

gering on small events. If VDD falls below VBOR for a

duration greater than parameter TBORDC, the device

will reset. See Figure 7-3 for more information.

TABLE 7-1: BOR OPERATING MODES

7.2.1 BOR IS ALWAYS ON

When the BOREN bits of Configuration Word 1 are set

to ‘11’, the BOR is always on. The device start-up will

be delayed until the BOR is ready and VDD is higher

than the BOR threshold.

BOR protection is active during Sleep. The BOR does

not delay wake-up from Sleep.

7.2.2 BOR IS OFF IN SLEEP

When the BOREN bits of Configuration Word 1 are set

to ‘10’, the BOR is on, except in Sleep. The device

start-up will be delayed until the BOR is ready and VDD

is higher than the BOR threshold.

BOR protection is not active during Sleep. The device

wake-up will be delayed until the BOR is ready.

7.2.3 BOR CONTROLLED BY SOFTWARE

When the BOREN bits of Configuration Word 1 are set

to ‘01’, the BOR is controlled by the SBOREN bit of the

BORCON register. The device start-up is not delayed

by the BOR ready condition or the VDD level.

BOR protection begins as soon as the BOR circuit is

ready. The status of the BOR circuit is reflected in the

BORRDY bit of the BORCON register.

BOR protection is unchanged by Sleep.

BOREN

Config bits SBOREN Device Mode BOR Mode

Device

Operation upon

release of POR

Device

Operation upon

wake-up from

Sleep

BOR_ON (11)XX Active Waits for BOR ready(1)

BOR_NSLEEP (10) X Awake Active Waits for BOR ready

BOR_NSLEEP (10)XSleep Disabled

BOR_SBOREN (01)1X Active Begins immediately

BOR_SBOREN (01)0X Disabled Begins immediately

BOR_OFF (00)XX Disabled Begins immediately

Note 1: Even though this case specifically waits for the BOR, the BOR is already operating, so there is no delay in

start-up.

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FIGURE 7-2: BROWN-OUT READY

FIGURE 7-3: BROWN-OUT SITUATIONS

R/W-1/u U-0 U-0 U-0 U-0 U-0 U-0 R-q/u

SBOREN — — — — — —BORRDY

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 SBOREN: Software Brown-out Reset Enable bit

If BOREN <1:0> in Configuration Word 1  01:

SBOREN is read/write, but has no effect on the BOR.

If BOREN <1:0> in Configuration Word 1 = 01:

1 = BOR Enabled

0 = BOR Disabled

bit 6-1 Unimplemented: Read as ‘0’

bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit

1 = The Brown-out Reset circuit is active

0 = The Brown-out Reset circuit is inactive

TBORRDY

SBOREN

BORRDY BOR Protection Active

TPWRT(1)

VBOR

VDD

Internal

Reset

VBOR

VDD

Internal

Reset TPWRT(1)

< TPWRT

TPWRT(1)

VBOR

VDD

Internal

Reset

Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.

PIC16(L)F1824/1828

DS41419C-page 82 Preliminary  2010-2011 Microchip Technology Inc.

7.3 MCLR

The MCLR is an optional external input that can reset

the device. The MCLR function is controlled by the

MCLRE bit of Configuration Word 1 and the LVP bit of

Configuration Word 2 (Ta b le 7- 2).

7.3.1 MCLR ENABLED

When MCLR is enabled and the pin is held low, the

device is held in Reset. The MCLR pin is connected to

VDD through an internal weak pull-up.

The device has a noise filter in the MCLR Reset path.

The filter will detect and ignore small pulses.

7.3.2 MCLR DISABLED

When MCLR is disabled, the pin functions as a general

purpose input and the internal weak pull-up is under

software control. See Section 12.2 “PORTA Registers”

for more information.

7.4 Watchdog Timer (WDT) Reset

The Watchdog Timer generates a Reset if the firmware

does not issue a CLRWDT instruction within the time-out

period. The TO and PD bits in the STATUS register are

changed to indicate the WDT Reset. See Section 10.0

“Watchdog Timer” for more information.

7.5 RESET Instruction

A RESET instruction will cause a device Reset. The RI

bit in the PCON register will be set to ‘0’. See Ta b l e 7- 4

for default conditions after a RESET instruction has

occurred.

7.6 Stack Overflow/Underflow Reset

The device can reset when the Stack Overflows or

Underflows. The STKOVF or STKUNF bits of the PCON

enabled by setting the STVREN bit in Configuration

Word 2. See Section 3.4.2 “Overflow/Underflow

Reset” for more information.

7.7 Programming Mode Exit

Upon exit of Programming mode, the device will

behave as if a POR had just occurred.

7.8 Power-Up Timer

The Power-up Timer optionally delays device execution

after a BOR or POR event. This timer is typically used to

allow VDD to stabilize before allowing the device to start

running.

The Power-up Timer is controlled by the PWRTE bit of

Configuration Word 1.

7.9 Start-up Sequence

Upon the release of a POR or BOR, the following must

occur before the device will begin executing:

1. Power-up Timer runs to completion (if enabled).

2. Oscillator start-up timer runs to completion (if

required for oscillator source).

3. MCLR must be released (if enabled).

The total time-out will vary based on oscillator configu-

ration and Power-up Timer configuration. See

Section 5.0 “Oscillator Module (With Fail-Safe

Clock Monitor)” for more information.

The Power-up Timer and oscillator start-up timer run

independently of MCLR Reset. If MCLR is kept low long

enough, the Power-up Timer and oscillator start-up

timer will expire. Upon bringing MCLR high, the device

will begin execution immediately (see Figure 7-4). This

is useful for testing purposes or to synchronize more

than one device operating in parallel.

TABLE 7-2: MCLR CONFIGURATION

MCLRE LVP MCLR

00Disabled

10Enabled

x1Enabled

Note: A Reset does not drive the MCLR pin low.

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FIGURE 7-4: RESET START-UP SEQUENCE

TOST

TMCLR

TPWRT

VDD

Internal POR

Power-Up Timer

MCLR

Internal RESET

Oscillator Modes

Oscillator Start-Up Timer

Oscillator

FOSC

Internal Oscillator

Oscillator

FOSC

External Clock (EC)

CLKIN

FOSC

External Crystal

PIC16(L)F1824/1828

DS41419C-page 84 Preliminary  2010-2011 Microchip Technology Inc.

7.10 Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS and

PCON register are updated to indicate the cause of the

Reset. Ta bl e 7 - 3 and Tab l e 7-4 show the Reset

conditions of these registers.

TABLE 7-3: RESET STATUS BITS AND THEIR SIGNIFICANCE

TABLE 7-4: RESET CONDITION FOR SPECIAL REGISTERS(2)

STKOVF STKUNF RMCLR RI POR BOR TO PD Condition

00110x11Power-on Reset

00110x0xIllegal, TO is set on POR

00110xx0Illegal, PD is set on POR

0011u011Brown-out Reset

uuuuuu0uWDT Reset

uuuuuu00WDT Wake-up from Sleep

uuuuuu10Interrupt Wake-up from Sleep

uu0uuuuuMCLR Reset during normal operation

uu0uuu10MCLR Reset during Sleep

u u u 0 u u u u RESET Instruction Executed

1uuuuuuuStack Overflow Reset (STVREN = 1)

u1uuuuuuStack Underflow Reset (STVREN = 1)

Condition Program

Counter

STATUS

PCON

Power-on Reset 0000h ---1 1000 00-- 110x

MCLR Reset during normal operation 0000h ---u uuuu uu-- 0uuu

MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu

WDT Reset 0000h ---0 uuuu uu-- uuuu

WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu

Brown-out Reset 0000h ---1 1uuu 00-- 11u0

Interrupt Wake-up from Sleep PC + 1(1) ---1 0uuu uu-- uuuu

RESET Instruction Executed 0000h ---u uuuu uu-- u0uu

Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu

Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set, the return address is

pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

2: If a Status bit is not implemented, that bit will be read as ‘0’.

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PIC16(L)F1824/1828

7.11 Power Control (PCON) Register

The Power Control (PCON) register contains flag bits

to differentiate between a:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Reset Instruction Reset (RI)

• Stack Overflow Reset (STKOVF)

• Stack Underflow Reset (STKUNF)

•MCLR

Reset (RMCLR)

The PCON register bits are shown in Register 7-2.

R/W/HS-0/q R/W/HS-0/q U-0 U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u

STKOVF STKUNF — — RMCLR RI POR BOR

bit 7 bit 0

Legend:

HC = Bit is cleared by hardware HS = Bit is set by hardware

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 STKOVF: Stack Overflow Flag bit

1 = A Stack Overflow occurred

0 = A Stack Overflow has not occurred or set to ‘0’ by firmware

bit 6 STKUNF: Stack Underflow Flag bit

1 = A Stack Underflow occurred

0 = A Stack Underflow has not occurred or set to ‘0’ by firmware

bit 5-4 Unimplemented: Read as ‘0’

bit 3 RMCLR: MCLR Reset Flag bit

1 = A MCLR Reset has not occurred or set to ‘1’ by firmware

0 = A MCLR Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs)

bit 2 RI: RESET Instruction Flag bit

1 = A RESET instruction has not been executed or set to ‘1’ by firmware

0 = A RESET instruction has been executed (set to ‘0’ in hardware upon executing a RESET instruction)

bit 1 POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR: Brown-out Reset Status bit

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset

occurs)

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DS41419C-page 86 Preliminary  2010-2011 Microchip Technology Inc.

TABLE 7-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

BORCON SBOREN —————— BORRDY 81

PCON STKOVF STKUNF ——RMCLRRI POR BOR 85

STATUS — — —TOPD ZDC C26

WDTCON —— WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN 105

Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.

Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 87

PIC16(L)F1824/1828

8.0 INTERRUPTS

The interrupt feature allows certain events to preempt

normal program flow. Firmware is used to determine

the source of the interrupt and act accordingly. Some

interrupts can be configured to wake the MCU from

Sleep mode.

This chapter contains the following information for

Interrupts:

• Operation

• Interrupt Latency

• Interrupts During Sleep

•INT Pin

• Automatic Context Saving

Many peripherals produce interrupts. Refer to the

corresponding chapters for details.

A block diagram of the interrupt logic is shown in

Figure 8-1 and Figure 8-2.

FIGURE 8-1: INTERRUPT LOGIC

TMR0IF

TMR0IE

INTF

INTE

IOCIF

IOCIE

GIE

PEIE

Wake-up (If in Sleep mode)

Interrupt to CPU

From Peripheral Interrupt

Logic (Figure 8-2)

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DS41419C-page 88 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 8-2: PERIPHERAL INTERRUPT LOGIC

To Interrupt Logic

(Figure 8-1)

Note 1: PIC16(L)F1828 only.

TMR1GIF

TMR1GIE

ADIF

ADIE

RCIF

RCIE

TXIF

TXIE

SSPIF

SSPIE

CCP1IF

CCP1IE

TMR1IF

TMR1IE

TMR6IF

TMR6IE

EEIF

EEIE

OSFIF

OSFIE

C1IF

C1IE

C2IF

C2IE

BCL1IF

BCL1IE

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8.1 Operation

Interrupts are disabled upon any device Reset. They

are enabled by setting the following bits:

• GIE bit of the INTCON register

• Interrupt Enable bit(s) for the specific interrupt

event(s)

• PEIE bit of the INTCON register (if the Interrupt

Enable bit of the interrupt event is contained in the

PIEx register)

The INTCON, PIR1, PIR2 and PIR3 registers record

individual interrupts via interrupt flag bits. Interrupt flag

bits will be set, regardless of the status of the GIE, PEIE

and individual interrupt enable bits.

The following events happen when an interrupt event

occurs while the GIE bit is set:

• Current prefetched instruction is flushed

• GIE bit is cleared

• Current Program Counter (PC) is pushed onto the

stack

• Critical registers are automatically saved to the

shadow registers (See Section 8.5 “Automatic

Context Saving”)

• PC is loaded with the interrupt vector 0004h

The firmware within the Interrupt Service Routine (ISR)

should determine the source of the interrupt by polling

the interrupt flag bits. The interrupt flag bits must be

cleared before exiting the ISR to avoid repeated

interrupts. Because the GIE bit is cleared, any interrupt

that occurs while executing the ISR will be recorded

through its interrupt flag, but will not cause the

processor to redirect to the interrupt vector.

The RETFIE instruction exits the ISR by popping the

previous address from the stack, restoring the saved

context from the shadow registers and setting the GIE

bit.

For additional information on a specific interrupt’s

operation, refer to its peripheral chapter.

8.2 Interrupt Latency

Interrupt latency is defined as the time from when the

interrupt event occurs to the time code execution at the

interrupt vector begins. The latency for synchronous

interrupts is 3 or 4 instruction cycles. For asynchronous

interrupts, the latency is 3 to 5 instruction cycles,

depending on when the interrupt occurs. See Figure 8-3

and Figure 8-4 for more details.

Note 1: Individual interrupt flag bits are set,

regardless of the state of any other

enable bits.

2: All interrupts will be ignored while the GIE

bit is cleared. Any interrupt occurring

while the GIE bit is clear will be serviced

when the GIE bit is set again.

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DS41419C-page 90 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 8-3: INTERRUPT LATENCY

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT

PC 0004h 0005h

Inst(0004h)NOP

GIE

Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4

1 Cycle Instruction at PC

Inst(0004h)NOP

2 Cycle Instruction at PC

FSR ADDR PC+1 PC+2 0004h 0005h

Inst(0004h)NOP

GIE

PCPC-1

3 Cycle Instruction at PC

Execute

Interrupt

Inst(PC)

Interrupt Sampled

during Q1

Inst(PC)

PC-1 PC+1

NOP

PC New PC/

PC+1 0005hPC-1 PC+1/FSR

ADDR 0004h

NOP

Interrupt

GIE

Interrupt

INST(PC) NOPNOP

FSR ADDR PC+1 PC+2 0004h 0005h

Inst(0004h)NOP

GIE

PCPC-1

3 Cycle Instruction at PC

Interrupt

INST(PC) NOPNOP NOP

Inst(0005h)

Execute

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PIC16(L)F1824/1828

FIGURE 8-4: INT PIN INTERRUPT TIMING

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT pin

INTF

GIE

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

Interrupt Latency

PC PC + 1 PC + 1 0004h 0005h

Inst (0004h) Inst (0005h)

Dummy Cycle

Inst (PC) Inst (PC + 1)

Inst (PC – 1) Inst (0004h)

Dummy Cycle

Inst (PC)

—

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is not available in all oscillator modes.

4: For minimum width of INT pulse, refer to the AC specifications in Section 30.0 “Electrical Specifications”.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

(1)

(2)

(3)

(4)

(5)

(1)

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DS41419C-page 92 Preliminary  2010-2011 Microchip Technology Inc.

8.3 Interrupts During Sleep

Some interrupts can be used to wake from Sleep. To

wake from Sleep, the peripheral must be able to

operate without the system clock. The interrupt source

must have the appropriate Interrupt Enable bit(s) set

prior to entering Sleep.

On waking from Sleep, if the GIE bit is also set, the

processor will branch to the interrupt vector. Otherwise,

the processor will continue executing instructions after

the SLEEP instruction. The instruction directly after the

SLEEP instruction will always be executed before

branching to the ISR. Refer to the Section 9.0 “Power-

Down Mode (Sleep)” for more details.

8.4 INT Pin

The INT pin can be used to generate an asynchronous

edge-triggered interrupt. This interrupt is enabled by

setting the INTE bit of the INTCON register. The

INTEDG bit of the OPTION_REG register determines on

which edge the interrupt will occur. When the INTEDG

bit is set, the rising edge will cause the interrupt. When

the INTEDG bit is clear, the falling edge will cause the

interrupt. The INTF bit of the INTCON register will be set

when a valid edge appears on the INT pin. If the GIE and

INTE bits are also set, the processor will redirect

program execution to the interrupt vector.

8.5 Automatic Context Saving

Upon entering an interrupt, the return PC address is

saved on the stack. Additionally, the following registers

are automatically saved in the Shadow registers:

• W register

• STATUS register (except for TO and PD)

• BSR register

• FSR registers

• PCLATH register

Upon exiting the Interrupt Service Routine, these regis-

ters are automatically restored. Any modifications to

these registers during the ISR will be lost. If modifica-

tions to any of these registers are desired, the corre-

sponding Shadow register should be modified and the

value will be restored when exiting the ISR. The

Shadow registers are available in Bank 31 and are

readable and writable. Depending on the user’s appli-

cation, other registers may also need to be saved.

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PIC16(L)F1824/1828

8.5.1 INTCON REGISTER

The INTCON register is a readable and writable

for TMR0 register overflow, interrupt-on-change and

external INT pin interrupts.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE, of the INTCON

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0

GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all active interrupts

0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all active peripheral interrupts

0 = Disables all peripheral interrupts

bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit

1 = Enables the Timer0 interrupt

0 = Disables the Timer0 interrupt

bit 4 INTE: INT External Interrupt Enable bit

1 = Enables the INT external interrupt

0 = Disables the INT external interrupt

bit 3 IOCIE: Interrupt-on-Change Enable bit

1 = Enables the interrupt-on-change

0 = Disables the interrupt-on-change

bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed

0 = TMR0 register did not overflow

bit 1 INTF: INT External Interrupt Flag bit

1 = The INT external interrupt occurred

0 = The INT external interrupt did not occur

bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit(1)

1 = When at least one of the interrupt-on-change pins changed state

0 = None of the interrupt-on-change pins have changed state

Note 1: The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCxF register

have been cleared by software.

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DS41419C-page 94 Preliminary  2010-2011 Microchip Technology Inc.

8.5.2 PIE1 REGISTER

The PIE1 register contains the interrupt enable bits, as

shown in Register 8-2.

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit

1 = Enables the Timer1 Gate Acquisition interrupt

0 = Disables the Timer1 Gate Acquisition interrupt

bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit

1 = Enables the ADC interrupt

0 = Disables the ADC interrupt

bit 5 RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt

0 = Disables the USART receive interrupt

bit 4 TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt

0 = Disables the USART transmit interrupt

bit 3 SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit

1 = Enables the MSSP interrupt

0 = Disables the MSSP interrupt

bit 2 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the Timer2 to PR2 match interrupt

0 = Disables the Timer2 to PR2 match interrupt

bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt

0 = Disables the Timer1 overflow interrupt

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 95

PIC16(L)F1824/1828

8.5.3 PIE2 REGISTER

The PIE2 register contains the interrupt enable bits, as

shown in Register 8-3.

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0

OSFIE C2IE(1) C1IE EEIE BCL1IE —— CCP2IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables the Oscillator Fail interrupt

0 = Disables the Oscillator Fail interrupt

bit 6 C2IE: Comparator C2 Interrupt Enable bit(1)

1 = Enables the Comparator C2 interrupt

0 = Disables the Comparator C2 interrupt

bit 5 C1IE: Comparator C1 Interrupt Enable bit

1 = Enables the Comparator C1 interrupt

0 = Disables the Comparator C1 interrupt

bit 4 EEIE: EEPROM Write Completion Interrupt Enable bit

1 = Enables the EEPROM Write Completion interrupt

0 = Disables the EEPROM Write Completion interrupt

bit 3 BCL1IE: MSSP Bus Collision Interrupt Enable bit

1 = Enables the MSSP Bus Collision Interrupt

0 = Disables the MSSP Bus Collision Interrupt

bit 2-1 Unimplemented: Read as ‘0’

bit 0 CCP2IE: CCP2 Interrupt Enable bit

1 = Enables the CCP2 Interrupt

0 = Disables the CCP2 Interrupt

Note 1: PIC16(L)F1828 only.

PIC16(L)F1824/1828

DS41419C-page 96 Preliminary  2010-2011 Microchip Technology Inc.

8.5.4 PIE3 REGISTER

The PIE3 register contains the interrupt enable bits, as

shown in Register 8-4.

Note 1: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 U-0

—— CCP4IE CCP3IE TMR6IE —TMR4IE—

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5 CCP4IE: CCP4 Interrupt Enable bit

1 = Enables the CCP4 interrupt

0 = Disables the CCP4 interrupt

bit 4 CCP3IE: CCP3 Interrupt Enable bit

1 = Enables the CCP3 interrupt

0 = Disables the CCP3 interrupt

bit 3 TMR6IE: TMR6 to PR6 Match Interrupt Enable bit

1 = Enables the TMR6 to PR6 Match interrupt

0 = Disables the TMR6 to PR6 Match interrupt

bit 2 Unimplemented: Read as ‘0’

bit 1 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit

1 = Enables the TMR4 to PR4 Match interrupt

0 = Disables the TMR4 to PR4 Match interrupt

bit 0 Unimplemented: Read as ‘0’

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 97

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8.5.5 PIR1 REGISTER

The PIR1 register contains the interrupt flag bits, as

shown in Register 8-5.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE, of the INTCON

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 5 RCIF: USART Receive Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 4 TXIF: USART Transmit Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 3 SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 2 CCP1IF: CCP1 Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

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DS41419C-page 98 Preliminary  2010-2011 Microchip Technology Inc.

8.5.6 PIR2 REGISTER

The PIR2 register contains the interrupt flag bits, as

shown in Register 8-6.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE, of the INTCON

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0

OSFIF C2IF(1) C1IF EEIF BCL1IF —— CCP2IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 OSFIF: Oscillator Fail Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 6 C2IF: Comparator C2 Interrupt Flag bit(1)

1 = Interrupt is pending

0 = Interrupt is not pending

bit 5 C1IF: Comparator C1 Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 4 EEIF: EEPROM Write Completion Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 3 BCL1IF: MSSP Bus Collision Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 2-1 Unimplemented: Read as ‘0’

bit 0 CCP2IF: CCP2 Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

Note 1: PIC16(L)F1828 only.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 99

PIC16(L)F1824/1828

8.5.7 PIR3 REGISTER

The PIR3 register contains the interrupt flag bits, as

shown in Register 8-7.

Note 1: Interrupt flag bits are set when an inter-

rupt condition occurs, regardless of the

state of its corresponding enable bit or

the Global Interrupt Enable bit, GIE, of

the INTCON register. User software

should ensure the appropriate interrupt

flag bits are clear prior to enabling an

interrupt.

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 U-0

—— CCP4IF CCP3IF TMR6IF —TMR4IF—

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5 CCP4IF: CCP4 Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 4 CCP3IF: CCP3 Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 3 TMR6IF: TMR6 to PR6 Match Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 2 Unimplemented: Read as ‘0’

bit 1 TMR4IF: TMR4 to PR4 Match Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 0 Unimplemented: Read as ‘0’

PIC16(L)F1824/1828

DS41419C-page 100 Preliminary  2010-2011 Microchip Technology Inc.

TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93

OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 187

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 94

PIE2 OSFIE C2IE C1IE EEIE BCL1IE —— CCP2IE 95

PIE3 —— CCP4IE CCP3IE TMR6IE —TMR4IE—96

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 97

PIR2 OSFIF C2IF C1IF EEIF BCL1IF —— CCP2IF 98

PIR3 —— CCP4IF CCP3IF TMR6IF —TMR4IF—99

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 101

PIC16(L)F1824/1828

9.0 POWER-DOWN MODE (SLEEP)

The Power-Down mode is entered by executing a

SLEEP instruction.

Upon entering Sleep mode, the following conditions

exist:

1. WDT will be cleared but keeps running, if

enabled for operation during Sleep.

2. PD bit of the STATUS register is cleared.

3. TO bit of the STATUS register is set.

4. CPU clock is disabled.

5. 31 kHz LFINTOSC is unaffected and peripherals

that operate from it may continue operation in

Sleep.

6. Timer1 oscillator is unaffected and peripherals

that operate from it may continue operation in

Sleep.

7. ADC is unaffected, if the dedicated FRC clock is

selected.

8. Capacitive Sensing oscillator is unaffected.

9. I/O ports maintain the status they had before

SLEEP was executed (driving high, low or high-

impedance).

10. Resets other than WDT are not affected by

Sleep mode.

Refer to individual chapters for more details on

peripheral operation during Sleep.

To minimize current consumption, the following condi-

tions should be considered:

• I/O pins should not be floating

• External circuitry sinking current from I/O pins

• Internal circuitry sourcing current from I/O pins

• Current draw from pins with internal weak pull-ups

• Modules using 31 kHz LFINTOSC

• Modules using Timer1 oscillator

I/O pins that are high-impedance inputs should be

pulled to VDD or VSS externally to avoid switching

currents caused by floating inputs.

Examples of internal circuitry that might be sourcing

current include modules such as the DAC and FVR

modules. See Section 17.0 “Digital-to-Analog

Converter (DAC) Module” and Section 14.0 “Fixed

Voltage Reference (FVR)” for more information on

these modules.

9.1 Wake-up from Sleep

The device can wake-up from Sleep through one of the

following events:

1. External Reset input on MCLR pin, if enabled

2. BOR Reset, if enabled

3. POR Reset

4. Watchdog Timer, if enabled

5. Any external interrupt

6. Interrupts by peripherals capable of running dur-

ing Sleep (see individual peripheral for more

information)

The first three events will cause a device Reset. The

last three events are considered a continuation of pro-

gram execution. To determine whether a device Reset

or wake-up event occurred, refer to Section 7.10

“Determining the Cause of a Reset”.

When the SLEEP instruction is being executed, the next

instruction (PC + 1) is prefetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be enabled. Wake-up will

occur regardless of the state of the GIE bit. If the GIE

bit is disabled, the device continues execution at the

instruction after the SLEEP instruction. If the GIE bit is

enabled, the device executes the instruction after the

SLEEP instruction, the device will call the Interrupt Ser-

vice Routine. In cases where the execution of the

instruction following SLEEP is not desirable, the user

should have a NOP after the SLEEP instruction.

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

9.1.1 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

• If the interrupt occurs before the execution of a

SLEEP instruction

-SLEEP instruction will execute as a NOP

- WDT and WDT prescaler will not be cleared

-TO

bit of the STATUS register will not be set

-PD bit of the STATUS register will not be

cleared

• If the interrupt occurs during or after the

execution of a SLEEP instruction

-SLEEP instruction will be completely executed

- Device will immediately wake-up from Sleep

- WDT and WDT prescaler will be cleared

-TO

bit of the STATUS register will be set

-PD bit of the STATUS register will be cleared

PIC16(L)F1824/1828

DS41419C-page 102 Preliminary  2010-2011 Microchip Technology Inc.

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEP instruction completes. To

determine whether a SLEEP instruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

FIGURE 9-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT

TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1(1)

CLKOUT(2)

Interrupt flag

GIE bit

(INTCON reg.)

Instruction Flow

Instruction

Fetched

Instruction

Executed

PC PC + 1 PC + 2

Inst(PC) = Sleep

Inst(PC - 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency(4)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h) Inst(0005h)

Inst(0004h)

Dummy Cycle

PC + 2 0004h 0005h

Dummy Cycle

TOST(3)

PC + 2

Note 1: XT, HS or LP Oscillator mode assumed.

2: CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference.

3: TOST = 1024 TOSC (drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes.

4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on

Page

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93

IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 142

IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 142

IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 142

IOCBF(1) IOCBF7 IOCBF6 IOCBF5 IOCBF4 ———— 144

IOCBN(1) IOCBN7 IOCBN6 IOCBN5 IOCBN4 ———— 143

IOCBP(1) IOCBP7 IOCBP6 IOCBP5 IOCBP4 ———— 143

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 94

PIE2 OSFIE C2IE C1IE EEIE BCL1IE ——CCP2IE 95

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 97

PIR2 OSFIF C2IF C1IF EEIF BCL1IF — — CCP2IF 98

STATUS — — —TOPD ZDC C26

WDTCON —— WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN 105

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode.

Note 1: PIC16F/LF1828 only.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 103

PIC16(L)F1824/1828

10.0 WATCHDOG TIMER

The Watchdog Timer is a system timer that generates

a Reset if the firmware does not issue a CLRWDT

instruction within the time-out period. The Watchdog

Timer is typically used to recover the system from

unexpected events.

The WDT has the following features:

• Independent clock source

• Multiple operating modes

- WDT is always on

- WDT is off when in Sleep

- WDT is controlled by software

- WDT is always off

• Configurable time-out period is from 1ms to 256

seconds (typical)

• Multiple Reset conditions

• Operation during Sleep

FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM

LFINTOSC 23-bit Programmable

Prescaler WDT WDT Time-out

WDTPS<4:0>

SWDTEN

Sleep

WDTE<1:0> = 11

WDTE<1:0> = 01

WDTE<1:0> = 10

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DS41419C-page 104 Preliminary  2010-2011 Microchip Technology Inc.

10.1 Independent Clock Source

The WDT derives its time base from the 31 kHz

LFINTOSC internal oscillator.

10.2 WDT Operating Modes

The Watchdog Timer module has four operating modes

controlled by the WDTE<1:0> bits in Configuration

Word 1. See Table 10-1.

10.2.1 WDT IS ALWAYS ON

When the WDTE bits of Configuration Word 1 are set to

‘11’, the WDT is always on.

WDT protection is active during Sleep.

10.2.2 WDT IS OFF IN SLEEP

When the WDTE bits of Configuration Word 1 are set to

‘10’, the WDT is on, except in Sleep.

WDT protection is not active during Sleep.

10.2.3 WDT CONTROLLED BY SOFTWARE

When the WDTE bits of Configuration Word 1 are set to

‘01’, the WDT is controlled by the SWDTEN bit of the

WDTCON register.

WDT protection is unchanged by Sleep. See

Table 10-1 for more details.

TABLE 10-1: WDT OPERATING MODES

10.3 Time-Out Period

The WDTPS bits of the WDTCON register set the

time-out period from 1ms to 256 seconds. After a

Reset, the default time-out period is 2 seconds.

10.4 Clearing the WDT

The WDT is cleared when any of the following condi-

tions occur:

•Any Reset

•CLRWDT instruction is executed

• Device enters Sleep

• Device wakes up from Sleep

• Oscillator fail event

• WDT is disabled

•OST is running

See Table 10-2 for more information.

10.5 Operation During Sleep

When the device enters Sleep, the WDT is cleared. If

the WDT is enabled during Sleep, the WDT resumes

counting.

When the device exits Sleep, the WDT is cleared

again. The WDT remains clear until the OST, if

enabled, completes. See Section 5.0 “Oscillator

Module (With Fail-Safe Clock Monitor)” for more

information on the OST.

When a WDT time-out occurs while the device is in

Sleep, no Reset is generated. Instead, the device

wakes up and resumes operation. The TO and PD bits

in the STATUS register are changed to indicate the

event. See Section 3.0 “Memory Organization” and

The STATUS register (Register 3-1) for more

information.

WDTE

Config bits SWDTEN Device

Mode

WDT

Mode

WDT_ON (11)XXActive

WDT_NSLEEP (10) X Awake Active

WDT_NSLEEP (10)XSleep Disabled

WDT_SWDTEN (01)1XActive

WDT_SWDTEN (01)0XDisabled

WDT_OFF (00)XXDisabled

TABLE 10-2: WDT CLEARING CONDITIONS

Conditions WDT

WDTE<1:0> = 00

Cleared

WDTE<1:0> = 01 and SWDTEN = 0

WDTE<1:0> = 10 and enter Sleep

CLRWDT Command

Oscillator Fail Detected

Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK

Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST

Change INTOSC divider (IRCF bits) Unaffected

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 105

PIC16(L)F1824/1828

U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0

—— WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits

Bit Value = Prescale Rate

00000 = 1:32 (Interval 1 ms typ)

00001 = 1:64 (Interval 2 ms typ)

00010 = 1:128 (Interval 4 ms typ)

00011 = 1:256 (Interval 8 ms typ)

00100 = 1:512 (Interval 16 ms typ)

00101 = 1:1024 (Interval 32 ms typ)

00110 = 1:2048 (Interval 64 ms typ)

00111 = 1:4096 (Interval 128 ms typ)

01000 = 1:8192 (Interval 256 ms typ)

01001 = 1:16384 (Interval 512 ms typ)

01010 = 1:32768 (Interval 1s typ)

01011 = 1:65536 (Interval 2s typ) (Reset value)

01100 = 1:131072 (217) (Interval 4s typ)

01101 = 1:262144 (218) (Interval 8s typ)

01110 = 1:524288 (219) (Interval 16s typ)

01111 = 1:1048576 (220) (Interval 32s typ)

10000 = 1:2097152 (221) (Interval 64s typ)

10001 = 1:4194304 (222) (Interval 128s typ)

10010 = 1:8388608 (223) (Interval 256s typ)

10011 = Reserved. Results in minimum interval (1:32)

•

11111 = Reserved. Results in minimum interval (1:32)

bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit

If WDTE<1:0> = 00:

This bit is ignored.

If WDTE<1:0> = 01:

1 = WDT is turned on

0 = WDT is turned off

If WDTE<1:0> = 1x:

This bit is ignored.

PIC16(L)F1824/1828

DS41419C-page 106 Preliminary  2010-2011 Microchip Technology Inc.

NOTES:

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 107

PIC16(L)F1824/1828

11.0 DATA EEPROM AND FLASH

PROGRAM MEMORY

CONTROL

The data EEPROM and Flash program memory are

readable and writable during normal operation (full VDD

range). These memories are not directly mapped in the

addressed through the Special Function Registers

(SFRs). There are six SFRs used to access these

memories:

• EECON1

• EECON2

• EEDATL

•EEDATH

• EEADRL

•EEADRH

When interfacing the data memory block, EEDATL

holds the 8-bit data for read/write, and EEADRL holds

the address of the EEDATL location being accessed.

These devices have 256 bytes of data EEPROM with

an address range from 0h to 0FFh.

When accessing the program memory block, the

EEDATH:EEDATL register pair forms a 2-byte word

that holds the 14-bit data for read/write, and the

EEADRL and EEADRH registers form a 2-byte word

that holds the 15-bit address of the program memory

location being read.

The EEPROM data memory allows byte read and write.

An EEPROM byte write automatically erases the loca-

tion and writes the new data (erase before write).

The write time is controlled by an on-chip timer. The

write/erase voltages are generated by an on-chip

charge pump rated to operate over the voltage range of

the device for byte or word operations.

Depending on the setting of the Flash Program

Memory Self Write Enable bits WRT<1:0> of the

Configuration Word 2, the device may or may not be

able to write certain blocks of the program memory.

However, reads from the program memory are always

allowed.

When the device is code-protected, the device

programmer can no longer access data or program

memory. When code-protected, the CPU may continue

to read and write the data EEPROM memory and Flash

program memory.

11.1 EEADRL and EEADRH Registers

The EEADRH:EEADRL register pair can address up to

a maximum of 256 bytes of data EEPROM or up to a

maximum of 32K words of program memory.

When selecting a program address value, the MSB of

the address is written to the EEADRH register and the

LSB is written to the EEADRL register. When selecting

a EEPROM address value, only the LSB of the address

is written to the EEADRL register.

11.1.1 EECON1 AND EECON2 REGISTERS

EECON1 is the control register for EE memory

accesses.

Control bit EEPGD determines if the access will be a

program or data memory access. When clear, any

subsequent operations will operate on the EEPROM

memory. When set, any subsequent operations will

operate on the program memory. On Reset, EEPROM is

selected by default.

Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, only set, in

software. They are cleared in hardware at completion

of the read or write operation. The inability to clear the

WR bit in software prevents the accidental, premature

termination of a write operation.

The WREN bit, when set, will allow a write operation to

occur. On power-up, the WREN bit is clear. The

WRERR bit is set when a write operation is interrupted

by a Reset during normal operation. In these situations,

following Reset, the user can check the WRERR bit

and execute the appropriate error handling routine.

Interrupt flag bit EEIF of the PIR2 register is set when

the write is complete. It must be cleared in the software.

Reading EECON2 will read all ‘0’s. The EECON2 reg-

ister is used exclusively in the data EEPROM write

sequence. To enable writes, a specific pattern must be

written to EECON2.

PIC16(L)F1824/1828

DS41419C-page 108 Preliminary  2010-2011 Microchip Technology Inc.

11.2 Using the Data EEPROM

The data EEPROM is a high-endurance, byte address-

able array that has been optimized for the storage of

frequently changing information (e.g., program vari-

ables or other data that are updated often). When vari-

ables in one section change frequently, while variables

in another section do not change, it is possible to

exceed the total number of write cycles to the

EEPROM without exceeding the total number of write

cycles to a single byte. Refer to Section 30.0 “Electri-

cal Specifications”. If this is the case, then a refresh

of the array must be performed. For this reason, vari-

ables that change infrequently (such as constants, IDs,

calibration, etc.) should be stored in Flash program

memory.

11.2.1 READING THE DATA EEPROM

MEMORY

To read a data memory location, the user must write the

address to the EEADRL register, clear the EEPGD and

CFGS control bits of the EECON1 register, and then

set control bit RD. The data is available at the very next

cycle, in the EEDATL register; therefore, it can be read

in the next instruction. EEDATL will hold this value until

another read or until it is written to by the user (during

a write operation).

EXAMPLE 11-1: DATA EEPROM READ

11.2.2 WRITING TO THE DATA EEPROM

MEMORY

To write an EEPROM data location, the user must first

write the address to the EEADRL register and the data

to the EEDATL register. Then the user must follow a

specific sequence to initiate the write for each byte.

The write will not initiate if the above sequence is not

followed exactly (write 55h to EECON2, write AAh to

EECON2, then set WR bit) for each byte. Interrupts

should be disabled during this code segment.

Additionally, the WREN bit in EECON1 must be set to

enable write. This mechanism prevents accidental

writes to data EEPROM due to errant (unexpected)

code execution (i.e., lost programs). The user should

keep the WREN bit clear at all times, except when

updating EEPROM. The WREN bit is not cleared

by hardware.

After a write sequence has been initiated, clearing the

WREN bit will not affect this write cycle. The WR bit will

be inhibited from being set unless the WREN bit is set.

At the completion of the write cycle, the WR bit is

cleared in hardware and the EE Write Complete

Interrupt Flag bit (EEIF) is set. The user can either

enable this interrupt or poll this bit. EEIF must be

cleared by software.

11.2.3 PROTECTION AGAINST SPURIOUS

WRITE

There are conditions when the user may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built-in. On power-up, WREN is cleared. Also, the

Power-up Timer (64 ms duration) prevents EEPROM

write.

The write initiate sequence and the WREN bit together

help prevent an accidental write during:

• Brown-out

• Power Glitch

• Software Malfunction

11.2.4 DATA EEPROM OPERATION

DURING CODE-PROTECT

Data memory can be code-protected by programming

the CPD bit in the Configuration Word 1 (Register 5-1)

to ‘0’.

When the data memory is code-protected, only the

CPU is able to read and write data to the data

EEPROM. It is recommended to code-protect the pro-

gram memory when code-protecting data memory.

This prevents anyone from replacing your program with

a program that will access the contents of the data

EEPROM.

Note: Data EEPROM can be read regardless of

the setting of the CPD bit.

BANKSEL EEADRL ;

MOVLW DATA_EE_ADDR ;

MOVWF EEADRL ;Data Memory

;Address to read

BCF EECON1, CFGS ;Deselect Config space

BCF EECON1, EEPGD;Point to DATA memory

BSF EECON1, RD ;EE Read

MOVF EEDATL, W ;W = EEDATL

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 109

PIC16(L)F1824/1828

EXAMPLE 11-2: DATA EEPROM WRITE

FIGURE 11-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION

BANKSEL EEADRL ;

MOVLW DATA_EE_ADDR ;

MOVWF EEADRL ;Data Memory Address to write

MOVLW DATA_EE_DATA ;

MOVWF EEDATL ;Data Memory Value to write

BCF EECON1, CFGS ;Deselect Configuration space

BCF EECON1, EEPGD ;Point to DATA memory

BSF EECON1, WREN ;Enable writes

BCF INTCON, GIE ;Disable INTs.

MOVLW 55h ;

MOVWF EECON2 ;Write 55h

MOVLW 0AAh ;

MOVWF EECON2 ;Write AAh

BSF EECON1, WR ;Set WR bit to begin write

BSF INTCON, GIE ;Enable Interrupts

BCF EECON1, WREN ;Disable writes

BTFSC EECON1, WR ;Wait for write to complete

GOTO $-2 ;Done

Required

Sequence

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

BSF EECON1,RD

executed here INSTR(PC + 1)

executed here Forced NOP

executed here

PC + 1 EEADRH,EEADRL PC+3 PC + 5

Flash ADDR

RD bit

EEDATH,EEDATL

PC + 3 PC + 4

INSTR (PC + 1)

INSTR(PC - 1)

executed here INSTR(PC + 3)

executed here INSTR(PC + 4)

executed here

Flash Data

EEDATH

EEDATL

EERHLT

INSTR (PC) INSTR (PC + 3) INSTR (PC + 4)

PIC16(L)F1824/1828

DS41419C-page 110 Preliminary  2010-2011 Microchip Technology Inc.

11.3 Flash Program Memory Overview

It is important to understand the Flash program

memory structure for erase and programming

operations. Flash program memory is arranged in

rows. A row consists of a fixed number of 14-bit

program memory words. A row is the minimum block

size that can be erased by user software.

Flash program memory may only be written or erased

if the destination address is in a segment of memory

that is not write-protected, as defined in bits WRT<1:0>

of Configuration Word 2.

After a row has been erased, the user can reprogram

all or a portion of this row. Data to be written into the

program memory row is written to 14-bit wide data write

latches. These write latches are not directly accessible

to the user, but may be loaded via sequential writes to

the EEDATH:EEDATL register pair.

The number of data write latches is not equivalent to

the number of row locations. During programming, user

software will need to fill the set of write latches and ini-

tiate a programming operation multiple times in order to

fully reprogram an erased row. For example, a device

with a row size of 32 words and eight write latches will

need to load the write latches with data and initiate a

programming operation four times.

The size of a program memory row and the number of

program memory write latches may vary by device.

See Table 11-1 for details.

11.3.1 READING THE FLASH PROGRAM

MEMORY

To read a program memory location, the user must:

1. Write the Least and Most Significant address

bits to the EEADRH:EEADRL register pair.

2. Clear the CFGS bit of the EECON1 register.

3. Set the EEPGD control bit of the EECON1

4. Then, set control bit RD of the EECON1 register.

Once the read control bit is set, the program memory

Flash controller will use the second instruction cycle to

read the data. This causes the second instruction

immediately following the “BSF EECON1,RD” instruction

to be ignored. The data is available in the very next cycle,

in the EEDATH:EEDATL register pair; therefore, it can

be read as two bytes in the following instructions.

EEDATH:EEDATL register pair will hold this value until

another read or until it is written to by the user.

Note: If the user wants to modify only a portion

of a previously programmed row, then the

contents of the entire row must be read

and saved in RAM prior to the erase.

TABLE 11-1: FLASH MEMORY

ORGANIZATION BY DEVICE

Device

Erase Block

(Row) Size/

Boundary

Number of

Write Latches/

Boundary

PIC16(L)F1824/

1828

32 words,

EEADRL<4:0>

= 00000

32 words,

EEADRL<4:0>

= 00000

Note 1: The two instructions following a program

memory read are required to be NOPs.

This prevents the user from executing a

two-cycle instruction on the next

instruction after the RD bit is set.

2: Flash program memory can be read

regardless of the setting of the CP bit.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 111

PIC16(L)F1824/1828

EXAMPLE 11-3: FLASH PROGRAM MEMORY READ

* This code block will read 1 word of program

* memory at the memory address:

PROG_ADDR_HI : PROG_ADDR_LO

* data will be returned in the variables;

* PROG_DATA_HI, PROG_DATA_LO

BANKSEL EEADRL ; Select Bank for EEPROM registers

MOVLW PROG_ADDR_LO ;

MOVWF EEADRL ; Store LSB of address

MOVLW PROG_ADDR_HI ;

MOVWL EEADRH ; Store MSB of address

BCF EECON1,CFGS ; Do not select Configuration Space

BSF EECON1,EEPGD ; Select Program Memory

BCF INTCON,GIE ; Disable interrupts

BSF EECON1,RD ; Initiate read

NOP ; Executed (Figure 11-1)

NOP ; Ignored (Figure 11-1)

BSF INTCON,GIE ; Restore interrupts

MOVF EEDATL,W ; Get LSB of word

MOVWF PROG_DATA_LO ; Store in user location

MOVF EEDATH,W ; Get MSB of word

MOVWF PROG_DATA_HI ; Store in user location

PIC16(L)F1824/1828

DS41419C-page 112 Preliminary  2010-2011 Microchip Technology Inc.

11.3.2 ERASING FLASH PROGRAM

MEMORY

While executing code, program memory can only be

erased by rows. To erase a row:

1. Load the EEADRH:EEADRL register pair with

the address of the new row to be erased.

2. Clear the CFGS bit of the EECON1 register.

3. Set the EEPGD, FREE and WREN bits of the

EECON1 register.

4. Write 55h, then AAh, to EECON2 (Flash

programming unlock sequence).

5. Set control bit WR of the EECON1 register to

begin the erase operation.

6. Poll the FREE bit in the EECON1 register to

determine when the row erase has completed.

See Example 11-4.

After the “BSF EECON1,WR” instruction, the processor

requires two cycles to set up the erase operation. The

user must place two NOP instructions after the WR bit is

set. The processor will halt internal operations for the

typical 2ms erase time. This is not Sleep mode, as the

clocks and peripherals will continue to run. After the

erase cycle, the processor will resume operation with

the third instruction after the EECON1 write instruction.

11.3.3 WRITING TO FLASH PROGRAM

MEMORY

Program memory is programmed using the following

steps:

1. Load the starting address of the word(s) to be

programmed.

2. Load the write latches with data.

3. Initiate a programming operation.

4. Repeat steps 1 through 3 until all data is written.

Before writing to program memory, the word(s) to be

written must be erased or previously unwritten. Pro-

gram memory can only be erased one row at a time. No

automatic erase occurs upon the initiation of the write.

Program memory can be written one or more words at

a time. The maximum number of words written at one

time is equal to the number of write latches. See

Figure 11-2 (block writes to program memory with 32

write latches) for more details. The write latches are

aligned to the address boundary defined by EEADRL

as shown in Ta bl e 11 - 1 . Write operations do not cross

these boundaries. At the completion of a program

memory write operation, the write latches are reset to

contain 0x3FFF.

The following steps should be completed to load the

write latches and program a block of program memory.

These steps are divided into two parts. First, all write

latches are loaded with data except for the last program

memory location. Then, the last write latch is loaded

and the programming sequence is initiated. A special

unlock sequence is required to load a write latch with

data or initiate a Flash programming operation. This

unlock sequence should not be interrupted.

1. Set the EEPGD and WREN bits of the EECON1

2. Clear the CFGS bit of the EECON1 register.

3. Set the LWLO bit of the EECON1 register. When

the LWLO bit of the EECON1 register is ‘1’, the

write sequence will only load the write latches

and will not initiate the write to Flash program

memory.

4. Load the EEADRH:EEADRL register pair with

the address of the location to be written.

5. Load the EEDATH:EEDATL register pair with

the program memory data to be written.

6. Write 55h, then AAh, to EECON2, then set the

WR bit of the EECON1 register (Flash

programming unlock sequence). The write latch

is now loaded.

7. Increment the EEADRH:EEADRL register pair

to point to the next location.

8. Repeat steps 5 through 7 until all but the last

write latch has been loaded.

9. Clear the LWLO bit of the EECON1 register.

When the LWLO bit of the EECON1 register is

‘0’, the write sequence will initiate the write to

Flash program memory.

10. Load the EEDATH:EEDATL register pair with

the program memory data to be written.

11. Write 55h, then AAh, to EECON2, then set the

WR bit of the EECON1 register (Flash

programming unlock sequence). The entire

latch block is now written to Flash program

memory.

It is not necessary to load the entire write latch block

with user program data. However, the entire write latch

block will be written to program memory.

An example of the complete write sequence for eight

words is shown in Example 11-5. The initial address is

loaded into the EEADRH:EEADRL register pair; the

eight words of data are loaded using indirect addressing.

Note: If the number of write latches is smaller

than the erase block size, the code

sequence provided in Example 11-5 may

be repeated multiple times to fully pro-

gram an erased program memory row.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 113

PIC16(L)F1824/1828

After the “BSF EECON1,WR” instruction, the processor

requires two cycles to set up the write operation. The

user must place two NOP instructions after the WR bit is

set. The processor will halt internal operations for the

typical 2ms, only during the cycle in which the write

takes place (i.e., the last word of the block write). This

is not Sleep mode, as the clocks and peripherals will

continue to run. The processor does not stall when

LWLO = 1, loading the write latches. After the write

cycle, the processor will resume operation with the third

instruction after the EECON1 write instruction.

FIGURE 11-2: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES

14 14 14 14

Program Memory

Buffer Register

EEADRL<4:0> = 00000

Buffer Register

EEADRL<4:0> = 00001

Buffer Register

EEADRL<4:0> = 00010

Buffer Register

EEADRL<4:0> = 11111

EEDATA

EEDATH

75 07 0

First word of block

to be written

Last word of block

to be written

PIC16(L)F1824/1828

DS41419C-page 114 Preliminary  2010-2011 Microchip Technology Inc.

EXAMPLE 11-4: ERASING ONE ROW OF PROGRAM MEMORY

; This row erase routine assumes the following:

; 1. A valid address within the erase block is loaded in ADDRH:ADDRL

; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F

BCF INTCON,GIE ; Disable ints so required sequences will execute properly

BANKSEL EEADRL

MOVF ADDRL,W ; Load lower 8 bits of erase address boundary

MOVWF EEADRL

MOVF ADDRH,W ; Load upper 6 bits of erase address boundary

MOVWF EEADRH

BSF EECON1,EEPGD ; Point to program memory

BCF EECON1,CFGS ; Not configuration space

BSF EECON1,FREE ; Specify an erase operation

BSF EECON1,WREN ; Enable writes

MOVLW 55h ; Start of required sequence to initiate erase

MOVWF EECON2 ; Write 55h

MOVLW 0AAh ;

MOVWF EECON2 ; Write AAh

BSF EECON1,WR ; Set WR bit to begin erase

NOP ; Any instructions here are ignored as processor

; halts to begin erase sequence

NOP ; Processor will stop here and wait for erase complete.

; after erase processor continues with 3rd instruction

BCF EECON1,WREN ; Disable writes

BSF INTCON,GIE ; Enable interrupts

Required

Sequence

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 115

PIC16(L)F1824/1828

EXAMPLE 11-5: WRITING TO FLASH PROGRAM MEMORY

; This write routine assumes the following:

; 1. The 16 bytes of data are loaded, starting at the address in DATA_ADDR

; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,

; stored in little endian format

; 3. A valid starting address (the least significant bits = 000) is loaded in ADDRH:ADDRL

; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F

;

BCF INTCON,GIE ; Disable ints so required sequences will execute properly

BANKSEL EEADRH ; Bank 3

MOVF ADDRH,W ; Load initial address

MOVWF EEADRH ;

MOVF ADDRL,W ;

MOVWF EEADRL ;

MOVLW LOW DATA_ADDR ; Load initial data address

MOVWF FSR0L ;

MOVLW HIGH DATA_ADDR ; Load initial data address

MOVWF FSR0H ;

BSF EECON1,EEPGD ; Point to program memory

BCF EECON1,CFGS ; Not configuration space

BSF EECON1,WREN ; Enable writes

BSF EECON1,LWLO ; Only Load Write Latches

LOOP

MOVIW FSR0++ ; Load first data byte into lower

MOVWF EEDATL ;

MOVIW FSR0++ ; Load second data byte into upper

MOVWF EEDATH ;

MOVF EEADRL,W ; Check if lower bits of address are '000'

XORLW 0x07 ; Check if we're on the last of 8 addresses

ANDLW 0x07 ;

BTFSC STATUS,Z ; Exit if last of eight words,

GOTO START_WRITE ;

MOVLW 55h ; Start of required write sequence:

MOVWF EECON2 ; Write 55h

MOVLW 0AAh ;

MOVWF EECON2 ; Write AAh

BSF EECON1,WR ; Set WR bit to begin write

NOP ; Any instructions here are ignored as processor

; halts to begin write sequence

NOP ; Processor will stop here and wait for write to complete.

; After write processor continues with 3rd instruction.

INCF EEADRL,F ; Still loading latches Increment address

GOTO LOOP ; Write next latches

START_WRITE

BCF EECON1,LWLO ; No more loading latches - Actually start Flash program

; memory write

MOVLW 55h ; Start of required write sequence:

MOVWF EECON2 ; Write 55h

MOVLW 0AAh ;

MOVWF EECON2 ; Write AAh

BSF EECON1,WR ; Set WR bit to begin write

NOP ; Any instructions here are ignored as processor

; halts to begin write sequence

NOP ; Processor will stop here and wait for write complete.

; after write processor continues with 3rd instruction

BCF EECON1,WREN ; Disable writes

BSF INTCON,GIE ; Enable interrupts

Required

Sequence

Required

Sequence

PIC16(L)F1824/1828

DS41419C-page 116 Preliminary  2010-2011 Microchip Technology Inc.

11.4 Modifying Flash Program Memory

When modifying existing data in a program memory

row, and data within that row must be preserved, it must

first be read and saved in a RAM image. Program

memory is modified using the following steps:

1. Load the starting address of the row to be mod-

ified.

2. Read the existing data from the row into a RAM

image.

3. Modify the RAM image to contain the new data

to be written into program memory.

4. Load the starting address of the row to be rewrit-

ten.

5. Erase the program memory row.

6. Load the write latches with data from the RAM

image.

7. Initiate a programming operation.

8. Repeat steps 6 and 7 as many times as required

to reprogram the erased row.

11.5 User ID, Device ID and

Configuration Word Access

Instead of accessing program memory or EEPROM

data memory, the User ID’s, Device ID/Revision ID and

Configuration Words can be accessed when CFGS = 1

in the EECON1 register. This is the region that would

be pointed to by PC<15> = 1, but not all addresses are

accessible. Different access may exist for reads and

writes. Refer to Table 11-2.

When read access is initiated on an address outside the

parameters listed in Table 11-2, the EEDATH:EEDATL

TABLE 11-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)

EXAMPLE 11-3: CONFIGURATION WORD AND DEVICE ID ACCESS

Address Function Read Access Write Access

8000h-8003h User IDs Yes Yes

8006h Device ID/Revision ID Yes No

8007h-8008h Configuration Words 1 and 2 Yes No

* This code block will read 1 word of program memory at the memory address:

* PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;

* PROG_DATA_HI, PROG_DATA_LO

BANKSEL EEADRL ; Select correct Bank

MOVLW PROG_ADDR_LO ;

MOVWF EEADRL ; Store LSB of address

CLRF EEADRH ; Clear MSB of address

BSF EECON1,CFGS ; Select Configuration Space

BCF INTCON,GIE ; Disable interrupts

BSF EECON1,RD ; Initiate read

NOP ; Executed (See Figure 11-1)

NOP ; Ignored (See Figure 11-1)

BSF INTCON,GIE ; Restore interrupts

MOVF EEDATL,W ; Get LSB of word

MOVWF PROG_DATA_LO ; Store in user location

MOVF EEDATH,W ; Get MSB of word

MOVWF PROG_DATA_HI ; Store in user location

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 117

PIC16(L)F1824/1828

11.6 Write Verify

Depending on the application, good programming

practice may dictate that the value written to the data

EEPROM or program memory should be verified (see

Example 11-6) to the desired value to be written.

Example 11-6 shows how to verify a write to EEPROM.

EXAMPLE 11-6: EEPROM WRITE VERIFY

BANKSEL EEDATL ;

MOVF EEDATL, W ;EEDATL not changed

;from previous write

BSF EECON1, RD ;YES, Read the

;value written

XORWF EEDATL, W ;

BTFSS STATUS, Z ;Is data the same

GOTO WRITE_ERR ;No, handle error

: ;Yes, continue

PIC16(L)F1824/1828

DS41419C-page 118 Preliminary  2010-2011 Microchip Technology Inc.

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

EEDAT<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 EEDAT<7:0>: Read/write value for EEPROM data byte or Least Significant bits of program memory

U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

—— EEDAT<13:8>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 EEDAT<13:8>: Read/write value for Most Significant bits of program memory

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

EEADR<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 EEADR<7:0>: Specifies the Least Significant bits for program memory address or EEPROM address

U-1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— EEADR<14:8>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘0’

bit 6-0 EEADR<14:8>: Specifies the Most Significant bits for program memory address or EEPROM address

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 119

PIC16(L)F1824/1828

R/W-0/0 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W-x/q R/W-0/0 R/S/HC-0/0 R/S/HC-0/0

EEPGD CFGS LWLO FREE WRERR WREN WR RD

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware

bit 7 EEPGD: Flash Program/Data EEPROM Memory Select bit

1 = Accesses program space Flash memory

0 = Accesses data EEPROM memory

bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit

1 = Accesses Configuration, User ID and Device ID Registers

0 = Accesses Flash Program or data EEPROM Memory

bit 5 LWLO: Load Write Latches Only bit

If CFGS = 1 (Configuration space) OR CFGS = 0 and EEPGD = 1 (program Flash):

1 = The next WR command does not initiate a write; only the program memory latches are

updated.

0 = The next WR command writes a value from EEDATH:EEDATL into program memory latches

and initiates a write of all the data stored in the program memory latches.

If CFGS = 0 and EEPGD = 0: (Accessing data EEPROM)

LWLO is ignored. The next WR command initiates a write to the data EEPROM.

bit 4 FREE: Program Flash Erase Enable bit

If CFGS = 1 (Configuration space) OR CFGS = 0 and EEPGD = 1 (program Flash):

1 = Performs an erase operation on the next WR command (cleared by hardware after comple-

tion of erase).

0 = Performs a write operation on the next WR command.

If EEPGD = 0 and CFGS = 0: (Accessing data EEPROM)

FREE is ignored. The next WR command will initiate both a erase cycle and a write cycle.

bit 3 WRERR: EEPROM Error Flag bit

1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set

automatically on any set attempt (write ‘1’) of the WR bit).

0 = The program or erase operation completed normally

bit 2 WREN: Program/Erase Enable bit

1 = Allows program/erase cycles

0 = Inhibits programming/erasing of program Flash and data EEPROM

bit 1 WR: Write Control bit

1 = Initiates a program Flash or data EEPROM program/erase operation.

The operation is self-timed and the bit is cleared by hardware once operation is complete.

The WR bit can only be set (not cleared) in software.

0 = Program/erase operation to the Flash or data EEPROM is complete and inactive.

bit 0 RD: Read Control bit

1 = Initiates an program Flash or data EEPROM read. Read takes one cycle. RD is cleared in

hardware. The RD bit can only be set (not cleared) in software.

0 = Does not initiate a program Flash or data EEPROM data read

PIC16(L)F1824/1828

DS41419C-page 120 Preliminary  2010-2011 Microchip Technology Inc.

TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM

W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0

EEPROM Control Register 2

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 Data EEPROM Unlock Pattern bits

To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the

EECON1 register. The value written to this register is used to unlock the writes. There are specific

timing requirements on these writes. Refer to Section 11.2.2 “Writing to the Data EEPROM

Memory” for more information.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 119

EECON2 EEPROM Control Register 2 (not a physical register) 120*

EEADRL EEADRL<7:0> 118

EEADRH — EEADRH<6:0 118

EEDATL EEDATL<7:0> 118

EEDATH —— EEDATH<5:0> 118

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93

PIE2 OSFIE C2IE C1IE EEIE BCL1IE —— CCP2IE 95

PIR2 OSFIF C2IF C1IF EEIF BCL1IF —— CCP2IF 98

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by data EEPROM module.

* Page provides register information.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 121

PIC16(L)F1824/1828

12.0 I/O PORTS

Depending on the device selected and peripherals

enabled, there are up to two ports available. In general,

when a peripheral is enabled, that pin may not be used

as a general purpose I/O pin.

Each port has three registers for its operation. These

registers are:

• TRISx registers (data direction register)

• PORTx registers (reads the levels on the pins of

the device)

• LATx registers (output latch)

The Data Latch (LATx registers) is useful for

read-modify-write operations on the value that the I/O

pins are driving.

A write operation to the LATx register has the same

affect as a write to the corresponding PORTx register.

A read of the LATx register reads of the values held in

the I/O PORT latches, while a read of the PORTx

Ports with analog functions also have an ANSELx

power. A simplified model of a generic I/O port, without

the interfaces to other peripherals, is shown in

Figure 12-1.

FIGURE 12-1: GENERIC I/O PORT

OPERATION

12.1 Alternate Pin Function

The Alternate Pin Function Control 0 (APFCON0) and

Alternate Pin Function Control 1 (APFCON1) registers

are used to steer specific peripheral input and output

functions between different pins. The APFCON0 and

APFCON1 registers are shown in Register 12-1 and

functions can be moved between different pins.

• RX/DT/TX/CK

•SDO

•SS

(Slave Select)

•T1G

• P1B/P1C/P1D/P2B

• CCP1/P1A/CCP2

These bits have no effect on the values of any TRIS

correct pin. The unselected pin will be unaffected.

Write LATx

Data Register

I/O pin

Read PORTx

Write PORTx

TRISx

Read LATx

Data Bus

To peripherals

ANSELx

VDD

VSS

PIC16(L)F1824/1828

DS41419C-page 122 Preliminary  2010-2011 Microchip Technology Inc.

R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 U-0

RXDTSEL SDOSEL(1) SSSEL(1) —T1GSEL TXCKSEL — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 RXDTSEL: Pin Selection

For 14-Pin Devices (PIC16(L)F1824)

0 = RX/DT function is on RC5

1 = RX/DT function is on RA1

For 20-Pin Devices (PIC16(L)F1828)

0 = RX/DT function is on RB5

1 = RX/DT function is on RC5

bit 6 SDOSEL: Pin Selection

For 14-Pin Devices (PIC16(L)F1824)

0 = SDO function is on RC2

1 = SDO function is on RA4

For 20-Pin Devices (PIC16(L)F1828)

Bit is Read-Only, ‘0’

SDO function is always on RC7

bit 5 SSSEL: Pin Selection

For 14-Pin Devices (PIC16(L)F1824)

0 =SS function is on RC3

1 =SS

function is on RA3

For 20-Pin Devices (PIC16(L)F1828)

Bit is Read-Only, ‘0’

SDO function is always on RC6

bit 4 Unimplemented: Read as ‘0’

bit 3 T1GSEL: Pin Selection

0 = T1G function is on RA4

1 = T1G function is on RA3

bit 2 TXCKSEL: Pin Selection

For 14-Pin Devices (PIC16(L)F1824)

0 = TX/CK function is on RC4

1 = TX/CK function is on RA0

For 20-Pin Devices (PIC16(L)F1828)

0 = TX/CK function is on RB7

1 = TX/CK function is on RC4

bit 1-0 Unimplemented: Read as ‘0’

Note 1: PIC16(L)F1824 only.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 123

PIC16(L)F1824/1828

U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— — — — P1DSEL P1CSEL P2BSEL CCP2SEL

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 Unimplemented: Read as ‘0’

bit 3 P1DSEL: Pin Selection

0 = P1D function is on RC2

1 = P1D function is on RC0

bit 2 P1CSEL: Pin Selection

0 = P1C function is on RC3

1 = P1C function is on RC1

bit 1 P2BSEL: Pin Selection

0 = P2B function is on RC2

1 = P2B function is on RA4

bit 0 CCP2SEL: Pin Selection

0 = CCP2 function is on RC3

1 = CCP2 function is on RA5

PIC16(L)F1824/1828

DS41419C-page 124 Preliminary  2010-2011 Microchip Technology Inc.

12.2 PORTA Registers

PORTA is a 6-bit wide, bidirectional port. The

corresponding data direction register is TRISA

(Register 12-4). Setting a TRISA bit (= 1) will make the

corresponding PORTA pin an input (i.e., disable the

output driver). Clearing a TRISA bit (= 0) will make the

corresponding PORTA pin an output (i.e., enables

output driver and puts the contents of the output latch

on the selected pin). The exception is RA3, which is

input only and its TRIS bit will always read as ‘1’.

Example 12-1 shows how to initialize PORTA.

Reading the PORTA register (Register 12-3) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then

written to the PORT data latch (LATA).

The TRISA register (Register 12-4) controls the

PORTA pin output drivers, even when they are being

used as analog inputs. The user should ensure the bits

in the TRISA register are maintained set when using

them as analog inputs. I/O pins configured as analog

input always read ‘0’.

The INLVLA register (Register 12-8) controls the input

voltage threshold for each of the available PORTA input

pins. A selection between the Schmitt Trigger CMOS or

the TTL Compatible thresholds is available. The input

threshold is important in determining the value of a

read of the PORTA register and also the level at which

an Interrupt-on-Change occurs, if that feature is

enabled. See Section 30.4 “DC Characteristics:

PIC16(L)F1824/1828-I/E” for more information on

threshold levels.

12.2.1 WEAK PULL-UPS

Each of the PORTA pins has an individually configurable

internal weak pull-up. Control bits WPUA<5:0> enable or

disable each pull-up (see Register 12-7). Each weak

pull-up is automatically turned off when the port pin is

configured as an output. All pull-ups are disabled on a

Power-on Reset by the WPUEN bit of the

OPTION_REG register.

12.2.2 ANSELA REGISTER

The ANSELA register (Register 12-6) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELA bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

The state of the ANSELA bits has no affect on digital

output functions. A pin with TRIS clear and ANSEL set

will still operate as a digital output, but the Input mode

will be analog. This can cause unexpected behavior

when executing read-modify-write instructions on the

affected port.

EXAMPLE 12-1: INITIALIZING PORTA

Note: Changing the input threshold selection

should be performed while all peripheral

modules are disabled. Changing the

threshold level during the time a module is

active may inadvertently generate a tran-

sition associated with an input pin, regard-

less of the actual voltage level on that pin.

Note: The ANSELA register must be initialized

to configure an analog channel as a digital

input. Pins configured as analog inputs

will read ‘0’.

BANKSEL PORTA ;

CLRF PORTA ;Init PORTA

BANKSEL LATA ;Data Latch

CLRF LATA ;

BANKSEL ANSELA ;

CLRF ANSELA ;digital I/O

BANKSEL TRISA ;

MOVLW B'00111000' ;Set RA<5:3> as inputs

MOVWF TRISA ;and set RA<2:0> as

;outputs

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 125

PIC16(L)F1824/1828

12.2.3 PORTA FUNCTIONS AND OUTPUT

PRIORITIES

Each PORTA pin is multiplexed with other functions. The

pins, their combined functions and their output priorities

are briefly described here. For additional information,

refer to the appropriate section in this data sheet.

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the lowest number in

the following lists.

Analog input functions, such as ADC, comparator and

CapSense inputs, are not shown in the priority lists.

These inputs are active when the I/O pin is set for

Analog mode using the ANSELx registers. Digital

output functions may control the pin when it is in Analog

mode with the priority shown below.

RA0

1. ICSPDAT

2. ICDDAT

3. DACOUT (DAC)

RA1

1. ICSPCLK

2. ICDCLK

3. RX/DT (EUSART)

RA2

1. SRQ

2. C1OUT (Comparator)

3. CCP3

RA3

No output priorities. Input only pin.

RA4

1. CLKOUT

2. T1OSO

3. CLKR

4. SDO

5. P2B

RA5

1. CCP2/P2A

PIC16(L)F1824/1828

DS41419C-page 126 Preliminary  2010-2011 Microchip Technology Inc.

U-0 U-0 R/W-x/x R/W-x/x R-x/x R/W-x/x R/W-x/x R/W-x/x

—— RA5 RA4 RA3 RA2 RA1 RA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0

bit 5-0 RA<5:0>: PORTA I/O Value bits(1)

1 = Port pin is > VIH

0 = Port pin is < VIL

Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is

return of actual I/O pin values.

U-0 U-0 R/W-1/1 R/W-1/1 R-1/1 R/W-1/1 R/W-1/1 R/W-1/1

—— TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0

bit 5-4 TRISA<5:4>: PORTA Tri-State Control bit

1 = PORTA pin configured as an input (tri-stated)

0 = PORTA pin configured as an output

bit 3 TRISA3: RA3 Port Tri-State Control bit

This bit is always ‘1’ as RA3 is an input only

bit 2-0 TRISA<2:0>: PORTA Tri-State Control bit

1 = PORTA pin configured as an input (tri-stated)

0 = PORTA pin configured as an output

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 127

PIC16(L)F1824/1828

U-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u

——LATA5LATA4— LATA2 LATA1 LATA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0

bit 5-4 LATA<5:4>: RA<5:4> Output Latch Value bits(1)

bit 3 Unimplemented: Read as ‘0

bit 2-0 LATA<2:0>: RA<2:0> Output Latch Value bits(1)

Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is

return of actual I/O pin values.

U-0 U-0 U-0 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1

— — — ANSA4 — ANSA2 ANSA1 ANSA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4 ANSA4: Analog Select between Analog or Digital Function on pins RA4, respectively

0 = Digital I/O. Pin is assigned to port or digital special function.

1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.

bit 3 Unimplemented: Read as ‘0’

bit 2-0 ANSA<2:0>: Analog Select between Analog or Digital Function on pins RA<2:0>, respectively

0 = Digital I/O. Pin is assigned to port or digital special function.

1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

PIC16(L)F1824/1828

DS41419C-page 128 Preliminary  2010-2011 Microchip Technology Inc.

U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1

—— WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 WPUA<5:0>: Weak Pull-up Register bits

1 = Pull-up enabled

0 = Pull-up disabled

Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in configured as an output.

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-0/0

—— INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0

bit 5-0 INLVLA<5:0>: PORTA Input Level Select bits

For RA<5:0> pins, respectively

1 = ST input used for PORT reads and interrupt-on-change

0 = TTL input used for PORT reads and interrupt-on-change

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 129

PIC16(L)F1824/1828

TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

TABLE 12-2: SUMMARY OF CONFIGURATION WORD WITH PORTA

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

ANSELA — — —ANSA4— ANSA2 ANSA1 ANSA0 127

APFCON0(1) RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL — — 123

APFCON1 — — — — P1DSEL P1CSEL P2BSEL CCP2SEL 123

INLVLA —— INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 128

LATA ——LATA5LATA4—LATA2LATA1LATA0

127

OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 187

PORTA —— RA5 RA4 RA3 RA2 RA1 RA0 126

TRISA —— TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 126

WPUA —— WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 128

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

Note 1: Unshaded cells apply to PIC16(L)F1824 only.

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register

on Page

CONFIG1 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> CPD 52

7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.

PIC16(L)F1824/1828

DS41419C-page 130 Preliminary  2010-2011 Microchip Technology Inc.

12.3 PORTB Registers

(PIC16(L)F1828 only)

PORTB is a 4-bit wide, bidirectional port. The

corresponding data direction register is TRISB

(Register 12-10). Setting a TRISB bit (= 1) will make the

corresponding PORTB pin an input (i.e., put the

corresponding output driver in a High-Impedance mode).

Clearing a TRISB bit (= 0) will make the corresponding

PORTB pin an output (i.e., enable the output driver and

put the contents of the output latch on the selected pin).

Example 12-2 shows how to initialize PORTB.

Reading the PORTB register (Register 12-9) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then written

to the PORT data latch (LATB).

The TRISB register (Register 12-10) controls the PORTB

pin output drivers, even when they are being used as

analog inputs. The user should ensure the bits in the

TRISB register are maintained set when using them as

analog inputs. I/O pins configured as analog input always

read ‘0’.

The INLVLB register (Register 12-14) controls the input

voltage threshold for each of the available PORTB

input pins. A selection between the Schmitt Trigger

CMOS or the TTL Compatible thresholds is available.

The input threshold is important in determining the

value of a read of the PORTB register and also the level

at which an Interrupt-on-Change occurs, if that feature

is enabled. See Section 30.4 “DC Characteristics:

PIC16(L)F1824/1828-I/E” for more information on

threshold levels.

12.3.1 WEAK PULL-UPS

Each of the PORTB pins has an individually configurable

internal weak pull-up. Control bits WPUB<7:4> enable or

disable each pull-up (see Register 12-13). Each weak

pull-up is automatically turned off when the port pin is

configured as an output. All pull-ups are disabled on a

Power-on Reset by the WPUEN bit of the OPTION_REG

12.3.2 ANSELB REGISTER

The ANSELB register (Register 12-12) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELB bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

The state of the ANSELB bits has no affect on digital out-

put functions. A pin with TRIS clear and ANSELB set will

still operate as a digital output, but the Input mode will be

analog. This can cause unexpected behavior when exe-

cuting read-modify-write instructions on the affected

port.

EXAMPLE 12-2: INITIALIZING PORTB

Note: Changing the input threshold selection

should be performed while all peripheral

modules are disabled. Changing the

threshold level during the time a module is

active may inadvertently generate a tran-

sition associated with an input pin, regard-

less of the actual voltage level on that pin.

Note: The ANSELB register must be initialized

to configure an analog channel as a digital

input. Pins configured as analog inputs

will read ‘0’.

BANKSEL PORTB ;

CLRF PORTB ;Init PORTB

BANKSEL LATB ;Data Latch

CLRF LATB ;

BANKSEL ANSELB

CLRF ANSELB ;Make RB<7:4> digital

BANKSEL TRISB ;

MOVLW B’11110000’ ;Set RB<7:4> as inputs

MOVWF TRISB ;

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 131

PIC16(L)F1824/1828

12.3.3 PORTB FUNCTIONS AND OUTPUT

PRIORITIES

Each PORTB pin is multiplexed with other functions. The

pins, their combined functions and their output priorities

are briefly described here. For additional information,

refer to the appropriate section in this data sheet.

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the lowest number in

the following lists.

Analog input and some digital input functions are not

included in the list below. These input functions can

remain active when the pin is configured as an output.

Certain digital input functions override other port

functions and are included in the priority list.

RB4

SDA (MSSP)

RB5

RX/DT (EUSART)

RB6

SCL/SCK (MSSP)

RB7

TX/CK (EUSART)

PIC16(L)F1824/1828

DS41419C-page 132 Preliminary  2010-2011 Microchip Technology Inc.

R/W-x/u R/W-x/u R/W-x/u R/W-x/u U-0 U-0 U-0 U-0

RB7 RB6 RB5 RB4 — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 RB<7:4>: PORTB General Purpose I/O Pin bits

1 = Port pin is > VIH

0 = Port pin is < VIL

bit 3-0 Unimplemented: Read as ‘0’

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0

TRISB7 TRISB6 TRISB5 TRISB4 — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 TRISB<7:4>: PORTB Tri-State Control bits

1 = PORTB pin configured as an input (tri-stated)

0 = PORTB pin configured as an output

bit 3-0 Unimplemented: Read as ‘0’

R/W-x/u R/W-x/u R/W-x/u R/W-x/u U-0 U-0 U-0 U-0

LATB7 LATB6 LATB5 LATB4 — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 LATB<7:4>: PORTB Output Latch Value bits(1)

bit 3-0 Unimplemented: Read as ‘0’

Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is

return of actual I/O pin values.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 133

PIC16(L)F1824/1828

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0

ANSB7 ANSB6 ANSB5 ANSB4 — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 ANSB<7:4>: Analog Select between Analog or Digital Function on pins RB<7:4>, respectively

0 = Digital I/O. Pin is assigned to port or digital special function.

1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.

bit 3-0 Unimplemented: Read as ‘0’

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external

control of the voltage on the pin.

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0

WPUB7 WPUB6 WPUB5 WPUB4 — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 WPUB<7:4>: Weak Pull-up Register bits

1 = Pull-up enabled

0 = Pull-up disabled

bit 3-0 Unimplemented: Read as ‘0’

Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in configured as an output.

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0

INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 INLVLB<7:4>: PORTB Input Level Select bits

For RB<7:4> pins, respectively

1 = ST input used for PORT reads and interrupt-on-change

0 = TTL input used for PORT reads and interrupt-on-change

bit 3-0 Unimplemented: Read as ‘0

PIC16(L)F1824/1828

DS41419C-page 134 Preliminary  2010-2011 Microchip Technology Inc.

TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB(1)

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

ANSELB ANSB7 ANSB6 ANSB5 ANSB4 — — — — 133

INLVLB INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — — 133

LATB LATB7 LATB6 LATB5 LATB4 — — — — 132

PORTB RB7 RB6 RB5 RB4 — — — — 132

TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 132

WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 133

Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.

Note 1: PIC16(L)F1828 only.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 135

PIC16(L)F1824/1828

12.4 PORTC Registers

PORTC is a 6-bit wide (8-bit wide for PIC16(L)F1828),

bidirectional port. The corresponding data direction

(= 1) will make the corresponding PORTC pin an input

(i.e., put the corresponding output driver in a

High-Impedance mode). Clearing a TRISC bit (= 0) will

make the corresponding PORTC pin an output (i.e.,

enable the output driver and put the contents of the

output latch on the selected pin). Example 12-2 shows

how to initialize PORTC.

Reading the PORTC register (Register 12-9) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then written

to the PORT data latch (LATC).

The TRISC register (Register 12-10) controls the

PORTC pin output drivers, even when they are being

used as analog inputs. The user should ensure the bits in

the TRISC register are maintained set when using them

as analog inputs. I/O pins configured as analog input

always read ‘0’.

The INLVLC register (Register 12-14) controls the input

voltage threshold for each of the available PORTC

input pins. A selection between the Schmitt Trigger

CMOS or the TTL Compatible thresholds is available.

The input threshold is important in determining the

value of a read of the PORTC register and also the

level at which an Interrupt-on-Change occurs, if that

feature is enabled. See Section 30.4 “DC Character-

istics: PIC16(L)F1824/1828-I/E” for more information

on threshold levels.

12.4.1 WEAK PULL-UPS

Each of the PORTC pins has an individually configurable

internal weak pull-up. Control bits WPUC<7:0> enable or

disable each pull-up (see Register 12-19). Each weak

pull-up is automatically turned off when the port pin is

configured as an output. All pull-ups are disabled on a

Power-on Reset by the WPUEN bit of the OPTION_REG

12.4.2 ANSELC REGISTER

The ANSELC register (Register 12-12) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELC bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

The state of the ANSELC bits has no affect on digital out-

put functions. A pin with TRIS clear and ANSELC set will

still operate as a digital output, but the Input mode will be

analog. This can cause unexpected behavior when exe-

cuting read-modify-write instructions on the affected

port.

EXAMPLE 12-3: INITIALIZING PORTC

Note: Changing the input threshold selection

should be performed while all peripheral

modules are disabled. Changing the

threshold level during the time a module is

active may inadvertently generate a tran-

sition associated with an input pin, regard-

less of the actual voltage level on that pin.

Note: The ANSELC register must be initialized

to configure an analog channel as a digital

input. Pins configured as analog inputs

will read ‘0’.

BANKSEL PORTC ;

CLRF PORTC ;Init PORTC

BANKSEL LATC ;Data Latch

CLRF LATC ;

BANKSEL ANSELC

CLRF ANSELC ;Make RC<5:0> digital

BANKSEL TRISB ;

MOVLW B’00110000’;Set RC<5:4> as inputs

;and RC<3:0> as outputs

MOVWF TRISC ;

PIC16(L)F1824/1828

DS41419C-page 136 Preliminary  2010-2011 Microchip Technology Inc.

12.4.3 PORTC FUNCTIONS AND OUTPUT

PRIORITIES

Each PORTC pin is multiplexed with other functions. The

pins, their combined functions and their output priorities

are briefly described here. For additional information,

refer to the appropriate section in this data sheet.

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the lowest number in

the following lists.

Analog input and some digital input functions are not

included in the list below. These input functions can

remain active when the pin is configured as an output.

Certain digital input functions override other port

functions and are included in the priority list.

RC0

1. SCL (MSSP) (PIC16(L)F1824 only)

2. SCK (MSSP) (PIC16(L)F1824 only)

3. P1D

RC1

1. SDA (MSSP) (PIC16(L)F1824 only)

2. P1C

3. CCP4 (PIC16(L)F1828 only)

RC2

1. SDO (MSSP) (PIC16(L)F1824 only)

2. P1D

3. P2B

RC3

1. SS (MSSP) (PIC16(L)F1824 only)

2. CCP2

3. P1C

4. P2A

RC4

1. MDOUT

2. SRNQ

3. C2OUT

4. TX/CK

5. P1B

RC5

1. RX/DT

2. CCP1/P1A

RC6 (PIC16(L)F1828 only)

1. SS (MSSP)

2. CCP4

RC7 (PIC16(L)F1828 only)

1. SDO (MSSP)

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 137

PIC16(L)F1824/1828

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

RC7(1) RC6(1) RC5 RC4 RC3 RC2 RC1 RC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bits(1)

1 = Port pin is > VIH

0 = Port pin is < VIL

Note 1: RC<7:6> available on PIC16(L)F1828 only. Otherwise, they are unimplemented and read as ‘0’.

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1

TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits(1)

1 = PORTC pin configured as an input (tri-stated)

0 = PORTC pin configured as an output

Note 1: TRISC<7:6> available on PIC16(L)F1828 only. Otherwise, they are unimplemented and read as ‘0’.

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

LATC7(1) LATC6(1) LATC5 LATC4 LATC3 LATC2 LATC1 LATC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 LATC<7:0>: PORTC Output Latch Value bits(1, 2)

Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is

return of actual I/O pin values.

2: LATC<7:6> available on PIC16(L)F1828 only. Otherwise, they are unimplemented and read as ‘0’.

PIC16(L)F1824/1828

DS41419C-page 138 Preliminary  2010-2011 Microchip Technology Inc.

R/W-1/1 R/W-1/1 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1

ANSC7(1) ANSC6(1) —— ANSC3 ANSC2 ANSC1 ANSC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 ANSC<7:6>: Analog Select between Analog or Digital Function on pins RC<3:0>, respectively(1)

0 = Digital I/O. Pin is assigned to port or digital special function.

1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.

bit 5-4 Unimplemented: Read as ‘0’

bit 3-0 ANSC<3:0>: Analog Select between Analog or Digital Function on pins RC<3:0>, respectively

0 = Digital I/O. Pin is assigned to port or digital special function.

1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

2: ANSELC<7:6> available on PIC16(L)F1828 only. Otherwise, they are unimplemented and read as ‘0’.

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1

WPUC7(1) WPUC6(1) WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 WPUC<7:0>: Weak Pull-up Register bits(1)

1 = Pull-up enabled

0 = Pull-up disabled

Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in configured as an output.

3: WPUC<7:6> available on PIC16(L)F1828 only. Otherwise, they are unimplemented and read as ‘0’.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 139

PIC16(L)F1824/1828

TABLE 12-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-0/0

INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 INLVLC<7:0>: PORTC Input Level Select bits(1)

For RC<7:0> pins, respectively

1 = ST input used for PORT reads and Interrupt-on-Change

0 = TTL input used for PORT reads and Interrupt-on-Change

Note 1: INLVLC<7:6> available on PIC16(L)F1828 only. Otherwise, they are unimplemented and read as ‘0’.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

ANSELC ANSC7(1) ANSC6(1) —— ANSC3 ANSC2 ANSC1 ANSC0 133

INLVLC INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 139

LATC LATC7(1) LATC6(1) LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 132

PORTC RC7(1) RC6(1) RC5 RC4 RC3 RC2 RC1 RC0 132

TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132

WPUC WPUC7(1) WPUC6(1) WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 133

Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

Note 1: PIC16(L)F1828 only.

PIC16(L)F1824/1828

DS41419C-page 140 Preliminary  2010-2011 Microchip Technology Inc.

NOTES:

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 141

PIC16(L)F1824/1828

13.0 INTERRUPT-ON-CHANGE

The PORTA pins can be configured to operate as

Interrupt-on-Change (IOC) pins. On the PIC16(L)F1828

devices, the PORTB pins can also be configured to

operate as IOC pins. An interrupt can be generated by

detecting a signal that has either a rising edge or a falling

edge. Any individual port pin, or combination of port pins,

can be configured to generate an interrupt. The

interrupt-on-change module has the following features:

• Interrupt-on-change enable (Master Switch)

• Individual pin configuration

• Rising and falling edge detection

• Individual pin interrupt flags

Figure 13-1 is a block diagram of the IOC module.

13.1 Enabling the Module

To allow individual port pins to generate an interrupt, the

IOCIE bit of the INTCON register must be set. If the

IOCIE bit is disabled, the edge detection on the pin will

still occur, but an interrupt will not be generated.

13.2 Individual Pin Configuration

For each port pin, a rising edge detector and a falling

edge detector are present. To enable a pin to detect a

rising edge, the associated bit of the IOCxP register is

set. To enable a pin to detect a falling edge, the

associated bit of the IOCxN register is set.

A pin can be configured to detect rising and falling

edges simultaneously by setting both associated bits of

the IOCxP and IOCxN registers, respectively.

13.3 Interrupt Flags

The IOCAFx and IOCBFx bits located in the IOCAF and

IOCBF registers, respectively, are status flags that

correspond to the interrupt-on-change pins of the

associated port. If an expected edge is detected on an

appropriately enabled pin, then the status flag for that pin

will be set, and an interrupt will be generated if the IOCIE

bit is set. The IOCIF bit of the INTCON register reflects

the status of all IOCAFx and IOCBFx bits.

13.4 Clearing Interrupt Flags

The individual status flags, (IOCAFx and IOCBFx bits),

can be cleared by resetting them to zero. If another edge

is detected during this clearing operation, the associated

status flag will be set at the end of the sequence,

regardless of the value actually being written.

In order to ensure that no detected edge is lost while

clearing flags, only AND operations masking out known

changed bits should be performed. The following

sequence is an example of what should be performed.

EXAMPLE 13-1:

13.5 Operation in Sleep

The interrupt-on-change interrupt sequence will wake

the device from Sleep mode, if the IOCIE bit is set.

If an edge is detected while in Sleep mode, the IOCxF

executed out of Sleep.

FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE)

MOVLW 0xff

XORWF IOCAF, W

ANDWF IOCAF, F

RAx

From all other IOCAFx

individual pin detectors

IOCANx

IOCAPx

Q2 Clock Cycle

IOCIE

IOC Interrupt to

CPU Core

IOCAFx

PIC16(L)F1824/1828

DS41419C-page 142 Preliminary  2010-2011 Microchip Technology Inc.

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

—— IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 IOCAP<5:0>: Interrupt-on-Change PORTA Positive Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and interrupt

flag will be set upon detecting an edge.

0 = Interrupt-on-Change disabled for the associated pin.

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

—— IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 IOCAN<5:0>: Interrupt-on-Change PORTA Negative Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and interrupt

flag will be set upon detecting an edge.

0 = Interrupt-on-Change disabled for the associated pin.

U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0

—— IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 IOCAF<5:0>: Interrupt-on-Change PORTA Flag bits

1 = An enabled change was detected on the associated pin.

Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling edge

was detected on RAx.

0 = No change was detected, or the user cleared the detected change.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 143

PIC16(L)F1824/1828

(PIC16(L)F1828 ONLY)

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0

IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 IOCBP<7:4>: Interrupt-on-Change PORTB Positive Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and interrupt

flag will be set upon detecting an edge.

0 = Interrupt-on-Change disabled for the associated pin.

bit 3-0 Unimplemented: Read as ‘0’

(PIC16(L)F1828 ONLY)

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0

IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 IOCAN<7:4>: Interrupt-on-Change PORTB Negative Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and interrupt

flag will be set upon detecting an edge.

0 = Interrupt-on-Change disabled for the associated pin.

bit 3-0 Unimplemented: Read as ‘0’

PIC16(L)F1824/1828

DS41419C-page 144 Preliminary  2010-2011 Microchip Technology Inc.

TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE

(PIC16(L)F1828 ONLY)

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0

IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware

bit 7-4 IOCBF<7:4>: Interrupt-on-Change PORTB Flag bits

1 = An enabled change was detected on the associated pin.

Set when IOCBPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling edge

was detected on RBx.

0 = No change was detected, or the user cleared the detected change.

bit 3-0 Unimplemented: Read as ‘0’

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

ANSELA ———ANSA4— ANSA2 ANSA1 ANSA0 127

ANSELB(1) ANSB7 ANSB6 ANSB5 ANSB4 ————133

INLVLA — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 128

INLVLB(1) INLVLB7 INLVLB6 INLVLB5 INLVLB4 ————133

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93

IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 142

IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 142

IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 142

IOCBF(1) IOCBF7 IOCBF6 IOCBF5 IOCBF4 ————144

IOCBN(1) IOCBN7 IOCBN6 IOCBN5 IOCBN4 ————143

IOCBP(1) IOCBP7 IOCBP6 IOCBP5 IOCBP4 ————143

TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 126

TRISB(1) TRISB7 TRISB6 TRISB5 TRISB4 ————132

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupt-on-Change.

Note 1: PIC16(L)F1828 only.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 145

PIC16(L)F1824/1828

14.0 FIXED VOLTAGE REFERENCE

(FVR)

The Fixed Voltage Reference (FVR), is a stable voltage

reference, independent of VDD, with 1.024V, 2.048V or

4.096V selectable output levels. The output of the FVR

can be configured to supply a reference voltage to the

following:

• ADC input channel

• ADC positive reference

• Comparator positive input

• Digital-to-Analog Converter (DAC)

The FVR can be enabled by setting the FVREN bit of

the FVRCON register.

14.1 Independent Gain Amplifiers

The output of the FVR supplied to the ADC,

Comparators, and DAC is routed through two

independent programmable gain amplifiers. Each

amplifier can be configured to amplify the reference

voltage by 1x, 2x or 4x, to produce the three possible

voltage levels.

The ADFVR<1:0> bits of the FVRCON register are

used to enable and configure the gain amplifier settings

for the reference supplied to the ADC module. Refer-

ence Section 16.0 “Analog-to-Digital Converter

(ADC) Module” for additional information.

The CDAFVR<1:0> bits of the FVRCON register are

used to enable and configure the gain amplifier settings

for the reference supplied to the DAC and comparator

module. Reference Section 17.0 “Digital-to-Analog

Converter (DAC) Module” and Section 19.0 “Com-

parator Module” for additional information.

14.2 FVR Stabilization Period

When the Fixed Voltage Reference module is enabled, it

requires time for the reference and amplifier circuits to

stabilize. Once the circuits stabilize and are ready for use,

the FVRRDY bit of the FVRCON register will be set. See

Section 30.0 “Electrical Specifications” for the

minimum delay requirement.

FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM

ADFVR<1:0>

CDAFVR<1:0>

FVR BUFFER1

(To ADC Module)

FVR BUFFER2

(To Comparators, DAC)

FVREN

FVRRDY

1.024V Fixed

Reference

PIC16(L)F1824/1828

DS41419C-page 146 Preliminary  2010-2011 Microchip Technology Inc.

TABLE 14-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCE

R/W-0/0 R-q/q R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

FVREN FVRRDY(1) TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR1 ADFVR0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 FVREN: Fixed Voltage Reference Enable bit

0 = Fixed Voltage Reference is disabled

1 = Fixed Voltage Reference is enabled

bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1)

0 = Fixed Voltage Reference output is not ready or not enabled

1 = Fixed Voltage Reference output is ready for use

bit 5 TSEN: Temperature Indicator Enable bit(3)

0 = Temperature Indicator is disabled

1 = Temperature Indicator is enabled

bit 4 TSRNG: Temperature Indicator Range Selection bit(3)

0 =VOUT = VDD - 4VT (High Range)

1 =V

OUT = VDD - 2VT (Low Range)

bit 3-2 CDAFVR<1:0>: Comparator and DAC Fixed Voltage Reference Selection bits

00 = Comparator and DAC Fixed Voltage Reference Peripheral output is off.

01 = Comparator and DAC Fixed Voltage Reference Peripheral output is 1x (1.024V)

10 = Comparator and DAC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)

11 = Comparator and DAC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)

bit 1-0 ADFVR<1:0>: ADC Fixed Voltage Reference Selection bits

00 = ADC Fixed Voltage Reference Peripheral output is off.

01 = ADC Fixed Voltage Reference Peripheral output is 1x (1.024V)

10 = ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)

11 = ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)

Note 1: FVRRDY is always ‘1’ on devices with the LDO (PIC16F1824/1828).

2: Fixed Voltage Reference output cannot exceed VDD.

3: See Section 15.0 “Temperature Indicator Module” for additional information.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on page

FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 146

Legend: Shaded cells are unused by the Fixed Voltage Reference module.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 147

PIC16(L)F1824/1828

15.0 TEMPERATURE INDICATOR

MODULE

This family of devices is equipped with a temperature

circuit designed to measure the operating temperature

of the silicon die. The circuit’s range of operating

temperature falls between of -40°C and +85°C. The

output is a voltage that is proportional to the device

temperature. The output of the temperature indicator is

internally connected to the device ADC.

The circuit may be used as a temperature threshold

detector or a more accurate temperature indicator,

depending on the level of calibration performed. A one-

point calibration allows the circuit to indicate a

temperature closely surrounding that point. A two-point

calibration allows the circuit to sense the entire range

of temperature more accurately. Reference Application

Note AN1333, “Use and Calibration of the Internal

Temperature Indicator” (DS01333) for more details

regarding the calibration process.

15.1 Circuit Operation

Figure 15-1 shows a simplified block diagram of the

temperature circuit. The proportional voltage output is

achieved by measuring the forward voltage drop across

multiple silicon junctions.

Equation 15-1 describes the output characteristics of

the temperature indicator.

EQUATION 15-1: VOUT RANGES

The temperature sense circuit is integrated with the

Fixed Voltage Reference (FVR) module. See

Section 14.0 “Fixed Voltage Reference (FVR)” for

more information.

The circuit is enabled by setting the TSEN bit of the

FVRCON register (Register 14-1). When disabled, the

circuit draws no current.

The circuit operates in either high or low range. The high

range, selected by setting the TSRNG bit of the

FVRCON register, provides a wider output voltage. This

provides more resolution over the temperature range,

but may be less consistent from part to part. This range

requires a higher bias voltage to operate and thus, a

higher VDD is needed.

The low range is selected by clearing the TSRNG bit of

the FVRCON register. The low range generates a lower

voltage drop and thus, a lower bias voltage is needed to

operate the circuit. The low range is provided for low

voltage operation.

FIGURE 15-1: TEMPERATURE CIRCUIT

DIAGRAM

15.2 Minimum Operating VDD vs.

Minimum Sensing Temperature

When the temperature circuit is operated in low range,

the device may be operated at any operating voltage

that is within specifications.

When the temperature circuit is operated in high range,

the device operating voltage, VDD, must be high

enough to ensure that the temperature circuit is

correctly biased.

Table 15-1 shows the recommended minimum VDD vs.

range setting.

TABLE 15-1: RECOMMENDED VDD VS.

RANGE

15.3 Temperature Output

The output of the circuit is measured using the internal

analog-to-digital converter. A channel is reserved for the

temperature circuit output. Refer to Section 16.0

“Analog-to-Digital Converter (ADC) Module” for

detailed information.

15.4 ADC Acquisition Time

To ensure accurate temperature measurements, the

user must wait at least 200 s after the ADC input

multiplexer is connected to the temperature indicator

output before the conversion is performed. In addition,

the user must wait 200 s between sequential

conversions of the temperature indicator output.

High Range: VOUT = VDD - 4VT

Low Range: VOUT = VDD - 2VT

Min. VDD, TSRNG = 1Min. VDD, TSRNG = 0

3.6V 1.8V

TSEN

ADC

MUX

TSRNG

VDD

ADC

CHS bits

(ADCON0 register)

VOUT

PIC16(L)F1824/1828

DS41419C-page 148 Preliminary  2010-2011 Microchip Technology Inc.

NOTES:

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 149

PIC16(L)F1824/1828

16.0 ANALOG-TO-DIGITAL

CONVERTER (ADC) MODULE

The Analog-to-Digital Converter (ADC) allows

conversion of an analog input signal to a 10-bit binary

representation of that signal. This device uses analog

inputs, which are multiplexed into a single sample and

hold circuit. The output of the sample and hold is

connected to the input of the converter. The converter

generates a 10-bit binary result via successive

approximation and stores the conversion result into the

ADC result registers (ADRESH:ADRESL register pair).

Figure 16-1 shows the block diagram of the ADC.

The ADC voltage reference is software selectable to be

either internally generated or externally supplied.

The ADC can generate an interrupt upon completion of

a conversion. This interrupt can be used to wake-up the

device from Sleep.

FIGURE 16-1: ADC BLOCK DIAGRAM

DAC

VDD

VREF+ADPREF = 10

ADPREF = 00

ADPREF = 11

FVR Buffer1

VSS

VREF-ADNREF = 1

ADNREF = 0

Note 1: When ADON = 0, all multiplexer inputs are disconnected.

2: PIC16(L)F1828 only.

ADON

GO/DONE

VSS

ADC

00000

00001

00010

00011

00100

00101

00111

00110

01000

01001

01010

01011

11110

CHS<4:0>

AN0

AN1

AN2

AN4

AN5

AN6

AN7

AN3

AN8(2)

AN9(2)

AN10(2)

AN11(2)

11111

ADRESH ADRESL

ADFM 0 = Left Justify

1 = Right Justify

11101

Temp Indicator

PIC16(L)F1824/1828

DS41419C-page 150 Preliminary  2010-2011 Microchip Technology Inc.

16.1 ADC Configuration

When configuring and using the ADC the following

functions must be considered:

• Port configuration

• Channel selection

• ADC voltage reference selection

• ADC conversion clock source

• Interrupt control

• Result formatting

16.1.1 PORT CONFIGURATION

The ADC can be used to convert both analog and

digital signals. When converting analog signals, the I/O

pin should be configured for analog by setting the

associated TRIS and ANSEL bits. Refer to

Section 12.0 “I/O Ports” for more information.

16.1.2 CHANNEL SELECTION

There are up to 14 channel selections available:

• AN<7:0> pins (PIC16(L)F1824 only)

• AN<11:0> pins (PIC16(L)F1828 only)

• DAC Output

• FVR (Fixed Voltage Reference) Output

Refer to Section 17.0 “Digital-to-Analog Converter

(DAC) Module” and Section 14.0 “Fixed Voltage

Reference (FVR)” for more information on these

channel selections.

The CHS bits of the ADCON0 register determine which

channel is connected to the sample and hold circuit.

When changing channels, a delay is required before

starting the next conversion. Refer to Section 16.2

“ADC Operation” for more information.

16.1.3 ADC VOLTAGE REFERENCE

The ADPREF bits of the ADCON1 register provides

control of the positive voltage reference. The positive

voltage reference can be:

•V

REF+ pin

•V

• FVR 2.028V

• FVR 4.096V (Not available on LF devices)

The ADNREF bits of the ADCON1 register provides

control of the negative voltage reference. The negative

voltage reference can be:

•V

REF- pin

•VSS

See Section 14.0 “Fixed Voltage Reference (FVR)”

for more details on the fixed voltage reference.

16.1.4 CONVERSION CLOCK

The source of the conversion clock is software select-

able via the ADCS bits of the ADCON1 register. There

are seven possible clock options:

•F

OSC/2

•FOSC/4

•FOSC/8

•F

OSC/16

•FOSC/32

•FOSC/64

•F

RC (dedicated internal oscillator)

The time to complete one bit conversion is defined as

TAD. One full 10-bit conversion requires 11.5 TAD peri-

ods as shown in Figure 16-3.

For correct conversion, the appropriate TAD

specification must be met. Refer to the A/D conversion

requirements in Section 30.0 “Electrical

Specifications” for more information. Tab le 16 - 1 gives

examples of appropriate ADC clock selections.

Note: Analog voltages on any pin that is defined

as a digital input may cause the input buf-

fer to conduct excess current.

Note: Unless using the FRC, any changes in the

system clock frequency will change the

ADC clock frequency, which may

adversely affect the ADC result.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 151

PIC16(L)F1824/1828

TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES

FIGURE 16-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES

ADC Clock Period (TAD) Device Frequency (FOSC)

ADC

Clock Source ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz

Fosc/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s

Fosc/4 100 125 ns(2) 200 ns(2) 250 ns(2) 500 ns(2) 1.0 s4.0 s

Fosc/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) 1.0 s2.0 s8.0 s(3)

Fosc/16 101 800 ns 800 ns 1.0 s2.0 s4.0 s16.0 s(3)

Fosc/32 010 1.0 s1.6 s2.0 s4.0 s8.0 s(3) 32.0 s(3)

Fosc/64 110 2.0 s3.2 s4.0 s8.0 s(3) 16.0 s(3) 64.0 s(3)

FRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4)

Legend: Shaded cells are outside of recommended range.

Note 1: The FRC source has a typical TAD time of 1.6 s for VDD.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the

system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the

device in Sleep mode.

TAD1 TAD2TAD3TAD4 TAD5TAD6 TAD7TAD8TAD11

Set GO bit

Holding capacitor is disconnected from analog input (typically 100 ns)

TAD9 TAD10

TCY - TAD

ADRESH:ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

Conversion starts

b9 b6 b5 b4 b3 b2 b1

b8 b7

On the following cycle:

PIC16(L)F1824/1828

DS41419C-page 152 Preliminary  2010-2011 Microchip Technology Inc.

16.1.5 INTERRUPTS

The ADC module allows for the ability to generate an

interrupt upon completion of an Analog-to-Digital

conversion. The ADC Interrupt Flag is the ADIF bit in

the PIR1 register. The ADC Interrupt Enable is the

ADIE bit in the PIE1 register. The ADIF bit must be

cleared in software.

This interrupt can be generated while the device is

operating or while in Sleep. If the device is in Sleep, the

interrupt will wake-up the device. Upon waking from

Sleep, the next instruction following the SLEEP instruc-

tion is always executed. If the user is attempting to

wake-up from Sleep and resume in-line code execu-

tion, the GIE and PEIE bits of the INTCON register

must be disabled. If the GIE and PEIE bits of the

INTCON register are enabled, execution will switch to

the Interrupt Service Routine.

Please refer to Section 16.1.5 “Interrupts” for more

information.

16.1.6 RESULT FORMATTING

The 10-bit A/D conversion result can be supplied in two

formats, left justified or right justified. The ADFM bit of

the ADCON1 register controls the output format.

Figure 16-3 shows the two output formats.

FIGURE 16-3: 10-BIT A/D CONVERSION RESULT FORMAT

Note 1: The ADIF bit is set at the completion of

every conversion, regardless of whether

or not the ADC interrupt is enabled.

2: The ADC operates during Sleep only

when the FRC oscillator is selected.

ADRESH ADRESL

(ADFM = 0)MSB LSB

bit 7 bit 0 bit 7 bit 0

10-bit A/D Result Unimplemented: Read as ‘0’

(ADFM = 1)MSB LSB

bit 7 bit 0 bit 7 bit 0

Unimplemented: Read as ‘0’ 10-bit A/D Result

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PIC16(L)F1824/1828

16.2 ADC Operation

16.2.1 STARTING A CONVERSION

To enable the ADC module, the ADON bit of the

ADCON0 register must be set to a ‘1’. Setting the GO/

DONE bit of the ADCON0 register to a ‘1’ will start the

Analog-to-Digital conversion.

16.2.2 COMPLETION OF A CONVERSION

When the conversion is complete, the ADC module will:

• Clear the GO/DONE bit

• Set the ADIF Interrupt Flag bit

• Update the ADRESH and ADRESL registers with

new conversion result

16.2.3 TERMINATING A CONVERSION

If a conversion must be terminated before completion,

the GO/DONE bit can be cleared in software. The

ADRESH and ADRESL registers will be updated with

the partially complete Analog-to-Digital conversion

sample. Incomplete bits will match the last bit

converted.

16.2.4 ADC OPERATION DURING SLEEP

The ADC module can operate during Sleep. This

requires the ADC clock source to be set to the FRC

option. When the FRC clock source is selected, the

ADC waits one additional instruction before starting the

conversion. This allows the SLEEP instruction to be

executed, which can reduce system noise during the

conversion. If the ADC interrupt is enabled, the device

will wake-up from Sleep when the conversion

completes. If the ADC interrupt is disabled, the ADC

module is turned off after the conversion completes,

although the ADON bit remains set.

When the ADC clock source is something other than

FRC, a SLEEP instruction causes the present conver-

sion to be aborted and the ADC module is turned off,

although the ADON bit remains set.

16.2.5 SPECIAL EVENT TRIGGER

The Special Event Trigger of the CCPx/ECCPX module

allows periodic ADC measurements without software

intervention. When this trigger occurs, the GO/DONE

bit is set by hardware and the Timer1 counter resets to

zero.

Using the Special Event Trigger does not assure proper

ADC timing. It is the user’s responsibility to ensure that

the ADC timing requirements are met.

Refer to Section 24.0 “Capture/Compare/PWM

Modules” for more information.

Note: The GO/DONE bit should not be set in the

same instruction that turns on the ADC.

Refer to Section 16.2.6 “A/D Conver-

sion Procedure”.

Note: A device Reset forces all registers to their

Reset state. Thus, the ADC module is

turned off and any pending conversion is

terminated.

TABLE 16-2: SPECIAL EVENT TRIGGER

Device CCPx/ECCPx

PIC16(L)F1824/1828 CCP4

PIC16(L)F1824/1828

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16.2.6 A/D CONVERSION PROCEDURE

This is an example procedure for using the ADC to

perform an Analog-to-Digital conversion:

1. Configure Port:

• Disable pin output driver (Refer to the TRIS

• Configure pin as analog (Refer to the ANSEL

2. Configure the ADC module:

• Select ADC conversion clock

• Configure voltage reference

• Select ADC input channel

• Turn on ADC module

3. Configure ADC interrupt (optional):

• Clear ADC interrupt flag

• Enable ADC interrupt

• Enable peripheral interrupt

• Enable global interrupt(1)

4. Wait the required acquisition time(2).

5. Start conversion by setting the GO/DONE bit.

6. Wait for ADC conversion to complete by one of

the following:

• Polling the GO/DONE bit

• Waiting for the ADC interrupt (interrupts

enabled)

7. Read ADC Result.

8. Clear the ADC interrupt flag (required if interrupt

is enabled).

EXAMPLE 16-1: A/D CONVERSION

Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep

and resume in-line code execution.

2: Refer to Section 16.3 “A/D Acquisition

Requirements”.

;This code block configures the ADC

;for polling, Vdd and Vss references, Frc

;clock and AN0 input.

;

;Conversion start & polling for completion

; are included.

;

BANKSEL ADCON1 ;

MOVLW B’11110000’ ;Right justify, Frc

;clock

MOVWF ADCON1 ;Vdd and Vss Vref

BANKSEL TRISA ;

BSF TRISA,0 ;Set RA0 to input

BANKSEL ANSEL ;

BSF ANSEL,0 ;Set RA0 to analog

BANKSEL ADCON0 ;

MOVLW B’00000001’ ;Select channel AN0

MOVWF ADCON0 ;Turn ADC On

CALL SampleTime ;Acquisiton delay

BSF ADCON0,ADGO ;Start conversion

BTFSC ADCON0,ADGO ;Is conversion done?

GOTO $-1 ;No, test again

BANKSEL ADRESH ;

MOVF ADRESH,W ;Read upper 2 bits

MOVWF RESULTHI ;store in GPR space

BANKSEL ADRESL ;

MOVF ADRESL,W ;Read lower 8 bits

MOVWF RESULTLO ;Store in GPR space

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16.2.7 ADC REGISTER DEFINITIONS

The following registers are used to control the

operation of the ADC.

U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— CHS<4:0> GO/DONE ADON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘0’

bit 6-2 CHS<4:0>: Analog Channel Select bits

00000 =AN0

00001 =AN1

00010 =AN2

00011 =AN3

00100 =AN4

00101 =AN5

00110 =AN6

00111 =AN7

01000 =AN8

(2)

01001 =AN9

(2)

01010 =AN10

(2)

01011 =AN11

(2)

01100 = Reserved. No channel connected

•

11101 = Reserved. No channel connected

11110 = DAC output(1)

11111 = FVR (Fixed Voltage Reference) Buffer 1 Output(2)

bit 1 GO/DONE: A/D Conversion Status bit

1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.

This bit is automatically cleared by hardware when the A/D conversion has completed.

0 = A/D conversion completed/not in progress

bit 0 ADON: ADC Enable bit

1 = ADC is enabled

0 = ADC is disabled and consumes no operating current

Note 1: See Section 17.0 “Digital-to-Analog Converter (DAC) Module”for more information.

2: See Section 14.0 “Fixed Voltage Reference (FVR)” for more information.

3: PIC16(L)F1828 only.

PIC16(L)F1824/1828

DS41419C-page 156 Preliminary  2010-2011 Microchip Technology Inc.

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0

ADFM ADCS<2:0> — ADNREF ADPREF<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 ADFM: A/D Result Format Select bit

1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is

loaded.

0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is

loaded.

bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits

000 =F

OSC/2

001 =F

OSC/8

010 =F

OSC/32

011 =F

RC (clock supplied from a dedicated RC oscillator)

100 =F

OSC/4

101 =F

OSC/16

110 =F

OSC/64

111 =F

RC (clock supplied from a dedicated RC oscillator)

bit 3 Unimplemented: Read as ‘0’

bit 2 ADNREF: A/D Negative Voltage Reference Configuration bit

0 =VREF- is connected to VSS

1 =VREF- is connected to external VREF- pin(1)

bit 1-0 ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits

00 =V

REF+ is connected to VDD

01 = Reserved

10 =V

REF+ is connected to external VREF+ pin(1)

11 =VREF+ is connected to internal Fixed Voltage Reference (FVR) module

Note 1: When selecting the FVR or the VREF+ pin as the source of the positive reference, be aware that a

minimum voltage specification exists. See Section 30.0 “Electrical Specifications” for details.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 157

PIC16(L)F1824/1828

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

ADRES<9:2>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 ADRES<9:2>: ADC Result Register bits

Upper 8 bits of 10-bit conversion result

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

ADRES<1:0> — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 ADRES<1:0>: ADC Result Register bits

Lower 2 bits of 10-bit conversion result

bit 5-0 Reserved: Do not use.

PIC16(L)F1824/1828

DS41419C-page 158 Preliminary  2010-2011 Microchip Technology Inc.

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

— — — — — — ADRES<9:8>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-2 Reserved: Do not use.

bit 1-0 ADRES<9:8>: ADC Result Register bits

Upper 2 bits of 10-bit conversion result

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

ADRES<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 ADRES<7:0>: ADC Result Register bits

Lower 8 bits of 10-bit conversion result

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 159

PIC16(L)F1824/1828

16.3 A/D Acquisition Requirements

For the ADC to meet its specified accuracy, the charge

holding capacitor (CHOLD) must be allowed to fully

charge to the input channel voltage level. The Analog

Input model is shown in Figure 16-4. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge

the capacitor CHOLD. The sampling switch (RSS)

impedance varies over the device voltage (VDD), refer

to Figure 16-4. The maximum recommended

impedance for analog sources is 10 k. As the

source impedance is decreased, the acquisition time

may be decreased. After the analog input channel is

selected (or changed), an A/D acquisition must be

done before the conversion can be started. To calculate

the minimum acquisition time, Equation 16-1 may be

used. This equation assumes that 1/2 LSb error is used

(1,024 steps for the ADC). The 1/2 LSb error is the

maximum error allowed for the ADC to meet its

specified resolution.

EQUATION 16-1: ACQUISITION TIME EXAMPLE

TACQ Amplifier Settling Time Hold Capacitor Charging Time Temperature Coefficient++=

TAMP TCTCOFF++=

2µs TCTemperature - 25°C0.05µs/°C++=

TCCHOLD RIC RSS RS++ ln(1/511)–=

10pF 1k



10k



++– ln(0.001957)=

1.12=µs

VAPPLIED 1e

Tc–

---------

–







VAPPLIED 11

2n1+

1–

--------------------------–





VAPPLIED 11

2n1+

1–

--------------------------

–





VCHOLD=

VAPPLIED 1e

TC–

----------

–







VCHOLD=

;[1] VCHOLD charged to within 1/2 lsb

;[2] VCHOLD charge response to VAPPLIED

;combining [1] and [2]

The value for TC can be approximated with the following equations:

Solving for TC:

Therefore:

Temperature 50°C and external impedance of 10k



5.0V VDD=

Assumptions:

Note: Where n = number of bits of the ADC.

TACQ 2µs 1.12µs 50°C- 25°C0.05µs/°C++=

4.42µs=

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (CHOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin

leakage specification.

PIC16(L)F1824/1828

DS41419C-page 160 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 16-4: ANALOG INPUT MODEL

FIGURE 16-5: ADC TRANSFER FUNCTION

CPIN

Analog

5 pF

VDD

VT  0.6V

VT  0.6V I LEAKAGE(1)

RIC  1k

Sampling

Switch

SS Rss

CHOLD = 10 pF

VSS/VREF-

Sampling Switch

567891011

(k)

VDD

Legend:

CPIN

I LEAKAGE

RIC

CHOLD

= Input Capacitance

= Threshold Voltage

= Leakage current at the pin due to

= Interconnect Resistance

= Sampling Switch

= Sample/Hold Capacitance

various junctions

RSS

Note 1: Refer to Section 30.0 “Electrical Specifications”.

RSS = Resistance of Sampling Switch

Input

3FFh

3FEh

ADC Output Code

3FDh

3FCh

03h

02h

01h

00h

Full-Scale

3FBh

0.5 LSB

VREF-Zero-Scale

Transition VREF+

Transition

1.5 LSB

Full-Scale Range

Analog Input Voltage

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 161

PIC16(L)F1824/1828

TABLE 16-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC

Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

Page

ADCON0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 155

ADCON1 ADFM ADCS2 ADCS1 ADCS0 — ADNREF ADPREF1 ADPREF0 156

ADRESH A/D Result Register High 157, 154

ADRESL A/D Result Register Low 157, 154

ANSELA ——— ANSA4 — ANSA2 ANSA1 ANSA0 127

ANSELB(1) ANSB7 ANSB6 ANSB5 ANSB4 ————133

ANSELC ANSC7(1) ANSC6(1) —— ANSC3 ANSC2 ANSC1 ANSC0 138

INLVLA —— INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 128

INLVLB(1) INLVLA7 INLVLA6 INLVLA5 INLVLA4 ————133

INLVLC INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 139

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 94

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 97

TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 126

TRISB(1) TRISB7 TRISB6 TRISB5 TRISB4 ————132

TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 137

FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 146

DACCON0 DACEN DACLPS DACOE — DACPSS1 DACPSS0 —DACNSS166

DACCON1 ——— DACR4 DACR3 DACR2 DACR1 DACR0 166

Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not used for ADC

module.

Note 1: PIC16(L)F1828 only.

PIC16(L)F1824/1828

DS41419C-page 162 Preliminary  2010-2011 Microchip Technology Inc.

NOTES:

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 163

PIC16(L)F1824/1828

17.0 DIGITAL-TO-ANALOG

CONVERTER (DAC) MODULE

The Digital-to-Analog Converter supplies a variable

voltage reference, ratiometric with the input source,

with 32 selectable output levels.

The input of the DAC can be connected to:

•External V

REF pins

•VDD supply voltage

• FVR (Fixed Voltage Reference)

The output of the DAC can be configured to supply a

reference voltage to the following:

• Comparator positive input

• ADC input channel

•DACOUT pin

The Digital-to-Analog Converter (DAC) can be enabled

by setting the DACEN bit of the DACCON0 register.

17.1 Output Voltage Selection

The DAC has 32 voltage level ranges. The 32 levels

are set with the DACR<4:0> bits of the DACCON1

The DAC output voltage is determined by the following

equations:

EQUATION 17-1: DAC OUTPUT VOLTAGE

17.2 Ratiometric Output Level

The DAC output value is derived using a resistor ladder

with each end of the ladder tied to a positive and

negative voltage reference input source. If the voltage

of either input source fluctuates, a similar fluctuation will

result in the DAC output value.

The value of the individual resistors within the ladder

can be found in Section 30.0 “Electrical

Specifications”.

17.3 DAC Voltage Reference Output

The DAC can be output to the DACOUT pin by setting

the DACOE bit of the DACCON0 register to ‘1’. Selecting

the DAC reference voltage for output on the DACOUT

pin automatically overrides the digital output buffer and

digital input threshold detector functions of that pin.

Reading the DACOUT pin when it has been configured

for DAC reference voltage output will always return a ‘0’.

Due to the limited current drive capability, a buffer must

be used on the DAC voltage reference output for

external connections to DACOUT. Figure 17-2 shows

an example buffering technique.

VOUT VSOURCE+VSOURCE-–

DACR<4:0>

-------------------------------





=+ VSRC-

Note: VSOURCE+ can equal FVR Buffer 2, VDD or

VREF+. VSOURCE- can equal VSS or VREF-.

PIC16(L)F1824/1828

DS41419C-page 164 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 17-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM

FIGURE 17-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

32-to-1 MUX

DACR<4:0>

VREF-

32 DAC

DACOUT

(To Comparator, CSM and

ADC Modules)

DACOE

VDD

VREF+

DACPSS<1:0> 2

DACEN

Steps

Digital-to-Analog Converter (DAC)

FVR BUFFER2

VSRC-

VSRC+

VSS

DACLPS

DACNSS

DACOUT Buffered DAC Output

–

DAC

Module

Voltage

Reference

Output

Impedance

PIC® MCU

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 165

PIC16(L)F1824/1828

17.4 Low Power Voltage State

In order for the DAC module to consume the least

amount of power, one of the two voltage reference input

sources to the resistor ladder must be disconnected.

Either the positive voltage source, (VSRC+), or the

negative voltage source, (VSRC-) can be disabled.

The negative voltage source is disabled by setting the

DACLPS bit in the DACCON0 register. Clearing the

DACLPS bit in the DACCON0 register disables the

positive voltage source.

17.4.1 OUTPUT CLAMPED TO POSITIVE

VOLTAGE SOURCE

The DAC output voltage can be set to VSRC+ with the

least amount of power consumption by performing the

following:

• Clearing the DACEN bit in the DACCON0 register.

• Setting the DACLPS bit in the DACCON0 register.

• Configuring the DACPSS bits to the proper

positive source.

• Configuring the DACR<4:0> bits to ‘11111’ in the

DACCON1 register.

This is also the method used to output the voltage level

from the FVR to an output pin. See Figure 17-2 for more

information.

Reference Figure 17-3 for output clamping examples.

17.4.2 OUTPUT CLAMPED TO NEGATIVE

VOLTAGE SOURCE

The DAC output voltage can be set to VSRC- with the

least amount of power consumption by performing the

following:

• Clearing the DACEN bit in the DACCON0 register.

• Clearing the DACLPS bit in the DACCON0 register.

• Configuring the DACNSS bits to the proper

negative source.

• Configuring the DACR<4:0> bits to ‘00000’ in the

DACCON1 register.

This allows the comparator to detect a zero-crossing

while not consuming additional current through the DAC

module.

Reference Figure 17-3 for output clamping examples.

FIGURE 17-3: OUTPUT VOLTAGE CLAMPING EXAMPLES

17.5 Operation During Sleep

When the device wakes up from Sleep through an

interrupt or a Watchdog Timer time-out, the contents of

the DACCON0 register are not affected. To minimize

current consumption in Sleep mode, the voltage

reference should be disabled.

17.6 Effects of a Reset

A device Reset affects the following:

• DAC is disabled.

• DAC output voltage is removed from the

DACOUT pin.

• The DACR<4:0> range select bits are cleared.

DAC Voltage Ladder

(see Figure 17-1)

VSRC+

DACEN = 0

DACLPS = 1

DACR<4:0> = 11111

VSRC-

DAC Voltage Ladder

(see Figure 17-1)

VSRC+

DACEN = 0

DACLPS = 0

DACR<4:0> = 00000

VSRC-

Output Clamped to Positive Voltage Source Output Clamped to Negative Voltage Source

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R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 U-0

DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 DACEN: DAC Enable bit

1 = DAC is enabled

0 = DAC is disabled

bit 6 DACLPS: DAC Low-Power Voltage State Select bit

1 = DAC Positive reference source selected

0 = DAC Negative reference source selected

bit 5 DACOE: DAC Voltage Output Enable bit

1 = DAC voltage level is also an output on the DACOUT pin

0 = DAC voltage level is disconnected from the DACOUT pin

bit 4 Unimplemented: Read as ‘0’

bit 3-2 DACPSS<1:0>: DAC Positive Source Select bits

00 =V

01 =VREF+

10 = FVR Buffer2 output

11 = Reserved, do not use

bit 1 Unimplemented: Read as ‘0’

bit 0 DACNSS: DAC Negative Source Select bit

1 =V

REF-

0 =V

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— — — DACR<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 DACR<4:0>: DAC Voltage Output Select bits

VOUT = ((VSRC+) - (VSRC-))*(DACR<4:0>/(25)) + VSRC-

Note 1: The output select bits are always right justified to ensure that any number of bits can be used without

affecting the register layout.

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PIC16(L)F1824/1828

TABLE 17-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on page

FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 146

DACCON0 DACEN DACLPS DACOE — DACPSS1 DACPSS0 — DACNSS 166

DACCON1 — — — DACR4 DACR3 DACR2 DACR1 DACR0 166

Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the DAC module.

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NOTES:

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PIC16(L)F1824/1828

18.0 SR LATCH

The module consists of a single SR latch with multiple

Set and Reset inputs as well as separate latch outputs.

The SR latch module includes the following features:

• Programmable input selection

• SR latch output is available externally

• Separate Q and Q outputs

• Firmware Set and Reset

The SR latch can be used in a variety of analog appli-

cations, including oscillator circuits, one-shot circuit,

hysteretic controllers, and analog timing applications.

18.1 Latch Operation

The latch is a Set-Reset latch that does not depend on a

clock source. Each of the Set and Reset inputs are

active-high. The latch can be Set or Reset by:

• Software control (SRPS and SRPR bits)

• Comparator C1 output (SYNCC1OUT)

• Comparator C2 output (SYNCC2OUT)

•SRI pin

• Programmable clock (SRCLK)

The SRPS and the SRPR bits of the SRCON0 register

may be used to Set or Reset the SR latch, respectively.

The latch is Reset-dominant. Therefore, if both Set and

Reset inputs are high, the latch will go to the Reset

state. Both the SRPS and SRPR bits are self resetting

which means that a single write to either of the bits is all

that is necessary to complete a latch Set or Reset oper-

ation.

The output from Comparator C1 or C2 can be used as

the Set or Reset inputs of the SR latch. The output of

either Comparator can be synchronized to the Timer1

clock source. See Section 19.0 “Comparator

Module” and Section 21.0 “Timer1 Module with

Gate Control” for more information.

An external source on the SRI pin can be used as the

Set or Reset inputs of the SR latch.

An internal clock source is available that can periodically

set or reset the SR latch. The SRCLK<2:0> bits in the

SRCON0 register are used to select the clock source

period. The SRSCKE and SRRCKE bits of the SRCON1

latch, respectively.

18.2 Latch Output

The SRQEN and SRNQEN bits of the SRCON0 regis-

ter control the Q and Q latch outputs. Both of the SR

latch outputs may be directly output to an I/O pin at the

same time.

The applicable TRIS bit of the corresponding port must

be cleared to enable the port pin output driver.

18.3 Effects of a Reset

Upon any device Reset, the SR latch output is not

initialized to a known state. The user’s firmware is

responsible for initializing the latch output before

enabling the output pins.

Note: Enabling both the Set and Reset inputs

from any one source at the same time

may result in indeterminate operation, as

the Reset dominance cannot be assured.

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FIGURE 18-1: SR LATCH SIMPLIFIED BLOCK DIAGRAM

SRPS

Note 1: If R = 1 and S = 1 simultaneously, Q = 0, Q =1

2: Pulse generator causes a 1 Q-state pulse width.

3: Name denotes the connection point at the comparator output.

Pulse

Gen(2)

Latch(1)

SRQEN

SRSPE

SRSC2E

SRSCKE

SRCLK

SYNCC2OUT(3)

SRSC1E

SYNCC1OUT(3)

SRPR Pulse

Gen(2)

SRRPE

SRRC2E

SRRCKE

SRCLK

SYNCC2OUT(3)

SRRC1E

SYNCC1OUT(3)

SRLEN

SRNQEN

SRLEN

SRQ

SRNQ

SRI

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PIC16(L)F1824/1828

TABLE 18-1: SRCLK FREQUENCY TABLE

SRCLK Divider FOSC = 32 MHz FOSC = 20 MHz FOSC = 16 MHz FOSC = 4 MHz FOSC = 1 MHz

111 512 62.5 kHz 39.0 kHz 31.3 kHz 7.81 kHz 1.95 kHz

110 256 125 kHz 78.1 kHz 62.5 kHz 15.6 kHz 3.90 kHz

101 128 250 kHz 156 kHz 125 kHz 31.25 kHz 7.81 kHz

100 64 500 kHz 313 kHz 250 kHz 62.5 kHz 15.6 kHz

011 32 1 MHz 625 kHz 500 kHz 125 kHz 31.3 kHz

010 16 2 MHz 1.25 MHz 1 MHz 250 kHz 62.5 kHz

001 8 4 MHz 2.5 MHz 2 MHz 500 kHz 125 kHz

000 4 8 MHz 5 MHz 4 MHz 1 MHz 250 kHz

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/S-0/0 R/S-0/0

SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared S = Bit is set only

bit 7 SRLEN: SR Latch Enable bit

1 = SR latch is enabled

0 = SR latch is disabled

bit 6-4 SRCLK<2:0>: SR Latch Clock Divider bits

000 = Generates a 1 FOSC wide pulse every 4th FOSC cycle clock

001 = Generates a 1 FOSC wide pulse every 8th FOSC cycle clock

010 = Generates a 1 FOSC wide pulse every 16th FOSC cycle clock

011 = Generates a 1 FOSC wide pulse every 32nd FOSC cycle clock

100 = Generates a 1 FOSC wide pulse every 64th FOSC cycle clock

101 = Generates a 1 FOSC wide pulse every 128th FOSC cycle clock

110 = Generates a 1 FOSC wide pulse every 256th FOSC cycle clock

111 = Generates a 1 FOSC wide pulse every 512th FOSC cycle clock

bit 3 SRQEN: SR Latch Q Output Enable bit

If SRLEN = 1:

1 = Q is present on the SRQ pin

0 = External Q output is disabled

If SRLEN = 0:

SR latch is disabled

bit 2 SRNQEN: SR Latch Q Output Enable bit

If SRLEN = 1:

1 =Q

is present on the SRnQ pin

0 = External Q output is disabled

If SRLEN = 0:

SR latch is disabled

bit 1 SRPS: Pulse Set Input of the SR Latch bit(1)

1 = Pulse set input for 1 Q-clock period

0 = No effect on set input.

bit 0 SRPR: Pulse Reset Input of the SR Latch bit(1)

1 = Pulse reset input for 1 Q-clock period

0 = No effect on reset input.

Note 1: Set only, always reads back ‘0’.

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R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 SRSPE: SR Latch Peripheral Set Enable bit

1 = SR latch is set when the SRI pin is high

0 = SRI pin has no effect on the set input of the SR latch

bit 6 SRSCKE: SR Latch Set Clock Enable bit

1 = Set input of SR latch is pulsed with SRCLK

0 = SRCLK has no effect on the set input of the SR latch

bit 5 SRSC2E: SR Latch C2 Set Enable bit

1 = SR latch is set when the C2 Comparator output is high

0 = C2 Comparator output has no effect on the set input of the SR latch

bit 4 SRSC1E: SR Latch C1 Set Enable bit

1 = SR latch is set when the C1 Comparator output is high

0 = C1 Comparator output has no effect on the set input of the SR latch

bit 3 SRRPE: SR Latch Peripheral Reset Enable bit

1 = SR latch is reset when the SRI pin is high

0 = SRI pin has no effect on the reset input of the SR latch

bit 2 SRRCKE: SR Latch Reset Clock Enable bit

1 = Reset input of SR latch is pulsed with SRCLK

0 = SRCLK has no effect on the reset input of the SR latch

bit 1 SRRC2E: SR Latch C2 Reset Enable bit

1 = SR latch is reset when the C2 Comparator output is high

0 = C2 Comparator output has no effect on the reset input of the SR latch

bit 0 SRRC1E: SR Latch C1 Reset Enable bit

1 = SR latch is reset when the C1 Comparator output is high

0 = C1 Comparator output has no effect on the reset input of the SR latch

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TABLE 18-2: SUMMARY OF REGISTERS ASSOCIATED WITH SR LATCH MODULE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

ANSELA — — —ANSA4—ANSA2 ANSA1 ANSA0 127

INLVLA — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 128

INLVLC INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 139

SRCON0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 171

SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 171

TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 126

TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 137

Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the SR latch module.

Note 1: PIC16(L)F1828 only.

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NOTES:

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PIC16(L)F1824/1828

19.0 COMPARATOR MODULE

Comparators are used to interface analog circuits to a

digital circuit by comparing two analog voltages and

providing a digital indication of their relative magnitudes.

Comparators are very useful mixed signal building

blocks because they provide analog functionality

independent of program execution. The analog

comparator module includes the following features:

• Independent comparator control

• Programmable input selection

• Comparator output is available internally/externally

• Programmable output polarity

• Interrupt-on-change

• Wake-up from Sleep

• Programmable Speed/Power optimization

•PWM shutdown

• Programmable and fixed voltage reference

19.1 Comparator Overview

A single comparator is shown in Figure 19-1 along with

the relationship between the analog input levels and

the digital output. When the analog voltage at VIN+ is

less than the analog voltage at VIN-, the output of the

comparator is a digital low level. When the analog

voltage at VIN+ is greater than the analog voltage at

VIN-, the output of the comparator is a digital high level.

FIGURE 19-1: SINGLE COMPARATOR

–

VIN+

VIN-Output

Output

VIN+

VIN-

Note: The black areas of the output of the

comparator represents the uncertainty

due to input offsets and response time.

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FIGURE 19-2: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM

Note 1: When CxON = 0, the Comparator will produce a ‘0’ at the output

2: When CxON = 0, all multiplexer inputs are disconnected.

3: Output of comparator can be frozen during debugging.

MUX

Cx(3)

CxON(1)

CxNCH<1:0>

CXPCH<1:0>

C12IN1-

C12IN2-

C12IN3-

CXIN+

MUX

CxVN

CxVP

CXOUT

To ECCP PWM Logic

CXPOL

MCXOUT

Set CxIF

CXSYNC CXOE

CXOUT

SYNCCXOUT

DAC

FVR Buffer2

C12IN0-

CxSP

CxHYS

det

Interrupt

det

Interrupt

CxINTN

CxINTP

To D ata Bus

VSS TRIS bit

CxON

(2)

(from Timer1)

T1CLK To Timer1 or SR Latch

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19.2 Comparator Control

Each comparator has 2 control registers: CMxCON0 and

CMxCON1.

The CMxCON0 registers (see Register 19-1) contain

Control and Status bits for the following:

• Enable

•Output selection

• Output polarity

• Speed/Power selection

• Hysteresis enable

• Output synchronization

The CMxCON1 registers (see Register 19-2) contain

Control bits for the following:

• Interrupt enable

• Interrupt edge polarity

• Positive input channel selection

• Negative input channel selection

19.2.1 COMPARATOR ENABLE

Setting the CxON bit of the CMxCON0 register enables

the comparator for operation. Clearing the CxON bit

disables the comparator resulting in minimum current

consumption.

19.2.2 COMPARATOR OUTPUT

SELECTION

The output of the comparator can be monitored by

reading either the CxOUT bit of the CMxCON0 register

or the MCxOUT bit of the CMOUT register. In order to

make the output available for an external connection,

the following conditions must be true:

• CxOE bit of the CMxCON0 register must be set

• Corresponding TRIS bit must be cleared

• CxON bit of the CMxCON0 register must be set

19.2.3 COMPARATOR OUTPUT POLARITY

Inverting the output of the comparator is functionally

equivalent to swapping the comparator inputs. The

polarity of the comparator output can be inverted by

setting the CxPOL bit of the CMxCON0 register.

Clearing the CxPOL bit results in a non-inverted output.

Table 19-1 shows the output state versus input

conditions, including polarity control.

19.2.4 COMPARATOR SPEED/POWER

SELECTION

The trade-off between speed or power can be opti-

mized during program execution with the CxSP control

bit. The default state for this bit is ‘1’ which selects the

normal speed mode. Device power consumption can

be optimized at the cost of slower comparator propaga-

tion delay by clearing the CxSP bit to ‘0’.

Note 1: The CxOE bit of the CMxCON0 register

overrides the PORT data latch. Setting

the CxON bit of the CMxCON0 register

has no impact on the port override.

2: The internal output of the comparator is

latched with each instruction cycle.

Unless otherwise specified, external

outputs are not latched.

TABLE 19-1: COMPARATOR OUTPUT

STATE VS. INPUT

CONDITIONS

Input Condition CxPOL CxOUT

CxVN > CxVP00

CxVN < CxVP01

CxVN > CxVP10

CxVN < CxVP11

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19.3 Comparator Hysteresis

A selectable amount of separation voltage can be

added to the input pins of each comparator to provide a

hysteresis function to the overall operation. Hysteresis

is enabled by setting the CxHYS bit of the CMxCON0

See Section 30.0 “Electrical Specifications” for

more information.

19.4 Timer1 Gate Operation

The output resulting from a comparator operation can

be used as a source for gate control of Timer1. See

Section 21.6 “Timer1 Gate” for more information.

This feature is useful for timing the duration or interval

of an analog event.

It is recommended that the comparator output be syn-

chronized to Timer1. This ensures that Timer1 does not

increment while a change in the comparator is occur-

ring.

19.4.1 COMPARATOR OUTPUT

SYNCHRONIZATION

The output from either comparator, C1 or C2, can be

synchronized with Timer1 by setting the CxSYNC bit of

the CMxCON0 register.

Once enabled, the comparator output is latched on the

falling edge of the Timer1 source clock. If a prescaler is

used with Timer1, the comparator output is latched after

the prescaling function. To prevent a race condition, the

comparator output is latched on the falling edge of the

Timer1 clock source and Timer1 increments on the

rising edge of its clock source. See the Comparator

Block Diagrams (Figure 19-2 and Figure 19-2) and the

Timer1 Block Diagram (Figure 20-1) for more

information.

19.5 Comparator Interrupt

An interrupt can be generated upon a change in the

output value of the comparator for each comparator, a

rising edge detector and a Falling edge detector are

present.

When either edge detector is triggered and its

associated enable bit is set (CxINTP and/or CxINTN

bits of the CMxCON1 register), the Corresponding

Interrupt Flag bit (CxIF bit of the PIR2 register) will be

set.

To enable the interrupt, you must set the following bits:

• CxON, CxPOL and CxSP bits of the CMxCON0

• CxIE bit of the PIE2 register

• CxINTP bit of the CMxCON1 register (for a rising

edge detection)

• CxINTN bit of the CMxCON1 register (for a falling

edge detection)

• PEIE and GIE bits of the INTCON register

The associated interrupt flag bit, CxIF bit of the PIR2

detected while this flag is being cleared, the flag will still

be set at the end of the sequence.

19.6 Comparator Positive Input

Selection

Configuring the CxPCH<1:0> bits of the CMxCON1

analog pin to the non-inverting input of the comparator:

• CxIN+ analog pin

•DAC

• FVR (Fixed Voltage Reference)

•V

SS (Ground)

See Section 14.0 “Fixed Voltage Reference (FVR)”

for more information on the Fixed Voltage Reference

module.

See Section 17.0 “Digital-to-Analog Converter

(DAC) Module” for more information on the DAC input

signal.

Any time the comparator is disabled (CxON = 0), all

comparator inputs are disabled.

Note: Although a comparator is disabled, an

interrupt can be generated by changing

the output polarity with the CxPOL bit of

the CMxCON0 register, or by switching

the comparator on or off with the CxON bit

of the CMxCON0 register.

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19.7 Comparator Negative Input

Selection

The CxNCH<1:0> bits of the CMxCON0 register direct

one of four analog pins to the comparator inverting

input.

19.8 Comparator Response Time

The comparator output is indeterminate for a period of

time after the change of an input source or the selection

of a new reference voltage. This period is referred to as

the response time. The response time of the comparator

differs from the settling time of the voltage reference.

Therefore, both of these times must be considered when

determining the total response time to a comparator

input change. See the Comparator and Voltage Refer-

ence Specifications in Section 30.0 “Electrical Specifi-

cations” for more details.

19.9 Interaction with ECCP Logic

The C1 and C2 comparators can be used as general

purpose comparators. Their outputs can be brought

out to the C1OUT and C2OUT pins. When the ECCP

Auto-Shutdown is active it can use one or both

comparator signals. If auto-restart is also enabled, the

comparators can be configured as a closed loop

analog feedback to the ECCP, thereby, creating an

analog controlled PWM.

19.10 Analog Input Connection

Considerations

A simplified circuit for an analog input is shown in

Figure 19-3. Since the analog input pins share their

connection with a digital input, they have reverse

biased ESD protection diodes to VDD and VSS. The

analog input, therefore, must be between VSS and VDD.

If the input voltage deviates from this range by more

than 0.6V in either direction, one of the diodes is for-

ward biased and a latch-up may occur.

A maximum source impedance of 10 k is recommended

for the analog sources. Also, any external component

connected to an analog input pin, such as a capacitor or

a Zener diode, should have very little leakage current to

minimize inaccuracies introduced.

Note: To use CxIN+ and CxINx- pins as analog

input, the appropriate bits must be set in

the ANSEL register and the correspond-

ing TRIS bits must also be set to disable

the output drivers.

Note: When the comparator module is first

initialized the output state is unknown.

Upon initialization, the user should verify

the output state of the comparator prior to

relying on the result, primarily when using

the result in connection with other

peripheral features, such as the ECCP

Auto-Shutdown mode.

Note 1: When reading a PORT register, all pins

configured as analog inputs will read as a

‘0’. Pins configured as digital inputs will

convert as an analog input, according to

the input specification.

2: Analog levels on any pin defined as a

digital input, may cause the input buffer to

consume more current than is specified.

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FIGURE 19-3: ANALOG INPUT MODEL

Rs < 10K

CPIN

5 pF

VDD

VT  0.6V

RIC

ILEAKAGE(1)

Vss

Legend: CPIN = Input Capacitance

ILEAKAGE = Leakage Current at the pin due to various junctions

RIC = Interconnect Resistance

RS= Source Impedance

VA= Analog Voltage

VT= Threshold Voltage

To Comparator

Note 1: See Section 30.0 “Electrical Specifications”.

Analog

Input

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R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 U-0 R/W-1/1 R/W-0/0 R/W-0/0

CxON CxOUT CxOE CxPOL —CxSP CxHYS CxSYNC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 CxON: Comparator Enable bit

1 = Comparator is enabled and consumes no active power

0 = Comparator is disabled

bit 6 CxOUT: Comparator Output bit

If CxPOL = 1 (inverted polarity):

1 = CxVP < CxVN

0 = CxVP > CxVN

If CxPOL = 0 (non-inverted polarity):

1 = CxVP > CxVN

0 = CxVP < CxVN

bit 5 CxOE: Comparator Output Enable bit

1 = CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually

drive the pin. Not affected by CxON.

0 = CxOUT is internal only

bit 4 CxPOL: Comparator Output Polarity Select bit

1 = Comparator output is inverted

0 = Comparator output is not inverted

bit 3 Unimplemented: Read as ‘0’

bit 2 CxSP: Comparator Speed/Power Select bit

1 = Comparator operates in normal power, higher speed mode

0 = Comparator operates in low-power, low-speed mode

bit 1 CxHYS: Comparator Hysteresis Enable bit

1 = Comparator hysteresis enabled

0 = Comparator hysteresis disabled

bit 0 CxSYNC: Comparator Output Synchronous Mode bit

1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source.

Output updated on the falling edge of Timer1 clock source.

0 = Comparator output to Timer1 and I/O pin is asynchronous.

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R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0

CxINTP CxINTN CxPCH<1:0> — — CxNCH<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits

1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit

0 = No interrupt flag will be set on a positive going edge of the CxOUT bit

bit 6 CxINTN: Comparator Interrupt on Negative Going Edge Enable bits

1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit

0 = No interrupt flag will be set on a negative going edge of the CxOUT bit

bit 5-4 CxPCH<1:0>: Comparator Positive Input Channel Select bits

00 = CxVP connects to CxIN+ pin

01 = CxVP connects to DAC Voltage Reference

10 = CxVP connects to FVR Voltage Reference

11 = CxVP connects to VSS

bit 3-2 Unimplemented: Read as ‘0’

bit 1-0 CxNCH<1:0>: Comparator Negative Input Channel Select bits

00 = CxVN connects to C12IN0- pin

01 = CxVN connects to C12IN1- pin

10 = CxVN connects to C12IN2- pin

11 = CxVN connects to C12IN3- pin

U-0 U-0 U-0 U-0 U-0 U-0 R-0/0 R-0/0

— — — — — — MC2OUT MC1OUT

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-2 Unimplemented: Read as ‘0’

bit 1 MC2OUT: Mirror Copy of C2OUT bit

bit 0 MC1OUT: Mirror Copy of C1OUT bit

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TABLE 19-2: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

CM1CON0 C1ON C1OUT C1OE C1POL --- C1SP C1HYS C1SYNC 181

CM2CON0 C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC 181

CM1CON1 C1NTP C1INTN C1PCH1 C1PCH0 —— C1NCH1 C1NCH0 182

CM2CON1 C2NTP C2INTN C2PCH1 C2PCH0 —— C2NCH1 C2NCH0 182

CMOUT — — — — — — MC2OUT MC1OUT 182

DACCON0 DACEN DACLPS DACOE — DACPSS1 DACPSS0 — DACNSS 166

DACCON1 — — — DACR4 DACR3 DACR2 DACR1 DACR0 166

FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 146

INLVLA — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 128

INLVLC INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 139

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93

PIE2 OSFIE C2IE C1IE EEIE BCLIE — — CCP2IE 95

PIR2 OSFIF C2IF C1IF EEIF BCLIF — — CCP2IF 98

TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 126

TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 137

Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.

Note 1: PIC16(L)F1828 only.

PIC16(L)F1824/1828

DS41419C-page 184 Preliminary  2010-2011 Microchip Technology Inc.

NOTES:

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 185

PIC16(L)F1824/1828

20.0 TIMER0 MODULE

The Timer0 module is an 8-bit timer/counter with the

following features:

• 8-bit timer/counter register (TMR0)

• 8-bit prescaler (independent of Watchdog Timer)

• Programmable internal or external clock source

• Programmable external clock edge selection

• Interrupt on overflow

• TMR0 can be used to gate Timer1

Figure 20-1 is a block diagram of the Timer0 module.

20.1 Timer0 Operation

The Timer0 module can be used as either an 8-bit timer

or an 8-bit counter.

20.1.1 8-BIT TIMER MODE

The Timer0 module will increment every instruction

cycle, if used without a prescaler. 8-bit Timer mode is

selected by clearing the TMR0CS bit of the

OPTION_REG register.

When TMR0 is written, the increment is inhibited for

two instruction cycles immediately following the write.

20.1.2 8-BIT COUNTER MODE

In 8-Bit Counter mode, the Timer0 module will increment

on every rising or falling edge of the T0CKI pin or the

Capacitive Sensing Oscillator (CPSCLK) signal.

8-Bit Counter mode using the T0CKI pin is selected by

setting the TMR0CS bit in the OPTION_REG register to

‘1’ and resetting the T0XCS bit in the CPSCON0 register

to ‘0’.

8-Bit Counter mode using the Capacitive Sensing

Oscillator (CPSCLK) signal is selected by setting the

TMR0CS bit in the OPTION_REG register to ‘1’ and

setting the T0XCS bit in the CPSCON0 register to ‘1’.

The rising or falling transition of the incrementing edge

for either input source is determined by the TMR0SE bit

in the OPTION_REG register.

FIGURE 20-1: BLOCK DIAGRAM OF THE TIMER0

Note: The value written to the TMR0 register

can be adjusted, in order to account for

the two instruction cycle delay when

TMR0 is written.

T0CKI

TMR0SE

TMR0

PS<2:0>

Data Bus

Set Flag bit TMR0IF

on Overflow

TMR0CS

8-bit

Prescaler

FOSC/4

PSA

Sync

2 TCY

Overflow to Timer1

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20.1.3 SOFTWARE PROGRAMMABLE

PRESCALER

A software programmable prescaler is available for

exclusive use with Timer0. The prescaler is enabled by

clearing the PSA bit of the OPTION_REG register.

There are 8 prescaler options for the Timer0 module

ranging from 1:2 to 1:256. The prescale values are

selectable via the PS<2:0> bits of the OPTION_REG

Timer0 module, the prescaler must be disabled by set-

ting the PSA bit of the OPTION_REG register.

The prescaler is not readable or writable. All instructions

writing to the TMR0 register will clear the prescaler.

20.1.4 TIMER0 INTERRUPT

Timer0 will generate an interrupt when the TMR0

interrupt flag bit of the INTCON register is set every

time the TMR0 register overflows, regardless of

whether or not the Timer0 interrupt is enabled. The

TMR0IF bit can only be cleared in software. The Timer0

interrupt enable is the TMR0IE bit of the INTCON

20.1.5 8-BIT COUNTER MODE

SYNCHRONIZATION

When in 8-Bit Counter mode, the incrementing edge on

the T0CKI pin must be synchronized to the instruction

clock. Synchronization can be accomplished by

sampling the prescaler output on the Q2 and Q4 cycles

of the instruction clock. The high and low periods of the

external clocking source must meet the timing

requirements as shown in Section 30.0 “Electrical

Specifications”.

20.1.6 OPERATION DURING SLEEP

Timer0 cannot operate while the processor is in Sleep

mode. The contents of the TMR0 register will remain

unchanged while the processor is in Sleep mode.

Note: The Watchdog Timer (WDT) uses its own

independent prescaler.

Note: The Timer0 interrupt cannot wake the

processor from Sleep since the timer is

frozen during Sleep.

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20.2 Option and Timer0 Control Registers

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1

WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 WPUEN: Weak Pull-up Enable bit

1 = All weak pull-ups are disabled (except MCLR, if it is enabled)

0 = Weak pull-ups are enabled by individual WPUx latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of INT pin

0 = Interrupt on falling edge of INT pin

bit 5 TMR0CS: Timer0 Clock Source Select bit

1 = Transition on T0CKI pin

0 = Internal instruction cycle clock (FOSC/4)

bit 4 TMR0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is not assigned to the Timer0 module

0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS<2:0>: Prescaler Rate Select bits

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

Bit Value Timer0 Rate

PIC16(L)F1824/1828

DS41419C-page 188 Preliminary  2010-2011 Microchip Technology Inc.

TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

CPSCON0 CPSON CPSRM — — CPSRNG1 CPSRNG0 CPSOUT T0XCS 331

FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 146

INLVLA — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 128

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93

OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 187

TMR0 Timer0 Module Register 185*

TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 126

Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.

* Page provides register information.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 189

PIC16(L)F1824/1828

21.0 TIMER1 MODULE WITH GATE

CONTROL

The Timer1 module is a 16-bit timer/counter with the

following features:

• 16-bit timer/counter register pair (TMR1H:TMR1L)

• Programmable internal or external clock source

• 2-bit prescaler

• Dedicated 32 kHz oscillator circuit

• Optionally synchronized comparator out

• Multiple Timer1 gate (count enable) sources

• Interrupt on overflow

• Wake-up on overflow (external clock,

Asynchronous mode only)

• Time base for the Capture/Compare function

• Special Event Trigger (with CCP/ECCP)

• Selectable Gate Source Polarity

• Gate Toggle Mode

• Gate Single-pulse Mode

• Gate Value Status

• Gate Event Interrupt

Figure 21-1 is a block diagram of the Timer1 module.

FIGURE 21-1: TIMER1 BLOCK DIAGRAM

TMR1H TMR1L

T1SYNC

T1CKPS<1:0>

Prescaler

1, 2, 4, 8

Synchronized

clock input

Set flag bit

TMR1IF on

Overflow TMR1(2)

TMR1ON

Note 1: ST Buffer is high speed type when using T1CKI.

2: Timer1 register increments on rising edge.

3: Synchronize does not operate while in Sleep.

T1G

T1OSC

FOSC/4

Internal

Clock

T1OSO

T1OSI

T1OSCEN

T1CKI

TMR1CS<1:0>

(1)

Synchronize(3)

det

Sleep input

TMR1GE

T1GPOL

T1GVAL

T1GTM

Single Pulse

Acq. Control

T1GSPM

T1GGO/DONE

T1GSS<1:0>

OUT

FOSC

Internal

Clock

Cap. Sensing

T1GCON

Data Bus

det

Interrupt

TMR1GIF

Set

T1CLK

FOSC/2

Internal

Clock

T1G_IN

TMR1ON

Oscillator

From Timer0

Comparator 1

Overflow

Comparator 2

SYNCC2OUT

SYNCC1OUT

To Comparator Module

To Clock Switching Modules

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DS41419C-page 190 Preliminary  2010-2011 Microchip Technology Inc.

21.1 Timer1 Operation

The Timer1 module is a 16-bit incrementing counter

which is accessed through the TMR1H:TMR1L register

pair. Writes to TMR1H or TMR1L directly update the

counter.

When used with an internal clock source, the module is

a timer and increments on every instruction cycle.

When used with an external clock source, the module

can be used as either a timer or counter and incre-

ments on every selected edge of the external source.

Timer1 is enabled by configuring the TMR1ON and

TMR1GE bits in the T1CON and T1GCON registers,

respectively. Table 21-1 displays the Timer1 enable

selections.

21.2 Clock Source Selection

The TMR1CS<1:0> and T1OSCEN bits of the T1CON

Table 21-2 displays the clock source selections.

21.2.1 INTERNAL CLOCK SOURCE

When the internal clock source is selected the

TMR1H:TMR1L register pair will increment on multiples

of FOSC as determined by the Timer1 prescaler.

When the FOSC internal clock source is selected, the

Timer1 register value will increment by four counts every

instruction clock cycle. Due to this condition, a 2 LSB

error in resolution will occur when reading the Timer1

value. To utilize the full resolution of Timer1, an

asynchronous input signal must be used to gate the

Timer1 clock input.

The following asynchronous sources may be used:

• Asynchronous event on the T1G pin to Timer1

gate

• C1 or C2 comparator input to Timer1 gate

21.2.2 EXTERNAL CLOCK SOURCE

When the external clock source is selected, the Timer1

module may work as a timer or a counter.

When enabled to count, Timer1 is incremented on the

rising edge of the external clock input T1CKI or the

capacitive sensing oscillator signal. Either of these

external clock sources can be synchronized to the

microcontroller system clock or they can run

asynchronously.

When used as a timer with a clock oscillator, an

external 32.768 kHz crystal can be used in conjunction

with the dedicated internal oscillator circuit.

TABLE 21-1: TIMER1 ENABLE

SELECTIONS

TMR1ON TMR1GE Timer1

Operation

00Off

01Off

10Always On

11Count Enabled

Note: In Counter mode, a falling edge must be

registered by the counter prior to the first

incrementing rising edge after any one or

more of the following conditions:

• Timer1 enabled after POR

• Write to TMR1H or TMR1L

• Timer1 is disabled

• Timer1 is disabled (TMR1ON = 0)

when T1CKI is high then Timer1 is

enabled (TMR1ON=1) when T1CKI is

low.

TABLE 21-2: CLOCK SOURCE SELECTIONS

TMR1CS1 TMR1CS0 T1OSCEN Clock Source

01xSystem Clock (FOSC)

00xInstruction Clock (FOSC/4)

11xCapacitive Sensing Oscillator

100External Clocking on T1CKI Pin

101Osc.Circuit On T1OSI/T1OSO Pins

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21.3 Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8

divisions of the clock input. The T1CKPS bits of the

T1CON register control the prescale counter. The

prescale counter is not directly readable or writable;

however, the prescaler counter is cleared upon a write to

TMR1H or TMR1L.

21.4 Timer1 Oscillator

A dedicated low-power 32.768 kHz oscillator circuit is

built-in between pins T1OSI (input) and T1OSO

(amplifier output). This internal circuit is to be used in

conjunction with an external 32.768 kHz crystal.

The oscillator circuit is enabled by setting the

T1OSCEN bit of the T1CON register. The oscillator will

continue to run during Sleep.

21.5 Timer1 Operation in

Asynchronous Counter Mode

If control bit T1SYNC of the T1CON register is set, the

external clock input is not synchronized. The timer

increments asynchronously to the internal phase

clocks. If the external clock source is selected, then

the timer will continue to run during Sleep and can

generate an interrupt on overflow, which will wake-up

the processor. However, special precautions in

software are needed to read/write the timer (see

Section 21.5.1 “Reading and Writing Timer1 in

Asynchronous Counter Mode”).

21.5.1 READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER

MODE

Reading TMR1H or TMR1L while the timer is running

from an external asynchronous clock will ensure a valid

read (taken care of in hardware). However, the user

should keep in mind that reading the 16-bit timer in two

8-bit values itself, poses certain problems, since the

timer may overflow between the reads.

For writes, it is recommended that the user simply stop

the timer and write the desired values. A write

contention may occur by writing to the timer registers,

while the register is incrementing. This may produce an

unpredictable value in the TMR1H:TMR1L register pair.

21.6 Timer1 Gate

Timer1 can be configured to count freely or the count

can be enabled and disabled using Timer1 gate

circuitry. This is also referred to as Timer1 Gate Enable.

Timer1 gate can also be driven by multiple selectable

sources.

21.6.1 TIMER1 GATE ENABLE

The Timer1 Gate Enable mode is enabled by setting

the TMR1GE bit of the T1GCON register. The polarity

of the Timer1 Gate Enable mode is configured using

the T1GPOL bit of the T1GCON register.

When Timer1 Gate Enable mode is enabled, Timer1

will increment on the rising edge of the Timer1 clock

source. When Timer1 Gate Enable mode is disabled,

no incrementing will occur and Timer1 will hold the

current count. See Figure 21-3 for timing details.

21.6.2 TIMER1 GATE SOURCE

SELECTION

The Timer1 gate source selections are shown in

Table 21-4. Source selection is controlled by the

T1GSS bits of the T1GCON register. The polarity for

each available source is also selectable. Polarity selec-

tion is controlled by the T1GPOL bit of the T1GCON

TABLE 21-4: TIMER1 GATE SOURCES

Note: The oscillator requires a start-up and

stabilization time before use. Thus,

T1OSCEN should be set and a suitable

delay observed prior to enabling Timer1.

Note: When switching from synchronous to

asynchronous operation, it is possible to

skip an increment. When switching from

asynchronous to synchronous operation,

it is possible to produce an additional

increment.

TABLE 21-3: TIMER1 GATE ENABLE

SELECTIONS

T1CLK T1GPOL T1G Timer1 Operation

00Counts

01Holds Count

10Holds Count

11Counts

T1GSS Timer1 Gate Source

00 Timer1 Gate Pin

01 Overflow of Timer0

(TMR0 increments from FFh to 00h)

10 Comparator 1 Output SYNCC1OUT

(optionally Timer1 synchronized output)

11 Comparator 2 Output SYNCC2OUT

(optionally Timer1 synchronized output)

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DS41419C-page 192 Preliminary  2010-2011 Microchip Technology Inc.

21.6.2.1 T1G Pin Gate Operation

The T1G pin is one source for Timer1 gate control. It

can be used to supply an external source to the Timer1

gate circuitry.

21.6.2.2 Timer0 Overflow Gate Operation

When Timer0 increments from FFh to 00h, a

low-to-high pulse will automatically be generated and

internally supplied to the Timer1 gate circuitry.

21.6.2.3 Comparator C1 Gate Operation

The output resulting from a Comparator 1 operation can

be selected as a source for Timer1 gate control. The

Comparator 1 output (SYNCC1OUT) can be

synchronized to the Timer1 clock or left asynchronous.

For more information see Section 19.4.1 “Comparator

Output Synchronization”.

21.6.2.4 Comparator C2 Gate Operation

The output resulting from a Comparator 2 operation

can be selected as a source for Timer1 gate control.

The Comparator 2 output (SYNCC2OUT) can be

synchronized to the Timer1 clock or left asynchronous.

For more information see Section 19.4.1 “Comparator

Output Synchronization”.

21.6.3 TIMER1 GATE TOGGLE MODE

When Timer1 Gate Toggle mode is enabled, it is possi-

ble to measure the full-cycle length of a Timer1 gate

signal, as opposed to the duration of a single level

pulse.

The Timer1 gate source is routed through a flip-flop that

changes state on every incrementing edge of the sig-

nal. See Figure 21-4 for timing details.

Timer1 Gate Toggle mode is enabled by setting the

T1GTM bit of the T1GCON register. When the T1GTM

bit is cleared, the flip-flop is cleared and held clear. This

is necessary in order to control which edge is

measured.

21.6.4 TIMER1 GATE SINGLE-PULSE

MODE

When Timer1 Gate Single-Pulse mode is enabled, it is

possible to capture a single pulse gate event. Timer1

Gate Single-Pulse mode is first enabled by setting the

T1GSPM bit in the T1GCON register. Next, the

T1GGO/DONE bit in the T1GCON register must be set.

The Timer1 will be fully enabled on the next

incrementing edge. On the next trailing edge of the

pulse, the T1GGO/DONE bit will automatically be

cleared. No other gate events will be allowed to

increment Timer1 until the T1GGO/DONE bit is once

again set in software. See Figure 21-5 for timing details.

If the Single Pulse Gate mode is disabled by clearing the

T1GSPM bit in the T1GCON register, the T1GGO/DONE

bit should also be cleared.

Enabling the Toggle mode and the Single-Pulse mode

simultaneously will permit both sections to work

together. This allows the cycle times on the Timer1

Gate source to be measured. See Figure 21-6 for

timing details.

21.6.5 TIMER1 GATE VALUE STATUS

When Timer1 Gate Value Status is utilized, it is possible

to read the most current level of the gate control value.

The value is stored in the T1GVAL bit in the T1GCON

Gate is not enabled (TMR1GE bit is cleared).

21.6.6 TIMER1 GATE EVENT INTERRUPT

When Timer1 Gate Event Interrupt is enabled, it is pos-

sible to generate an interrupt upon the completion of a

gate event. When the falling edge of T1GVAL occurs,

the TMR1GIF flag bit in the PIR1 register will be set. If

the TMR1GIE bit in the PIE1 register is set, then an

interrupt will be recognized.

The TMR1GIF flag bit operates even when the Timer1

gate is not enabled (TMR1GE bit is cleared).

Note: Enabling Toggle mode at the same time

as changing the gate polarity may result in

indeterminate operation.

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21.7 Timer1 Interrupt

The Timer1 register pair (TMR1H:TMR1L) increments

to FFFFh and rolls over to 0000h. When Timer1 rolls

over, the Timer1 interrupt flag bit of the PIR1 register is

set. To enable the interrupt on rollover, you must set

these bits:

• TMR1ON bit of the T1CON register

• TMR1IE bit of the PIE1 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

The interrupt is cleared by clearing the TMR1IF bit in

the Interrupt Service Routine.

21.8 Timer1 Operation During Sleep

Timer1 can only operate during Sleep when set up in

Asynchronous Counter mode. In this mode, an external

crystal or clock source can be used to increment the

counter. To set up the timer to wake the device:

• TMR1ON bit of the T1CON register must be set

• TMR1IE bit of the PIE1 register must be set

• PEIE bit of the INTCON register must be set

• T1SYNC bit of the T1CON register must be set

• TMR1CS bits of the T1CON register must be

configured

• T1OSCEN bit of the T1CON register must be

configured

The device will wake-up on an overflow and execute

the next instructions. If the GIE bit of the INTCON

Routine.

Timer1 oscillator will continue to operate in Sleep

regardless of the T1SYNC bit setting.

21.9 ECCP/CCP Capture/Compare Time

Base

The CCP modules use the TMR1H:TMR1L register

pair as the time base when operating in Capture or

Compare mode.

In Capture mode, the value in the TMR1H:TMR1L

In Compare mode, an event is triggered when the value

CCPR1H:CCPR1L register pair matches the value in

the TMR1H:TMR1L register pair. This event can be a

Special Event Trigger.

For more information, see Section 24.0

“Capture/Compare/PWM Modules”.

21.10 ECCP/CCP Special Event Trigger

When any of the CCP’s are configured to trigger a spe-

cial event, the trigger will clear the TMR1H:TMR1L reg-

ister pair. This special event does not cause a Timer1

interrupt. The CCP module may still be configured to

generate a CCP interrupt.

In this mode of operation, the CCPR1H:CCPR1L

Timer1 should be synchronized and FOSC/4 should be

selected as the clock source in order to utilize the Spe-

cial Event Trigger. Asynchronous operation of Timer1

can cause a Special Event Trigger to be missed.

In the event that a write to TMR1H or TMR1L coincides

with a Special Event Trigger from the CCP, the write will

take precedence.

For more information, see Section 16.2.5 “Special

Event Trigger”.

FIGURE 21-2: TIMER1 INCREMENTING EDGE

Note: The TMR1H:TMR1L register pair and the

TMR1IF bit should be cleared before

enabling interrupts.

T1CKI = 1

when TMR1

Enabled

T1CKI = 0

when TMR1

Enabled

Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.

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DS41419C-page 194 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 21-3: TIMER1 GATE ENABLE MODE

FIGURE 21-4: TIMER1 GATE TOGGLE MODE

TMR1GE

T1GPOL

T1G_IN

T1CKI

T1GVAL

Timer1 N N + 1 N + 2 N + 3 N + 4

TMR1GE

T1GPOL

T1GTM

T1G_IN

T1CKI

T1GVAL

Timer1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 195

PIC16(L)F1824/1828

FIGURE 21-5: TIMER1 GATE SINGLE-PULSE MODE

TMR1GE

T1GPOL

T1G_IN

T1CKI

T1GVAL

Timer1 N N + 1 N + 2

T1GSPM

T1GGO/

DONE

Set by software

Cleared by hardware on

falling edge of T1GVAL

Set by hardware on

falling edge of T1GVAL

Cleared by software

Cleared by

software

TMR1GIF

Counting enabled on

rising edge of T1G

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DS41419C-page 196 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 21-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE

TMR1GE

T1GPOL

T1G_IN

T1CKI

T1GVAL

Timer1 NN + 1

N + 2

T1GSPM

T1GGO/

DONE

Set by software

Cleared by hardware on

falling edge of T1GVAL

Set by hardware on

falling edge of T1GVAL

Cleared by software

Cleared by

software

TMR1GIF

T1GTM

Counting enabled on

rising edge of T1G

N + 4

N + 3

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PIC16(L)F1824/1828

21.11 Timer1 Control Registers

R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u U-0 R/W-0/u

TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC —TMR1ON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits

11 = Timer1 clock source is Capacitive Sensing Oscillator (CAPOSC)

10 = Timer1 clock source is pin or oscillator:

If T1OSCEN = 0:

External clock from T1CKI pin (on the rising edge)

If T1OSCEN = 1:

Crystal oscillator on T1OSI/T1OSO pins

01 = Timer1 clock source is system clock (FOSC)

00 = Timer1 clock source is instruction clock (FOSC/4)

bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale value

10 = 1:4 Prescale value

01 = 1:2 Prescale value

00 = 1:1 Prescale value

bit 3 T1OSCEN: LP Oscillator Enable Control bit

1 = Dedicated Timer1 oscillator circuit enabled

0 = Dedicated Timer1 oscillator circuit disabled

bit 2 T1SYNC: Timer1 Synchronization Control bit

1 = Do not synchronize synchronous clock input

0 = Synchronize asynchronous clock input with system clock (FOSC)

bit 1 Unimplemented: Read as ‘0’

bit 0 TMR1ON: Timer1 On bit

1 = Enables Timer1

0 = Stops Timer1 and clears Timer1 gate flip-flop

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DS41419C-page 198 Preliminary  2010-2011 Microchip Technology Inc.

R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x R/W-0/u R/W-0/u

TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

DONE

T1GVAL T1GSS<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware

bit 7 TMR1GE: Timer1 Gate Enable bit

If TMR1ON = 0:

This bit is ignored

If TMR1ON = 1:

1 = Timer1 counting is controlled by the Timer1 gate function

0 = Timer1 counts regardless of Timer1 gate function

bit 6 T1GPOL: Timer1 Gate Polarity bit

1 = Timer1 gate is active-high (Timer1 counts when gate is high)

0 = Timer1 gate is active-low (Timer1 counts when gate is low)

bit 5 T1GTM: Timer1 Gate Toggle Mode bit

1 = Timer1 Gate Toggle mode is enabled

0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared

Timer1 gate flip-flop toggles on every rising edge.

bit 4 T1GSPM: Timer1 Gate Single-Pulse Mode bit

1 = Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate

0 = Timer1 gate Single-Pulse mode is disabled

bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit

1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge

0 = Timer1 gate single-pulse acquisition has completed or has not been started

bit 2 T1GVAL: Timer1 Gate Current State bit

Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.

Unaffected by Timer1 Gate Enable (TMR1GE).

bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits

11 = Comparator 2 optionally synchronized output (SYNCC2OUT)

10 = Comparator 1 optionally synchronized output (SYNCC1OUT)

01 = Timer0 overflow output

00 = Timer1 gate pin

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TABLE 21-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

ANSELA — — —ANSA4 —ANSA2 ANSA1 ANSA0 127

CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 238

CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 238

INLVLA —— INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 128

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 94

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 97

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 193*

TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 193*

TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 126

T1CON TMR1CS1 TMR1CS0 T1CKPS<1:0> T1OSCEN T1SYNC —TMR1ON

197

T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

DONE

T1GVAL T1GSS1 T1GSS0 198

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module.

* Page provides register information.

Note 1: PIC16(L)F1828 only.

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NOTES:

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 201

PIC16(L)F1824/1828

22.0 TIMER2/4/6 MODULES

There are up to three identical Timer2-type modules

available. To maintain pre-existing naming conventions,

the Timers are called Timer2, Timer4 and Timer6 (also

Timer2/4/6).

The Timer2/4/6 modules incorporate the following

features:

• 8-bit Timer and Period registers (TMRx and PRx,

respectively)

• Readable and writable (both registers)

• Software programmable prescaler (1:1, 1:4, 1:16,

and 1:64)

• Software programmable postscaler (1:1 to 1:16)

• Interrupt on TMRx match with PRx, respectively

• Optional use as the shift clock for the MSSPx

modules (Timer2 only)

See Figure 22-1 for a block diagram of Timer2/4/6.

FIGURE 22-1: TIMER2/4/6 BLOCK DIAGRAM

Note: The ‘x’ variable used in this section is

used to designate Timer2, Timer4, or

Timer6. For example, TxCON references

T2CON, T4CON, or T6CON. PRx refer-

ences PR2, PR4, or PR6.

Comparator

TMRx Sets Flag

TMRx

Output

Reset

Postscaler

Prescaler

PRx

FOSC/4

1:1 to 1:16

1:1, 1:4, 1:16, 1:64

bit TMRxIF

TxOUTPS<3:0>

TxCKPS<1:0>

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22.1 Timer2/4/6 Operation

The clock input to the Timer2/4/6 modules is the

system instruction clock (FOSC/4).

TMRx increments from 00h on each clock edge.

A 4-bit counter/prescaler on the clock input allows direct

input, divide-by-4 and divide-by-16 prescale options.

These options are selected by the prescaler control bits,

TxCKPS<1:0> of the TxCON register. The value of

TMRx is compared to that of the Period register, PRx, on

each clock cycle. When the two values match, the

comparator generates a match signal as the timer

output. This signal also resets the value of TMRx to 00h

on the next cycle and drives the output

counter/postscaler (see Section 22.2 “Timer2/4/6

Interrupt”).

The TMRx and PRx registers are both directly readable

and writable. The TMRx register is cleared on any

device Reset, whereas the PRx register initializes to

FFh. Both the prescaler and postscaler counters are

cleared on the following events:

• a write to the TMRx register

• a write to the TxCON register

• Power-on Reset (POR)

• Brown-out Reset (BOR)

•MCLR

Reset

• Watchdog Timer (WDT) Reset

• Stack Overflow Reset

• Stack Underflow Reset

•RESET Instruction

22.2 Timer2/4/6 Interrupt

Timer2/4/6 can also generate an optional device

interrupt. The Timer2/4/6 output signal (TMRx-to-PRx

match) provides the input for the 4-bit

counter/postscaler. This counter generates the TMRx

match interrupt flag which is latched in TMRxIF of the

PIRx register. The interrupt is enabled by setting the

TMRx Match Interrupt Enable bit, TMRxIE of the PIEx

A range of 16 postscale options (from 1:1 through 1:16

inclusive) can be selected with the postscaler control

bits, TxOUTPS<3:0>, of the TxCON register.

22.3 Timer2/4/6 Output

The unscaled output of TMRx is available primarily to

the CCP modules, where it is used as a time base for

operations in PWM mode.

Timer2 can be optionally used as the shift clock source

for the MSSPx modules operating in SPI mode.

Additional information is provided in Section 25.1

“Master SSP (MSSP1) Module Overview”.

22.4 Timer2/4/6 Operation During Sleep

The Timer2/4/6 timers cannot be operated while the

processor is in Sleep mode. The contents of the TMRx

and PRx registers will remain unchanged while the

processor is in Sleep mode.

Note: TMRx is not cleared when TxCON is

written.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 203

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22.5 Timer2 Control Register

U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— TxOUTPS<3:0> TMRxON TxCKPS<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘0’

bit 6-3 TxOUTPS<3:0>: Timerx Output Postscaler Select bits

1111 = 1:16 Postscaler

1110 = 1:15 Postscaler

1101 = 1:14 Postscaler

1100 = 1:13 Postscaler

1011 = 1:12 Postscaler

1010 = 1:11 Postscaler

1001 = 1:10 Postscaler

1000 = 1:9 Postscaler

0111 = 1:8 Postscaler

0110 = 1:7 Postscaler

0101 = 1:6 Postscaler

0100 = 1:5 Postscaler

0011 = 1:4 Postscaler

0010 = 1:3 Postscaler

0001 = 1:2 Postscaler

0000 = 1:1 Postscaler

bit 2 TMRxON: Timerx On bit

1 =Timerx is on

0 =Timerx is off

bit 1-0 TxCKPS<1:0>: Timer2-type Clock Prescale Select bits

11 = Prescaler is 64

10 =Prescaler is 16

01 =Prescaler is 4

00 =Prescaler is 1

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DS41419C-page 204 Preliminary  2010-2011 Microchip Technology Inc.

TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2/4/6

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 94

PIE3 — — CCP4IE CCP3IE TMR6IE —TMR4IE—96

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 97

PIR3 — — CCP4IF CCP3IF TMR6IF —TMR4IF—99

PR2 Timer2 Module Period Register 201*

PR4 Timer4 Module Period Register 201*

PR6 Timer6 Module Period Register 201*

T2CON — TOUTPS<3:0> TMR2ON T2CKPS1 T2CKPS0 203

T4CON — T4OUTPS<3:0> TMR4ON T4CKPS1 T4CKPS0 203

T6CON — T6OUTPS<3:0> TMR6ON T6CKPS1 T6CKPS0 203

TMR2 Holding Register for the 8-bit TMR2 Register 201*

TMR4 Holding Register for the 8-bit TMR4 Register(1) 201*

TMR6 Holding Register for the 8-bit TMR6 Register(1) 201*

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module.

* Page provides register information.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 205

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23.0 DATA SIGNAL MODULATOR

The Data Signal Modulator (DSM) is a peripheral which

allows the user to mix a data stream, also known as a

modulator signal, with a carrier signal to produce a

modulated output.

Both the carrier and the modulator signals are supplied

to the DSM module either internally, from the output of

a peripheral, or externally through an input pin.

The modulated output signal is generated by perform-

ing a logical “AND” operation of both the carrier and

modulator signals and then provided to the MDOUT pin.

The carrier signal is comprised of two distinct and sep-

arate signals. A carrier high (CARH) signal and a car-

rier low (CARL) signal. During the time in which the

modulator (MOD) signal is in a logic high state, the

DSM mixes the carrier high signal with the modulator

signal. When the modulator signal is in a logic low

state, the DSM mixes the carrier low signal with the

modulator signal.

Using this method, the DSM can generate the following

types of key modulation schemes:

• Frequency-Shift Keying (FSK)

• Phase-Shift Keying (PSK)

• On-Off Keying (OOK)

Additionally, the following features are provided within

the DSM module:

• Carrier Synchronization

• Carrier Source Polarity Select

• Carrier Source Pin Disable

• Programmable Modulator Data

• Modulator Source Pin Disable

• Modulated Output Polarity Select

• Slew Rate Control

Figure 23-1 shows a Simplified Block Diagram of the

Data Signal Modulator peripheral.

FIGURE 23-1: SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR

MDBIT

MDMIN

CCP1

CCP2

CCP3

CCP4

Comparator C1

Comparator C2

Reserved

0000

0001

0010

0011

0100

0101

0110

0111

1000

0011

1001

1010

No Channel

Selected

VSS

MDCIN1

MDCIN2

CLKR

CCP1

CCP2

CCP3

CCP4

Reserved

0000

0001

0010

0011

0100

0101

0110

0111

1000

1111

No Channel

Selected

VSS

MDCIN1

MDCIN2

CLKR

CCP1

CCP2

CCP3

CCP4

Reserved

0000

0001

0010

0011

0100

0101

0110

0111

1000

1111

No Channel

Selected

MDCH<3:0>

MDMS<3:0>

MDCL<3:0>

1111

MSSP1 SDO1

MSSP2 SDO2

EUSART

SYNC

MDCHPOL

MDCLPOL

SYNC

MDCHSYNC

MDCLSYNC

MDOUT

MDOPOL

CARH

CARL

MDEN

Data Signal

Modulator

MOD

MDOE

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23.1 DSM Operation

The DSM module can be enabled by setting the MDEN

bit in the MDCON register. Clearing the MDEN bit in the

MDCON register, disables the DSM module by auto-

matically switching the carrier high and carrier low sig-

nals to the VSS signal source. The modulator signal

source is also switched to the MDBIT in the MDCON

inactive, but that it is also consuming the least amount

of current.

The values used to select the carrier high, carrier low,

and modulator sources held by the modulation source,

modulation high carrier, and modulation low carrier

control registers are not affected when the MDEN bit is

cleared and the DSM module is disabled. The values

inside these registers remain unchanged while the

DSM is inactive. The sources for the carrier high, car-

rier low and modulator signals will once again be

selected when the MDEN bit is set and the DSM mod-

ule is again enabled and active.

The modulated output signal can be disabled without

shutting down the DSM module. The DSM module will

remain active and continue to mix signals, but the out-

put value will not be sent to the MDOUT pin. During the

time that the output is disabled, the MDOUT pin will

remain low. The modulated output can be disabled by

clearing the MDOE bit in the MDCON register.

23.2 Modulator Signal Sources

The modulator signal can be supplied from the follow-

ing sources:

• CCP1 Signal

• CCP2 Signal

• CCP3 Signal

• CCP4 Signal

• MSSP1 SDO1 Signal (SPI mode only)

• MSSP2 SDO2 Signal (SPI mode only)

• Comparator C1 Signal

• Comparator C2 Signal

• EUSART TX Signal

• External Signal on MDMIN1 pin

• MDBIT bit in the MDCON register

The modulator signal is selected by configuring the

MDMS <3:0> bits in the MDSRC register.

23.3 Carrier Signal Sources

The carrier high signal and carrier low signal can be

supplied from the following sources:

• CCP1 signal

• CCP2 signal

• CCP3 signal

• CCP4 signal

• Reference clock module signal

• External signal on MDCIN1 pin

• External signal on MDCIN2 pin

•VSS

The carrier high signal is selected by configuring the

MDCH <3:0> bits in the MDCARH register. The carrier

low signal is selected by configuring the MDCL <3:0>

bits in the MDCARL register.

23.4 Carrier Synchronization

During the time when the DSM switches between car-

rier high and carrier low signal sources, the carrier data

in the modulated output signal can become truncated.

To prevent this, the carrier signal can be synchronized

to the modulator signal. When synchronization is

enabled, the carrier pulse that is being mixed at the

time of the transition is allowed to transition low before

the DSM switches over to the next carrier source.

Synchronization is enabled separately for the carrier

high and carrier low signal sources. Synchronization for

the carrier high signal can be enabled by setting the

MDCHSYNC bit in the MDCARH register. Synchroniza-

tion for the carrier low signal can be enabled by setting

the MDCLSYNC bit in the MDCARL register.

Figure 23-1 through Figure 23-5 show timing diagrams

of using various synchronization methods.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 207

PIC16(L)F1824/1828

FIGURE 23-2: ON OFF KEYING (OOK) SYNCHRONIZATION

EXAMPLE 23-1: NO SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 0)

FIGURE 23-3: CARRIER HIGH SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 0)

Carrier Low (CARL)

MDCHSYNC = 1

MDCLSYNC = 0

MDCHSYNC = 1

MDCLSYNC = 1

MDCHSYNC = 0

MDCLSYNC = 0

MDCHSYNC = 0

MDCLSYNC = 1

Carrier High (CARH)

Modulator (MOD)

MDCHSYNC = 0

MDCLSYNC = 0

Modulator (MOD)

Carrier High (CARH)

Carrier Low (CARL)

Active Carrier CARH CARL CARL

CARH

State

MDCHSYNC = 1

MDCLSYNC = 0

Modulator (MOD)

Carrier High (CARH)

Carrier Low (CARL)

Active Carrier

CARH CARL CARL

CARH

State

both both

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FIGURE 23-4: CARRIER LOW SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 1)

FIGURE 23-5: FULL SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 1)

MDCHSYNC = 0

MDCLSYNC = 1

Modulator (MOD)

Carrier High (CARH)

Carrier Low (CARL)

Active Carrier CARH CARL CARL

CARH

State

MDCHSYNC = 1

MDCLSYNC = 1

Modulator (MOD)

Carrier High (CARH)

Carrier Low (CARL)

Active Carrier CARH CARL CARL

CARH

State

Falling edges

used to sync

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 209

PIC16(L)F1824/1828

23.5 Carrier Source Polarity Select

The signal provided from any selected input source for

the carrier high and carrier low signals can be inverted.

Inverting the signal for the carrier high source is

enabled by setting the MDCHPOL bit of the MDCARH

enabled by setting the MDCLPOL bit of the MDCARL

23.6 Carrier Source Pin Disable

Some peripherals assert control over their correspond-

ing output pin when they are enabled. For example,

when the CCP1 module is enabled, the output of CCP1

is connected to the CCP1 pin.

This default connection to a pin can be disabled by set-

ting the MDCHODIS bit in the MDCARH register for the

carrier high source and the MDCLODIS bit in the

MDCARL register for the carrier low source.

23.7 Pragrammable Modulator Data

The MDBIT of the MDCON register can be selected as

the source for the modulator signal. This gives the user

the ability to program the value used for modulation.

23.8 Modulator Source Pin Disable

The modulator source default connection to a pin can

be disabled by setting the MDMSODIS bit in the

MDSRC register.

23.9 Modulated Output Polarity

The modulated output signal provided on the MDOUT

pin can also be inverted. Inverting the modulated out-

put signal is enabled by setting the MDOPOL bit of the

MDCON register.

23.10 Slew Rate Control

The slew rate limitation on the output port pin can be

disabled. The slew rate limitation can be removed by

clearing the MDSLR bit in the MDCON register.

23.11 Operation in Sleep mode

The DSM module is not affected by Sleep mode. The

DSM can still operate during Sleep, if the carrier and

modulator input sources are also still operable during

Sleep.

23.12 Effects of a Reset

Upon any device Reset, the data signal modulator

module is disabled. The user’s firmware is responsible

for initializing the module before enabling the output.

The registers are reset to their default values.

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R/W-0/0 R/W-0/0 R/W-1/1 R/W-0/0 R-0/0 U-0 U-0 R/W-0/0

MDEN MDOE MDSLR MDOPOL MDOUT ——MDBIT

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 MDEN: Modulator Module Enable bit

1 = Modulator module is enabled and mixing input signals

0 = Modulator module is disabled and has no output

bit 6 MDOE: Modulator Module Pin Output Enable bit

1 = Modulator pin output enabled

0 = Modulator pin output disabled

bit 5 MDSLR: MDOUT Pin Slew Rate Limiting bit

1 = MDOUT pin slew rate limiting enabled

0 = MDOUT pin slew rate limiting disabled

bit 4 MDOPOL: Modulator Output Polarity Select bit

1 = Modulator output signal is inverted

0 = Modulator output signal is not inverted

bit 3 MDOUT: Modulator Output bit

Displays the current output value of the modulator module.(1)

bit 2-1 Unimplemented: Read as ‘0’

bit 0 MDBIT: Allows software to manually set modulation source input to module(2)

Note 1: The modulated output frequency can be greater and asynchronous from the clock that updates this

2: MDBIT must be selected as the modulation source in the MDSRC register for this operation.

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PIC16(L)F1824/1828

R/W-x/u U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u

MDMSODIS — — —MDMS<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 MDMSODIS: Modulation Source Output Disable

1 = Output signal driving the peripheral output pin (selected by MDMS<3:0>) is disabled

0 = Output signal driving the peripheral output pin (selected by MDMS<3:0>) is enabled

bit 6-4 Unimplemented: Read as ‘0’

bit 3-0 MDMS<3:0> Modulation Source Selection bits

1111 = Reserved. No channel connected.

1110 = Reserved. No channel connected.

1101 = Reserved. No channel connected.

1100 = Reserved. No channel connected.

1011 = Reserved. No channel connected.

1010 = EUSART TX output

1001 = MSSP2 SDOx output

1000 = MSSP1 SDOx output

0111 = Comparator2 output

0110 = Comparator1 output

0101 = CCP4 output (PWM Output mode only)

0100 = CCP3 output (PWM Output mode only)

0011 = CCP2 output (PWM Output mode only)

0010 = CCP1 output (PWM Output mode only)

0001 = MDMIN port pin

0000 = MDBIT bit of MDCON register is modulation source

Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.

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DS41419C-page 212 Preliminary  2010-2011 Microchip Technology Inc.

R/W-x/u R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u

MDCHODIS MDCHPOL MDCHSYNC — MDCH<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 MDCHODIS: Modulator High Carrier Output Disable

1 = Output signal driving the peripheral output pin (selected by MDCH<3:0>) is disabled

0 = Output signal driving the peripheral output pin (selected by MDCH<3:0>) is enabled

bit 6 MDCHPOL: Modulator High Carrier Polarity Select bit

1 = Selected high carrier signal is inverted

0 = Selected high carrier signal is not inverted

bit 5 MDCHSYNC: Modulator High Carrier Synchronization Enable bit

1 = Modulator waits for a falling edge on the high time carrier signal before allowing a switch to the

low time carrier

0 = Modulator Output is not synchronized to the high time carrier signal(1)

bit 4 Unimplemented: Read as ‘0’

bit 3-0 MDCH<3:0> Modulator Data High Carrier Selection bits (1)

1111 = Reserved. No channel connected.

•

1000 = Reserved. No channel connected.

0111 = CCP4 output (PWM Output mode only)

0110 = CCP3 output (PWM Output mode only)

0101 = CCP2 output (PWM Output mode only)

0100 = CCP1 output (PWM Output mode only)

0011 = Reference clock module signal

0010 = MDCIN2 port pin

0001 = MDCIN1 port pin

0000 =V

Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 213

PIC16(L)F1824/1828

TABLE 23-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA SIGNAL MODULATOR MODE

R/W-x/u R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u

MDCLODIS MDCLPOL MDCLSYNC — MDCL<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 MDCLODIS: Modulator Low Carrier Output Disable bit

1 = Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register)

is disabled

0 = Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register)

is enabled

bit 6 MDCLPOL: Modulator Low Carrier Polarity Select bit

1 = Selected low carrier signal is inverted

0 = Selected low carrier signal is not inverted

bit 5 MDCLSYNC: Modulator Low Carrier Synchronization Enable bit

1 = Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high

time carrier

0 = Modulator output is not synchronized to the low time carrier signal(1)

bit 4 Unimplemented: Read as ‘0’

bit 3-0 MDCL<3:0> Modulator Data High Carrier Selection bits (1)

1111 = Reserved. No channel connected.

•

1000 = Reserved. No channel connected.

0111 = CCP4 output (PWM Output mode only)

0110 = CCP3 output (PWM Output mode only)

0101 = CCP2 output (PWM Output mode only)

0100 = CCP1 output (PWM Output mode only)

0011 = Reference clock module signal

0010 = MDCIN2 port pin

0001 = MDCIN1 port pin

0000 =V

Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

MDCARH MDCHODIS MDCHPOL MDCHSYNC —

MDCH<3:0>

212

MDCARL MDCLODIS MDCLPOL MDCLSYNC —

MDCL<3:0>

213

MDCON MDEN MDOE MDSLR MDOPOL MDOUT — —

MDBIT

210

MDSRC MDMSODIS — — —

MDMS<3:0>

211

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in the Data Signal Modulator mode.

PIC16(L)F1824/1828

DS41419C-page 214 Preliminary  2010-2011 Microchip Technology Inc.

NOTES:

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 215

PIC16(L)F1824/1828

24.0 CAPTURE/COMPARE/PWM

MODULES

The Capture/Compare/PWM module is a peripheral

which allows the user to time and control different

events, and to generate Pulse-Width Modulation

(PWM) signals. In Capture mode, the peripheral allows

the timing of the duration of an event. The Compare

mode allows the user to trigger an external event when

a predetermined amount of time has expired. The

PWM mode can generate Pulse-Width Modulated

signals of varying frequency and duty cycle.

This family of devices contains two Enhanced Capture/

Compare/PWM modules (ECCP1 and ECCP2) and two

standard Capture/Compare/PWM modules (CCP3 and

CCP4).

The capture and compare functions are identical for all

four CCP modules (ECCP1, ECCP2, CCP3, and

CCP4). The only differences between CCP modules

are in the Pulse-Width Modulation (PWM) function. The

standard PWM function is identical in modules, CCP3

and CCP4. In CCP modules ECCP1 and ECCP2, the

Enhanced PWM function has slight variations from one

another. Full-Bridge ECCP modules have four

available I/O pins while Half-Bridge ECCP modules

only have two available I/O pins. See Tab le 24-1 for

more information.

Note 1: In devices with more than one CCP

module, it is very important to pay close

attention to the register names used. A

number placed after the module acronym

is used to distinguish between separate

modules. For example, the CCP1CON

and CCP2CON control the same

operational aspects of two completely

different CCP modules.

2: Throughout this section, generic

references to a CCP module in any of its

operating modes may be interpreted as

being equally applicable to ECCP1,

ECCP2, CCP3 and CCP4. Register

names, module signals, I/O pins, and bit

names may use the generic designator ‘x’

to indicate the use of a numeral to

distinguish a particular module, when

required.

TABLE 24-1: PWM RESOURCES

Device Name ECCP1 ECCP2 CCP3 CCP4

PIC16(L)F1824/1828 Enhanced PWM

Full-Bridge

Enhanced PWM

Half-Bridge Standard PWM Standard PWM

PIC16(L)F1824/1828

DS41419C-page 216 Preliminary  2010-2011 Microchip Technology Inc.

24.1 Capture Mode

The Capture mode function described in this section is

available and identical for CCP modules ECCP1,

ECCP2, CCP3 and CCP4.

Capture mode makes use of the 16-bit Timer1

resource. When an event occurs on the CCPx pin, the

16-bit CCPRxH:CCPRxL register pair captures and

stores the 16-bit value of the TMR1H:TMR1L register

pair, respectively. An event is defined as one of the

following and is configured by the CCPxM<3:0> bits of

the CCPxCON register:

• Every falling edge

• Every rising edge

• Every 4th rising edge

• Every 16th rising edge

When a capture is made, the Interrupt Request Flag bit

CCPxIF of the PIRx register is set. The interrupt flag

must be cleared in software. If another capture occurs

before the value in the CCPRxH, CCPRxL register pair

is read, the old captured value is overwritten by the new

captured value.

Figure 24-1 shows a simplified diagram of the Capture

operation.

24.1.1 CCP PIN CONFIGURATION

In Capture mode, the CCPx pin should be configured

as an input by setting the associated TRIS control bit.

Also, the CCPx pin function can be moved to

alternative pins using the APFCON1 register. Refer to

Section 12.1 “Alternate Pin Function” for more

details.

FIGURE 24-1: CAPTURE MODE

OPERATION BLOCK

DIAGRAM

24.1.2 TIMER1 MODE RESOURCE

Timer1 must be running in Timer mode or Synchronized

Counter mode for the CCP module to use the capture

feature. In Asynchronous Counter mode, the capture

operation may not work.

See Section 21.0 “Timer1 Module with Gate Control”

for more information on configuring Timer1.

24.1.3 SOFTWARE INTERRUPT MODE

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep the

CCPxIE interrupt enable bit of the PIEx register clear to

avoid false interrupts. Additionally, the user should

clear the CCPxIF interrupt flag bit of the PIRx register

following any change in Operating mode.

24.1.4 CCP PRESCALER

There are four prescaler settings specified by the

CCPxM<3:0> bits of the CCPxCON register. Whenever

the CCP module is turned off, or the CCP module is not

in Capture mode, the prescaler counter is cleared. Any

Reset will clear the prescaler counter.

Switching from one capture prescaler to another does not

clear the prescaler and may generate a false interrupt. To

avoid this unexpected operation, turn the module off by

clearing the CCPxCON register before changing the

prescaler. Example 24-1 demonstrates the code to

perform this function.

EXAMPLE 24-1: CHANGING BETWEEN

CAPTURE PRESCALERS

Note: If the CCPx pin is configured as an output,

a write to the port can cause a capture

condition.

CCPRxH CCPRxL

TMR1H TMR1L

Set Flag bit CCPxIF

(PIRx register)

Capture

Enable

CCPxM<3:0>

Prescaler

 1, 4, 16

and

Edge Detect

CCPx

System Clock (FOSC)

Note: Clocking Timer1 from the system clock

(FOSC) should not be used in Capture

mode. In order for Capture mode to

recognize the trigger event on the CCPx

pin, Timer1 must be clocked from the

instruction clock (FOSC/4) or from an

external clock source.

BANKSEL CCPxCON ;Set Bank bits to point

;to CCPxCON

CLRF CCPxCON ;Turn CCP module off

MOVLW NEW_CAPT_PS ;Load the W reg with

;the new prescaler

;move value and CCP ON

MOVWF CCPxCON ;Load CCPxCON with this

;value

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 217

PIC16(L)F1824/1828

24.1.5 CAPTURE DURING SLEEP

Capture mode depends upon the Timer1 module for

proper operation. There are two options for driving the

Timer1 module in Capture mode. It can be driven by the

instruction clock (FOSC/4), or by an external clock source.

When Timer1 is clocked by FOSC/4, Timer1 will not

increment during Sleep. When the device wakes from

Sleep, Timer1 will continue from its previous state.

Capture mode will operate during Sleep when Timer1

is clocked by an external clock source.

24.1.6 ALTERNATE PIN LOCATIONS

This module incorporates I/O pins that can be moved to

other locations with the use of the alternate pin function

registers, APFCON0 and APFCON1. To determine

which pins can be moved and what their default loca-

tions are upon a Reset, see Section 12.1 “Alternate

Pin Function” for more information.

TABLE 24-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

APFCON1 ————P1DSEL P1CSEL P2BSEL CCP2SEL 123

CCPxCON PxM1(1) PxM0(1) DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 238

CCPRxL Capture/Compare/PWM Register x Low Byte (LSB) 216*

CCPRxH Capture/Compare/PWM Register x High Byte (MSB) 216*

CMxCON0 CxON CxOUT CxOE CxPOL — CxSP CxHYS CxSYNC 181

CMxCON1 CxINTP CxINTN CxPCH1 CxPCH0 —— CxNCH1 CxNCH0 182

INLVLA ——INLVLA5INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 128

INLVLC INLVLC7(2) INLVLC6(2) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 139

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 94

PIE2 OSFIE C2IE C1IE EEIE BCL1IE —— CCP2IE 95

PIE3 ——CCP4IE CCP3IE TMR6IE —TMR4IE—96

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 97

PIR2 OSFIF C2IF C1IF EEIF BCL1IF —— CCP2IF 98

PIR3 ——CCP4IF CCP3IF TMR6IF —TMR4IF—99

T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC —TMR1ON

197

T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS1 T1GSS0 198

TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 193*

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 193*

TRISA —— TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 126

TRISC TRISC7(2) TRISC6(2) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 137

Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Capture.

* Page provides register information.

Note 1: Applies to ECCP modules only.

2: PIC16(L)F1828 only.

PIC16(L)F1824/1828

DS41419C-page 218 Preliminary  2010-2011 Microchip Technology Inc.

24.2 Compare Mode

The Compare mode function described in this section

is available and identical for CCP modules ECCP1,

ECCP2, CCP3 and CCP4.

Compare mode makes use of the 16-bit Timer1

resource. The 16-bit value of the CCPRxH:CCPRxL

value of the TMR1H:TMR1L register pair. When a

match occurs, one of the following events can occur:

• Toggle the CCPx output

• Set the CCPx output

• Clear the CCPx output

• Generate a Special Event Trigger

• Generate a Software Interrupt

The action on the pin is based on the value of the

CCPxM<3:0> control bits of the CCPxCON register. At

the same time, the interrupt flag CCPxIF bit is set.

All Compare modes can generate an interrupt.

Figure 24-2 shows a simplified diagram of the

Compare operation.

FIGURE 24-2: COMPARE MODE

OPERATION BLOCK

DIAGRAM

24.2.1 CCP PIN CONFIGURATION

The user must configure the CCPx pin as an output by

clearing the associated TRIS bit.

Also, the CCPx pin function can be moved to

alternative pins using the APFCON1 register. Refer to

Section 12.1 “Alternate Pin Function” for more

details.

24.2.2 TIMER1 MODE RESOURCE

In Compare mode, Timer1 must be running in either

Timer mode or Synchronized Counter mode. The

compare operation may not work in Asynchronous

Counter mode.

See Section 21.0 “Timer1 Module with Gate Control”

for more information on configuring Timer1.

24.2.3 SOFTWARE INTERRUPT MODE

When Generate Software Interrupt mode is chosen

(CCPxM<3:0> = 1010), the CCPx module does not

assert control of the CCPx pin (see the CCPxCON

24.2.4 SPECIAL EVENT TRIGGER

When Special Event Trigger mode is chosen

(CCPxM<3:0> = 1011), the CCPx module does the

following:

• Resets Timer1

• Starts an ADC conversion if ADC is enabled

The CCPx module does not assert control of the CCPx

pin in this mode.

The Special Event Trigger output of the CCP occurs

immediately upon a match between the TMR1H,

TMR1L register pair and the CCPRxH, CCPRxL regis-

ter pair. The TMR1H, TMR1L register pair is not reset

until the next rising edge of the Timer1 clock. The Spe-

cial Event Trigger output starts an A/D conversion (if

the A/D module is enabled). This allows the CCPRxH,

CCPRxL register pair to effectively provide a 16-bit

programmable period register for Timer1.

Refer to Section 16.2.5 “Special Event Trigger” for

more information.

Note: Clearing the CCPxCON register will force

the CCPx compare output latch to the

default low level. This is not the PORT I/O

data latch.

CCPRxH CCPRxL

TMR1H TMR1L

Comparator

Output

Logic

Special Event Trigger

Set CCPxIF Interrupt Flag

(PIRx)

Match

TRIS

CCPxM<3:0>

Mode Select

Output Enable

CCPx

Note: Clocking Timer1 from the system clock

(FOSC) should not be used in Compare

mode. In order for Compare mode to

recognize the trigger event on the CCPx

pin, TImer1 must be clocked from the

instruction clock (FOSC/4) or from an

external clock source.

TABLE 24-3: SPECIAL EVENT TRIGGER

Device CCPx/ECCPx

PIC16(L)F1824/1828 CCP4

Note 1: The Special Event Trigger from the CCP

module does not set interrupt flag bit

TMR1IF of the PIR1 register.

2: Removing the match condition by

changing the contents of the CCPRxH

and CCPRxL register pair, between the

clock edge that generates the Special

Event Trigger and the clock edge that

generates the Timer1 Reset, will

preclude the Reset from occurring.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 219

PIC16(L)F1824/1828

24.2.5 COMPARE DURING SLEEP

The Compare mode is dependent upon the system

clock (FOSC) for proper operation. Since FOSC is shut

down during Sleep mode, the Compare mode will not

function properly during Sleep.

24.2.6 ALTERNATE PIN LOCATIONS

This module incorporates I/O pins that can be moved to

other locations with the use of the alternate pin function

registers, APFCON0 and APFCON1. To determine

which pins can be moved and what their default loca-

tions are upon a Reset, see Section 12.1 “Alternate

Pin Function” for more information.

TABLE 24-4: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

APFCON1 ————P1DSEL P1CSEL P2BSEL CCP2SEL 123

CCPxCON PxM<1:0>(1) DCxB<1:0> CCPxM<3:0> 238

CCPRxL Capture/Compare/PWM Register x Low Byte (LSB) 216*

CCPRxH Capture/Compare/PWM Register x High Byte (MSB) 216*

INLVLA ——INLVLA5INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 128

INLVLC INLVLC7(2) INLVLC6(2) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 139

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 94

PIE2 OSFIE C2IE C1IE EEIE BCL1IE —— CCP2IE 95

PIE3 ——CCP4IE CCP3IE TMR6IE —TMR4IE—96

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 97

PIR2 OSFIF C2IF C1IF EEIF BCL1IF —— CCP2IF 98

PIR3 ——CCP4IF CCP3IF TMR6IF —TMR4IF—99

T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC —TMR1ON

197

T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 198

TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 193*

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 193*

TRISA —— TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 126

TRISC TRISC7(2) TRISC6(2) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 137

Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode.

* Page provides register information.

Note 1: Applies to ECCP modules only.

2: PIC16(L)F1828 only.

PIC16(L)F1824/1828

DS41419C-page 220 Preliminary  2010-2011 Microchip Technology Inc.

24.3 PWM Overview

Pulse-Width Modulation (PWM) is a scheme that

provides power to a load by switching quickly between

fully on and fully off states. The PWM signal resembles

a square wave where the high portion of the signal is

considered the on state and the low portion of the signal

is considered the off state. The high portion, also known

as the pulse width, can vary in time and is defined in

steps. A larger number of steps applied, which

lengthens the pulse width, also supplies more power to

the load. Lowering the number of steps applied, which

shortens the pulse width, supplies less power. The

PWM period is defined as the duration of one complete

cycle or the total amount of on and off time combined.

PWM resolution defines the maximum number of steps

that can be present in a single PWM period. A higher

resolution allows for more precise control of the pulse

width time and in turn the power that is applied to the

load.

The term duty cycle describes the proportion of the on

time to the off time and is expressed in percentages,

where 0% is fully off and 100% is fully on. A lower duty

cycle corresponds to less power applied and a higher

duty cycle corresponds to more power applied.

Figure 24-3 shows a typical waveform of the PWM

signal.

24.3.1 STANDARD PWM OPERATION

The standard PWM function described in this section is

available and identical for CCP modules ECCP1,

ECCP2, CCP3 and CCP4.

The standard PWM mode generates a Pulse-Width

Modulation (PWM) signal on the CCPx pin with up to 10

bits of resolution. The period, duty cycle, and resolution

are controlled by the following registers:

•PRx registers

•TxCON registers

• CCPRxL registers

• CCPxCON registers

Figure 24-4 shows a simplified block diagram of PWM

operation.

FIGURE 24-3: CCP PWM OUTPUT SIGNAL

FIGURE 24-4: SIMPLIFIED PWM BLOCK

DIAGRAM

Note 1: The corresponding TRIS bit must be

cleared to enable the PWM output on the

CCPx pin.

2: Clearing the CCPxCON register will

relinquish control of the CCPx pin.

Period

Pulse Width

TMRx = 0

TMRx = CCPRxH:CCPxCON<5:4>

TMRx = PRx

CCPRxL

CCPRxH(2) (Slave)

Comparator

TMRx

PRx

(1)

Duty Cycle Registers CCPxCON<5:4>

Clear Timer,

toggle CCPx pin and

latch duty cycle

Note 1: The 8-bit timer TMRx register is concatenated

with the 2-bit internal system clock (FOSC), or

2 bits of the prescaler, to create the 10-bit time

base.

2: In PWM mode, CCPRxH is a read-only register.

TRIS

CCPx

Comparator

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 221

PIC16(L)F1824/1828

24.3.2 SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for standard PWM operation:

1. Disable the CCPx pin output driver by setting the

associated TRIS bit.

2. Load the PRx register with the PWM period

value.

3. Configure the CCP module for the PWM mode

by loading the CCPxCON register with the

appropriate values.

4. Load the CCPRxL register and the DCxBx bits

of the CCPxCON register, with the PWM duty

cycle value.

5. Configure and start Timer2/4/6:

• Select the Timer2/4/6 resource to be used

for PWM generation by setting the

CxTSEL<1:0> bits in the CCPTMRSx

• Clear the TMRxIF interrupt flag bit of the

PIRx register. See Note below.

• Configure the TxCKPS bits of the TxCON

• Enable the Timer by setting the TMRxON

bit of the TxCON register.

6. Enable PWM output pin:

• Wait until the Timer overflows and the

TMRxIF bit of the PIRx register is set. See

Note below.

• Enable the CCPx pin output driver by clear-

ing the associated TRIS bit.

24.3.3 TIMER2/4/6 TIMER RESOURCE

The PWM standard mode makes use of one of the 8-bit

Timer2/4/6 timer resources to specify the PWM period.

Configuring the CxTSEL<1:0> bits in the CCPTMRSx

24.3.4 PWM PERIOD

The PWM period is specified by the PRx register of

Timer2/4/6. The PWM period can be calculated using

the formula of Equation 24-1.

EQUATION 24-1: PWM PERIOD

When TMRx is equal to PRx, the following three events

occur on the next increment cycle:

• TMRx is cleared

• The CCPx pin is set. (Exception: If the PWM duty

cycle = 0%, the pin will not be set.)

• The PWM duty cycle is latched from CCPRxL into

CCPRxH

24.3.5 PWM DUTY CYCLE

The PWM duty cycle is specified by writing a 10-bit

value to multiple registers: CCPRxL register and

DCxB<1:0> bits of the CCPxCON register. The

CCPRxL contains the eight MSbs and the DCxB<1:0>

bits of the CCPxCON register contain the two LSbs.

CCPRxL and DCxB<1:0> bits of the CCPxCON

value is not latched into CCPRxH until after the period

completes (i.e., a match between PRx and TMRx

registers occurs). While using the PWM, the CCPRxH

Equation 24-2 is used to calculate the PWM pulse

width.

Equation 24-3 is used to calculate the PWM duty cycle

ratio.

EQUATION 24-2: PULSE WIDTH

EQUATION 24-3: DUTY CYCLE RATIO

The CCPRxH register and a 2-bit internal latch are

used to double buffer the PWM duty cycle. This double

buffering is essential for glitchless PWM operation.

The 8-bit timer TMRx register is concatenated with either

the 2-bit internal system clock (FOSC), or 2 bits of the

prescaler, to create the 10-bit time base. The system

clock is used if the Timer2/4/6 prescaler is set to 1:1.

When the 10-bit time base matches the CCPRxH and

2-bit latch, then the CCPx pin is cleared (see

Figure 24-4).

Note: In order to send a complete duty cycle and

period on the first PWM output, the above

steps must be included in the setup

sequence. If it is not critical to start with a

complete PWM signal on the first output,

then step 6 may be ignored.

PWM Period PRx1+4TOSC =

(TMRx Prescale Value)

Note 1: TOSC = 1/FOSC

Note: The Timer postscaler (see Section 22.1

“Timer2/4/6 Operation”) is not used in the

determination of the PWM frequency.

Pulse Width CCPRxL:CCPxCON<5:4>



TOSC



(TMRx Prescale Value)

Duty Cycle Ratio CCPRxL:CCPxCON<5:4>

4 PRx 1+

-----------------------------------------------------------------------=

PIC16(L)F1824/1828

DS41419C-page 222 Preliminary  2010-2011 Microchip Technology Inc.

24.3.6 PWM RESOLUTION

The resolution determines the number of available duty

cycles for a given period. For example, a 10-bit resolution

will result in 1024 discrete duty cycles, whereas an 8-bit

resolution will result in 256 discrete duty cycles.

The maximum PWM resolution is 10 bits when PRx is

255. The resolution is a function of the PRx register

value as shown by Equation 24-4.

EQUATION 24-4: PWM RESOLUTION

TABLE 24-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 32 MHz)

TABLE 24-6: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)

TABLE 24-7: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)

Note: If the pulse width value is greater than the

period the assigned PWM pin(s) will

remain unchanged.

Resolution 4PRx 1+log

2log

------------------------------------------ bits=

PWM Frequency 1.95 kHz 7.81 kHz 31.25 kHz 125 kHz 250 kHz 333.3 kHz

Timer Prescale (1, 4, 16) 16 4 1 1 1 1

PRx Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17

Maximum Resolution (bits) 10 10 10 8 7 6.6

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz

Timer Prescale (1, 4, 16) 16 4 1 1 1 1

PRx Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17

Maximum Resolution (bits) 10 10 10 8 7 6.6

PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz

Timer Prescale (1, 4, 16) 16 4 1 1 1 1

PRx Value 0x65 0x65 0x65 0x19 0x0C 0x09

Maximum Resolution (bits) 8 8 8 6 5 5

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PIC16(L)F1824/1828

24.3.7 OPERATION IN SLEEP MODE

In Sleep mode, the TMRx register will not increment

and the state of the module will not change. If the CCPx

pin is driving a value, it will continue to drive that value.

When the device wakes up, TMRx will continue from its

previous state.

24.3.8 CHANGES IN SYSTEM CLOCK

FREQUENCY

The PWM frequency is derived from the system clock

frequency. Any changes in the system clock frequency

will result in changes to the PWM frequency. See

Section 5.0 “Oscillator Module (With Fail-Safe

Clock Monitor)” for additional details.

24.3.9 EFFECTS OF RESET

Any Reset will force all ports to Input mode and the

CCP registers to their Reset states.

24.3.10 ALTERNATE PIN LOCATIONS

This module incorporates I/O pins that can be moved to

other locations with the use of the alternate pin function

registers, APFCON0 and APFCON1. To determine

which pins can be moved and what their default loca-

tions are upon a Reset, see Section 12.1 “Alternate

Pin Function” for more information.

TABLE 24-8: SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

APFCON1 ————P1DSEL P1CSEL P2BSEL CCP2SEL 123

CCPxCON PxM<1:0>(1) DCxB<1:0> CCPxM<3:0> 238

CCPTMRS0 C4TSEL<1:0> C3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 216*

INLVLA ——INLVLA5INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 128

INLVLC INLVLC7(2) INLVLC6(2) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 139

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 94

PIE2 OSFIE C2IE C1IE EEIE BCLIE ——CCP2IE

PIE3 —— CCP4IE CCP3IE TMR6IE —TMR4IE —96

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 97

PIR2 OSFIF C2IF C1IF EEIF BCLIF ——CCP2IF

PIR3 —— CCP4IF CCP3IF TMR6IF —TMR4IF —99

PRx Timer2/4/6 Period Register 201*

TxCON — TxOUTPS<3:0> TMRxON TxCKPS<:0>1 203*

TMRx Timer2/4/6 Module Register 201*

TRISA —— TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 126

TRISC TRISC7(2) TRISC6(2) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 137

Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.

* Page provides register information.

Note 1: Applies to ECCP modules only.

2: PIC16(L)F1828 only.

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24.4 PWM (Enhanced Mode)

The enhanced PWM function described in this section is

available for CCP modules ECCP1, ECCP2 and

ECCP3, with any differences between modules noted.

The enhanced PWM mode generates a Pulse-Width

Modulation (PWM) signal on up to four different output

pins with up to 10 bits of resolution. The period, duty

cycle, and resolution are controlled by the following

registers:

•PRx registers

•TxCON registers

• CCPRxL registers

• CCPxCON registers

The ECCP modules have the following additional PWM

registers which control Auto-shutdown, Auto-restart,

Dead-band Delay and PWM Steering modes:

• CCPxAS registers

• PSTRxCON registers

• PWMxCON registers

The enhanced PWM module can generate the following

five PWM Output modes:

• Single PWM

• Half-Bridge PWM

• Full-Bridge PWM, Forward Mode

• Full-Bridge PWM, Reverse Mode

• Single PWM with PWM Steering Mode

To select an Enhanced PWM Output mode, the PxM bits

of the CCPxCON register must be configured

appropriately.

The PWM outputs are multiplexed with I/O pins and are

designated PxA, PxB, PxC and PxD. The polarity of the

PWM pins is configurable and is selected by setting the

CCPxM bits in the CCPxCON register appropriately.

Figure 24-5 shows an example of a simplified block

diagram of the Enhanced PWM module.

Table 24-9 shows the pin assignments for various

Enhanced PWM modes.

FIGURE 24-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE

Note 1: The corresponding TRIS bit must be

cleared to enable the PWM output on the

CCPx pin.

2: Clearing the CCPxCON register will

relinquish control of the CCPx pin.

3: Any pin not used in the enhanced PWM

mode is available for alternate pin

functions, if applicable.

4: To prevent the generation of an

incomplete waveform when the PWM is

first enabled, the ECCP module waits

until the start of a new PWM period

before generating a PWM signal.

CCPRxL

CCPRxH (Slave)

Comparator

TMRx

Comparator

PRx

(1)

Duty Cycle Registers DCxB<1:0>

Clear Timer,

toggle PWM pin and

latch duty cycle

Note 1: The 8-bit timer TMRx register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time

base.

TRISx

CCPx/PxA

TRISx

PxB

TRISx

PxC

TRISx

PxD

Output

Controller

PxM<1:0>

CCPxM<3:0>

PWMxCON

CCPx/PxA

PxB

PxC

PxD

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TABLE 24-9: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES

FIGURE 24-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH

STATE)

ECCP Mode PxM<1:0> CCPx/PxA PxB PxC PxD

Single 00 Yes(1) Yes(1) Yes(1) Yes(1)

Half-Bridge 10 Yes Yes No No

Full-Bridge, Forward 01 Yes Yes Yes Yes

Full-Bridge, Reverse 11 Yes Yes Yes Yes

Note 1: PWM Steering enables outputs in Single mode.

Period

Signal PRX+1

PxM<1:0>

PxA Modulated

PxB Modulated

PxA Active

PxB Inactive

PxC Inactive

PxD Modulated

PxA Inactive

PxB Modulated

PxC Active

PxD Inactive

Pulse

Width

(Single Output)

(Half-Bridge)

(Full-Bridge,

Forward)

(Full-Bridge,

Reverse)

Delay Delay

Relationships:

• Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)

• Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)

• Delay = 4 * TOSC * (PWMxCON<6:0>)

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FIGURE 24-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)

Period

Signal PRx+1

PxM<1:0>

PxA Modulated

PxB Modulated

PxA Active

PxB Inactive

PxC Inactive

PxD Modulated

PxA Inactive

PxB Modulated

PxC Active

PxD Inactive

Pulse

Width

(Single Output)

(Half-Bridge)

(Full-Bridge,

Forward)

(Full-Bridge,

Reverse)

Delay Delay

Relationships:

• Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)

• Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)

• Delay = 4 * TOSC * (PWMxCON<6:0>)

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24.4.1 HALF-BRIDGE MODE

In Half-Bridge mode, two pins are used as outputs to

drive push-pull loads. The PWM output signal is output

on the CCPx/PxA pin, while the complementary PWM

output signal is output on the PxB pin (see Figure 24-

9). This mode can be used for Half-Bridge applications,

as shown in Figure 24-9, or for Full-Bridge applications,

where four power switches are being modulated with

two PWM signals.

In Half-Bridge mode, the programmable dead-band delay

can be used to prevent shoot-through current in Half-

Bridge power devices. The value of the PDC<6:0> bits of

the PWMxCON register sets the number of instruction

cycles before the output is driven active. If the value is

greater than the duty cycle, the corresponding output

remains inactive during the entire cycle. See

Section 24.4.5 “Programmable Dead-Band Delay

Mode” for more details of the dead-band delay

operations.

Since the PxA and PxB outputs are multiplexed with the

PORT data latches, the associated TRIS bits must be

cleared to configure PxA and PxB as outputs.

FIGURE 24-8: EXAMPLE OF HALF-

BRIDGE PWM OUTPUT

FIGURE 24-9: EXAMPLE OF HALF-BRIDGE APPLICATIONS

Period

Pulse Width

(1)

PxA(2)

PxB(2)

td = Dead-Band Delay

Period

(1) (1)

Note 1: At this time, the TMRx register is equal to the

PRx register.

2: Output signals are shown as active-high.

PxA

PxB

FET

Driver

FET

Driver

Load

FET

Driver

FET

Driver

V+

Load

FET

Driver

FET

Driver

PxA

PxB

Standard Half-Bridge Circuit (“Push-Pull”)

Half-Bridge Output Driving a Full-Bridge Circuit

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24.4.2 FULL-BRIDGE MODE

In Full-Bridge mode, all four pins are used as outputs.

An example of Full-Bridge application is shown in

Figure 24-10.

In the Forward mode, pin CCPx/PxA is driven to its active

state, pin PxD is modulated, while PxB and PxC will be

driven to their inactive state as shown in Figure 24-11.

In the Reverse mode, PxC is driven to its active state, pin

PxB is modulated, while PxA and PxD will be driven to

their inactive state as shown Figure 24-11.

PxA, PxB, PxC and PxD outputs are multiplexed with

the PORT data latches. The associated TRIS bits must

be cleared to configure the PxA, PxB, PxC and PxD

pins as outputs.

FIGURE 24-10: EXAMPLE OF FULL-BRIDGE APPLICATION

PxA

PxC

FET

Driver

FET

Driver

V+

V-

Load

FET

Driver

FET

Driver

PxB

PxD

QB QD

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PIC16(L)F1824/1828

FIGURE 24-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT

Period

Pulse Width

PxA(2)

PxB(2)

PxC(2)

PxD(2)

Forward Mode

(1)

Period

Pulse Width

PxA(2)

PxC(2)

PxD(2)

PxB(2)

Reverse Mode

(1)

Note 1: At this time, the TMRx register is equal to the PRx register.

2: Output signal is shown as active-high.

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24.4.2.1 Direction Change in Full-Bridge

Mode

In the Full-Bridge mode, the PxM1 bit in the CCPxCON

direction. When the application firmware changes this

direction control bit, the module will change to the new

direction on the next PWM cycle.

A direction change is initiated in software by changing

the PxM1 bit of the CCPxCON register. The following

sequence occurs four Timer cycles prior to the end of

the current PWM period:

• The modulated outputs (PxB and PxD) are placed

in their inactive state.

• The associated unmodulated outputs (PxA and

PxC) are switched to drive in the opposite

direction.

• PWM modulation resumes at the beginning of the

next period.

See Figure 24-12 for an illustration of this sequence.

The Full-Bridge mode does not provide dead-band

delay. As one output is modulated at a time, dead-band

delay is generally not required. There is a situation

where dead-band delay is required. This situation

occurs when both of the following conditions are true:

1. The direction of the PWM output changes when

the duty cycle of the output is at or near 100%.

2. The turn off time of the power switch, including

the power device and driver circuit, is greater

than the turn on time.

Figure 24-13 shows an example of the PWM direction

changing from forward to reverse, at a near 100% duty

cycle. In this example, at time t1, the output PxA and

PxD become inactive, while output PxC becomes

active. Since the turn off time of the power devices is

longer than the turn on time, a shoot-through current

will flow through power devices QC and QD (see

Figure 24-10) for the duration of ‘t’. The same

phenomenon will occur to power devices QA and QB

for PWM direction change from reverse to forward.

If changing PWM direction at high duty cycle is required

for an application, two possible solutions for eliminating

the shoot-through current are:

1. Reduce PWM duty cycle for one PWM period

before changing directions.

2. Use switch drivers that can drive the switches off

faster than they can drive them on.

Other options to prevent shoot-through current may

exist.

FIGURE 24-12: EXAMPLE OF PWM DIRECTION CHANGE

Pulse Width

Period(1)

Signal

Note 1: The direction bit PxM1 of the CCPxCON register is written any time during the PWM cycle.

2: When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The

modulated PxB and PxD signals are inactive at this time. The length of this time is four Timer counts.

Period

(2)

PxA (Active-High)

PxB (Active-High)

PxC (Active-High)

PxD (Active-High)

Pulse Width

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 231

PIC16(L)F1824/1828

FIGURE 24-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE

Forward Period Reverse Period

PxA

TON

TOFF

T = TOFF – TON

PxB

PxC

PxD

External Switch D

Potential

Shoot-Through Current

Note 1: All signals are shown as active-high.

2: TON is the turn-on delay of power switch QC and its driver.

3: TOFF is the turn-off delay of power switch QD and its driver.

External Switch C

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24.4.3 ENHANCED PWM AUTO-

SHUTDOWN MODE

The PWM mode supports an Auto-Shutdown mode that

will disable the PWM outputs when an external

shutdown event occurs. Auto-Shutdown mode places

the PWM output pins into a predetermined state. This

mode is used to help prevent the PWM from damaging

the application.

The auto-shutdown sources are selected using the

CCPxAS<2:0> bits of the CCPxAS register. A shutdown

event may be generated by:

•A logic ‘0’ on the INT pin

•A logic ‘1’ on a Comparator (Cx) output

A shutdown condition is indicated by the CCPxASE

(Auto-Shutdown Event Status) bit of the CCPxAS

normally. If the bit is a ‘1’, the PWM outputs are in the

shutdown state.

When a shutdown event occurs, two things happen:

The CCPxASE bit is set to ‘1’. The CCPxASE will

remain set until cleared in firmware or an auto-restart

occurs (see Section 24.4.4 “Auto-Restart Mode”).

The enabled PWM pins are asynchronously placed in

their shutdown states. The PWM output pins are

grouped into pairs [PxA/PxC] and [PxB/PxD]. The state

of each pin pair is determined by the PSSxAC and

PSSxBD bits of the CCPxAS register. Each pin pair may

be placed into one of three states:

•Drive logic ‘1’

•Drive logic ‘0’

• Tri-state (high-impedance)

FIGURE 24-14: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PXRSEN = 0)

Note 1: The auto-shutdown condition is a level-

based signal, not an edge-based signal.

As long as the level is present, the auto-

shutdown will persist.

2: Writing to the CCPxASE bit is disabled

while an auto-shutdown condition

persists.

3: Once the auto-shutdown condition has

been removed and the PWM restarted

(either through firmware or auto-restart)

the PWM signal will always restart at the

beginning of the next PWM period.

4: Prior to an auto-shutdown event caused

by a comparator output or INT pin event,

a software shutdown can be triggered in

firmware by setting the CCPxASE bit of

the CCPxAS register to ‘1’. The Auto-

Restart feature tracks the active status of

a shutdown caused by a comparator out-

put or INT pin event only. If it is enabled at

this time, it will immediately clear this bit

and restart the ECCP module at the

beginning of the next PWM period.

Shutdown

PWM

CCPxASE bit

Activity

Event

Shutdown

Event Occurs Shutdown

Event Clears

PWM

Resumes

PWM Period

Start of

PWM Period

CCPxASE

Cleared by

Firmware

Timer

Overflow Timer

Overflow

Timer

Overflow Timer

Overflow

Missing Pulse

(Auto-Shutdown) Missing Pulse

(CCPxASE not clear)

Timer

Overflow

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24.4.4 AUTO-RESTART MODE

The Enhanced PWM can be configured to automati-

cally restart the PWM signal once the auto-shutdown

condition has been removed. Auto-restart is enabled by

setting the PxRSEN bit in the PWMxCON register.

If auto-restart is enabled, the CCPxASE bit will remain

set as long as the auto-shutdown condition is active.

When the auto-shutdown condition is removed, the

CCPxASE bit will be cleared via hardware and normal

operation will resume.

FIGURE 24-15: PWM AUTO-SHUTDOWN WITH AUTO-RESTART (PXRSEN = 1)

Shutdown

PWM

CCPxASE bit

Activity

Event

Shutdown

Event Occurs

Shutdown

Event Clears

PWM Period

Start of

PWM Period

CCPxASE

Cleared by

Hardware

Timer

Overflow Timer

Overflow

Timer

Overflow Timer

Overflow

Missing Pulse

(Auto-Shutdown) Missing Pulse

(CCPxASE not clear)

Timer

Overflow

PWM

Resumes

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24.4.5 PROGRAMMABLE DEAD-BAND

DELAY MODE

In Half-Bridge applications where all power switches

are modulated at the PWM frequency, the power

switches normally require more time to turn off than to

turn on. If both the upper and lower power switches are

switched at the same time (one turned on, and the

other turned off), both switches may be on for a short

period of time until one switch completely turns off.

During this brief interval, a very high current (shoot-

through current) will flow through both power switches,

shorting the bridge supply. To avoid this potentially

destructive shoot-through current from flowing during

switching, turning on either of the power switches is

normally delayed to allow the other switch to

completely turn off.

In Half-Bridge mode, a digitally programmable dead-

band delay is available to avoid shoot-through current

from destroying the bridge power switches. The delay

occurs at the signal transition from the non-active state

to the active state. See Figure 24-16 for illustration.

The lower seven bits of the associated PWMxCON

of microcontroller instruction cycles (TCY or 4 TOSC).

FIGURE 24-16: EXAMPLE OF HALF-

BRIDGE PWM OUTPUT

FIGURE 24-17: EXAMPLE OF HALF-BRIDGE APPLICATIONS

Period

Pulse Width

(1)

PxA(2)

PxB(2)

td = Dead-Band Delay

Period

(1) (1)

Note 1: At this time, the TMRx register is equal to the

PRx register.

2: Output signals are shown as active-high.

PxA

PxB

FET

Driver

FET

Driver

V+

V-

Load

Standard Half-Bridge Circuit (“Push-Pull”)

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 235

PIC16(L)F1824/1828

24.4.6 PWM STEERING MODE

In Single Output mode, PWM steering allows any of the

PWM pins to be the modulated signal. Additionally, the

same PWM signal can be simultaneously available on

multiple pins.

Once the Single Output mode is selected

(CCPxM<3:2> = 11 and PxM<1:0> = 00 of the

CCPxCON register), the user firmware can bring out

the same PWM signal to one, two, three or four output

pins by setting the appropriate STRx<D:A> bits of the

PSTRxCON register, as shown in Tabl e 24 - 9 .

While the PWM Steering mode is active, CCPxM<1:0>

bits of the CCPxCON register select the PWM output

polarity for the Px<D:A> pins.

The PWM auto-shutdown operation also applies to

PWM Steering mode as described in Section 24.4.3

“Enhanced PWM Auto-shutdown mode”. An auto-

shutdown event will only affect pins that have PWM

outputs enabled.

FIGURE 24-18: SIMPLIFIED STEERING

BLOCK DIAGRAM

Note: The associated TRIS bits must be set to

output (‘0’) to enable the pin output driver

in order to see the PWM signal on the pin.

0TRIS

PxA pin

PORT Data

PxA Signal

STRxA

TRIS

PxB pin

PORT Data

STRxB

TRIS

PxC pin

PORT Data

STRxC

TRIS

PxD pin

PORT Data

STRxD

Note 1: Port outputs are configured as shown when

the CCPxCON register bits PxM<1:0> = 00

and CCPxM<3:2> = 11.

2: Single PWM output requires setting at least

one of the STRx bits.

CCPxM1

CCPxM0

CCPxM1

CCPxM0

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24.4.6.1 Steering Synchronization

The STRxSYNC bit of the PSTRxCON register gives

the user two selections of when the steering event will

happen. When the STRxSYNC bit is ‘0’, the steering

event will happen at the end of the instruction that

writes to the PSTRxCON register. In this case, the

output signal at the Px<D:A> pins may be an

incomplete PWM waveform. This operation is useful

when the user firmware needs to immediately remove

a PWM signal from the pin.

When the STRxSYNC bit is ‘1’, the effective steering

update will happen at the beginning of the next PWM

period. In this case, steering on/off the PWM output will

always produce a complete PWM waveform.

Figures 24-19 and 24-20 illustrate the timing diagrams

of the PWM steering depending on the STRxSYNC

setting.

24.4.7 START-UP CONSIDERATIONS

When any PWM mode is used, the application

hardware must use the proper external pull-up and/or

pull-down resistors on the PWM output pins.

The CCPxM<1:0> bits of the CCPxCON register allow

the user to choose whether the PWM output signals are

active-high or active-low for each pair of PWM output

pins (PxA/PxC and PxB/PxD). The PWM output

polarities must be selected before the PWM pin output

drivers are enabled. Changing the polarity

configuration while the PWM pin output drivers are

enable is not recommended since it may result in

damage to the application circuits.

The PxA, PxB, PxC and PxD output latches may not be

in the proper states when the PWM module is

initialized. Enabling the PWM pin output drivers at the

same time as the Enhanced PWM modes may cause

damage to the application circuit. The Enhanced PWM

modes must be enabled in the proper Output mode and

complete a full PWM cycle before enabling the PWM

pin output drivers. The completion of a full PWM cycle

is indicated by the TMRxIF bit of the PIRx register

being set as the second PWM period begins.

24.4.8 ALTERNATE PIN LOCATIONS

This module incorporates I/O pins that can be moved to

other locations with the use of the alternate pin function

registers, APFCON0 and APFCON1. To determine

which pins can be moved and what their default loca-

tions are upon a Reset, see Section 12.1 “Alternate

Pin Function” for more information.

FIGURE 24-19: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRxSYNC = 0)

FIGURE 24-20: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION

(STRxSYNC = 1)

Note: When the microcontroller is released from

Reset, all of the I/O pins are in the high-

impedance state. The external circuits

must keep the power switch devices in the

Off state until the microcontroller drives

the I/O pins with the proper signal levels or

activates the PWM output(s).

PWM

P1n = PWM

STRx

P1<D:A> PORT Data

PWM Period

PORT Data

PWM

PORT Data

P1n = PWM

STRx

P1<D:A> PORT Data

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TABLE 24-10: SUMMARY OF REGISTERS ASSOCIATED WITH ENHANCED PWM

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

APFCON1 ———— P1DSEL P1CSEL P2BSEL CCP2SEL 123

CCPxCON PxM<1:0>(1) DCxB<1:0> CCPxM<3:0> 238

CCPxAS CCPxASE CCPxAS<2:0> PSSxAC<1:0> PSSxBD<1:0> 240

CCPTMRS0 C4TSEL<1:0> C3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 239

INLVLA ——INLVLA5INLVLA4INLVLA3 INLVLA2 INLVLA1 INLVLA0 128

INLVLC INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 139

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 94

PIE2 OSFIE C2IE C1IE EEIE BCLIE —— CCP2IE 95

PIE3 —— CCP4IE CCP3IE TMR6IE —TMR4IE —96

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 97

PIR2 OSFIF C2IF C1IF EEIF BCLIF ——CCP2IF

PIR3 —— CCP4IF CCP3IF TMR6IF —TMR4IF —99

PRx Timer2/4/6 Period Register 201*

PSTRxCON ——— STRxSYNC STRxD STRxC STRxB STRxA 242

PWMxCON PxRSEN PxDC<6:0> 241

TxCON — TxOUTPS<3:0> TMRxON TxCKPS<:0>1 203

TRISA —— TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 126

TRISC TRISC7(2) TRISC6(2) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 137

Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.

* Page provides register information.

Note 1: Applies to ECCP modules only.

2: PIC16(L)F1828 only.

PIC16(L)F1824/1828

DS41419C-page 238 Preliminary  2010-2011 Microchip Technology Inc.

R/W-00 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

PxM<1:0>(1) DCxB<1:0> CCPxM<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 PxM<1:0>: Enhanced PWM Output Configuration bits(1)

Capture mode:

Unused

Compare mode:

Unused

If CCPxM<3:2> = 00, 01, 10:

xx = PxA assigned as Capture/Compare input; PxB, PxC, PxD assigned as port pins

If CCPxM<3:2> = 11:

00 = Single output; PxA modulated; PxB, PxC, PxD assigned as port pins

01 = Full-Bridge output forward; PxD modulated; PxA active; PxB, PxC inactive

10 = Half-Bridge output; PxA, PxB modulated with dead-band control; PxC, PxD assigned as port pins

11 = Full-Bridge output reverse; PxB modulated; PxC active; PxA, PxD inactive

bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits

Capture mode:

Unused

Compare mode:

Unused

PWM mode:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.

bit 3-0 CCPxM<3:0>: ECCPx Mode Select bits

0000 = Capture/Compare/PWM off (resets ECCPx module)

0001 = Reserved

0010 = Compare mode: toggle output on match

0011 = Reserved

0100 = Capture mode: every falling edge

0101 = Capture mode: every rising edge

0110 = Capture mode: every 4th rising edge

0111 = Capture mode: every 16th rising edge

1000 = Compare mode: initialize ECCPx pin low; set output on compare match (set CCPxIF)

1001 = Compare mode: initialize ECCPx pin high; clear output on compare match (set CCPxIF)

1010 = Compare mode: generate software interrupt only; ECCPx pin reverts to I/O state

1011 = Compare mode: Special Event Trigger (ECCPx resets TMR1 or TMR3, sets CCPxIF bit, ECCP2 trigger

also starts A/D conversion if A/D module is enabled)(1)

CCP Modules only:

11xx =PWM mode

ECCP modules only:

1100 = PWM mode: PxA, PxC active-high; PxB, PxD active-high

1101 = PWM mode: PxA, PxC active-high; PxB, PxD active-low

1110 = PWM mode: PxA, PxC active-low; PxB, PxD active-high

1111 = PWM mode: PxA, PxC active-low; PxB, PxD active-low

Note 1: These bits are not implemented on CCP<4:3>.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 239

PIC16(L)F1824/1828

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

C4TSEL<1:0> C3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 C4TSEL<1:0>: CCP4 Timer Selection bits

00 = CCP4 is based off Timer 2 in PWM mode

01 = CCP4 is based off Timer 4 in PWM mode

10 = CCP4 is based off Timer 6 in PWM mode

11 =Reserved

bit 5-4 C3TSEL<1:0>: CCP3 Timer Selection bits

00 = CCP3 is based off Timer 2 in PWM mode

01 = CCP3 is based off Timer 4 in PWM mode

10 = CCP3 is based off Timer 6 in PWM mode

11 =Reserved

bit 3-2 C2TSEL<1:0>: CCP2 Timer Selection bits

00 = CCP2 is based off Timer 2 in PWM mode

01 = CCP2 is based off Timer 4 in PWM mode

10 = CCP2 is based off Timer 6 in PWM mode

11 =Reserved

bit 1-0 C1TSEL<1:0>: CCP1 Timer Selection bits

00 = CCP1 is based off Timer 2 in PWM mode

01 = CCP1 is based off Timer 4 in PWM mode

10 = CCP1 is based off Timer 6 in PWM mode

11 =Reserved

PIC16(L)F1824/1828

DS41419C-page 240 Preliminary  2010-2011 Microchip Technology Inc.

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

CCPxASE CCPxAS<2:0> PSSxAC<1:0> PSSxBD<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 CCPxASE: CCPx Auto-Shutdown Event Status bit

1 = A shutdown event has occurred; CCPx outputs are in shutdown state

0 = CCPx outputs are operating

bit 6-4 CCPxAS<2:0>: CCPx Auto-Shutdown Source Select bits

000 = Auto-shutdown is disabled

001 = Comparator C1 output high(1)

010 = Comparator C2 output high(1)

011 = Either Comparator C1 or C2 high(1)

100 =VIL on INT pin

101 =V

IL on INT pin or Comparator C1 high(1)

110 =VIL on INT pin or Comparator C2 high(1)

111 =VIL on INT pin or Comparator C1 or Comparator C2 high(1)

bit 3-2 PSSxAC<1:0>: Pins PxA and PxC Shutdown State Control bits

00 = Drive pins PxA and PxC to ‘0’

01 = Drive pins PxA and PxC to ‘1’

1x = Pins PxA and PxC tri-state

bit 1-0 PSSxBD<1:0>: Pins PxB and PxD Shutdown State Control bits

00 = Drive pins PxB and PxD to ‘0’

01 = Drive pins PxB and PxD to ‘1’

1x = Pins PxB and PxD tri-state

Note 1: If CxSYNC is enabled, the shutdown will be delayed by Timer1.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 241

PIC16(L)F1824/1828

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

PxRSEN PxDC<6:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 PxRSEN: PWM Restart Enable bit

1 = Upon auto-shutdown, the CCPxASE bit clears automatically once the shutdown event goes

away; the PWM restarts automatically

0 = Upon auto-shutdown, CCPxASE must be cleared in software to restart the PWM

bit 6-0 PxDC<6:0>: PWM Delay Count bits

PxDCx = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal

should transition active and the actual time it transitions active

Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe

mode is enabled.

PIC16(L)F1824/1828

DS41419C-page 242 Preliminary  2010-2011 Microchip Technology Inc.

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1

— — — STRxSYNC STRxD STRxC STRxB STRxA

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4 STRxSYNC: Steering Sync bit

1 = Output steering update occurs on next PWM period

0 = Output steering update occurs at the beginning of the instruction cycle boundary

bit 3 STRxD: Steering Enable bit D

1 = PxD pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = PxD pin is assigned to port pin

bit 2 STRxC: Steering Enable bit C

1 = PxC pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = PxC pin is assigned to port pin

bit 1 STRxB: Steering Enable bit B

1 = PxB pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = PxB pin is assigned to port pin

bit 0 STRxA: Steering Enable bit A

1 = PxA pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = PxA pin is assigned to port pin

Note 1: The PWM Steering mode is available only when the CCPxCON register bits CCPxM<3:2> = 11 and

PxM<1:0> = 00.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 243

PIC16(L)F1824/1828

25.0 MASTER SYNCHRONOUS

SERIAL PORT MODULE

25.1 Master SSP (MSSP1) Module

Overview

The Master Synchronous Serial Port (MSSP1) module

is a serial interface useful for communicating with other

peripheral or microcontroller devices. These peripheral

devices may be Serial EEPROMs, shift registers, dis-

play drivers, A/D converters, etc. The MSSP1 module

can operate in one of two modes:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I2C™)

The SPI interface supports the following modes and

features:

•Master mode

• Slave mode

• Clock Parity

• Slave Select Synchronization (Slave mode only)

• Daisy chain connection of slave devices

Figure 25-1 is a block diagram of the SPI interface

module.

FIGURE 25-1: MSSP1 BLOCK DIAGRAM (SPI MODE)

( )

Read Write

Data Bus

SSP1SR Reg

SSP1M<3:0>

bit 0 Shift

Clock

SS Control

Enable

Edge

Select

Clock Select

TMR2 Output

TOSC

Prescaler

4, 16, 64

Edge

Select

2 (CKP, CKE)

TRIS bit

SDO

SSP1BUF Reg

SDI

SCK

Baud rate

generator

(SSP1ADD)

PIC16(L)F1824/1828

DS41419C-page 244 Preliminary  2010-2011 Microchip Technology Inc.

The I2C interface supports the following modes and

features:

•Master mode

• Slave mode

• Byte NACKing (Slave mode)

• Limited multi-master support

• 7-bit and 10-bit addressing

• Start and Stop interrupts

• Interrupt masking

• Clock stretching

• Bus collision detection

• General call address matching

•Address masking

• Address Hold and Data Hold modes

• Selectable SDA hold times

Figure 25-2 is a block diagram of the I2C interface mod-

ule in Master mode. Figure 25-3 is a diagram of the I2C

interface module in Slave mode.

FIGURE 25-2: MSSP1 BLOCK DIAGRAM (I2C™ MASTER MODE)

Read Write

SSP1SR

Start bit, Stop bit,

Start bit detect,

SSP1BUF

Internal

data bus

Set/Reset: S, P, SSP1STAT, WCOL, SSPOV

Shift

Clock

MSb LSb

SDA

Acknowledge

Generate (SSP1CON2)

Stop bit detect

Write collision detect

Clock arbitration

State counter for

end of XMIT/RCV

SCL

SCL in

Bus Collision

SDA in

Receive Enable (RCEN)

Clock Cntl

Clock arbitrate/BCOL detect

(Hold off clock source)

[SSPM 3:0]

Baud rate

Reset SEN, PEN (SSP1CON2)

generator

(SSP1ADD)

Address Match detect

Set SSP1IF, BCL1IF

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 245

PIC16(L)F1824/1828

FIGURE 25-3: MSSP1 BLOCK DIAGRAM (I2C™ SLAVE MODE)

Read Write

SSP1SR Reg

Match Detect

SSP1ADD Reg

Start and

Stop bit Detect

SSP1BUF Reg

Internal

Data Bus

Addr Match

Set, Reset

S, P bits

(SSP1STAT Reg)

SCL

SDA

Shift

Clock

MSb LSb

SSP1MSK Reg

PIC16(L)F1824/1828

DS41419C-page 246 Preliminary  2010-2011 Microchip Technology Inc.

25.2 SPI Mode Overview

The Serial Peripheral Interface (SPI) bus is a

synchronous serial data communication bus that

operates in Full Duplex mode. Devices communicate in

a master/slave environment where the master device

initiates the communication. A slave device is

controlled through a chip select known as Slave Select.

The SPI bus specifies four signal connections:

• Serial Clock (SCK)

• Serial Data Out (SDO)

• Serial Data In (SDI)

• Slave Select (SS)

Figure 25-1 shows the block diagram of the MSSP1

module when operating in SPI Mode.

The SPI bus operates with a single master device and

one or more slave devices. When multiple slave

devices are used, an independent Slave Select con-

nection is required from the master device to each

slave device.

Figure 25-4 shows a typical connection between a

master device and multiple slave devices.

The master selects only one slave at a time. Most slave

devices have tri-state outputs so their output signal

appears disconnected from the bus when they are not

selected.

Transmissions involve two shift registers, eight bits in

size, one in the master and one in the slave. With either

the master or the slave device, data is always shifted

out one bit at a time, with the Most Significant bit (MSb)

shifted out first. At the same time, a new Least

Significant bit (LSb) is shifted into the same register.

Figure 25-5 shows a typical connection between two

processors configured as master and slave devices.

Data is shifted out of both shift registers on the pro-

grammed clock edge and latched on the opposite edge

of the clock.

The master device transmits information out on its SDO

output pin which is connected to, and received by, the

slave’s SDI input pin. The slave device transmits infor-

mation out on its SDO output pin, which is connected

to, and received by, the master’s SDI input pin.

To begin communication, the master device first sends

out the clock signal. Both the master and the slave

devices should be configured for the same clock polar-

ity.

The master device starts a transmission by sending out

the MSb from its shift register. The slave device reads

this bit from that same line and saves it into the LSb

position of its shift register.

During each SPI clock cycle, a full duplex data

transmission occurs. This means that while the master

device is sending out the MSb from its shift register (on

its SDO pin) and the slave device is reading this bit and

saving it as the LSb of its shift register, that the slave

device is also sending out the MSb from its shift register

(on its SDO pin) and the master device is reading this

bit and saving it as the LSb of its shift register.

After 8 bits have been shifted out, the master and slave

have exchanged register values.

If there is more data to exchange, the shift registers are

loaded with new data and the process repeats itself.

Whether the data is meaningful or not (dummy data),

depends on the application software. This leads to

three scenarios for data transmission:

• Master sends useful data and slave sends dummy

data.

• Master sends useful data and slave sends useful

data.

• Master sends dummy data and slave sends useful

data.

Transmissions may involve any number of clock

cycles. When there is no more data to be transmitted,

the master stops sending the clock signal and it dese-

lects the slave.

Every slave device connected to the bus that has not

been selected through its slave select line must disre-

gard the clock and transmission signals and must not

transmit out any data of its own.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 247

PIC16(L)F1824/1828

FIGURE 25-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION

25.2.1 SPI MODE REGISTERS

The MSSP1 module has five registers for SPI mode

operation. These are:

• MSSP1 STATUS Register (SSP1STAT)

• MSSP1 Control Register 1 (SSP1CON1)

• MSSP1 Control Register 3 (SSP1CON3)

• MSSP1 Data Buffer Register (SSP1BUF)

• MSSP1 Address Register (SSP1ADD)

• MSSP1 Shift Register (SSP1SR)

(Not directly accessible)

SSP1CON1 and SSP1STAT are the control and

STATUS registers in SPI mode operation. The

SSP1CON1 register is readable and writable. The

lower 6 bits of the SSP1STAT are read-only. The upper

two bits of the SSP1STAT are read/write.

In SPI master mode, SSP1ADD can be loaded with a

value used in the Baud Rate Generator. More informa-

tion on the Baud Rate Generator is available in

Section 25.7 “Baud Rate Generator”.

SSP1SR is the shift register used for shifting data in

and out. SSP1BUF provides indirect access to the

SSP1SR register. SSP1BUF is the buffer register to

which data bytes are written, and from which data

bytes are read.

In receive operations, SSP1SR and SSP1BUF

together create a buffered receiver. When SSP1SR

receives a complete byte, it is transferred to SSP1BUF

and the SSP1IF interrupt is set.

During transmission, the SSP1BUF is not buffered. A

write to SSP1BUF will write to both SSP1BUF and

SSP1SR.

SPI Master SCK

SDO

SDI

General I/O

SCK

SDI

SDO

SPI Slave

SCK

SDI

SDO

SPI Slave

SCK

SDI

SDO

SPI Slave

PIC16(L)F1824/1828

DS41419C-page 248 Preliminary  2010-2011 Microchip Technology Inc.

25.2.2 SPI MODE OPERATION

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits (SSP1CON1<5:0> and SSP1STAT<7:6>).

These control bits allow the following to be specified:

• Master mode (SCK1 is the clock output)

• Slave mode (SCK1 is the clock input)

• Clock Polarity (Idle state of SCK1)

• Data Input Sample Phase (middle or end of data

output time)

• Clock Edge (output data on rising/falling edge of

SCK1)

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

To enable the serial port, SSP1 Enable bit, SSP1EN of

the SSP1CON1 register, must be set. To reset or

reconfigure SPI mode, clear the SSP1EN bit, re-initial-

ize the SSP1CONx registers and then set the SSP1EN

bit. This configures the SDI, SDO, SCK and SS pins as

serial port pins. For the pins to behave as the serial port

function, some must have their data direction bits (in

the TRIS register) appropriately programmed as fol-

lows:

• SDI must have corresponding TRIS bit set

• SDO must have corresponding TRIS bit cleared

• SCK (Master mode) must have corresponding

TRIS bit cleared

• SCK (Slave mode) must have corresponding

TRIS bit set

•SS

must have corresponding TRIS bit set

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

The MSSP1 consists of a transmit/receive shift register

(SSP1SR) and a buffer register (SSP1BUF). The

SSP1SR shifts the data in and out of the device, MSb

first. The SSP1BUF holds the data that was written to

the SSP1SR until the received data is ready. Once the

8 bits of data have been received, that byte is moved to

the SSP1BUF register. Then, the Buffer Full Detect bit,

BF of the SSP1STAT register, and the interrupt flag bit,

SSP1IF, are set. This double-buffering of the received

data (SSP1BUF) allows the next byte to start reception

before reading the data that was just received. Any

write to the SSP1BUF register during

transmission/reception of data will be ignored and the

write collision detect bit WCOL of the SSP1CON1

WCOL bit to allow the following write(s) to the

SSP1BUF register to complete successfully.

When the application software is expecting to receive

valid data, the SSP1BUF should be read before the

next byte of data to transfer is written to the SSP1BUF.

The Buffer Full bit, BF of the SSP1STAT register,

indicates when SSP1BUF has been loaded with the

received data (transmission is complete). When the

SSP1BUF is read, the BF bit is cleared. This data may

be irrelevant if the SPI is only a transmitter. Generally,

the MSSP1 interrupt is used to determine when the

transmission/reception has completed. If the interrupt

method is not going to be used, then software polling

can be done to ensure that a write collision does not

occur.

The SSP1SR is not directly readable or writable and

can only be accessed by addressing the SSP1BUF

the various Status conditions.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 249

PIC16(L)F1824/1828

FIGURE 25-5: SPI MASTER/SLAVE CONNECTION

Serial Input Buffer

(BUF)

Shift Register

(SSP1SR)

MSb LSb

SDO

SDI

Processor 1

SCK

SPI Master SSP1M<3:0> = 00xx

Serial Input Buffer

(SSP1BUF)

Shift Register

(SSP1SR)

LSb

MSb

SDI

SDO

Processor 2

SCK

SPI Slave SSP1M<3:0> = 010x

Serial Clock

Slave Select

General I/O (optional)

= 1010

PIC16(L)F1824/1828

DS41419C-page 250 Preliminary  2010-2011 Microchip Technology Inc.

25.2.3 SPI MASTER MODE

The master can initiate the data transfer at any time

because it controls the SCK line. The master

determines when the slave (Processor 2, Figure 25-5)

is to broadcast data by the software protocol.

In Master mode, the data is transmitted/received as

soon as the SSP1BUF register is written to. If the SPI

is only going to receive, the SDO output could be dis-

abled (programmed as an input). The SSP1SR register

will continue to shift in the signal present on the SDI pin

at the programmed clock rate. As each byte is

received, it will be loaded into the SSP1BUF register as

if a normal received byte (interrupts and Status bits

appropriately set).

The clock polarity is selected by appropriately

programming the CKP bit of the SSP1CON1 register

and the CKE bit of the SSP1STAT register. This then,

would give waveforms for SPI communication as

shown in Figure 25-6, Figure 25-9 and Figure 25-10,

where the MSb is transmitted first. In Master mode, the

SPI clock rate (bit rate) is user programmable to be one

of the following:

•F

OSC/4 (or TCY)

•FOSC/16 (or 4 * TCY)

•FOSC/64 (or 16 * TCY)

• Timer2 output/2

• Fosc/(4 * (SSP1ADD + 1))

Figure 25-6 shows the waveforms for Master mode.

When the CKE bit is set, the SDO data is valid before

there is a clock edge on SCK. The change of the input

sample is shown based on the state of the SMP bit. The

time when the SSP1BUF is loaded with the received

data is shown.

FIGURE 25-6: SPI MODE WAVEFORM (MASTER MODE)

SCK

(CKP = 0

SCK

(CKP = 1

SCK

(CKP = 0

SCK

(CKP = 1

4 Clock

Modes

Input

Sample

Input

Sample

SDI

bit 7 bit 0

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

bit 7

SDI

SSP1IF

(SMP = 1)

(SMP = 0)

(SMP = 1)

CKE = 1)

CKE = 0)

CKE = 1)

CKE = 0)

(SMP = 0)

Write to

SSP1BUF

SSP1SR to

SSP1BUF

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 0)

(CKE = 1)

bit 0

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 251

PIC16(L)F1824/1828

25.2.4 SPI SLAVE MODE

In Slave mode, the data is transmitted and received as

external clock pulses appear on SCK. When the last

bit is latched, the SSP1IF interrupt flag bit is set.

Before enabling the module in SPI Slave mode, the clock

line must match the proper Idle state. The clock line can

be observed by reading the SCK pin. The Idle state is

determined by the CKP bit of the SSP1CON1 register.

While in Slave mode, the external clock is supplied by

the external clock source on the SCK pin. This external

clock must meet the minimum high and low times as

specified in the electrical specifications.

While in Sleep mode, the slave can transmit/receive

data. The shift register is clocked from the SCK pin

input and when a byte is received, the device will gen-

erate an interrupt. If enabled, the device will wake-up

from Sleep.

25.2.4.1 Daisy-Chain Configuration

The SPI bus can sometimes be connected in a

daisy-chain configuration. The first slave output is con-

nected to the second slave input, the second slave

output is connected to the third slave input, and so on.

The final slave output is connected to the master input.

Each slave sends out, during a second group of clock

pulses, an exact copy of what was received during the

first group of clock pulses. The whole chain acts as

one large communication shift register. The

daisy-chain feature only requires a single Slave Select

line from the master device.

Figure 25-7 shows the block diagram of a typical

Daisy-Chain connection when operating in SPI Mode.

In a daisy-chain configuration, only the most recent

byte on the bus is required by the slave. Setting the

BOEN bit of the SSP1CON3 register will enable writes

to the SSP1BUF register, even if the previous byte has

not been read. This allows the software to ignore data

that may not apply to it.

25.2.5 SLAVE SELECT

SYNCHRONIZATION

The Slave Select can also be used to synchronize com-

munication. The Slave Select line is held high until the

master device is ready to communicate. When the

Slave Select line is pulled low, the slave knows that a

new transmission is starting.

If the slave fails to receive the communication properly,

it will be reset at the end of the transmission, when the

Slave Select line returns to a high state. The slave is

then ready to receive a new transmission when the

Slave Select line is pulled low again. If the Slave Select

line is not used, there is a risk that the slave will even-

tually become out of sync with the master. If the slave

misses a bit, it will always be one bit off in future trans-

missions. Use of the Slave Select line allows the slave

and master to align themselves at the beginning of

each transmission.

The SS pin allows a Synchronous Slave mode. The

SPI must be in Slave mode with SS pin control enabled

(SSP1CON1<3:0> = 0100).

When the SS pin is low, transmission and reception are

enabled and the SDO pin is driven.

When the SS pin goes high, the SDO pin is no longer

driven, even if in the middle of a transmitted byte and

becomes a floating output. External pull-up/pull-down

resistors may be desirable depending on the applica-

tion.

When the SPI module resets, the bit counter is forced

to ‘0’. This can be done by either forcing the SS pin to

a high level or clearing the SSP1EN bit.

Note 1: When the SPI is in Slave mode with SS pin

control enabled (SSP1CON1<3:0> =

0100), the SPI module will reset if the SS

pin is set to VDD.

2: When the SPI is used in Slave mode with

CKE set; the user must enable SS pin

control.

3: While operated in SPI Slave mode the

SMP bit of the SSP1STAT register must

remain clear.

PIC16(L)F1824/1828

DS41419C-page 252 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 25-7: SPI DAISY-CHAIN CONNECTION

FIGURE 25-8: SLAVE SELECT SYNCHRONOUS WAVEFORM

SPI Master SCK

SDO

SDI

General I/O

SCK

SDI

SDO

SPI Slave

SCK

SDI

SDO

SPI Slave

SCK

SDI

SDO

SPI Slave

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI

bit 7

SDO bit 7 bit 6 bit 7

SSP1IF

Interrupt

CKE = 0)

Write to

SSP1BUF

SSP1SR to

SSP1BUF

Flag

bit 0

bit 7

bit 0

bit 6

SSP1BUF to

SSP1SR

Shift register SSP1SR

and bit count are reset

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 253

PIC16(L)F1824/1828

FIGURE 25-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

FIGURE 25-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI

bit 7

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SSP1IF

Interrupt

CKE = 0)

Write to

SSP1BUF

SSP1SR to

SSP1BUF

Flag

Optional

bit 0

detection active

Write Collision

Valid

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI

bit 7 bit 0

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SSP1IF

Interrupt

CKE = 1)

Write to

SSP1BUF

SSP1SR to

SSP1BUF

Flag

Not Optional

Write Collision

detection active

Valid

PIC16(L)F1824/1828

DS41419C-page 254 Preliminary  2010-2011 Microchip Technology Inc.

25.2.6 SPI OPERATION IN SLEEP MODE

In SPI Master mode, module clocks may be operating

at a different speed than when in Full Power mode; in

the case of the Sleep mode, all clocks are halted.

Special care must be taken by the user when the

MSSP1 clock is much faster than the system clock.

In Slave mode, when MSSP1 interrupts are enabled,

after the master completes sending data, an MSSP1

interrupt will wake the controller from Sleep.

If an exit from Sleep mode is not desired, MSSP1 inter-

rupts should be disabled.

In SPI Master mode, when the Sleep mode is selected,

all module clocks are halted and the transmis-

sion/reception will remain in that state until the device

wakes. After the device returns to Run mode, the mod-

ule will resume transmitting and receiving data.

In SPI Slave mode, the SPI Transmit/Receive Shift

allows the device to be placed in Sleep mode and data

to be shifted into the SPI Transmit/Receive Shift

MSSP1 interrupt flag bit will be set and if enabled, will

wake the device.

TABLE 25-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on

Page

ANSELA — — —ANSA4 —ANSA2 ANSA1 ANSA0 127

ANSELB(1) ANSB7 ANSB6 ANSB5 ANSB4 — — — — 133

ANSELC ANSC7(1) ANSC6(1) — — ANSC3 ANSC2 ANSC1 ANSC0 133

APFCON0 RXDTSEL SDOSEL(2) SSSEL(2) —T1GSEL TXCKSEL — — 122

INLVLA(3) — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 128

INLVLA(4) — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 128

INLVLB(1) INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — — 133

INLVLC(3) INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 139

INLVLC(4) INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 139

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 94

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 97

SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 247*

SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 293

SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 295

SSP1STAT SMP CKE D/A P S R/W UA BF 292

TRISA(3) — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 126

TRISA(4) — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 126

TRISB(1) TRISB7 TRISB6 TRISB5 TRISB4 — — — — 132

TRISC(3) TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132

TRISC(4) TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132

Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP1 in SPI mode.

* Page provides register information.

Note 1: PIC16(L)F1828 only.

2: PIC16(L)F1824 only.

3: Unshaded cells apply to PIC16(L)F1828 only.

4: Unshaded cells apply to PIC16(L)F1824 only.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 255

PIC16(L)F1824/1828

25.3 I2C Mode Overview

The Inter-Integrated Circuit Bus (I²C) is a multi-master

serial data communication bus. Devices communicate

in a master/slave environment where the master

devices initiate the communication. A Slave device is

controlled through addressing.

The I2C bus specifies two signal connections:

• Serial Clock (SCL)

• Serial Data (SDA)

Figure 25-2 and Figure 25-3 shows the block diagram

of the MSSP1 module when operating in I2C Mode.

Both the SCL and SDA connections are bidirectional

open-drain lines, each requiring pull-up resistors for the

supply voltage. Pulling the line to ground is considered

a logical zero and letting the line float is considered a

logical one.

Figure 25-11 shows a typical connection between two

processors configured as master and slave devices.

The I2C bus can operate with one or more master

devices and one or more slave devices.

There are four potential modes of operation for a given

device:

• Master Transmit mode

(master is transmitting data to a slave)

• Master Receive mode

(master is receiving data from a slave)

•Slave Transmit mode

(slave is transmitting data to a master)

• Slave Receive mode

(slave is receiving data from the master)

To begin communication, a master device starts out in

Master Transmit mode. The master device sends out a

Start bit followed by the address byte of the slave it

intends to communicate with. This is followed by a sin-

gle Read/Write bit, which determines whether the mas-

ter intends to transmit to or receive data from the slave

device.

If the requested slave exists on the bus, it will respond

with an Acknowledge bit, otherwise known as an ACK.

The master then continues in either Transmit mode or

Receive mode and the slave continues in the comple-

ment, either in Receive mode or Transmit mode,

respectively.

A Start bit is indicated by a high-to-low transition of the

SDA line while the SCL line is held high. Address and

data bytes are sent out, Most Significant bit (MSb) first.

The Read/Write bit is sent out as a logical one when the

master intends to read data from the slave, and is sent

out as a logical zero when it intends to write data to the

slave.

FIGURE 25-11: I2C MASTER/

SLAVE CONNECTION

The Acknowledge bit (ACK) is an active-low signal,

which holds the SDA line low to indicate to the transmit-

ter that the slave device has received the transmitted

data and is ready to receive more.

The transition of a data bit is always performed while

the SCL line is held low. Transitions that occur while the

SCL line is held high are used to indicate Start and Stop

bits.

If the master intends to write to the slave, then it repeat-

edly sends out a byte of data, with the slave responding

after each byte with an ACK bit. In this example, the

master device is in Master Transmit mode and the

slave is in Slave Receive mode.

If the master intends to read from the slave, then it

repeatedly receives a byte of data from the slave, and

responds after each byte with an ACK bit. In this exam-

ple, the master device is in Master Receive mode and

the slave is Slave Transmit mode.

On the last byte of data communicated, the master

device may end the transmission by sending a Stop bit.

If the master device is in Receive mode, it sends the

Stop bit in place of the last ACK bit. A Stop bit is indi-

cated by a low-to-high transition of the SDA line while

the SCL line is held high.

In some cases, the master may want to maintain con-

trol of the bus and re-initiate another transmission. If

so, the master device may send another Start bit in

place of the Stop bit or last ACK bit when it is in receive

mode.

The I2C bus specifies three message protocols;

• Single message where a master writes data to a

slave.

• Single message where a master reads data from

a slave.

• Combined message where a master initiates a

minimum of two writes, or two reads, or a

combination of writes and reads, to one or more

slaves.

Master

SCL

SDA

SCL

SDA

Slave

VDD

PIC16(L)F1824/1828

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When one device is transmitting a logical one, or letting

the line float, and a second device is transmitting a log-

ical zero, or holding the line low, the first device can

detect that the line is not a logical one. This detection,

when used on the SCL line, is called clock stretching.

Clock stretching gives slave devices a mechanism to

control the flow of data. When this detection is used on

the SDA line, it is called arbitration. Arbitration ensures

that there is only one master device communicating at

any single time.

25.3.1 CLOCK STRETCHING

When a slave device has not completed processing

data, it can delay the transfer of more data through the

process of Clock Stretching. An addressed slave

device may hold the SCL clock line low after receiving

or sending a bit, indicating that it is not yet ready to con-

tinue. The master that is communicating with the slave

will attempt to raise the SCL line in order to transfer the

next bit, but will detect that the clock line has not yet

been released. Because the SCL connection is

open-drain, the slave has the ability to hold that line low

until it is ready to continue communicating.

Clock stretching allows receivers that cannot keep up

with a transmitter to control the flow of incoming data.

25.3.2 ARBITRATION

Each master device must monitor the bus for Start and

Stop bits. If the device detects that the bus is busy, it

cannot begin a new message until the bus returns to an

Idle state.

However, two master devices may try to initiate a trans-

mission on or about the same time. When this occurs,

the process of arbitration begins. Each transmitter

checks the level of the SDA data line and compares it

to the level that it expects to find. The first transmitter to

observe that the two levels don’t match, loses arbitra-

tion, and must stop transmitting on the SDA line.

For example, if one transmitter holds the SDA line to a

logical one (lets it float) and a second transmitter holds

it to a logical zero (pulls it low), the result is that the

SDA line will be low. The first transmitter then observes

that the level of the line is different than expected and

concludes that another transmitter is communicating.

The first transmitter to notice this difference is the one

that loses arbitration and must stop driving the SDA

line. If this transmitter is also a master device, it also

must stop driving the SCL line. It then can monitor the

lines for a Stop condition before trying to reissue its

transmission. In the meantime, the other device that

has not noticed any difference between the expected

and actual levels on the SDA line continues with its

original transmission. It can do so without any compli-

cations, because so far, the transmission appears

exactly as expected with no other transmitter disturbing

the message.

Slave Transmit mode can also be arbitrated, when a

master addresses multiple slaves, but this is less com-

mon.

If two master devices are sending a message to two dif-

ferent slave devices at the address stage, the master

sending the lower slave address always wins arbitra-

tion. When two master devices send messages to the

same slave address, and addresses can sometimes

refer to multiple slaves, the arbitration process must

continue into the data stage.

Arbitration usually occurs very rarely, but it is a neces-

sary process for proper multi-master support.

25.4 I2C Mode Operation

All MSSP1 I2C communication is byte oriented and

shifted out MSb first. Six SFR registers and 2 interrupt

flags interface the module with the PIC® microcon-

troller and user software. Two pins, SDA and SCL, are

exercised by the module to communicate with other

external I2C devices.

25.4.1 BYTE FORMAT

All communication in I2C is done in 9-bit segments. A

byte is sent from a Master to a Slave or vice-versa, fol-

lowed by an Acknowledge bit sent back. After the 8th

falling edge of the SCL line, the device outputting data

on the SDA changes that pin to an input and reads in

an acknowledge value on the next clock pulse.

The clock signal, SCL, is provided by the master. Data

is valid to change while the SCL signal is low, and

sampled on the rising edge of the clock. Changes on

the SDA line while the SCL line is high define special

conditions on the bus, explained below.

25.4.2 DEFINITION OF I2C TERMINOLOGY

There is language and terminology in the description

of I2C communication that have definitions specific to

I2C. That word usage is defined below and may be

used in the rest of this document without explana-

tion. This table was adapted from the Phillips I2C

specification.

25.4.3 SDA AND SCL PINS

Selection of any I2C mode with the SSP1EN bit set,

forces the SCL and SDA pins to be open-drain. These

pins should be set by the user to inputs by setting the

appropriate TRIS bits.

Note: Data is tied to output zero when an I2C

mode is enabled.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 257

PIC16(L)F1824/1828

25.4.4 SDA HOLD TIME

The hold time of the SDA pin is selected by the SDAHT

bit of the SSP1CON3 register. Hold time is the time

SDA is held valid after the falling edge of SCL. Setting

the SDAHT bit selects a longer 300 ns minimum hold

time and may help on buses with large capacitance.

TABLE 25-2: I2C BUS TERMS

TERM Description

Transmitter The device which shifts data out

onto the bus.

Receiver The device which shifts data in

from the bus.

Master The device that initiates a transfer,

generates clock signals and termi-

nates a transfer.

Slave The device addressed by the mas-

ter.

Multi-master A bus with more than one device

that can initiate data transfers.

Arbitration Procedure to ensure that only one

master at a time controls the bus.

Winning arbitration ensures that

the message is not corrupted.

Synchronization Procedure to synchronize the

clocks of two or more devices on

the bus.

Idle No master is controlling the bus,

and both SDA and SCL lines are

high.

Active Any time one or more master

devices are controlling the bus.

Addressed

Slave

Slave device that has received a

matching address and is actively

being clocked by a master.

Matching

Address

Address byte that is clocked into a

slave that matches the value

stored in SSP1ADD.

Write Request Slave receives a matching

address with R/W bit clear, and is

ready to clock in data.

Read Request Master sends an address byte with

the R/W bit set, indicating that it

wishes to clock data out of the

Slave. This data is the next and all

following bytes until a Restart or

Stop.

Clock Stretching When a device on the bus hold

SCL low to stall communication.

Bus Collision Any time the SDA line is sampled

low by the module while it is out-

putting and expected high state.

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DS41419C-page 258 Preliminary  2010-2011 Microchip Technology Inc.

25.4.5 START CONDITION

The I2C specification defines a Start condition as a

transition of SDA from a high to a low state while SCL

line is high. A Start condition is always generated by

the master and signifies the transition of the bus from

an Idle to an Active state. Figure 25-12 shows wave

forms for Start and Stop conditions.

A bus collision can occur on a Start condition if the

module samples the SDA line low before asserting it

low. This does not conform to the I2C Specification that

states no bus collision can occur on a Start.

25.4.6 STOP CONDITION

A Stop condition is a transition of the SDA line from

low-to-high state while the SCL line is high.

25.4.7 RESTART CONDITION

A Restart is valid any time that a Stop would be valid.

A master can issue a Restart if it wishes to hold the

bus after terminating the current transfer. A Restart

has the same effect on the slave that a Start would,

resetting all slave logic and preparing it to clock in an

address. The master may want to address the same or

another slave.

In 10-bit Addressing Slave mode a Restart is required

for the master to clock data out of the addressed

slave. Once a slave has been fully addressed, match-

ing both high and low address bytes, the master can

issue a Restart and the high address byte with the

R/W bit set. The slave logic will then hold the clock

and prepare to clock out data.

After a full match with R/W clear in 10-bit mode, a prior

match flag is set and maintained. Until a Stop condi-

tion, a high address with R/W clear, or high address

match fails.

25.4.8 START/STOP CONDITION INTERRUPT

MASKING

The SCIE and PCIE bits of the SSP1CON3 register

can enable the generation of an interrupt in Slave

modes that do not typically support this function. Slave

modes where interrupt on Start and Stop detect are

already enabled, these bits will have no effect.

FIGURE 25-12: I2C START AND STOP CONDITIONS

FIGURE 25-13: I2C RESTART CONDITION

Note: At least one SCL low time must appear

before a Stop is valid, therefore, if the SDA

line goes low then high again while the SCL

line stays high, only the Start condition is

detected.

SDA

SCL

Stop

Condition

Start

Condition

Change of

Data Allowed

Change of

Data Allowed

Restart

Condition

Change of

Data Allowed

Change of

Data Allowed

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 259

PIC16(L)F1824/1828

25.4.9 ACKNOWLEDGE SEQUENCE

The 9th SCL pulse for any transferred byte in I2C is

dedicated as an Acknowledge. It allows receiving

devices to respond back to the transmitter by pulling

the SDA line low. The transmitter must release control

of the line during this time to shift in the response. The

Acknowledge (ACK) is an active-low signal, pulling the

SDA line low indicated to the transmitter that the

device has received the transmitted data and is ready

to receive more.

The result of an ACK is placed in the ACKSTAT bit of

the SSP1CON2 register.

Slave software, when the AHEN and DHEN bits are

set, allow the user to set the ACK value sent back to

the transmitter. The ACKDT bit of the SSP1CON2 reg-

ister is set/cleared to determine the response.

Slave hardware will generate an ACK response if the

AHEN and DHEN bits of the SSP1CON3 register are

clear.

There are certain conditions where an ACK will not be

sent by the slave. If the BF bit of the SSP1STAT regis-

ter or the SSPOV bit of the SSP1CON1 register are

set when a byte is received.

When the module is addressed, after the 8th falling

edge of SCL on the bus, the ACKTIM bit of the

SSP1CON3 register is set. The ACKTIM bit indicates

the acknowledge time of the active bus. The ACKTIM

Status bit is only active when the AHEN bit or DHEN

bit is enabled.

25.5 I2C Slave Mode Operation

The MSSP1 Slave mode operates in one of four

modes selected in the SSP1M bits of SSP1CON1 reg-

ister. The modes can be divided into 7-bit and 10-bit

Addressing mode. 10-bit Addressing modes operate

the same as 7-bit with some additional overhead for

handling the larger addresses.

Modes with Start and Stop bit interrupts operate the

same as the other modes with SSP1IF additionally

getting set upon detection of a Start, Restart, or Stop

condition.

25.5.1 SLAVE MODE ADDRESSES

The SSP1ADD register (Register 25-6) contains the

Slave mode address. The first byte received after a

Start or Restart condition is compared against the

value stored in this register. If the byte matches, the

value is loaded into the SSP1BUF register and an

interrupt is generated. If the value does not match, the

module goes idle and no indication is given to the soft-

ware that anything happened.

The SSP Mask register (Register 25-5) affects the

address matching process. See Section 25.5.9

“SSP1 Mask Register” for more information.

25.5.1.1 I2C Slave 7-bit Addressing Mode

In 7-bit Addressing mode, the LSb of the received data

byte is ignored when determining if there is an address

match.

25.5.1.2 I2C Slave 10-bit Addressing Mode

In 10-bit Addressing mode, the first received byte is

compared to the binary value of ‘1 1 1 1 0 A9 A8

0’. A9 and A8 are the two MSb of the 10-bit address

and stored in bits 2 and 1 of the SSP1ADD register.

After the acknowledge of the high byte the UA bit is set

and SCL is held low until the user updates SSP1ADD

with the low address. The low address byte is clocked

in and all 8 bits are compared to the low address value

in SSP1ADD. Even if there is not an address match;

SSP1IF and UA are set, and SCL is held low until

SSP1ADD is updated to receive a high byte again.

When SSP1ADD is updated the UA bit is cleared. This

ensures the module is ready to receive the high

address byte on the next communication.

A high and low address match as a write request is

required at the start of all 10-bit addressing communi-

cation. A transmission can be initiated by issuing a

Restart once the slave is addressed, and clocking in

the high address with the R/W bit set. The slave hard-

ware will then acknowledge the read request and pre-

pare to clock out data. This is only valid for a slave

after it has received a complete high and low address

byte match.

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25.5.2 SLAVE RECEPTION

When the R/W bit of a matching received address byte

is clear, the R/W bit of the SSP1STAT register is

cleared. The received address is loaded into the

SSP1BUF register and acknowledged.

When the overflow condition exists for a received

address, then not Acknowledge is given. An overflow

condition is defined as either bit BF bit of the

SSP1STAT register is set, or bit SSPOV bit of the

SSP1CON1 register is set. The BOEN bit of the

SSP1CON3 register modifies this operation. For more

information see Register 25-4.

An MSSP1 interrupt is generated for each transferred

data byte. Flag bit, SSP1IF, must be cleared by soft-

ware.

When the SEN bit of the SSP1CON2 register is set,

SCL will be held low (clock stretch) following each

received byte. The clock must be released by setting

the CKP bit of the SSP1CON1 register, except

sometimes in 10-bit mode. See Section 25.2.3 “SPI

Master Mode” for more detail.

25.5.2.1 7-bit Addressing Reception

This section describes a standard sequence of events

for the MSSP1 module configured as an I2C Slave in

7-bit Addressing mode. Figure 25-14 and Figure 25-15

are used as a visual reference for this description.

This is a step by step process of what typically must

be done to accomplish I2C communication.

1. Start bit detected.

2. S bit of SSP1STAT is set; SSP1IF is set if inter-

rupt on Start detect is enabled.

3. Matching address with R/W bit clear is received.

4. The slave pulls SDA low sending an ACK to the

master, and sets SSP1IF bit.

5. Software clears the SSP1IF bit.

6. Software reads received address from

SSP1BUF clearing the BF flag.

7. If SEN = 1; Slave software sets CKP bit to

release the SCL line.

8. The master clocks out a data byte.

9. Slave drives SDA low sending an ACK to the

master, and sets SSP1IF bit.

10. Software clears SSP1IF.

11. Software reads the received byte from

SSP1BUF clearing BF.

12. Steps 8-12 are repeated for all received bytes

from the Master.

13. Master sends Stop condition, setting P bit of

SSP1STAT, and the bus goes idle.

25.5.2.2 7-bit Reception with AHEN and DHEN

Slave device reception with AHEN and DHEN set

operate the same as without these options with extra

interrupts and clock stretching added after the 8th fall-

ing edge of SCL. These additional interrupts allow the

slave software to decide whether it wants to ACK the

receive address or data byte, rather than the hard-

ware. This functionality adds support for PMBus™ that

was not present on previous versions of this module.

This list describes the steps that need to be taken by

slave software to use these options for I2C communi-

cation. Figure 25-16 displays a module using both

address and data holding. Figure 25-17 includes the

operation with the SEN bit of the SSP1CON2 register

set.

1. S bit of SSP1STAT is set; SSP1IF is set if inter-

rupt on Start detect is enabled.

2. Matching address with R/W bit clear is clocked

in. SSP1IF is set and CKP cleared after the 8th

falling edge of SCL.

3. Slave clears the SSP1IF.

4. Slave can look at the ACKTIM bit of the

SSP1CON3 register to determine if the SSP1IF

was after or before the ACK.

5. Slave reads the address value from SSP1BUF,

clearing the BF flag.

6. Slave sets ACK value clocked out to the master

by setting ACKDT.

7. Slave releases the clock by setting CKP.

8. SSP1IF is set after an ACK, not after a NACK.

9. If SEN = 1 the slave hardware will stretch the

clock after the ACK.

10. Slave clears SSP1IF.

11. SSP1IF set and CKP cleared after 8th falling

edge of SCL for a received data byte.

12. Slave looks at ACKTIM bit of SSP1CON3 to

determine the source of the interrupt.

13. Slave reads the received data from SSP1BUF

clearing BF.

14. Steps 7-14 are the same for each received data

byte.

15. Communication is ended by either the slave

sending an ACK =1, or the master sending a

Stop condition. If a Stop is sent and Interrupt on

Stop Detect is disabled, the slave will only know

by polling the P bit of the SSPSTAT register.

Note: SSP1IF is still set after the 9th falling edge

of SCL even if there is no clock stretching

and BF has been cleared. Only if NACK is

sent to Master is SSP1IF not set

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 261

PIC16(L)F1824/1828

FIGURE 25-14: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)

Receiving Address

ACK

Receiving Data

ACK

Receiving Data ACK =1

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDA

SCL

SSP1IF

SSPOV

12345678 12345678 12345678

999

ACK is not sent.

SSPOV set because

SSP1BUF is still full.

Cleared by software

First byte

of data is

available

in SSP1BUF

SSP1BUF is read

SSP1IF set on 9th

falling edge of

SCL

Cleared by software

Bus Master sends

Stop condition

From Slave to Master

PIC16(L)F1824/1828

DS41419C-page 262 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 25-15: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)

SEN SEN

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0SDA

SCL 123456789 123456789 123456789 P

SSP1IF set on 9th

SCL is not held

CKP is written to 1 in software,

CKP is written to ‘1’ in software,

ACK

low because

falling edge of SCL

releasing SCL

ACK is not sent.

Bus Master sends

CKP

SSPOV

SSP1IF

SSPOV set because

SSP1BUF is still full.

Cleared by software

First byte

of data is

available

in SSP1BUF

ACK=1

Cleared by software

SSP1BUF is read

Clock is held low until CKP is set to ‘1’

releasing SCL

Stop condition

ACK

Receive Address Receive Data Receive Data

R/W=0

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 263

PIC16(L)F1824/1828

FIGURE 25-16: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)

Receiving Address Receiving Data Received Data

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDA

SCL

CKP

12 3 456 7 8 912345678 9

12345678

Master sends

Stop condition

Data is read from SSP1BUF

Cleared by software

SSP1IF is set on

9th falling edge of

SCL, after ACK

CKP set by software,

SCL is released

Slave software

ACKTIM cleared by

hardware in 9th

rising edge of SCL

sets ACKDT to

not ACK

When DHEN=1:

CKP is cleared by

hardware on 8th falling

edge of SCL

Slave software

clears ACKDT to

ACK the received

byte

ACKTIM set by hardware

on 8th falling edge of SCL

When AHEN=1:

CKP is cleared by hardware

and SCL is stretched

Address is

read from

SSBUF

ACKTIM set by hardware

on 8th falling edge of SCL

ACK

Master Releases SDA

to slave for ACK sequence

No interrupt

after not ACK

from Slave

ACK=1

ACK

ACKDT

ACKTIM

SSP1IF

If AHEN = 1:

SSP1IF is set

PIC16(L)F1824/1828

DS41419C-page 264 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 25-17: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)

Receiving Address Receive Data Receive Data

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDA

SCL

SSP1IF

ACKDT

CKP

ACK

S12

345678 912

34567 8 9 1234567 8 9

ACK

Cleared by software

ACKTIM is cleared by hardware

SSP1BUF can be

Set by software,

read any time before

next byte is loaded

release SCL

on 9th rising edge of SCL

Received

address is loaded into

SSP1BUF

Slave software clears

ACKDT to ACK

R/W = 0Master releases

SDA to slave for ACK sequence

the received byte

When AHEN = 1;

on the 8th falling edge

of SCL of an address

byte, CKP is cleared

ACKTIM is set by hardware

on 8th falling edge of SCL

When DHEN = 1;

on the 8th falling edge

of SCL of a received

data byte, CKP is cleared

Received data is

available on SSP1BUF

Slave sends

not ACK

CKP is not cleared

if not ACK

Master sends

Stop condition

No interrupt after

if not ACK

from Slave

ACKTIM

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 265

PIC16(L)F1824/1828

25.5.3 SLAVE TRANSMISSION

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSP1STAT register is set. The received address is

loaded into the SSP1BUF register, and an ACK pulse

is sent by the slave on the ninth bit.

Following the ACK, slave hardware clears the CKP bit

and the SCL pin is held low (see Section 25.5.6

“Clock Stretching” for more detail). By stretching the

clock, the master will be unable to assert another clock

pulse until the slave is done preparing the transmit

data.

The transmit data must be loaded into the SSP1BUF

the SCL pin should be released by setting the CKP bit

of the SSP1CON1 register. The eight data bits are

shifted out on the falling edge of the SCL input. This

ensures that the SDA signal is valid during the SCL

high time.

The ACK pulse from the master-receiver is latched on

the rising edge of the ninth SCL input pulse. This ACK

value is copied to the ACKSTAT bit of the SSP1CON2

transfer is complete. In this case, when the not ACK is

latched by the slave, the slave goes idle and waits for

another occurrence of the Start bit. If the SDA line was

low (ACK), the next transmit data must be loaded into

the SSP1BUF register. Again, the SCL pin must be

released by setting bit CKP.

An MSSP1 interrupt is generated for each data transfer

byte. The SSP1IF bit must be cleared by software and

the SSP1STAT register is used to determine the status

of the byte. The SSP1IF bit is set on the falling edge of

the ninth clock pulse.

25.5.3.1 Slave Mode Bus Collision

A slave receives a read request and begins shifting

data out on the SDA line. If a bus collision is detected

and the SBCDE bit of the SSP1CON3 register is set,

the BCL1IF bit of the PIRx register is set. Once a bus

collision is detected, the slave goes Idle and waits to be

addressed again. User software can use the BCL1IF bit

to handle a slave bus collision.

25.5.3.2 7-bit Transmission

A master device can transmit a read request to a

slave, and then clock data out of the slave. The list

below outlines what software for a slave will need to

do to accomplish a standard transmission.

Figure 25-17 can be used as a reference to this list.

1. Master sends a Start condition on SDA and

SCL.

2. S bit of SSP1STAT is set; SSP1IF is set if inter-

rupt on Start detect is enabled.

3. Matching address with R/W bit set is received by

the Slave setting SSP1IF bit.

4. Slave hardware generates an ACK and sets

SSP1IF.

5. SSP1IF bit is cleared by user.

6. Software reads the received address from

SSP1BUF, clearing BF.

7. R/W is set so CKP was automatically cleared

after the ACK.

8. The slave software loads the transmit data into

SSP1BUF.

9. CKP bit is set releasing SCL, allowing the mas-

ter to clock the data out of the slave.

10. SSP1IF is set after the ACK response from the

master is loaded into the ACKSTAT register.

11. SSP1IF bit is cleared.

12. The slave software checks the ACKSTAT bit to

see if the master wants to clock out more data.

13. Steps 9-13 are repeated for each transmitted

byte.

14. If the master sends a not ACK; the clock is not

held, but SSP1IF is still set.

15. The master sends a Restart condition or a Stop.

16. The slave is no longer addressed.

Note 1: If the master ACKs the clock will be

stretched.

2: ACKSTAT is the only bit updated on the

rising edge of SCL (9th) rather than the

falling.

PIC16(L)F1824/1828

DS41419C-page 266 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 25-18: I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)

Receiving Address Automatic Transmitting Data Automatic Transmitting Data

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

SDA

SCL

SSP1IF

CKP

ACKSTAT

R/W

D/A

Received address

When R/W is set

R/W is copied from the

Indicates an address

is read from SSP1BUF

SCL is always

held low after 9th SCL

falling edge

matching address byte

has been received

Masters not ACK

is copied to

ACKSTAT

CKP is not

held for not

ACK

BF is automatically

cleared after 8th falling

edge of SCL

Data to transmit is

loaded into SSP1BUF

Set by software

Cleared by software

ACK

R/W = 1

Master sends

Stop condition

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 267

PIC16(L)F1824/1828

25.5.3.3 7-bit Transmission with Address

Hold Enabled

Setting the AHEN bit of the SSP1CON3 register

enables additional clock stretching and interrupt gen-

eration after the 8th falling edge of a received match-

ing address. Once a matching address has been

clocked in, CKP is cleared and the SSP1IF interrupt is

set.

Figure 25-18 displays a standard waveform of a 7-bit

Address Slave Transmission with AHEN enabled.

1. Bus starts Idle.

2. Master sends Start condition; the S bit of

SSP1STAT is set; SSP1IF is set if interrupt on

Start detect is enabled.

3. Master sends matching address with R/W bit

set. After the 8th falling edge of the SCL line the

CKP bit is cleared and SSP1IF interrupt is gen-

erated.

4. Slave software clears SSP1IF.

5. Slave software reads ACKTIM bit of SSP1CON3

6. Slave reads the address value from the

SSP1BUF register clearing the BF bit.

7. Slave software decides from this information if it

wishes to ACK or not ACK and sets ACKDT bit

of the SSP1CON2 register accordingly.

8. Slave sets the CKP bit releasing SCL.

9. Master clocks in the ACK value from the slave.

10. Slave hardware automatically clears the CKP bit

and sets SSP1IF after the ACK if the R/W bit is

set.

11. Slave software clears SSP1IF.

12. Slave loads value to transmit to the master into

SSP1BUF setting the BF bit.

13. Slave sets CKP bit releasing the clock.

14. Master clocks out the data from the slave and

sends an ACK value on the 9th SCL pulse.

15. Slave hardware copies the ACK value into the

ACKSTAT bit of the SSP1CON2 register.

16. Steps 10-15 are repeated for each byte transmit-

ted to the master from the slave.

17. If the master sends a not ACK the slave

releases the bus allowing the master to send a

Stop and end the communication.

Note: SSP1BUF cannot be loaded until after the

ACK.

Note: Master must send a not ACK on the last byte

to ensure that the slave releases the SCL

line to receive a Stop.

PIC16(L)F1824/1828

DS41419C-page 268 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 25-19: I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)

Receiving Address Automatic Transmitting Data Automatic Transmitting Data

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

SDA

SCL

SSP1IF

ACKDT

ACKSTAT

CKP

R/W

D/A

Received address

is read from SSP1BUF

BF is automatically

cleared after 8th falling

edge of SCL

Data to transmit is

loaded into SSP1BUF

Cleared by software

Slave clears

ACKDT to ACK

address

Master’s ACK

response is copied

to SSP1STAT

CKP not cleared

after not ACK

Set by software,

releases SCL

ACKTIM is cleared

on 9th rising edge of SCL

ACKTIM is set on 8th falling

edge of SCL

When AHEN = 1;

CKP is cleared by hardware

after receiving matching

address.

When R/W = 1;

CKP is always

cleared after ACK

Master sends

Stop condition

ACK

R/W = 1

Master releases SDA

to slave for ACK sequence

ACK

ACKTIM

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 269

PIC16(L)F1824/1828

25.5.4 SLAVE MODE 10-BIT ADDRESS

RECEPTION

This section describes a standard sequence of events

for the MSSP1 module configured as an I2C Slave in

10-bit Addressing mode.

Figure 25-19 is used as a visual reference for this

description.

This is a step by step process of what must be done by

slave software to accomplish I2C communication.

1. Bus starts Idle.

2. Master sends Start condition; S bit of

SSP1STAT is set; SSP1IF is set if interrupt on

Start detect is enabled.

3. Master sends matching high address with R/W

bit clear; UA bit of the SSP1STAT register is set.

4. Slave sends ACK and SSP1IF is set.

5. Software clears the SSP1IF bit.

6. Software reads received address from

SSP1BUF clearing the BF flag.

7. Slave loads low address into SSP1ADD,

releasing SCL.

8. Master sends matching low address byte to the

Slave; UA bit is set.

9. Slave sends ACK and SSP1IF is set.

10. Slave clears SSP1IF.

11. Slave reads the received matching address

from SSP1BUF clearing BF.

12. Slave loads high address into SSP1ADD.

13. Master clocks a data byte to the slave and

clocks out the slaves ACK on the 9th SCL pulse;

SSP1IF is set.

14. If SEN bit of SSP1CON2 is set, CKP is cleared

by hardware and the clock is stretched.

15. Slave clears SSP1IF.

16. Slave reads the received byte from SSP1BUF

clearing BF.

17. If SEN is set the slave sets CKP to release the

SCL.

18. Steps 13-17 repeat for each received byte.

19. Master sends Stop to end the transmission.

25.5.5 10-BIT ADDRESSING WITH ADDRESS

OR DATA HOLD

Reception using 10-bit addressing with AHEN or

DHEN set is the same as with 7-bit modes. The only

difference is the need to update the SSP1ADD register

using the UA bit. All functionality, specifically when the

CKP bit is cleared and SCL line is held low are the

same. Figure 25-20 can be used as a reference of a

slave in 10-bit addressing with AHEN set.

Figure 25-21 shows a standard waveform for a slave

transmitter in 10-bit Addressing mode.

Note: Updates to the SSP1ADD register are not

allowed until after the ACK sequence.

Note: If the low address does not match, SSP1IF

and UA are still set so that the slave soft-

ware can set SSP1ADD back to the high

address. BF is not set because there is no

match. CKP is unaffected.

PIC16(L)F1824/1828

DS41419C-page 270 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 25-20: I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)

SSP1IF

Receive First Address Byte

ACK

Receive Second Address Byte

ACK

Receive Data

ACK

Receive Data

ACK

11110

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDA

SCL

CKP

12345678912345678

912345678

9123456789P

Master sends

Stop condition

Cleared by software

Receive address is

Software updates SSP1ADD

Data is read

SCL is held low

Set by software,

while CKP =

from SSP1BUF

releasing SCL

When SEN =

;

CKP is cleared after

9th falling edge of received byte

read from SSP1BUF

and releases SCL

When UA =

;

If address matches

Set by hardware

on 9th falling edge

SSP1ADD it is loaded into

SSP1BUF

SCL is held low

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 271

PIC16(L)F1824/1828

FIGURE 25-21: I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)

Receive First Address Byte

Receive Second Address Byte

Receive Data

ACK

Receive Data

1 1 1 1 0

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5SDA

SCL

SSP1IF

ACKDT

CKP

ACKTIM

12345678 9

ACK

12345678 91234567891

SSP1BUF

is read from

Received data

SSP1BUF can be

read anytime before

the next received byte

Cleared by software

falling edge of SCL

not allowed until 9th

Update to SSP1ADD is

Set CKP with software

releases SCL

SCL

clears UA and releases

Update of SSP1ADD,

Set by hardware

on 9th falling edge

Slave software clears

ACKDT to ACK

the received byte

If when AHEN = 1;

on the 8th falling edge

of SCL of an address

byte, CKP is cleared

ACKTIM is set by hardware

on 8th falling edge of SCL

Cleared by software

R/W = 0

PIC16(L)F1824/1828

DS41419C-page 272 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 25-22: I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)

Receiving Address

ACK

Receiving Second Address Byte

Receive First Address Byte

ACK

Transmitting Data Byte

1 1 1 1 0

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 1 1 1 0

A9 A8 D7 D6 D5 D4 D3 D2 D1 D0SDA

SCL

SSP1IF

CKP

R/W

D/A

123456789 123456789 1234 56789 123456789

ACK = 1

Master sends

Stop condition

Master sends

not ACK

Master sends

Restart event

ACK

R/W = 0

Cleared by software

After SSP1ADD is

updated, UA is cleared

and SCL is released

High address is loaded

Received address is Data to transmit is

Set by software

Indicates an address

When R/W = 1;

R/W is copied from the

Set by hardware

UA indicates SSP1ADD

SSP1BUF loaded

with received address

must be updated

has been received

loaded into SSP1BUF

releases SCL

Masters not ACK

is copied

matching address byte

CKP is cleared on

9th falling edge of SCL

read from SSP1BUF

back into SSP1ADD

ACKSTAT

Set by hardware

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 273

PIC16(L)F1824/1828

25.5.6 CLOCK STRETCHING

Clock stretching occurs when a device on the bus

holds the SCL line low effectively pausing communica-

tion. The slave may stretch the clock to allow more

time to handle data or prepare a response for the mas-

ter device. A master device is not concerned with

stretching as anytime it is active on the bus and not

transferring data it is stretching. Any stretching done

by a slave is invisible to the master software and han-

dled by the hardware that generates SCL.

The CKP bit of the SSP1CON1 register is used to con-

trol stretching in software. Any time the CKP bit is

cleared, the module will wait for the SCL line to go low

and then hold it. Setting CKP will release SCL and

allow more communication.

25.5.6.1 Normal Clock Stretching

Following an ACK if the R/W bit of SSP1STAT is set, a

read request, the slave hardware will clear CKP. This

allows the slave time to update SSP1BUF with data to

transfer to the master. If the SEN bit of SSP1CON2 is

set, the slave hardware will always stretch the clock

after the ACK sequence. Once the slave is ready; CKP

is set by software and communication resumes.

25.5.6.2 10-bit Addressing Mode

In 10-bit Addressing mode, when the UA bit is set, the

clock is always stretched. This is the only time the SCL

is stretched without CKP being cleared. SCL is

released immediately after a write to SSP1ADD.

25.5.6.3 Byte NACKing

When AHEN bit of SSP1CON3 is set; CKP is cleared

by hardware after the 8th falling edge of SCL for a

received matching address byte. When DHEN bit of

SSP1CON3 is set; CKP is cleared after the 8th falling

edge of SCL for received data.

Stretching after the 8th falling edge of SCL allows the

slave to look at the received address or data and

decide if it wants to ACK the received data.

25.5.7 CLOCK SYNCHRONIZATION AND

THE CKP BIT

Any time the CKP bit is cleared, the module will wait

for the SCL line to go low and then hold it. However,

clearing the CKP bit will not assert the SCL output low

until the SCL output is already sampled low. There-

fore, the CKP bit will not assert the SCL line until an

external I2C master device has already asserted the

SCL line. The SCL output will remain low until the CKP

bit is set and all other devices on the I2C bus have

released SCL. This ensures that a write to the CKP bit

will not violate the minimum high time requirement for

SCL (see Figure 25-22).

FIGURE 25-23: CLOCK SYNCHRONIZATION TIMING

Note 1: The BF bit has no effect on if the clock will

be stretched or not. This is different than

previous versions of the module that

would not stretch the clock, clear CKP, if

SSP1BUF was read before the 9th falling

edge of SCL.

2: Previous versions of the module did not

stretch the clock for a transmission if

SSP1BUF was loaded before the 9th fall-

ing edge of SCL. It is now always cleared

for read requests.

Note: Previous versions of the module did not

stretch the clock if the second address byte

did not match.

SDA

SCL

DX ‚ – 1DX

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SSP1CON1

CKP

Master device

releases clock

Master device

asserts clock

PIC16(L)F1824/1828

DS41419C-page 274 Preliminary  2010-2011 Microchip Technology Inc.

25.5.8 GENERAL CALL ADDRESS SUPPORT

The addressing procedure for the I2C bus is such that

the first byte after the Start condition usually deter-

mines which device will be the slave addressed by the

master device. The exception is the general call

address which can address all devices. When this

address is used, all devices should, in theory, respond

with an acknowledge.

The general call address is a reserved address in the

I2C protocol, defined as address 0x00. When the

GCEN bit of the SSP1CON2 register is set, the slave

module will automatically ACK the reception of this

address regardless of the value stored in SSP1ADD.

After the slave clocks in an address of all zeros with

the R/W bit clear, an interrupt is generated and slave

software can read SSP1BUF and respond.

Figure 25-23 shows a general call reception

sequence.

In 10-bit Address mode, the UA bit will not be set on

the reception of the general call address. The slave

will prepare to receive the second byte as data, just as

it would in 7-bit mode.

If the AHEN bit of the SSP1CON3 register is set, just

as with any other address reception, the slave hard-

ware will stretch the clock after the 8th falling edge of

SCL. The slave must then set its ACKDT value and

release the clock with communication progressing as it

would normally.

FIGURE 25-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

25.5.9 SSP1 MASK REGISTER

An SSP1 Mask (SSP1MSK) register (Register 25-5) is

available in I2C Slave mode as a mask for the value

held in the SSP1SR register during an address

comparison operation. A zero (‘0’) bit in the SSP1MSK

of the received address a “don’t care.”

This register is reset to all ‘1’s upon any Reset

condition and, therefore, has no effect on standard

SSP1 operation until written with a mask value.

The SSP1 Mask register is active during:

• 7-bit Address mode: address compare of A<7:1>.

• 10-bit Address mode: address compare of A<7:0>

only. The SSP1 mask has no effect during the

reception of the first (high) byte of the address.

SDA

SCL

SSP1IF

BF (SSP1STAT<0>)

Cleared by software

SSP1BUF is read

R/W = 0

ACK

General Call Address

Address is compared to General Call Address

Receiving Data ACK

123456789123456789

D7 D6 D5 D4 D3 D2 D1 D0

after ACK, set interrupt

GCEN (SSP1CON2<7>)

’1’

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 275

PIC16(L)F1824/1828

25.6 I2C Master Mode

Master mode is enabled by setting and clearing the

appropriate SSP1M bits in the SSP1CON1 register and

by setting the SSP1EN bit. In Master mode, the SCL

and SDA lines are set as inputs and are manipulated by

the MSSP1 hardware.

Master mode of operation is supported by interrupt

generation on the detection of the Start and Stop con-

ditions. The Stop (P) and Start (S) bits are cleared from

a Reset or when the MSSP1 module is disabled. Con-

trol of the I2C bus may be taken when the P bit is set,

or the bus is Idle.

In Firmware Controlled Master mode, user code

conducts all I2C bus operations based on Start and

Stop bit condition detection. Start and Stop condition

detection is the only active circuitry in this mode. All

other communication is done by the user software

directly manipulating the SDA and SCL lines.

The following events will cause the SSP1 Interrupt Flag

bit, SSP1IF, to be set (SSP1 interrupt, if enabled):

• Start condition detected

• Stop condition detected

• Data transfer byte transmitted/received

• Acknowledge transmitted/received

• Repeated Start generated

25.6.1 I2C MASTER MODE OPERATION

The master device generates all of the serial clock

pulses and the Start and Stop conditions. A transfer is

ended with a Stop condition or with a Repeated Start

condition. Since the Repeated Start condition is also

the beginning of the next serial transfer, the I2C bus will

not be released.

In Master Transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (7 bits) and the Read/Write (R/W) bit.

In this case, the R/W bit will be logic ‘0’. Serial data is

transmitted 8 bits at a time. After each byte is transmit-

ted, an Acknowledge bit is received. Start and Stop

conditions are output to indicate the beginning and the

end of a serial transfer.

In Master Receive mode, the first byte transmitted con-

tains the slave address of the transmitting device

(7 bits) and the R/W bit. In this case, the R/W bit will be

logic ‘1’. Thus, the first byte transmitted is a 7-bit slave

address followed by a ‘1’ to indicate the receive bit.

Serial data is received via SDA, while SCL outputs the

serial clock. Serial data is received 8 bits at a time. After

each byte is received, an Acknowledge bit is transmit-

ted. Start and Stop conditions indicate the beginning

and end of transmission.

A Baud Rate Generator is used to set the clock fre-

quency output on SCL. See Section 25.7 “Baud Rate

Generator” for more detail.

Note 1: The MSSP1 module, when configured in

I2C Master mode, does not allow queue-

ing of events. For instance, the user is not

allowed to initiate a Start condition and

immediately write the SSP1BUF register

to initiate transmission before the Start

condition is complete. In this case, the

SSP1BUF will not be written to and the

WCOL bit will be set, indicating that a

write to the SSP1BUF did not occur

2: When in Master mode, Start/Stop detec-

tion is masked and an interrupt is gener-

ated when the SEN/PEN bit is cleared and

the generation is complete.

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25.6.2 CLOCK ARBITRATION

Clock arbitration occurs when the master, during any

receive, transmit or Repeated Start/Stop condition,

releases the SCL pin (SCL allowed to float high). When

the SCL pin is allowed to float high, the Baud Rate Gen-

erator (BRG) is suspended from counting until the SCL

pin is actually sampled high. When the SCL pin is sam-

pled high, the Baud Rate Generator is reloaded with

the contents of SSP1ADD<7:0> and begins counting.

This ensures that the SCL high time will always be at

least one BRG rollover count in the event that the clock

is held low by an external device (Figure 25-25).

FIGURE 25-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

25.6.3 WCOL STATUS FLAG

If the user writes the SSP1BUF when a Start, Restart,

Stop, Receive or Transmit sequence is in progress, the

WCOL is set and the contents of the buffer are

unchanged (the write doesn’t occur). Any time the

WCOL bit is set it indicates that an action on SSP1BUF

was attempted while the module was not Idle.

SDA

SCL

SCL deasserted but slave holds

DX ‚ – 1DX

BRG

SCL is sampled high, reload takes

place and BRG starts its count

03h 02h 01h 00h (hold off) 03h 02h

Reload

BRG

Value

SCL low (clock arbitration)

SCL allowed to transition high

BRG decrements on

Q2 and Q4 cycles

Note: Because queueing of events is not

allowed, writing to the lower 5 bits of

SSP1CON2 is disabled until the Start

condition is complete.

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25.6.4 I2C MASTER MODE START

CONDITION TIMING

To initiate a Start condition, the user sets the Start

Enable bit, SEN bit of the SSP1CON2 register. If the

SDA and SCL pins are sampled high, the Baud Rate

Generator is reloaded with the contents of

SSP1ADD<7:0> and starts its count. If SCL and SDA

are both sampled high when the Baud Rate Generator

times out (TBRG), the SDA pin is driven low. The action

of the SDA being driven low while SCL is high is the

Start condition and causes the S bit of the SSP1STAT1

erator is reloaded with the contents of SSP1ADD<7:0>

and resumes its count. When the Baud Rate Genera-

tor times out (TBRG), the SEN bit of the SSP1CON2

Baud Rate Generator is suspended, leaving the SDA

line held low and the Start condition is complete.

FIGURE 25-26: FIRST START BIT TIMING

Note 1: If at the beginning of the Start condition,

the SDA and SCL pins are already sam-

pled low, or if during the Start condition,

the SCL line is sampled low before the

SDA line is driven low, a bus collision

occurs, the Bus Collision Interrupt Flag,

BCL1IF, is set, the Start condition is

aborted and the I2C module is reset into

its Idle state.

2: The Philips I2C Specification states that a

bus collision cannot occur on a Start.

SDA

SCL

TBRG

1st bit 2nd bit

TBRG

SDA = 1, At completion of Start bit,

SCL = 1

Write to SSP1BUF occurs here

TBRG

hardware clears SEN bit

TBRG

Write to SEN bit occurs here Set S bit (SSP1STAT<3>)

and sets SSP1IF bit

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25.6.5 I2C MASTER MODE REPEATED

START CONDITION TIMING

A Repeated Start condition occurs when the RSEN bit

of the SSP1CON2 register is programmed high and the

Master state machine is no longer active. When the

RSEN bit is set, the SCL pin is asserted low. When the

SCL pin is sampled low, the Baud Rate Generator is

loaded and begins counting. The SDA pin is released

(brought high) for one Baud Rate Generator count

(TBRG). When the Baud Rate Generator times out, if

SDA is sampled high, the SCL pin will be deasserted

(brought high). When SCL is sampled high, the Baud

Rate Generator is reloaded and begins counting. SDA

and SCL must be sampled high for one TBRG. This

action is then followed by assertion of the SDA pin

(SDA = 0) for one TBRG while SCL is high. SCL is

asserted low. Following this, the RSEN bit of the

SSP1CON2 register will be automatically cleared and

the Baud Rate Generator will not be reloaded, leaving

the SDA pin held low. As soon as a Start condition is

detected on the SDA and SCL pins, the S bit of the

SSP1STAT register will be set. The SSP1IF bit will not

be set until the Baud Rate Generator has timed out.

FIGURE 25-27: REPEAT START CONDITION WAVEFORM

Note 1: If RSEN is programmed while any other

event is in progress, it will not take effect.

2: A bus collision during the Repeated Start

condition occurs if:

• SDA is sampled low when SCL

goes from low-to-high.

• SCL goes low before SDA is

asserted low. This may indicate

that another master is attempting to

transmit a data ‘1’.

SDA

SCL

Repeated Start

Write to SSP1CON2

Write to SSP1BUF occurs here

At completion of Start bit,

hardware clears RSEN bit

1st bit

S bit set by hardware

TBRG

SDA = 1,SDA = 1,

SCL (no change) SCL = 1

occurs here

TBRG TBRG TBRG

and sets SSP1IF

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25.6.6 I2C MASTER MODE TRANSMISSION

Transmission of a data byte, a 7-bit address or the

other half of a 10-bit address is accomplished by simply

writing a value to the SSP1BUF register. This action will

set the Buffer Full flag bit, BF and allow the Baud Rate

Generator to begin counting and start the next trans-

mission. Each bit of address/data will be shifted out

onto the SDA pin after the falling edge of SCL is

asserted. SCL is held low for one Baud Rate Generator

rollover count (TBRG). Data should be valid before SCL

is released high. When the SCL pin is released high, it

is held that way for TBRG. The data on the SDA pin

must remain stable for that duration and some hold

time after the next falling edge of SCL. After the eighth

bit is shifted out (the falling edge of the eighth clock),

the BF flag is cleared and the master releases SDA.

This allows the slave device being addressed to

respond with an ACK bit during the ninth bit time if an

address match occurred, or if data was received prop-

erly. The status of ACK is written into the ACKSTAT bit

on the rising edge of the ninth clock. If the master

receives an Acknowledge, the Acknowledge Status bit,

ACKSTAT, is cleared. If not, the bit is set. After the ninth

clock, the SSP1IF bit is set and the master clock (Baud

Rate Generator) is suspended until the next data byte

is loaded into the SSP1BUF, leaving SCL low and SDA

unchanged (Figure 25-27).

After the write to the SSP1BUF, each bit of the address

will be shifted out on the falling edge of SCL until all

seven address bits and the R/W bit are completed. On

the falling edge of the eighth clock, the master will

release the SDA pin, allowing the slave to respond with

an Acknowledge. On the falling edge of the ninth clock,

the master will sample the SDA pin to see if the address

was recognized by a slave. The status of the ACK bit is

loaded into the ACKSTAT Status bit of the SSP1CON2

transmission of the address, the SSP1IF is set, the BF

flag is cleared and the Baud Rate Generator is turned

off until another write to the SSP1BUF takes place,

holding SCL low and allowing SDA to float.

25.6.6.1 BF Status Flag

In Transmit mode, the BF bit of the SSP1STAT register

is set when the CPU writes to SSP1BUF and is cleared

when all 8 bits are shifted out.

25.6.6.2 WCOL Status Flag

If the user writes the SSP1BUF when a transmit is

already in progress (i.e., SSP1SR is still shifting out a

data byte), the WCOL bit is set and the contents of the

buffer are unchanged (the write doesn’t occur).

WCOL must be cleared by software before the next

transmission.

25.6.6.3 ACKSTAT Status Flag

In Transmit mode, the ACKSTAT bit of the SSP1CON2

edge (ACK =0) and is set when the slave does not

Acknowledge (ACK =1). A slave sends an Acknowl-

edge when it has recognized its address (including a

general call), or when the slave has properly received

its data.

25.6.6.4 Typical transmit sequence:

1. The user generates a Start condition by setting

the SEN bit of the SSP1CON2 register.

2. SSP1IF is set by hardware on completion of the

Start.

3. SSP1IF is cleared by software.

4. The MSSP1 module will wait the required start

time before any other operation takes place.

5. The user loads the SSP1BUF with the slave

address to transmit.

6. Address is shifted out the SDA pin until all 8 bits

are transmitted. Transmission begins as soon

as SSP1BUF is written to.

7. The MSSP1 module shifts in the ACK bit from

the slave device and writes its value into the

ACKSTAT bit of the SSP1CON2 register.

8. The MSSP1 module generates an interrupt at

the end of the ninth clock cycle by setting the

SSP1IF bit.

9. The user loads the SSP1BUF with eight bits of

data.

10. Data is shifted out the SDA pin until all 8 bits are

transmitted.

11. The MSSP1 module shifts in the ACK bit from

the slave device and writes its value into the

ACKSTAT bit of the SSP1CON2 register.

12. Steps 8-11 are repeated for all transmitted data

bytes.

13. The user generates a Stop or Restart condition

by setting the PEN or RSEN bits of the

SSP1CON2 register. Interrupt is generated

once the Stop/Restart condition is complete.

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FIGURE 25-28: I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)

SDA

SCL

SSP1IF

BF (SSP1STAT<0>)

SEN

A7 A6 A5 A4 A3 A2 A1 ACK = 0D7 D6 D5 D4 D3 D2 D1 D0

ACK

Transmitting Data or Second Half

R/W = 0Transmit Address to Slave

123456789 123456789 P

Cleared by software service routine

SSP1BUF is written by software

from SSP1 interrupt

After Start condition, SEN cleared by hardware

SSP1BUF written with 7-bit address and R/W

start transmit

SCL held low

while CPU

responds to SSP1IF

SEN = 0

of 10-bit Address

Write SSP1CON2<0> SEN = 1

Start condition begins From slave, clear ACKSTAT bit SSP1CON2<6>

ACKSTAT in

SSP1CON2 = 1

Cleared by software

SSP1BUF written

PEN

R/W

Cleared by software

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25.6.7 I2C MASTER MODE RECEPTION

Master mode reception is enabled by programming the

Receive Enable bit, RCEN bit of the SSP1CON2

The Baud Rate Generator begins counting and on each

rollover, the state of the SCL pin changes

(high-to-low/low-to-high) and data is shifted into the

SSP1SR. After the falling edge of the eighth clock, the

receive enable flag is automatically cleared, the con-

tents of the SSP1SR are loaded into the SSP1BUF, the

BF flag bit is set, the SSP1IF flag bit is set and the Baud

Rate Generator is suspended from counting, holding

SCL low. The MSSP1 is now in Idle state awaiting the

next command. When the buffer is read by the CPU,

the BF flag bit is automatically cleared. The user can

then send an Acknowledge bit at the end of reception

by setting the Acknowledge Sequence Enable, ACKEN

bit of the SSP1CON2 register.

25.6.7.1 BF Status Flag

In receive operation, the BF bit is set when an address

or data byte is loaded into SSP1BUF from SSP1SR. It

is cleared when the SSP1BUF register is read.

25.6.7.2 SSPOV Status Flag

In receive operation, the SSPOV bit is set when 8 bits

are received into the SSP1SR and the BF flag bit is

already set from a previous reception.

25.6.7.3 WCOL Status Flag

If the user writes the SSP1BUF when a receive is

already in progress (i.e., SSP1SR is still shifting in a

data byte), the WCOL bit is set and the contents of the

buffer are unchanged (the write doesn’t occur).

25.6.7.4 Typical Receive Sequence:

1. The user generates a Start condition by setting

the SEN bit of the SSP1CON2 register.

2. SSP1IF is set by hardware on completion of the

Start.

3. SSP1IF is cleared by software.

4. User writes SSP1BUF with the slave address to

transmit and the R/W bit set.

5. Address is shifted out the SDA pin until all 8 bits

are transmitted. Transmission begins as soon

as SSP1BUF is written to.

6. The MSSP1 module shifts in the ACK bit from

the slave device and writes its value into the

ACKSTAT bit of the SSP1CON2 register.

7. The MSSP1 module generates an interrupt at

the end of the ninth clock cycle by setting the

SSP1IF bit.

8. User sets the RCEN bit of the SSP1CON2 regis-

ter and the master clocks in a byte from the slave.

9. After the 8th falling edge of SCL, SSP1IF and

BF are set.

10. Master clears SSP1IF and reads the received

byte from SSP1UF, clears BF.

11. Master sets ACK value sent to slave in ACKDT

bit of the SSP1CON2 register and initiates the

ACK by setting the ACKEN bit.

12. Masters ACK is clocked out to the slave and

SSP1IF is set.

13. User clears SSP1IF.

14. Steps 8-13 are repeated for each received byte

from the slave.

15. Master sends a not ACK or Stop to end

communication.

Note: The MSSP1 module must be in an Idle

state before the RCEN bit is set or the

RCEN bit will be disregarded.

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FIGURE 25-29: I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)

D3D4

D6D7

A7 A6 A5 A4 A3 A2 A1

SDA

SCL 12345678912345678 9 1234

Bus master

terminates

transfer

ACK

Receiving Data from Slave

D3D4

D6D7

ACK

R/W = 1

Transmit Address to Slave

SSP1IF

ACK is not sent

Write to SSP1CON2<0>(SEN = 1),

Write to SSP1BUF occurs here, ACK from Slave

Master configured as a receiver

by programming SSP1CON2<3> (RCEN = 1)

PEN bit = 1

written here

Data shifted in on falling edge of CLK

Cleared by software

start XMIT

SEN = 0

SSPOV

SDA = 0, SCL = 1

while CPU

(SSP1STAT<0>)

ACK

Cleared by software

Set SSP1IF interrupt

at end of receive

Set P bit

(SSP1STAT<4>)

and SSP1IF

Cleared in

software

ACK from Master

Set SSP1IF at end

Set SSP1IF interrupt

at end of Acknowledge

sequence

Set SSP1IF interrupt

at end of Acknow-

ledge sequence

of receive

Set ACKEN, start Acknowledge sequence

SSPOV is set because

SSP1BUF is still full

SDA = ACKDT = 1

RCEN cleared

automatically

RCEN = 1, start

next receive

Write to SSP1CON2<4>

to start Acknowledge sequence

SDA = ACKDT (SSP1CON2<5>) = 0

RCEN cleared

automatically

responds to SSP1IF

ACKEN

begin Start condition

Cleared by software

SDA = ACKDT = 0

Last bit is shifted into SSP1SR and

contents are unloaded into SSP1BUF

RCEN

Master configured as a receiver

by programming SSP1CON2<3> (RCEN = 1)

RCEN cleared

automatically

ACK from Master

SDA\ = ACKDT = 0 RCEN cleared

automatically

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25.6.8 ACKNOWLEDGE SEQUENCE

TIMING

An Acknowledge sequence is enabled by setting the

Acknowledge Sequence Enable bit, ACKEN bit of the

SSP1CON2 register. When this bit is set, the SCL pin is

pulled low and the contents of the Acknowledge data bit

are presented on the SDA pin. If the user wishes to gen-

erate an Acknowledge, then the ACKDT bit should be

cleared. If not, the user should set the ACKDT bit before

starting an Acknowledge sequence. The Baud Rate

Generator then counts for one rollover period (TBRG)

and the SCL pin is deasserted (pulled high). When the

SCL pin is sampled high (clock arbitration), the Baud

Rate Generator counts for TBRG. The SCL pin is then

pulled low. Following this, the ACKEN bit is automatically

cleared, the Baud Rate Generator is turned off and the

MSSP1 module then goes into Idle mode

(Figure 25-29).

25.6.8.1 WCOL Status Flag

If the user writes the SSP1BUF when an Acknowledge

sequence is in progress, then the WCOL bit is set and

the contents of the buffer are unchanged (the write

doesn’t occur).

25.6.9 STOP CONDITION TIMING

A Stop bit is asserted on the SDA pin at the end of a

receive/transmit by setting the Stop Sequence Enable

bit, PEN bit of the SSP1CON2 register. At the end of a

receive/transmit, the SCL line is held low after the

falling edge of the ninth clock. When the PEN bit is set,

the master will assert the SDA line low. When the SDA

line is sampled low, the Baud Rate Generator is

reloaded and counts down to ‘0’. When the Baud Rate

Generator times out, the SCL pin will be brought high

and one TBRG (Baud Rate Generator rollover count)

later, the SDA pin will be deasserted. When the SDA

pin is sampled high while SCL is high, the P bit of the

SSP1STAT register is set. A TBRG later, the PEN bit is

cleared and the SSP1IF bit is set (Figure 25-30).

25.6.9.1 WCOL Status Flag

If the user writes the SSP1BUF when a Stop sequence

is in progress, then the WCOL bit is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

FIGURE 25-30: ACKNOWLEDGE SEQUENCE WAVEFORM

Note: TBRG = one Baud Rate Generator period.

SDA

SCL

SSP1IF set at

Acknowledge sequence starts here,

write to SSP1CON2 ACKEN automatically cleared

Cleared in

TBRG TBRG

the end of receive

ACKEN = 1, ACKDT = 0

SSP1IF

software SSP1IF set at the end

of Acknowledge sequence

Cleared in

software

ACK

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FIGURE 25-31: STOP CONDITION RECEIVE OR TRANSMIT MODE

25.6.10 SLEEP OPERATION

While in Sleep mode, the I2C slave module can receive

addresses or data and when an address match or

complete byte transfer occurs, wake the processor

from Sleep (if the MSSP1 interrupt is enabled).

25.6.11 EFFECTS OF A RESET

A Reset disables the MSSP1 module and terminates

the current transfer.

25.6.12 MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allows the

determination of when the bus is free. The Stop (P) and

Start (S) bits are cleared from a Reset or when the

MSSP1 module is disabled. Control of the I2C bus may

be taken when the P bit of the SSP1STAT register is

set, or the bus is Idle, with both the S and P bits clear.

When the bus is busy, enabling the SSP interrupt will

generate the interrupt when the Stop condition occurs.

In multi-master operation, the SDA line must be

monitored for arbitration to see if the signal level is the

expected output level. This check is performed by

hardware with the result placed in the BCL1IF bit.

The states where arbitration can be lost are:

• Address Transfer

• Data Transfer

• A Start Condition

• A Repeated Start Condition

• An Acknowledge Condition

25.6.13 MULTI -MASTER COMMUNICATION,

BUS COLLISION AND BUS

ARBITRATION

Multi-Master mode support is achieved by bus arbitra-

tion. When the master outputs address/data bits onto

the SDA pin, arbitration takes place when the master

outputs a ‘1’ on SDA, by letting SDA float high and

another master asserts a ‘0’. When the SCL pin floats

high, data should be stable. If the expected data on

SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’,

then a bus collision has taken place. The master will set

the Bus Collision Interrupt Flag, BCL1IF and reset the

I2C port to its Idle state (Figure 25-31).

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the BF flag is

cleared, the SDA and SCL lines are deasserted and the

SSP1BUF can be written to. When the user services

the bus collision Interrupt Service Routine and if the I2C

bus is free, the user can resume communication by

asserting a Start condition.

If a Start, Repeated Start, Stop or Acknowledge condi-

tion was in progress when the bus collision occurred, the

condition is aborted, the SDA and SCL lines are deas-

serted and the respective control bits in the SSP1CON2

lision Interrupt Service Routine and if the I2C bus is free,

the user can resume communication by asserting a Start

condition.

The master will continue to monitor the SDA and SCL

pins. If a Stop condition occurs, the SSP1IF bit will be set.

A write to the SSP1BUF will start the transmission of

data at the first data bit, regardless of where the

transmitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the

detection of Start and Stop conditions allows the deter-

mination of when the bus is free. Control of the I2C bus

can be taken when the P bit is set in the SSP1STAT

cleared.

SCL

SDA

SDA asserted low before rising edge of clock

Write to SSP1CON2,

set PEN

Falling edge of

SCL = 1 for TBRG, followed by SDA = 1 for TBRG

9th clock

SCL brought high after TBRG

Note: TBRG = one Baud Rate Generator period.

TBRG TBRG

after SDA sampled high. P bit (SSP1STAT<4>) is set.

TBRG

to set up Stop condition

ACK

TBRG

PEN bit (SSP1CON2<2>) is cleared by

hardware and the SSP1IF bit is set

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FIGURE 25-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

SDA

SCL

BCL1IF

SDA released

SDA line pulled low

by another source

Sample SDA. While SCL is high,

data doesn’t match what is driven

Bus collision has occurred.

Set bus collision

interrupt (BCL1IF)

by the master.

by master

Data changes

while SCL = 0

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25.6.13.1 Bus Collision During a Start

Condition

During a Start condition, a bus collision occurs if:

a) SDA or SCL are sampled low at the beginning of

the Start condition (Figure 25-32).

b) SCL is sampled low before SDA is asserted low

(Figure 25-33).

During a Start condition, both the SDA and the SCL

pins are monitored.

If the SDA pin is already low, or the SCL pin is already

low, then all of the following occur:

• the Start condition is aborted,

• the BCL1IF flag is set and

• the MSSP1 module is reset to its Idle state

(Figure 25-32).

The Start condition begins with the SDA and SCL pins

deasserted. When the SDA pin is sampled high, the

Baud Rate Generator is loaded and counts down. If the

SCL pin is sampled low while SDA is high, a bus colli-

sion occurs because it is assumed that another master

is attempting to drive a data ‘1’ during the Start

condition.

If the SDA pin is sampled low during this count, the

BRG is reset and the SDA line is asserted early

(Figure 25-34). If, however, a ‘1’ is sampled on the SDA

pin, the SDA pin is asserted low at the end of the BRG

count. The Baud Rate Generator is then reloaded and

counts down to zero; if the SCL pin is sampled as ‘0’

during this time, a bus collision does not occur. At the

end of the BRG count, the SCL pin is asserted low.

FIGURE 25-33: BUS COLLISION DURING START CONDITION (SDA ONLY)

Note: The reason that bus collision is not a fac-

tor during a Start condition is that no two

bus masters can assert a Start condition

at the exact same time. Therefore, one

master will always assert SDA before the

other. This condition does not cause a bus

collision because the two masters must be

allowed to arbitrate the first address fol-

lowing the Start condition. If the address is

the same, arbitration must be allowed to

continue into the data portion, Repeated

Start or Stop conditions.

SDA

SCL

SEN

SDA sampled low before

SDA goes low before the SEN bit is set.

S bit and SSP1IF set because

SSP1 module reset into Idle state.

SEN cleared automatically because of bus collision.

S bit and SSP1IF set because

Set SEN, enable Start

condition if SDA = 1, SCL = 1

SDA = 0, SCL = 1.

BCL1IF

SSP1IF

SDA = 0, SCL = 1.

SSP1IF and BCL1IF are

cleared by software

SSP1IF and BCL1IF are

cleared by software

Set BCL1IF,

Start condition. Set BCL1IF.

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PIC16(L)F1824/1828

FIGURE 25-34: BUS COLLISION DURING START CONDITION (SCL = 0)

FIGURE 25-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION

SDA

SCL

SEN bus collision occurs. Set BCL1IF.

SCL = 0 before SDA = 0,

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

TBRG TBRG

SDA = 0, SCL = 1

BCL1IF

SSP1IF

Interrupt cleared

by software

bus collision occurs. Set BCL1IF.

SCL = 0 before BRG time-out,

‘0’‘0’

SDA

SCL

SEN

Set S

Less than TBRG TBRG

SDA = 0, SCL = 1

BCL1IF

SSP1IF

Interrupts cleared

by software

set SSP1IF

SDA = 0, SCL = 1,

SCL pulled low after BRG

time-out

Set SSP1IF

‘0’

SDA pulled low by other master.

Reset BRG and assert SDA.

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

PIC16(L)F1824/1828

DS41419C-page 288 Preliminary  2010-2011 Microchip Technology Inc.

25.6.13.2 Bus Collision During a Repeated

Start Condition

During a Repeated Start condition, a bus collision

occurs if:

a) A low level is sampled on SDA when SCL goes

from low level to high level.

b) SCL goes low before SDA is asserted low,

indicating that another master is attempting to

transmit a data ‘1’.

When the user releases SDA and the pin is allowed to

float high, the BRG is loaded with SSP1ADD and

counts down to zero. The SCL pin is then deasserted

and when sampled high, the SDA pin is sampled.

If SDA is low, a bus collision has occurred (i.e., another

master is attempting to transmit a data ‘0’, Figure 25-35).

If SDA is sampled high, the BRG is reloaded and begins

counting. If SDA goes from high-to-low before the BRG

times out, no bus collision occurs because no two

masters can assert SDA at exactly the same time.

If SCL goes from high-to-low before the BRG times out

and SDA has not already been asserted, a bus collision

occurs. In this case, another master is attempting to

transmit a data ‘1’ during the Repeated Start condition,

see Figure 25-36.

If, at the end of the BRG time-out, both SCL and SDA

are still high, the SDA pin is driven low and the BRG is

reloaded and begins counting. At the end of the count,

regardless of the status of the SCL pin, the SCL pin is

driven low and the Repeated Start condition is

complete.

FIGURE 25-36: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

FIGURE 25-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

SDA

SCL

RSEN

BCL1IF

SSP1IF

Sample SDA when SCL goes high.

If SDA = 0, set BCL1IF and release SDA and SCL.

Cleared by software

‘0’

SDA

SCL

BCL1IF

RSEN

SSP1IF

Interrupt cleared

by software

SCL goes low before SDA,

set BCL1IF. Release SDA and SCL.

TBRG TBRG

‘0’

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 289

PIC16(L)F1824/1828

25.6.13.3 Bus Collision During a Stop

Condition

Bus collision occurs during a Stop condition if:

a) After the SDA pin has been deasserted and

allowed to float high, SDA is sampled low after

the BRG has timed out.

b) After the SCL pin is deasserted, SCL is sampled

low before SDA goes high.

The Stop condition begins with SDA asserted low.

When SDA is sampled low, the SCL pin is allowed to

float. When the pin is sampled high (clock arbitration),

the Baud Rate Generator is loaded with SSP1ADD and

counts down to 0. After the BRG times out, SDA is

sampled. If SDA is sampled low, a bus collision has

occurred. This is due to another master attempting to

drive a data ‘0’ (Figure 25-37). If the SCL pin is sampled

low before SDA is allowed to float high, a bus collision

occurs. This is another case of another master

attempting to drive a data ‘0’ (Figure 25-38).

FIGURE 25-38: BUS COLLISION DURING A STOP CONDITION (CASE 1)

FIGURE 25-39: BUS COLLISION DURING A STOP CONDITION (CASE 2)

SDA

SCL

BCL1IF

PEN

SSP1IF

TBRG TBRG TBRG

SDA asserted low

SDA sampled

low after TBRG,

set BCL1IF

‘0’

SDA

SCL

BCL1IF

PEN

SSP1IF

TBRG TBRG TBRG

Assert SDA SCL goes low before SDA goes high,

set BCL1IF

‘0’

PIC16(L)F1824/1828

DS41419C-page 290 Preliminary  2010-2011 Microchip Technology Inc.

TABLE 25-3: SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ OPERATION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values on

Page:

INLVLB(1) INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — — 133

INLVLC INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 139

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 94

PIE2 OSFIE C2IE C1IE EEIE BCL1IE ——CCP2IE95

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 97

PIR2 OSFIF C2IF C1IF EEIF BCL1IF — — CCP2IF 98

SSP1ADD ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 296

SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 247*

SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 293

SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 294

SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 295

SSP1MSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 296

SSP1STAT SMP CKE D/A P S R/W UA BF 292

TRISB(1) TRISB7 TRISB6 TRISB5 TRISB4 — — — — 132

TRISC(2) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode.

* Page provides register information.

Note 1: PIC16(L)F1828 only.

2: Unshaded cells apply to PIC16(L)F1824 only.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 291

PIC16(L)F1824/1828

25.7 Baud Rate Generator

The MSSP1 module has a Baud Rate Generator avail-

able for clock generation in both I2C and SPI Master

modes. The Baud Rate Generator (BRG) reload value

is placed in the SSP1ADD register (Register 25-6).

When a write occurs to SSP1BUF, the Baud Rate Gen-

erator will automatically begin counting down.

Once the given operation is complete, the internal clock

will automatically stop counting and the clock pin will

remain in its last state.

An internal signal “Reload” in Figure 25-39 triggers the

value from SSP1ADD to be loaded into the BRG

counter. This occurs twice for each oscillation of the

module clock line. The logic dictating when the reload

signal is asserted depends on the mode the MSSP1 is

being operated in.

Table 25-4 demonstrates clock rates based on

instruction cycles and the BRG value loaded into

SSP1ADD.

EQUATION 25-1:

FIGURE 25-40: BAUD RATE GENERATOR BLOCK DIAGRAM

TABLE 25-4: MSSP1 CLOCK RATE W/BRG

25.7.1 ALTERNATE PIN LOCATIONS

This module incorporates I/O pins that can be moved to

other locations with the use of the alternate pin function

registers, APFCON0 and APFCON1. To determine

which pins can be moved and what their default loca-

tions are upon a Reset, see Section 12.1 “Alternate

Pin Function” for more information.

FCLOCK FOSC

SSPxADD 1+4

-------------------------------------------------=

Note: Values of 0x00, 0x01 and 0x02 are not valid

for SSP1ADD when used as a Baud Rate

Generator for I2C. This is an implementation

limitation.

FOSC FCY BRG Value FCLOCK

(2 Rollovers of BRG)

32 MHz 8 MHz 13h 400 kHz(1)

32 MHz 8 MHz 19h 308 kHz

32 MHz 8 MHz 4Fh 100 kHz

16 MHz 4 MHz 09h 400 kHz(1)

16 MHz 4 MHz 0Ch 308 kHz

16 MHz 4 MHz 27h 100 kHz

4 MHz 1 MHz 09h 100 kHz

Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than

100 kHz) in all details, but may be used with care where higher rates are required by the application.

SSP1M<3:0>

BRG Down Counter

SSP1CLK FOSC/2

SSP1ADD<7:0>

SSP1M<3:0>

SCL

Reload

Control

Reload

PIC16(L)F1824/1828

DS41419C-page 292 Preliminary  2010-2011 Microchip Technology Inc.

R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0

SMP CKE D/A PSR/WUA BF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 SMP: SPI Data Input Sample bit

SPI Master mode:

1 = Input data sampled at end of data output time

0 = Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode

In I2 C Master or Slave mode:

1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)

0 = Slew rate control enabled for high speed mode (400 kHz)

bit 6 CKE: SPI Clock Edge Select bit (SPI mode only)

In SPI Master or Slave mode:

1 = Transmit occurs on transition from active to Idle clock state

0 = Transmit occurs on transition from Idle to active clock state

In I2 C™ mode only:

1 = Enable input logic so that thresholds are compliant with SMbus specification

0 = Disable SMbus specific inputs

bit 5 D/A: Data/Address bit (I2C mode only)

1 = Indicates that the last byte received or transmitted was data

0 = Indicates that the last byte received or transmitted was address

bit 4 P: Stop bit

(I2C mode only. This bit is cleared when the MSSP1 module is disabled, SSP1EN is cleared.)

1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)

0 = Stop bit was not detected last

bit 3 S: Start bit

(I2C mode only. This bit is cleared when the MSSP1 module is disabled, SSP1EN is cleared.)

1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)

0 = Start bit was not detected last

bit 2 R/W: Read/Write bit information (I2C mode only)

This bit holds the R/W bit information following the last address match. This bit is only valid from the address match

to the next Start bit, Stop bit, or not ACK bit.

In I2 C Slave mode:

1 = Read

0 = Write

In I2 C Master mode:

1 = Transmit is in progress

0 = Transmit is not in progress

OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP1 is in Idle mode.

bit 1 UA: Update Address bit (10-bit I2C mode only)

1 = Indicates that the user needs to update the address in the SSP1ADD register

0 = Address does not need to be updated

bit 0 BF: Buffer Full Status bit

Receive (SPI and I2 C modes):

1 = Receive complete, SSP1BUF is full

0 = Receive not complete, SSP1BUF is empty

Transmit (I2 C mode only):

1 = Data transmit in progress (does not include the ACK and Stop bits), SSP1BUF is full

0 = Data transmit complete (does not include the ACK and Stop bits), SSP1BUF is empty

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 293

PIC16(L)F1824/1828

R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

WCOL SSPOV SSPEN CKP SSPM<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared

bit 7 WCOL: Write Collision Detect bit

Master mode:

1 = A write to the SSP1BUF register was attempted while the I2C™ conditions were not valid for a transmission to be started

0 = No collision

Slave mode:

1 = The SSP1BUF register is written while it is still transmitting the previous word (must be cleared in software)

0 = No collision

bit 6 SSPOV: Receive Overflow Indicator bit(1)

In SPI mode:

1 = A new byte is received while the SSP1BUF register is still holding the previous data. In case of overflow, the data in SSP1SR is lost.

Overflow can only occur in Slave mode. In Slave mode, the user must read the SSP1BUF, even if only transmitting data, to avoid

setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the

SSP1BUF register (must be cleared in software).

0 = No overflow

In I2 C mode:

1 = A byte is received while the SSP1BUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode

(must be cleared in software).

0 = No overflow

bit 5 SSPEN: Synchronous Serial Port Enable bit

In both modes, when enabled, these pins must be properly configured as input or output

In SPI mode:

1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2)

0 = Disables serial port and configures these pins as I/O port pins

In I2 C mode:

1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3)

0 = Disables serial port and configures these pins as I/O port pins

bit 4 CKP: Clock Polarity Select bit

In SPI mode:

1 = Idle state for clock is a high level

0 = Idle state for clock is a low level

In I2 C Slave mode:

SCL release control

1 = Enable clock

0 = Holds clock low (clock stretch). (Used to ensure data setup time.)

In I2 C Master mode:

Unused in this mode

bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits

0000 = SPI Master mode, clock = FOSC/4

0001 = SPI Master mode, clock = FOSC/16

0010 = SPI Master mode, clock = FOSC/64

0011 = SPI Master mode, clock = TMR2 output/2

0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled

0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin

0110 = I2C Slave mode, 7-bit address

0111 = I2C Slave mode, 10-bit address

1000 = I2C Master mode, clock = FOSC/(4 * (SSP1ADD+1))(4)

1001 = Reserved

1010 = SPI Master mode, clock = FOSC/(4 * (SSP1ADD+1))(5)

1011 = I2C firmware controlled Master mode (Slave idle)

1100 = Reserved

1101 = Reserved

1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled

1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSP1BUF register.

2: When enabled, these pins must be properly configured as input or output.

3: When enabled, the SDA and SCL pins must be configured as inputs.

4: SSP1ADD values of 0, 1 or 2 are not supported for I2C™ mode.

5: SSPxADD value of 0 is not supported. Use SSPxM = 0000 instead.

PIC16(L)F1824/1828

DS41419C-page 294 Preliminary  2010-2011 Microchip Technology Inc.

R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0

GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set

bit 7 GCEN: General Call Enable bit (in I2C Slave mode only)

1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSP1SR

0 = General call address disabled

bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only)

1 = Acknowledge was not received

0 = Acknowledge was received

bit 5 ACKDT: Acknowledge Data bit (in I2C mode only)

In Receive mode:

Value transmitted when the user initiates an Acknowledge sequence at the end of a receive

1 = Not Acknowledge

0 = Acknowledge

bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)

In Master Receive mode:

1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.

Automatically cleared by hardware.

0 = Acknowledge sequence idle

bit 3 RCEN: Receive Enable bit (in I2C Master mode only)

1 = Enables Receive mode for I2C

0 = Receive idle

bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only)

SCK Release Control:

1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.

0 = Stop condition Idle

bit 1 RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only)

1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.

0 = Repeated Start condition Idle

bit 0 SEN: Start Condition Enabled bit (in I2C Master mode only)

In Master mode:

1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.

0 = Start condition Idle

In Slave mode:

1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)

0 = Clock stretching is disabled

Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be

set (no spooling) and the SSP1BUF may not be written (or writes to the SSP1BUF are disabled).

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 295

PIC16(L)F1824/1828

R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3)

1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCL clock

0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock

bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only)

1 = Enable interrupt on detection of Stop condition

0 = Stop detection interrupts are disabled(2)

bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only)

1 = Enable interrupt on detection of Start or Restart conditions

0 = Start detection interrupts are disabled(2)

bit 4 BOEN: Buffer Overwrite Enable bit

In SPI Slave mode:(1)

1 = SSP1BUF updates every time that a new data byte is shifted in ignoring the BF bit

0 = If new byte is received with BF bit of the SSP1STAT register already set, SSPOV bit of the

SSP1CON1 register is set, and the buffer is not updated

In I2C Master mode and SPI Master mode:

This bit is ignored.

In I2C Slave mode:

1 = SSP1BUF is updated and ACK is generated for a received address/data byte, ignoring the

state of the SSPOV bit only if the BF bit = 0.

0 = SSP1BUF is only updated when SSPOV is clear

bit 3 SDAHT: SDA Hold Time Selection bit (I2C mode only)

1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL

0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL

bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)

If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the

BCL1IF bit of the PIR2 register is set, and bus goes idle

1 = Enable slave bus collision interrupts

0 = Slave bus collision interrupts are disabled

bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only)

1 = Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the

SSP1CON1 register will be cleared and the SCL will be held low.

0 = Address holding is disabled

bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only)

1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit

of the SSP1CON1 register and SCL is held low.

0 = Data holding is disabled

Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set

when a new byte is received and BF = 1, but hardware continues to write the most recent byte to

SSP1BUF.

2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.

3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.

PIC16(L)F1824/1828

DS41419C-page 296 Preliminary  2010-2011 Microchip Technology Inc.

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1

MSK<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-1 MSK<7:1>: Mask bits

1 = The received address bit n is compared to SSP1ADD<n> to detect I2C address match

0 = The received address bit n is not used to detect I2C address match

bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address

I2C Slave mode, 10-bit address (SSP1M<3:0> = 0111 or 1111):

1 = The received address bit 0 is compared to SSP1ADD<0> to detect I2C address match

0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address,

the bit is ignored

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

ADD<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

Master mode:

bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits

SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC

10-Bit Slave mode — Most Significant Address byte:

bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care.” Bit

pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits

are compared by hardware and are not affected by the value in this register.

bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address

bit 0 Not used: Unused in this mode. Bit state is a “don’t care.”

10-Bit Slave mode — Least Significant Address byte:

bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address

7-Bit Slave mode:

bit 7-1 ADD<7:1>: 7-bit address

bit 0 Not used: Unused in this mode. Bit state is a “don’t care.”

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 297

PIC16(L)F1824/1828

26.0 ENHANCED UNIVERSAL

SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (EUSART)

The Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART) module is a serial I/O

communications peripheral. It contains all the clock

generators, shift registers and data buffers necessary

to perform an input or output serial data transfer

independent of device program execution. The

EUSART, also known as a Serial Communications

Interface (SCI), can be configured as a full-duplex

asynchronous system or half-duplex synchronous

system. Full-Duplex mode is useful for

communications with peripheral systems, such as CRT

terminals and personal computers. Half-Duplex

Synchronous mode is intended for communications

with peripheral devices, such as A/D or D/A integrated

circuits, serial EEPROMs or other microcontrollers.

These devices typically do not have internal clocks for

baud rate generation and require the external clock

signal provided by a master synchronous device.

The EUSART module includes the following capabilities:

• Full-duplex asynchronous transmit and receive

• Two-character input buffer

• One-character output buffer

• Programmable 8-bit or 9-bit character length

• Address detection in 9-bit mode

• Input buffer overrun error detection

• Received character framing error detection

• Half-duplex synchronous master

• Half-duplex synchronous slave

• Programmable clock polarity in synchronous

modes

• Sleep operation

The EUSART module implements the following

additional features, making it ideally suited for use in

Local Interconnect Network (LIN) bus systems:

• Automatic detection and calibration of the baud rate

• Wake-up on Break reception

• 13-bit Break character transmit

Block diagrams of the EUSART transmitter and

receiver are shown in Figure 26-1 and Figure 26-2.

FIGURE 26-1: EUSART TRANSMIT BLOCK DIAGRAM

TXIF

TXIE

Interrupt

TXEN

TX9D

MSb LSb

Data Bus

TXREG Register

Transmit Shift Register (TSR)

(8) 0

TX9

TRMT SPEN

TX/CK pin

Pin Buffer

and Control

SPBRGL

SPBRGH

BRG16

FOSC ÷ n

+ 1 Multiplier x4 x16 x64

SYNC 1X00 0

BRGH X110 0

BRG16 X101 0

Baud Rate Generator

•••

PIC16(L)F1824/1828

DS41419C-page 298 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 26-2: EUSART RECEIVE BLOCK DIAGRAM

The operation of the EUSART module is controlled

through three registers:

• Transmit Status and Control (TXSTA)

• Receive Status and Control (RCSTA)

• Baud Rate Control (BAUDCON)

These registers are detailed in Register 26-1,

When the receiver or transmitter section is not enabled

then the corresponding RX or TX pin may be used for

general purpose input and output.

RX/DT pin

Pin Buffer

and Control

SPEN

Data

Recovery

CREN OERR

FERR

RSR Register

MSb LSb

RX9D RCREG Register FIFO

Interrupt

RCIF

RCIE

Data Bus

Stop START

(8) 7 1 0

RX9

• • •

SPBRGLSPBRGH

BRG16

RCIDL

FOSC ÷ n

+ 1 Multiplier x4 x16 x64

SYNC 1X00 0

BRGH X110 0

BRG16 X101 0

Baud Rate Generator

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PIC16(L)F1824/1828

26.1 EUSART Asynchronous Mode

The EUSART transmits and receives data using the

standard non-return-to-zero (NRZ) format. NRZ is

implemented with two levels: a VOH mark state which

represents a ‘1’ data bit, and a VOL space state which

represents a ‘0’ data bit. NRZ refers to the fact that

consecutively transmitted data bits of the same value

stay at the output level of that bit without returning to a

neutral level between each bit transmission. An NRZ

transmission port idles in the mark state. Each character

transmission consists of one Start bit followed by eight

or nine data bits and is always terminated by one or

more Stop bits. The Start bit is always a space and the

Stop bits are always marks. The most common data

format is 8 bits. Each transmitted bit persists for a period

of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud

Rate Generator is used to derive standard baud rate

frequencies from the system oscillator. See Table 26-5

for examples of baud rate configurations.

The EUSART transmits and receives the LSb first. The

EUSART’s transmitter and receiver are functionally

independent, but share the same data format and baud

rate. Parity is not supported by the hardware, but can

be implemented in software and stored as the ninth

data bit.

26.1.1 EUSART ASYNCHRONOUS

TRANSMITTER

The EUSART transmitter block diagram is shown in

Figure 26-1. The heart of the transmitter is the serial

Transmit Shift Register (TSR), which is not directly

accessible by software. The TSR obtains its data from

the transmit buffer, which is the TXREG register.

26.1.1.1 Enabling the Transmitter

The EUSART transmitter is enabled for asynchronous

operations by configuring the following three control

bits:

•TXEN = 1

• SYNC = 0

• SPEN = 1

All other EUSART control bits are assumed to be in

their default state.

Setting the TXEN bit of the TXSTA register enables the

transmitter circuitry of the EUSART. Clearing the SYNC

bit of the TXSTA register configures the EUSART for

asynchronous operation. Setting the SPEN bit of the

RCSTA register enables the EUSART and automatically

configures the TX/CK I/O pin as an output. If the TX/CK

pin is shared with an analog peripheral, the analog I/O

function must be disabled by clearing the corresponding

ANSEL bit.

26.1.1.2 Transmitting Data

A transmission is initiated by writing a character to the

TXREG register. If this is the first character, or the

previous character has been completely flushed from

the TSR, the data in the TXREG is immediately

transferred to the TSR register. If the TSR still contains

all or part of a previous character, the new character

data is held in the TXREG until the Stop bit of the

previous character has been transmitted. The pending

character in the TXREG is then transferred to the TSR

in one TCY immediately following the Stop bit

transmission. The transmission of the Start bit, data bits

and Stop bit sequence commences immediately

following the transfer of the data to the TSR from the

TXREG.

26.1.1.3 Transmit Interrupt Flag

The TXIF interrupt flag bit of the PIR1 register is set

whenever the EUSART transmitter is enabled and no

character is being held for transmission in the TXREG.

In other words, the TXIF bit is only clear when the TSR

is busy with a character and a new character has been

queued for transmission in the TXREG. The TXIF flag bit

is not cleared immediately upon writing TXREG. TXIF

becomes valid in the second instruction cycle following

the write execution. Polling TXIF immediately following

the TXREG write will return invalid results. The TXIF bit

is read-only, it cannot be set or cleared by software.

The TXIF interrupt can be enabled by setting the TXIE

interrupt enable bit of the PIE1 register. However, the

TXIF flag bit will be set whenever the TXREG is empty,

regardless of the state of TXIE enable bit.

To use interrupts when transmitting data, set the TXIE

bit only when there is more data to send. Clear the

TXIE interrupt enable bit upon writing the last character

of the transmission to the TXREG.

Note 1: The TXIF Transmitter Interrupt flag is set

when the TXEN enable bit is set.

PIC16(L)F1824/1828

DS41419C-page 300 Preliminary  2010-2011 Microchip Technology Inc.

26.1.1.4 TSR Status

The TRMT bit of the TXSTA register indicates the

status of the TSR register. This is a read-only bit. The

TRMT bit is set when the TSR register is empty and is

cleared when a character is transferred to the TSR

until all bits have been shifted out of the TSR register.

No interrupt logic is tied to this bit, so the user has to

poll this bit to determine the TSR status.

26.1.1.5 Transmitting 9-Bit Characters

The EUSART supports 9-bit character transmissions.

When the TX9 bit of the TXSTA register is set, the

EUSART will shift 9 bits out for each character transmit-

ted. The TX9D bit of the TXSTA register is the ninth,

and Most Significant, data bit. When transmitting 9-bit

data, the TX9D data bit must be written before writing

the 8 Least Significant bits into the TXREG. All nine bits

of data will be transferred to the TSR shift register

immediately after the TXREG is written.

A special 9-bit Address mode is available for use with

multiple receivers. See Section 26.1.2.7 “Address

Detection” for more information on the address mode.

26.1.1.6 Asynchronous Transmission Setup:

1. Initialize the SPBRGH, SPBRGL register pair and

the BRGH and BRG16 bits to achieve the desired

baud rate (see Section 26.3 “EUSART Baud

Rate Generator (BRG)”).

2. Enable the asynchronous serial port by clearing

the SYNC bit and setting the SPEN bit.

3. If 9-bit transmission is desired, set the TX9 con-

trol bit. A set ninth data bit will indicate that the 8

Least Significant data bits are an address when

the receiver is set for address detection.

4. Enable the transmission by setting the TXEN

control bit. This will cause the TXIF interrupt bit

to be set.

5. If interrupts are desired, set the TXIE interrupt

enable bit of the PIE1 register. An interrupt will

occur immediately provided that the GIE and

PEIE bits of the INTCON register are also set.

6. If 9-bit transmission is selected, the ninth bit

should be loaded into the TX9D data bit.

7. Load 8-bit data into the TXREG register. This

will start the transmission.

FIGURE 26-3: ASYNCHRONOUS TRANSMISSION

Note: The TSR register is not mapped in data

memory, so it is not available to the user.

Word 1

Stop bit

Word 1

Transmit Shift Reg.

Start bit bit 0 bit 1 bit 7/8

Write to TXREG

Word 1

BRG Output

(Shift Clock)

TX/CK

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

1 TCY

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PIC16(L)F1824/1828

FIGURE 26-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)

TABLE 26-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on

Page

APFCON0 RXDTSEL SDOSEL(2) SSSEL(2) —T1GSEL TXCKSEL — — 122

BAUDCON ABDOVF RCIDL — SCKP BRG16 —WUE ABDEN 308

INLVLA(3) — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 128

INLVLB(1) INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — — 133

INLVLC INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 139

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 94

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 97

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 307

SPBRGL BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 309*

SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 309*

TRISA3) — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 126

TRISB(1) TRISB7 TRISB6 TRISB5 TRISB4 — — — — 132

TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132

TXREG EUSART Transmit Data Register 299*

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 306

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Asynchronous Transmission.

* Page provides register information.

Note 1: PIC16(L)F1828 only.

2: PIC16(L)F1824 only.

3: Unshaded cells apply to PIC16(L)F1824 only.

Transmit Shift Reg.

Write to TXREG

BRG Output

(Shift Clock)

TX/CK

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1 Word 2

Start bit Stop bit Start bit

Transmit Shift Reg.

Word 1 Word 2

bit 0 bit 1 bit 7/8 bit 0

Note: This timing diagram shows two consecutive transmissions.

1 TCY

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

PIC16(L)F1824/1828

DS41419C-page 302 Preliminary  2010-2011 Microchip Technology Inc.

26.1.2 EUSART ASYNCHRONOUS

RECEIVER

The Asynchronous mode is typically used in RS-232

systems. The receiver block diagram is shown in

Figure 26-2. The data is received on the RX/DT pin and

drives the data recovery block. The data recovery block

is actually a high-speed shifter operating at 16 times

the baud rate, whereas the serial Receive Shift

bits of the character have been shifted in, they are

immediately transferred to a two character

First-In-First-Out (FIFO) memory. The FIFO buffering

allows reception of two complete characters and the

start of a third character before software must start

servicing the EUSART receiver. The FIFO and RSR

registers are not directly accessible by software.

Access to the received data is via the RCREG register.

26.1.2.1 Enabling the Receiver

The EUSART receiver is enabled for asynchronous

operation by configuring the following three control bits:

• CREN = 1

• SYNC = 0

• SPEN = 1

All other EUSART control bits are assumed to be in

their default state.

Setting the CREN bit of the RCSTA register enables the

receiver circuitry of the EUSART. Clearing the SYNC bit

of the TXSTA register configures the EUSART for

asynchronous operation. Setting the SPEN bit of the

RCSTA register enables the EUSART. The programmer

must set the corresponding TRIS bit to configure the

TX/CK I/O pin as an input.

26.1.2.2 Receiving Data

The receiver data recovery circuit initiates character

reception on the falling edge of the first bit. The first bit,

also known as the Start bit, is always a zero. The data

recovery circuit counts one-half bit time to the center of

the Start bit and verifies that the bit is still a zero. If it is

not a zero then the data recovery circuit aborts

character reception, without generating an error, and

resumes looking for the falling edge of the Start bit. If

the Start bit zero verification succeeds then the data

recovery circuit counts a full bit time to the center of the

next bit. The bit is then sampled by a majority detect

circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.

This repeats until all data bits have been sampled and

shifted into the RSR. One final bit time is measured and

the level sampled. This is the Stop bit, which is always

a ‘1’. If the data recovery circuit samples a ‘0’ in the

Stop bit position then a framing error is set for this

character, otherwise the framing error is cleared for this

character. See Section 26.1.2.4 “Receive Framing

Error” for more information on framing errors.

Immediately after all data bits and the Stop bit have

been received, the character in the RSR is transferred

to the EUSART receive FIFO and the RCIF interrupt

flag bit of the PIR1 register is set. The top character in

the FIFO is transferred out of the FIFO by reading the

RCREG register.

26.1.2.3 Receive Interrupts

The RCIF interrupt flag bit of the PIR1 register is set

whenever the EUSART receiver is enabled and there is

an unread character in the receive FIFO. The RCIF

interrupt flag bit is read-only, it cannot be set or cleared

by software.

RCIF interrupts are enabled by setting all of the

following bits:

• RCIE interrupt enable bit of the PIE1 register

• PEIE peripheral interrupt enable bit of the

INTCON register

• GIE global interrupt enable bit of the INTCON

The RCIF interrupt flag bit will be set when there is an

unread character in the FIFO, regardless of the state of

interrupt enable bits.

Note 1: If the RX/DT function is on an analog pin,

the corresponding ANSEL bit must be

cleared for the receiver to function.

Note: If the receive FIFO is overrun, no additional

characters will be received until the overrun

condition is cleared. See Section 26.1.2.5

“Receive Overrun Error” for more

information on overrun errors.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 303

PIC16(L)F1824/1828

26.1.2.4 Receive Framing Error

Each character in the receive FIFO buffer has a

corresponding framing error Status bit. A framing error

indicates that a Stop bit was not seen at the expected

time. The framing error status is accessed via the

FERR bit of the RCSTA register. The FERR bit

represents the status of the top unread character in the

receive FIFO. Therefore, the FERR bit must be read

before reading the RCREG.

The FERR bit is read-only and only applies to the top

unread character in the receive FIFO. A framing error

(FERR = 1) does not preclude reception of additional

characters. It is not necessary to clear the FERR bit.

Reading the next character from the FIFO buffer will

advance the FIFO to the next character and the next

corresponding framing error.

The FERR bit can be forced clear by clearing the SPEN

bit of the RCSTA register which resets the EUSART.

Clearing the CREN bit of the RCSTA register does not

affect the FERR bit. A framing error by itself does not

generate an interrupt.

26.1.2.5 Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be generated if a third character, in its

entirety, is received before the FIFO is accessed. When

this happens the OERR bit of the RCSTA register is set.

The characters already in the FIFO buffer can be read

but no additional characters will be received until the

error is cleared. The error must be cleared by either

clearing the CREN bit of the RCSTA register or by

resetting the EUSART by clearing the SPEN bit of the

RCSTA register.

26.1.2.6 Receiving 9-bit Characters

The EUSART supports 9-bit character reception. When

the RX9 bit of the RCSTA register is set the EUSART

will shift 9 bits into the RSR for each character

received. The RX9D bit of the RCSTA register is the

ninth and Most Significant data bit of the top unread

character in the receive FIFO. When reading 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the 8 Least Significant bits from

the RCREG.

26.1.2.7 Address Detection

A special Address Detection mode is available for use

when multiple receivers share the same transmission

line, such as in RS-485 systems. Address detection is

enabled by setting the ADDEN bit of the RCSTA

Address detection requires 9-bit character reception.

When address detection is enabled, only characters

with the ninth data bit set will be transferred to the

receive FIFO buffer, thereby setting the RCIF interrupt

bit. All other characters will be ignored.

Upon receiving an address character, user software

determines if the address matches its own. Upon

address match, user software must disable address

detection by clearing the ADDEN bit before the next

Stop bit occurs. When user software detects the end of

the message, determined by the message protocol

used, software places the receiver back into the

Address Detection mode by setting the ADDEN bit.

Note: If all receive characters in the receive

FIFO have framing errors, repeated reads

of the RCREG will not clear the FERR bit.

PIC16(L)F1824/1828

DS41419C-page 304 Preliminary  2010-2011 Microchip Technology Inc.

26.1.2.8 Asynchronous Reception Setup:

1. Initialize the SPBRGH, SPBRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 26.3 “EUSART

Baud Rate Generator (BRG)”).

2. Clear the ANSEL bit for the RX pin (if applicable).

3. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

4. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

5. If 9-bit reception is desired, set the RX9 bit.

6. Enable reception by setting the CREN bit.

7. The RCIF interrupt flag bit will be set when a

character is transferred from the RSR to the

receive buffer. An interrupt will be generated if

the RCIE interrupt enable bit was also set.

8. Read the RCSTA register to get the error flags

and, if 9-bit data reception is enabled, the ninth

data bit.

9. Get the received 8 Least Significant data bits

from the receive buffer by reading the RCREG

10. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

26.1.2.9 9-bit Address Detection Mode Setup

This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address

Detect Enable:

1. Initialize the SPBRGH, SPBRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 26.3 “EUSART

Baud Rate Generator (BRG)”).

2. Clear the ANSEL bit for the RX pin (if applicable).

3. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

4. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

5. Enable 9-bit reception by setting the RX9 bit.

6. Enable address detection by setting the ADDEN

bit.

7. Enable reception by setting the CREN bit.

8. The RCIF interrupt flag bit will be set when a

character with the ninth bit set is transferred

from the RSR to the receive buffer. An interrupt

will be generated if the RCIE interrupt enable bit

was also set.

9. Read the RCSTA register to get the error flags.

The ninth data bit will always be set.

10. Get the received 8 Least Significant data bits

from the receive buffer by reading the RCREG

device’s address.

11. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

12. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and generate interrupts.

FIGURE 26-5: ASYNCHRONOUS RECEPTION

Start

bit bit 7/8

bit 1bit 0 bit 7/8 bit 0Stop

bit

Start

bit

Start

bit

bit 7/8 Stop

bit

RX/DT pin

Reg

Rcv Buffer Reg.

Rcv Shift

Read Rcv

Buffer Reg.

RCREG

RCIF

(Interrupt Flag)

OERR bit

CREN

Word 1

RCREG

Word 2

RCREG

Stop

bit

Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,

causing the OERR (overrun) bit to be set.

RCIDL

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 305

PIC16(L)F1824/1828

TABLE 26-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

APFCON0 RXDTSEL SDOSEL(2) SSSEL(2) —T1GSEL TXCKSEL — — 122

BAUDCON ABDOVF RCIDL —SCKP BRG16 —WUEABDEN 308

INLVLA(3) — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 128

INLVLB(1) INLVLB7 INLVLB6 INLVLB5 INLVLB4 ————133

INLVLC INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 139

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 94

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 97

RCREG EUSART Receive Data Register 302*

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 307

SPBRGL BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 309*

SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 309*

TRISA(3) — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 126

TRISB(1) TRISB7 TRISB6 TRISB5 TRISB4 ————132

TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 306

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Asynchronous Reception.

* Page provides register information.

Note 1: PIC16(L)F1828 only.

2: PIC16(L)F1824 only.

3: Unshaded cells apply to PIC16(L)F1828 only.

PIC16(L)F1824/1828

DS41419C-page 306 Preliminary  2010-2011 Microchip Technology Inc.

26.2 Clock Accuracy with

Asynchronous Operation

The factory calibrates the internal oscillator block out-

put (INTOSC). However, the INTOSC frequency may

drift as VDD or temperature changes, and this directly

affects the asynchronous baud rate. Two methods may

be used to adjust the baud rate clock, but both require

a reference clock source of some kind.

The first (preferred) method uses the OSCTUNE

value in the OSCTUNE register allows for fine resolution

changes to the system clock source. See Section 5.2.2

“Internal Clock Sources” for more information.

The other method adjusts the value in the Baud Rate

Generator. This can be done automatically with the

Auto-Baud Detect feature (see Section 26.3.1

“Auto-Baud Detect”). There may not be fine enough

resolution when adjusting the Baud Rate Generator to

compensate for a gradual change in the peripheral

clock frequency.

R/W-/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0

CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care

Synchronous mode:

1 = Master mode (clock generated internally from BRG)

0 = Slave mode (clock from external source)

bit 6 TX9: 9-bit Transmit Enable bit

1 = Selects 9-bit transmission

0 = Selects 8-bit transmission

bit 5 TXEN: Transmit Enable bit(1)

1 = Transmit enabled

0 = Transmit disabled

bit 4 SYNC: EUSART Mode Select bit

1 = Synchronous mode

0 = Asynchronous mode

bit 3 SENDB: Send Break Character bit

Asynchronous mode:

1 = Send Sync Break on next transmission (cleared by hardware upon completion)

0 = Sync Break transmission completed

Synchronous mode:

Don’t care

bit 2 BRGH: High Baud Rate Select bit

Asynchronous mode:

1 = High speed

0 = Low speed

Synchronous mode:

Unused in this mode

bit 1 TRMT: Transmit Shift Register Status bit

1 = TSR empty

0 = TSR full

bit 0 TX9D: Ninth bit of Transmit Data

Can be address/data bit or a parity bit.

Note 1: SREN/CREN overrides TXEN in Sync mode.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 307

PIC16(L)F1824/1828

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-x/x

SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 SPEN: Serial Port Enable bit

1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)

0 = Serial port disabled (held in Reset)

bit 6 RX9: 9-bit Receive Enable bit

1 = Selects 9-bit reception

0 = Selects 8-bit reception

bit 5 SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care

Synchronous mode – Master:

1 = Enables single receive

0 = Disables single receive

This bit is cleared after reception is complete.

Synchronous mode – Slave

Don’t care

bit 4 CREN: Continuous Receive Enable bit

Asynchronous mode:

1 = Enables receiver

0 = Disables receiver

Synchronous mode:

1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0 = Disables continuous receive

bit 3 ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set

0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit

Asynchronous mode 8-bit (RX9 = 0):

Don’t care

bit 2 FERR: Framing Error bit

1 = Framing error (can be updated by reading RCREG register and receive next valid byte)

0 = No framing error

bit 1 OERR: Overrun Error bit

1 = Overrun error (can be cleared by clearing bit CREN)

0 = No overrun error

bit 0 RX9D: Ninth bit of Received Data

This can be address/data bit or a parity bit and must be calculated by user firmware.

PIC16(L)F1824/1828

DS41419C-page 308 Preliminary  2010-2011 Microchip Technology Inc.

R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0

ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 ABDOVF: Auto-Baud Detect Overflow bit

Asynchronous mode:

1 = Auto-baud timer overflowed

0 = Auto-baud timer did not overflow

Synchronous mode:

Don’t care

bit 6 RCIDL: Receive Idle Flag bit

Asynchronous mode:

1 = Receiver is Idle

0 = Start bit has been received and the receiver is receiving

Synchronous mode:

Don’t care

bit 5 Unimplemented: Read as ‘0’

bit 4 SCKP: Synchronous Clock Polarity Select bit

Asynchronous mode:

1 = Transmit inverted data to the TX/CK pin

0 = Transmit non-inverted data to the TX/CK pin

Synchronous mode:

1 = Data is clocked on rising edge of the clock

0 = Data is clocked on falling edge of the clock

bit 3 BRG16: 16-bit Baud Rate Generator bit

1 = 16-bit Baud Rate Generator is used

0 = 8-bit Baud Rate Generator is used

bit 2 Unimplemented: Read as ‘0’

bit 1 WUE: Wake-up Enable bit

Asynchronous mode:

1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE

will automatically clear after RCIF is set.

0 = Receiver is operating normally

Synchronous mode:

Don’t care

bit 0 ABDEN: Auto-Baud Detect Enable bit

Asynchronous mode:

1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete)

0 = Auto-Baud Detect mode is disabled

Synchronous mode:

Don’t care

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 309

PIC16(L)F1824/1828

26.3 EUSART Baud Rate Generator

(BRG)

The Baud Rate Generator (BRG) is an 8-bit or 16-bit

timer that is dedicated to the support of both the

asynchronous and synchronous EUSART operation.

By default, the BRG operates in 8-bit mode. Setting the

BRG16 bit of the BAUDCON register selects 16-bit

mode.

The SPBRGH, SPBRGL register pair determines the

period of the free running baud rate timer. In

Asynchronous mode the multiplier of the baud rate

period is determined by both the BRGH bit of the TXSTA

Synchronous mode, the BRGH bit is ignored.

Table 26-3 contains the formulas for determining the

baud rate. Example 26-1 provides a sample calculation

for determining the baud rate and baud rate error.

Typical baud rates and error values for various

asynchronous modes have been computed for your

convenience and are shown in Table 26-3. It may be

advantageous to use the high baud rate (BRGH = 1),

or the 16-bit BRG (BRG16 = 1) to reduce the baud rate

error. The 16-bit BRG mode is used to achieve slow

baud rates for fast oscillator frequencies.

Writing a new value to the SPBRGH, SPBRGL register

pair causes the BRG timer to be reset (or cleared). This

ensures that the BRG does not wait for a timer overflow

before outputting the new baud rate.

If the system clock is changed during an active receive

operation, a receive error or data loss may result. To

avoid this problem, check the status of the RCIDL bit to

make sure that the receive operation is Idle before

changing the system clock.

EXAMPLE 26-1: CALCULATING BAUD

RATE ERROR

For a device with FOSC of 16 MHz, desired baud rate

of 9600, Asynchronous mode, 8-bit BRG:

Solving for SPBRGH:SPBRGL:

FOSC

Desired Baud Rate

---------------------------------------------

--------------------------------------------- 1–=

Desired Baud Rate FOSC

64 [SPBRGH:SPBRGL] 1+

------------------------------------------------------------------------=

16000000

9600

------------------------

------------------------1–=

25.04225==

Calculated Baud Rate 16000000

64 25 1+

---------------------------=

9615=

Error Calc. Baud Rate Desired Baud Rate –

Desired Baud Rate

--------------------------------------------------------------------------------------------=

9615 9600–

9600

---------------------------------- 0 . 1 6 %==

PIC16(L)F1824/1828

DS41419C-page 310 Preliminary  2010-2011 Microchip Technology Inc.

TABLE 26-3: BAUD RATE FORMULAS

TABLE 26-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR

Configuration Bits

BRG/EUSART Mode Baud Rate Formula

SYNC BRG16 BRGH

000 8-bit/Asynchronous FOSC/[64 (n+1)]

001 8-bit/Asynchronous FOSC/[16 (n+1)]

010 16-bit/Asynchronous

011 16-bit/Asynchronous

FOSC/[4 (n+1)]10x 8-bit/Synchronous

11x 16-bit/Synchronous

Legend: x = Don’t care, n = value of SPBRGH, SPBRGL register pair

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

BAUDCON ABDOVF RCIDL —SCKP BRG16 —WUE ABDEN 308

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 307

SPBRGL BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 309*

SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 309*

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 306

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the Baud Rate Generator.

* Page provides register information.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 311

PIC16(L)F1824/1828

TABLE 26-5: BAUD RATES FOR ASYNCHRONOUS MODES

BAUD

RATE

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz

Actual

Rate

Error

SPBRG

value

(decimal)

Actual

Rate

Error

SPBRG

value

(decimal)

Actual

Rate

Error

SPBRG

value

(decimal)

Actual

Rate

Error

SPBRG

value

(decimal)

300—— — —— — —— — —— —

1200 — — — 1221 1.73 255 1200 0.00 239 1200 0.00 143

2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 71

9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17

10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16

19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8

57.6k 55.55k -3.55 3 — — — 57.60k 0.00 7 57.60k 0.00 2

115.2k — — — — — — — — — — — —

BAUD

RATE

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz

Actual

Rate

Error

SPBRG

value

(decimal)

Actual

Rate

Error

SPBRG

value

(decimal)

Actual

Rate

Error

SPBRG

value

(decimal)

Actual

Rate

Error

SPBRG

value

(decimal)

300 — — — 300 0.16 207 300 0.00 191 300 0.16 51

1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12

2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — —

9600 9615 0.16 12 — — — 9600 0.00 5 — — —

10417 10417 0.00 11 10417 0.00 5 — — — — — —

19.2k — — — — — — 19.20k 0.00 2 — — —

57.6k — — — — — — 57.60k 0.00 0 — — —

115.2k — — — — — — — — — — — —

BAUD

RATE

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz

Actual

Rate

Error

SPBRG

value

(decimal)

Actual

Rate

Error

SPBRG

value

(decimal)

Actual

Rate

Error

SPBRG

value

(decimal)

Actual

Rate

Error

SPBRG

value

(decimal)

300 —— — —— — —— — —— —

1200 — — — — — — — — — — — —

2400 — — — — — — — — — —— —

9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71

10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65

19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35

57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11

115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5

PIC16(L)F1824/1828

DS41419C-page 312 Preliminary  2010-2011 Microchip Technology Inc.

BAUD

RATE

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz

Actual

Rate

Error

SPBRG

value

(decimal)

Actual

Rate

Error

SPBRG

value

(decimal)

Actual

Rate

Error

SPBRG

value

(decimal)

Actual

Rate

Error

SPBRG

value

(decimal)

300 —— — — — — — — — 300 0.16 207

1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51

2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25

9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —

10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5

19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — —

57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —

115.2k — — — — — — 115.2k 0.00 1 — — —

BAUD

RATE

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz

Actual

Rate

Error

SPBRG

value

(decimal)

Actual

Rate

Error

SPBRG

value

(decimal)

Actual

Rate

Error

SPBRG

value

(decimal)

Actual

Rate

Error

SPBRG

value

(decimal)

300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303

1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575

2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287

9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71

10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65

19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35

57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11

115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5

BAUD

RATE

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz

Actual

Rate

Error

SPBRG

value

(decimal)

Actual

Rate

Error

SPBRG

value

(decimal)

Actual

Rate

Error

SPBRG

value

(decimal)

Actual

Rate

Error

SPBRG

value

(decimal)

300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207

1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51

2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25

9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —

10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5

19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — —

57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —

115.2k — — — — — — 115.2k 0.00 1 — — —

TABLE 26-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 313

PIC16(L)F1824/1828

BAUD

RATE

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz

Actual

Rate

Error

SPBRG

value

(decimal)

Actual

Rate

Error

SPBRG

value

(decimal)

Actual

Rate

Error

SPBRG

value

(decimal)

Actual

Rate

Error

SPBRG

value

(decimal)

300 300.0 0.00 26666 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215

1200 1200 0.00 6666 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303

2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151

9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287

10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264

19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143

57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47

115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23

BAUD

RATE

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz

Actual

Rate

Error

SPBRG

value

(decimal)

Actual

Rate

Error

SPBRG

value

(decimal)

Actual

Rate

Error

SPBRG

value

(decimal)

Actual

Rate

Error

SPBRG

value

(decimal)

300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832

1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207

2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103

9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25

10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23

19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12

57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — —

115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —

TABLE 26-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

PIC16(L)F1824/1828

DS41419C-page 314 Preliminary  2010-2011 Microchip Technology Inc.

26.3.1 AUTO-BAUD DETECT

The EUSART module supports automatic detection

and calibration of the baud rate.

In the Auto-Baud Detect (ABD) mode, the clock to the

BRG is reversed. Rather than the BRG clocking the

incoming RX signal, the RX signal is timing the BRG.

The Baud Rate Generator is used to time the period of

a received 55h (ASCII “U”) which is the Sync character

for the LIN bus. The unique feature of this character is

that it has five rising edges including the Stop bit edge.

Setting the ABDEN bit of the BAUDCON register starts

the auto-baud calibration sequence (Figure 26-6).

While the ABD sequence takes place, the EUSART

state machine is held in Idle. On the first rising edge of

the receive line, after the Start bit, the SPBRG begins

counting up using the BRG counter clock as shown in

Table 26-6. The fifth rising edge will occur on the RX pin

at the end of the eighth bit period. At that time, an

accumulated value totaling the proper BRG period is

left in the SPBRGH, SPBRGL register pair, the ABDEN

bit is automatically cleared and the RCIF interrupt flag

is set. The value in the RCREG needs to be read to

clear the RCIF interrupt. RCREG content should be

discarded. When calibrating for modes that do not use

the SPBRGH register the user can verify that the

SPBRGL register did not overflow by checking for 00h

in the SPBRGH register.

The BRG auto-baud clock is determined by the BRG16

and BRGH bits as shown in Table 26-6. During ABD,

both the SPBRGH and SPBRGL registers are used as

a 16-bit counter, independent of the BRG16 bit setting.

While calibrating the baud rate period, the SPBRGH

and SPBRGL registers are clocked at 1/8th the BRG

base clock rate. The resulting byte measurement is the

average bit time when clocked at full speed.

TABLE 26-6: BRG COUNTER CLOCK RATES

FIGURE 26-6: AUTOMATIC BAUD RATE CALIBRATION

Note 1: If the WUE bit is set with the ABDEN bit,

auto-baud detection will occur on the byte

following the Break character (see

Section 26.3.3 “Auto-Wake-up on

Break”).

2: It is up to the user to determine that the

incoming character baud rate is within the

range of the selected BRG clock source.

Some combinations of oscillator frequency

and EUSART baud rates are not possible.

3: During the auto-baud process, the

auto-baud counter starts counting at 1.

Upon completion of the auto-baud

sequence, to achieve maximum accuracy,

subtract 1 from the SPBRGH:SPBRGL

BRG16 BRGH BRG Base

Clock

BRG ABD

Clock

00FOSC/64 FOSC/512

01FOSC/16 FOSC/128

10FOSC/16 FOSC/128

11 FOSC/4 FOSC/32

Note: During the ABD sequence, SPBRGL and

SPBRGH registers are both used as a 16-bit

counter, independent of BRG16 setting.

BRG Value

RX pin

ABDEN bit

RCIF bit

bit 0 bit 1

(Interrupt)

Read

RCREG

BRG Clock

Start

Auto Cleared

Set by User

XXXXh 0000h

Edge #1

bit 2 bit 3

Edge #2

bit 4 bit 5

Edge #3

bit 6 bit 7

Edge #4

Stop bit

Edge #5

001Ch

Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.

SPBRGL XXh 1Ch

SPBRGH XXh 00h

RCIDL

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 315

PIC16(L)F1824/1828

26.3.2 AUTO-BAUD OVERFLOW

During the course of automatic baud detection, the

ABDOVF bit of the BAUDCON register will be set if the

baud rate counter overflows before the fifth rising edge

is detected on the RX pin. The ABDOVF bit indicates

that the counter has exceeded the maximum count that

can fit in the 16 bits of the SPBRGH:SPBRGL register

pair. After the ABDOVF has been set, the counter con-

tinues to count until the fifth rising edge is detected on

the RX pin. Upon detecting the fifth RX edge, the hard-

ware will set the RCIF interrupt flag and clear the

ABDEN bit of the BAUDCON register. The RCIF flag

can be subsequently cleared by reading the RCREG

can be cleared by software directly.

To terminate the auto-baud process before the RCIF

flag is set, clear the ABDEN bit then clear the ABDOVF

bit of the BAUDCON register. The ABDOVF bit will

remain set if the ABDEN bit is not cleared first.

26.3.3 AUTO-WAKE-UP ON BREAK

During Sleep mode, all clocks to the EUSART are

suspended. Because of this, the Baud Rate Generator

is inactive and a proper character reception cannot be

performed. The Auto-Wake-up feature allows the

controller to wake-up due to activity on the RX/DT line.

This feature is available only in Asynchronous mode.

The Auto-Wake-up feature is enabled by setting the

WUE bit of the BAUDCON register. Once set, the normal

receive sequence on RX/DT is disabled, and the

EUSART remains in an Idle state, monitoring for a

wake-up event independent of the CPU mode. A

wake-up event consists of a high-to-low transition on the

RX/DT line. (This coincides with the start of a Sync Break

or a wake-up signal character for the LIN protocol.)

The EUSART module generates an RCIF interrupt

coincident with the wake-up event. The interrupt is

generated synchronously to the Q clocks in normal CPU

operating modes (Figure 26-7), and asynchronously if

the device is in Sleep mode (Figure 26-8). The interrupt

condition is cleared by reading the RCREG register.

The WUE bit is automatically cleared by the low-to-high

transition on the RX line at the end of the Break. This

signals to the user that the Break event is over. At this

point, the EUSART module is in Idle mode waiting to

receive the next character.

26.3.3.1 Special Considerations

Break Character

To avoid character errors or character fragments during

a wake-up event, the wake-up character must be all

zeros.

When the wake-up is enabled the function works

independent of the low time on the data stream. If the

WUE bit is set and a valid non-zero character is

received, the low time from the Start bit to the first rising

edge will be interpreted as the wake-up event. The

remaining bits in the character will be received as a

fragmented character and subsequent characters can

result in framing or overrun errors.

Therefore, the initial character in the transmission must

be all ‘0’s. This must be 10 or more bit times, 13-bit

times recommended for LIN bus, or any number of bit

times for standard RS-232 devices.

Oscillator Startup Time

Oscillator start-up time must be considered, especially

in applications using oscillators with longer start-up

intervals (i.e., LP, XT or HS/PLL mode). The Sync

Break (or wake-up signal) character must be of

sufficient length, and be followed by a sufficient

interval, to allow enough time for the selected oscillator

to start and provide proper initialization of the EUSART.

WUE Bit

The wake-up event causes a receive interrupt by

setting the RCIF bit. The WUE bit is cleared in

hardware by a rising edge on RX/DT. The interrupt

condition is then cleared in software by reading the

RCREG register and discarding its contents.

To ensure that no actual data is lost, check the RCIDL

bit to verify that a receive operation is not in process

before setting the WUE bit. If a receive operation is not

occurring, the WUE bit may then be set just prior to

entering the Sleep mode.

PIC16(L)F1824/1828

DS41419C-page 316 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 26-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION

FIGURE 26-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

WUE bit

RX/DT Line

RCIF

Bit set by user Auto Cleared

Cleared due to User Read of RCREG

Note 1: The EUSART remains in Idle while the WUE bit is set.

Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4

OSC1

WUE bit

RX/DT Line

RCIF

Bit Set by User Auto Cleared

Cleared due to User Read of RCREG

Sleep Command Executed

Note 1

Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is

still active. This sequence should not depend on the presence of Q clocks.

2: The EUSART remains in Idle while the WUE bit is set.

Sleep Ends

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 317

PIC16(L)F1824/1828

26.3.4 BREAK CHARACTER SEQUENCE

The EUSART module has the capability of sending the

special Break character sequences that are required by

the LIN bus standard. A Break character consists of a

Start bit, followed by 12 ‘0’ bits and a Stop bit.

To send a Break character, set the SENDB and TXEN

bits of the TXSTA register. The Break character trans-

mission is then initiated by a write to the TXREG. The

value of data written to TXREG will be ignored and all

‘0’s will be transmitted.

The SENDB bit is automatically reset by hardware after

the corresponding Stop bit is sent. This allows the user

to preload the transmit FIFO with the next transmit byte

following the Break character (typically, the Sync

character in the LIN specification).

The TRMT bit of the TXSTA register indicates when the

transmit operation is active or Idle, just as it does during

normal transmission. See Figure 26-9 for the timing of

the Break character sequence.

26.3.4.1 Break and Sync Transmit Sequence

The following sequence will start a message frame

header made up of a Break, followed by an auto-baud

Sync byte. This sequence is typical of a LIN bus

master.

1. Configure the EUSART for the desired mode.

2. Set the TXEN and SENDB bits to enable the

Break sequence.

3. Load the TXREG with a dummy character to

initiate transmission (the value is ignored).

4. Write ‘55h’ to TXREG to load the Sync character

into the transmit FIFO buffer.

5. After the Break has been sent, the SENDB bit is

reset by hardware and the Sync character is

then transmitted.

When the TXREG becomes empty, as indicated by the

TXIF, the next data byte can be written to TXREG.

26.3.5 RECEIVING A BREAK CHARACTER

The Enhanced EUSART module can receive a Break

character in two ways.

The first method to detect a Break character uses the

FERR bit of the RCSTA register and the Received data

as indicated by RCREG. The Baud Rate Generator is

assumed to have been initialized to the expected baud

rate.

A Break character has been received when;

• RCIF bit is set

• FERR bit is set

• RCREG = 00h

The second method uses the Auto-Wake-up feature

described in Section 26.3.3 “Auto-Wake-up on

Break”. By enabling this feature, the EUSART will

sample the next two transitions on RX/DT, cause an

RCIF interrupt, and receive the next data byte followed

by another interrupt.

Note that following a Break character, the user will

typically want to enable the Auto-Baud Detect feature.

For both methods, the user can set the ABDEN bit of

the BAUDCON register before placing the EUSART in

Sleep mode.

FIGURE 26-9: SEND BREAK CHARACTER SEQUENCE

Write to TXREG Dummy Write

BRG Output

(Shift Clock)

Start bit bit 0 bit 1 bit 11 Stop bit

Break

TXIF bit

(Transmit

Interrupt Flag)

TX (pin)

TRMT bit

(Transmit Shift

Empty Flag)

SENDB

(send Break

control bit)

SENDB Sampled Here Auto Cleared

PIC16(L)F1824/1828

DS41419C-page 318 Preliminary  2010-2011 Microchip Technology Inc.

26.4 EUSART Synchronous Mode

Synchronous serial communications are typically used

in systems with a single master and one or more

slaves. The master device contains the necessary cir-

cuitry for baud rate generation and supplies the clock

for all devices in the system. Slave devices can take

advantage of the master clock by eliminating the inter-

nal clock generation circuitry.

There are two signal lines in Synchronous mode: a bidi-

rectional data line and a clock line. Slaves use the

external clock supplied by the master to shift the serial

data into and out of their respective receive and trans-

mit shift registers. Since the data line is bidirectional,

synchronous operation is half-duplex only. Half-duplex

refers to the fact that master and slave devices can

receive and transmit data but not both simultaneously.

The EUSART can operate as either a master or slave

device.

Start and Stop bits are not used in synchronous trans-

missions.

26.4.1 SYNCHRONOUS MASTER MODE

The following bits are used to configure the EUSART

for Synchronous Master operation:

• SYNC = 1

• CSRC = 1

• SREN = 0 (for transmit); SREN = 1 (for receive)

• CREN = 0 (for transmit); CREN = 1 (for receive)

• SPEN = 1

Setting the SYNC bit of the TXSTA register configures

the device for synchronous operation. Setting the CSRC

bit of the TXSTA register configures the device as a

master. Clearing the SREN and CREN bits of the RCSTA

otherwise the device will be configured to receive. Setting

the SPEN bit of the RCSTA register enables the

EUSART.

26.4.1.1 Master Clock

Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device config-

ured as a master transmits the clock on the TX/CK line.

The TX/CK pin output driver is automatically enabled

when the EUSART is configured for synchronous

transmit or receive operation. Serial data bits change

on the leading edge to ensure they are valid at the trail-

ing edge of each clock. One clock cycle is generated

for each data bit. Only as many clock cycles are gener-

ated as there are data bits.

26.4.1.2 Clock Polarity

A clock polarity option is provided for Microwire

compatibility. Clock polarity is selected with the SCKP

bit of the BAUDCON register. Setting the SCKP bit sets

the clock Idle state as high. When the SCKP bit is set,

the data changes on the falling edge of each clock.

Clearing the SCKP bit sets the Idle state as low. When

the SCKP bit is cleared, the data changes on the rising

edge of each clock.

26.4.1.3 Synchronous Master Transmission

Data is transferred out of the device on the RX/DT pin.

The RX/DT and TX/CK pin output drivers are automat-

ically enabled when the EUSART is configured for syn-

chronous master transmit operation.

A transmission is initiated by writing a character to the

TXREG register. If the TSR still contains all or part of a

previous character the new character data is held in the

TXREG until the last bit of the previous character has

been transmitted. If this is the first character, or the pre-

vious character has been completely flushed from the

TSR, the data in the TXREG is immediately transferred

to the TSR. The transmission of the character com-

mences immediately following the transfer of the data

to the TSR from the TXREG.

Each data bit changes on the leading edge of the mas-

ter clock and remains valid until the subsequent leading

clock edge.

26.4.1.4 Synchronous Master Transmission

Setup:

1. Initialize the SPBRGH, SPBRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 26.3 “EUSART

Baud Rate Generator (BRG)”).

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

3. Disable Receive mode by clearing bits SREN

and CREN.

4. Enable Transmit mode by setting the TXEN bit.

5. If 9-bit transmission is desired, set the TX9 bit.

6. If interrupts are desired, set the TXIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

7. If 9-bit transmission is selected, the ninth bit

should be loaded in the TX9D bit.

8. Start transmission by loading data to the TXREG

Note: The TSR register is not mapped in data

memory, so it is not available to the user.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 319

PIC16(L)F1824/1828

FIGURE 26-10: SYNCHRONOUS TRANSMISSION

FIGURE 26-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

TABLE 26-7: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER

TRANSMISSION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on

Page

APFCON0 RXDTSEL SDOSEL(1) SSSEL(1) —T1GSEL TXCKSEL — — 122

BAUDCON ABDOVF RCIDL — SCKP BRG16 —WUE ABDEN 308

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 94

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 97

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 307

SPBRGL BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 309*

SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 309*

TXREG EUSART Transmit Data Register 299*

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 306

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Transmission.

* Page provides register information.

Note 1: PIC16(L)F1824 only.

bit 0 bit 1 bit 7

Word 1

bit 2 bit 0 bit 1 bit 7

RX/DT

Write to

TXREG Reg

TXIF bit

(Interrupt Flag)

TXEN bit ‘1’ ‘1’

Word 2

TRMT bit

Write Word 1 Write Word 2

Note: Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.

TX/CK pin

(SCKP = 0)

(SCKP = 1)

RX/DT pin

TX/CK pin

Write to

TXREG reg

TXIF bit

TRMT bit

bit 0 bit 1 bit 2 bit 6 bit 7

TXEN bit

PIC16(L)F1824/1828

DS41419C-page 320 Preliminary  2010-2011 Microchip Technology Inc.

26.4.1.5 Synchronous Master Reception

Data is received at the RX/DT pin. The RX/DT pin

output driver is automatically disabled when the

EUSART is configured for synchronous master receive

operation.

In Synchronous mode, reception is enabled by setting

either the Single Receive Enable bit (SREN of the

RCSTA register) or the Continuous Receive Enable bit

(CREN of the RCSTA register).

When SREN is set and CREN is clear, only as many

clock cycles are generated as there are data bits in a

single character. The SREN bit is automatically cleared

at the completion of one character. When CREN is set,

clocks are continuously generated until CREN is

cleared. If CREN is cleared in the middle of a character

the CK clock stops immediately and the partial charac-

ter is discarded. If SREN and CREN are both set, then

SREN is cleared at the completion of the first character

and CREN takes precedence.

To initiate reception, set either SREN or CREN. Data is

sampled at the RX/DT pin on the trailing edge of the

TX/CK clock pin and is shifted into the Receive Shift

received into the RSR, the RCIF bit is set and the char-

acter is automatically transferred to the two character

receive FIFO. The Least Significant eight bits of the top

character in the receive FIFO are available in RCREG.

The RCIF bit remains set as long as there are unread

characters in the receive FIFO.

26.4.1.6 Slave Clock

Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device configured

as a slave receives the clock on the TX/CK line. The

TX/CK pin output driver is automatically disabled when

the device is configured for synchronous slave transmit

or receive operation. Serial data bits change on the

leading edge to ensure they are valid at the trailing edge

of each clock. One data bit is transferred for each clock

cycle. Only as many clock cycles should be received as

there are data bits.

26.4.1.7 Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be generated if a third character, in its

entirety, is received before RCREG is read to access

the FIFO. When this happens the OERR bit of the

RCSTA register is set. Previous data in the FIFO will

not be overwritten. The two characters in the FIFO

buffer can be read, however, no additional characters

will be received until the error is cleared. The OERR bit

can only be cleared by clearing the overrun condition.

If the overrun error occurred when the SREN bit is set

and CREN is clear then the error is cleared by reading

RCREG. If the overrun occurred when the CREN bit is

set then the error condition is cleared by either clearing

the CREN bit of the RCSTA register or by clearing the

SPEN bit which resets the EUSART.

26.4.1.8 Receiving 9-bit Characters

The EUSART supports 9-bit character reception. When

the RX9 bit of the RCSTA register is set the EUSART

will shift 9-bits into the RSR for each character

received. The RX9D bit of the RCSTA register is the

ninth, and Most Significant, data bit of the top unread

character in the receive FIFO. When reading 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the 8 Least Significant bits from

the RCREG.

26.4.1.9 Synchronous Master Reception

Setup:

1. Initialize the SPBRGH, SPBRGL register pair for

the appropriate baud rate. Set or clear the

BRGH and BRG16 bits, as required, to achieve

the desired baud rate.

2. Clear the ANSEL bit for the RX pin (if applicable).

3. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

4. Ensure bits CREN and SREN are clear.

5. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

6. If 9-bit reception is desired, set bit RX9.

7. Start reception by setting the SREN bit or for

continuous reception, set the CREN bit.

8. Interrupt flag bit RCIF will be set when reception

of a character is complete. An interrupt will be

generated if the enable bit RCIE was set.

9. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

10. Read the 8-bit received data by reading the

RCREG register.

11. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

the EUSART.

Note: If the RX/DT function is on an analog pin,

the corresponding ANSEL bit must be

cleared for the receiver to function.

Note: If the device is configured as a slave and

the TX/CK function is on an analog pin, the

corresponding ANSEL bit must be

cleared.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 321

PIC16(L)F1824/1828

FIGURE 26-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

TABLE 26-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER

RECEPTION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

APFCON0 RXDTSEL SDOSEL(1) SSSEL(1) —T1GSEL TXCKSEL — — 122

BAUDCON ABDOVF RCIDL — SCKP BRG16 —WUE ABDEN 308

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 94

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 97

RCREG EUSART Receive Data Register 302*

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 307

SPBRGL BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 309*

SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 309*

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 306

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Reception.

* Page provides register information.

Note 1: PIC16(L)F1824 only.

CREN bit

RX/DT

Write to

bit SREN

SREN bit

RCIF bit

(Interrupt)

Read

RCREG

‘0’

bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7

‘0’

Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.

TX/CK pin

(SCKP = 0)

(SCKP = 1)

PIC16(L)F1824/1828

DS41419C-page 322 Preliminary  2010-2011 Microchip Technology Inc.

26.4.2 SYNCHRONOUS SLAVE MODE

The following bits are used to configure the EUSART

for Synchronous slave operation:

• SYNC = 1

• CSRC = 0

• SREN = 0 (for transmit); SREN = 1 (for receive)

• CREN = 0 (for transmit); CREN = 1 (for receive)

• SPEN = 1

Setting the SYNC bit of the TXSTA register configures the

device for synchronous operation. Clearing the CSRC bit

of the TXSTA register configures the device as a slave.

Clearing the SREN and CREN bits of the RCSTA register

ensures that the device is in the Transmit mode,

otherwise the device will be configured to receive. Setting

the SPEN bit of the RCSTA register enables the

EUSART.

26.4.2.1 EUSART Synchronous Slave

Transmit

The operation of the Synchronous Master and Slave

modes are identical (see Section 26.4.1.3

“Synchronous Master Transmission”), except in the

case of the Sleep mode.

If two words are written to the TXREG and then the

SLEEP instruction is executed, the following will occur:

1. The first character will immediately transfer to

the TSR register and transmit.

2. The second word will remain in the TXREG

3. The TXIF bit will not be set.

4. After the first character has been shifted out of

TSR, the TXREG register will transfer the second

character to the TSR and the TXIF bit will now be

set.

5. If the PEIE and TXIE bits are set, the interrupt

will wake the device from Sleep and execute the

next instruction. If the GIE bit is also set, the

program will call the Interrupt Service Routine.

26.4.2.2 Synchronous Slave Transmission

Setup:

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

2. Clear the ANSEL bit for the CK pin (if applicable).

3. Clear the CREN and SREN bits.

4. If interrupts are desired, set the TXIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

5. If 9-bit transmission is desired, set the TX9 bit.

6. Enable transmission by setting the TXEN bit.

7. If 9-bit transmission is selected, insert the Most

Significant bit into the TX9D bit.

8. Start transmission by writing the Least

Significant 8 bits to the TXREG register.

TABLE 26-9: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE

TRANSMISSION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

APFCON0 RXDTSEL SDOSEL(1) SSSEL(1) —T1GSEL TXCKSEL — — 122

BAUDCON ABDOVF RCIDL —SCKPBRG16 —WUE ABDEN 308

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 94

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 97

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 307

TXREG EUSART Transmit Data Register 299*

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 306

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission.

* Page provides register information.

Note 1: PIC16(L)F1824 only.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 323

PIC16(L)F1824/1828

26.4.2.3 EUSART Synchronous Slave

Reception

The operation of the Synchronous Master and Slave

modes is identical (Section 26.4.1.5 “Synchronous

Master Reception”), with the following exceptions:

• Sleep

• CREN bit is always set, therefore the receiver is

never Idle

• SREN bit, which is a “don’t care” in Slave mode

A character may be received while in Sleep mode by

setting the CREN bit prior to entering Sleep. Once the

word is received, the RSR register will transfer the data

to the RCREG register. If the RCIE enable bit is set, the

interrupt generated will wake the device from Sleep

and execute the next instruction. If the GIE bit is also

set, the program will branch to the interrupt vector.

26.4.2.4 Synchronous Slave Reception

Setup:

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

2. Clear the ANSEL bit for both the CK and DT pins

(if applicable).

3. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

4. If 9-bit reception is desired, set the RX9 bit.

5. Set the CREN bit to enable reception.

6. The RCIF bit will be set when reception is

complete. An interrupt will be generated if the

RCIE bit was set.

7. If 9-bit mode is enabled, retrieve the Most

Significant bit from the RX9D bit of the RCSTA

8. Retrieve the 8 Least Significant bits from the

receive FIFO by reading the RCREG register.

9. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

the EUSART.

TABLE 26-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE

RECEPTION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

APFCON0 RXDTSEL SDOSEL(1) SSSEL(1) —T1GSEL TXCKSEL — — 122

BAUDCON ABDOVF RCIDL —SCKPBRG16 —WUE ABDEN 308

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 94

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 97

RCREG EUSART Receive Data Register 302*

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 307

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 306

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.

* Page provides register information.

Note 1: PIC16(L)F1824 only.

PIC16(L)F1824/1828

DS41419C-page 324 Preliminary  2010-2011 Microchip Technology Inc.

26.5 EUSART Operation During Sleep

The EUSART will remain active during Sleep only in the

Synchronous Slave mode. All other modes require the

system clock and therefore cannot generate the

necessary signals to run the Transmit or Receive Shift

registers during Sleep.

Synchronous Slave mode uses an externally generated

clock to run the Transmit and Receive Shift registers.

26.5.1 SYNCHRONOUS RECEIVE DURING

SLEEP

To receive during Sleep, all the following conditions

must be met before entering Sleep mode:

• RCSTA and TXSTA Control registers must be

configured for Synchronous Slave Reception (see

Section 26.4.2.4 “Synchronous Slave

Reception Setup:”).

• If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

• The RCIF interrupt flag must be cleared by read-

ing RCREG to unload any pending characters in

the receive buffer.

Upon entering Sleep mode, the device will be ready to

accept data and clocks on the RX/DT and TX/CK pins,

respectively. When the data word has been completely

clocked in by the external device, the RCIF interrupt

flag bit of the PIR1 register will be set. Thereby, waking

the processor from Sleep.

Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the Global Inter-

rupt Enable (GIE) bit of the INTCON register is also set,

then the Interrupt Service Routine at address 004h will

be called.

26.5.2 SYNCHRONOUS TRANSMIT

DURING SLEEP

To transmit during Sleep, all the following conditions

must be met before entering Sleep mode:

• RCSTA and TXSTA Control registers must be

configured for Synchronous Slave Transmission

(see Section 26.4.2.2 “Synchronous Slave

Transmission Setup:”).

• The TXIF interrupt flag must be cleared by writing

the output data to the TXREG, thereby filling the

TSR and transmit buffer.

• If interrupts are desired, set the TXIE bit of the

PIE1 register and the PEIE bit of the INTCON reg-

ister.

• Interrupt enable bits TXIE of the PIE1 register and

PEIE of the INTCON register must set.

Upon entering Sleep mode, the device will be ready to

accept clocks on the TX/CK pin and transmit data on

the RX/DT pin. When the data word in the TSR has

been completely clocked out by the external device, the

pending byte in the TXREG will transfer to the TSR and

the TXIF flag will be set. Thereby, waking the processor

from Sleep. At this point, the TXREG is available to

accept another character for transmission, which will

clear the TXIF flag.

Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the Global

Interrupt Enable (GIE) bit is also set then the Interrupt

Service Routine at address 0004h will be called.

26.5.3 ALTERNATE PIN LOCATIONS

This module incorporates I/O pins that can be moved to

other locations with the use of the alternate pin function

registers, APFCON0 and APFCON1. To determine

which pins can be moved and what their default

locations are upon a Reset, see Section 12.1

“Alternate Pin Function” for more information.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 325

PIC16(L)F1824/1828

27.0 CAPACITIVE SENSING

MODULE

The capacitive sensing module allows for an interaction

with an end user without a mechanical interface. In a

typical application, the capacitive sensing module is

attached to a pad on a Printed Circuit Board (PCB),

which is electrically isolated from the end user. When the

end user places their finger over the PCB pad, a

capacitive load is added, causing a frequency shift in the

capacitive sensing module. The capacitive sensing

module requires software and at least one timer

resource to determine the change in frequency. Key

features of this module include:

• Analog MUX for monitoring multiple inputs

• Capacitive sensing oscillator

• Multiple Power modes

• High power range with variable voltage references

• Multiple timer resources

• Software control

• Operation during Sleep

FIGURE 27-1: CAPACITIVE SENSING BLOCK DIAGRAM

Note 1: Reference CPSCON1 register (Register 27-2) for channels implemented on each device.

2: If CPSON = 0, disabling capacitive sensing, no channel is selected.

TMR0CS

CPS0

CPS1

CPS2

CPS3

CPS4

CPS5

CPS6

CPSCH<3:0>

Capacitive

Sensing

Oscillator

CPSOSC

CPSON

CPSRNG<1:0>

TMR0

Set

TMR0IF

Overflow

T0XCS

T0CKI

CPSOUT

CPS7

CPSCLK

FOSC/4

Timer0 Module

CPSON(2)

T1CS<1:0>

T1OSC/

T1CKI

TMR1H:TMR1L

T1GSEL<1:0>

Timer1 Gate

Control Logic

T1G

FOSC

FOSC/4

Timer1 Module

SYNCC1OUT

SYNCC2OUT

Int.

Ref.

FVR

DAC

Ref+

Ref-

CPSRM

CPS9(1)

CPS10(1)

CPS11(1)

CPS8(1)

PIC16(L)F1824/1828

DS41419C-page 326 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 27-2: CAPACITIVE SENSING OSCILLATOR BLOCK DIAGRAM

Note 1: Module Enable and Power mode selections are not shown.

2: Comparators remain active in Noise Detection mode.

VDD

CPSCLK

Oscillator Module

CPSx SQ

(2)

(1)

(1) (2)

Internal

References

FVR

DAC

CPSRM

Analog Pin

Ref- Ref+

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 327

PIC16(L)F1824/1828

27.1 Analog MUX

The capacitive sensing module can monitor up to four

inputs for the PIC16(L)F1824 (CPSCH<7:0>) and up to

eight inputs for the PIC16(L)F1828 (CPSCH<11:0>).

See Register 27-2 for details. The capacitive sensing

inputs are defined as CPS<11:0>, as applicable to

device. To determine if a frequency change has

occurred the user must:

• Select the appropriate CPS pin by setting the

appropriate CPSCH bits of the CPSCON1 register

• Set the corresponding ANSEL bit

• Set the corresponding TRIS bit

• Run the software algorithm

Selection of the CPSx pin while the module is enabled

will cause the capacitive sensing oscillator to be on the

CPSx pin. Failure to set the corresponding ANSEL and

TRIS bits can cause the capacitive sensing oscillator to

stop, leading to false frequency readings.

27.2 Capacitive Sensing Oscillator

The capacitive sensing oscillator consists of a constant

current source and a constant current sink, to produce

a triangle waveform. The CPSOUT bit of the

CPSCON0 register shows the status of the capacitive

sensing oscillator, whether it is a sinking or sourcing

current. The oscillator is designed to drive a capacitive

load (single PCB pad) and at the same time, be a clock

source to either Timer0 or Timer1. The oscillator has

three different current settings as defined by

CPSRNG<1:0> of the CPSCON0 register. The different

current settings for the oscillator serve two purposes:

• Maximize the number of counts in a timer for a

fixed time base.

• Maximize the count differential in the timer during

a change in frequency.

27.3 Voltage References

The capacitive sensing oscillator uses voltage refer-

ences to provide two voltage thresholds for oscillation.

The upper voltage threshold is referred to as Ref+ and

the lower voltage threshold is referred to as Ref-.

The user can elect to use fixed voltage references,

which are internal to the capacitive sensing oscillator,

or variable voltage references, which are supplied by

the Fixed Voltage Reference (FVR) module and the

Digital-to-Analog Converter (DAC) module.

When the fixed voltage references are used, the VSS

voltage determines the lower threshold level (Ref-) and

the VDD voltage determines the upper threshold level

(Ref+).

When the variable voltage references are used, the

DAC voltage determines the lower threshold level

(Ref-) and the FVR voltage determines the upper

threshold level (Ref+). An advantage of using these ref-

erence sources is that oscillation frequency remains

constant with changes in VDD.

Different oscillation frequencies can be obtained

through the use of these variable voltage references.

The more the upper voltage reference level is lowered

and the more the lower voltage reference level is

raised, the higher the capacitive sensing oscillator

frequency becomes.

Selection between the voltage references is controlled

by the CPSRM bit of the CPSCON0 register. Setting

this bit selects the variable voltage references and

clearing this bit selects the fixed voltage references.

Please see Section 14.0 “Fixed Voltage Reference

(FVR)” and Section 17.0 “Digital-to-Analog Converter

(DAC) Module” for more information on configuring the

variable voltage levels.

PIC16(L)F1824/1828

DS41419C-page 328 Preliminary  2010-2011 Microchip Technology Inc.

27.4 Power Modes

The capacitive sensing oscillator can operate in one of

seven different power modes. The power modes are

separated into two ranges; the low range and the high

range.

When the oscillator’s low range is selected, the fixed

internal voltage references of the capacitive sensing

oscillator are being used. When the oscillator’s high

range is selected, the variable voltage references

supplied by the FVR and DAC modules are being used.

Selection between the voltage references is controlled

by the CPSRM bit of the CPSCON0 register. See

Section 27.3 “Voltage References” for more

information.

Within each range there are three distinct Power modes;

low, medium and high. Current consumption is dependent

upon the range and mode selected. Selecting Power

modes within each range is accomplished by configuring

the CPSRNG <1:0> bits in the CPSCON0 register. See

Table 27-1 for proper Power mode selection.

The remaining mode is a Noise Detection mode that

resides within the high range. The Noise Detection

mode is unique in that it disables the sinking and sourc-

ing of current on the analog pin but leaves the rest of

the oscillator circuitry active. This reduces the oscilla-

tion frequency on the analog pin to zero and also

greatly reduces the current consumed by the oscillator

module.

When noise is introduced onto the pin, the oscillator is

driven at the frequency determined by the noise. This

produces a detectable signal at the comparator output,

indicating the presence of activity on the pin.

Figure 27-2 shows a more detailed drawing of the

current sources and comparators associated with the

oscillator.

TABLE 27-1: POWER MODE SELECTION

CPSRM Range CPSRNG<1:0> Mode Nominal Current(1)

0Low

00 Off 0.0 A

01 Low 0.1 A

10 Medium 1.2 A

11 High 18 A

1High

00 Noise Detection 0.0 A

01 Low 9 A

10 Medium 30 A

11 High 100 A

Note 1: See Section 30.0 “Electrical Specifications” for more information.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 329

PIC16(L)F1824/1828

27.5 Timer Resources

To measure the change in frequency of the capacitive

sensing oscillator, a fixed time base is required. For the

period of the fixed time base, the capacitive sensing

oscillator is used to clock either Timer0 or Timer1. The

frequency of the capacitive sensing oscillator is equal

to the number of counts in the timer divided by the

period of the fixed time base.

27.6 Fixed Time Base

To measure the frequency of the capacitive sensing

oscillator, a fixed time base is required. Any timer

resource or software loop can be used to establish the

fixed time base. It is up to the end user to determine the

method in which the fixed time base is generated.

27.6.1 TIMER0

To select Timer0 as the timer resource for the capacitive

sensing module:

• Set the T0XCS bit of the CPSCON0 register

• Clear the TMR0CS bit of the OPTION_REG regis-

ter

When Timer0 is chosen as the timer resource, the

capacitive sensing oscillator will be the clock source for

Timer0. Refer to Section 20.0 “Timer0 Module” for

additional information.

27.6.2 TIMER1

To select Timer1 as the timer resource for the

capacitive sensing module, set the TMR1CS<1:0> of

the T1CON register to ‘11’. When Timer1 is chosen as

the timer resource, the capacitive sensing oscillator will

be the clock source for Timer1. Because the Timer1

module has a gate control, developing a time base for

the frequency measurement can be simplified by using

the Timer0 overflow flag.

It is recommend that the Timer0 overflow flag, in con-

junction with the Toggle mode of the Timer1 Gate, be

used to develop the fixed time base required by the

software portion of the capacitive sensing module.

Refer to Section “” for additional information.

TABLE 27-2: TIMER1 ENABLE FUNCTION

27.7 Software Control

The software portion of the capacitive sensing module

is required to determine the change in frequency of the

capacitive sensing oscillator. This is accomplished by

the following:

• Setting a fixed time base to acquire counts on

Timer0 or Timer1

• Establishing the nominal frequency for the

capacitive sensing oscillator

• Establishing the reduced frequency for the

capacitive sensing oscillator due to an additional

capacitive load

• Set the frequency threshold

27.7.1 NOMINAL FREQUENCY

(NO CAPACITIVE LOAD)

To determine the nominal frequency of the capacitive

sensing oscillator:

• Remove any extra capacitive load on the selected

CPSx pin

• At the start of the fixed time base, clear the timer

resource

• At the end of the fixed time base save the value in

the timer resource

The value of the timer resource is the number of

oscillations of the capacitive sensing oscillator for the

given time base. The frequency of the capacitive

sensing oscillator is equal to the number of counts on

in the timer divided by the period of the fixed time base.

27.7.2 REDUCED FREQUENCY

(ADDITIONAL CAPACITIVE LOAD)

The extra capacitive load will cause the frequency of the

capacitive sensing oscillator to decrease. To determine

the reduced frequency of the capacitive sensing

oscillator:

• Add a typical capacitive load on the selected

CPSx pin

• Use the same fixed time base as the nominal

frequency measurement

• At the start of the fixed time base, clear the timer

resource

• At the end of the fixed time base save the value in

the timer resource

The value of the timer resource is the number of oscil-

lations of the capacitive sensing oscillator with an addi-

tional capacitive load. The frequency of the capacitive

sensing oscillator is equal to the number of counts on

in the timer divided by the period of the fixed time base.

This frequency should be less than the value obtained

during the nominal frequency measurement.

Note: The fixed time base can not be generated

by the timer resource that the capacitive

sensing oscillator is clocking.

TMR1ON TMR1GE Timer1 Operation

00 Off

01 Off

10 On

11Count Enabled by input

PIC16(L)F1824/1828

DS41419C-page 330 Preliminary  2010-2011 Microchip Technology Inc.

27.7.3 FREQUENCY THRESHOLD

The frequency threshold should be placed midway

between the value of nominal frequency and the

reduced frequency of the capacitive sensing oscillator.

Refer to Application Note AN1103, “Software Handling

for Capacitive Sensing” (DS01103) for more detailed

information on the software required for capacitive

sensing module.

27.8 Operation during Sleep

The capacitive sensing oscillator will continue to run as

long as the module is enabled, independent of the part

being in Sleep. In order for the software to determine if

a frequency change has occurred, the part must be

awake. However, the part does not have to be awake

when the timer resource is acquiring counts.

Note: For more information on general capacitive

sensing refer to Application Notes:

• AN1101, “Introduction to Capacitive

Sensing” (DS01101)

• AN1102, “Layout and Physical

Design Guidelines for Capacitive

Sensing” (DS01102)

Note: Timer0 does not operate when in Sleep,

and therefore cannot be used for

capacitive sense measurements in Sleep.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 331

PIC16(L)F1824/1828

R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R-0/0 R/W-0/0

CPSON CPSRM —— CPSRNG<1:0> CPSOUT T0XCS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 CPSON: Capacitive Sensing Module Enable bit

1 = Capacitive sensing module is enabled

0 = Capacitive sensing module is disabled

bit 6 CPSRM: Capacitive Sensing Reference Mode bit

1 = Capacitive Sensing module is in high range. DAC and FVR provide oscillator voltage references.

0 = Capacitive Sensing module is in the low range. Internal oscillator voltage references are used.

bit 5-4 Unimplemented: Read as ‘0’

bit 3-2 CPSRNG<1:0>: Capacitive Sensing Current Range bits

If CPSRM = 0 (low range):

00 = Oscillator is off

01 = Oscillator is in Low Range. Charge/Discharge Current is nominally 0.1 µA

10 = Oscillator is in Medium Range. Charge/Discharge Current is nominally 1.2 µA

11 = Oscillator is in High Range. Charge/Discharge Current is nominally 18 µA

If CPSRM = 1 (high range):

00 = Oscillator is on. Noise Detection mode. No Charge/Discharge current is supplied.

01 = Oscillator is in Low Range. Charge/Discharge Current is nominally 9 µA

10 = Oscillator is in Medium Range. Charge/Discharge Current is nominally 30 µA

11 = Oscillator is in High Range. Charge/Discharge Current is nominally 100 µA

bit 1 CPSOUT: Capacitive Sensing Oscillator Status bit

1 = Oscillator is sourcing current (Current flowing out of the pin)

0 = Oscillator is sinking current (Current flowing into the pin)

bit 0 T0XCS: Timer0 External Clock Source Select bit

If TMR0CS = 1:

The T0XCS bit controls which clock external to the core/Timer0 module supplies Timer0:

1 = Timer0 clock source is the capacitive sensing oscillator

0 = Timer0 clock source is the T0CKI pin

If TMR0CS = 0:

Timer0 clock source is controlled by the core/Timer0 module and is FOSC/4

PIC16(L)F1824/1828

DS41419C-page 332 Preliminary  2010-2011 Microchip Technology Inc.

TABLE 27-3: SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING

U-0 U-0 U-0 U-0 R/W-0/0(1) R/W-0/0 R/W-0/0 R/W-0/0

— — — — CPSCH<3:2> CPSCH<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 CPSCH<3:0>: Capacitive Sensing Channel Select bits

If CPSON = 0:

These bits are ignored. No channel is selected.

If CPSON = 1:

0000 = channel 0, (CPS0)

0001 = channel 1, (CPS1)

0010 = channel 2, (CPS2)

0011 = channel 3, (CPS3)

0100 = channel 4, (CPS4)

0101 = channel 5, (CPS5)

0110 = channel 6, (CPS6)

0111 = channel 7, (CPS7)

1000 = channel 8, (CPS4)(1)

1001 = channel 9, (CPS5)(1)

1010 = channel 10, (CPS6)(1)

1011 = channel 11, (CPS7)(1)

1100 = Reserved. Do not use.

•

1111 = Reserved. Do not use.

Note 1: These channels are only implemented on the PIC16(L)F1828.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

ANSELA ———ANSA4— ANSA2 ANSA1 ANSA0 127

ANSELC ANSC7 ANSC6 —— ANSC3 ANSC2 ANSC1 ANSC0 138

CPSCON0 CPSON CPSRM —— CPSRNG1 CPSRNG0 CPSOUT T0XCS 331

CPSCON1 ———— CPSCH3 CPSCH2 CPSCH1 CPSCH0 332

INLVLA — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 128

INLVLB(1) INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — — 133

INLVLC INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 139

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93

OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 187

T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC —TMR1ON

197

TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 126

TRISB(1) TRISB7 TRISB6 TRISB5 TRISB4 — — — — 132

TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 137

Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the capacitive sensing module.

Note 1: PIC16(L)F1828 only.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 333

PIC16(L)F1824/1828

28.0 IN-CIRCUIT SERIAL

PROGRAMMING™ (ICSP™)

ICSP™ programming allows customers to manufacture

circuit boards with unprogrammed devices. Programming

can be done after the assembly process allowing the

device to be programmed with the most recent firmware

or a custom firmware. Five pins are needed for ICSP™

programming:

• ICSPCLK

• ICSPDAT

•MCLR

/VPP

•VDD

•VSS

In Program/Verify mode the Program Memory, User IDs

and the Configuration Words are programmed through

serial communications. The ICSPDAT pin is a bidirec-

tional I/O used for transferring the serial data and the

ICSPCLK pin is the clock input. For more information on

ICSP™ refer to the “PIC16F/LF182X/PIC12F/LF1822

Memory Programming Specification” (DS41390).

28.1 High-Voltage Programming Entry

Mode

The device is placed into High-Voltage Programming

Entry mode by holding the ICSPCLK and ICSPDAT

pins low then raising the voltage on MCLR/VPP to VIHH.

Some programmers produce VPP greater than VIHH

(9.0V), an external circuit is required to limit the VPP

voltage. See Figure 28-1 for example circuit.

FIGURE 28-1: VPP LIMITER EXAMPLE CIRCUIT

VREF

VPP

VDD

VSS

ICSP_DATA

ICSP_CLOCK

RJ11-6PIN

270 Ohm

To M P L A B ® ICD 2 To Tar get B o ard

R2 R3

10k 1% 24k 1%

LM431BCMX

Note: The MPLAB ICD 2 produces a VPP volt-

age greater than the maximum VPP spec-

ification of the PIC16F/LF1824/1828.

PIC16(L)F1824/1828

DS41419C-page 334 Preliminary  2010-2011 Microchip Technology Inc.

28.2 Low-Voltage Programming Entry

Mode

The Low-Voltage Programming Entry mode allows the

PIC16F/LF1824/1828 devices to be programmed using

VDD only, without high voltage. When the LVP bit of

Configuration Word 2 is set to ‘1’, the low-voltage ICSP

programming entry is enabled. To disable the

Low-Voltage ICSP mode, the LVP bit must be

programmed to ‘0’.

Entry into the Low-Voltage Programming Entry mode

requires the following steps:

1. MCLR is brought to VIL.

2. A 32-bit key sequence is presented on

ICSPDAT, while clocking ICSPCLK.

Once the key sequence is complete, MCLR must be

held at VIL for as long as Program/Verify mode is to be

maintained.

If low-voltage programming is enabled (LVP = 1), the

MCLR Reset function is automatically enabled and

cannot be disabled. See Section 7.3 “MCLR” for more

information.

The LVP bit can only be reprogrammed to ‘0’ by using

the High-Voltage Programming mode.

28.3 Common Programming Interfaces

Connection to a target device is typically done through

an ICSP™ header. A commonly found connector on

development tools is the RJ-11 in the 6P6C (6 pin, 6

connector) configuration. See Figure 28-2.

FIGURE 28-2: ICD RJ-11 STYLE

CONNECTOR INTERFACE

Another connector often found in use with the PICkit™

programmers is a standard 6-pin header with 0.1 inch

spacing. Refer to Figure 28-3.

FIGURE 28-3: PICkit™ STYLE CONNECTOR INTERFACE

Target

Bottom Side

PC Board

VPP/MCLR VSS

ICSPCLK

VDD

ICSPDAT

Pin Description*

1 = VPP/MCLR

2 = VDD Target

3 = VSS (ground)

4 = ICSPDAT

5 = ICSPCLK

6 = No Connect

* The 6-pin header (0.100" spacing) accepts 0.025" square pins.

Pin Description*

1 = VPP/MCLR

2 = VDD Target

3 = VSS (ground)

4 = ICSPDAT

5 = ICSPCLK

6 = No Connect

Pin 1 Indicator

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 335

PIC16(L)F1824/1828

For additional interface recommendations, refer to your

specific device programmer manual prior to PCB

design.

It is recommended that isolation devices be used to

separate the programming pins from other circuitry.

The type of isolation is highly dependent on the specific

application and may include devices such as resistors,

diodes, or even jumpers. See Figure 28-4 for more

information.

FIGURE 28-4: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING

VDD

VPP

VSS

External

Device to be

Data

Clock

VDD

MCLR/VPP

VSS

ICSPDAT

ICSPCLK

To Normal Connections

*Isolation devices (as required).

Programming

Signals Programmed

VDD

PIC16(L)F1824/1828

DS41419C-page 336 Preliminary  2010-2011 Microchip Technology Inc.

NOTES:

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 337

PIC16(L)F1824/1828

29.0 INSTRUCTION SET SUMMARY

Each PIC16 instruction is a 14-bit word containing the

operation code (opcode) and all required operands.

The opcodes are broken into three broad categories.

• Byte Oriented

• Bit Oriented

• Literal and Control

The literal and control category contains the most var-

ied instruction word format.

Table 29-3 lists the instructions recognized by the

MPASMTM assembler.

All instructions are executed within a single instruction

cycle, with the following exceptions, which may take

two or three cycles:

• Subroutine takes two cycles (CALL, CALLW)

• Returns from interrupts or subroutines take two

cycles (RETURN, RETLW, RETFIE)

• Program branching takes two cycles (GOTO, BRA,

BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)

• One additional instruction cycle will be used when

any instruction references an indirect file register

and the file select register is pointing to program

memory.

One instruction cycle consists of 4 oscillator cycles; for

an oscillator frequency of 4 MHz, this gives a nominal

instruction execution rate of 1 MHz.

All instruction examples use the format ‘0xhh’ to

represent a hexadecimal number, where ‘h’ signifies a

hexadecimal digit.

29.1 Read-Modify-Write Operations

Any instruction that specifies a file register as part of

the instruction performs a Read-Modify-Write (R-M-W)

operation. The register is read, the data is modified,

and the result is stored according to either the instruc-

tion, or the destination designator ‘d’. A read operation

is performed on a register even if the instruction writes

to that register.

TABLE 29-1: OPCODE FIELD

DESCRIPTIONS

TABLE 29-2: ABBREVIATION

DESCRIPTIONS

Field Description

fRegister file address (0x00 to 0x7F)

WWorking register (accumulator)

bBit address within an 8-bit file register

kLiteral field, constant data or label

xDon’t care location (= 0 or 1).

The assembler will generate code with x = 0.

It is the recommended form of use for

compatibility with all Microchip software tools.

dDestination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1.

nFSR or INDF number. (0-1)

mm Pre-post increment-decrement mode

selection

Field Description

PC Program Counter

TO Time-out bit

CCarry bit

DC Digit carry bit

ZZero bit

PD Power-down bit

PIC16(L)F1824/1828

DS41419C-page 338 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 29-1: GENERAL FORMAT FOR

INSTRUCTIONS

Byte-oriented file register operations

13 8 7 6 0

d = 0 for destination W

OPCODE d f (FILE #)

d = 1 for destination f

f = 7-bit file register address

Bit-oriented file register operations

13 10 9 7 6 0

OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

13 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

13 11 10 0

OPCODE k (literal)

k = 11-bit immediate value

General

CALL and GOTO instructions only

MOVLP instruction only

13 5 4 0

OPCODE k (literal)

k = 5-bit immediate value

MOVLB instruction only

13 9 8 0

OPCODE k (literal)

k = 9-bit immediate value

BRA instruction only

FSR Offset instructions

13 7 6 5 0

OPCODE n k (literal)

n = appropriate FSR

FSR Increment instructions

13 7 6 0

OPCODE k (literal)

k = 7-bit immediate value

13 3 2 1 0

OPCODE n m (mode)

n = appropriate FSR

m = 2-bit mode value

k = 6-bit immediate value

13 0

OPCODE

OPCODE only

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 339

PIC16(L)F1824/1828

TABLE 29-3: PIC16F/LF1824/1828 ENHANCED INSTRUCTION SET

Mnemonic,

Operands Description Cycles

14-Bit Opcode Status

Affected Notes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ADDWFC

ANDWF

ASRF

LSLF

LSRF

CLRF

CLRW

COMF

DECF

INCF

IORWF

MOVF

MOVWF

RLF

RRF

SUBWF

SUBWFB

SWAPF

XORWF

f, d

–

f, d

Add W and f

Add with Carry W and f

AND W with f

Arithmetic Right Shift

Logical Left Shift

Logical Right Shift

Clear f

Clear W

Complement f

Decrement f

Increment f

Inclusive OR W with f

Move f

Move W to f

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Subtract with Borrow W from f

Swap nibbles in f

Exclusive OR W with f

0111

1101

0101

0111

0101

0110

0001

1001

0011

1010

0100

1000

0000

1101

1100

0010

1011

1110

0110

dfff

lfff

0000

dfff

1fff

dfff

ffff

00xx

ffff

C, DC, Z

C, Z

C, DC, Z

BYTE ORIENTED SKIP OPERATIONS

DECFSZ

INCFSZ

f, d

Decrement f, Skip if 0

Increment f, Skip if 0

1(2)

1011

1111

dfff

ffff

1, 2

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

f, b

Bit Clear f

Bit Set f

00bb

01bb

bfff

ffff

BIT-ORIENTED SKIP OPERATIONS

BTFSC

BTFSS

f, b

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1 (2)

10bb

11bb

bfff

ffff

1, 2

LITERAL OPERATIONS

ADDLW

ANDLW

IORLW

MOVLB

MOVLP

MOVLW

SUBLW

XORLW

Add literal and W

AND literal with W

Inclusive OR literal with W

Move literal to BSR

Move literal to PCLATH

Move literal to W

Subtract W from literal

Exclusive OR literal with W

1110

1001

1000

0000

0001

0000

1100

1010

kkkk

001k

1kkk

kkkk

C, DC, Z

Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle

is executed as a NOP.

2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one

additional instruction cycle.

PIC16(L)F1824/1828

DS41419C-page 340 Preliminary  2010-2011 Microchip Technology Inc.

TABLE 29-3: PIC16F/LF1824/1828 ENHANCED INSTRUCTION SET (CONTINUED)

Mnemonic,

Operands Description Cycles

14-Bit Opcode Status

Affected Notes

MSb LSb

CONTROL OPERATIONS

BRA

BRW

CALL

CALLW

GOTO

RETFIE

RETLW

RETURN

–

Relative Branch

Relative Branch with W

Call Subroutine

Call Subroutine with W

Go to address

Return from interrupt

Return with literal in W

Return from Subroutine

001k

0000

0kkk

0000

1kkk

0000

0100

0000

kkkk

0000

kkkk

0000

kkkk

0000

kkkk

0000

kkkk

1011

kkkk

1010

kkkk

1001

kkkk

1000

INHERENT OPERATIONS

CLRWDT

NOP

OPTION

RESET

SLEEP

TRIS

–

Clear Watchdog Timer

No Operation

Load OPTION_REG register with W

Software device Reset

Go into Standby mode

Load TRIS register with W

0000

0110

0000

0110

0000

0110

0100

0000

0010

0001

0011

0fff

TO, PD

C-COMPILER OPTIMIZED

ADDFSR

MOVIW

MOVWI

n, k

n mm

k[n]

n mm

k[n]

Add Literal k to FSRn

Move Indirect FSRn to W with pre/post inc/dec

modifier, mm

Move INDFn to W, Indexed Indirect.

Move W to Indirect FSRn with pre/post inc/dec

modifier, mm

Move W to INDFn, Indexed Indirect.

0001

0000

1111

0000

1111

0nkk

0001

0nkk

0001

1nkk

kkkk

0nmm

kkkk

1nmm

kkkk

2, 3

Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle

is executed as a NOP.

2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require

one additional instruction cycle.

3: See Table in the MOVIW and MOVWI instruction descriptions.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 341

PIC16(L)F1824/1828

29.2 Instruction Descriptions

ADDFSR Add Literal to FSRn

Syntax: [ label ] ADDFSR FSRn, k

Operands: -32  k  31

n  [ 0, 1]

Operation: FSR(n) + k  FSR(n)

Status Affected: None

Description: The signed 6-bit literal ‘k’ is added to

the contents of the FSRnH:FSRnL

FSRn is limited to the range 0000h -

FFFFh. Moving beyond these bounds

will cause the FSR to wrap around.

ADDLW Add literal and W

Syntax: [ label ] ADDLW k

Operands: 0  k  255

Operation: (W) + k  (W)

Status Affected: C, DC, Z

Description: The contents of the W register are

added to the eight-bit literal ‘k’ and the

result is placed in the W register.

ADDWF Add W and f

Syntax: [ label ] ADDWF f,d

Operands: 0  f  127

d 0,1

Operation: (W) + (f)  (destination)

Status Affected: C, DC, Z

Description: Add the contents of the W register

with register ‘f’. If ‘d’ is ‘0’, the result is

stored in the W register. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

ADDWFC ADD W and CARRY bit to f

Syntax: [ label ] ADDWFC f {,d}

Operands: 0  f  127

d [0,1]

Operation: (W) + (f) + (C)  dest

Status Affected: C, DC, Z

Description: Add W, the Carry flag and data mem-

ory location ‘f’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed in data memory location ‘f’.

ANDLW AND literal with W

Syntax: [ label ] ANDLW k

Operands: 0  k  255

Operation: (W) .AND. (k)  (W)

Status Affected: Z

Description: The contents of W register are

AND’ed with the eight-bit literal ‘k’.

The result is placed in the W register.

ANDWF AND W with f

Syntax: [ label ] ANDWF f,d

Operands: 0  f  127

d 0,1

Operation: (W) .AND. (f)  (destination)

Status Affected: Z

Description: AND the W register with register ‘f’. If

‘d’ is ‘0’, the result is stored in the W

back in register ‘f’.

ASRF Arithmetic Right Shift

Syntax: [ label ] ASRF f {,d}

Operands: 0  f  127

d [0,1]

Operation: (f<7>) dest<7>

(f<7:1>)  dest<6:0>,

(f<0>)  C,

Status Affected: C, Z

Description: The contents of register ‘f’ are shifted

one bit to the right through the Carry

flag. The MSb remains unchanged. If

‘d’ is ‘0’, the result is placed in W. If ‘d’

is ‘1’, the result is stored back in reg-

ister ‘f’.

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BCF Bit Clear f

Syntax: [ label ] BCF f,b

Operands: 0  f  127

0  b  7

Operation: 0  (f<b>)

Status Affected: None

Description: Bit ‘b’ in register ‘f’ is cleared.

BRA Relative Branch

Syntax: [ label ] BRA label

[ label ] BRA $+k

Operands: -256 label - PC + 1 255

-256  k  255

Operation: (PC) + 1 + k  PC

Status Affected: None

Description: Add the signed 9-bit literal ‘k’ to the

PC. Since the PC will have incre-

mented to fetch the next instruction,

the new address will be PC + 1 + k.

This instruction is a two-cycle instruc-

tion. This branch has a limited range.

BRW Relative Branch with W

Syntax: [ label ] BRW

Operands: None

Operation: (PC) + (W)  PC

Status Affected: None

Description: Add the contents of W (unsigned) to

the PC. Since the PC will have incre-

mented to fetch the next instruction,

the new address will be PC + 1 + (W).

This instruction is a two-cycle instruc-

tion.

BSF Bit Set f

Syntax: [ label ] BSF f,b

Operands: 0  f  127

0  b  7

Operation: 1  (f<b>)

Status Affected: None

Description: Bit ‘b’ in register ‘f’ is set.

BTFSC Bit Test f, Skip if Clear

Syntax: [ label ] BTFSC f,b

Operands: 0  f  127

0  b  7

Operation: skip if (f<b>) = 0

Status Affected: None

Description: If bit ‘b’ in register ‘f’ is ‘1’, the next

instruction is executed.

If bit ‘b’, in register ‘f’, is ‘0’, the next

instruction is discarded, and a NOP is

executed instead, making this a

2-cycle instruction.

BTFSS Bit Test f, Skip if Set

Syntax: [ label ] BTFSS f,b

Operands: 0  f  127

0  b < 7

Operation: skip if (f<b>) = 1

Status Affected: None

Description: If bit ‘b’ in register ‘f’ is ‘0’, the next

instruction is executed.

If bit ‘b’ is ‘1’, then the next

instruction is discarded and a NOP is

executed instead, making this a

2-cycle instruction.

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PIC16(L)F1824/1828

CALL Call Subroutine

Syntax: [ label ] CALL k

Operands: 0  k  2047

Operation: (PC)+ 1 TOS,

k  PC<10:0>,

(PCLATH<4:3>)  PC<12:11>

Status Affected: None

Description: Call Subroutine. First, return address

(PC + 1) is pushed onto the stack.

The eleven-bit immediate address is

loaded into PC bits <10:0>. The upper

bits of the PC are loaded from

PCLATH. CALL is a two-cycle instruc-

tion.

CALLW Subroutine Call With W

Syntax: [ label ] CALLW

Operands: None

Operation: (PC) +1  TOS,

(W)  PC<7:0>,

(PCLATH<6:0>) PC<14:8>

Status Affected: None

Description: Subroutine call with W. First, the

return address (PC + 1) is pushed

onto the return stack. Then, the con-

tents of W is loaded into PC<7:0>,

and the contents of PCLATH into

PC<14:8>. CALLW is a two-cycle

instruction.

CLRF Clear f

Syntax: [ label ] CLRF f

Operands: 0  f  127

Operation: 00h  (f)

1  Z

Status Affected: Z

Description: The contents of register ‘f’ are cleared

and the Z bit is set.

CLRW Clear W

Syntax: [ label ] CLRW

Operands: None

Operation: 00h  (W)

1  Z

Status Affected: Z

Description: W register is cleared. Zero bit (Z) is

set.

CLRWDT Clear Watchdog Timer

Syntax: [ label ] CLRWDT

Operands: None

Operation: 00h  WDT

0  WDT prescaler,

1  TO

1  PD

Status Affected: TO, PD

Description: CLRWDT instruction resets the Watch-

dog Timer. It also resets the prescaler

of the WDT.

Status bits TO and PD are set.

COMF Complement f

Syntax: [ label ] COMF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f)  (destination)

Status Affected: Z

Description: The contents of register ‘f’ are com-

plemented. If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

DECF Decrement f

Syntax: [ label ] DECF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f) - 1  (destination)

Status Affected: Z

Description: Decrement register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W

back in register ‘f’.

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DECFSZ Decrement f, Skip if 0

Syntax: [ label ] DECFSZ f,d

Operands: 0  f  127

d  [0,1]

Operation: (f) - 1  (destination);

skip if result = 0

Status Affected: None

Description: The contents of register ‘f’ are decre-

mented. If ‘d’ is ‘0’, the result is placed

in the W register. If ‘d’ is ‘1’, the result

is placed back in register ‘f’.

If the result is ‘1’, the next instruction is

executed. If the result is ‘0’, then a

NOP is executed instead, making it a

2-cycle instruction.

GOTO Unconditional Branch

Syntax: [ label ] GOTO k

Operands: 0  k  2047

Operation: k  PC<10:0>

PCLATH<4:3>  PC<12:11>

Status Affected: None

Description: GOTO is an unconditional branch. The

eleven-bit immediate value is loaded

into PC bits <10:0>. The upper bits of

PC are loaded from PCLATH<4:3>.

GOTO is a two-cycle instruction.

INCF Increment f

Syntax: [ label ] INCF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f) + 1  (destination)

Status Affected: Z

Description: The contents of register ‘f’ are incre-

mented. If ‘d’ is ‘0’, the result is placed

in the W register. If ‘d’ is ‘1’, the result

is placed back in register ‘f’.

INCFSZ Increment f, Skip if 0

Syntax: [ label ] INCFSZ f,d

Operands: 0  f  127

d  [0,1]

Operation: (f) + 1  (destination),

skip if result = 0

Status Affected: None

Description: The contents of register ‘f’ are incre-

mented. If ‘d’ is ‘0’, the result is placed

in the W register. If ‘d’ is ‘1’, the result

is placed back in register ‘f’.

If the result is ‘1’, the next instruction is

executed. If the result is ‘0’, a NOP is

executed instead, making it a 2-cycle

instruction.

IORLW Inclusive OR literal with W

Syntax: [ label ] IORLW k

Operands: 0  k  255

Operation: (W) .OR. k  (W)

Status Affected: Z

Description: The contents of the W register are

OR’ed with the eight-bit literal ‘k’. The

result is placed in the W register.

IORWF Inclusive OR W with f

Syntax: [ label ] IORWF f,d

Operands: 0  f  127

d  [0,1]

Operation: (W) .OR. (f)  (destination)

Status Affected: Z

Description: Inclusive OR the W register with regis-

ter ‘f’. If ‘d’ is ‘0’, the result is placed in

the W register. If ‘d’ is ‘1’, the result is

placed back in register ‘f’.

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PIC16(L)F1824/1828

LSLF Logical Left Shift

Syntax: [ label ] LSLF f {,d}

Operands: 0  f  127

d [0,1]

Operation: (f<7>)  C

(f<6:0>)  dest<7:1>

0  dest<0>

Status Affected: C, Z

Description: The contents of register ‘f’ are shifted

one bit to the left through the Carry flag.

A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’,

the result is placed in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

LSRF Logical Right Shift

Syntax: [ label ] LSLF f {,d}

Operands: 0  f  127

d [0,1]

Operation: 0  dest<7>

(f<7:1>)  dest<6:0>,

(f<0>)  C,

Status Affected: C, Z

Description: The contents of register ‘f’ are shifted

one bit to the right through the Carry

flag. A ‘0’ is shifted into the MSb. If ‘d’ is

‘0’, the result is placed in W. If ‘d’ is ‘1’,

the result is stored back in register ‘f’.

MOVF Move f

Syntax: [ label ] MOVF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f)  (dest)

Status Affected: Z

Description: The contents of register f is moved to

a destination dependent upon the

status of d. If d = 0,

destination is W register. If d = 1, the

destination is file register f itself. d = 1

is useful to test a file register since

status flag Z is affected.

Words: 1

Cycles: 1

Example: MOVF FSR, 0

After Instruction

W = value in FSR register

Z= 1

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MOVIW Move INDFn to W

Syntax: [ label ] MOVIW ++FSRn

[ label ] MOVIW --FSRn

[ label ] MOVIW FSRn++

[ label ] MOVIW FSRn--

[ label ] MOVIW k[FSRn]

Operands: n  [0,1]

-32  k  31

Operation: INDFn  W

Effective address is determined by

• FSR + 1 (preincrement)

• FSR - 1 (predecrement)

• FSR + k (relative offset)

After the Move, the FSR value will be

either:

• FSR + 1 (all increments)

• FSR - 1 (all decrements)

• Unchanged

Status Affected: Z

Mode Syntax mm

Preincrement ++FSRn 00

Predecrement --FSRn 01

Postincrement FSRn++ 10

Postdecrement FSRn-- 11

Description: This instruction is used to move data

between W and one of the indirect

registers (INDFn). Before/after this

move, the pointer (FSRn) is updated by

pre/post incrementing/decrementing it.

Note: The INDFn registers are not

physical registers. Any instruction that

accesses an INDFn register actually

accesses the register at the address

specified by the FSRn.

FSRn is limited to the range 0000h -

FFFFh. Incrementing/decrementing it

beyond these bounds will cause it to wrap

around.

MOVLB Move literal to BSR

Syntax: [ label ] MOVLB k

Operands: 0  k  15

Operation: k  BSR

Status Affected: None

Description: The five-bit literal ‘k’ is loaded into the

Bank Select Register (BSR).

MOVLP Move literal to PCLATH

Syntax: [ label ] MOVLP k

Operands: 0  k  127

Operation: k  PCLATH

Status Affected: None

Description: The seven-bit literal ‘k’ is loaded into the

PCLATH register.

MOVLW Move literal to W

Syntax: [ label ] MOVLW k

Operands: 0  k  255

Operation: k  (W)

Status Affected: None

Description: The eight-bit literal ‘k’ is loaded into W

ble as ‘0’s.

Words: 1

Cycles: 1

Example: MOVLW 0x5A

After Instruction

W = 0x5A

MOVWF Move W to f

Syntax: [ label ] MOVWF f

Operands: 0  f  127

Operation: (W)  (f)

Status Affected: None

Description: Move data from W register to register

‘f’.

Words: 1

Cycles: 1

Example: MOVWF OPTION

Before Instruction

OPTION = 0xFF

W = 0x4F

After Instruction

OPTION = 0x4F

W = 0x4F

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PIC16(L)F1824/1828

MOVWI Move W to INDFn

Syntax: [ label ] MOVWI ++INDFn

[ label ] MOVWI --INDFn

[ label ] MOVWI INDFn++

[ label ] MOVWI INDFn--

[ label ] MOVWI k[FSRn]

Operands: n  [0,1]

-32  k  31

Operation: W  INDFn

Effective address is determined by

• FSR + 1 (preincrement)

• FSR - 1 (predecrement)

• FSR + k (relative offset)

After the Move, the FSR value will be

either:

• FSR + 1 (all increments)

• FSR - 1 (all decrements)

Unchanged

Status Affected: None

Mode Syntax mm

Preincrement ++FSRn 00

Predecrement --FSRn 01

Postincrement FSRn++ 10

Postdecrement FSRn-- 11

Description: This instruction is used to move data

between W and one of the indirect

registers (INDFn). Before/after this

move, the pointer (FSRn) is updated by

pre/post incrementing/decrementing it.

Note: The INDFn registers are not

physical registers. Any instruction that

accesses an INDFn register actually

accesses the register at the address

specified by the FSRn.

FSRn is limited to the range 0000h -

FFFFh. Incrementing/decrementing it

beyond these bounds will cause it to wrap

around.

The increment/decrement operation on

FSRn WILL NOT affect any Status bits.

NOP No Operation

Syntax: [ label ] NOP

Operands: None

Operation: No operation

Status Affected: None

Description: No operation.

Words: 1

Cycles: 1

Example: NOP

OPTION Load OPTION_REG Register

with W

Syntax: [ label ] OPTION

Operands: None

Operation: (W)  OPTION_REG

Status Affected: None

Description: Move data from W register to

OPTION_REG register.

RESET Software Reset

Syntax: [ label ] RESET

Operands: None

Operation: Execute a device Reset. Resets the

nRI flag of the PCON register.

Status Affected: None

Description: This instruction provides a way to

execute a hardware Reset by soft-

ware.

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RETFIE Return from Interrupt

Syntax: [ label ] RETFIE

Operands: None

Operation: TOS  PC,

1  GIE

Status Affected: None

Description: Return from Interrupt. Stack is POPed

and Top-of-Stack (TOS) is loaded in

the PC. Interrupts are enabled by

setting Global

Interrupt Enable bit, GIE

(INTCON<7>). This is a two-cycle

instruction.

Words: 1

Cycles: 2

Example: RETFIE

After Interrupt

PC = TOS

GIE = 1

RETLW Return with literal in W

Syntax: [ label ] RETLW k

Operands: 0  k  255

Operation: k  (W);

TOS  PC

Status Affected: None

Description: The W register is loaded with the eight

bit literal ‘k’. The program counter is

loaded from the top of the stack (the

return address). This is a two-cycle

instruction.

Words: 1

Cycles: 2

Example:

TABLE

CALL TABLE;W contains table

;offset value

• ;W now has table value

•

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2 ;

•

RETLW kn ; End of table

Before Instruction

W = 0x07

After Instruction

W = value of k8

RETURN Return from Subroutine

Syntax: [ label ] RETURN

Operands: None

Operation: TOS  PC

Status Affected: None

Description: Return from subroutine. The stack is

POPed and the top of the stack (TOS)

is loaded into the program counter.

This is a two-cycle instruction.

RLF Rotate Left f through Carry

Syntax: [ label ] RLF f,d

Operands: 0  f  127

d  [0,1]

Operation: See description below

Status Affected: C

Description: The contents of register ‘f’ are rotated

one bit to the left through the Carry

flag. If ‘d’ is ‘0’, the result is placed in

the W register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

Words: 1

Cycles: 1

Example: RLF REG1,0

Before Instruction

REG1 = 1110 0110

C=0

After Instruction

REG1 = 1110 0110

W = 1100 1100

C=1

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PIC16(L)F1824/1828

RRF Rotate Right f through Carry

Syntax: [ label ] RRF f,d

Operands: 0  f  127

d  [0,1]

Operation: See description below

Status Affected: C

Description: The contents of register ‘f’ are rotated

one bit to the right through the Carry

flag. If ‘d’ is ‘0’, the result is placed in

the W register. If ‘d’ is ‘1’, the result is

placed back in register ‘f’.

SLEEP Enter Sleep mode

Syntax: [ label ]SLEEP

Operands: None

Operation: 00h  WDT,

0  WDT prescaler,

1  TO,

0  PD

Status Affected: TO, PD

Description: The power-down Status bit, PD is

cleared. Time-out Status bit, TO is

set. Watchdog Timer and its pres-

caler are cleared.

The processor is put into Sleep mode

with the oscillator stopped.

SUBLW Subtract W from literal

Syntax: [ label ]SUBLW k

Operands: 0 k 255

Operation: k - (W) W)

Status Affected: C, DC, Z

Description: The W register is subtracted (2’s com-

plement method) from the eight-bit

literal ‘k’. The result is placed in the W

SUBWF Subtract W from f

Syntax: [ label ] SUBWF f,d

Operands: 0 f 127

d  [0,1]

Operation: (f) - (W) destination)

Status Affected: C, DC, Z

Description: Subtract (2’s complement method) W

result is stored in the W

back in register ‘f.

SUBWFB Subtract W from f with Borrow

Syntax: SUBWFB f {,d}

Operands: 0  f  127

d  [0,1]

Operation: (f) – (W) – (B) dest

Status Affected: C, DC, Z

Description: Subtract W and the BORROW flag

(CARRY) from register ‘f’ (2’s comple-

ment method). If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

C = 0W  k

C = 1W  k

DC = 0W<3:0>  k<3:0>

DC = 1W<3:0>  k<3:0>

C = 0W  f

C = 1W  f

DC = 0W<3:0>  f<3:0>

DC = 1W<3:0>  f<3:0>

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SWAPF Swap Nibbles in f

Syntax: [ label ] SWAPF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f<3:0>)  (destination<7:4>),

(f<7:4>)  (destination<3:0>)

Status Affected: None

Description: The upper and lower nibbles of regis-

ter ‘f’ are exchanged. If ‘d’ is ‘0’, the

result is placed in the W register. If ‘d’

is ‘1’, the result is placed in register ‘f’.

TRIS Load TRIS Register with W

Syntax: [ label ] TRIS f

Operands: 5  f  7

Operation: (W)  TRIS register ‘f’

Status Affected: None

Description: Move data from W register to TRIS

When ‘f’ = 5, TRISA is loaded.

When ‘f’ = 6, TRISB is loaded.

When ‘f’ = 7, TRISC is loaded.

XORLW Exclusive OR literal with W

Syntax: [ label ] XORLW k

Operands: 0 k 255

Operation: (W) .XOR. k W)

Status Affected: Z

Description: The contents of the W register are

XOR’ed with the eight-bit

literal ‘k’. The result is placed in the

W register.

XORWF Exclusive OR W with f

Syntax: [ label ] XORWF f,d

Operands: 0  f  127

d  [0,1]

Operation: (W) .XOR. (f) destination)

Status Affected: Z

Description: Exclusive OR the contents of the W

result is stored in the W register. If ‘d’

is ‘1’, the result is stored back in regis-

ter ‘f’.

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PIC16(L)F1824/1828

30.0 ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings(†)

Ambient temperature under bias....................................................................................................... -40°C to +125°C

Storage temperature ........................................................................................................................ -65°C to +150°C

Voltage on VDD with respect to VSS, PIC16F1824/1828 .................................................................... -0.3V to +6.5V

Voltage on VDD with respect to VSS, PIC16LF1824/1828 .................................................................. -0.3V to +4.0V

Voltage on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0V

Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)

Total power dissipation(1) ............................................................................................................................... 800 mW

Maximum current out of VSS pin, -40°C  TA  +85°C for industrial................................................................. 85 mA

Maximum current out of VSS pin, -40°C  TA  +125°C for extended .............................................................. 35 mA

Maximum current into VDD pin, -40°C  TA  +85°C for industrial.................................................................. 800 mA

Maximum current into VDD pin, -40°C  TA  +125°C for extended ................................................................. 30 mA

Clamp current, IK (VPIN < 0 or VPIN > VDD)20 mA

Maximum output current sunk by any I/O pin.................................................................................................... 25 mA

Maximum output current sourced by any I/O pin .............................................................................................. 25 mA

Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x IOL).

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

PIC16(L)F1824/1828

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FIGURE 30-1: PIC16F1824/1828 VOLTAGE FREQUENCY GRAPH, -40°C





+125°C

FIGURE 30-2: PIC16LF1824/1828 VOLTAGE FREQUENCY GRAPH, -40°C





+125°C

1.8

2.5

Frequency (MHz)

VDD (V)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: Refer to Table 30-1 for each Oscillator mode’s supported frequencies.

43210 16

5.5

1.8

2.5

Frequency (MHz)

VDD (V)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: Refer to Table 30-1 for each Oscillator mode’s supported frequencies.

432

10 16

3.6

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PIC16(L)F1824/1828

FIGURE 30-3: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE

125

2.0

VDD (V)

4.0 5.04.5

Temperature (°C)

2.5 3.0 3.5 5.51.8

-40

-20

± 5%

± 2%

± 5%

± 3%

PIC16(L)F1824/1828

DS41419C-page 354 Preliminary  2010-2011 Microchip Technology Inc.

30.1 DC Characteristics: PIC16(L)F1824/1828-I/E (Industrial, Extended)

PIC16LF1824/1828

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

PIC16F1824/1828

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param.

No.

Sym. Characteristic Min. Typ† Max. Units Conditions

D001 VDD Supply Voltage

PIC16LF1824/1828 1.8

2.5

—

3.6

FOSC  16 MHz:

FOSC  32 MHz (NOTE 2)

D001 PIC16F1824/1828 1.8

2.5

—

5.5

FOSC  16 MHz:

FOSC  32 MHz (NOTE 2)

D002* VDR RAM Data Retention Voltage(1)

PIC16LF1824/1828 1.5 — — V Device in Sleep mode

D002* PIC16F1824/1828 1.7 — — V Device in Sleep mode

VPOR*Power-on Reset Release Voltage —1.6— V

VPORR*Power-on Reset Rearm Voltage

PIC16LF1824/1828 — 0.8 — V Device in Sleep mode

PIC16F1824/1828 —1.7 — V Device in Sleep mode

D003 VADFVR Fixed Voltage Reference Voltage for

ADC, Initial Accuracy

-7

-8

-7

-8

-7

-8

—

% 1.024V, VDD  2.5V, 85°C (NOTE 3)

1.024V, VDD  2.5V, 125°C (NOTE 3)

2.048V, VDD  2.5V, 85°C

2.048V, VDD  2.5V, 125°C

4.096V, VDD  4.75V, 85°C

4.096V, VDD  4.75V, 125°C

D003A VCDAFVR Fixed Voltage Reference Voltage for

Comparator and DAC, Initial Accu-

racy

-11

—

% 1.024V, VDD  2.5V, 85°C

1.024V, VDD  2.5V, 125°C

2.048V, VDD  2.5V, 85°C

2.048V, VDD  2.5V, 125°C

4.096V, VDD  4.75V, 85°C

4.096V, VDD  4.75V, 125°C

D004* SVDD VDD Rise Rate to ensure internal

Power-on Reset signal

0.05 — — V/ms See Section 7.1 “Power-on Reset

(POR)” for details.

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

2: PLL required for 32 MHz operation.

3: For proper operation, the minimum value of the ADC positive voltage reference must be 1.8V or greater. When selecting

the FVR or the VREF+ pin as the source of the ADC positive voltage reference, be aware that the voltage must be 1.8V or

greater.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 355

PIC16(L)F1824/1828

FIGURE 30-4: POR AND POR REARM WITH SLOW RISING VDD

VDD

VPOR

VPORR

VSS

NPOR

TPOR(3)

POR REARM

Note 1: When NPOR is low, the device is held in Reset.

2: TPOR 1 s typical.

3: TVLOW 2.7 s typical.

TVLOW(2)

PIC16(L)F1824/1828

DS41419C-page 356 Preliminary  2010-2011 Microchip Technology Inc.

30.2 DC Characteristics: PIC16(L)F1824/1828-I/E (Industrial, Extended)

PIC16LF1824/1828

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

PIC16F1824/1828

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param

No.

Device

Characteristics Min. Typ† Max. Units

Conditions

VDD Note

Supply Current (IDD)(1, 2)

D010 — 5.0 10 A1.8

FOSC = 32 kHz

LP Oscillator mode, -40  TA  +85°C

—7.5 12 A3.0

—5.0 13 A1.8

FOSC = 32 kHz

LP Oscillator mode, -40  TA +125°C

—7.5 15 A3.0

D010 —24 50 A1.8 FOSC = 32 kHz

LP Oscillator mode, -40  TA  +85°C

—30 55 A3.0

—32 60 A5.0

—24 55 A1.8 FOSC = 32 kHz

LP Oscillator mode, -40  TA +125°C

—30 60 A3.0

—32 65 A5.0

D011 — 60 110 A1.8F

OSC = 1 MHz

XT Oscillator mode

— 111 190 A3.0

D011 —82 130 A1.8 FOSC = 1 MHz

XT Oscillator mode

—141 220 A3.0

—200 290 A5.0

D012 — 145 290 A1.8F

OSC = 4 MHz

XT Oscillator mode

— 260 480 A3.0

D012 —165 300 A1.8 FOSC = 4 MHz

XT Oscillator mode

—290 500 A3.0

—368 700 A5.0

D013 — 34 160 A1.8F

OSC = 1 MHz

EC Oscillator mode, Medium-power mode

—59

230 A3.0

D013 —60 180 A1.8 FOSC = 1 MHz

EC Oscillator mode

Medium-power mode

—92 240 A3.0

—126 320 A5.0

D014 — 118 250 A1.8F

OSC = 4 MHz

EC Oscillator mode,

Medium-power mode

— 210 430 A3.0

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from

rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current

consumption.

3: 8 MHz internal RC oscillator with 4xPLL enabled.

4: 8 MHz crystal oscillator with 4xPLL enabled.

5: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended

by the formula IR = VDD/2REXT (mA) with REXT in k.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 357

PIC16(L)F1824/1828

D014 —143 275 A1.8 FOSC = 4 MHz

EC Oscillator mode

Medium-power mode

—240 450 A3.0

—300 650 A5.0

Supply Current (IDD)(1, 2)

D015 — 2.0 18 A1.8FOSC = 31 kHz

LFINTOSC mode

—4.0 20 A3.0

D015 —21 58 A1.8 FOSC = 31 kHz

LFINTOSC mode

—27 65 A3.0

—28 70 A5.0

D016 — 96 165 A1.8F

OSC = 500 kHz

MFINTOSC mode

— 120 190 A3.0

D016 —124 180 A1.8 FOSC = 500 kHz

MFINTOSC mode

—150 210 A3.0

—190 270 A5.0

D017* — .44 .70 mA 1.8 FOSC = 8 MHz

HFINTOSC mode

—.701.1 mA 3.0

D017* —.48 .75 mA 1.8 FOSC = 8 MHz

HFINTOSC mode

—.74 1.15 mA 3.0

—.82 1.35 mA 5.0

D018 — .70 1.2 mA 1.8 FOSC = 16 MHz

HFINTOSC mode

—1.1

1.75 mA 3.0

D018 —.7 1.2 mA 1.8 FOSC = 16 MHz

HFINTOSC mode

—1.1 1.8 mA 3.0

—1.4 2.0 mA 5.0

D019 — 2.1 3.1 mA 3.0 FOSC = 32 MHz

HFINTOSC mode (Note 3)

—2.23.4 mA 3.6

D019 —2.2 3.1 mA 3.0 FOSC = 32 MHz

HFINTOSC mode (Note 3)

—2.3 3.4 mA 5.0

30.2 DC Characteristics: PIC16(L)F1824/1828-I/E (Industrial, Extended) (Continued)

PIC16LF1824/1828

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

PIC16F1824/1828

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param

No.

Device

Characteristics Min. Typ† Max. Units

Conditions

VDD Note

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from

rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current

consumption.

3: 8 MHz internal RC oscillator with 4xPLL enabled.

4: 8 MHz crystal oscillator with 4xPLL enabled.

5: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended

by the formula IR = VDD/2REXT (mA) with REXT in k.

PIC16(L)F1824/1828

DS41419C-page 358 Preliminary  2010-2011 Microchip Technology Inc.

Supply Current (IDD)(1, 2)

D020 — 1.8 3.1 mA 3.0 FOSC = 32 MHz

HS Oscillator mode (Note 4)

—2.43.4 mA 3.6

D020 —1.8 3.1 mA 3.0 FOSC = 32 MHz

HS Oscillator mode (Note 4)

—2.4 3.4 mA 5.0

D021 — 128 350 A1.8F

OSC = 4 MHz

EXTRC mode (Note 5)

— 237 680 A3.0

D021 —153 350 A1.8 FOSC = 4 MHz

EXTRC mode (Note 5)

—273 680 A3.0

—353 830 A5.0

30.2 DC Characteristics: PIC16(L)F1824/1828-I/E (Industrial, Extended) (Continued)

PIC16LF1824/1828

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

PIC16F1824/1828

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param

No.

Device

Characteristics Min. Typ† Max. Units

Conditions

VDD Note

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from

rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current

consumption.

3: 8 MHz internal RC oscillator with 4xPLL enabled.

4: 8 MHz crystal oscillator with 4xPLL enabled.

5: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended

by the formula IR = VDD/2REXT (mA) with REXT in k.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 359

PIC16(L)F1824/1828

30.3 DC Characteristics: PIC16(L)F1824/1828-I/E (Power-Down)

PIC16LF1824/1828

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

PIC16F1824/1828

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param

No. Device Characteristics Min. Typ† Max.

+85°C

Max.

+125°C Units

Conditions

VDD Note

Power-down Base Current (IPD)(2)

D022 — 0.02 0.7 2.4 A 1.8 WDT, BOR, FVR, and T1OSC

disabled, all Peripherals Inactive

— 0.03 1.0 3.0 A3.0

D022 —18 37 44 A1.8 WDT, BOR, FVR, and T1OSC

disabled, all Peripherals Inactive

—20 42 48 A3.0

—22 45 61 A5.0

D023 — .2 1.5 3.0 A 1.8 LPWDT Current (Note 1)

—.52.03.5A3.0

D023 —18 38 44 A1.8 LPWDT Current (Note 1)

—21 43 48 A3.0

—22 46 65 A5.0

D023A — 4.8 22 25 A 1.8 FVR current (Note 1)

— 4.8 24 27 A3.0

D023A —26 62 65 A1.8 FVR current (Note 1)

—33 72 75 A3.0

—61 115 120 A5.0

D024 — 7.0 14 16 A 3.0 BOR Current (Note 1)

D024 —24 47 50 A3.0 BOR Current (Note 1)

—29 55 66 A5.0

D025 — 1.0 3.5 4.0 A 1.8 T1OSC Current (Note 1)

— 1.2 4.0 4.5 A3.0

D025 —19 39 45 A1.8 T1OSC Current (Note 1)

—21 43 49 A3.0

—23 46 65 A5.0

D026 — .03 1.5 3.0 A 1.8 A/D Current (Note 1, Note 3), no

conversion in progress

— .04 2.0 3.5 A3.0

D026 —18 38 45 A1.8 A/D Current (Note 1, Note 3), no

conversion in progress

—20 43 49 A3.0

—22 46 65 A5.0

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max

values should be used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

3: A/D oscillator source is FRC.

PIC16(L)F1824/1828

DS41419C-page 360 Preliminary  2010-2011 Microchip Technology Inc.

Power-down Base Current (IPD)(2)

D026A* — 250 — — A 1.8 A/D Current (Note 1, Note 3),

conversion in progress

—250 — — A3.0

D026A* —280 — — A1.8 A/D Current (Note 1, Note 3),

conversion in progress

—280 — — A3.0

—280 — — A5.0

D027 — 2.0 5.0 6.0 A 1.8 Cap Sense Low Power

Oscillator mode (Note 1)

— 4.0 6.0 8.0 A3.0

D027 —21 41 45 A1.8 Cap Sense Low Power

Oscillator mode (Note 1)

—23 47 55 A3.0

—24 53 68 A5.0

D027A — 5.0 8.0 10 A 1.8 Cap Sense Medium Power

Oscillator mode (Note 1)

—7.9 11 12 A3.0

D027A —21 44 47 A1.8 Cap Sense Medium Power

Oscillator mode (Note 1)

—23 53 60 A3.0

—24 57 71 A5.0

D027B — 13 22 24 A 1.8 Cap Sense High Power

Oscillator mode (Note 1)

—35 42 44 A3.0

D027B —21 58 65 A1.8 Cap Sense High Power

Oscillator mode (Note 1)

—23 84 90 A3.0

—24 95 110 A5.0

D028 — 7.3 16 17 A 1.8 Comparator Current, Low Power

mode, one comparator enabled

(Note 1)

— 7.4 18 19 A3.0

D028 —28 45 50 A1.8 Comparator Current, Low Power

mode, one comparator enabled

(Note 1)

—30 56 61 A3.0

—32 60 80 A5.0

D028A — 7.5 17 18 A 1.8 Comparator Current, Low Power

mode, two comparators enabled

(Note 1)

— 7.6 19 20 A3.0

D028A —29 47 52 A1.8 Comparator Current, Low Power

mode, two comparators enabled

(Note 1)

—31 58 63 A3.0

—33 62 82 A5.0

30.3 DC Characteristics: PIC16(L)F1824/1828-I/E (Power-Down) (Continued)

PIC16LF1824/1828

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

PIC16F1824/1828

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param

No. Device Characteristics Min. Typ† Max.

+85°C

Max.

+125°C Units

Conditions

VDD Note

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max

values should be used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

3: A/D oscillator source is FRC.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 361

PIC16(L)F1824/1828

Power-down Base Current (IPD)(2)

D028B — 28 46 48 A 1.8 Comparator Current, High Power

mode, one comparator enabled

(Note 1)

—29 48 49 A3.0

D028B —60 80 85 A1.8 Comparator Current, High Power

mode, one comparator enabled

(Note 1)

—62 85 90 A3.0

—64 90 105 A5.0

D028C — 29 47 50 A 1.8 Comparator Current, High Power

mode, two comparators enabled

—30 49 51 A3.0

D028C —61 82 87 A1.8 Comparator Current, High Power

mode, two comparators enabled

(Note 1)

—63 87 92 A3.0

—65 92 107 A5.0

30.3 DC Characteristics: PIC16(L)F1824/1828-I/E (Power-Down) (Continued)

PIC16LF1824/1828

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

PIC16F1824/1828

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param

No. Device Characteristics Min. Typ† Max.

+85°C

Max.

+125°C Units

Conditions

VDD Note

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max

values should be used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

3: A/D oscillator source is FRC.

PIC16(L)F1824/1828

DS41419C-page 362 Preliminary  2010-2011 Microchip Technology Inc.

30.4 DC Characteristics: PIC16(L)F1824/1828-I/E

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

VIL Input Low Voltage

I/O PORT:

D030 with TTL buffer — — 0.8 V 4.5V  VDD  5.5V

D030A — — 0.15 VDD V1.8V  VDD  4.5V

D031 with Schmitt Trigger buffer — — 0.2 VDD V2.0V  VDD  5.5V

with I2C™ levels — — 0.3 VDD V

with SMBus levels — — 0.8 V 2.7V  VDD  5.5V

D032 MCLR, OSC1 (RC mode)(1) ——0.2VDD V

D033 OSC1 (HS mode) — — 0.3 VDD V

VIH Input High Voltage

I/O ports: — —

D040 with TTL buffer 2.0 — — V 4.5V  VDD 5.5V

D040A 0.25 VDD +

0.8

——V1.8V  VDD  4.5V

D041 with Schmitt Trigger buffer 0.8 VDD ——V2.0V  VDD  5.5V

with I2C™ levels 0.7 VDD ——V

with SMBus levels 2.1 — — V 2.7V  VDD  5.5V

D042 MCLR 0.8 VDD ——V

D043A OSC1 (HS mode) 0.7 VDD ——V

D043B OSC1 (RC mode) 0.9 VDD ——V(Note 1)

IIL Input Leakage Current(2)

D060 I/O ports — ± 5

± 5

± 125

± 1000

VSS  VPIN  VDD, Pin at high-

impedance at 85°C

125°C

D061 MCLR(3) —± 50± 200nAVSS  VPIN  VDD at 85°C

IPUR Weak Pull-up Current

D070* 25

100

140

200

300 A

VDD = 3.3V, VPIN = VSS

VDD = 5.0V, VPIN = VSS

VOL Output Low Voltage(4)

D080 I/O ports

——0.6V

IOL = 8mA, VDD = 5V

IOL = 6mA, VDD = 3.3V

IOL = 1.8mA, VDD = 1.8V

VOH Output High Voltage(4)

D090 I/O ports

VDD - 0.7 — — V

IOH = 3.5mA, VDD = 5V

IOH = 3mA, VDD = 3.3V

IOH = 1mA, VDD = 1.8V

Capacitive Loading Specs on Output Pins

D101* COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when

external clock is used to drive

OSC1

D101A* CIO All I/O pins — — 50 pF

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external

clock in RC mode.

2: Negative current is defined as current sourced by the pin.

3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

4: Including OSC2 in CLKOUT mode.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 363

PIC16(L)F1824/1828

30.5 Memory Programming Requirements

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +125°C

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

Program Memory

Programming Specifications

D110 VIHH Voltage on MCLR/VPP/RA5 pin 8.0 — 9.0 V (Note 3, Note 4)

D111 IDDP Supply Current during

Programming

——10mA

D112 VDD for Bulk Erase 2.7 — VDD

max.

D113 VPEW VDD for Write or Row Erase VDD

min.

—V

max.

D114 IPPPGM Current on MCLR/VPP during Erase/

Write

——1.0mA

D115 IDDPGM Current on VDD during Erase/Write — 5.0 mA

Data EEPROM Memory

D116 EDByte Endurance 100K — —E/W-40C to +85C

D117 VDRW VDD for Read/Write VDD

min.

—V

max.

D118 TDEW Erase/Write Cycle Time — 4.0 5.0 ms

D119 TRETD Characteristic Retention 20 — — Year Provided no other

specifications are violated

D120 TREF Number of Total Erase/Write

Cycles before Refresh(2)

1M 10M — E/W -40°C to +85°C

Program Flash Memory

D121 EPCell Endurance 10K — —E/W-40C to +85C (Note 1)

D122 VPR VDD for Read VDD

min.

—V

max.

D123 TIW Self-timed Write Cycle Time — 2 2.5 ms

D124 TRETD Characteristic Retention 40 — — Year Provided no other

specifications are violated

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Self-write and Block Erase.

2: Refer to Section 11.2 “Using the Data EEPROM” for a more detailed discussion on data EEPROM

endurance.

3: Required only if single-supply programming is disabled.

4: The MPLAB® ICD 2 does not support variable VPP output. Circuitry to limit the ICD 2 VPP voltage must be

placed between the ICD 2 and target system when programming or debugging with the ICD 2.

PIC16(L)F1824/1828

DS41419C-page 364 Preliminary  2010-2011 Microchip Technology Inc.

30.6 Thermal Considerations

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +125°C

Param

No. Sym. Characteristic Typ. Units Conditions

TH01 JA Thermal Resistance Junction to Ambient TBD C/W 8-pin PDIP package

TBD C/W 8-pin SOIC package

TBD C/W 8-pin DFN 3X3mm package

TBD C/W 14-pin PDIP package

TBD C/W 14-pin SOIC package

TBD C/W 14-pin TSSOP 4x4mm package

TBD C/W 16-pin QFN 4X4mm package

TH02 JC Thermal Resistance Junction to Case TBD C/W 8-pin PDIP package

TBD C/W 8-pin SOIC package

TBD C/W 8-pin DFN 3X3mm package

TBD C/W 14-pin PDIP package

TBD C/W 14-pin SOIC package

TBD C/W 14-pin TSSOP 4x4mm package

TBD C/W 16-pin QFN 4X4mm package

TH03 TJMAX Maximum Junction Temperature 150 C

TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O

TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1)

TH06 PI/OI/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH))

TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2)

Legend: TBD = To Be Determined

Note 1: IDD is current to run the chip alone without driving any load on the output pins.

2: TA = Ambient Temperature

3: TJ = Junction Temperature

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 365

PIC16(L)F1824/1828

30.7 Timing Parameter Symbology

The timing parameter symbols have been created with

one of the following formats:

FIGURE 30-5: LOAD CONDITIONS

1. TppS2ppS

2. TppS

F Frequency T Time

Lowercase letters (pp) and their meanings:

cc CCP1 osc OSC1

ck CLKOUT rd RD

cs CS rw RD or WR

di SDIx sc SCKx

do SDO ss SS

dt Data in t0 T0CKI

io I/O PORT t1 T1CKI

mc MCLR wr WR

Uppercase letters and their meanings:

FFall PPeriod

HHigh RRise

I Invalid (High-impedance) V Valid

L Low Z High-impedance

Legend: CL = 50 pF for all pins, 15 pF for

OSC2 output

Load Condition

PIC16(L)F1824/1828

DS41419C-page 366 Preliminary  2010-2011 Microchip Technology Inc.

30.8 AC Characteristics: PIC16(L)F1824/1828-I/E

FIGURE 30-6: CLOCK TIMING

TABLE 30-1: CLOCK OSCILLATOR TIMING REQUIREMENTS

OSC1/CLKIN

OSC2/CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

OS02

OS03

OS04 OS04

OSC2/CLKOUT

(LP,XT,HS Modes)

(CLKOUT Mode)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +125°C

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

OS01 FOSC External CLKIN Frequency(1) DC — 0.5 MHz EC Oscillator mode (low)

DC — 4 MHz EC Oscillator mode (medium)

DC — 32 MHz EC Oscillator mode (high)

Oscillator Frequency(1) — 32.768 — kHz LP Oscillator mode

0.1 — 4 MHz XT Oscillator mode

1 — 4 MHz HS Oscillator mode, VDD  2.7V

1 — 20 MHz HS Oscillator mode, VDD > 2.7V

DC — 4 MHz RC Oscillator mode

OS02 TOSC External CLKIN Period(1) 27 — s LP Oscillator mode

250 — ns XT Oscillator mode

50 — ns HS Oscillator mode

31.25 — ns EC Oscillator mode

Oscillator Period(1) — 30.5 — s LP Oscillator mode

250 — 10,000 ns XT Oscillator mode

50 — 1,000 ns HS Oscillator mode

250 — — ns RC Oscillator mode

OS03 TCY Instruction Cycle Time(1) 200 — DC ns TCY = FOSC/4

OS04* TosH,

TosL

External CLKIN High,

External CLKIN Low

2——s LP oscillator

100 — — ns XT oscillator

20 — — ns HS oscillator

OS05* TosR,

TosF

External CLKIN Rise,

External CLKIN Fall

0—ns LP oscillator

0—ns XT oscillator

0—ns HS oscillator

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: Instruction cycle period (T

CY) equals four times the input oscillator time base period. All specified values are based on

characterization data for that particular oscillator type under standard operating conditions with the device executing code.

Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-

sumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external

clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 367

PIC16(L)F1824/1828

TABLE 30-2: OSCILLATOR PARAMETERS

TABLE 30-3: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.7V TO 5.5V)

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param

No. Sym. Characteristic

Freq.

Toleranc

Min. Typ† Max. Units Conditions

OS08 HFOSC Internal Calibrated HFINTOSC

Frequency(2)

2% — 16.0 — MHz 0°C  TA  +60°C, VDD  2.5V

3—16.0—MHz60°C  TA  +85°C, VDD 

2.5V

5% — 16.0 — MHz -40°C  TA  +125°C

OS08A MFOSC Internal Calibrated MFINTOSC

Frequency(2)

2% — 500 — kHz 0°C  TA  +60°C, VDD  2.5V

3% — 500 — kHz 60°C  TA  +85°C, VDD 

2.5V

5% — 500 — kHz -40°C  TA  +125°C

OS10* TIOSC ST HFINTOSC

Wake-up from Sleep Start-up Time

MFINTOSC

Wake-up from Sleep Start-up Time

—

s

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on

characterization data for that particular oscillator type under standard operating conditions with the device executing

code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current

consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an

external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as

possible. 0.1 F and 0.01 F values in parallel are recommended.

3: By design.

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

F10 FOSC Oscillator Frequency Range 4 — 8 MHz

F11 FSYS On-Chip VCO System Frequency 16 — 32 MHz

F12 TRC PLL Start-up Time (Lock Time) — — 2 ms

F13* CLK CLKOUT Stability (Jitter) -0.25% — +0.25% %

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3V, 25C unless otherwise stated. These parameters are for design guidance

only and are not tested.

PIC16(L)F1824/1828

DS41419C-page 368 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 30-7: CLKOUT AND I/O TIMING

FOSC

CLKOUT

I/O pin

(Input)

I/O pin

(Output)

Q4 Q1 Q2 Q3

OS11

OS19

OS13

OS15

OS18, OS19

OS20

OS21

OS17

OS16

OS14

OS12

OS18

Old Value New Value

Write Fetch Read ExecuteCycle

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 369

PIC16(L)F1824/1828

TABLE 30-4: CLKOUT AND I/O TIMING PARAMETERS

FIGURE 30-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

OS11 TosH2ckL FOSC to CLKOUT (1) ——70nsVDD = 3.0-5.0V

OS12 TosH2ckH FOSC to CLKOUT (1) ——72nsVDD = 3.0-5.0V

OS13 TckL2ioV CLKOUT to Port out valid(1) ——20ns

OS14 TioV2ckH Port input valid before CLKOUT(1) TOSC + 200

——ns

OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid — 50 70* ns VDD = 3.0-5.0V

OS16 TosH2ioI Fosc (Q2 cycle) to Port input invalid

(I/O in hold time)

50 — — ns VDD = 3.0-5.0V

OS17 TioV2osH Port input valid to Fosc(Q2 cycle)

(I/O in setup time)

20 — — ns

OS18* TioR Port output rise time —

—

140

ns VDD = 1.8V

VDD = 3.0-5.0V

OS19* TioF Port output fall time —

—

ns VDD = 1.8V

VDD = 3.0-5.0V

OS20* Tinp INT pin input high or low time 25 — — ns

OS21* Tioc Interrupt-on-change new input level

time

25 — — ns

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25C unless otherwise stated.

Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.

VDD

MCLR

Internal

POR

PWRT

Time-out

OSC

Start-Up Time

Internal Reset(1)

Watchdog Timer

I/O pins

Note 1: Asserted low.

Reset(1)

PIC16(L)F1824/1828

DS41419C-page 370 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 30-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS

VBOR

VDD

(Device in Brown-out Reset) (Device not in Brown-out Reset)

33(1)

Note 1: 64 ms delay only if PWRTE bit in the Configuration Word 1 is programmed to ‘0’.

2 ms delay if PWRTE = 0 and VREGEN = 1.

Reset

(due to BOR)

VBOR and VHYST

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 371

PIC16(L)F1824/1828

TABLE 30-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET PARAMETERS

FIGURE 30-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

30 TMCLMCLR Pulse Width (low) 2

—

s

VDD = 3.3-5V, -40°C to +85°C

VDD = 3.3-5V

31 TWDTLP Watchdog Timer

Time-out Period (No Prescaler)

10 18 27 ms VDD = 3.3V-5V

32 TOST Oscillator Start-up Timer Period(1), (2) — 1024 — Tosc (Note 3)

33* TPWRT Power-up Timer Period, PWRTE =040 65 140 ms

34* TIOZ I/O high-impedance from MCLR Low

or Watchdog Timer Reset

——2.0s

35 VBOR Brown-out Reset Voltage 2.56

1.80

2.7

1.9

2.8

2.05

V BORV=2.7V

BORV=1.9V

36* VHYST Brown-out Reset Hysteresis 0 25 50 mV -40°C to +85°C

37* TBORDC Brown-out Reset DC Response Time 0 1 40 sVDD  VBOR

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are

based on characterization data for that particular oscillator type under standard operating conditions with the

device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or

higher than expected current consumption. All devices are tested to operate at “min” values with an external

clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no

clock) for all devices.

2: By design.

3: Period of the slower clock.

4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as

possible. 0.1 F and 0.01 F values in parallel are recommended.

T0CKI

T1CKI

40 41

45 46

47 49

TMR0 or

TMR1

PIC16(L)F1824/1828

DS41419C-page 372 Preliminary  2010-2011 Microchip Technology Inc.

TABLE 30-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

FIGURE 30-11: CAPTURE/COMPARE/PWM TIMINGS (CCP)

TABLE 30-7: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns

With Prescaler 10 — — ns

41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns

With Prescaler 10 — — ns

42* TT0P T0CKI Period Greater of:

20 or TCY + 40

— — ns N = prescale value

(2, 4, ..., 256)

45* TT1H T1CKI High

Time

Synchronous, No Prescaler 0.5 TCY + 20 — — ns

Synchronous,

with Prescaler

15 — — ns

Asynchronous 30 — — ns

46* TT1L T1CKI Low

Time

Synchronous, No Prescaler 0.5 TCY + 20 — — ns

Synchronous, with Prescaler 15 — — ns

Asynchronous 30 — — ns

47* TT1P T1CKI Input

Period

Synchronous Greater of:

30 or TCY + 40

— — ns N = prescale value

(1, 2, 4, 8)

Asynchronous 60 — — ns

48 FT1 Timer1 Oscillator Input Frequency Range

(oscillator enabled by setting bit T1OSCEN)

32.4 32.768 33.1 kHz

49* TCKEZTMR1 Delay from External Clock Edge to Timer

Increment

2 TOSC —7 TOSC — Timers in Sync

mode

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C  TA  +125°C

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

CC01* TccL CCP Input Low Time No Prescaler 0.5TCY + 20 — — ns

With Prescaler 20 — — ns

CC02* TccH CCP Input High Time No Prescaler 0.5TCY + 20 — — ns

With Prescaler 20 — — ns

CC03* TccP CCP Input Period 3TCY + 40

— — ns N = prescale value (1, 4 or 16)

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note: Refer to Figure 30.5 for load conditions.

(Capture mode)

CC01 CC02

CC03

CCP

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 373

PIC16(L)F1824/1828

TABLE 30-8: PIC16(L)F1824/1828 A/D CONVERTER (ADC) CHARACTERISTICS

TABLE 30-9: PIC16(L)F1824/1828 A/D CONVERSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating temperature TA  25°C

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

AD01 NRResolution — — 10 bit

AD02 EIL Integral Error — — ±1.7 LSb VREF = 3.0V

AD03 EDL Differential Error — — ±1 LSb No missing codes

VREF = 3.0V

AD04 EOFF Offset Error — — ±2 LSb VREF = 3.0V

AD05 EGN Gain Error — — ±1.5 LSb VREF = 3.0V

AD06 VREF Reference Voltage(3) 1.8 — VDD VVREF = (VREF+ minus VREF-) (NOTE 5)

AD07 VAIN Full-Scale Range VSS —VREF V

AD08 ZAIN Recommended Impedance of

Analog Voltage Source

—— 50

kCan go higher if external 0.01F capacitor is

present on input pin.

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: Total Absolute Error includes integral, differential, offset and gain errors.

2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

3: ADC VREF is from external VREF, VDD pin or FVR, whichever is selected as reference input.

4: When ADC is off, it will not consume any current other than leakage current. The power-down current specification

includes any such leakage from the ADC module.

5: FVR voltage selected must be 2.048V or 4.096V.

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +125°C

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

AD130* TAD A/D Clock Period 1.0 — 9.0 sTOSC-based

A/D Internal RC Oscillator

Period

1.0 1.6 6.0 s ADCS<1:0> = 11 (ADRC mode)

AD131 TCNV Conversion Time (not including

Acquisition Time)(1)

—11—TAD Set GO/DONE bit to conversion

complete

AD132* TACQ Acquisition Time — 5.0 — s

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: The ADRES register may be read on the following TCY cycle.

PIC16(L)F1824/1828

DS41419C-page 374 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 30-12: PIC16(L)F1824/1828 A/D CONVERSION TIMING (NORMAL MODE)

FIGURE 30-13: PIC16(L)F1824/1828 A/D CONVERSION TIMING (SLEEP MODE)

AD131

AD130

BSF ADCON0, GO

A/D CLK

A/D Data

ADRES

ADIF

Sample

OLD_DATA

Sampling Stopped

DONE

NEW_DATA

765 3210

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP instruction to be executed.

1 TCY

AD134 (TOSC/2(1))

1 TCY

AD132

AD131

AD130

BSF ADCON0, GO

A/D CLK

A/D Data

ADRES

ADIF

Sample

OLD_DATA

Sampling Stopped

DONE

NEW_DATA

7 5 3210

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP instruction to be executed.

AD134

1 TCY

(TOSC/2 + TCY(1))

1 TCY

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 375

PIC16(L)F1824/1828

TABLE 30-10: COMPARATOR SPECIFICATIONS

TABLE 30-11: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS

FIGURE 30-14: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated).

Param

No. Sym. Characteristics Min. Typ. Max. Units Comments

CM01 VIOFF Input Offset Voltage(3) —±7.5±60mV

CM02 VICM Input Common Mode Voltage 0 — VDD V

CM03 CMRR Common Mode Rejection Ratio — 50 — dB

CM04A

TRESP

Response Time Rising Edge — 400 800 ns High Power Mode, Note 1

CM04B Response Time Falling Edge — 200 400 ns High Power Mode, Note 1

CM04C Response Time Rising Edge — 1200 — ns Low Power Mode, Note 1

CM04D Response Time Falling Edge — 550 — ns Low Power Mode, Note 1

CM05 TMC2OV Comparator Mode Change to

Output Valid*

——10s

CM06 CHYSTER Comparator Hysteresis — 45 — mV Note 2

* These parameters are characterized but not tested.

Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions

from VSS to VDD.

2: Comparator Hysteresis is available when the CxHYS bit of the CMxCON0 register is enabled.

3: High Power mode.

Operating Conditions: 2.5V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated).

Param

No. Sym. Characteristics Min. Typ. Max. Units Comments

DAC01* CLSB Step Size — VDD/32 — V

DAC02* CACC Absolute Accuracy — —  1/2 LSb

DAC03* CRUnit Resistor Value (R) — 5K — 

DAC04* CST Settling Time(1) ——10s

* These parameters are characterized but not tested.

Legend: TBD = To Be Determined

Note 1: Settling time measured while DACR<4:0> transitions from ‘0000’ to ‘1111’.

Note: Refer to Figure 30-5 for load conditions.

US121 US121

US120 US122

PIC16(L)F1824/1828

DS41419C-page 376 Preliminary  2010-2011 Microchip Technology Inc.

TABLE 30-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

FIGURE 30-15: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

TABLE 30-13: USART SYNCHRONOUS RECEIVE REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param.

No. Symbol Characteristic Min. Max. Units Conditions

US120 TCKH2DTV SYNC XMIT (Master and Slave)

Clock high to data-out valid

3.0-5.5V — 80 ns

1.8-5.5V — 100 ns

US121 TCKRF Clock out rise time and fall time

(Master mode)

3.0-5.5V — 45 ns

1.8-5.5V — 50 ns

US122 TDTRF Data-out rise time and fall time 3.0-5.5V — 45 ns

1.8-5.5V — 50 ns

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param.

No. Symbol Characteristic Min. Max. Units Conditions

US125 TDTV2CKL SYNC RCV (Master and Slave)

Data-hold before CK  (DT hold time) 10 — ns

US126 T

CKL2DTL Data-hold after CK  (DT hold time) 15 — ns

Note: Refer to Figure 30-5 for load conditions.

US125

US126

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 377

PIC16(L)F1824/1828

FIGURE 30-16: SPI MASTER MODE TIMING (CKE = 0, SMP = 0)

FIGURE 30-17: SPI MASTER MODE TIMING (CKE = 1, SMP = 1)

SSx

SCKx

(CKP = 0)

SCKx

(CKP = 1)

SDOx

SDIx

SP70

SP71 SP72

SP73

SP74

SP75, SP76

SP78

SP79

SP80

SP79

SP78

MSb LSb

bit 6 - - - - - -1

MSb In LSb In

bit 6 - - - -1

Note: Refer to Figure 30-5 for load conditions.

SSx

SCKx

(CKP = 0)

SCKx

(CKP = 1)

SDOx

SDIx

SP81

SP71 SP72

SP74

SP75, SP76

SP78

SP80

MSb

SP79

SP73

MSb In

bit 6 - - - - - -1

LSb In

bit 6 - - - -1

LSb

Note: Refer to Figure 30-5 for load conditions.

PIC16(L)F1824/1828

DS41419C-page 378 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 30-18: SPI SLAVE MODE TIMING (CKE = 0)

FIGURE 30-19: SPI SLAVE MODE TIMING (CKE = 1)

SSx

SCKx

(CKP = 0)

SCKx

(CKP = 1)

SDOx

SDIx

SP70

SP71 SP72

SP73

SP74

SP75, SP76 SP77

SP78

SP79

SP80

SP79

SP78

MSb LSb

bit 6 - - - - - -1

MSb In bit 6 - - - -1 LSb In

SP83

Note: Refer to Figure 30-5 for load conditions.

SSx

SCKx

(CKP = 0)

SCKx

(CKP = 1)

SDOx

SDIx

SP70

SP71 SP72

SP82

SP74

SP75, SP76

MSb bit 6 - - - - - -1 LSb

SP77

MSb In bit 6 - - - -1 LSb In

SP80

SP83

Note: Refer to Figure 30-5 for load conditions.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 379

PIC16(L)F1824/1828

TABLE 30-14: SPI MODE REQUIREMENTS

FIGURE 30-20: I2C™ BUS START/STOP BITS TIMING

Param

No. Symbol Characteristic Min. Typ† Max. Units Conditions

SP70* TSSL2SCH,

TSSL2SCL

SSx to SCKx or SCKx input TCY ——ns

SP71* TSCH SCKx input high time (Slave mode) TCY + 20 — — ns

SP72* TSCL SCKx input low time (Slave mode) TCY + 20 — — ns

SP73* TDIV2SCH,

TDIV2SCL

Setup time of SDIx data input to SCKx edge 100 — — ns

SP74* TSCH2DIL,

TSCL2DIL

Hold time of SDIx data input to SCKx edge 100 — — ns

SP75* TDOR SDO data output rise time 3.0-5.5V — 10 25 ns

1.8-5.5V — 25 50 ns

SP76* TDOF SDOx data output fall time — 10 25 ns

SP77* TSSH2DOZ SSx to SDOx output high-impedance 10 — 50 ns

SP78* TSCR SCKx output rise time

(Master mode)

3.0-5.5V — 10 25 ns

1.8-5.5V — 25 50 ns

SP79* TSCF SCKx output fall time (Master mode) — 10 25 ns

SP80* TSCH2DOV,

TSCL2DOV

SDOx data output valid after

SCKx edge

3.0-5.5V — — 50 ns

1.8-5.5V — — 145 ns

SP81* TDOV2SCH,

TDOV2SCL

SDOx data output setup to SCKx edge Tcy — — ns

SP82* TSSL2DOV SDOx data output valid after SS edge — — 50 ns

SP83* TSCH2SSH,

TSCL2SSH

SSx after SCKx edge 1.5TCY + 40 — — ns

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note: Refer to Figure 30-5 for load conditions.

SP91

SP92

SP93

SCLx

SDAx

Start

Condition

Stop

Condition

SP90

PIC16(L)F1824/1828

DS41419C-page 380 Preliminary  2010-2011 Microchip Technology Inc.

FIGURE 30-21: I2C™ BUS DATA TIMING

Note: Refer to Figure 30-5 for load conditions.

SP90

SP91 SP92

SP100

SP101

SP103

SP106 SP107

SP109 SP109

SP110

SP102

SCLx

SDAx

Out

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 381

PIC16(L)F1824/1828

TABLE 30-15: I2C™ BUS DATA REQUIREMENTS

Param.

No. Symbol Characteristic Min. Max. Units Conditions

SP100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a

minimum of 1.5 MHz

400 kHz mode 0.6 — s Device must operate at a

minimum of 10 MHz

SSPx module 1.5TCY ——

SP101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a

minimum of 1.5 MHz

400 kHz mode 1.3 — s Device must operate at a

minimum of 10 MHz

SSPx module 1.5TCY ——

SP102* TRSDAx and SCLx

rise time

100 kHz mode — 1000 ns

400 kHz mode 20 + 0.1CB300 ns CB is specified to be from

10-400 pF

SP103* TFSDAx and SCLx fall

time

100 kHz mode — 250 ns

400 kHz mode 20 + 0.1CB250 ns CB is specified to be from

10-400 pF

SP106* THD:DAT Data input hold time 100 kHz mode 0 — ns

400 kHz mode 0 0.9 s

SP107* TSU:DAT Data input setup

time

100 kHz mode 250 — ns (Note 2)

400 kHz mode 100 — ns

SP109* TAA Output valid from

clock

100 kHz mode — 3500 ns (Note 1)

400 kHz mode — — ns

SP110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free

before a new transmission

can start

400 kHz mode 1.3 — s

SP111 CBBus capacitive loading — 400 pF

* These parameters are characterized but not tested.

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions.

2: A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but

the requirement T

SU:DAT 250 ns must then be met. This will automatically be the case if the device does

not stretch the low period of the SCLx signal. If such a device does stretch the low period of the SCLx sig-

nal, it must output the next data bit to the SDAx line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according

to the Standard mode I2C bus specification), before the SCLx line is released.

PIC16(L)F1824/1828

DS41419C-page 382 Preliminary  2010-2011 Microchip Technology Inc.

TABLE 30-16: CAP SENSE OSCILLATOR SPECIFICATIONS

FIGURE 30-22: CAP SENSE OSCILLATOR

Param.

No. Symbol Characteristic Min. Typ† Max. Units Conditions

CS01 ISRC Current Source High -1.25 -8 -15 A

Medium -0.8 -1.5 -3 A

Low -0.1 -0.3 -0.6 A

CS02 ISNK Current Sink High 1.25 7.5 14 A

Medium 0.6 1.5 3.2 A

Low 0.1 0.25 1.5 A

CS03 VCTH Cap Threshold — 0.8 — V

CS04 VCTL Cap Threshold — 0.4 — V

CS05 VCHYST CAP HYSTERESIS

(VCTH - VCTL)

High 350 525 725 mV

Medium 250 375 500 mV

Low 175 300 425 mV

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

ISRC

VCTH

VCTL

ISNK

EnabledEnabled

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 383

PIC16(L)F1824/1828

31.0 DC AND AC

CHARACTERISTICS GRAPHS

AND CHARTS

Graphs and charts are not available at this time.

PIC16(L)F1824/1828

DS41419C-page 384 Preliminary  2010-2011 Microchip Technology Inc.

NOTES:

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 385

PIC16(L)F1824/1828

32.0 DEVELOPMENT SUPPORT

The PIC® microcontrollers and dsPIC® digital signal

controllers are supported with a full range of software

and hardware development tools:

• Integrated Development Environment

- MPLAB® IDE Software

• Compilers/Assemblers/Linkers

- MPLAB C Compiler for Various Device

Families

- HI-TECH C for Various Device Families

- MPASMTM Assembler

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

- MPLAB Assembler/Linker/Librarian for

Various Device Families

• Simulators

- MPLAB SIM Software Simulator

•Emulators

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers

- MPLAB ICD 3

- PICkit™ 3 Debug Express

• Device Programmers

- PICkit™ 2 Programmer

- MPLAB PM3 Device Programmer

• Low-Cost Demonstration/Development Boards,

Evaluation Kits, and Starter Kits

32.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16/32-bit

microcontroller market. The MPLAB IDE is a Windows®

operating system-based application that contains:

• A single graphical interface to all debugging tools

- Simulator

- Programmer (sold separately)

- In-Circuit Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

• Customizable data windows with direct edit of

contents

• High-level source code debugging

• Mouse over variable inspection

• Drag and drop variables from source to watch

windows

• Extensive on-line help

• Integration of select third party tools, such as

IAR C Compilers

The MPLAB IDE allows you to:

• Edit your source files (either C or assembly)

• One-touch compile or assemble, and download to

emulator and simulator tools (automatically

updates all project information)

• Debug using:

- Source files (C or assembly)

- Mixed C and assembly

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

PIC16(L)F1824/1828

DS41419C-page 386 Preliminary  2010-2011 Microchip Technology Inc.

32.2 MPLAB C Compilers for Various

Device Families

The MPLAB C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC18,

PIC24 and PIC32 families of microcontrollers and the

dsPIC30 and dsPIC33 families of digital signal control-

lers. These compilers provide powerful integration

capabilities, superior code optimization and ease of

use.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

32.3 HI-TECH C for Various Device

Families

The HI-TECH C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC

family of microcontrollers and the dsPIC family of digital

signal controllers. These compilers provide powerful

integration capabilities, omniscient code generation

and ease of use.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The compilers include a macro assembler, linker, pre-

processor, and one-step driver, and can run on multiple

platforms.

32.4 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel® standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• User-defined macros to streamline

assembly code

• Conditional assembly for multi-purpose

source files

• Directives that allow complete control over the

assembly process

32.5 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

32.6 MPLAB Assembler, Linker and

Librarian for Various Device

Families

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC devices. MPLAB C Compiler uses

the assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich directive set

• Flexible macro language

• MPLAB IDE compatibility

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 387

PIC16(L)F1824/1828

32.7 MPLAB SIM Software Simulator

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC® DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C Compilers,

and the MPASM and MPLAB Assemblers. The soft-

ware simulator offers the flexibility to develop and

debug code outside of the hardware laboratory envi-

ronment, making it an excellent, economical software

development tool.

32.8 MPLAB REAL ICE In-Circuit

Emulator System

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs PIC® Flash MCUs and dsPIC® Flash DSCs

with the easy-to-use, powerful graphical user interface of

the MPLAB Integrated Development Environment (IDE),

included with each kit.

The emulator is connected to the design engineer’s PC

using a high-speed USB 2.0 interface and is connected

to the target with either a connector compatible with in-

circuit debugger systems (RJ11) or with the new high-

speed, noise tolerant, Low-Voltage Differential Signal

(LVDS) interconnection (CAT5).

The emulator is field upgradable through future firmware

downloads in MPLAB IDE. In upcoming releases of

MPLAB IDE, new devices will be supported, and new

features will be added. MPLAB REAL ICE offers

significant advantages over competitive emulators

including low-cost, full-speed emulation, run-time

variable watches, trace analysis, complex breakpoints, a

ruggedized probe interface and long (up to three meters)

interconnection cables.

32.9 MPLAB ICD 3 In-Circuit Debugger

System

MPLAB ICD 3 In-Circuit Debugger System is Micro-

chip's most cost effective high-speed hardware

debugger/programmer for Microchip Flash Digital Sig-

nal Controller (DSC) and microcontroller (MCU)

devices. It debugs and programs PIC® Flash microcon-

trollers and dsPIC® DSCs with the powerful, yet easy-

to-use graphical user interface of MPLAB Integrated

Development Environment (IDE).

The MPLAB ICD 3 In-Circuit Debugger probe is con-

nected to the design engineer's PC using a high-speed

USB 2.0 interface and is connected to the target with a

connector compatible with the MPLAB ICD 2 or MPLAB

REAL ICE systems (RJ-11). MPLAB ICD 3 supports all

MPLAB ICD 2 headers.

32.10 PICkit 3 In-Circuit Debugger/

Programmer and

PICkit 3 Debug Express

The MPLAB PICkit 3 allows debugging and program-

ming of PIC® and dsPIC® Flash microcontrollers at a

most affordable price point using the powerful graphical

user interface of the MPLAB Integrated Development

Environment (IDE). The MPLAB PICkit 3 is connected

to the design engineer's PC using a full speed USB

interface and can be connected to the target via an

Microchip debug (RJ-11) connector (compatible with

MPLAB ICD 3 and MPLAB REAL ICE). The connector

uses two device I/O pins and the reset line to imple-

ment in-circuit debugging and In-Circuit Serial Pro-

gramming™.

The PICkit 3 Debug Express include the PICkit 3, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

PIC16(L)F1824/1828

DS41419C-page 388 Preliminary  2010-2011 Microchip Technology Inc.

32.11 PICkit 2 Development

Programmer/Debugger and

PICkit 2 Debug Express

The PICkit™ 2 Development Programmer/Debugger is

a low-cost development tool with an easy to use inter-

face for programming and debugging Microchip’s Flash

families of microcontrollers. The full featured

Windows® programming interface supports baseline

(PIC10F, PIC12F5xx, PIC16F5xx), midrange

(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,

dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit

microcontrollers, and many Microchip Serial EEPROM

products. With Microchip’s powerful MPLAB Integrated

Development Environment (IDE) the PICkit™ 2

enables in-circuit debugging on most PIC® microcon-

trollers. In-Circuit-Debugging runs, halts and single

steps the program while the PIC microcontroller is

embedded in the application. When halted at a break-

point, the file registers can be examined and modified.

The PICkit 2 Debug Express include the PICkit 2, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

32.12 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an MMC card for file

storage and data applications.

32.13 Demonstration/Development

Boards, Evaluation Kits, and

Starter Kits

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

for analog filter design, KEELOQ® security ICs, CAN,

IrDA®, PowerSmart battery management, SEEVAL®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Also available are starter kits that contain everything

needed to experience the specified device. This usually

includes a single application and debug capability, all

on one board.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 389

PIC16(L)F1824/1828

33.0 PACKAGING INFORMATION

33.1 Package Marking Information

*Standard PICmicro® device marking consists of Microchip part number, year code, week code and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check

with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP

price.

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

14-Lead PDIP (300 mil) Example

PIC16F1824-I/P

1010017

14-Lead SOIC (3.90 mm) Example

PIC16F1824

-I/SL

1010017

Example

YYWW

NNN

XXXXXXXX

PIC16F1824/ST

1010

017

14-Lead TSSOP (4.4 mm)

PIC16(L)F1824/1828

DS41419C-page 390 Preliminary  2010-2011 Microchip Technology Inc.

33.2 Package Marking Information

*Standard PICmicro® device marking consists of Microchip part number, year code, week code and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check

with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP

price.

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

16-Lead QFN (4x4x0.9 mm) Example

PIN 1 PIN 1

-I/ML

1010017

16F1824

20-Lead PDIP (300 mil) Example

XXXXXXXXXXXXXXXXX

YYWWNNN

PIC16F1824-I/P

1010017

20-Lead SOIC (7.50 mm) Example

XXXXXXXXXXXX

YYWWNNN

XXXXXXXXXXXX

PICXXFXXXX-I

/SO

0610017

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 391

PIC16(L)F1824/1828

33.3 Package Marking Information

*Standard PICmicro® device marking consists of Microchip part number, year code, week code and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check

with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP

price.

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

20-Lead QFN (4x4x0.9 mm) Example

PIN 1 PIN 1

XXFXXX

-I/ML

0610017

20-Lead TSSOP Example

MCPXXXX

/SS017

0610

PIC16(L)F1824/1828

DS41419C-page 392 Preliminary  2010-2011 Microchip Technology Inc.

33.4 Package Details

The following sections give the technical details of the packages.

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

 



 

   

  

  

    

    

    

    

    

    

    

    

    

    

    

NOTE 1

123

A1 b1

   

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 393

PIC16(L)F1824/1828

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC16(L)F1824/1828

DS41419C-page 394 Preliminary  2010-2011 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 395

PIC16(L)F1824/1828



PIC16(L)F1824/1828

DS41419C-page 396 Preliminary  2010-2011 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 397

PIC16(L)F1824/1828

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC16(L)F1824/1828

DS41419C-page 398 Preliminary  2010-2011 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 399

PIC16(L)F1824/1828

!"#$%&'(()*"#



 

 

 

 

 



 

   

  

  

    

    

  

  

    

  

    

    

    

    

EXPOSED

PAD

NOTE 1

TOP VIEW BOTTOM VIEW

   

PIC16(L)F1824/1828

DS41419C-page 400 Preliminary  2010-2011 Microchip Technology Inc.



 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 401

PIC16(L)F1824/1828

+





 

 



 

   

  

  

    

    

    

    

    

    

    

    

    

    

    

NOTE 1

123

   

PIC16(L)F1824/1828

DS41419C-page 402 Preliminary  2010-2011 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 403

PIC16(L)F1824/1828

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC16(L)F1824/1828

DS41419C-page 404 Preliminary  2010-2011 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 405

PIC16(L)F1824/1828

+,-.-/%.0.,),..0



 

 



 

   

  

  

    

    

    

  

    

    

    

  

   

    

    

NOTE 1

L1 L

   

PIC16(L)F1824/1828

DS41419C-page 406 Preliminary  2010-2011 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 407

PIC16(L)F1824/1828

+"#$%&'(()*"#





 

 



 

   

  

  

    

    

  

  

    

  

    

    

    

    

EXPOSED

PAD

TOP VIEW NOTE 1

BOTTOM VIEW

   

PIC16(L)F1824/1828

DS41419C-page 408 Preliminary  2010-2011 Microchip Technology Inc.



 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 409

PIC16(L)F1824/1828

APPENDIX A: DATA SHEET

REVISION HISTORY

Revision A (06/2010)

Original release.

Revision B (12/2010)

Updated the data sheet to new format; Updated the

Electrical Specifications section; Revised Sections

24.2 and 24.3.1; Updated Figure 8-2; Revised the

Product Identification System section; Added the

Temperature Indicator section.

Revision C (09/2011)

Updated Table 3-3 and Register 20-1.

APPENDIX B: MIGRATING FROM

OTHER PIC®

DEVICES

This section provides comparisons when migrating

from other similar PIC® devices to the

PIC16F/LF1824/1828 family of devices.

B.1 PIC16F648A to PIC16F/LF1828

TABLE B-1: FEATURE COMPARISON

Feature PIC16F648A PIC16F/LF1828

Max. Operating

Speed

20 MHz 32 MHz

Max. Program

Memory (Words)

4K 4K

Max. SRAM (Bytes) 256 256

Max. EEPROM

(Bytes)

256 256

A/D Resolution 10-bit 10-bit

Timers (8/16-bit) 2/1 4/1

Brown-out Reset Y Y

Internal Pull-ups RB<7:0> RA<7:0>

RB<7:4>(1)

Interrupt-on-change RB<7:4> RA<5:0>, Edge

Selectable

RB<7:4>(1)

Comparator 2 2

AUSART/EUSART 1/0 0/1

Extended WDT N Y

Software Control

Option of WDT/BOR

INTOSC

Frequencies

48 kHz or

4 MHz

31 kHz -

32 MHz

Clock Switching Y Y

Capacitive Sensing N Y

CCP/ECCP 2/0 2/2

Enhanced PIC16

CPU

MSSPx/SSPx 0 1/0

Reference Clock N Y

Data Signal

Modulator

SR Latch N Y

Voltage Reference N Y

DAC Y Y

Note 1: PIC16F/LF1828 only.

PIC16(L)F1824/1828

DS41419C-page 410 Preliminary  2010-2011 Microchip Technology Inc.

Note 1: This device has been designed to perform to the parameters of its data sheet. It has been tested to an

electrical specification designed to determine its conformance with these parameters. Due to process dif-

ferences in the manufacture of this device, this device may have different performance characteristics than

its earlier version. These differences may cause this device to perform differently in your application than

the earlier version of this device.

Note 1: The user should verify that the device oscillator starts and performs as expected. Adjusting the loading

capacitor values and/or the oscillator mode may be required.

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 411

PIC16(L)F1824/1828

INDEX

A/D

Specifications............................................................ 373

Absolute Maximum Ratings .............................................. 351

AC Characteristics

Industrial and Extended ............................................ 366

Load Conditions ........................................................ 365

ACKSTAT ......................................................................... 279

ACKSTAT Status Flag ...................................................... 279

ADC .................................................................................. 149

Acquisition Requirements ......................................... 159

Associated registers.................................................. 161

Block Diagram........................................................... 149

Calculating Acquisition Time..................................... 159

Channel Selection..................................................... 150

Configuration............................................................. 150

Configuring Interrupt ................................................. 154

Conversion Clock...................................................... 150

Conversion Procedure .............................................. 154

Internal Sampling Switch (RSS) Impedance.............. 159

Interrupts................................................................... 152

Operation .................................................................. 153

Operation During Sleep ............................................ 153

Port Configuration..................................................... 150

Reference Voltage (VREF)......................................... 150

Source Impedance.................................................... 159

Special Event Trigger................................................ 153

Starting an A/D Conversion ......................................152

ADCON0 Register....................................................... 34, 155

ADCON1 Register....................................................... 34, 156

ADDFSR ........................................................................... 341

ADDWFC .......................................................................... 341

ADRESH Register............................................................... 34

ADRESH Register (ADFM = 0) ......................................... 157

ADRESH Register (ADFM = 1) ......................................... 158

ADRESL Register (ADFM = 0).......................................... 157

ADRESL Register (ADFM = 1).......................................... 158

Alternate Pin Function.......................................................121

Analog-to-Digital Converter. See ADC

ANSELA Register ............................................................. 127

ANSELB Register ............................................................. 133

ANSELC Register ............................................................. 138

APFCON0 Register........................................................... 122

APFCON1 Register........................................................... 123

Assembler

MPASM Assembler................................................... 386

BAUDCON Register.......................................................... 308

BF ............................................................................. 279, 281

BF Status Flag .......................................................... 279, 281

Block Diagram

Capacitive Sensing ........................................... 325, 326

Block Diagrams

(CCP) Capture Mode Operation ............................... 216

ADC .......................................................................... 149

ADC Transfer Function ............................................. 160

Analog Input Model ........................................... 160, 180

CCP PWM................................................................. 220

Clock Source............................................................... 58

Compare ................................................................... 218

Crystal Operation .................................................. 60, 61

Digital-to-Analog Converter (DAC)............................ 164

EUSART Receive ..................................................... 298

EUSART Transmit .................................................... 297

External RC Mode ...................................................... 61

Fail-Safe Clock Monitor (FSCM)................................. 69

Generic I/O Port........................................................ 121

Interrupt Logic............................................................. 87

On-Chip Reset Circuit................................................. 79

Peripheral Interrupt Logic ........................................... 88

PIC16F/LF1824/1828 ................................................. 22

PIC16F/LF1826/27 ..................................................... 14

PWM (Enhanced) ..................................................... 224

Resonator Operation .................................................. 60

Timer0 ...................................................................... 185

Timer1 ...................................................................... 189

Timer1 Gate.............................................. 194, 195, 196

Timer2/4/6 ................................................................ 201

Voltage Reference.................................................... 145

Voltage Reference Output Buffer Example .............. 164

BORCON Register.............................................................. 81

BRA .................................................................................. 342

Break Character (12-bit) Transmit and Receive ............... 317

Brown-out Reset (BOR)...................................................... 81

Specifications ........................................................... 371

Timing and Characteristics ....................................... 370

C Compilers

MPLAB C18.............................................................. 386

CALL................................................................................. 343

CALLW ............................................................................. 343

Capacitive Sensing ........................................................... 325

Associated registers w/ Capacitive Sensing............. 332

Specifications ........................................................... 382

Capture Module. See Enhanced Capture/Compare/

PWM(ECCP)

Capture/Compare/PWM ................................................... 215

Capture/Compare/PWM (CCP)

Associated Registers w/ Capture ............................. 217

Associated Registers w/ Compare ........................... 219

Associated Registers w/ PWM ......................... 223, 237

Capture Mode........................................................... 216

CCPx Pin Configuration............................................ 216

Compare Mode......................................................... 218

CCPx Pin Configuration.................................... 218

Software Interrupt Mode........................... 216, 218

Special Event Trigger ....................................... 218

Timer1 Mode Resource ............................ 216, 218

Prescaler .................................................................. 216

PWM Mode

Duty Cycle ........................................................ 221

Effects of Reset ................................................ 223

Example PWM Frequencies and

Resolutions, 20 MHZ................................ 222

Example PWM Frequencies and

Resolutions, 32 MHZ................................ 222

Example PWM Frequencies and

Resolutions, 8 MHz .................................. 222

Operation in Sleep Mode.................................. 223

Resolution ........................................................ 222

System Clock Frequency Changes .................. 223

PWM Operation ........................................................ 220

PWM Overview......................................................... 220

PWM Period ............................................................. 221

PWM Setup .............................................................. 221

PIC16(L)F1824/1828

DS41419C-page 412 Preliminary  2010-2011 Microchip Technology Inc.

CCP1CON Register ...................................................... 38, 39

CCPR1H Register ......................................................... 38, 39

CCPR1L Register.......................................................... 38, 39

CCPTMRS0 Register........................................................239

CCPxAS Register..............................................................240

CCPxCON (ECCPx) Register ........................................... 238

CLKRCON Register ............................................................ 76

Clock Accuracy with Asynchronous Operation ................. 306

Clock Sources

External Modes ........................................................... 59

EC ....................................................................... 59

HS ....................................................................... 59

LP........................................................................59

OST..................................................................... 60

RC....................................................................... 61

XT ....................................................................... 59

Internal Modes ............................................................ 62

HFINTOSC.......................................................... 62

Internal Oscillator Clock Switch Timing...............64

LFINTOSC .......................................................... 63

MFINTOSC ......................................................... 62

Clock Switching................................................................... 66

CMOUT Register............................................................... 182

CMxCON0 Register ..........................................................181

CMxCON1 Register ..........................................................182

Code Examples

A/D Conversion.........................................................154

Changing Between Capture Prescalers .................... 216

Initializing PORTA..................................................... 124

Initializing PORTB..................................................... 130

Initializing PORTC.....................................................135

Write Verify ............................................................... 117

Writing to Flash Program Memory ............................115

Comparator

Associated Registers ................................................ 183

Operation .................................................................. 175

Comparator Module ..........................................................175

Cx Output State Versus Input Conditions ................. 177

Comparator Specifications................................................375

Comparators

C2OUT as T1 Gate ...................................................191

Compare Module. See Enhanced Capture/

Compare/PWM (ECCP)

CONFIG1 Register..............................................................52

CONFIG2 Register..............................................................54

CPSCON0 Register .......................................................... 331

CPSCON1 Register .......................................................... 332

Customer Change Notification Service ............................. 419

Customer Notification Service...........................................419

Customer Support .............................................................419

DACCON0 (Digital-to-Analog Converter Control 0)

DACCON1 (Digital-to-Analog Converter Control 1)

Data EEPROM Memory ....................................................107

Associated Registers ................................................ 120

Code Protection ........................................................ 108

Reading..................................................................... 108

Writing....................................................................... 108

Data Memory....................................................................... 25

DC and AC Characteristics ............................................... 383

DC Characteristics

Extended and Industrial ............................................ 362

Industrial and Extended ............................................ 354

Development Support ....................................................... 385

Device Configuration .......................................................... 51

Code Protection.......................................................... 55

Configuration Word..................................................... 51

User ID ................................................................. 55, 56

Device Overview......................................................... 13, 103

Digital-to-Analog Converter (DAC) ................................... 163

Associated Registers ................................................ 167

Effects of a Reset ..................................................... 164

Specifications ........................................................... 375

ECCP/CCP. See Enhanced Capture/Compare/PWM

EEADR Registers ............................................................. 107

EEADRH Registers........................................................... 107

EEADRL Register............................................................. 118

EEADRL Registers ........................................................... 107

EECON1 Register..................................................... 107, 119

EECON2 Register..................................................... 107, 120

EEDATH Register............................................................. 118

EEDATL Register ............................................................. 118

EEPROM Data Memory

Avoiding Spurious Write ........................................... 108

Write Verify ............................................................... 117

Effects of Reset

PWM mode............................................................... 223

Electrical Specifications.................................................... 351

Enhanced Capture/Compare/PWM (ECCP)..................... 215

Enhanced PWM Mode.............................................. 224

Auto-Restart ..................................................... 233

Auto-shutdown.................................................. 232

Direction Change in Full-Bridge Output Mode.. 230

Full-Bridge Application...................................... 228

Full-Bridge Mode .............................................. 228

Half-Bridge Application ..................................... 227

Half-Bridge Application Examples .................... 234

Half-Bridge Mode.............................................. 227

Output Relationships (Active-High and

Active-Low)............................................... 225

Output Relationships Diagram.......................... 226

Programmable Dead Band Delay..................... 234

Shoot-through Current...................................... 234

Start-up Considerations .................................... 236

Specifications ........................................................... 372

Enhanced Mid-Range CPU ................................................ 21

Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART) .............................. 297

Errata .................................................................................. 12

EUSART ........................................................................... 297

Associated Registers

Baud Rate Generator ....................................... 310

Asynchronous Mode ................................................. 299

12-bit Break Transmit and Receive .................. 317

Associated Registers

Receive .................................................... 305

Transmit.................................................... 301

Auto-Wake-up on Break ................................... 315

Baud Rate Generator (BRG) ............................ 309

Clock Accuracy................................................. 306

Receiver ........................................................... 302

Setting up 9-bit Mode with Address Detect ...... 304

Transmitter ....................................................... 299

Baud Rate Generator (BRG)

Auto Baud Rate Detect..................................... 314

Baud Rate Error, Calculating............................ 309

Baud Rates, Asynchronous Modes .................. 311

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 413

PIC16(L)F1824/1828

Formulas........................................................... 310

High Baud Rate Select (BRGH Bit) .................. 309

Synchronous Master Mode ............................... 318, 322

Associated Registers

Receive..................................................... 321

Transmit.................................................... 319

Reception.......................................................... 320

Transmission .................................................... 318

Synchronous Slave Mode

Associated Registers

Receive..................................................... 323

Transmit.................................................... 322

Reception.......................................................... 323

Transmission .................................................... 322

Extended Instruction Set

ADDFSR ................................................................... 341

Fail-Safe Clock Monitor....................................................... 69

Fail-Safe Condition Clearing....................................... 69

Fail-Safe Detection ..................................................... 69

Fail-Safe Operation..................................................... 69

Reset or Wake-up from Sleep..................................... 69

Firmware Instructions........................................................ 337

Fixed Voltage Reference (FVR)........................................ 145

Associated Registers ................................................ 146

Flash Program Memory .................................................... 107

Erasing...................................................................... 112

Modifying................................................................... 116

Writing....................................................................... 112

FSR Register .......... 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43

FVRCON (Fixed Voltage Reference Control) Register..... 146

I2C Mode (MSSPx)

Acknowledge Sequence Timing................................ 283

Bus Collision

During a Repeated Start Condition................... 288

During a Stop Condition.................................... 289

Effects of a Reset...................................................... 284

I2C Clock Rate w/BRG.............................................. 291

Master Mode

Operation .......................................................... 275

Reception.......................................................... 281

Start Condition Timing .............................. 277, 278

Transmission .................................................... 279

Multi-Master Communication, Bus Collision

and Arbitration .................................................. 284

Multi-Master Mode .................................................... 284

Read/Write Bit Information (R/W Bit) ........................ 260

Slave Mode

Transmission .................................................... 265

Sleep Operation ........................................................ 284

Stop Condition Timing............................................... 283

INDF Register ......... 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43

Indirect Addressing ............................................................. 47

INLVLA Register ............................................................... 128

INLVLB Register ............................................................... 133

Instruction Format............................................................. 338

Instruction Set ................................................................... 337

ADDLW ..................................................................... 341

ADDWF..................................................................... 341

ADDWFC .................................................................. 341

ANDLW ..................................................................... 341

ANDWF..................................................................... 341

BRA........................................................................... 342

CALL......................................................................... 343

CALLW ..................................................................... 343

LSLF ......................................................................... 345

LSRF ........................................................................ 345

MOVF ....................................................................... 345

MOVIW ..................................................................... 346

MOVLB ..................................................................... 346

MOVWI..................................................................... 347

OPTION.................................................................... 347

RESET...................................................................... 347

SUBWFB .................................................................. 349

TRIS ......................................................................... 350

BCF .......................................................................... 342

BSF........................................................................... 342

BTFSC...................................................................... 342

BTFSS ...................................................................... 342

CALL......................................................................... 343

CLRF ........................................................................ 343

CLRW ....................................................................... 343

CLRWDT .................................................................. 343

COMF ....................................................................... 343

DECF........................................................................ 343

DECFSZ ................................................................... 344

GOTO ....................................................................... 344

INCF ......................................................................... 344

INCFSZ..................................................................... 344

IORLW...................................................................... 344

IORWF...................................................................... 344

MOVLW .................................................................... 346

MOVWF.................................................................... 346

NOP.......................................................................... 347

RETFIE..................................................................... 348

RETLW ..................................................................... 348

RETURN................................................................... 348

RLF........................................................................... 348

RRF .......................................................................... 349

SLEEP ...................................................................... 349

SUBLW..................................................................... 349

SUBWF..................................................................... 349

SWAPF..................................................................... 350

XORLW .................................................................... 350

XORWF .................................................................... 350

INTCON Register................................................................ 93

Internal Oscillator Block

INTOSC

Specifications ................................................... 367

Internal Sampling Switch (RSS) Impedance ..................... 159

Internet Address ............................................................... 419

Interrupt-On-Change......................................................... 141

Associated Registers................................................ 144

Interrupts ............................................................................ 87

ADC .......................................................................... 154

Associated registers w/ Interrupts ............................ 100

Configuration Word w/ Clock Sources........................ 73

Configuration Word w/ Reference Clock Sources ...... 77

TMR1........................................................................ 193

INTOSC Specifications ..................................................... 367

IOCAF Register ................................................................ 142

IOCAN Register................................................................ 142

IOCAP Register ................................................................ 142

IOCBF Register ................................................................ 144

IOCBN Register................................................................ 143

IOCBP Register ................................................................ 143

LATA Register .......................................................... 127, 137

PIC16(L)F1824/1828

DS41419C-page 414 Preliminary  2010-2011 Microchip Technology Inc.

LATB Register................................................................... 132

Load Conditions ................................................................ 365

LSLF.................................................................................. 345

LSRF ................................................................................. 345

Master Synchronous Serial Port. See MSSPx

MCLR .................................................................................. 82

Internal ........................................................................82

MDCARH Register............................................................ 212

MDCARL Register.............................................................213

MDCON Register .............................................................. 210

MDSRC Register...............................................................211

Memory Organization.......................................................... 23

Data ............................................................................ 25

Program ......................................................................23

Microchip Internet Web Site..............................................419

Migrating from other PIC Microcontroller Devices............. 409

MOVIW.............................................................................. 346

MOVLB.............................................................................. 346

MOVWI.............................................................................. 347

MPLAB ASM30 Assembler, Linker, Librarian ................... 386

MPLAB Integrated Development Environment Software .. 385

MPLAB PM3 Device Programmer.....................................388

MPLAB REAL ICE In-Circuit Emulator System.................387

MPLINK Object Linker/MPLIB Object Librarian ................386

MSSPx .............................................................................. 243

I2C Mode Operation .................................................. 256

SPI Mode ..................................................................246

SSPxBUF Register ...................................................250

SSPxSR Register...................................................... 250

OPCODE Field Descriptions ............................................. 337

OPTION ............................................................................ 347

OPTION Register.............................................................. 187

OSCCON Register..............................................................71

Oscillator

Associated Registers ..................................................73

Oscillator Module ................................................................57

ECH ............................................................................ 57

ECL ............................................................................. 57

ECM ............................................................................ 57

HS ............................................................................... 57

INTOSC ......................................................................57

LP................................................................................ 57

RC............................................................................... 57

XT ............................................................................... 57

Oscillator Parameters........................................................ 367

Oscillator Specifications....................................................366

Oscillator Start-up Timer (OST)

Specifications............................................................ 371

Oscillator Switching

Fail-Safe Clock Monitor...............................................69

Two-Speed Clock Start-up.......................................... 67

OSCSTAT Register.............................................................72

OSCTUNE Register ............................................................ 73

P1A/P1B/P1C/P1D.See Enhanced Capture/

Compare/PWM (ECCP) ............................................224

Packaging ......................................................................... 389

Marking ..................................................... 389, 390, 391

PDIP Details..............................................................392

PCL and PCLATH ............................................................... 22

PCL Register........... 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43

PCLATH Register ... 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43

PCON Register............................................................. 34, 85

PIE1 Register................................................................ 34, 94

PIE2 Register................................................................ 34, 95

PIE3 Register................................................................ 34, 96

Pinout Descriptions

PIC16F/LF1826/27 ............................................... 15, 18

PIR1 Register ............................................................... 33, 97

PIR2 Register ............................................................... 33, 98

PIR3 Register ............................................................... 33, 99

PORTA ............................................................................. 124

ANSELA Register ..................................................... 124

Associated Registers ................................................ 129

Configuration Word w/ PORTA................................. 129

LATA Register ............................................................ 35

PORTA Register......................................................... 33

Specifications ........................................................... 369

PORTA Register............................................................... 126

PORTB

ANSELB Register ..................................................... 130

Associated Registers ................................................ 134

LATB Register ............................................................ 35

Pin Descriptions and Diagrams ................................ 131

PORTB Register......................................................... 33

PORTB Register............................................................... 132

PORTC

ANSELC Register ..................................................... 135

Associated Registers ................................................ 139

LATC Register ............................................................ 35

Pin Descriptions and Diagrams ................................ 136

PORTC Register......................................................... 33

PORTC Register............................................................... 137

Power-Down Mode (Sleep)............................................... 101

Associated Registers........................................ 102, 213

Power-on Reset.................................................................. 80

Power-up Time-out Sequence ............................................ 82

Power-up Timer (PWRT) .................................................... 80

Specifications ........................................................... 371

PR2 Register ...................................................................... 33

PR4 Register ...................................................................... 41

PR6 Register ...................................................................... 41

Precision Internal Oscillator Parameters .......................... 367

Program Memory ................................................................ 23

Map and Stack (PIC16F/LF1826) ............................... 24

Map and Stack (PIC16F/LF1826/27) .................... 23, 24

Programming, Device Instructions.................................... 337

PSTRxCON Register........................................................ 242

PWM (ECCP Module)

PWM Steering........................................................... 235

Steering Synchronization.......................................... 236

PWM Mode. See Enhanced Capture/Compare/PWM ...... 224

PWM Steering................................................................... 235

PWMxCON Register......................................................... 241

RCREG............................................................................. 304

RCREG Register ................................................................ 36

RCSTA Register ......................................................... 36, 307

Reader Response............................................................. 420

Read-Modify-Write Operations ......................................... 337

Reference Clock ................................................................. 75

Associated Registers .................................................. 77

Registers

ADCON0 (ADC Control 0) ........................................ 155

ADCON1 (ADC Control 1) ........................................ 156

ADRESH (ADC Result High) with ADFM = 0) .......... 157

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 415

PIC16(L)F1824/1828

ADRESH (ADC Result High) with ADFM = 1)........... 158

ADRESL (ADC Result Low) with ADFM = 0)............ 157

ADRESL (ADC Result Low) with ADFM = 1)............ 158

ANSELA (PORTA Analog Select)............................. 127

ANSELB (PORTB Analog Select)............................. 133

ANSELC (PORTC Analog Select) ............................ 138

APFCON0 (Alternate Pin Function Control 0)........... 122

APFCON1 (Alternate Pin Function Control 1)........... 123

BAUDCON (Baud Rate Control) ............................... 308

BORCON Brown-out Reset Control)........................... 81

CCPTMRS0 (PWM Timer Selection Control 0) ........ 239

CCPxAS (CCPx Auto-Shutdown Control)................. 240

CCPxCON (ECCPx Control)..................................... 238

CLKRCON (Reference Clock Control)........................ 76

CMOUT (Comparator Output)................................... 182

CMxCON0 (Cx Control) ............................................ 181

CMxCON1 (Cx Control 1) ......................................... 182

Configuration Word 1 .................................................. 52

Configuration Word 2 .................................................. 54

CPSCON0 (Capacitive Sensing Control Register 0) 331

CPSCON1 (Capacitive Sensing Control Register 1) 332

DACCON0 ................................................................ 166

DACCON1 ................................................................ 166

EEADRL (EEPROM Address) .................................. 118

EECON1 (EEPROM Control 1)................................. 119

EECON2 (EEPROM Control 2)................................. 120

EEDATH (EEPROM Data)........................................ 118

EEDATL (EEPROM Data) ........................................ 118

FVRCON................................................................... 146

INLVLA (Input Level Control PORTA)....................... 128

INLVLB (Input Level Control PORTB)....................... 133

INLVLC (Input Level Control PORTC) ...................... 139

INTCON (Interrupt Control)......................................... 93

IOCAF (Interrupt-on-Change PORTA Flag).............. 142

IOCAN (Interrupt-on-Change PORTA Negative

Edge) ................................................................ 142

IOCAP (Interrupt-on-Change PORTA Positive

Edge) ................................................................ 142

IOCBF (Interrupt-on-Change PORTB Flag).............. 144

IOCBN (Interrupt-on-Change PORTB Negative

Edge) ................................................................ 143

IOCBP (Interrupt-on-Change PORTB Positive

Edge) ................................................................ 143

LATA (Data Latch PORTA)....................................... 127

LATB (Data Latch PORTB)....................................... 132

LATC (Data Latch PORTC) ...................................... 137

MDCARH (Modulation High Carrier Control

MDCARL (Modulation Low Carrier Control Register)213

MDCON (Modulation Control Register) .................... 210

MDSRC (Modulation Source Control Register) ........ 211

OPTION_REG (OPTION) ......................................... 187

OSCCON (Oscillator Control) ..................................... 71

OSCSTAT (Oscillator Status) ..................................... 72

OSCTUNE (Oscillator Tuning).................................... 73

PCON (Power Control Register) ................................. 85

PCON (Power Control) ............................................... 85

PIE1 (Peripheral Interrupt Enable 1)........................... 94

PIE2 (Peripheral Interrupt Enable 2)........................... 95

PIE3 (Peripheral Interrupt Enable 3)........................... 96

PIR1 (Peripheral Interrupt Register 1) ........................ 97

PIR2 (Peripheral Interrupt Request 2) ........................ 98

PIR3 (Peripheral Interrupt Request 3) ........................ 99

PORTA...................................................................... 126

PORTB...................................................................... 132

PORTC ..................................................................... 137

PSTRxCON (PWM Steering Control) ....................... 242

PWMxCON (Enhanced PWM Control) ..................... 241

RCREG..................................................................... 314

RCSTA (Receive Status and Control) ...................... 307

SPBRGH .................................................................. 309

SPBRGL ................................................................... 309

Special Function, Summary........................................ 33

SRCON0 (SR Latch Control 0) ................................. 171

SRCON1 (SR Latch Control 1) ................................. 172

SSPxADD (MSSPx Address and Baud Rate,

I2C Mode) ......................................................... 296

SSPxCON1 (MSSPx Control 1)................................ 293

SSPxCON2 (SSPx Control 2)................................... 294

SSPxCON3 (SSPx Control 3)................................... 295

SSPxMSK (SSPx Mask) ........................................... 296

SSPxSTAT (SSPx Status)........................................ 292

STATUS ..................................................................... 26

T1CON (Timer1 Control) .......................................... 197

T1GCON (Timer1 Gate Control)............................... 198

TRISA (Tri-State PORTA) ........................................ 126

TRISB (Tri-State PORTB) ........................................ 132

TRISC (Tri-State PORTC) ........................................ 137

TXCON ..................................................................... 203

TXSTA (Transmit Status and Control)...................... 306

WDTCON (Watchdog Timer Control) ....................... 105

WPUA (Weak Pull-up PORTA)................................. 128

WPUB (Weak Pull-up PORTB)................................. 133

WPUC (Weak Pull-up PORTC) ................................ 138

RESET.............................................................................. 347

Reset .................................................................................. 79

Reset Instruction................................................................. 82

Resets ................................................................................ 79

Associated Registers.................................................. 86

Revision History................................................................ 409

Shoot-through Current ...................................................... 234

Software Simulator (MPLAB SIM) .................................... 387

SPBRG Register................................................................. 36

SPBRGH Register ............................................................ 309

SPBRGL Register............................................................. 309

Special Event Trigger ....................................................... 153

Special Function Registers (SFRs)..................................... 33

SPI Mode (MSSPx)

Associated Registers................................................ 254

SPI Clock.................................................................. 250

SR Latch........................................................................... 169

Associated registers w/ SR Latch............................. 173

SRCON0 Register ............................................................ 171

SRCON1 Register ............................................................ 172

SSP1ADD Register............................................................. 37

SSP1BUF Register ............................................................. 37

SSP1CON Register ............................................................ 37

SSP1CON2 Register .......................................................... 37

SSP1CON3 Register .......................................................... 37

SSP1MSK Register ............................................................ 37

SSP1STAT Register ........................................................... 37

SSPxADD Register........................................................... 296

SSPxCON1 Register ........................................................ 293

SSPxCON2 Register ........................................................ 294

SSPxCON3 Register ........................................................ 295

SSPxMSK Register........................................................... 296

SSPxOV ........................................................................... 281

SSPxOV Status Flag ........................................................ 281

SSPxSTAT Register ......................................................... 292

PIC16(L)F1824/1828

DS41419C-page 416 Preliminary  2010-2011 Microchip Technology Inc.

R/W Bit......................................................................260

Stack ................................................................................... 45

Accessing.................................................................... 45

Reset........................................................................... 47

Stack Overflow/Underflow...................................................82

STATUS Register................................................................26

SUBWFB........................................................................... 349

T1CON Register.......................................................... 33, 197

T1GCON Register.............................................................198

T2CON Register..................................................................33

T4CON Register..................................................................41

T6CON Register..................................................................41

Temperature Indicator Module .......................................... 147

Thermal Considerations....................................................364

Timer0 ............................................................................... 185

Associated Registers ................................................ 188

Operation .................................................................. 185

Specifications............................................................ 372

Timer1 ............................................................................... 189

Associated registers.................................................. 199

Asynchronous Counter Mode ................................... 191

Reading and Writing ......................................... 191

Clock Source Selection.............................................190

Interrupt..................................................................... 193

Operation .................................................................. 190

Operation During Sleep ............................................193

Oscillator ................................................................... 191

Prescaler................................................................... 191

Specifications............................................................ 372

Timer1 Gate

Selecting Source...............................................191

TMR1H Register ....................................................... 189

TMR1L Register........................................................189

Timer2

Associated registers.................................................. 204

Timer2/4/6 ......................................................................... 201

Associated registers.................................................. 204

Timers

Timer1

T1CON.............................................................. 197

T1GCON ........................................................... 198

Timer2/4/6

TXCON ............................................................. 203

Timing Diagrams

A/D Conversion.........................................................374

A/D Conversion (Sleep Mode) .................................. 374

Acknowledge Sequence ........................................... 283

Asynchronous Reception .......................................... 304

Asynchronous Transmission ..................................... 300

Asynchronous Transmission (Back to Back) ............ 301

Auto Wake-up Bit (WUE) During Normal Operation . 316

Auto Wake-up Bit (WUE) During Sleep .................... 316

Automatic Baud Rate Calibration.............................. 314

Baud Rate Generator with Clock Arbitration ............. 276

BRG Reset Due to SDA Arbitration During Start

Condition........................................................... 287

Brown-out Reset (BOR) ............................................ 370

Brown-out Reset Situations ........................................81

Bus Collision During a Repeated Start Condition

(Case 1) ............................................................288

Bus Collision During a Repeated Start Condition

(Case 2) ............................................................288

Bus Collision During a Start Condition (SCL = 0) .....287

Bus Collision During a Stop Condition (Case 1) .......289

Bus Collision During a Stop Condition (Case 2) ....... 289

Bus Collision During Start Condition (SDA only) ...... 286

Bus Collision for Transmit and Acknowledge ........... 285

CLKOUT and I/O ...................................................... 368

Clock Synchronization .............................................. 273

Clock Timing............................................................. 366

Comparator Output ................................................... 175

Enhanced Capture/Compare/PWM (ECCP)............. 372

Fail-Safe Clock Monitor (FSCM)................................. 70

First Start Bit Timing ................................................. 277

Full-Bridge PWM Output........................................... 229

Half-Bridge PWM Output .................................. 227, 234

I2C Bus Data............................................................. 380

I2C Bus Start/Stop Bits ............................................. 379

I2C Master Mode (7 or 10-Bit Transmission) ............ 280

I2C Master Mode (7-Bit Reception)........................... 282

I2C Stop Condition Receive or Transmit Mode......... 284

INT Pin Interrupt ......................................................... 91

Internal Oscillator Switch Timing ................................ 65

PWM Auto-shutdown................................................ 233

Firmware Restart .............................................. 232

PWM Direction Change ............................................ 230

PWM Direction Change at Near 100% Duty Cycle... 231

PWM Output (Active-High) ....................................... 225

PWM Output (Active-Low) ........................................ 226

Repeat Start Condition ............................................. 278

Reset Start-up Sequence ........................................... 83

Reset, WDT, OST and Power-up Timer ................... 369

Send Break Character Sequence............................. 317

SPI Master Mode (CKE = 1, SMP = 1) ..................... 377

SPI Mode (Master Mode).......................................... 250

SPI Slave Mode (CKE = 0) ....................................... 378

SPI Slave Mode (CKE = 1) ....................................... 378

Synchronous Reception (Master Mode, SREN) ....... 321

Synchronous Transmission ...................................... 319

Synchronous Transmission (Through TXEN) ........... 319

Timer0 and Timer1 External Clock ........................... 371

Timer1 Incrementing Edge ....................................... 193

Two Speed Start-up.................................................... 68

USART Synchronous Receive (Master/Slave) ......... 376

USART Synchronous Transmission (Master/Slave). 375

Wake-up from Interrupt............................................. 102

Timing Diagrams and Specifications

PLL Clock ................................................................. 367

Timing Parameter Symbology .......................................... 365

Timing Requirements

I2C Bus Data............................................................. 381

SPI Mode .................................................................. 379

TINLVLC Register............................................................. 139

TMR0 Register.................................................................... 33

TMR1H Register................................................................. 33

TMR1L Register.................................................................. 33

TMR2 Register.................................................................... 33

TMR4 Register.................................................................... 41

TMR6 Register.................................................................... 41

TRIS.................................................................................. 350

TRISA Register........................................................... 34, 126

TRISB ............................................................................... 130

TRISB Register........................................................... 34, 132

TRISC ............................................................................... 135

TRISC Register........................................................... 34, 137

Two-Speed Clock Start-up Mode........................................ 67

TXCON (Timer2/4/6) Register .......................................... 203

TXREG ............................................................................. 299

TXREG Register................................................................. 36

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 417

PIC16(L)F1824/1828

TXSTA Register .......................................................... 36, 306

BRGH Bit .................................................................. 309

USART

Synchronous Master Mode

Requirements, Synchronous Receive .............. 376

Requirements, Synchronous Transmission ...... 376

Timing Diagram, Synchronous Receive ........... 376

Timing Diagram, Synchronous Transmission ... 375

VREF. SEE ADC Reference Voltage

Wake-up on Break ............................................................ 315

Wake-up Using Interrupts ................................................. 101

Watchdog Timer (WDT) ...................................................... 82

Modes ....................................................................... 104

Specifications............................................................ 371

WCOL ....................................................... 276, 279, 281, 283

WCOL Status Flag .................................... 276, 279, 281, 283

WDTCON Register ........................................................... 105

WPUA Register................................................................. 128

WPUB Register................................................................. 133

WPUC Register................................................................. 138

Write Protection .................................................................. 55

WWW Address.................................................................. 419

WWW, On-Line Support ..................................................... 12

PIC16(L)F1824/1828

DS41419C-page 418 Preliminary  2010-2011 Microchip Technology Inc.

NOTES:

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 419

PIC16(L)F1824/1828

THE MICROCHIP WEB SITE

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

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will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com. Under “Support”, click on

“Customer Change Notification” and follow the

registration instructions.

CUSTOMER SUPPORT

Users of Microchip products can receive assistance

through several channels:

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Customers should contact their distributor,

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support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

Technical support is available through the web site

at: http://microchip.com/support

PIC16(L)F1824/1828

DS41419C-page 420  2010-2011 Microchip Technology Inc.

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip

product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our

documentation can better serve you, please FAX your comments to the Technical Publications Manager at

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DS41419CPIC16(L)F1824/1828

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

 2010-2011 Microchip Technology Inc. Preliminary DS41419C-page 421

PIC16(L)F1824/1828

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X/XX XXX

PatternPackageTemperature

Range

Device

Device: PIC16F1824(1), PIC16F1828(1), PIC16F1824T(2),

PIC16F1828T(2);

VDD range 1.8V to 5.5V

PIC16LF1824(1), PIC16LF1828(1), PIC16LF1824T(2),

PIC16LF1828T(2);

VDD range 1.8V to 3.6V

Temperature

Range:

I= -40C to +85C (Industrial)

E= -40C to +125C (Extended)

Package: ML = Micro Lead Frame (QFN) 4x4

P = Plastic DIP

SL = SOIC, 14 lead

SO = SOIC, 20 lead

SS = SSOP, 20 lead

ST = TSSOP, 14 lead

Pattern: QTP, SQTP, Code or Special Requirements

(blank otherwise)

Examples:

a) PIC16F1824 - I/ML 301 = Industrial temp., QFN

package, Extended VDD limits, QTP pattern

#301.

b) PIC16F1828 - I/P = Industrial temp., PDIP

package, Extended VDD limits.

c) PIC16F1828 - E/SS= Extended temp., SSOP

package, normal VDD limits.

Note 1: F = Wide Voltage Range

LF = Standard Voltage Range

2: T = i n t a p e a n d r e e l S O I C , S S O P ,

TSSOP, and QFN packages only.

DS41419C-page 422 Preliminary  2010-2011 Microchip Technology Inc.

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Fax: 91-11-4160-8632

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-330-9305

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Worldwide Sales and Service

08/02/11