ISD5008SIR - Nuvoton Technology

ISD · 2727 North First Street, San Jose, CA 95134 · TEL: 408/943-6666 · FAX: 408/544-1787 · http://www.isd.com

August 2000

Figure: ISD5008 Block Diagram

AUX IN

AMP

1.0/1.414/2.0/2.828

AGC

SUM1 MUX

Vol MUX

Filter

MUX

SUM1

FTHRU

INP

ANA OUT MUX

VOL

SUM2

ANA IN

SUM2 SP+

SP-

SPEAKER

AUX OUT

ANA OUT-

ANA OUT+

MIC+

MIC -

AGCCAP

MICROPHONE

AUX IN

XCLK

ANA IN

VSSA

VCCA

Input Source MUX

FILTO

SUM1

INP

ANA IN

SUM2

FILTO

VOL

SUM1

Summing

AMP

ANA IN

AMP

0.625/0.883/1.25/1.76

6dB

SUM2

Summing

AMP

Output MUX

Volume

Control

MIC IN

AUX IN FILTO

ANA IN

SUM1 ANA IN

FILTO

ARRAY

INP

SUM1 MUX

ARRAY

Spkr.

AMP

AUX

OUT

AMP

VSSA VSSD VSSD VCCD

VCCD

Device Control

ANA

OUT

AMP

ΣΣ

( )

VLS0

VLS1

( )

AIG0

AIG1

2( )

AXG0

AXG1

( )

S1S0

S1S1

( )

S1M0

S1M1 2

( )

S2M0

S2M1

( )

OPA0

OPA1

( )

OPS0

OPS1

Internal

Clock Multilevel

Storage Array

( )

FLD0

FLD1

(INS0)1

(AXPD)

(AGPD) 1

(FLPD)

(FLS0)

(AIPD)

(AOPD)

( )

AOS0

AOS1

AOS2

( )

VOL0

VOL1

VOL2

CAR KIT

CHIP SET

CAR KIT

CHIP SET

Low Pass

Filter

VSSA

Power Conditioning

MISOMOSISSSCLK RACINT

(VLPD)

AUX IN

AMP

1.0/1.414/2.0/2.828

AGC

SUM1 MUX

Vol MUX

Filter

MUX

SUM1

FTHRU

INP

ANA OUT MUX

VOL

SUM2

ANA IN

SUM2 SP+

SP-

SPEAKER

AUX OUT

ANA OUT-

ANA OUT+

MIC+

MIC -

AGCCAP

MICROPHONE

AUX IN

XCLK

ANA IN

VSSA

VCCA

Input Source MUX

FILTO

SUM1

INP

ANA IN

SUM2

FILTO

VOL

SUM1

Summing

AMP

ANA IN

AMP

0.625/0.883/1.25/1.76

6dB

SUM2

Summing

AMP

Output MUX

Volume

Control

MIC IN

AUX IN FILTO

ANA IN

SUM1 ANA IN

FILTO

ARRAY

INP

SUM1 MUX

ARRAY

Spkr.

AMP

AUX

OUT

AMP

VSSA VSSD VSSD VCCD

VCCD

Device Control

ANA

OUT

AMP

ΣΣ

( )

VLS0

VLS1

( )

VLS0

VLS1

( )

AIG0

AIG1

2( )

AXG0

AXG1

( )

S1S0

S1S1

( )

S1M0

S1M1 2

( )

S2M0

S2M1

( )

S2M0

S2M1

( )

OPA0

OPA1

( )

OPS0

OPS1

Internal

Clock Multilevel

Storage Array

( )

FLD0

FLD1

( )

FLD0

FLD1

(INS0)1

(AXPD)

(AGPD) 1

(FLPD)

(FLS0)

(AIPD)

(AOPD)

( )

AOS0

AOS1

AOS2

( )

VOL0

VOL1

VOL2

( )

VOL0

VOL1

VOL2

CAR KIT

CHIP SET

CAR KIT

CHIP SET

Low Pass

Filter

VSSA

Power Conditioning

MISOMOSISSSCLK RACINT

(VLPD)

ISD5008 PRODUCT SUMMARY

The ISD5008 ChipCorder product is a fully-inte-

grated, single-chip solution which provides seam-

less integration of enhanced voice record and

playback features for digital cellular phones (GSM,

CDMA, TDMA, PDC, and PHS), automotive com-

munications, GPS/navigation systems, and porta-

ble communication products. This low-power, 3-

volt product enables customers to quickly and

easily integrate 4 to 8 minutes of voice storage

features such as one-way and two-way (full du-

plex) call record, voice memo record, and call

screening/answering machine functionality.

Like other ChipCorder products, the ISD5008 inte-

grates the sampling clock, anti-aliasing and

smoothing filters, and the multi-level storage array

on a single-chip. For enhanced voice features,

the ISD5008 eliminates external circuitry by also in-

tegrating automatic gain control (AGC), a power

amplifier/speaker driver, volume control, sum-

ming amplifiers, analog switches, and a car kit in-

terface. Input level adjustable amplifiers are also

included, providing a flexible interface for multiple

applications.

ISD5008

Single-Chip Voice Record/Playback Device

4-, 5-, 6-, and 8-Minute Durations

Preliminary Datasheet

ISD5008 Product

ii Voice Solutions in Silicon™

Duration/sample rate selection is accomplished

via softwa re, allow ing customer s to op timize qual-

ity and duration for various features within the

same end pro du ct .

The ISD5 008 device is desig ned for use in a micro -

processor- or microcontroller-based system. Ad-

dress, control, and duration selection are

accomplished through a Serial Peripheral Inter-

face ( S PI) or Microwire Ser ial I nterfa ce to m inimize

pin count .

Recordings are stored in on-chip nonvolatile

memory cells, providing zero-power message

storage. This unique, single-chip solution is made

possible th roug h ISD’s patente d multil evel sto rage

technology. Voice and audio signals are stored

directly into solid-state memory in their natural, un-

compressed form, providing superior quality voice

and music reproduction.

ISD5008 FEATURES

FULLY-INTEGRATED SOLUTION

•Single-chip voice record/playb ac k solution

•Integrated sampling clock, anti-aliasing and

smoothing filters, and multi-level storage array

•Integrated analog features such as automatic

gain contr ol (AGC), audi o g ating swit ch e s ,

speake r dri ve r (23mW with 8 ohm load),

summing amplifiers, volume control, and an

AUX IN/AUX OUT interfa ce (e.g., fo r car kits).

LOW-POWER CONSUMPTION

•Single +3 volt supply

•Operat ing current:

ICC Play = 15 mA (typical)

ICC Rec = 25 mA (typical)

ICC Feedthru = 12 mA (ty pica l)

•Standby current:

ISB = 1 µA

•Power consumption controlled by SPI or

Microwire control register

•Most stages can be individually powered

down for minimum power consumption

ENHANCED VOICE FEATURES

•One or tw o-way (ful l dupl ex ) conver sa t io n

record (record signal summation)

•One- or two-way (full duplex) message

playbac k (whil e on a cal l)

•Voice me mo re c or d and pl ayb a c k

•Private call scr eening

•In-terminal answering machine

•Personali z ed outgoing message (giv en caller

ID information from host chip set)

•Private call announce whi l e on call (giv en

CIDCW information from host chip set )

EASY-TO-USE AND CONTROL

•No compression algorithm development

required

•User -c ontrollabl e sam ple ra tes of 8.0 kHz,

6.4 kHz, 5.3 kHz, or 4.0 kHz providin g up to

8 minutes of voice storage.

•Microcontroller SPI or Microwire™ Serial

Interface

•Fully ad d ressable to handle multiple

messages in 1200 rows

HIGH QUALITY SOLUTION

•High quality voice and music re pro du ct i on

•ISD’s standard 100-year message retention

(typical)

•100,000 record cycles (typical)

OPTIONS

•Available in die form, PDIP, SOIC, TSOP, and

chip scale packaging (CSP)

•Compact µBGA chip scale package

available fo r portable appl i cat io n s

•Extended temperature (-20 to +70°C) and

industri al tempe ratur e (-40 to +85°C ) vers ions

available

Table of Contents

1 DETAILED DESCRIPTION ................................................. .................... 1

1.1 Speech/Sound Quality ...................................... .................... 1

1.2 Duration ............................................................ .................... 1

1.3 Flash Storage .................................................... .................... 1

1.4 Microcontroller Interface ....................................................... 1

1.5 Programming .................................................... .................... 1

2 PIN DESCRIPTIONS ........................................................ .................... 2

2.1 Digital I/O Pins ................................................... .................... 2

2.2 Analog I/O Pins .................................................. .................... 3

2.3 Power and Ground Pins .................................... .................... 6

3 INTERNAL FUNCTIONAL BLOCKS .................................... .................... 7

4 SERIAL PERIPHERAL INTERFACE (SPI) DESCRIPTION .......... .................... 13

4.1 Message Cueing .............................................. .................... 13

4.2 Power-Up Sequence ......................................... .................... 14

4.3 SPI Port .............................................................. .................... 15

4.4 SPI Control Register ........................................... .................... 15

5 OPERATIONAL MODES DESCRIPTION ............................. .................... 21

5.1 Feed Through Mode ......................................... .................... 21

5.2 Call Record ...................................................... .................... 23

5.3 Memo Record .................................................. .................... 24

5.4 Memo and Call Record Playback .................... .................... 24

6 TIMING DIAGRAMS ....................................................... .................... 34

7 DEVICE PHYSICAL DIMENSIONS ..................................... .................... 36

8 ORDERING INFORMATION ........................................... .................... 42

ISD5008 Product

ISD

1 DETAILED DESCRIPTION

1.1 SPEECH/SOUND QUALITY

The ISD5008 C hipCorder pro duct can be config-

ured via so ftware to operate at 4.0, 5.3, 6.4, and

8.0 kHz sampling frequencies, allowing the user a

choice of speech quality options. Increasing the

duration decreases the sa mpling frequenc y and

bandwidth, which affects sound quality. Table 1

compares filter pass band and product durations.

The speech samp les are stored directly into on-chip

nonvolatile memory without the digitization and

compression associated with other solutions. Di-

rect analog storage provides a natural sounding

reproduction of voice, music, tones, and sound

effects not available with most solid-state solu-

tions.

1.2 DURATION

To meet end system requirements, the ISD5008

device is a single-chip solution which provides

from 4 to 8 minutes of voice record and playback,

depending on the sample rates defined by cus-

tomer software.

1.3 FLASH STORAGE

One of the benefits of ISD’s ChipCorder technology

is the use of on-chip nonvolatile memory, which pro-

v ides zero-p ower message storage. The mes sage

is retained for up to 100 years (typically) without

power. In add ition, the devic e can be re-record -

ed over 100,0 00 ti mes (t ypi cally).

1.4 MICROCONTROLLER INTERFACE

A four-wire (SCLK, MOSI, MISO, SS) SPI interface is

provided for ISD5008 control, addressing func-

tions, and sample rate selection. The ISD5008 is

configured to operate as a peripheral slave de-

vice with a microcontroller-based SPI bus inter-

face. Read/Write access to all the internal registers

occurs through this SPI interface. An interrupt sig-

nal (INT) and inter nal read-onl y Status Regis ter are

provided for handshake purposes.

1.5 PROGRAMMING

The ISD5008 series is also ideal for playback-only

applications, where single or multiple message

Playback is controlled through the SPI port. Once

the desired message configuration is created, du -

plicates can easily be generated via an ISD or

third-p arty p rogramme rs. For mo re in format ion on

available application tools and programmers

please see the ISD web site at www.isd.com.

Table 1: Input Sample Rate to Durati o n

Input Sample

Rate (kHz)

Duration

(Minutes)

Typical Filter Pass Band

(kHz)

8.0 4.0 3.4

6.4 5.0 2.7

5.3 6.0 2.3

4.0 8.0 1.7

ISD5008 Product

2Voice Solutions in Silicon™

2PIN DESCRIPTIONS

2.1 DIGITAL I/O PINS

SCLK (S e r ial Clock )

The SCLK is the clock input to the ISD5008. Gener-

ated by t he m ast er micro controller , th e SCLK sy n -

chronizes data tra nsfers in and out of the device

through the MISO and MOSI lines. Data is latched

into the ISD5008 on the rising edge of SCLK and

shift ed ou t on th e fallin g edg e.

SS (Slave Select)

This input, when LOW, will select the ISD5008 de-

vice.

MOSI (Master Out Slave In)

MOSI is the serial data input to the ISD5008 de-

vice. The master microcontroller places data to

be clocked int o the ISD5008 device on the MOSI

line one-half cycle before the rising edge of SCLK.

Data is cl ocked into the device LSB (Le ast Signifi-

can t Bit) firs t.

MISO (Master In Slave Out)

MISO is the serial data output of the ISD5008 de-

vice. Data is clocked out on the falling edge of

SCLK. This output goes into a high-impedance

state when the device is not selected. Data is

clocked out of the device LSB first.

INT (Interrupt)

INT is an ope n drain outpu t pin. Th e IS D5008 inter-

rupt pin goes LOW and stays LOW when an Over-

flow (OVF) or End of Message (EOM) marker is

detected. Each operation that ends in an EOM or

OVF generates an interrupt, including the mes-

sage cueing cycles. The interrupt is cleared the

next time an SPI cycle is completed. The interrupt

status can be read by a RINT instruction that will

give one of the two flags out the MISO line.

OVF Flag

. The overflow flag indicates that the end

of the ISD5008’s analog memory has been

reached during a record or playback operation.

EOM Flag.

The end of message flag is set only

during playback, when an EOM is found. There are

eight possible EOM markers per row.

RAC (Row Address Clock)

RAC is an open drain output pin that marks the

end of a row. At th e 8 kHz sample f requency , t he

duratio n of this per iod is 200 ms. There a re 1,200

rows of memory in the ISD5008 devices. RAC stays

HIGH for 175 ms and stays LO W f or the re m ai nin g

25 ms before it reaches the end of the row.

The RAC pin remains HIGH for 109.38 µsec and

stays LOW for 15.63 µsec under the Message Cue-

ing mode. See Table 15 Timing Parameters for

RAC timing information at other sample rates.

When a record c ommand is f irst init iated, the RAC

pin remains HIGH for an extra TRACLO period, to

load sample and hold circuits internal to the de -

vice. The RAC pin can be used for message man-

agement techniques.

XCLK (External Clock Input)

The external clock input for the ISD5008 product

has an internal pull-down device. Normally, the

ISD5008 is operated at one of four internal rates

selected for its internal oscillator by the Sample

Rate Select bits. If greater precision is required, the

device can be clocked through the XCLK pin as

described in Tab le 2.

Because the antialiasing and smoothing filters

track the Sample Rate Select bits, one must, for

optimum performance, change the external

clock AND the Sample Rate Configuration bits to

one of the four value s to properly set the filte rs to

the correct cutoff frequency as described in Table

3. The d u ty cycl e on the input clock is not criti cal ,

as the clock is immediately divided by two inter-

nally. If the XCLK is not used, this input should b e

connected to VSSD.

ISD5008 Product

ISD

Table 3: Inte rnal Clock Rat e/Filter Ed ge

2.2 ANALOG I/O PINS

MIC+, MIC – (Microphone Input+/–)

The microphone input transfers the voice signal to

the on-chip AGC preamplifier or directly to the

ANA OUT MUX, dep ending on the sele cted path .

The direct path to the ANA OUT MUX has a gain of

6 dB so a 208 mVp-p signal across the differential

microphone inputs would give 416 mVp-p across

the ANA OUT pins. The AGC circuit has a range of

45 dB in order to deliver a nominal 694 mVp-p into

the storage array from a typical electret micro-

pho ne o utp ut of 2 to 20 mVp- p. Th e in put imp e d-

anc e is typica lly 10 kΩ.

Figure 1: Microphone Input

Table 2: External Clock Input Table

Duration

(Minutes)

Sample Rate

(kHz)

Required Clock

(kHz)

4 8.0 1024

5 6.4 819.2

6 5.3 682.7

84.0 512

FLD1 FLD0

Sample Rate

(kHz)

Filter Pass Band

(kHz)

00 8 3.4

01 6.4 2.7

10 5.3 2.3

11 4 1.7

Ra = 10 k

10 k

CCOUP = 0.1 F

0.1 F

Internal to the device

Electret

Microphone

WM-54B

Panasonic

1.5 k

220 F

VCC

MIC+

MIC

NOTE: fCUTOFF=

2RaCCOUP

ISD5008 Product

4Voice Solutions in Silicon™

ANA IN (Analog Input)

The ANA IN pin is the analog input from the tele-

phone chip set. It can be switched (by the SPI bus)

to the speaker output, the array input or to various

oth er pat hs. Thi s pin is desig ned t o accep t a nom -

inal 1.11 Vp-p when at its minimum gain (6 dB)

setting. There is additional gain available in 3 dB

steps controlled from the SPI bus, if required, up to

15 dB.

Figure 2: ANA IN Input Modes

1. Gain from ANA IN to SP+/–

2. Gain from ANA IN to ARRAY IN

3. 0TLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3 dB below clipping.

4. Speaker Out gain set to 1.6 (High). (Differential)

Gain

Setting

Resistor Ratio

(Rb/Ra) Gain Gain2

(dB)

00 63.9/102 0.625 –4.1

01 77.9/88.1 0.88 –1.1

10 92.3/73.8 1.25 1.9

11 106/60 1.77 4.9

Table 4: A NA IN Amp lif ier Ga in Se tt ings

Setting(1) 0TLP Input

VPP(3)

CFG0

Gain(2) Array In/Out

VPP

Speaker Out

VPP(4)

AIG1 AIG0

6 dB 1.11 0 0 .625 .694 2.22

9 dB .785 0 1 .883 .694 2.22

12 dB .555 1 0 1.250 .694 2.22

15 dB .393 1 1 1.767 .694 2.22

ISD5008 Product

ISD

AUX IN (Auxiliary Input)

The AUX IN is an additional audio input to the

ISD5008, such as from the microphone circuit in a

mobile phone “car kit.” This input has a nominal

700 mVp-p level at its minimum gain setting

(0 d B). See T able 5 . Addi tion al gai n i s avai labl e in

3 dB steps (con tr olled by the SPI bus) up to 9 dB.

Figur e 3: AUX IN Inp u t Modes

1. Gain from AUX IN to ANA OUT

2. Gain from AUX IN to ARRAY IN

3. 0TLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3 dB below clipping.

4. Differential

Gain

Setting

Resistor Ratio

(Rb/Ra) Gain Gain

(dB)

00 40.1/40.1 1.0 0

01 47.0/33.2 1.414 3

10 53.5/26.7 2.0 6

11 59.2/21 2.82 9

Table 5: AUXIN Amplifier Gain Settings

Setting(1) 0TLP Input

VPP(3)

CFG0

Gain(2) Array In/Out

VPP

Ana Out VPP(4)

AXG1 AXG0

0 dB .694 0 0 1.00 .694 .694

3 dB .491 0 1 1.41 .694 .694

6 dB .347 1 0 2.00 .694 .694

9 dB .245 1 1 2.82 .694 .694

ISD5008 Product

6Voice Solutions in Silicon™

ANAOUT+/– (Analog Outputs)

This differential output is designed to go to the mi-

crophone input of the telephone chip set. It is de-

signed to drive a minimum of 5 kΩ between the

“+” and “–” pins to a nominal voltage level of

700 mVp-p. Both pins have DC bias of approxi-

mately 1.2 VDC. The AC signal is superimposed

upon this analog ground voltage. These pins can

be used single-ended, getting only half the volt-

age. Do NOT ground the unused pin.

AUX OUT (Auxiliary Output)

The AUXOUT is an additional audio output pin, to

be used, for e xam ple, to d rive th e spea ker ci rcuit

in a “car kit.” It drives a minimum load of 5 kΩ and

up to a maximum of 1 Vp-p. The AC signal is su-

perimpose d on approxim ately 1.2 VDC bi as and

must be capacitive l y cou pled to the load.

SP+, SP– (Speaker+/–)

This is the speaker differential output circuit. It is de-

sig n ed to dr iv e an 8 Ω speak er connect ed acr oss

the speaker pins up to a maximum of 23.5 mW

power. This stage has two selectable gains, 1.32

and 1.6, which can be chosen through the con-

figuration registers. These pins are biased to ap-

proximately 1.2 VDC and, if used single-ended,

must be capacitively coupled to their load. Do

NOT ground the unused pin.

ACAP (AGC Capacitor)

This pin provides the capacitor connection for

setting the parameters of the microphone AGC

circuit. It should have a 4.7 µF capacitor con-

nected to ground. It cannot be left floating. This is

because the capacitor is also used in the

playback mode for the AutoMute circuit. This

circuit reduces the amount of noise present in the

output during quiet pauses. Tying this pin to

ground gives maximum gain; to VCCA gives

minimum gain for the AGC amplifier but will

cancel the AutoMute function.

2.3 POWER AND GROUND PINS

VCCA, VCCD (Voltage Inputs)

To minimi ze noise, the ana log and digita l circuits

in the ISD5008 device uses separate power bus-

ses. These + 3 V busses lea d to sepa rate pins. Tie

the VCCD pins together as close as possible and

decouple both supplies as near to the package

as possib le.

VSSA, VSSD (Ground Inputs)

The ISD5008 series utilizes separate analog and

digital ground busses. The analog ground (VSSA)

pins should be tied together as close to the pack-

age as possible and connected through a low-

impedance path to power supply ground. The

digital ground (VSSD) pin should be connected

through a separate low-impedance path to pow-

er supply ground. These ground paths should be

large enough to en sure that the impedan ce be-

tween the VSSA pins and the VSSD pin is less than

3Ω. The backside o f th e die is connec ted to VSSD

through the substrate resistance. In a chip-on-

board de sign, the die a ttach area m ust be con-

nected to VSSD.

ISD5008 Product

ISD

Figure 4: ISD5008 Series TSOP and PDIP/SOIC Pinouts

3 INTERNAL FUNCTIONAL BLOCKS

Figure 5: Microphone Amplifier

28-PIN TSOP

ISD5008

PDIP/SOIC

ISD5008

Microphone

(300 mVp-p Max) MIC+

MIC–

ACAP

FTHRU

AGC

1 (AG PD )

6 dB

To AutoMute

(Playback Only)

* Differential Path

AGPD

0 Power Up

1 Power Down

1514131211109876543210

VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD CFG1

AGC

ISD5008 Product

8Voice Solutions in Silicon™

Figure 6: AUX IN and ANA IN

Car Kit AUX IN AUX IN AMP

AUX IN

1514131211109876543210

AIG1 AIG0 AIPD AXG1 AXG0 AXPD INS0 AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD CFG0

AMP

1.0 / 1.414 / 2.0 / 2.828

1 (AXPD) AXPD

0 Power Up

1 Power Down

2 (AXG1, AXG0)

AXG1 A X G0 Inpu t G ai n 0TLP Input Lev el

0 0 1 .694

0 1 1.414 .491

1 0 2 .347

1 1 2.828 .245

Chip Set ANA IN ANA IN AMP

ANA IN

AMP

.625 /.883 / 1.25 / 1.767

1 (AIPD) AIPD

0 Power Up

1 Power Down

2 (AIG1,AIG0)

AIG1 AIG0 Input Gain 0 T LP Input Level

000.6251.11

010.883.785

101.250.555

111.767.393

ISD5008 Product

ISD

Figure 7: ISD5008 Core (Left Half)

INPUT

AGC AMP SUM1

2 (S1M1,S1M0)

S1M1 S1M0 SOURCE

00BOTH

0 1 SUM1 MUX ONLY

10INP ONLY

11Power Down

SOURCE

MUX

SUM1 SUMMING

AMP

1514131211109876543210

AIG1 AIG0 AIPD AXG1 AXG0 AXPD INS0 AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD CFG0

AUX IN AMP

FILTO

SUM1

MUX

ANA IN AMP

ARRAY

2 (S1S1,S1S0)

S1S1 S1S0 SOURCE

0 0 ANA IN AMP

01ARRAY

10FILTO

11N/C

1514131211109876543210

VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD CFG1

INSO Source

0AGC AMP

1AUX IN AMP

(INS0)

ISD5008 Product

10 Voice Solutions in Silicon™

Figure 8: ISD5008 Core (Right Half)

SUM1

SUM2

2 (S2M1,S2M0) S2M1 S2M0 SOURCE

00BOTH

01ANA IN ONLY

1 0 FILTO ONLY

11Power Down

FILTER

MUX SUM2 SUMMING

AMP

ARRAY

FLD1 FLD0 SAMPLE RATE FI LTER PASS BAND

008kHz 3.4 kHz

0 1 6.4 kHz 2.7 kHz

1 0 5.3 kHz 2.3 kHz

114 kHz 1.7 kHz

1514131211109876543210

VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD CFG1

FILTO

LOW PASS

FILTER

INTERNAL

CLOCK

MULTILEVEL

STORAGE

ARRAY

FLS0 Source

0SUM1

1 ARRAY 1

(FLS0) 1

(FLPD)

FLPD

0 Power Up

1 Power Down

ARRAY

ANA IN AMP

XCLK

(FLD1,FLD0)

ISD5008 Product

ISD

Figure 9: Volume Control

INS0

VOL

1514131211109876543210

AIG1 AIG0 AIPD AXG1 AXG0 AXPD AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD CFG0

SUM2

VOL

MUX

SUM1

INP

VLS1 VLS0 SOURCE

00ANA IN AMP

01SUM2

10SUM1

11INP

1514131211109876543210

VLS1 VLS0 VOL2 VOL1 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD CFG1

ANA IN AMP

VOLUME

CONTROL

(VLS1,VLS0) 3

VOL2 VOL1 VOL0 Attenuation

0000 dB

0014 dB

0108 dB

0 1 1 12 dB

1 0 0 16 dB

1 0 1 20 dB

1 1 0 24 dB

1 1 1 28 dB

(VOL2,VOL1,VOL0) 1 (VLP D) VLPD

0 Power Up

1 Power Down

VOL0

ISD5008 Product

12 Voice Solutions in Silicon™

Figur e 10: Speake r an d AUX OUT

Figure 11: ANA OUT Output

Speaker

SP+

SP–

AUX OUT Car Kit

(1 Vp-p Max)

ANA IN AMP

OUTPUT

MUX

FILTO

SUM2

OPS1 OPS0 SOURCE

00VOL

01ANA IN

10FILTO

11SUM2

VOL

(OPS1,OPS0)

OPA1 OPA0 SPKR Drive AUX OP

0 0 Power Down Pow er Down

0 1 3.6 Vp-p @ 150 ΩPower Down

1 0 23 mWatt @ 8 ΩPower Down

11Power Down1 Vp-p Max @ 5kΩ

(OPA1, OPA0)

INS0

1514131211109876543210

AIG1 AIG0 AIPD AXG1 AXG0 AXPD AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD CFG0

Chip Set

ANA OUT+

ANA OUT–

*VOL

ANA OUT

MUX

*FILTO

*SUM2

3 (AO S2, A OS 1 , AO S0)

AOS2 AOS1 AOS0

000FTHRU

001INP

010VOL

011FILTO

100SUM1

101SUM2

110N/C

111N/C

*FTHRU

AOPD

0 Power Up

1 Power Down

(AOPD)

INS0

1514131211109876543210

AIG1 AIG0 AIPD AXG1 AXG0 AXPD AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD CFG0

*INP

*SUM1

(1 Vp-p max. from AUX IN or ARRAY)

(600 mVp-p max. from microphone in put )

*DIFFERENTIAL PATH

ISD5008 Product

ISD

4 SERIAL PERIPHERAL INTERFACE (SPI) DESCRIPTION

The ISD5008 product operates from an SPI serial in-

terface. The SPI interface operates with the following

protocol.

The data transfer protocol assumes that the mi-

crocontroller’s SPI shift registers are clocked on the

falling edge of the SCLK. With the ISD5008, data is

clocked in on the MOSI pin on the rising clock

edge. Data is clocked out on the MISO pin on the

falli n g cl ock edge.

1. All serial data transfers begin with the falling

edge of SS pin.

2. SS is held LOW during all serial communica-

tions and held HIGH between instructions.

3. Data is clocked in on the ri sing clock edg e

and data is clocked out on the falling clock

edge.

4. Play and Record operations are initiated by

enabling the device by asserting the SS pin

LOW, shifting in an opcode and an address

field to the ISD5008 device (refer to the Op-

code Summary on the pa ge 14).

5. The opcodes and address fields are as fol-

lows: <8 control bits> and <16 address

bits>.

6. Each operation that ends in an EOM or

Overflow will generate an interrupt, includ-

ing the Message Cueing cycles. The Inter-

rupt will be cleared the next time an SPI

cycle is completed.

7. As Interrupt data is shifted out of the

ISD5008 MISO pin, control and address

data is simultaneously being shifted into

the MOSI pin. Care should be taken such

that the data shifted in is compatible with

current system operation. It is possible to

read interrupt data and start a new opera-

tion with in th e sam e S P I cycl e.

8. A recor d or play back op eratio n begi ns with

the RUN bit set and the operation ends with

the RUN bit reset.

9. All operations begin with the rising edge

of SS.

4.1 MESSAGE CUEING

Message cueing allows the user to skip through

messages, without knowing the actual physical lo-

cation of the message. This operation is used dur-

ing playback. In this mode, the messages are

skipped 1600 times faster than in normal play-

back mode. It will stop when an EOM marker is

reached. Then, the internal address counter will

poin t t o th e next m es s age.

ISD5008 Product

14 Voice Solutions in Silicon™

1. X = Don’t Care.

2. Changes in CFG0 are not recognized until CFG1 is loaded. The changes will occur at the ris ing edge of SS during

the cycle that CFG1 is loaded.

4.2 POWER-UP SEQUENCE

The ISD5008 will be ready for an operation after

TPUD (25 ms approximately for 8 kHz sample rate).

The user needs to wait TPUD before issuing an opera-

tional command. For example, to play from ad-

dress 00 the following programing cycle should

be used.

Playback Mode

1. Send POWERUP command.

2. Wait TPUD (power-up delay).

3. Load CFG0 and CFG1 for desired opera-

tion.

4. Send SETPLAY command with address 00.

The device will start playback at address 00 and it

will generate an interrupt when an EOM is

reached. It will then stop pl ayback .

Record M ode

1. Send POWERUP command.

2. Wait TPUD (power -up delay).

3. Load CFG0 and CFG1 for desired opera-

tion.

4. Send SETREC com man d with address 00.

The device will start recording at address 00 and it

will generate an interrupt when an overflow is

reached (end of memory array) or when it has re-

ceived a STOP command. It will then stop record-

ing.

Table 6: Opcode Summary

Instruction Opcode <8 bits>(1)

Address <16 bits> Operational Summary

POWERUP 0110 0000 Power-Up: See “Power-Up S equence”

LOADCFG0(2) 01X0 0010 <D15–D0> Loads a 16-bit value into Confi guration Register 0

LOADC FG1 01X0 0100 <D15–D0> Loads a 16-bit value into Configuration Register 1

SETPLAY 1110 0000 <A15–A0> Initiates Playback fro m address <A15–A0>

PLAY 1111 0000 Playback from current address (until EOM or OVF)

SETREC 1010 0000 <A15–A0> Initiates Record at address <A15–A0>

REC 1011 0000 Records from current address until OVF is reached

MC 1111 1000 Performs a Message Cue. Proceeds to the end of the current

message (EOM) or enters OVF condition if it reaches the end of

the array.

STOP 0111 0000 Stops current operation

STOPWRDN 0101 0000 Stops current operation and enters stand-by (power-down) mode.

RINT 0111 0000 Read interrupt status bits: OVF and EOM.

ISD5008 Product

ISD

4.3 SPI PORT

The following diagram describes the SPI port and the control bits associated with it.

Figure 12: SPI Port

NOTE: Bytes 1 and 2 of the MOSI input may be address bits or configuration bits, depending on the selected mode

in byte 3.

4.4 SPI CONTROL REGISTER

The SPI control register provides control of individual device functions such as Play, Record, Message

Cueing, Power-Up and Power-Down, Start and Stop operations, Ignore Address Pointers and Load Con-

figuration Registers.

Table 7: SPI Control Register

Control

RUN Enable or Disable an operation PU Master power control

0Start

Stop =

0Power-Up

Power-Down

P/R Selects Play or Record operatio n IAB Ignore addres s control bit

0Play

Record =

0Ignore input addres s r eg ister (A1 5–A0 )

Use the input address register contents

for an operation (A15–A0)

MC Enable or Disable Message Cueing A15–A0 Output of the row pointer register

0Enable Message Cueing

Disable Message Cueing D15–D0 Input control and address register

LC0 LC1

0Load Configuration Reg 0

No Loa d =

0Load Configuration Reg 1

No Loa d

ISD5008 Product

Voice Solutions in Silicon™

NOTE: See details on following pages.

Table 8: Configuration Register 0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CFG0

AIG1 AIG0 AIPD AXG1 AXG0 AXPD INS0 AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD

ANA IN AMP Gain SET (2 bits)

ANA IN Power Down

AUX IN AMP Gain SET (2 bits)

AUX IN Power Down

INPUT SOURCE MUX Select (1 bit)

ANA OUT MUX Select (3 bits)

ANA OUT Power Down

OUPUT MUX Select (2 bits)

SPKR & AUX OUT Control (2 bits)

Volume Control Power Down

NOTE: See details on following pages.

Table 9: Configuration Register 1

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CFG1

VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLSO FLD1 FLD0 FLPD AGPD

VOLUME CONT. MUX Select (2 bits)

VOLUME CONTROL (3 bits)

SUM 1 MUX Select (2 bits)

SUM 1 SUMMING AMP Control (2 bits)

SUM2 SUMMING AMP Control (2 bits)

FILTER MUX Select

SAMPLE RATE (& Filter) Set Up (2 bits)

Filter Power Down

AGC AMP Power Down

ISD5008 Product

ISD

Detail of Configuration Register 0

Volume Control

Power Bit Bit 0

(VLPD) 0 = Power ON

1 = Power OFF

SPEAKER and AUX

OUT Control Bits Bits 2,1

(OPA1, OPA0) 00 = Power down SPKR and AUX

01 = SPKR ON, HIGH GAIN, AUX Power down

10 = SPKR ON, LOW GAIN, AUX Power down

11 = SPKR Powered down, AUX ON

OUTPUT MUX Control

Bits Bits 4,3

(OPS1, OPS0) 00 = Source is VOL CONTROL (VOL)

01 = Source is ANA IN Input (ANA IN AMP)

10 = Source is LOW PASS FILTER (FILT0)

11 = Source is SUM2 SUMMING AMP (SUM2)

ANA OUT Power Bit Bit 5

(AOPD) 0 = Power ON

1 = Power OFF

ANA OUT MUX Con-

trol Bits Bits 8,7,6

(AOS2, AOS1, AOS0) 000 = Source is MICROPHONE AMP (FTHRU)

001 = Source is INPUT MUX (INP)

010 = Source is VOLUME CONTROL (VOL)

011 = Source is LOW PASS FILTER (FILT0)

100 = Source is SUM1 SUMMING AMP (SUM1)

101 = Source is SUM2 SUMMING AMP (SUM2)

110 = Unused

111 = Unused

INPUT SOURCE MUX

Control Bit Bit 9

(INS0) 0 = Source is Microphone AGC AMP (AGC)

1 = Source is AUX IN Input (AUX IN AMP)

AUX IN AMP Power Bit Bit 10

(AXPD) 0 = Power ON

1 = Power OFF

AUX IN AMP Control

Bits Bits 12,11

(AXG1, AXG0) 00 = Input Gain = 1, OTLP input Level = 0.694

01 = Input Gain = 1.414, OTLP input Level = 0.491

10 = Input Gain = 2, OTLP input Level = 0.347

11 = Input Gain = 2.828, OTLP input Level = 0.245

ANA IN AMP Power Bit Bit 13

(AIPD) 0 = Power ON

1 = Power OFF

ANA IN AMP Control

Bits Bits 15,14

(AIG1, AIG0) 00 = Input Gain = 0.625, OTLP input Level = 1.11

01 = Input Gain = 0.883, OTLP input Level = 0.7l85

10 = Input Gain = 1.250, OTLP input Level = 0.555

11 = Input Gain = 1.767, OTLP input Level = 0.393

ISD5008 Product

Voice Solutions in Silicon™

Configuration Register Notes

Important:

All changes to the internal settings of the ISD5008 are synchronized with the load of Configuration

settings of the device and the changes take place immediately at the end of the command when SS\ goes

HIGH. A load to Configuration Register 0 sends the new data to a temporary register in the ISD5008 and does

not affect th e in ter nal sett ing s of th e de vice. Th e n ex t ti me C onf igu rat ion Regis ter 1 is lo aded, d ata will a lso

tra nsfer from th e tempor ary r egiste r to the Confi gurati on 0 Re giste r and ef fect t he desi red cha nges. Se e Figur e

Table 13.

2. Configuration Registers may be loaded with data at any time, including when the chip is powered down using

the PU bit in the SPI Control Register. The PU bit in the SPI Control Word will have to be set to a “1” before the

changes in configuration will be seen.

Detail of Configuration Register 1

AGC Power Control

Bit Bit 0

(AGPD) 0 = Power ON

1 = Power OFF

LOW PASS FILTER

Power Control Bit Bit 1

(FLPD) 0 = Power ON

1 = Power OFF

SAMPLE RATE and

LOW PASS FILTER

Control Bits

Bits 3,2

(FLD1, FLD0) 00 = S ample Rate = 8 KHz, FPB = 3.4 KHz

01 = Sample Rate = 6.4 KHz, FP B = 2.7 KHz

10 = Sample Rate = 5.3 KHz, FP B = 2.3 KHz

11 = S ample Rate = 4 KHz, FPB = 1.7 KHz

FILTER MUX Control

bits Bit 4

(FLS0) 0 = Source is SUM1 SUMMING AMP (SUM1)

1 = Source is Analog Memory Array (ARRAY)

SUM 2 SUMMING AMP

Control Bits Bits 6,5

(S2M1, S2M0) 00 = Source is both ANA IN AMP and FILT0

01 = Source is ANA IN Input (ANA IN AMP) ONLY

10 = Source is LOW PASS FILTER (FILT0 ) ONLY

11 = Power Down SUM2 SUMMING AMP

SUM1 SUMMING AMP

Control Bits Bit 8,7

(S1M1, S1M0) 00 = Source is both SUM1 and INP

01 = Source is SUM1 SUMMING AMP (SUM1) ONLY

10 = Source is INPUT MUX (INP) ONLY

11 = Power Down SUM1 SUMMING AMP

SUM1MUX Control Bits Bit 10,9

(S1S 1, S1S0) 00 = Source is ANA IN Input (ANA IN AMP)

01 = Source is Analog Memory Array (ARRAY)

10 = Source is LOW PASS FILTER (FILT0)

11 = UNUSED

VOLUME CONTROL

Control Bits Bits 13,12,11

(VOL2, VOL1, VOL0) 000 = Attenuation = 0 dB

001 = Attenuation = 4 dB

010 = Attenuation = 8 dB

011 = Attenuation = 12 dB

100 = Attenuation = 16 dB

101 = Attenuation = 20 dB

110 = Attenuation = 24 dB

111 = Attenuation = 28 dB

VOL MUX Control Bits Bit 15,14 (VLS1, VLS0) 00 = Source is ANA IN Input (ANA IN AMP)

01 = Source is SUM2 SUMMING AMP (SUM2)

10 = Source is SUM1 SUMMING AMP (SUM1)

11 = Source is INPUT MUX (INP)

ISD5008 Product

ISD

Figure 13: Configuration Register Programming Sequence

Figure 14: SPI Interface Simplified Block Diagram

1. See Table 8 for bit details.

{Command =

Load Configuration Register 1

}

Command =

Load Configuration Register 0

Temporary Register

Configuration Register 1

Configuration Register 0

Input Shift Register (16 bits) MOSI

Control Word (C7-C0)

{Command =

Load Configuration Register 1

}

Command =

Load Configuration Register 0

Temporary Register

Configuration Register 1

Configuration Register 0

Input Shift Register (16 bits) MOSI

Control Word (C7-C0)

Configuration Registers (1)

D15

CFG1

CFG0

D15 - D0

ISD5008 Product

20 Voice Solutions in Silicon™

Figure 15 : Typic al D igital Cell ular Pho n e Integrati on

Section

Flash

DSP

Interface

Microcontroller

Keypad

Display

EEPROM

Voice Band

Codec

Microphone

Earpiece

ANA OUT+

ANA OUT-

ANA IN

ISD5008

SP+

SP–

MIC+

MIC-

SPI

MIC IN+

MIC IN–

SP OUT+

SP OUT –

AUX IN

AUX OUT

Car Kit

SPI

ISD5008 Product

ISD

5 OPERATIONAL MODES DESCRIPTION

The ISD5008 can operate in many different

modes. It’s flexibility allows the user to configure

the chip such that almost any input can mixed

with any other input and then be dir ected to any

output. Th e variab le sett ings f or the ANA and AUX

input amplifiers plus the microphone AGC and

speaker volume controls make it possible to use

the dev ice with most ex isting ce ll phone or co rd-

less phone chip sets with no ext ernal level ad just-

ment. Several modes will be found in most

applications, however. Please refer to the ISD5008

block dia gram to bet ter un ders tand the fol lowing

modes. In all cases, we are assuming that the

chip has been po wered up with the PU bit i n the

SPI contr ol register and that a time period of TPUD

has elapsed after that bit was set:

5.1 FEED THROUGH MODE

This mode enables the ISD5008 to connect to a

base band cell phone or cordless phone chip set

without affec tin g the au dio sour ce or d estina ti on.

There are two paths involved, the transmit path

and the receive path. The transmit path connects

the ISD chip’s microphone source through to the

micr opho ne input on th e base ban d chip set . The

receive path connects the base band chip set’s

speaker output through to the speaker driver on

the ISD chip . This allows the ISD chip to substitute

for those functions and incidentally gain access to

the audio to and from the base band chip set.

Figure 15 sho w s o n e possible co n n ect ion t o su ch

a chip set.

Figure 16 shows the part of the ISD5008 block dia-

gram that is used in Feed Through Mode. The rest

of the chip will be powered down to conserve

power. The bold lines highlight the audio paths.

Note that the Microphone to ANA OUT +/– path is

differential.

Figure 16: Basic Feed-Thru Mode

Chip Set

ANA OUT+

ANA OUT–

VOL

ANA OUT

MUX

FILTO

SUM2

3 (AOS2,AOS1,AOS0)

FTHRU

(AOPD)

INP

SUM1

Speaker

SP+

SP–

ANA IN AMP

OUTPUT

MUX

FILTO

SUM2

VOL

(OPS1,OPS0)

(OPA1, OPA0)

Chip Set

ANA IN ANA IN

AMP

.625 /.883 / 1.25 / 1.767

1 (AIPD)

2 (AIG1,AIG0)

Microphone

MIC+

MIC–

6 dB

ISD5008 Product

22 Voice Solutions in Silicon™

To se lect t his m ode, the followin g cont rol bi ts must

be configured i n the ISD5008 c onfiguration regis-

ters. To set up the transmit path:

Select the FTHRU path through the ANA OUT

MUX—

Bits AOS0, AOS1 and AOS2 control

the state of the ANAOUT MUX. These are the

D6, D7 and D8 bits respectively of Configu-

ration Register 0 (CFG0) and they should all

be ZERO to select the FTHRU path.

Power up the ANA OUT am pli fier

—Bit AOPD

controls the power up state of ANA OUT. This

is bit D5 of CFG0 and it should be a ZERO

to power up the amplifier.

To set up the receive pa th :

Set up the ANA IN amplifier for the correct

gain

—Bits AIG0 and AIG1 control the gain

settings of this amplifier. These are bits D14

and D15 respectively of CFG0. The input

level at this pin determines the setting of

this gain stage. Table 4 will help determine

this setting. In this example we will assume

that the peak signal never goes above 1

volt p-p single ended. That would enable

us to use the 9dB attenuation setting, or

where D14 is ONE and D15 is ZERO .

Power up the ANA IN amplifier

—Bit AIPD

controls the power up state of AN A IN. This

is bit D13 of CFG0 and should be a ZERO to

power up the ampl i fi er .

Select the ANA IN path through the OUTPUT

MUX

—Bits OPS0 and OPS1 control the state

of the OUTPUT MUX. These are bits D3 and

D4 respectively of CFG0 and they should

be set to the state where D3 is ONE and D4

is ZERO to select the ANA IN path.

Power up the S peake r Ampli fier

—Bits OPA0

and OPA1 co ntrol the st ate of the S peaker

and AUX amplifiers. Thes e are bits D1 and

D2 respectively of CFG0. They should be

set to the stat e where D1 is ONE and D2 is

ZERO. This powers up the Speaker Amplifier

and configures it for it’s higher gain setting

for use with a piezo speaker element and

also powers do wn the AUX outpu t stage.

The status of the rest of the functions in the ISD5008

chip must be defined before the configuration

registers settings ar e updated:

1. Power down the Volume Control Ele-

ment—Bit VLPD cont rols the power up state

of the Volume Con trol. This is b it D0 of CFG0

and it should be set to a ONE to power

down this stage.

2. Power down the AUX IN amplifier—Bit

AXPD controls the power up state of the

AUX IN input amplifier. This is bit D10 of

CFG0 and it should be set to a ONE to pow-

er down this stage.

3. Power down the SUM1 and SUM2 Mixer

amplifiers—Bits S1M0 and S1M1 control

the SUM1 mixer and bits S2M0 and S2M1

control the SUM2 mixer. These are bits D7

and D8 in CFG1 and bits D5 and D6 in

CFG1 respectively. All 4 bits should be set

to a ONE to power down these two amplifi-

ers.

4. Power down the FILTER stage—Bit FLPD

controls the power up state of the FILTER

stage in the device. This is bit D1 in CFG1

and should be set to a ONE to power down

the stage.

5. Power down the AGC amplifier—Bit

AGPD controls the power up state of the

AGC amplifier. This is bit D0 in CFG1 and

should be set to a ONE to power down this

stage.

6. Don’t Care bits—The following stages are

not used in Feed Through Mode. Their bits

may be set to either level. In this example

we will set all the following bits to a ZERO.

(a). Bi t IN S0, bi t D9 of CF G0 co ntrol s the In-

put Source Mux. (b). Bits AXG0 and AXG1

are bits D11 and D12 respectively in CFG0.

They control the AUX IN amplifier gain set-

ting . (c) . Bits FLD0 and FLD 1 are bi ts D2 and

D3 respectively in CFG1. They control the

sample rate and filter band pass setting.

(d). Bit FLS0 is bit D4 in CFG1. It controls the

FILTER MUX. (e). Bits S1S0 and S1S1 are bits

ISD5008 Product

ISD

D9 and D10 of CFG1. They control the

SUM1 MUX. (f). Bits VOL0, VOL1 and VOL2

are bits D11, D12 and D13 of CFG1. They

control the setting of the Volume Control.

(g). Bits VLS0 and VLS1 are bits D14 and D15

of CFG1. They control the Volume Control

MUX.

The end result of the above set u p is

CFG0=0100 0100 0000 1011 (hex 440B)

and

CFG1=0000 0001 1110 0011 (hex 01E3).

Since both registers are being loaded, CFG0 is

loaded followed by the loading of CFG1. These

two registe rs must be loade d in this order . The in-

ternal set up f or both registe rs will take effect syn-

chronously with the rising edge of SS.

5.2 CALL RECORD

The call record mode adds the ability to record

the incoming phone call. In most applications,

the ISD5008 would first be set up for Feed Through

Mode as d esc ri bed above. Wh en the user wishe s

to record the incoming call, the set up of the chip

is modi fied to ad d that abi lity. F or the purpo se of

this explanation, we will use the 6.4 kHz sample

rate during recording.

The block diagr am of the ISD5008 shows that the

Multilevel Storage array is always driven from the

SUM2 SUMMING amplifier. The path traces back

from there th rough the LOW PASS Filte r, THE FILTER

MUX, THE SUM1 SUMMING amplifier, the SUM1

MUX, then from the ANA in amplifier. Feed Through

Mode has already powered up the ANA IN amp

so we only need to power up and enable the path

to th e M u ltilevel Storage array from tha t point :

Select the ANA IN path through the SUM1

MUX

—Bits S1S0 and S1S1 control the state

of the SUM1 MUX. These are bits D9 and

D10 respect ively of CFG1 and th ey should

be set to the state where both D9 and D10

are ZERO to select th e A NA IN path.

Select the SUM 1 MUX inpu t (only ) to the S1

SUMMING amplifier

—Bits S1M0 and S1M1

control the state of the SUM1 SUMMING

amplifier. These are bits D7 and D8 respec-

tively of CFG1 and they should be set to the

stat e wher e D7 is ONE and D8 is ZE RO to s e-

lect the SUM1 MUX (only) path.

3. Select

the SUM1 SUMMING amplifier path

through the FILTER MUX

—Bit FLS0 controls

the state of the FILTER MUX. This is bit D4 of

CFG1 and it must be set to ZERO to select

the SUM1 SUMMING amplifier path.

Power up the LOWPASS FILTER

—Bit FLPD

controls the power up state of the LOWPASS

FILTER stage. This is bit D1 of CFG1 and it

must be set to ZERO to power up the LOW

PASS FILTER STAGE.

5. Select the 6.4 kHz sample rate—Bits

FLD0 and FLD1 select the Low Pass filter set-

ting and sample rate to be used during

record and playback. These are bits D2

and D3 of CFG1. To enable the 6.4 kHz

sample rate, D2 must be set to ONE and

D3 set to ZERO.

6. Select th e LO W PA SS FI LTE R in put (o nly)

to the S2 SUMMING amplifier—Bits S2M0

and S2M1 control the state of the SUM2

SUMMING amplifier. These are bits D5 and

D6 respectively of CFG1 and they should

be set to the state where D5 is ZERO and D6

is ONE to select the LOW PASS FILTER (only)

path.

In this mode, the elements of the original PASS

THROUGH mode do not change. The sections of

the chip not required to a dd the record pat h re-

main powered down. In fact, CFG0 does not

change and remains

CFG0=0100 0100 0000 1011 (hex 440B).

CFG1 changes to

CFG1=0000 0000 1100 0101 (hex 00C5).

Since CFG0 is not changed, it is only necessary to

load CFG1. Note that if only CFG0 was changed,

it would be necessary to load both registers.

ISD5008 Product

24 Voice Solutions in Silicon™

5.3 MEMO RECORD

The Memo Record mode sets the chip up to

record f rom the loca l microphon e into the ch ip’s

Multilevel Storage Array. A connected cellular

telephone or cordless phone chip set may remain

powered down and is not active in this mode. The

path to be used is microphone input to AGC am-

plifi er, the n thr oug h the IN PUT SO URC E MU X t o th e

SUM1 SUMMING amplifier. From there the path

goes through the FILTER MUX, the LOW PASS FILTER,

the SUM2 SUMMING amplifier, then to the MULTI-

LEVEL STORAGE ARRAY. In this instance, we will se-

lect the 5.3 kHz sam ple rate. The re st of the chip

may be powered down.

1. Power up the AGC amplifier—Bit AGPD

controls the power up state of the AGC

amplifier. This is bit D0 of CFG1 and must

be set to ZERO to power up this stage.

Select th e A GC am plifier th rough th e INP UT

SOURCE MUX

—Bi t INS0 contr ols the s tate o f

the INPUT SOURCE MUX. This is bit D9 of

CFG0 and must be set to a ZERO to select

the AGC amplifi er .

3. Select the INPUT SOURCE MUX (only) to

the S1 SUMMING amplifier—Bits S1M0

and S1M1 control the state of the SUM1

SUMMING ampl ifier. These are bits D7 and

D8 respectively of CFG1 and they should

be set to the state where D7 is ZERO and D8

is ONE to select the INPUT SOURCE MUX

(only) path.

4. Select the SUM1 SUMMING amplifier

path through the FILTER MUX—Bit FLS0

controls the state of the FILTER MUX. This is

bit D4 of CFG1 and it must be set to ZERO

to select the SUM1 SUMMING amplifier

path.

5. Power up the LOWPASS FILTER—Bit FLPD

controls the power up state of the LOWPASS

FILTER stage. This is bit D1 of CFG1 and it

must be set to ZERO to power up the LOW

PASS FILTER STAGE.

Select the 5.3 kHz sample rate

—Bits FLD0

and FLD1 select the Low Pass filter setting

and sample rate to be used during record

and playback. These are bits D2 and D3 of

CFG1. T o enable th e 5.3 kHz samp le rate,

D2 must be set to ZERO and D3 set to ONE.

7. Select th e LO W PA SS FI LTE R in put (o nly)

to the S2 SUMMING amplifier—Bits S2M0

and S2M1 control the state of the SUM2

SUMMING amplifier. These are bits D5 and

D6 respectively of CFG1 and they should

be set to the state where D5 is ZERO and D6

is ONE to select the LOW PASS FILTER (only)

path.

To set up the chip for Memo Record, the configu-

ration registers are set up as follows:

CFG0=0010 0100 0010 0001 (hex 2421).

CFG1=0000 0001 0100 1000 (hex 0148).

Only those portions necessary for this mode are

powered up.

5.4 MEMO AND CALL PLAYBACK

This mode sets the chip up for local playback of

message s recorded earl ier. Th e playback p ath is

from the MU L TILEV EL STO RA GE ARRA Y t o the FIL T ER

MUX, then to the LOW PASS FILTER stage. From

there the audio path goes through the SUM2 SUM-

MING amplifier to the VOLUME MUX, through the

VOLUME CONTROL then to the SPEAKER output

stage. We will assume that we are driving a pizeo

speaker element. This audio was previously re-

corded at 8 kHz. All unnecessary stages will be

powered down.

1. Select the MULTILEVEL STORAGE ARRAY

path through the FILTER MUX—Bit FLS0,

the state of the FILTER MUX. This is bit D4 of

CFG1 and must be set to ONE to select the

MULT ILE VEL STOR AGE AR RAY .

2. Power up the LOWPASS FILTER—Bit FLPD

controls the power up state of the LOWPASS

FILTER stage. This is bit D1 of CFG1 and it

must be set to ZERO to power up the LOW

PASS FILTER STAGE.

Select the 8.0 kHz sample rate

—Bits FLD0

and FLD1 select the Low Pass filter setting

and sample rate to be used durin g recor d

ISD5008 Product

ISD

and playback. These are bits D2 and D3 of

CFG1. To e nable the 8.0 kHz sample r ate,

D2 and D3 must be set to ZERO.

Select the LOW PASS FILTER input (only) to

the S2 SUMMING amplifier

—Bits S2M0 and

S2M1 control the state of the SUM2 SUM-

MING amplifier. These are bits D5 and D6

respectively of CFG1 and they should be

set to the state where D5 is ZERO and D6 is

ONE to select the LOW PASS FILTER (only)

path.

5. Select the SUM2 SUMMING amplifier

path through the VOLUME MUX—Bits

VLS0 and VLS1 control the state VOLUME

MUX. These bits are bits D14 and D15, re-

spectively of CFG1. They should be set to

the state where D14 is ONE and D15 is ZERO

to select the SUM2 SUMMING amplifier.

6. Power up the VOLUME CONTROL LEVEL—

Bit VLPD controls the power-up state of the

VOLUME CONTROL attenuator. This is Bit D0

of CFG0. Thi s bit must be set to a ZERO to

power-up the VOLUME CONT ROL.

7. Select a VOLUME CONTROL LEVEL—Bits

VOL0, VOL1, and VOL2 control the state of

the VOLUME CONTROL LEVEL. T hese are bits

D11, D12, and D13, respectivel y, of CF G1.

A binary count of 000 through 111 controls

the amount of attenuation through that

state. In most cases, the software will select

an attenuation level according to the de-

sires of the current users of the product. In

this example, we will assume the user wants

an attenuation of –12 dB. For that setting,

D11 should be set to ONE, D1 2 should be

set to ONE, and D13 should be set to a ZE-

RO.

8. Select the VOLUME CONTROL path

through the OUTPUT MUX—These are bit s

D3 and D4, respectively, of CFG0. They

should be set to the state where D3 is ZERO

and D4 is a ZERO to select the VOLUME

CONTROL.

9. Power up the SPEAKER amplifier and se-

lect the HIGH GAIN mode—Bits OPA0

and OPA1 cont rol the state of the spea ker

(SP+ and S P–) an d AUX OUT outp uts. Thes e

are bits D1 an d D2 of CFG0. Th ey mu st be

set to the stat e where D1 is ONE and D2 is

ZERO to power-up the speaker outputs in

the HIGH GAIN mode and to power-down

the AUX OUT.

To set up the chip for Memo or Call Playback, the

configur ation regi sters are set up as fo ll ows:

CFG0=0010 0100 0010 0010 (hex 2422).

CFG1=0101 1001 1101 0001 (hex 59D1).

Only those portions necessary for this mode are

powered up.

ISD5008 Product

Voice Solutions in Silicon™

1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum

ratings may affect device reliability. Functional operation is not implied at these conditions.

1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum

ratings may affect device reliability. Functional operation is not implied at these conditions.

1. Case Temperature

2. VCC = VCCA = VCCD

3. VSS = VSSA = VSSD

1. VCC = VCCA = VCCD

2. VSS = VSSA = VSSD

Table 10: Absolute Maximum Ratings (Packaged Parts)(1)

Condition Value

Junction temperature 150°C

Storage temperature range –65°C to +150°C

Voltage applied to any pin (VSS – 0.3 V) to (VCC + 0.3 V)

Voltage applied to MOSI, SCLK, INT, RAC and SS pins (Input

current limited to ±20mA) (VSS – 1.0 V) to 5.5V

Lead temperature (soldering – 10 seconds) 300°C

VCC – VSS –0.3 V to +7.0 V

Table 11: Absolute Maximum Ratings (Die)(1)

Condition Value

Junction temperature 150°C

Storage temperature range –65°C to +150°C

Voltage applied to MOSI, SCLK, INT, RAC and SS pins (Input

current limited to ±20mA) (VSS – 0.3 V) to 5.5V

VCC – VSS –0.3 V to +7.0 V

Table 12: Operating Conditions (Packaged Parts)

Condition Value

Commercial operating temperature range(1) 0°C to +70°C

Extended operating temperature(1) –20°C to +70°C

Industrial operating temperature(1) –40°C to +85°C

Supply voltage (VCC)(2) +2.7 V to +3.3 V

Ground voltage (VSS)(3) 0 V

Table 13: Operating Conditions (Die)

Condition Value

Commercial operating temperature range 0°C to +50°C

Supply voltage (VCC)(1) +2.7 V to +3.3 V

Ground voltage (VSS)(2) 0 V

ISD5008 Product

ISD

1. Typical values: TA = 25°C and Vcc = 3.0 V.

2. All min/max limits are guaranteed by ISD via electrical testing or characterization. Not all specifications are

100 percent tested.

3. VCCA and VCCD summed together.

4. SS = VCCA = VCCD, XCLK = MOSI = VSSA= VSSD and all other pins floating.

Table 14: General Parameters

Symbol Parameters Min(2) Typ(1) Max(2) Units Conditions

VIL Input Low Voltage VCC x0.2 V

VIH Input High Voltage VCC x0.8 V

VOL Output Low Voltage 0.4 V IOL = 10 µA

VOL1 RAC, INT Output Low

Voltage 0.4 V IOL = 1 mA

VOH Output High Voltage VCC –0.4 V I

OH = –10 µA

ICC VCC Current (Operating)

— Playback

— Record

— Feedthru

No load(3)

No load (3)

ISB VCC Current (Standby) 1 10 µA (3) (4)

IIL Input Leakage Current ±1 µA

IHZ MISO Tris tate Cur ren t 1 1 0 µA

ISD5008 Product

Voice Solutions in Silicon™

Table 15: Timing Parameters

Symbol Characteristic Min(2) Typ(1) Max(2) Units Conditions

FSSampling Frequency 8.0

6.4

5.3

4.0

kHz

(5)

FCF Filter Pass Band

8.0 kHz (sample rate)

6.4 kHz (sample rate)

5.3 kHz (sample rate)

4.0 kHz (sample rate)

3.4

2.7

2.3

1.7

kHz

3-dB Roll-Off Point( 3) (7)

TREC Record Duration

8.0 kHz (sample rate)

6.4 kHz (sample rate)

5.3 kHz (sample rate)

4.0 kHz (sample rate)

min

(6)

TPLAY Playback Duration

8.0 kHz (sample rate)

6.4 kHz (sample rate)

5.3 kHz (sample rate)

4.0 kHz (sample rate)

min

(6)

TPUD Power-Up Delay

8.0 kHz (sample rate)

6.4 kHz (sample rate)

5.3 kHz (sample rate)

4.0 kHz (sample rate)

31.25

37.5

msec

TSTOP OR PAUSE Stop or Pause

Record or Play

8.0 kHz (sample rate)

6.4 kHz (sample rate)

5.3 kHz (sample rate)

4.0 kHz (sample rate)

62.5

100

msec

TRAC RAC Clock Period

8.0 kHz (sample rate)

6.4 kHz (sample rate)

5.3 kHz (sample rate)

4.0 kHz (sample rate)

200

250

300

400

msec

(9)

TRACLO RAC Clock Low Time

8.0 kHz (sample rate)

6.4 kHz (sample rate)

5.3 kHz (sample rate)

4.0 kHz (sample rate)

31.25

37.5

msec

ISD5008 Product

ISD

TRACM RAC Clock Period in

Message Cuei ng

Mode

8.0 kHz (sample rate)

6.4 kHz (sample rate)

5.3 kHz (sample rate)

4.0 kHz (sample rate)

125

156.3

187.5

250

µsec

TRACML RAC Clock Low Time in

Message Cuei ng

Mode

8.0 kHz (sample rate)

6.4 kHz (sample rate)

5.3 kHz (sample rate)

4.0 kHz (sample rate)

15.63

19.53

23.44

31.25

µsec

THD Total Harmonic

Distortion

ANA IN to ARRAY,

ARRAY to SPKR

12%

@1 kHz at 0TLP, sample rate =

5.3kHz

Tabl e 16: A n alog Parameters

Symbol Characteristic Min(2) Typ(1) Max(2) Units Conditions

MICROPHONE INPUT (14)

VMIC+/– MIC +/– Input Voltage 3 300 mV Peak-to-Peak (4)(8)

VMIC (0TLP) MIC +/– input

reference transmission

level point (0TLP)

208 mV Peak-to-Peak(4)(10)

AMIC Gain fr om MIC+ /–

input to ANA OUT 5.5 6.0 6.5 dB 1kHz at V

MIC (0TLP) (4)

AMIC (GT) MIC +/– Gain Tracking ±0.1 dB 1 kHz, +3 to –40 dB 0TLP Input

RMIC Microphone input

resistance 51015kΩMIC– and MIC+ pins

AAGC Microphone AGC

Amplifier Range 640dB

Over 3–300 mV Input Range

ANA IN (14)

VANA IN ANA IN Input Voltage 1.6 V Peak-to-Peak (6dB gain

setting)

VANA IN (0TLP) ANA IN (0TLP) Input

Voltage 1.11 V Peak-to-Peak (6dB gain

setting)(10)

AANA IN (SP) Gain from ANA IN to

SP+/– 6 to 15 dB 4 Steps of 3 d B

Table 15: Timing Parameters

Symbol Characteristic Min(2) Typ(1) Max(2) Units Conditions

ISD5008 Product

Voice Solutions in Silicon™

Symbol Characteristic Min(2) Typ(1) Max(2) Units Conditions

AANA IN (AUX OUT) Gain from ANA IN to

AUX OUT –4 to +5 dB 4 Step s of 3 dB

AANA IN (GA) ANA IN Gain Accuracy –0.5 +0.5 dB (11)

AANA IN (GT) ANA IN Gain Tracking ±0.1 dB 1000 Hz, +3 to

–40 dB 0TLP Input, 6dB setting

RANA IN AN A IN Inp ut

Resistance 60 to 102 kΩSee Ra in Figure 2

AUX IN(14)

VAUX IN AUX IN Input Voltage 1.0 V Peak-to-Peak (0 dB gain

setting)

VAUX IN (0TLP) AUX IN (0TLP) Input

Voltage 694.2 mV Peak-to-Peak (0 dB gain

setting)(10)

AAUX IN (ANA OUT) Gain from AUX IN to

ANA OUT 0 to 9 dB 4 Steps o f 3dB

AAUX IN (GA) AUX IN Gain Accuracy –0.5 +0.5 dB (11)

AAux IN (G T ) AUX IN Gain Tracking ±0.1 dB 1000 Hz, +3 to

–40 dB 0TLP Input, 0dB setting

RAux IN AUX IN Inp ut

Resistance 21 to 40 kΩSee Ra in Figure 3

SPEAKER OUTPUT S(14)

VSPHG SP+/– Output Voltage

(High Gain setting) 3.6 V Peak -to-P ea k, diff er en tial lo ad

= 150Ω; OPA1, OPA0 = 01

RSPLG SP+/– Output Load

Imp. (Low Gain) 8ΩOPA1, OPA0 = 10

RSPHG SP+/– Output Load

Imp. (High Gain) 70 ΩOPA1, OPA0 = 01

CSP SP+/– Output Load

Cap. 100 pF

VSPAG SP+/– Output Bias

Voltage (analog

ground)

1.2 VDC

VSPDCO Speaker Output DC

Offset –100 100 mVDC W ith ANA IN to Speake r, ANA IN

AC coupled to VSSA

ICNANA IN/(SP+/–) ANA IN to SP+/– Idle

Channel Noise –65 dB Speaker load = 150Ω (12)(13)

CRT(SP+/–)/ANA

OUT

SP+/– to ANA OUT

Cross Talk –65 dB 1kHz 0TLP input to ANA IN, with

MIC+/– and AUX IN AC

coupled to VSSA, and

measured at ANA OUT

feedthrough mode (12)

PSRR Power Supply

Rejection Ratio –50 dB Measured with a 1kHz,100

mVpp sine wave input at VCCA

and VCCD pins

Tabl e 16: A n alog Parameters

ISD5008 Product

ISD

Symbol Characteristic Min(2) Typ(1) Max(2) Units Conditions

FRFrequency Respon se

(300–3400 Hz) –0.25 +0.25 dB With 0TLP input to ANA IN, 6dB

setting (12)

POUTLG Power Output (Low

Gain Setting) 23.5 mW

RMS Differential load at 8Ω

SINAD SINAD ANA IN to

SP+/– 62.5 dB 0TLP ANA IN input minimum

gain, 150Ω load (12)(13)

ANA OUT(14)

SINAD SINAD MIC IN to ANA

OUT +/- 62.5 dB Load = 5k Ω (12)(13)

SINAD SINAD AUX IN to ANA

OUT (0 to 9 dB) 62.5 dB Load = 5k Ω (12)(13)

ICNMIC/ANA OUT Idle Channel Noise—

Microphone –65 dB Load = 5k Ω (12)(13)

ICNAUX IN/ANA

OUT

Idle Channel Noise—

AUX IN (0 to 9 dB) –65 dB Load = 5k Ω (12)(13)

PSRR(ANA OUT) Power Supply

Rejection Ratio -50 dB Measured with a 1kHz,

100mVpp sine wave to VCCA,

VCCD pins

VBIAS ANA OUT+ and ANA

OUT– 1.2 VDC Inputs AC coupled to VSSA

VOFFSET ANA OUT+ to ANA

OUT– –100 +100 mVDC Inputs AC coupled to VSSA

RLMinimum Load

Impedence 5kΩDifferential Load

FRFrequenc y Response

(300–3400 Hz) –0.25 +0.25 dB 0TLP input to MIC+/- in

feedthrough mode.

0TLP input to AUX IN in

feedthrough mode(12)

CRTANA OUT/(SP+/-) ANA OUT to SP+/-

Cross Talk –65 dB 1kHz 0TLP output from ANA

OUT, with ANA IN AC coupled

to VSSA, and measured at

SP+/- (12)

CRTANA OUT/AUX OUT ANA OUT to AUX OUT

Cross Talk –65 dB 1kHz 0TLP output from ANA

OUT, with ANA IN AC coupled

to VSSA, and measured at AUX

OUT(12)

AUX OUT(14)

VAUX OUT AUX OUT—Maximum

Output Swing 1.0 Vpp 5 kΩ Load

RLMinimum Load

Impedence 5kΩ

CLMaximum Load

Capacitance 100 pF

Tabl e 16: A n alog Parameters

ISD5008 Product

Voice Solutions in Silicon™

1. Typical values: TA = 25°C and Vcc = 3.0V.

2. All min/max limits are guaranteed by ISD via electrical testing or characterization. Not all specifications are

100 percent tested.

3. Low-frequency cut off depends upon the value of external capacitors (see Pin Descriptions).

4. Differential input mode. Nominal differential input is 208 mVp-p. (0 dBm0)

5. Sampling frequency can vary as much as –6/+4 percent over the industrial temperature and voltage ranges.

For greater stability, an external clock can be utilized (see Pin Descriptions). Sampling frequency will be accurate

within ±1% for 5.3kHz, and ±5% for 4.0, 6.4 and 8.0 kHz sampling rates at room temperature.

6. Playback and Record Duration can vary as much as –6/+4 percent over the industrial temperature and voltage

ranges. For greater stability, an external clock can be utilized (See Pin Descriptions). Playback and record durations

are accurate within ±1% for 5.3kHz, and ±5% for 4.0, 6.4 and 8.0kHz sampling rates at room temperature.

7. Filter specification applies to the low pass filter. Ther efore, from input to output, expect a 6 dB drop by nature

of passing through the filter twice.

8. For optimal signal quality, this maximum limit is recommended.

9. When a record command is sent, TRAC = TRAC + TRACLO on the first row addressed.

10. The maximum signal level at any input is defined as 3.17dB higher than the reference transmission level point.

(0TLP) This is the point where signal clipping may begin.

11. Measured at 0TLP point for each gain setting. See Table 4 and Table 5.

12. 0TLP is the reference test level through inputs and outputs. See Table 4 and Table 5.

13. Referenced to 0TLP input at 1kHz, measured over 300 to 3,400 Hz bandwidth.

14. For die, only typical values from Analog Parameters are applicable.

Symbol Characteristic Min(2) Typ(1) Max(2) Units Conditions

VBIAS AUX OUT 1.2 VDC

SINAD SINAD—ANA IN to AUX

OUT 62.5 dB 0TLP ANA IN i nput, minimum

gain, 5k load (12)(13)

ICN(AUX OUT) Idle Channel Noise—

ANA IN to AUX OUT –65 dB Load = 5kΩ (12)(13)

CRTAUX OUT/ANA

OUT

AUX OUT to ANA OUT

cross Talk –65 dB 1 kHz 0TLP in put to ANA IN, with

MIC +/- and AUX IN AC

coupled to VSSA, and

measured at SP+/-, load =

5kΩ. Referenced to nominal

0TLP @ output

VOLUME CONTROL (14)

AOUT Output Gain –28 to 0 dB 8 Steps of 4 d B, referenced to

output

Gain Accuracy -0.5 0.5 dB ANA IN = 1 kHz 0TLP, 6d B Gai n

setting, measured differentially

at SP+/–

Tabl e 16: A n alog Parameters

ISD5008 Product

ISD

Table 17: SPI AC Parameters(1)

1. Typical values: TA= 25°C and Vcc= 3.0 V. Timing measured at 50 percent of the VCC level.

2. Tristate test condition

Symbol Characteristics Min Max Units Conditions

TSSS SS Setup Time 500 nsec

TSSH SS Hold Time 500 nsec

TDIS Data in Setup Time 200 nsec

TDIH Data in Hold Time 200 nsec

TPD Output Delay 500 nsec

TDF Output Delay to hiZ 500 nsec (2)

TSSmin SS HIGH 1 µsec

TSCKhi SCLK High Time 400 nsec

TSCKlow SCLK Low Time 400 nsec

F0CLK Frequency 1,000 kHz

ISD5008 Product

Voice Solutions in Silicon™

6TIMING DIAGRAMS

Figure 17: SPI Timi ng Di ag ram

Figure 18: 8-Bit SPI Command Format

ISD5008 Product

ISD

Figure 19 : 24-Bi t SPI Command Format

Figure 20: Playback/Record and Stop Cycle

MOSI

MISO

D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 C3 C4 C5 C6 C7

D0 D1 D2 D3 D4 D5

A4 A5 A6 A7 A8 A9OVF EOM A0 A1 A2 A3 A10

SCLK

BYTE 1 BYTE 2 BYTE 3

A11 A12 A13 A14 A15 XXXXXX

C1C0

ISD5008 Product

Voice Solutions in Silicon™

7 DEVICE PHYSICAL DIMENSIONS

Figure 21: 28-Le ad 8x13.4 mm Plastic Thin Sma ll Outline Packag e (TSO P ) Type I (E)

NOTE: Lead coplanarity to be within 0.004 inches.

Table 18: Pl ast ic Thin Small Outline Package (TSOP) Type I (E) Di mens ions

INCHES MILLIMETERS

Min Nom Max Min Nom Max

A 0.520 0.528 0.535 13.20 13.40 13.60

B 0.461 0.465 0.469 11.70 11.80 11.90

C 0.311 0.315 0.319 7.90 8.00 8.10

D 0.002 0.006 0.05 0.15

E 0.007 0.009 0.011 0.17 0.22 0.27

F 0.0217 0.55

G 0.037 0.039 0.041 0.95 1.00 1.05

H0°3°6°0°3°6°

I 0.020 0.022 0.028 0.50 0.55 0.70

J 0.004 0.008 0.10 0.21

ISD5008 Product

ISD

Figure 22: 28-L e ad 0.60 0-Inc h Pl astic Dua l In l i n e Packag e (PDIP) (P )

Table 19: Plastic Dual Inline Package (PDIP) (P) Dimensions

INCHES MILLIMETERS

Min Nom Max Min Nom Max

A 1.445 1.450 1.455 36.70 36.83 36.96

B1 0.150 3.81

B2 0.065 0.070 0.075 1.65 1.78 1.91

C1 0.600 0.625 15.24 15.88

C2 0.530 0.540 0.550 13.46 13.72 13.97

D 0.19 4.83

D1 0.015 0.38

E 0.125 0.135 3.18 3.43

F 0.015 0.018 0.022 0.38 0.46 0.56

G 0.055 0.060 0.065 1.40 1.52 1.65

H 0.100 2.54

J 0.008 0.010 0.012 0.20 0.25 0.30

S 0.070 0.075 0.080 1.78 1.91 2.03

θ0° 15° 0° 15°

ISD5008 Product

38 Voice Solutions in Silicon™

Figure 23: 28-Lead 0.300-Inch Plastic Small Outline Integrated Circuit (SOIC) (S)

NOTE: Lead coplanarity to be within 0.004 inches.

Table 20: Plastic Small Outline Integrated Circuit (SOIC) (S) Dimensions

INCHES MILLIMETERS

Min Nom Max Min Nom Max

A 0.701 0.706 0.711 17.81 17.93 18.06

B 0.097 0.101 0.104 2.46 2.56 2.64

C 0.292 0.296 0.299 7.42 7.52 7.59

D 0.005 0.009 0.0115 0.127 0.22 0.29

E 0.014 0.016 0.019 0.35 0.41 0.48

F 0.050 1.27

G 0.400 0.406 0.410 10.16 10.31 10.41

H 0.024 0.032 0.040 0.61 0.81 1.02

ISD5008 Product

ISD

Figure 24: ISD5008 Series Bonding Physical Layout(1) (Unpackaged Die)

1. The backside of die is internally connected to VSS. It MUST NOT be connected to any other potential or damage

may occur.

2. Double bond recommended.

3. This figure reflects the current die thickness. Please contact ISD as this thickness may change in the future.

ISD5008 Series

I. Die Dimensions

X: 166.5 ±1 mils

Y: 302.4 ±1 mils

II. Die Thickness(3)

11.5 ±1.0 mils

III. Pad Opening (min)

90 x 90 microns

3.5 x 3.5 mils

VSSD

ISD5008

VSSA

MIC+ AUX IN

ANA IN

ANAOUT+

MIC–

VSSA(2)

ANAOUT–

ACAP

AUXOUT

SP– VCCA(2)

SP+

RAC

VSSD MISO MOSI SS SCLK VCCD VCCD INT

XCLK

ISD5008 Product

40 Voice Solutions in Silicon™

Table 21: ISD5008 Series Device Pin/Pad Designations,

with Respect to Die Center (µm)

1. Double bond recommended.

Pin Pin Name XAxis YAxis

VSSD VSS Digital Power Supply –1837.0 3623.7

VSSD VSS Digital Power Supply –1665.4 3623.7

MISO Master In Slave Out –1325.7 3623.7

MOSI Master Out Slave In –1063.8 3623.7

SS Slave Select –198.2 3623.7

SCLK Slave Clock –14.8 3623.7

VCCD VCC Digital Power Supply 169.4 3623.7

VCCD VCC Digital Power Supply 384.8 3623.7

XCLK External Clock I nput 564.7 3623.7

INT Interrupt 794.7 3623.7

RAC Row Address Clock 1483.7 3623.7

VSSA VSS Analog Power Supply 1885.1 3623.7

VSSA VSS Analog Power Supply –1943.2 –3615.9

MIC+ Noninverting Microphone Input –1735.4 –3615.9

MIC– Inverting Microphone Input –1502.9 –3615.9

ANA OUT + Noninverting Analog Output —125 1.2 –3615.9

ANA OU T – Inverting Analog Output –917.0 –3615.9

ACAP AGC/AutoMute Cap –632.6 –3615.9

SP– Inverting Speaker Output –138.4 –3615.9

VSSA(1) VSS Analog Power Supply 240.2 –3615.9

SP+ Noninverting Speaker Output 618.8 –3615.9

VCCA(1) VCC Analog Power Supply 997.4 –3615.9

ANA IN Analog Input 1249.9 –3615.9

AUX IN Auxiliary Input 1515.5 –3615. 9

AUX OUT Auxiliary Output 1758.4 –361 5.9

ISD5008 Product

ISD

Figure 25: SD5008 Chip Scale Package (CSP) (Z)

Table 22: CSP Dimensions (mm)

TOP VIEW BOTTOM VIEW

SIDE VIEW

A5 A4 A3

B5 B4 B3 B2

C5 C4 C3 C2

D5 D4 D3 D2

E5 E4 E3 E2

A1 Ball Corner

A2 A1

Symbol Min. Nom. Max.

A——0.86

A10.18 — —

A2—0.55—

b 0.30 0.35 0.40

C—4.68—

D—8.13—

e0.75

F—3.00—

G—0.84—

H—2.57—

I—3.00—

Name

Ball

Location

MIC- A1

ACAP A2

VSSA A3

VCCA A4

AUX IN A5

MIC+ B1

ANA OU T- B2

SP- B3

ANA IN B4

AUX OUT B5

VSSA C1

ANA OU T+C2

SP+ C3

VCCD C4

VSSA C5

VSSD D1

MISO D2

SS D3

XCLK D4

RAC D5

VSSD E1

MOSI E2

SCLK E3

VCCD E4

INT E5

ISD5008 Product

42 Voice Solutions in Silicon™

8 ORDERING INFORMATION

When ordering ISD5008 series devices, please refer to the following valid part numbers.

For the latest product information, access ISD’s worldwide website at http://www.isd.com.

Part Number

ISD5008E

ISD5008ED

ISD5008EI

ISD5008P

ISD5008S

ISD5008SD

ISD5008SI

ISD5008X

ISD5008Z

ISD5008ZD

ISD5008ZI

Product Family

ISD5 00 8 Prod u c t

(4 to 8 minute durations)

Special Temperature Field:

Blank = Commercial Packaged (0°C to +70°C)

or Commercial Die (0°C to +50°C)

D= Extended (–20°C to +70°C)

I= Industr ial (–40 °C to +85 °C )

Package Type:

E= 28-Lead 8x13.4mm Plastic Thin Small Outline

Package (TSOP) Type 1

P= 28-Lead 0.600-Inch Plastic Dual Inline Package

(PDIP)

S= 28-Lead 0.300-Inch Plastic Small Outline Package

(SOIC)

X=Die

Z= Chip Scale Package (CSP)

ISD5008–_ _

ISD Part Number Description

ISD5008 Product

ISD

Part No. ISD5008PDS1-799

2727 North First Street

San Jose, California 95134

Tel: 408/943-6666

Fax: 408/544-1787

http://www.isd.com

IMPORTANT NOTICES

The warranty for each product of ISD (Information Storage

Devices, Inc.), is contained in a written warranty which governs

sale and use of such product. Such warranty is contained in the

printed terms and conditions under which such product is sold, or

in a separate written warranty supplied with the product. Please

refer to such written warranty with respect to its applicability to

certain applications of such product.

These Products may be subject to restrictions on use. Please

contact ISD for a list of the current additional restrictions on these

Products. By purchasing these Products, the purchaser of these

Products agrees to comply with such use restrictions. Please

contact ISD for clarification of any restrictions described herein.

ISD, reserves the right, without further notice, to change the ISD

ChipCorder product specifications and/or information in this

document and to improve reliability, functions and design.

ISD assumes no responsibility or liability for any use of the ISD

ChipCorder Product. ISD conveys no license or title, either

expressed or implied, under any patent, copyright, or mask work

right to the ISD ChipCorder Product, and ISD makes no warranties

or representations that the ISD ChipCorder Product are free from

patent, copyright, or mask work right infringement, unless

otherwise specified.

Application examples and alternative uses of any integrated

circuit contained in this publication are for illustration purposes

only and ISD makes no representation or warranty that such

applications shall be suitable for the use specified.

The 100-year retention and 100K record cycle projections are

based upon accelerated reliability tests, as published in the ISD

Reliability Report, and are neither warranted nor guaranteed by

ISD.

Information contained in this ISD ChipCorder data sheet

supersedes all data for the ISD ChipCorder Product published by

ISD prior to October, 1999.

This data sheet and any future addendum to this data sheet is

(are) the complete and controlling ISD ChipCorder product

specifications. In the event any inconsistencies exist between the

information in this and other product documentation, or in the

event that other product documentation contains information in

addition to the information in this, the information contained

herein supersedes and governs such other information in its entirety.

reserved. ISD is a registered trademark of ISD. ChipCorder is a

trademark of ISD. All other trademarks are properties of their

respective owners.