MCP3221A0T-E/OT - Microchip Technology

MCP3221

Features

• 12-bit resolution

• ±1 LSB DNL, ±2 LSB INL max.

• 250 µA max conversion current

• 5 nA typical standby current, 1 µA max.

•I

2C™-compatible serial interface

- 100 kHz I2C Standard Mode

- 400 kHz I2C Fast Mode

• Up to 8 devices on a single 2-Wire bus

• 22.3 ksps in I2C Fast Mode

• Single-ended analog input channel

• On-chip sample and hold

• On-chip conversion clock

• Single-supply specified operation: 2.7V to 5.5V

• Temperature range:

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

• Small SOT-23-5 package

Applications

• Data Logging

• Multi-zone Monitoring

• Hand-Held Portable Applications

• Battery-Powered Test Equipment

• Remote or Isolated Data Acquisition

Package Type

Description

The Microchip Technology Inc. MCP3221 is a

successive approximation A/D converter with 12-bit

resolution. Available in the SOT-23-5 package, this

device provides one single-ended input with very low

power consumption. Based on an advanced CMOS

technology, the MCP3221 provides a low maximum

conversion current and standby current of 250 µA and

1 µA, respectively. Low current consumption,

combined with the small SOT-23 package, make this

device ideal for battery-powered and remote data

acquisition applications.

Communication to the MCP3221 is performed using a

2-wire, I2C compatible interface. Standard (100 kHz)

and Fast (400 kHz) I2C modes are available with the

device. An on-chip conversion clock enables

independent timing for the I2C and conversion clocks.

The device is also addressable, allowing up to eight

devices on a single 2-wire bus.

The MCP3221 runs on a single supply voltage that

operates over a broad range of 2.7V to 5.5V. This

device also provides excellent linearity of ±1 LSB

differential non-linearity and ±2 LSB integral non-lin-

earity, maximum.

Functional Block Diagram

5-Pin SOT-23

SCL

AIN

MCP3221

SDA

VSS

VDD

Comparator

Sample

and

Hold

12-bit SAR

DAC

I2C™ Interface

AIN

VSS

VDD

SCL SDA

Clock

Control Logic

–

Low Power 12-Bit A/D Converter With I2C™ Interface

MCP3221

1.0 ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

VDD...................................................................................7.0V

Analog input pin w.r.t. VSS.......... ............. -0.6V to VDD +0.6V

SDA and SCL pins w.r.t. VSS........... .........-0.6V to VDD +1.0V

Storage temperature .....................................-65°C to +150°C

Ambient temp. with power applied ................-65°C to +125°C

Maximum Junction Temperature .......... .........................150°C

ESD protection on all pins (HBM) .................................≥ 4kV

† Stresses above those listed under “Maximum ratings” may

cause permanent damage to the device. This is a stress rating

only and functional operation of the device at those or any

other conditions above those indicated in the operational list-

ings of this specification is not implied. Exposure to maximum

rating conditions for extended periods may affect device

reliability.

DC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.0V, VSS = GND, RPU = 2 kΩ

TAMB = -40°C to +85°C, I2C Fast Mode Timing: fSCL = 400 kHz (Note 3).

Parameters Sym Min Typ Max Units Conditions

DC Accuracy

Resolution 12 bits

Integral Nonlinearity INL — ±0.75 ±2 LSB

Differential Nonlinearity DNL — ±0.5 ±1 LSB No missing codes

Offset Error — ±0.75 ±2 LSB

Gain Error — -1 ±3 LSB

Dynamic Performance

Total Harmonic Distortion THD — -82 — dB VIN = 0.1V to 4.9V @ 1 kHz

Signal-to-Noise and Distortion SINAD — 72 — dB VIN = 0.1V to 4.9V @ 1 kHz

Spurious-Free Dynamic Range SFDR — 86 — dB VIN = 0.1V to 4.9V @ 1 kHz

Analog Input

Input Voltage Range VSS-0.3 — VDD+0.3 V 2.7V ≤ VDD ≤ 5.5V

Leakage Current -1 — +1 µA

SDA/SCL (open-drain output):

Data Coding Format Straight Binary

High-level input voltage VIH 0.7 VDD ——V

Low-level input voltage VIL — — 0.3 VDD V

Low-level output voltage VOL ——0.4VI

OL = 3 mA, RPU = 1.53 kΩ

Hysteresis of Schmitt trigger inputs VHYST —0.05V

DD —Vf

SCL = 400 kHz only

Input leakage current ILI -1 — +1 µA VIN = 0.1 VDD and 0.9 VDD

Output leakage current ILO -1 — +1 µA VOUT = 0.1 VSS and

0.9 VDD

Pin capacitance

(all inputs/outputs)

CIN,

COUT

— — 10 pF TAMB = 25°C, f = 1 MHz;

(Note 2)

Bus Capacitance CB— — 400 pF SDA drive low, 0.4V

Note 1: “Sample time” is the time between conversions once the address byte has been sent to the converter.

Refer to Figure 5-6.

2: This parameter is periodically sampled and not 100% tested.

3: RPU = Pull-up resistor on SDA and SCL.

4: SDA and SCL = VSS to VDD at 400 kHz.

5: tACQ and tCONV are dependent on internal oscillator timing. See Figure 5-5 and Figure 5-6 for relation to

SCL.

MCP3221

TEMPERATURE SPECIFICATIONS

Power Requirements

Operating Voltage VDD 2.7 — 5.5 V

Conversion Current IDD — 175 250 µA

Standby Current IDDS — 0.005 1 µA SDA, SCL = VDD

Active bus current IDDA — — 120 µA Note 4

Conversion Rate

Conversion Time tCONV —8.96—µsNote 5

Analog Input Acquisition Time tACQ —1.12—µsNote 5

Sample Rate fSAMP — — 22.3 ksps fSCL = 400 kHz (Note 1)

Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.0V, VSS = GND.

Parameters Symbol Min Typ Max Units Conditions

Temperature Ranges

Industrial Temperature Range TA-40 — +85 °C

Extended Temperature Range TA-40 — +125 °C

Operating Temperature Range TA-40 — +125 °C

Storage Temperature Range TA-65 — +150 °C

Thermal Package Resistances

Thermal Resistance, 5L-SOT23 θJA —256 —°C/W

DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.0V, VSS = GND, RPU = 2 kΩ

TAMB = -40°C to +85°C, I2C Fast Mode Timing: fSCL = 400 kHz (Note 3).

Parameters Sym Min Typ Max Units Conditions

Note 1: “Sample time” is the time between conversions once the address byte has been sent to the converter.

Refer to Figure 5-6.

2: This parameter is periodically sampled and not 100% tested.

3: RPU = Pull-up resistor on SDA and SCL.

4: SDA and SCL = VSS to VDD at 400 kHz.

5: tACQ and tCONV are dependent on internal oscillator timing. See Figure 5-5 and Figure 5-6 for relation to

SCL.

MCP3221

TIMING SPECIFICATIONS

FIGURE 1-1: Standard and Fast Mode Bus Timing Data.

Electrical Characteristics: All parameters apply at VDD = 2.7V - 5.5V, VSS = GND, TAMB = -40°C to +85°C.

Parameters Sym Min Typ Max Units Conditions

I2C Standard Mode

Clock frequency fSCL 0 — 100 kHz

Clock high time THIGH 4000 — — ns

Clock low time TLOW 4700 — — ns

SDA and SCL rise time TR— — 1000 ns From VIL to VIH (Note 1)

SDA and SCL fall time TF— — 300 ns From VIL to VIH (Note 1)

START condition hold time THD:STA 4000 — — ns

START condition setup time TSU:STA 4700 — — ns

Data input setup time TSU:DAT 250 — — ns

STOP condition setup time TSU:STO 4000 — — ns

STOP condition hold time THD:STD 4000 — — ns

Output valid from clock TAA — — 3500 ns

Bus free time TBUF 4700 — — ns Note 2

Input filter spike suppression TSP — — 50 ns SDA and SCL pins (Note 1)

I2C Fast Mode

Clock frequency FSCL 0 — 400 kHz

Clock high time THIGH 600 — — ns

Clock low time TLOW 1300 — — ns

SDA and SCL rise time TR20 + 0.1CB— 300 ns From VIL to VIH (Note 1)

SDA and SCL fall time TF20 + 0.1CB— 300 ns From VIL to VIH (Note 1)

START condition hold time THD:STA 600 — — ns

START condition setup time TSU:STA 600 — — ns

Data input hold time THD:DAT 0—0.9ms

Data input setup time TSU:DAT 100 — — ns

STOP condition setup time TSU:STO 600 — — ns

STOP condition hold time THD:STD 600 — — ns

Output valid from clock TAA — — 900 ns

Bus free time TBUF 1300 — — ns Note 2

Input filter spike suppression TSP — — 50 ns SDA and SCL pins (Note 1)

Note 1: This parameter is periodically sampled and not 100% tested.

2: Time the bus must be free before a new transmission can start.

THIGH VHYS TR

TSU:STA

TSP

THD:STA

TLOW THD:DAT TSU:DAT TSU:STO

TBUF

TAA

SCL

SDA

OUT

MCP3221

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion

Mode (fSAMP = 22.3 ksps), TA = +25°C.

FIGURE 2-1: INL vs. Clock Rate.

FIGURE 2-2: INL vs. VDD - I2C™

Standard Mode (fSCL = 100 kHz).

FIGURE 2-3: INL vs. Code

(Representative Part).

FIGURE 2-4: INL vs. Clock Rate

(VDD =2.7V).

FIGURE 2-5: INL vs. VDD - I2C™ Fast

Mode (fSCL = 400 kHz).

FIGURE 2-6: INL vs. Code

(Representative Part, VDD = 2.7V).

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

0 100 200 300 400

I2C Bus Rate (kHz)

INL (LSB)

Positive INL

Negative INL

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

2.533.544.555.5

VDD (V)

INL (LSB)

Positive INL

Negative INL

-2

-1.5

-1

-0.5

0.5

1.5

0 1024 2048 3072 4096

Digital Code

INL (LSB)

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

0 100 200 300 400

I2C Bus Rate (kHz)

INL (LSB)

Positive INL

Negative INL

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

2.533.544.555.5

VDD (V)

INL (LSB)

Positive INL

Negative INL

-2

-1.5

-1

-0.5

0.5

1.5

0 1024 2048 3072 4096

Digital Code

INL (LSB)

MCP3221

Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion

Mode (fSAMP = 22.3 ksps), TA = +25°C.

FIGURE 2-7: INL vs. Temperature.

FIGURE 2-8: DNL vs. Clock Rate.

FIGURE 2-9: DNL vs. VDD - I2C™

Standard Mode (fSCL = 100 kHz).

FIGURE 2-10: INL vs. Temperature

(VDD =2.7V).

FIGURE 2-11: DNL vs. Clock Rate

(VDD =2.7V).

FIGURE 2-12: DNL vs. VDD - I2C™ Fast

Mode (fSCL = 400 kHz).

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

-50 -25 0 25 50 75 100 125

Temperature (°C)

INL (LSB)

Positive INL

Negative INL

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

0 100 200 300 400

I2C Bus Rate (kHz)

DNL (LSB)

Positive DNL

Negative DNL

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

2.5 3 3.5 4 4.5 5 5.5

VDD (V)

DNL (LSB)

Positive DNL

Negative DNL

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

-50 -25 0 25 50 75 100 125

Temperature (°C)

INL (LSB)

Negative INL

Positive INL

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

0 100 200 300 400

I2C Bus Rate (kHz)

DNL (LSB)

Negative DNL

Positive DNL

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

2.533.544.555.5

VDD (V)

DNL (LSB)

Positive DNL

Negative DNL

MCP3221

Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion

Mode (fSAMP = 22.3 ksps), TA = +25°C.

FIGURE 2-13: DNL vs. Code

(Representative Part).

FIGURE 2-14: DNL vs. Temperature.

FIGURE 2-15: Gain Error vs. VDD.

FIGURE 2-16: DNL vs. Code

(Representative Part, VDD = 2.7V).

FIGURE 2-17: DNL vs. Temperature

(VDD =2.7V).

FIGURE 2-18: Offset Error vs. VDD.

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

0 1024 2048 3072 4096

Digital Code

DNL (LSB)

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

-50 -25 0 25 50 75 100 125

Temperature (°C)

DNL (LSB)

Negative DNL

Positive DNL

-1

-0.9

-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

2.533.544.555.5

VDD (V)

Gain Error (LSB)

Fast Mode

(fSCL= 100 kHz) Standard Mode

(fSCL= 400 kHz)

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

0 1024204830724096

Digital Code

DNL (LSB)

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

-50 -25 0 25 50 75 100 125

Temperature (°C)

DNL (LSB)

Positive DNL

Negative DNL

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

2.5 3 3.5 4 4.5 5 5.5

VDD (V)

Offset Error (LSB)

fSCL = 100 kHz & 400 kHz

MCP3221

Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion

Mode (fSAMP = 22.3 ksps), TA = +25°C.

FIGURE 2-19: Gain Error vs. Temperature.

FIGURE 2-20: SNR vs. Input Frequency.

FIGURE 2-21: THD vs. Input Frequency.

FIGURE 2-22: Offset Error vs.

Temperature.

FIGURE 2-23: SINAD vs. Input Frequency.

FIGURE 2-24: SINAD vs. Input Signal

Level.

-3

-2

-1

-50 -25 0 25 50 75 100 125

Temperature (°C)

Gain Error (LSB)

VDD = 5V

VDD = 2.7V

100

110

Input Frequency (kHz)

SNR (dB)

VDD = 5V

VDD = 2.7V

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

110

Input Frequency (kHz)

THD (dB)

VDD = 2.7V

VDD = 5V

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

-50 -25 0 25 50 75 100 125

Temperature (°C)

Offset Error (LSB)

VDD = 5V

VDD = 2.7V

100

110

Input Frequency (kHz)

SINAD (dB)

VDD = 5V

VDD = 2.7V

-40 -30 -20 -10 0

Input Signal Level (dB)

SINAD (dB)

VDD = 5V

VDD = 2.7V

MCP3221

Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion

Mode (fSAMP = 22.3 ksps), TA = +25°C.

FIGURE 2-25: ENOB vs. VDD.

FIGURE 2-26: SFDR vs. Input Frequency.

FIGURE 2-27: Spectrum Using I2C™ Fast

Mode (Representative Part, 1 kHz Input

Frequency).

FIGURE 2-28: ENOB vs. Input Frequency.

FIGURE 2-29: Spectrum Using I2C™

Standard Mode (Representative Part, 1 kHz

Input Frequency).

FIGURE 2-30: IDD (Conversion) vs. VDD.

11.5

11.55

11.6

11.65

11.7

11.75

11.8

11.85

11.9

11.95

2.533.544.555.5

VDD (V)

ENOB (rms)

100

110

Input Frequency (kHz)

SFDR (dB)

VDD = 2.7V

VDD = 5V

-130

-110

-90

-70

-50

-30

-10

0 2000 4000 6000 8000 10000

Frequency (Hz)

Amplitude (dB)

9.5

10.5

11.5

110

Input Frequency (kHz)

ENOB (rms)

VDD = 2.7V

VDD = 5V

-130

-110

-90

-70

-50

-30

-10

0 500 1000 1500 2000 2500

Frequency (Hz)

Amplitude (dB)

fSAMP = 5.6 ksps

100

150

200

250

2.533.544.555.5

VDD (V)

IDD (µA)

MCP3221

Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion

Mode (fSAMP = 22.3 ksps), TA = +25°C.

FIGURE 2-31: IDD (Conversion) vs. Clock

Rate.

FIGURE 2-32: IDD (Conversion) vs.

Temperature.

FIGURE 2-33: IDDA (Active Bus) vs. VDD.

FIGURE 2-34: IDDA (Active Bus) vs. Clock

Rate.

FIGURE 2-35: IDDA (Active Bus) vs.

Temperature.

FIGURE 2-36: IDDS (Standby) vs. VDD.

100

120

140

160

180

200

0 100 200 300 400

I2C Clock Rate (kHz)

IDD (µA)

VDD = 5V

VDD = 2.7V

100

150

200

250

-50-25 0 255075100125

Temperature (°C)

IDD (µA)

VDD = 5V

VDD = 2.7V

100

2.5 3 3.5 4 4.5 5 5.5

VDD (V)

IDDA (µA)

100

0 100 200 300 400

I2C Clock Rate (kHz)

IDDA (µA)

VDD = 5V

VDD = 2.7V

100

-50-25 0 255075100125

Temperature (°C)

IDDA (µA)

VDD = 5V

VDD = 2.7V

2.5 3 3.5 4 4.5 5 5.5

VDD (V)

IDDS (pA)

MCP3221

Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion

Mode (fSAMP = 22.3 ksps), TA = +25°C.

FIGURE 2-37: IDDS (Standby) vs.

Temperature.

FIGURE 2-38: Analog Input Leakage vs.

Temperature.

2.1 Test Circuits

FIGURE 2-39: Typical Test Configuration.

0.0001

0.001

0.01

0.1

100

1000

-50 -25 0 25 50 75 100 125

Temperature (°C)

IDDS (nA)

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

-50 -25 0 25 50 75 100 125

Temperature (°C)

Analog Input Leakage (nA)

0.1 µF

AIN MCP3221

VDD = 5V

VCM = 2.5V

VIN

VDD

VSS

10 µF

SDA

SCL

2kΩ2kΩ

MCP3221
DS21732C-page 12 © 2006 Microchip Technology Inc.
3.0 PIN FUNCTIONS
TABLE 3-1: PIN FUNCTION TABLE
3.1 VDD and VSS
The VDD pin, with respect to VSS, provides power to the
device as well as a voltage reference for the conversion
process. Refer to Section 6.4 “Device Power and
Layout Considerations”, “Device Power and Layout
Considerations”, for tips on power and grounding.
3.2 Analog Input (AIN)
AIN is the input pin to the sample-and-hold circuitry of
the Successive Approximation Register (SAR) con-
verter. Care should be taken in driving this pin. Refer to
Section 6.1 “Driving the Analog Input”, “Driving the
Analog Input”. For proper conversions, the voltage on
this pin can vary from VSS to VDD.
3.3 Serial Data (SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. Since it is an open-
drain terminal, the SDA bus requires a pull-up resistor
to VDD (typically 10 kΩ for 100 kHz and 2 kΩ for
400 kHz SCL clock speeds). Refer to Section 6.2
“Connecting to the I2C Bus”, “Connecting to the I2C
Bus”, for more information.
For normal data transfer, SDA is allowed to change only
during SCL low. Changes during SCL high are reserved
for indicating the START and STOP conditions. Refer to
Section 5.1 “I2C Bus Characteristics”, “I2C Bus
Characteristics”.
3.4 Serial Clock (SCL)
SCL is an input pin used to synchronize the data trans-
fer to and from the device on the SDA pin and is an
open-drain terminal. Therefore, the SCL bus requires a
pull-up resistor to VDD (typically 10 kΩ for 100 kHz and
2kΩ for 400 kHz SCL clock speeds. Refer to
Section 6.2 “Connecting to the I2C Bus”, “Connect-
ing to the I2C Bus”).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the START and STOP
conditions. Refer to Section 6.1 “Driving the Analog
Input”, “Driving the Analog Input”.
Name Function
VDD +2.7V to 5.5V Power Supply
VSS Ground
AIN Analog Input
SDA Serial Data In/Out
SCL Serial Clock In

MCP3221

4.0 DEVICE OPERATION

The MCP3221 employs a classic SAR architecture.

This architecture uses an internal sample and hold

capacitor to store the analog input while the conversion

is taking place. At the end of the acquisition time, the

input switch of the converter opens and the device uses

the collected charge on the internal sample-and-hold

capacitor to produce a serial 12-bit digital output code.

The acquisition time and conversion is self-timed using

an internal clock. After each conversion, the results are

stored in a 12-bit register that can be read at any time.

Communication with the device is accomplished with a

2-wire, I2C interface. Maximum sample rates of

22.3 ksps are possible with the MCP3221 in a continu-

ous-conversion mode and an SCL clock rate of

400 kHz.

4.1 Digital Output Code

The digital output code produced by the MCP3221 is a

function of the input signal and power supply voltage,

VDD. As the VDD level is reduced, the LSB size is

reduced accordingly. The theoretical LSB size is shown

below.

EQUATION

The output code of the MCP3221 is transmitted serially

with MSB first. The format of the code is straight binary.

4.2 Conversion Time (tCONV)

The conversion time is the time required to obtain the

digital result once the analog input is disconnected

from the holding capacitor. With the MCP3221, the

specified conversion time is typically 8.96 µs. This time

is dependent on the internal oscillator and is

independent of SCL.

4.3 Acquisition Time (tACQ)

The acquisition time is the amount of time the sample

cap array is acquiring charge.

The acquisition time is, typically, 1.12 µs. This time is

dependent on the internal oscillator and independent of

SCL.

4.4 Sample Rate

Sample rate is the inverse of the maximum amount of

time that is required from the point of acquisition of the

first conversion to the point of acquisition of the second

conversion.

The sample rate can be measured either by single or

continuous conversions. A single conversion includes

a Start Bit, Address Byte, Two Data Bytes and a Stop

bit. This sample rate is measured from one Start Bit to

the next Start Bit.

For continuous conversions (requested by the Master

by issuing an acknowledge after a conversion), the

maximum sample rate is measured from conversion to

conversion or a total of 18 clocks (two data bytes and

two Acknowledge bits). Refer to Section 5.2 “Device

Addressing”, “Device Addressing”.

FIGURE 4-1: Transfer Function.

LSB SIZE

VDD

4096

------------=

VDD = Supply voltage

1111 1111 1111 (4095)

1111 1111 1110 (4094)

AIN

0000 0000 0001 (1)

0000 0000 0011 (3)

Output Code

VDD-1.5 LSB

.5 LSB

1.5 LSB VDD-2.5 LSB

2.5 LSB

0000 0000 0000 (0)

0000 0000 0010 (2)

MCP3221

4.5 Differential Non-Linearity (DNL)

In the ideal A/D converter transfer function, each code

has a uniform width. That is, the difference in analog

input voltage is constant from one code transition point

to the next. Differential nonlinearity (DNL) specifies the

deviation of any code in the transfer function from an

ideal code width of 1 LSB. The DNL is determined by

subtracting the locations of successive code transition

points after compensating for any gain and offset

errors. A positive DNL implies that a code is longer than

the ideal code width, while a negative DNL implies that

a code is shorter than the ideal width.

4.6 Integral Non-Linearity (INL)

Integral nonlinearity (INL) is a result of cumulative DNL

errors and specifies how much the overall transfer

function deviates from a linear response. The method

of measurement used in the MCP3221 A/D converter

to determine INL is the “end-point” method.

4.7 Offset Error

Offset error is defined as a deviation of the code transi-

tion points that are present across all output codes.

This has the effect of shifting the entire A/D transfer

function. The offset error is measured by finding the dif-

ference between the actual location of the first code

transition and the desired location of the first transition.

The ideal location of the first code transition is located

at 1/2 LSB above VSS.

4.8 Gain Error

The gain error determines the amount of deviation from

the ideal slope of the A/D converter transfer function.

Before the gain error is determined, the offset error is

measured and subtracted from the conversion result.

The gain error can then be determined by finding the

location of the last code transition and comparing that

location to the ideal location. The ideal location of the

last code transition is 1.5 LSBs below full-scale or VDD.

4.9 Conversion Current (IDD)

The average amount of current over the time required

to perform a 12-bit conversion.

4.10 Active Bus Current (IDDA)

The average amount of current over the time required

to monitor the I2C bus. Any current the device con-

sumes while it is not being addressed is referred to as

“Active Bus” current.

4.11 Standby Current (IDDS)

The average amount of current required while no con-

version is occurring and while no data is being output

(i.e., SCL and SDA lines are quiet).

4.12 I2C Standard Mode Timing

I2C specification where the frequency of SCL is

100 kHz.

4.13 I2C Fast Mode Timing

I2C specification where the frequency of SCL is

400 kHz.

MCP3221

5.0 SERIAL COMMUNICATIONS

5.1 I2C Bus Characteristics

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high will be

interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been

defined (refer to Figure 5-1).

5.1.1 BUS NOT BUSY (A)

Both data and clock lines remain high.

5.1.2 START DATA TRANSFER (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a START condition. All

commands must be preceded by a START condition.

5.1.3 STOP DATA TRANSFER (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a STOP condition. All

operations must be ended with a STOP condition.

5.1.4 DATA VALID (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the clock signal’s high period.

The data on the line must be changed during the low

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

data bytes transferred between the START and STOP

conditions is determined by the master device and is

unlimited.

5.1.5 ACKNOWLEDGE

Each receiving device, when addressed, is obliged to

generate an acknowledge bit after the reception of

each byte. The master device must generate an extra

clock pulse which is associated with this acknowledge

bit.

The device that acknowledges has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable-low during the high

period of the acknowledge-related clock pulse. Setup

and hold times must be taken into account. During

reads, a master device must signal an end of data to

the slave by not generating an acknowledge bit on the

last byte that has been clocked out of the slave (NAK).

In this case, the slave (MCP3221) will release the bus

to allow the master device to generate the STOP

condition.

The MCP3221 supports a bidirectional, 2-wire bus and

data transmission protocol. The device that sends data

onto the bus is the transmitter and the device receiving

data is the receiver. The bus has to be controlled by a

master device which generates the serial clock (SCL),

controls the bus access and generates the START and

STOP conditions, while the MCP3221 works as a slave

device. Both master and slave devices can operate as

either transmitter or receiver, but the master device

determines which mode is activated.

FIGURE 5-1: Data Transfer Sequence on the Serial Bus.

SCL

SDA

(A) (B) (D) (D) (A)(C)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

MCP3221

5.2 Device Addressing

The address byte is the first byte received following the

START condition from the master device. The first part

of the control byte consists of a 4-bit device code, which

is set to 1001 for the MCP3221. The device code is fol-

lowed by three address bits: A2, A1 and A0. The default

address bits are 101. Contact the Microchip factory for

additional address bit options. The address bits allow

up to eight MCP3221 devices on the same bus and are

used to determine which device is accessed.

The eighth bit of the slave address determines if the

master device wants to read conversion data or write to

the MCP3221. When set to a ‘1’, a read operation is

selected. When set to a ‘0’, a write operation is

selected. There are no writable registers on the

MCP3221. Therefore, this bit must be set to a ’1’ in

order to initiate a conversion.

The MCP3221 is a slave device that is compatible with

the I2C 2-wire serial interface protocol. A hardware

connection diagram is shown in Figure 6-2. Communi-

cation is initiated by the microcontroller (master

device), which sends a START bit followed by the

address byte.

On completion of the conversion(s) performed by the

MCP3221, the microcontroller must send a STOP bit to

end communication.

The last bit in the device address byte is the R/W bit.

When this bit is a logic ‘1’, a conversion will be exe-

cuted. Setting this bit to logic ‘0’ will also result in an

“acknowledge” (ACK) from the MCP3221, with the

device then releasing the bus. This can be used for

device polling. Refer to Section 6.3 “Device Polling”,

“Device Polling”, for more information.

FIGURE 5-2: Device Addressing.

5.3 Executing a Conversion

This section will describe the details of communicating

with the MCP3221 device. Initiating the sample-and-

hold acquisition, reading the conversion data and

executing multiple conversions will be discussed.

5.3.1 INITIATING THE SAMPLE AND

HOLD

The acquisition and conversion of the input signal

begins with the falling edge of the R/W bit of the

address byte. At this point, the internal clock initiates

the sample, hold and conversion cycle, all of which are

internal to the ADC.

FIGURE 5-3: Initiating the Conversion,

Address Byte.

FIGURE 5-4: Initiating the Conversion,

Continuous Conversions.

START READ/WRITE

SLAVE ADDRESS R/W A

1001101

Address Bits(1)

Note 1: Contact Microchip for additional address bits.

Device Code

123456789

SCL

SDA 1 0 0 1 A2 A1 A0 R/W

ACK

Start

Bit

Address Byte

Address bits Device bits

tACQ + tCONV is

initiated here

SCL

SDA D3 D2 D2

ACK

Lower Data Byte (n)

tACQ + tCONV is

initiated here

D6 D5 D4 D0D7

ACK

17 18 19 20 21 22 23 24 25 26

MCP3221

The input signal will initially be sampled with the first

falling edge of the clock following the transmission of a

logic-high R/W bit. Additionally, with the rising edge of

the SCL, the ADC will transmit an acknowledge bit

(ACK = 0). The master must release the data bus dur-

ing this clock pulse to allow the MCP3221 to pull the

line low (refer to Figure 5-3).

For consecutive samples, sampling begins on the fall-

ing edge of the LSB of the conversion result, which is

two bytes long. Refer to Figure 5-6 a for timing diagram.

5.3.2 READING THE CONVERSION DATA

Once the MCP3221 acknowledges the address byte,

the device will transmit four ‘0’ bits followed by the upper

four data bits of the conversion. The master device will

then acknowledge this byte with an ACK = Low. With the

following 8 clock pulses, the MCP3221 will transmit the

lower eight data bits from the conversion. The master

then sends an ACK = high, indicating to the MCP3221

that no more data is requested. The master can then

send a stop bit to end the transmission.

FIGURE 5-5: Executing a Conversion.

5.3.3 CONSECUTIVE CONVERSIONS

For consecutive samples, sampling begins on the fall-

ing edge of the LSB of the conversion result. See

Figure 5-6 for timing.

FIGURE 5-6: Continuous Conversion.

SDA

tACQ + tCONV is

initiated here

Address Byte

Address bits

Device bits

1001AR

Upper Data Byte

0000

DDDA

Lower Data Byte

S P

11 10

12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

SCL

SDA

fSAMP = 22.3 ksps (fCLK = 400 kHz)

tACQ + tCONV is

initiated here

Address Byte

Address bits

Device bits

1 0 0 1 A2 A1 A0 R

Upper Data Byte (n)

Lower Data Byte (n)

tACQ + tCONV is

initiated here

0000

DDD

11 10 9

12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

SCL

MCP3221

6.0 APPLICATIONS INFORMATION

6.1 Driving the Analog Input

The MCP3221 has a single-ended analog input (AIN).

For proper conversion results, the voltage at the AIN

pin must be kept between VSS and VDD. If the converter

has no offset error, gain error, INL or DNL errors, and

the voltage level of AIN is equal to or less than

VSS + 1/2 LSB, the resultant code will be 000h. Addi-

tionally, if the voltage at AIN is equal to or greater than

VDD - 1.5 LSB, the output code will be FFFh.

The analog input model is shown in Figure 6-1. In this

diagram, the source impedance (RSS) adds to the inter-

nal sampling switch (RS) impedance, directly affecting

the time required to charge the capacitor (CSAMPLE).

Consequently, a larger source impedance increases

the offset error, gain error and integral linearity errors of

the conversion. Ideally, the impedance of the signal

source should be near zero. This is achievable with an

operational amplifier, such as the MCP6022, which has

a closed-loop output impedance of tens of ohms.

FIGURE 6-1: Analog Input Model, AIN.

6.2 Connecting to the I2C Bus

The I2C bus is an open-collector bus, requiring pull-up

resistors connected to the SDA and SCL lines. This

configuration is shown in Figure 6-2.

FIGURE 6-2: Pull-up Resistors on I2C

Bus.

The number of devices connected to the bus is limited

only by the maximum bus capacitance of 400 pF. A

possible configuration using multiple devices is shown

in Figure 6-3.

FIGURE 6-3: Multiple Devices on I2C™

Bus.

CPIN

RSS AIN

7pF

VT = 0.6V

VT = 0.6V ILEAKAGE

Sampling

Switch

SS RS = 1 kΩ

CSAMPLE

= DAC capacitance

VSS

VDD

= 20 pF

±1 nA

Legend

VA = signal source

RSS = source impedance

AIN = analog input pad

CPIN = analog input pin capacitance

VT= threshold voltage

ILEAKAGE = leakage current at the pin

due to various junctions

SS = sampling switch

RS= sampling switch resistor

CSAMPLE = sample/hold capacitance

PICmicro®

SDA

SCL

VDD

RPU

RPU is typically: 10 kΩ for fSCL = 100 kHz

2kΩ for fSCL = 400 kHz

MCP3221

Analog

Input

Signal

Microcontroller

AIN

SDA SCL

PIC16F876

Microcontroller

MCP3221

12-bit ADC

TC74

Temperature

Sensor

24LC01

EEPROM

MCP3221

6.3 Device Polling

In some instances, it may be necessary to test for

MCP3221 presence on the I2C bus without performing

a conversion. This operation is described in Figure 6-4.

Here we are setting the R/W bit in the address byte to

a zero. The MCP3221 will then acknowledge by pulling

SDA low during the ACK clock and then release the

bus back to the I2C master. A stop or repeated start bit

can then be issued from the master and I2C

communication can continue.

FIGURE 6-4: Device Polling.

6.4 Device Power and Layout

Considerations

6.4.1 POWERING THE MCP3221

VDD supplies the power to the device as well as the ref-

erence voltage. A bypass capacitor value of 0.1 µF is

recommended. Adding a 10 µF capacitor in parallel is

recommended to attenuate higher frequency noise

present in some systems.

FIGURE 6-5: Powering the MCP3221.

6.4.2 LAYOUT CONSIDERATIONS

When laying out a printed circuit board for use with

analog components, care should be taken to reduce

noise wherever possible. A bypass capacitor from VDD

to ground should always be used with this device and

should be placed as close as possible to the device pin.

A bypass capacitor value of 0.1 µF is recommended.

Digital and analog traces should be separated as much

as possible on the board, with no traces running

underneath the device or the bypass capacitor. Extra

precautions should be taken to keep traces with high-

frequency signals (such as clock lines) as far as

possible from analog traces.

Use of an analog ground plane is recommended in

order to keep the ground potential the same for all

devices on the board. Providing VDD connections to

devices in a “star” configuration can also reduce noise

by eliminating current return paths and associated

errors (Figure 6-6). For more information on layout tips

when using the MCP3221 or other ADC devices, refer

to AN688, “Layout Tips for 12-Bit A/D Converter

Applications”.

FIGURE 6-6: VDD traces arranged in a

‘Star’ configuration in order to reduce errors

caused by current return paths.

6.4.3 USING A REFERENCE FOR

SUPPLY

The MCP3221 uses VDD as both power and a refer-

ence. In some applications, it may be necessary to use

a stable reference to achieve the required accuracy.

Figure 6-7 shows an example using the MCP1541 as a

4.096V, 2% reference.

FIGURE 6-7: Stable Power and

Reference Configuration.

123456789

SCL

SDA 100

1A2 A1A0 0

ACK

Start

Bit

Address Byte

Address bits

Device bits R/W Start

Bit

MCP3221 response

VDD

AIN

SCL

SDA

Microcontroller

10 µF

MCP3221

0.1 µF

VDD

RPU

VDD

Connection

Device 1

Device 2

Device 3

Device 4

VDD

4.096V

Reference

1µF

0.1 µF

MCP1541 CL

AIN

Microcontroller

MCP3221

VDD

RPU

SCL

SDA

MCP3221

7.0 PACKAGING INFORMATION

7.1 Package Marking Information

*Standard device marking consists of Microchip part number, year code, week code, and traceability

code.

2 13

5-Pin SOT-23A (EIAJ SC-74) Device

cdef

Legend: 1 Part Number code + temperature range

2 Part Number code + temperature range

3 Year and work week

4 Lot ID

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line thus limiting the number of available characters

for customer specific information.

Part Number Address Option SOT-23

MCP3221A0T-I/OT 000 EE

MCP3221A1T-I/OT 001 EH

MCP3221A2T-I/OT 010 EB

MCP3221A3T-I/OT 011 EC

MCP3221A4T-I/OT 100 ED

MCP3221A5T-I/OT 101 S1 *

MCP3221A6T-I/OT 110 EF

MCP3221A7T-I/OT 111 EG

MCP3221A0T-E/OT 000 GE

MCP3221A1T-E/OT 001 GH

MCP3221A2T-E/OT 010 GB

MCP3221A3T-E/OT 011 GC

MCP3221A4T-E/OT 100 GD

MCP3221A5T-E/OT 101 GA *

MCP3221A6T-E/OT 110 GF

MCP3221A7T-E/OT 111 GG

* Default option. Contact Microchip Factory for other

address options.

MCP3221

5-Lead Plastic Small Outline Transistor (OT) (SOT23)

10501050

Mold Draft Angle Bottom

10501050

Mold Draft Angle Top

0.500.430.35.020.017.014BLead Width

0.200.150.09.008.006.004

Lead Thickness

10501050

Foot Angle

0.550.450.35.022.018.014LFoot Length

3.102.952.80.122.116.110DOverall Length

1.751.631.50.069.064.059E1Molded Package Width

3.002.802.60.118.110.102EOverall Width

0.150.080.00.006.003.000A1Standoff

1.301.100.90.051.043.035A2Molded Package Thickness

1.451.180.90.057.046.035AOverall Height

1.90.075

Outside lead pitch (basic)

0.95.038

Pitch

Number of Pins

MAXNOMMINMAXNOMMINDimension Limits

MILLIMETERSINCHES

Units

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.

Notes:

EIAJ Equivalent: SC-74A

Drawing No. C04-091

Controlling Parameter

Revised 09-12-05

MCP3221

NOTES:

MCP3221

APPENDIX A: REVISION HISTORY

Revision C (July 2006)

• Section 5.2 Device Address: Changed 4-bit

device code to “1001”. Changed three address

bits to “101”.

Revision B (May 2003)

• Numerous changes throughout document.

Revision A (November 2005)

• Original Release of this Document.

MCP3221

NOTES:

MCP3221

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: MCP3221T: 12-Bit 2-Wire Serial A/D Converter

(Tape and Reel)

Temperature Range: I = -40°C to +85°C

E= -40°C to +125°C

Address Options: XX A2 A1 A0

A0 = 0 0 0

A1 = 0 0 1

A2 = 0 1 0

A3 = 0 1 1

A4 = 1 0 0

A5 * = 1 0 1

A6 = 1 1 0

A7 = 1 1 1

* Default option. Contact Microchip factory for other

address options

Package: OT = SOT-23, 5-lead (Tape and Reel)

PART NO. XXX

Address Temperature

Range

Device

Examples:

a) MCP3221A0T-I/OT: Industrial, A0 Address,

Tape and Reel

b) MCP3221A1T-I/OT: Industrial, A1 Address,

Tape and Reel

c) MCP3221A2T-I/OT: Industrial, A2 Address,

Tape and Reel

d) MCP3221A3T-I/OT: Industrial, A3 Address,

Tape and Reel

e) MCP3221A4T-I/OT: Industrial, A4 Address,

Tape and Reel

f) MCP3221A5T-I/OT: Industrial, A5 Address,

Tape and Reel

g) MCP3221A6T-I/OT: Industrial, A6 Address,

Tape and Reel

h) MCP3221A7T-I/OT: Industrial, A7 Address,

Tape and Reel

a) MCP3221A0T-E/OT: Extended, A0 Address,

Tape and Reel

b) MCP3221A1T-E/OT: Extended, A1 Address,

Tape and Reel

c) MCP3221A2T-E/OT: Extended, A2 Address,

Tape and Reel

d) MCP3221A3T-E/OT: Extended, A3 Address,

Tape and Reel

e) MCP3221A4T-E/OT: Extended, A4 Address,

Tape and Reel

f) MCP3221A5T-E/OT: Extended, A5 Address,

Tape and Reel

g) MCP3221A6T-E/OT: Extended, A6 Address,

Tape and Reel

h) MCP3221A7T-IE/OT: Extended, A7 Address,

Tape and Reel

/XX

Package

Options

MCP3221

NOTES:

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

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Company are registered trademarks of Microchip Technology

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SQTP is a service mark of Microchip Technology Incorporated

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All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona, Gresham, Oregon and Mountain View, California. The

Company’s quality system processes and procedures are for its

PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

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82-2-558-5934

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-3910

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

WORLDWIDE SALES AND SERVICE

06/08/06