Never stop thinking.
Microcontrollers
Data Sheet, V 1.0D3, Mar. 2001
82C900
Standalone TwinCAN Controller
Editio n 2001-03
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 Münc he n, Ge rmany
© Infineon Technologies AG 2001.
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Microcontrollers
Data Sheet, V 1.0D3, Mar. 2001
Never stop thinking.
82C900
Standalone TwinCAN Controller
82C900
Preliminary
Revision History: 2001-03 V1.0D3
Previous Version: -
Page Subjects (major changes since last revision)
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Data Sheet 5 V 1.0D3, 2001-03
Preliminary
82C900Standalone TwinC AN Controller
82C900
Architectural Overview
The Standalone TwinCAN device provides several submodules to control the data flow
and to configure the peripheral function:
Features:
• Two interface channels are implemented for the communication with a host device:
– the Multiplexed Data/Address Bus can be used by an external CPU to read and
write the TwinCAN’s internal registers for initial configuration and control during
normal operation. The standard Infineon Bus Mode and the Motorola Bus Mode can
be handled.
– alternativel y, a Synchronous Seri al Channel (SSC) may be selected to re ad out the
initial TwinCAN’s register configuration from a serial EEPROM. The SSC can be
also used by an external control device (microcontroller, CPU, etc.) in order to
exchange control and status information.
• Both communication channels are based on byte transfers. In order to minimize the
communication o verhead, all inter nal 16 bit and 32 bit wide regi sters can be a ccessed
in Page Mode requiring only one address byte.
• Powerful initialization mechanism for all registers, the device can be configured via
EEPROM, based on CAN messages or by an external host device.
• Additional input/output functionality controlled by CAN messages. The transmission of
CAN messages can be triggered by input pins if the SSC is used for communication.
• The clock control unit can be supplied wi th an exter nal clock. Altern atively, an on-chip
oscillator may be used to generate a clock driving also an external device via an output
pin.
• Power Saving features have been implemented. A Sleep Mode and a Power-Down
Mode can be activated in order to mini mize the power consumption. The clock control
of the device can be controlled by CAN messages.
• The inter nal power sa ving status can be moni tored at output pi ns. This all ows flexible
and powerful system partitioning.
• The Device Contr oller unit generates the in ternal targ et address by concatenati ng the
contents of the PAGE register with the address delivered by the appropriate host read/
write access.
• The Interrupt Control unit passes the interrupt requests generated by the TwinCAN
controller to the external host via selectable output pins.
• The Port Control unit can be used to select the required functionality of the port pins
operating as communication channel, CAN node function monitor, interrupt request
line or general purpose I/O. Furthermore, the slew rate of pins configured for output
operation can be adjusted via this module.
82C900
Data Sheet 6 V 1.0D3, 2001-03
Preliminary
The TwinCAN module permits the connection and autonomous handling of two
independent CAN buses.
•Full-CAN module with 32 message objects, which can be independently assigned to
one of the two buses.
•The CAN protocol version 2.0B active with standard and extended identifiers can be
handled.
•The full CAN baud rate range is supported.
•Scalable FIFO mechanism for reception and transmission in order to improve the real-
time behavior of the system.
•Built-in automatic gateway functionality for data exchange between both CAN buses.
The gateway feature can also be used for automatic reply to received messages
(lifesign: “I got it!”).
•Powerful interrupt structure, permitting application-specific interrupt generation.
•Remote frames can be monitored.
•Enhanced acceptance filtering (an acceptance mask for each message object).
•A 16 bit frame count / timestamp is implemented for each message object.
•Analyzing mode (no dominant level will be sent) supported.
Figure 1 shows a block diagram of the 82C900 device architecture.
Figure 1 Standalone TwinCAN A rchitecture
Note: The CAN bus transceivers are not integrated and have to be connected externally.
Message
Object
Buffer
CAN
Node
A
CAN
Node
B
TwinCAN Control
Clock
control
SSC
Port
Control
Interrupt
Control
Device Control
4
8
2
2
2
2
OUT0, OUT1
TXDCA, TXDCB
RXDCA, RXDCB
MODE0, MODE1
P0..P7
CTRL0..CTRL3
2
XTAL1, XTAL2
2
RESET, RDY
data
addr
clk
int
CAN
data
82C900
Data Sheet 7 V 1.0D3, 2001-03
Preliminary
Application Fields
The Standalone TwinCAN device 82C900 can be used in application requiring one or
two indep endent CAN nodes. The bu ilt-in FIFO an d gateway featur es minimize the CPU
load for the message handling and lead to an improved real-time behavior. The access
to the internal registers can be handled via a parallel or a serial interface, adapted to a
large variety of applications. The interface selection is done via the two MODE pins,
which can be directly connected to the supply voltage or via pull-up/down resistors (of
about 10-47 kOhm). In all modes, the clock generation can be controlled either by the
82C900 device or by the system it is connected to.
Connection to a Host Device via the Parallel Interface
The 82C900 can be conn ected to a host de vice via a paral lel 8 bit mu ltiplexed i nterface.
Therefore, pin MODE0 has to be 0, whereas pin MODE1 selects, whether an Infineon-
(Intel-) compatible or an Motorola-compatible protocol is handled. In this mode, the
device can be easily used to extend the CAN capability of a system. The internal
registers can be accessed in pages of 256 bytes per page. An additional RDY output
indicates whe n the device is ready to be accessed. This sign al can be u sed to detect an
overload situa tion of the CAN device (too many host accesses to the Tw inCAN module).
One interrupt output line (OUT1) is always avai lable, a second one (OU T0) can be used
as clockout pin or as another interrupt output.
Figure 2 Host Connection via the Parallel Interface
Host
Parallel Interface
AD7..0 CTRL3..0 RDY OUTx
Interrupt
Control
Clock ControlTwinCAN Module
82C900
RXDCB,
TXDCB
RXDCA,
TXDCA
CAN Bus A
Transceiver Transceiver
CAN Bus B
82C900
Data Sheet 8 V 1.0D3, 2001-03
Preliminary
Connection to a Host Device via the Serial Interface
The second possibil ity to connect the 82C900 to a host device i s via the serial inter face.
This mode is selected if the pin MODE0=1 and MODE1=0.
The standard four-line SPI-compatible interface has been extended by a RDY signal,
which indicates that the serial interface is ready for the next access by the host.
The page size is reduced to 128 bytes per page, because the MSB of the address byte
contains a read/write indication. A special incremental access mode has been
implemented in order to reduce significantly the number of transferred bytes for
consecutive register accesses.
The 8 remaining I/O pins from the unused parallel interface are controlled by a port
control logic and can be used as I/O extensio n. These lines can be read or written by the
serial channel or by CAN messages. Furthermore, these lines can be programmed as
additional interrupt output lines in order to increase the number of independent
interrupts.
The output lines OUT0 and OUT1 have the same functionality in the case a parallel
interface or a serial interface connects the 82C900 to a host device.
Figure 3 Host Connection via the Serial Interface
Host
Serial Interface
CTRL3..0 RDY OUTx
Interrupt
Control
Clock ControlTwinCAN Module
82C900
RXDCB,
TXDCB
RXDCA,
TXDCA
CAN Bus A
Transceiver Transceiver
CAN Bus B
Port Control
I/O7..0
Input/Output
Extension
82C900
Data Sheet 9 V 1.0D3, 2001-03
Preliminary
Operation without Host Device
The standalone functionality comprises an additional mode, leading to a low-cost
system, which d oes n ot r equ ire any externa l host devi ce. Thi s m ode can be selected b y
setting the input pins MODE0 and MODE1 to 1. The best solution are pull-up resistors
(about 10 to 47 kOhm). After the reset phase, the MODE pins can be enabled to control
the power-down functionality of the entire connected system by indicating the internal
status of two clock control bits. The power-down functionality can run completely via
CAN messages (sleep and wake-up by CAN messages).
The initialization sequence is automatically started from an external non-volatile
memory, a serial (SPI-compatible) EEPROM. The data, which is read out from the
EEPROM permits the user to initialize the registers with the desired values in a freely
progra mmable ord er. Changes in the application on ly lead to modi fied data stor ed in the
non-volatile mem ory.
For example, the bit timing, one message object and some control registers are set up
via the data read from the EEPROM. Then, the initialization can continue via CAN
messages.
The 8 remaining I/O pins from the unused parallel interface are controlled by a port
control logic and can be used as I/O extension. These lines can be read or written by
CAN messages.
Figure 4 Connection to a Serial EEPROM
Serial
EEPROM
Serial Interface
CTRL3..0
Device
Control
Clock ControlTwinCAN Module
82C900
RXDCB,
TXDCB
RXDCA,
TXDCA
CAN Bu s A
Transceiver Transceiver
CAN Bus B
Por t Control
I/O7..0
Input/Output
extension Power-Down
Indication
82C900
Data Sheet 10 V 1.0D3, 2001-03
Preliminary
Pin Configuration
Figure 5 82C900 Pin Conf iguration
Pin Definition
Table 1 Pin Definitions and Functions
Symbol Pin
Number I/O 1) Function
RXDCA 1IReceiver Input of CAN Node A
Receiver input of CAN node A, connected to the
associated CAN bus via a transceiver device.
TXDCA 2OTransmitter Output of CAN Node A
TXDCA delivers the output signal of CAN node A. The
signal level has to be adapted to the physical layer of t he
CAN bus via a transceiver device.
RXDCB 28 I Receiver Input of CAN Node B
Receiver input of CAN node B, connected to the
associated CAN bus via a transceiver device.
RXDCA RXDCB
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TXDCA TXDCB
RESET
RDY
CTRL0 CTRL1
CTRL2 CTRL3
P0
P2
P4
P6
P1
P3
P5
P7
OUT0 OUT1
MODE0
MODE1
XTAL1
XTAL2
VDD VDD
VSS
VSS
82C900
Data Sheet 11 V 1.0D3, 2001-03
Preliminary
TXDCB 27 O Transmitter Output of CAN Node B
TXDCB delivers the output signal of CAN node B. The
signal level has to be adapted to the physical layer of t he
CAN bus via a transceiver device.
RESET 3IReset
A low level on this pin resets the device.
RDY 24 O Ready Signal
Output signal indicating that the standalone device is
ready for data transfer.
CTRL0 9 I/O Control 0
MODE0=0: Chip Select CS
Input used as Chip Select for the device.
MODE0=1: Select Slave SLS
MODE1=0: Input used to enable SSC action when
active.
MODE1=1: Output used to select a slave when active.
CTRL1 20 I/O Control 1
MODE0=0: Address Latch Enable or Address
Strobe, ALE or AS
Input used for latching the address from the multiplexed
address/data bus.
MODE0=1: Serial Channel Clock SCLK
Input/output of the SSC clock.
MODE1=0: Clock input
MODE1=1: Clock output
CTRL2 10 I/O Control 2
MODE0=0: Write or Read/Write, WR or R/ W
MODE1=0: Input used as write signal WR
MODE1=1: R/W=0: Data transfer direction = write
MODE1=1: R/W=1: Data transfer direction = read
MODE0=1: Master Transmit Slave Receive MTSR
MODE1=0: Serial data input
MODE1=1: Serial data output
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin
Number I/O 1) Function
82C900
Data Sheet 12 V 1.0D3, 2001-03
Preliminary
CTRL3 19 I/O Control 3
MODE0=0: Read or Read/Write Enable, RD or E
MODE1=0: Input used as read signal RD
MODE1=0: Read/write enable
MODE0=1: Master Receive Slave Transmit MRST
MODE1=0: Serial data output
MODE1=1: Serial data input
P7
P6
P5
P4
P3
P2
P1
P0
15
14
16
13
17
12
18
11
I/O Parallel Bus
MODE0=0: 8-bit Address/ Data Bus AD[7:0]
Address and data bus AD7..AD0 in 8-bit multiplexed
modes.
MODE0=1: 8-bit parallel I/O Port IO[7:0]
Programmable 8-bit general purpose I/O-port IO7..IO0.
OUT0 2) 6OOutput Line 0
The logic 0 leve l at this pi n indicates an i nterrupt r equest
to the external host device if selected as interrupt output.
The interrupt line will be active if there is a new pending
interrupt request for interrupt node 0 (according to
register GLOBCTR).
If selected as clock output, the functionality is defined by
register CLKCTR.
OUT1 23 O,
open
drain
Output Line 1
The logic 0 leve l at this pi n indicates an i nterrupt r equest
to the external host device.
The interrupt line will be active if there is a new pending
interrupt request for interrupt node 1 (according to
register GLOBCTR).
MODE0 3) 26 I/O,
open
drain
Interface Selection
Pin MODE0 selects whe ther the on- chi p SSC o r an 8-bi t
multiplexed bus are u sed to access th e TwinCAN devi ce.
MODE0=0: 8-bit multiplexed address/data bus
MODE0=1: on-chip SSC
After regi stering the initial state of MODE0 with the rising
edge of the reset signal, the respective pin can be used
as additional general pur pose or special function I/O line
according register IOMODE4.
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin
Number I/O 1) Function
82C900
Data Sheet 13 V 1.0D3, 2001-03
Preliminary
MODE1 25 I/O,
open
drain
Interface Mode Selection
Pin MODE1 determines the access mode of the host
device.
MODE0=0: 8-bit multiplexed bus
MODE1=0: Infineon / Intel mode, (RD, WR)
MODE1=1: Motorola mode, (R/W, E)
MODE0=1: On-chip SSC
MODE1=0: SSC is slave, host device is master
MODE1=1: SSC is master, external serial
EEPROM is slave
After regi stering the initial state of MODE1 with the rising
edge of the reset signal, the respective pin can be used
as additional general pur pose or special function I/O line
according register IOMODE4.
XTAL1 4IXTAL1
Input of the inverting oscillator amplifier and input to the
internal clock generation circuit.
When the 82C900 device is provided with an external
clock, XTAL1 should be driven while XTAL2 is left
unconnected.
Minimum and m aximum high and low pulse w idth as well
as rise/fall times specified i n the AC characteristi cs must
be respected.
XTAL2 5OXTAL2
Output of the inverting oscillator amplifier.
VSS 21, 8 0V Ground, both pins must be connected.
VDD 22, 7 +5V Power Supply, both pins must be connected.
1) The slew rate of the outp ut pi ns O UT0, OUT1, C TRL1.. 3, P0 ..P7, TXDC A an d TX DCB ca n b e def ined b y t he
bit fields SLR0..3 in register GLOBCTR.
2) After reset, this pin is configured as clock out put, see register CLKCTR.
3) The initial logic state on pins MODE0 and MODE1 is registered with the rising edge of the RESET input.
Afterwards, both pins can be used as additional I/O lines, according to functionality specified in register
IOMODE4.
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin
Number I/O 1) Function
82C900
Data Sheet 14 V 1.0D3, 2001-03
Preliminary
Register Address Map
All Shell and Kernel registers, implemented for controlling the 82C900 device, are
summarized in Table 0-1; detailed information about each register is provided in the
respective module description chapter.
Note: Accesses to addresses which are not specified as registers in the following
register address map are forbidden.
Table 0-1 Summary of Registers
Register Name Register
Symbol Address Reset Value
1)
Standalone Shell Registers
Global Device Control Register GLOBCTR 0010HA0 00H
Interrupt Control Register INTCTR 0012H00 00H
CAN Clock Control Register CLKCTR 0014H00 24H
Input/Output Mode Register 0 IOMODE0 0020H00 00H
Input/Output Mode Register 2 IOMODE2 0022H00 00H
Input/Output Mode Register 4 IOMODE4 0024H00 00H
Input Value Register (8-bit port) INREG 0026H00 00H
Output Value Register (8-bit port) OUTREG 0028H00 00H
CAN Powe r-Down Control Register CANPWD 0040H00 00H
CAN Input/Output Control Register CANIO 0042H00 00H
CAN Initia lization Control Register CANINIT 0044H00 00H
Paging Mode Register
(accessible in all pages) PAGE XX7CH00 00H
CAN RAM Address Buffer Register CAB 007EH00 00H
Initialization Control Register INITCTR 02F0H0103 0000H
TwinCAN Kernel, Common Registers
CAN Receive Interrupt Pending Register RXIPND 0284H0000 0000H
CAN Transmit Interrupt Pending Register TXIPND 0288H0000 0000H
TwinCAN Kernel, Node A Registers
CAN Node A Control Register ACR 0200H0000 0001H
CAN Node A Status Register ASR 0204H0000 0000H
CAN Node A Interrupt Pending Register AIR 0208H0000 0000H
CAN Node A Bit Timing Register ABTR 020CH0000 0000H
82C900
Data Sheet 15 V 1.0D3, 2001-03
Preliminary
CAN Node A Global Int. Node Pointer Reg. AGINP 0210H0000 0000H
CAN Node A Frame Counter Register AFCR 0214H0000 0000H
CAN Node A INTID Mask Register 0 AIMR0 0218H0000 0000H
CAN Node A INTID Mask Register 4 AIMR4 021CH0000 0000H
CAN Node A Error Counter Register AECNT 0220H0060 0000H
TwinCAN Kernel, Node B Registers
CAN Node B Control Register BCR 0240H0000 0001H
CAN Node B Status Register BSR 0244H0000 0000H
CAN Node B Interrupt Pending Register BIR 0248H0000 0000H
CAN Node B Bit Timing Register BBTR 024CH0000 0000H
CAN Node B Global Int. Node Pointer Reg. BGINP 0250H0000 0000H
CAN Node B Frame Counter Register BFCR 0254H0000 0000H
CAN Node B INTID Mask Register 0 BIMR0 0258H0000 0000H
CAN Node B INTID Mask Register 4 BIMR4 025CH0000 0000H
CAN Node B Error Counter Register BECNT 0260H0060 0000H
TwinCAN Kernel, Message Object Registers
CAN Message Object n Data Register 0 MSGDRn0 0300H
+ n*20H
0000 0000H
CAN Message Object n Data Register 4 MSGDRn4 0304H
+ n*20H
0000 0000H
CAN Message Object n Arbitration Register MSGARn 0308H
+ n*20H
0000 0000H
CAN Message Object n Acceptance Mask
Register MSGAMRn 030CH
+ n*20H
FFFF FFFFH
CAN Message Object n Message Control
Register MSGCTRn 0310H
+ n*20H
0000 5555H
CAN Message Object n Message
Configuration Register MSGCFGn 0314H
+ n*20H
0000 0000H
CAN Message Object n Gateway / FIFO
Control Register MSGFGCRn 0318H
+ n*20H
0000 0000H
1) Registers with 32-bit reset values are located in the CAN RAM and have to be accessed accordingly. The
other registers are standard SFRs, which have 16 -bit reset values.
Table 0-1 Summary of Registers (cont’d)
Register Name Register
Symbol Address Reset Value
1)
82C900
Data Sheet 16 V 1.0D3, 2001-03
Preliminary
Absolute Maximum Ratings
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN>VDD or VIN<VSS) the
voltage on VDD pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Table 2 Absolute Maximum Rating Parameters
Parameter Symbol Limit Values Unit Notes
min. max.
Storage temperature TST -65 150 °C
Voltage on VDD pins with
respect to ground (VSS)VDD -0.5 6.5 V
Voltage on any pin with
respect to ground (VSS)VIN -0.5 VDD+0.5 V
Input current on any pin
during overload condition -10 10 mA
Absolute sum of all input
currents during overload
condition
|100| mA
Power dissipation PDISS 480 mW
82C900
Data Sheet 17 V 1.0D3, 2001-03
Preliminary
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the device. All parameters, specified in the following sections, refer to the
normal operating conditions, unless otherwise noticed. The timings refer to the fast edge
mode.
Table 3 Operating Co nd i tion Pa rameter s
Parameter Symbol Limit Values Unit Notes
min. max.
Standard
digital supply voltage VDD 4.5 5.5 V Active mode,
fmax = 25 MHz
2.5 1)
1) Output voltages and output currents will be reduced when VDD leaves the range defined for active mode. The
clock frequency has to be reduced to operate with a voltage supply below 4.5V.
5.5 V Power-Down mode
Digital ground voltage VSS 0 V Reference voltage
Overload current IOV -±5 mA Per pin 2) 3)
2) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range (i.e. VOV >VDD+0.5V or VOV <VSS-0.5V). The absolute sum of input overload
currents on all port pins may not exceed 50 mA . The supply volt age must remain within the specified limits.
3) Not 100% tested, guaranteed by desig n characteriza tion
Absolute sum of overload
currents Σ|IOV|- 50 mA
4)
4) Not 100% tested, guaranteed by desig n characteriza tion.
External Load
Capacitance CL- |100| pF
Ambient temperature TA-40 125 °C SAK 82C900
82C900
Data Sheet 18 V 1.0D3, 2001-03
Preliminary
DC Characteristics
Operating Conditions apply.
Table 4 DC Characteristics under Normal Operation Conditions
Parameter Symbol Limit Values Unit Test Condition
min. max.
Input low voltage
(XTAL1) VIL – 0.5 0.3 VDD V–
Input high voltage
(XTAL1) VIH 0.7 VDD VDD +
0.5 V–
Input low voltage
(other pins) VIL – 0.5 0.2 VDD
– 0.1 V–
Input high voltage
(other pins) VIH 0.2 VDD
+ 0.9 VDD +
0.5 V–
Output low voltage 1)
(P0..P7)
1) The sum of | IOHP |, IOLP must not exceed 20mA.
VOLP –0.45 V IOLP = 5 mA
Output high voltage 1)
(P0..P7) VOHP 2.4 –VIOHP = -5 mA
0.9 VDD –VIOHP = -0.5 mA
Output low vo ltage
(other pins) VOL –0.45 V IOL = 2.4 mA
Output high voltage 2)
(other pins)
2) This specif ication is no t valid for outp uts which are swi tched to op en drain mode. In this case the res pective
output will float and the voltage result s from the external circuitr y.
VOH 2.4 –VIOH = -2.4 mA
0.9 VDD –VIOH = -0.5 mA
Input leakage current IOZ –±500 nA 0.45V < VIN < VDD
RESET inactive current 3)
3) These parameters describe the RESET pull-up, which equals a resistance of ca. 50 to 250 KΩ.
IRSTH 4)
4) The maximum curre nt may be drawn while the respect ive signal line remains inac tive.
–-10 µAVIN = VIH
RESET active current IRSTL 5)
5) The minimum current must be drawn in order to drive the respective signal line active.
-100 –µAVIN = VIL
XTAL1 input current IIL –±20 µA0 V < VIN < VDD
Pin capacitance 6)
(digital inputs/outputs)
6) Not 100% tested, guaranteed by desig n characteriza tion.
CIO –10 pF f = 1 MHz
TA = 25 °C
82C900
Data Sheet 19 V 1.0D3, 2001-03
Preliminary
Power Cons um ption
Operating Conditions apply.
Table 5 Power Consumption
Parameter Symbol Limit Values Unit Test Condition
min. max.
Power supply current (5V active)
with all elements active IDD5 –80 mA RESET = VIH
fCAN = 25 MH z 1)
1) The supply current is a function of the operating frequency. These parameters are tested at VDDmax and
maximum CPU clock with all out puts disconnected and all inputs at VIL or VIH.
The oscilla to r also contri bute s to the to ta l supply curre nt . The giv en val ues refer to the worst case. For lo wer
oscillat or frequencies the respective supply current can be re duced accordingly.
Sleep mode supply current (5V)
(oscillator running, clock gated off) IIDX5 2)
2) This parameter is determined mainly by the current consumed by the oscillator. This current, however, is
influe nced by the ex ternal oscillator ci rcuitry (crystal, capacitors). T he values give n refer to a typical circui try
and may change in case of a not optimized external oscillator circuitry.
–1.5 mA RESET = VIH
fCAN = 25 MHz
Power-down mode supply current
(5V) (oscillator stopped) IIDO5 –10 µA RESET = VIH
82C900
Data Sheet 20 V 1.0D3, 2001-03
Preliminary
AC Characteristics
Operating Conditions apply.
Assuming a maximum access rate from an external host to the CAN RAM via the
communication interface (worst case, parallel interface), the CAN protocol can still be
handled on both nodes with 1 Mbps if the clock frequency fCAN is 24 MHz. For additiona l
data handling features (FIFO, gateway, etc.), a higher frequency should be used, the
access rate to the device has to be reduced or a lower baud rate has to be selected.
Under worst case access conditions and CAN traffic, a baud rate of 500 kbps for each
node can be achieved with full data handling functionality with fCAN=24 MHz.
CAN input delay, output delay: typ. 15 ns
Table 6 External Clock Drive XTAL1
Parameter Symbol Direct Drive (1:1) Unit
min. max.
Oscillator period 1)
1) The clock input signal mu st reach the defined lev els VIL and VIH.
TCAN 40 –ns
High time 10 –ns
Low time 15 –ns
82C900
Data Sheet 21 V 1.0D3, 2001-03
Preliminary
8-Bit Multiplexed Bus
Infineon/ Intel Compatibility Mode
The bus access is internally fully synchronized, asynchronous accesses are supported.
Figure 6 Timing of Multiplexed Address/Data bus with MODE1 = 0
ALE
AD7-0
WR
CS
t LHLL
ALE
A7-0
t LLAX
t AVLL
t RLDV t RHDZ
t RLRH
AD7-0
RD
CS
t LLCL
t LLRL
data out
Read Timi ng
Write Timi ng t LHLL
A7-0
t LLAX
t AVLL
t WLDS t WHDZ
t WLWH
t LLCL t WHLH
data in
t WHCH
t LLWL
t RLLH
82C900
Data Sheet 22 V 1.0D3, 2001-03
Preliminary
Operating Conditions apply.
Parameter Symbol Limit Values Unit
min. max.
Address valid to ALE low t AVLL 5–ns
Address hold after ALE low t LLAX 10 –ns
ALE high time t LHLL 10 –ns
ALE low to RD lo w t LLRL 10 –ns
ALE low to WR low t LLWL 10 –ns
ALE low to CS low t LLCL 10 –ns
Data setup to WR high t WLDS 10 –ns
Input data hold after WR high t WHDZ 10 –ns
WR pulse width t WLWH 1.5 TCAN –ns
WR high to next ALE high
(if the next access targets the device) t WHLH 10 TCAN –ns
WR high to next ALE high
(if the next access doesn’t target the
device)
t WHLH 4 TCAN +15 –ns
WR high to CS high t WHCH 0–ns
RD pulse width (short read) t RLRH 1.5 TCAN –ns
RD pulse width (long read) t RLRH 8 TCAN + 25 –ns
RD low to data valid (short read) t RLDV –25 ns
RD low to data valid (long read) t RLDV –25 + 8 TCAN ns
RD low to next ALE high (short read) t RLLH 8 TCAN –ns
RD low to next ALE high (long read) t RLLH 25 –ns
Data float after RD hig h t RHDZ –25 ns
82C900
Data Sheet 23 V 1.0D3, 2001-03
Preliminary
8-Bit Multiplexed Bus
Motorola Compatibility Mode
The bus access is internally fully synchron ized, asynchronous accesses are supported.
Figure 7 Timing of Multiplexed Address/Data bus with MODE1 = 1
t SHSL
AS t SLAX
t AVSL
t EHDW t ELDZ
t
EHEL
E
R/W
t CLSL
t SLEH
t RSEH
CS
t ELCH
Read Timing
Write Timing
A7-0
AD7-0 data out
t EHSH
t SHSL
AS t SLAX
t AVSL t ELDS t ELD H
t
EHEL
E
R/W
t CLSL
t SLEH
t RSEH
CS
t ELCH
A7-0
AD7-0 data in
t ELSH
82C900
Data Sheet 24 V 1.0D3, 2001-03
Preliminary
Operating Conditions apply.
Parameter Symbol Limit Values Unit
min. max.
Address valid to AS low t AVSL 5–ns
Address hold after AS low t SLAX 10 –ns
Data float after E low t ELDZ –25 ns
E high to data valid output t EHDV –25 ns
Input data setup to E low t ELDS 10 –ns
Input data hold after E low t ELDH 10 –ns
E high time t EHEL 1.5 TCAN –ns
AS high time t SHSL 10 –ns
Setup time of R/W to E high t RSEH 0–ns
AS low to E high t SLEH 10 –ns
CS low to E high t CLSL 0–ns
E low to CS high t ELCH 0–ns
E low to next AS high (for write)
(if the next access targets the device) t ELSH 10 TCAN –ns
E low to next AS high (for write)
(if the next access doesn’t target the
device)
t ELSH 4 TCAN + 15 –ns
E high to next AS high (for read) t EHSH 8 TCAN –ns
82C900
Data Sheet 25 V 1.0D3, 2001-03
Preliminary
Timings of the SSC
In the case that the SSC is used in slave mode without the RDY signal, the following
timings have to be respected:
Note: The RDY signal can be used for a handshake to access to the device.
Furthermore, this signal indicates SSC error conditions (see baud rate error
detection). Accesses to the device during an SSC error condition can not be
correctly taken into account and might lead to errors.
Parameter Min. Time
(access to
TwinCAN
registers)
Min. Time
(access to
standalone
registers)
Units
First activation of SLS
after end of reset 1100 1100 TCAN
SLS active after SLS inactive
(to start a new communication cycle) 44T
CAN
SLS active before SCLK active
in order to transfer the address byte 22T
CAN
SLS inactive after SLS active
without transfer of data 22T
CAN
Time after the address transfer
to the first data byte transfer 5 (write)
14 (read) 5 (write)
11 (read) TCAN
Time between two byte transfers
(SCLK active to SCLK active) 5 (write)
14 (read) 5 (write)
11 (read) TCAN
Time to SLS inactive after last byte
transfer 11 (write)
1 (read) 6 (write)
1 (read) TCAN
82C900
Data Sheet 26 V 1.0D3, 2001-03
Preliminary
Package
The 82C900 device is available in a 28-pin P-DSO package. Table 1 contains a
functional description of each pin.
Figure 8 P-DSO-28-1 Package
82C900
Data Sheet 27 V 1.0D3, 2001-03
Preliminary
((28))
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