SY88149HL
3.3V 1.25Gbps Burst-Mode Limiting
A mplifier with Ultra-Fast Signal Assert
Timing
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
June 2010
M9999-061110-I
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY88149HL is a high-sensitivity, burst-mode capable
limiting post amplifier designed for Optical Line Terminal
(OLT) receiver applications. The SY88149HL satisfies the
strict timing restrictions of the GPON standards by
providing ultra-fast Loss-of-Signal (LOS) or Signal-Detect
(SD) output. Auto Reset and Manual Reset options are
provided to control LOS/SD output timing. For increased
flexibility, this device also includes an option to select
between LOS or SD output. The device can be connected
to burst-mode capable transimpedance amplifiers (TIAs)
using AC or DC coupling.
The SY88149HL gener ates a high-ga in LOS or SD LVTTL
output. A programmable LOS/SD level pin (LOS/SDLVL)
sets the sensitivity of the input amplitude detection. This
device als o of fer s the o ption t o cho ose b etween a Loss -of-
Signal (LOS) and a Signal-Detect (SD) output from the
LOS/SD pin based the LOS/SDSEL pin setting. To select
SD output, lea ve LOS/SDSEL pin open or connect to Vcc;
to select LOS output, tie LOS/SDSEL-to-ground. If the
input signal amplitude falls below the threshold set by
LOS/SDLVL, LO S will as sert high (or SD will de-ass ert low).
Once the input signal rises above the threshold set by
LOS/SDLVL, LOS will de-assert low (or SD output will
assert high). T he SY88 149 H L also features a JAM fu nction
which, when active, disables the LVPECL outputs. JAM is
active LOW when SD is selected and active HIGH when
LOS is selected. The LOS/SD output should be fed back to
the JAM input to maintain output stability under an invalid
signal condition. Typically, 3dB SD hysteresis is provided
to prevent chattering.
The SY88149HL operates from a single +3.3V power
supply over temperatures ranging from –40oC to +85oC.
With its wide bandwidth and high gain, signals up to
1.25Gbps and as small as 4mVpp can be amplified to
drive devices with LVPECL inputs.
All support documentation can be found on Micrel’s web
site at: www.micrel.com.
Features
• Single 3.3V power supply
• <5ns SD assert (LOS de-assert) time
• Option to AUTORESET or Manual RESET LOS output
to HIGH and SD output to LOW
• Option to select LOS or SD output
• Up to 1.25Gbps operation
• Low-noise differential LVPECL data outputs
• 4mVpp input sensitivity
• High sensitivity LOS/SD detect
• Ultra fast LVTTL LOS/SD output
• Squelching function to disable output
• Programmable LOS/SD level set (LOS/SDLVL)
• Available in a 16-pin (3mmx 3mm) QFN package
Applications
• GE-PON/GPON/EPON OLT
• Gigabit Ether net
• Fibre Channel
• OC-3/12/24 SONET/SDH
• High-gain line driver and line receiver
• Low-gain TIA interface
Markets
• FTTH/FTTP
• Datacom/Telecom
• Optical transceiver
Micrel, Inc.
SY88149HL
June 2010 2 M9999-061110-I
hbwhelp@micrel.com or (408) 955-1690
Ordering Information
Part Number Package
Type Operating
Range Package Marking Lead
Finish
SY88149HLMG QFN-16 Industrial 149H with
Pb-Free bar-line indicator NiPdAu
Pb-Free
SY88149HLMGTR
(1)
QFN-16 Industrial 149H with
Pb-Free bar-line ind icat or NiPdAu
Pb-Free
Pin Configuration
16-Pin QFN
Truth Tables
LOS/SDSEL Function LOS/SD Output (JAM Input) OUTPUTS
High SD High Enabled
High SD Low Disabled
Low LOS Low Enabled
Low LOS High Disabled
Micrel, Inc.
SY88149HL
June 2010 3 M9999-061110-I
hbwhelp@micrel.com or (408) 955-1690
Pin Description
Pin Number Pin Name Pin Function
1, 4 DIN, /DIN Data Inputs. If AC-Coupled, terminate each pin to Vref with 50Ω.
2 VREF Reference Voltage Output. Typically Vcc – 1.3V.
3,11,8 GND Device Ground. Exposed pad must be soldered (or equivalent) to the same potential as
ground pins.
10 /AUTORESET LVTTL Input. This pin is internally connected to a 25kΩ pull-up resistor and defaults to
HIGH. When this pin is LOW or tied to ground, the /AUTORESET function is enabled and
SD de-asserts or LOS asserts within 100ns (typical) after the last high to low transition of
the burst inpu t. When this pin is left floating or not connected, the AUTORESET function
is disabled and the SD de-assert or LOS a sser t mus t be forced by us ing the manual
RESET function.
5,16 VCC Positive power supply. Bypass with 0.1uF | | 0.01uF low ESR capacitors. 0.01uF
capacitors should be as close as possible to VCC pins.
6 RESET LVTTL Input. Apply a high-level signal (>2V) to this pin to discharge the time constant and
reset the signal de-assert time or LOS assert time within 5ns. RESET defaults to Low if
left floating. If the /AUTORESET function is not used, this RESET function needs to be
used to quickly de-as sert the SD or assert LOS. Note that this input is internally
connected to a 25kΩ pull-up resistor.
7 LOS/SD LVTTL Output. Signal-Detect (SD) asserts high when the data input amplitude rises
above the threshold set by SDLVL. Conversely, Loss-of-Signal (LOS) de-asserts low when
the data input amplitude rises above the threshold set by LOSLVL.
12, 9 DOUT, /DOUT LVPECL Outputs. When JAM disables the device, output DOUT is forced to logic LOW
and output /DOUT is forced to logic HIGH.
13 LOS/SDSEL LVTTL Input. Connect to VCC or leave open to select SD; set l ow or connect-to-GND to
select LOS. This pin also controls the LOS/SD output and po lar ity of the JAM function.
When SD is selected, JAM is active LOW and LOS/SD (pin 7) operates as signal detect.
Conversely, when LOS is selected, JAM is active HIGH and LOS/SD operates as los s-of-
signal. Note that this input is internally connected to a 25Ω pull-down resistor
14 LOS/SDLVL Voltage Input. Sets the Loss of Signal/Signal Detect Level. A resistor from this pin to VCC
sets the threshold for the data input amplitude at which LOS/SD will be asserted.
15 JAM LVTTL Input. JAM acts as a squelch function w hich can disa ble the LVPEC L out puts .
The polarity of the input that triggers an active JAM depends upon LOS/SDSEL status.
When LOS is selected, this pin is active HIGH. When SD is selected, this pin is active
LOW. To create a squelch function, connect JAM to LOS/SD output. When JAM disables
the device, output Q is forced to logic LOW and output /Q is forced to logic HIGH. Note
that this input is internally connected to a 25kΩ pull-up resistor .
Micrel, Inc.
SY88149HL
June 2010 4 M9999-061110-I
hbwhelp@micrel.com or (408) 955-1690
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ....................................... 0V to +4.0V
Input Voltage (DIN, /DIN) ....................................... 0 to VCC
Output Current (IOUT)
Continuous ........................................................ ±50mA
Surge .............................................................. ±100mA
TTL Inputs Voltage ................................................. 0 to VCC
VREF Current .......................................... -800μA to +500μA
LOS/SDLVL Voltage ............................................VREF to VCC
Lead Temperature (soldering, 20sec.) ..................... 260°C
Storage Temperature (Ts) ....................... –65°C to +150°C
Operating Ratings(2)
Supply Voltage (VCC)................................. +3.0V to +3.6V
Ambient Temperature (TA) ....................... –40°C to +85°C
Junction Temperature (TJ) ..................... –40°C to +125°C
Junction Thermal Resistance(3)
QFN (θJA) Still-air ............................................. 60°C/W
QFN (ΨJB) Junction-to-board ........................... 38°C/W
DC Electrical Characteristics
VCC = 3.0 to 3.6V; TA = –40°C to +85°C, typical values at VCC = 3.3V, TA = 25°C.
Symbol Parameter Condition Min Typ Max Units
ICC Power Supply Current No output load 57 78 mA
LOS/SDLVL LOS/SDLVL Voltage VREF VCC V
VOH LVPECL Output HIGH Voltage 50Ω to VCC-2V VCC-1.085 VCC-0.955 VCC-0.880 V
VOL LVPECL Output LOW Voltage 50Ω to VCC-2V VCC-1.830 VCC-1.705 VCC-1.555 V
IOFFSET Input Offset Voltage 1 mV
VIHCMR Common Mode Range GND+2.0 VCC V
VREF Reference Voltage VCC-1.48 VCC-1.32 VCC-1.16 V
LVTTL DC Electrical Characteristics
VCC = 3.0 to 3.6V; TA = –40°C to +85°C, typical values at VCC = 3.3V, TA = 25°C.
Symbol Parameter Condition Min Typ Max Units
VIH TTL Input HIGH Voltage 2.0 V
VIL TTL Input LO W Voltage 0.8 V
IIH TTL Input HIGH Current
(/AUTORESET, JAM, LOS/SDSEL) VIN = 2.7V
VIN = VCC 20
100 µA
µA
IIL TTL Input LO W Current
(/AUTORESET, JAM, LOS/SDSEL) VIN = 0.5V -0.3 mA
IIH TTL Input HIGH Current (RESET) VIN = 2.7V
VIN = VCC 200
300 µA
µA
IIL TTL Input LOW Current (RESET) VIN = 0.5V -0.05 mA
VOL TTL Output LOW Level IOL = +20mA 0.5 V
Notes:
1. Permanent device dam age may occur if absolute maximum ratings are exceeded. This is a stress rating only and funct i onal operati on is not impli ed
at conditions other than thos e detailed in the operati onal sections of this data sheet. E xposure to absolute maximum rating c onditions
for extended periods may affect device reliabil ity.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Therm al perform ance ass umes the use of a 4-layer PCB. Exposed pad must be soldered (or equivalent) to the device’s most negative potenti al on
the PCB.
Micrel, Inc.
SY88149HL
June 2010 5 M9999-061110-I
hbwhelp@micrel.com or (408) 955-1690
AC Elect rical Chara cteristics
VCC = 3.0V to 3.6V; RLOAD = 50Ω to VCC–2V; TA = –40°C to +85°C.
Symbol Parameter Condition Min Typ Max Units
tr, tf Output Rise/Fall Time
(20% to 80%) Note 4 260 ps
tJAM_LH JAM Low to High Propagation Time Note 12 5 ns
tJAM_HL JAM High to Low Propagation Time Note 13 2 ns
tAUTORESET SD de-assert or LOS assert with Auto
Reset enabled .
75 100 150 ns
tRESET RESET time constant Note 5 5 ns
tON SD Assert Time/LOS De-assert time Note 9 5 ns
tJITTER Deterministic
Random Note 6
Note 7 15
5 psPP
psRMS
VID Differential Input Voltage Swing Figure 1 4 1800 mVPP
VOD Differential Output Voltage Swing VID > 18mVPP 1500 mVPP
SDAL
/LOSDL Lo w SD Asse rt / LOS De-assert Level RLOS/SDLVL = 5kΩ, Note 8, 10 4.2 mVPP
SDDL//
LOSAL Low SD De-assert/LOS Assert Level RLOS/SDLVL = 5kΩ, Note 10 3 mVPP
HYSL Low SD/LOS Hysteresis RLOS/SDLVL = 5kΩ, Note 11 2.9 dB
SDAM/
LOSDM Medium SD Assert/LOS
De-assert Level RLOS/SDLVL = 2.5kΩ, Note 10 5.2 12 mVPP
SDDM/
LOSAM Medium SD De-assert/LOS Assert
Level RLOS/SDLVL = 2.5kΩ, Note 10 2.5 3.7 mVPP
HYSM Medium SD/LOS Hysteresis RLOS/SDLVL = 2.5kΩ, Note 11 3 dB
SDAH/
LOSDH High SD Assert/LOS De-assert Level RLOS/SDLVL = 50Ω, Note 10 15 24 mVPP
SDDH/
LOSAH High SD De-assert/ LOS Assert Level RLOS/SDLVL = 50Ω, Note 10 6 9.5 mVPP
HYSH High SD/LOS Hysteresis RLOS/SDLVL = 50Ω, Note 11 4 dB
B-3dB 3dB Bandwidth 1 GHz
AV(Diff) Differential Voltage Gain 48 dB
S21 Single-ended Small-Signal Gain 42 dB
Notes:
4. Ampl ifi er i n limiting mode. I nput is a 200MHz square wave.
5. The time bet ween applying RESET and outputs being disabl ed.
6. Determini st ic jitter m easured using 1.25Gbps K28.5 pattern, VID = 10m VPP.
7. Random jitt er m easured using 1.25Gbps K28.7 pattern, VID = 10mVPP.
8. SD is the opposite pol arity of LOS. Therefore, an SD Assert parameter is equivalent to a LOS De-assert parameter and vice versa.
9. See “Typic al Operati ng Charact eristics” for graphs showing input signal vs. SD Assert/LOS De-ass ert time at various RLOS/SDLVL settings.
10. See “Typic al Operati ng Charact eristics” for a graph showing how to choose a particular RLOS/SDLVL for a particular assert and
its associat ed de-assert amplit ude.
11. This specification defines electrical hysteresis as 20log (SD Assert/SD De-assert ). The ratio between optical hysteres is and electri c al hysteres is is
found to vary between 1.5 and 2 depending upon the level of received optical power and ROSA characteristics. Based upon that ratio, the optical
hysteresis corresponding to the electrical hysteresis range 2dB-5dB, shown in the AC characteristics t able, will be: 1dB-4dB optical Hysteresis.
12. JAM Low to High transiti on propagation del ay ref ers t o the time it takes from a LOW to HIGH transition at JAM input to turning on (if SD is selected)
or turning off (if LOS is selected) the LVPECL outputs.
13. JAM High to Low transition propagation delay refers to the time it takes from a HIGH to LOW transition at JAM input to turning off (if SD is selected)
or turning on (if LOS is selected) the LVPECL outputs.
Micrel, Inc.
SY88149HL
June 2010 7 M9999-061110-I
hbwhelp@micrel.com or (408) 955-1690
Functional Block Diagram
Detailed Description
The SY88149HL is a high-sens itivity limiting pos t amplifier
which operates on a +3.3V power supply over the
industrial tem perature range. Signals with data rates up to
1.25Gbps and as small as 4mVpp can be amplified. Figure
1 shows the allo wed input voltage s wing. Depending upon
the LOS/SDSEL option, the SY88149HL can generate an
SD or LOS output, and allow feedback to the JAM input for
output stability. LOS/SDLVL sets the sensitivity of the input
amplitude detection.
To sat isf y the stri nge nt timing requ irements of the GPO N
specifications, the signal detect circuit offers 5ns SD
assert (LOS de-assert) time and the option to de-assert
SD (assert LOS) using the /AUTORESET or manual
RESET function. When /AUTORESET is enabled, SD
de-asserts/LOS asserts automatically within 100ns after
the last high-to-low transition of the input burst. When
the /AUTORESET function is disabled, the SD De-
assert/LOS Assert time can be reset by using the
provided RESET pin.
Input Bu ffe r
Figure 2 shows a simplified schematic of the input stage.
The high sensitivity of the input amplif ier allows signals as
small as 4mVpp to be detected and amplified. The input
buffer can allow input signals as large as 1800mVPP. Input
signals are linearly amplified with a typically 48dB
differential voltage gain until the outputs reach 1500mVPP
(typ). Applications requiring the SY88149HL to operate
with high-gain should have the upstream TIA placed as
close as possible to the SY88149HL’s input pins. This
ensures the best performance of the device.
Output Buf fer
The SY88149HL’s LVPECL output buffer is designed to
drive 50Ω lines. The output buffer requires appropriate
termination for proper operation. An external 50Ω
resistor to VCC–2V for each output pin provides this.
Figure 3 shows a simplified schematic of the output
stage.
Loss of Si gnal /S igna l De te ct
The SY88149HL generates a chatter-free Signal-Detect
(SD) or LOS LVTTL output, as s hown in Figure 4. A hig hl y
sensitive signal detect circuit is used to determine that the
input amplitude is too sm all to be considered a valid input.
LOS asserts high if the input amplitude falls below the
threshold set by LOS/SDLVL and de-asserts low
otherwise. SD asserts high if the input amplitude rises
above the threshold set by LOS/SDLVL and de-asserts
low otherwise. LOS/SD can be fed back to the JAM input
to maintain output stabilit y under the absenc e of an inva lid
signal condition. Typically, a 3 dB hysteresis is provided to
prevent chattering.
LOS/SD Level Set
A programmable LOS/SD level set pin (LOS/SDLVL) sets
the threshold of the input amplitude detection. Connecting
an external resistor between VCC and LOS/SDLVL sets the
voltage at LOS/SDLVL. This voltage ranges from VCC to
VREF. The external resistor creates a voltage divider
between VCC and VREF, as shown in Figure 5. Set the
LOS/SDLVL voltage closer to VREF or more sensitive
LOS/SD detection or closer to VCC for higher amplitude
inputs.
Micrel, Inc.
SY88149HL
June 2010 10 M9999-061110-I
hbwhelp@micrel.com or (408) 955-1690
Related Product and Support Documentation
Part Number Function Datasheet Link
SY88903AL 3.3V, Burst Mode 1.25Gbps PECL High-
Sensitivity Limiting Post Amplifier with
TTL Loss-of-Signal
http://www.micrel.com/product-info/sy88903al.shtml
SY88149CL 3.3V, 1.25Gbps PECL Limiting Post Amplifier
w/High Gain TTL Signal Detect http://www.micrel.com/product-info/sy88149cl.shtml
Application Notes Notes on Sensitivity and Hysteresis in Micrel
Post Amplifiers http://www.micrel.com/product-info/app_hints+notes.shtml
Micrel, Inc.
SY88149HL
June 2010 11 M9999-061110-I
hbwhelp@micrel.com or (408) 955-1690
Package Information
16-Pin QFN
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-10 00 WEB http:// www .micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its
use. Micrel reserves the right to change circuit ry and specific ations at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support applianc es, devic es or syst ems where malf unct i on of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or
systems that (a) are intended for surgical impl ant
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Purchaser’s use or sale of Micrel Products for use in
life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully
indemnify Micrel f or any damages resulting from such use or sale.
© 2010 Micrel, Incorporat ed.
