Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
LM10
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
LM10 Operational Amplifier and Voltage Reference
The circuit is recommended for portable equipment
1 Features and is completely specified for operation from a
1• Input Offset Voltage: 2 mV (Maximum) single power cell. In contrast, high output-drive
• Input Offset Current: 0.7 nA (Maximum) capability, both voltage and current, along with
thermal overload protection, suggest it in demanding
• Input Bias Current: 20 nA (Maximum) general-purpose applications.
• Reference Regulation: 0.1% (Maximum) The device is capable of operating in a floating mode,
• Offset Voltage Drift: 2 μV/°C independent of fixed supplies. It can function as a
• Reference Drift: 0.002%/°C remote comparator, signal conditioner, SCR controller
or transmitter for analog signals, delivering the
2 Applications processed signal on the same line used to supply
power. It is also suited for operation in a wide range
• Remote Amplifiers of voltage and current regulator applications, from low
• Battery-Level Indicators voltages to several hundred volts, providing greater
• Thermocouple Transmitters precision than existing ICs.
• Voltage and Current regulators This series is available in the three standard
temperature ranges, with the commercial part having
3 Description relaxed limits. In addition, a low-voltage specification
The LM10 series are monolithic linear ICs consisting (suffix L) is available in the limited temperature
of a precision reference, an adjustable reference ranges at a cost savings.
buffer and an independent, high-quality operational
amplifier. Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
The unit can operate from a total supply voltage as
low as 1.1 V or as high as 40 V, drawing only 270 μA. SOIC (14) 8.992 mm × 7.498 mm
A complementary output stage swings within 15 mV LM10 SDIP (8) 8.255 mm × 8.255 mm
of the supply terminals or will deliver ±20-mA output PDIP (8) 9.81 mm × 6.35 mm
current with ±0.4-V saturation. Reference output can (1) For all available packages, see the orderable addendum at
be as low as 200 mV. the end of the data sheet.
Operational Amplifier Schematic
(Pin numbers are for 8-pin packages)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM10
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 17
1 Features.................................................................. 18 Application and Implementation ........................ 18
2 Applications ........................................................... 18.1 Application Information............................................ 18
3 Description............................................................. 18.2 Typical Application ................................................. 18
4 Revision History..................................................... 28.3 System Examples ................................................... 19
5 Pin Configuration and Functions......................... 39 Power Supply Recommendations...................... 27
6 Specifications......................................................... 410 Layout................................................................... 27
6.1 Absolute Maximum Ratings ...................................... 410.1 Layout Guidelines ................................................. 27
6.2 Recommended Operating Conditions....................... 410.2 Layout Example .................................................... 27
6.3 Thermal Information.................................................. 411 Device and Documentation Support................. 28
6.4 Electrical Characteristics LM10/LM10B .................... 511.1 Device Support .................................................... 28
6.5 Electrical Characteristics, LM10C............................. 611.2 Documentation Support ........................................ 28
6.6 Electrical Characteristics, LM10BL ........................... 811.3 Community Resources.......................................... 28
6.7 Electrical Characteristics, LM10CL........................... 911.4 Trademarks........................................................... 29
6.8 Typical Characteristics............................................ 11 11.5 Electrostatic Discharge Caution............................ 29
7 Detailed Description............................................ 17 11.6 Glossary................................................................ 29
7.1 Overview................................................................. 17 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram....................................... 17 Information ........................................................... 29
7.3 Feature Description................................................. 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2013) to Revision E Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision C (March 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 26
2Submit Documentation Feedback Copyright © 1998–2015, Texas Instruments Incorporated
Product Folder Links: LM10
LM10
www.ti.com
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
5 Pin Configuration and Functions
NEV Package P Package
8-Pin SDIP 8-Pin PDIP
Top View Top View
Pin Functions — 8-Pin SDIP or PDIP
PIN I/O DESCRIPTION
NAME NO.
Balance 5 I Used for offset nulling
Op Amp Input (+) 3 I Noninverting input of operational amplifier
Op Amp Input (–) 2 I Inverting input of operational amplifier
Op Amp Output 6 O Output terminal of operational amplifier
Reference Feedback 8 I Feedback terminal of reference
Reference Output 1 O Output terminal of reference
V+ 7 I Positive supply voltage
V– 4 I Negative supply voltage
NPA Package
14-Pin SOIC
Top View
Pin Functions — 14-Pin SOIC
PIN I/O DESCRIPTION
NAME NO.
Balance 9 I Used for offset nulling
NC 1, 2, 7, 8, 14, 13 — No connection
Op Amp Input (–) 4 I Inverting input of operational amplifier
Op Amp Input (+) 5 I Noninverting input of operational amplifier
Op Amp Output 10 O Output terminal of operational amplifier
Reference Feedback 12 I Feedback terminal of reference
Reference Output 3 O Output terminal of reference
V+ 11 I Positive supply voltage
V– 6 I Negative supply voltage
Copyright © 1998–2015, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: LM10
LM10
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
See (1)(2)(3)
MIN MAX UNIT
LM10/LM10B/LM10C 45 V
Total supply voltage LM10BL/LM10CL 7 V
LM10/LM10B/LM10C ±40 V
Differential input voltage(4) LM10BL/LM10CL ±7 V
Power dissipation(5) Internally limited
Output short-circuit duration(6) Continuous
TO Soldering (10 seconds) 300 °C
Soldering (10 seconds) 260 °C
Lead temperature DIP Vapor phase (60 seconds) 215 °C
Infrared (15 seconds) 220 °C
LM10 150 °C
Maximum junction LM10B 100 °C
temperature LM10C 85 °C
Storage temperature, Tstg −55 150 °C
(1) Refer to RETS10X for LM10H military specifications.
(2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(4) The Input voltage can exceed the supply voltages provided that the voltage from the input to any other terminal does not exceed the
maximum differential input voltage and excess dissipation is accounted for when VIN < V−.
(5) The maximum, operating-junction temperature is 150°C for the LM10, 100°C for the LM10B(L) and 85°C for the LM10C(L). At elevated
temperatures, devices must be derated based on package thermal resistance.
(6) Internal thermal limiting prevents excessive heating that could result in sudden failure, but the IC can be subjected to accelerated stress
with a shorted output and worst-case conditions.
6.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
VSSupply input voltage range (V–) – (V+) 1.2 40 V
VCM Common-mode voltage (V–) (V+) – 0.85 V
VREF Reference voltage 0.2 V
IREF Reference current 0 1 mA
6.3 Thermal Information LM10
THERMAL METRIC(1) NEV (SDIP) NPA (SOIC) P (PDIP) UNIT
8 PINS 14 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 150 90 87 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 45 — — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4Submit Documentation Feedback Copyright © 1998–2015, Texas Instruments Incorporated
Product Folder Links: LM10
LM10
www.ti.com
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
6.4 Electrical Characteristics LM10/LM10B
TJ=25°C unless otherwise specified(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TJ=25°C 0.3 2 mV
Input offset voltage TMIN ≤TJ≤TMAX (see (1)) 3 mV
TJ=25°C 0.25 0.7 nA
Input offset current(2) TMIN ≤TJ≤TMAX (see (1)) 1.5 nA
TJ=25°C 10 20 nA
Input bias current TMIN ≤TJ≤TMAX (see (1)) 30 nA
TJ=25°C 250 500 kΩ
Input resistance TMIN ≤TJ≤TMAX (see (1)) 150 kΩ
VS= ±20 V, IOUT = 0 120 400 V/mV
VOUT = ±19.95 V, TMIN ≤TJ≤TMAX (see (1)) 80 V/mV
VS= ±20 V, VOUT = ±19.4 V 50 130 V/mV
IOUT = ±20 mA, TMIN ≤TJ≤TMAX (see (1)) 20 V/mV
Large signal voltage IOUT = ±15 mA, TMIN ≤TJ≤TMAX (see (1)) 20 V/mV
gain VS= ±0.6 V, IOUT = ±2 mA 1.5 3 V/mV
VS= ±0.65 V, IOUT = ±2 mA, TMIN ≤TJ≤TMAX (see (1)) 1.5 3 V/mV
VOUT = ±0.4 V, TMIN ≤TJ≤TMAX (see (1)) 0.5 V/mV
VOUT = ±0.3 V, VCM =−0.4 V, TMIN ≤TJ≤TMAX (see (1)) 0.5 V/mV
1.2 V ≤VOUT ≤40 V, RL= 1.1 kΩ14 33 V/mV
1.3 V ≤VOUT ≤40 V, RL= 1.1 kΩ, TMIN ≤TJ≤TMAX (see (1)) 14 33 V/mV
Shunt gain(3) 0.1 mA ≤IOUT ≤5 mA, TMIN ≤TJ≤TMAX (see (1)) 6 V/mV
1.5 V ≤V+≤40 V, RL= 250 Ω8 25 V/mV
0.1 mA ≤IOUT ≤20 mA, TMIN ≤TJ≤TMAX (see (1)) 4 V/mV
−20 V ≤VCM ≤19.15 V 93 102 dB
Common-mode −20 V ≤VCM ≤19 V, TMIN ≤TJ≤TMAX (see (1)) 93 102 dB
rejection VS= ±20 V, TMIN ≤TJ≤TMAX (see (1)) 87 dB
−0.2 V ≥V−≥ −39 V 90 96 dB
V+= 1 V, TMIN ≤TJ≤TMAX (see (1)) 84 dB
V+= 1.1 V, TMIN ≤TJ≤TMAX (see (1)) 84 dB
Supply-voltage
rejection 1 V ≤V+≤39.8 V 96 106 dB
1.1 V ≤V+≤39.8 V, TMIN ≤TJ≤TMAX (see (1)) 96 106 dB
V−=−0.2 V, TMIN ≤TJ≤TMAX (see (1)) 90 dB
Offset voltage drift 2 μV/°C
Offset current drift 2 pA/°C
Bias current drift TC< 100°C 60 pA/°C
1.2 V ≤VS≤40 V 0.001 0.003 %/V
Line regulation 1.3 V ≤VS≤40 V, TMIN ≤TJ≤TMAX (see (1)) 0.001 0.003 %/V
0≤IREF ≤1 mA, VREF = 200 mV, TMIN ≤TJ≤TMAX (see (1)) 0.006 %/V
0≤IREF ≤1 mA 0.01% 0.1%
Load regulation V+−VREF ≥1 V, TMIN ≤TJ≤TMAX (see (1)) 0.15%
V+−VREF ≥1.1 V, TMIN ≤TJ≤TMAX (see (1)) 0.15%
(1) These specifications apply for V−≤VCM ≤V+−0.85 V, 1 V (TMIN ≤TJ≤TMAX), 1.2 V, 1.3 V (TMIN ≤TJ≤TMAX) < VS≤VMAX, VREF = 0.2 V
and 0 ≤IREF ≤1 mA, unless otherwise specified: VMAX = 40 V for the standard part and 6.5 V for the low voltage part. The full-
temperature-range operation is −55°C to 125°C for the LM10, −25°C to 85°C for the LM10B(L) and 0°C to 70°C for the LM10C(L). The
specifications do not include the effects of thermal gradients (τ1≃20 ms), die heating (τ2≃0.2 s) or package heating. Gradient effects
are small and tend to offset the electrical error (see curves).
(2) For TJ> 90°C, IOS may exceed 1.5 nA for VCM = V−. With TJ= 125°C and V−≤VCM ≤V−+ 0.1 V, IOS ≤5 nA.
(3) This defines operation in floating applications such as the bootstrapped regulator or two-wire transmitter. Output is connected to the V+
terminal of the IC and input common mode is referred to V−(see System Examples). Effect of larger output-voltage swings with higher
load resistance can be accounted for by adding the positive-supply rejection error.
Copyright © 1998–2015, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LM10
LM10
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
www.ti.com
Electrical Characteristics LM10/LM10B (continued)
TJ=25°C unless otherwise specified(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TJ=25°C 50 75 V/mV
Amplifier gain 0.2 V ≤VREF ≤35 V TMIN ≤TJ≤TMAX (see (1)) 23 V/mV
TJ=25°C 195 200 205 mV
Feedback sense
voltage TMIN ≤TJ≤TMAX (see (1)) 194 206 mV
TJ=25°C 20 50 nA
Feedback current TMIN ≤TJ≤TMAX (see (1)) 65 nA
Reference drift 0.002 %/°C
TJ=25°C 270 400 μA
Supply current TMIN ≤TJ≤TMAX (see (1)) 500 μA
TJ=25°C 15
1.2 V ≤VS≤40 V μA
TMIN ≤TJ≤TMAX (see (1)) 75
Supply current change TJ=25°C 15
1.3 V ≤VS≤40 V μA
TMIN ≤TJ≤TMAX (see (1)) 75
6.5 Electrical Characteristics, LM10C
TJ=25°C unless otherwise specified(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TJ=25°C 0.5 4 mV
Input offset voltage TMIN ≤TJ≤TMAX (see (1)) 5 mV
TJ=25°C 0.4 2 nA
Input offset current(2) TMIN ≤TJ≤TMAX (see (1)) 3 nA
TJ=25°C 12 30 nA
Input bias current TMIN ≤TJ≤TMAX (see (1)) 40 nA
TJ=25°C 150 400 kΩ
Input resistance TMIN ≤TJ≤TMAX (see (1)) 115 kΩ
VS= ±20 V, IOUT = 0 80 400 V/mV
VOUT = ±19.95 V, TMIN ≤TJ≤TMAX (see (1)) 50 V/mV
VS= ±20 V, VOUT = ±19.4 V 25 130 V/mV
IOUT = ±20 mA, TMIN ≤TJ≤TMAX (see (1)) 15 V/mV
Large signal voltage gain IOUT = ±15 mA, TMIN ≤TJ≤TMAX (see (1)) 15 V/mV
VS= ±0.6 V, IOUT = ±2 mA 1 3 V/mV
VS= 0.65 V, IOUT = ±2 mA, TMIN ≤TJ≤TMAX (see (1)) 1 3 V/mV
VOUT = ±0.4 V, TMIN ≤TJ≤TMAX (see (1)) 0.75 V/mV
VOUT = ±0.3 V, VCM =−0.4 V, TMIN ≤TJ≤TMAX (see (1)) 0.75 V/mV
1.2 V ≤VOUT ≤40 V, RL= 1.1 kΩ10 33 V/mV
1.3 V ≤VOUT ≤40 V, RL= 1.1 kΩ, TMIN ≤TJ≤TMAX (see (1)) 10 33 V/mV
Shunt gain(3) 0.1 mA ≤IOUT ≤5 mA, TMIN ≤TJ≤TMAX (see (1)) 6 V/mV
1.5 V ≤V+≤40 V, RL= 250 Ω6 25 V/mV
0.1 mA ≤IOUT ≤20 mA, TMIN ≤TJ≤TMAX (see (1)) 4 V/mV
(1) These specifications apply for V−≤VCM ≤V+−0.85 V, 1 V (TMIN ≤TJ≤TMAX), 1.2 V, 1.3 V (TMIN ≤TJ≤TMAX) < VS≤VMAX, VREF = 0.2 V
and 0 ≤IREF ≤1 mA, unless otherwise specified: VMAX = 40 V for the standard part and 6.5 V for the low voltage part. The full-
temperature-range operation is −55°C to 125°C for the LM10, −25°C to 85°C for the LM10B(L) and 0°C to 70°C for the LM10C(L). The
specifications do not include the effects of thermal gradients (τ1≃20 ms), die heating (τ2≃0.2 s) or package heating. Gradient effects
are small and tend to offset the electrical error (see curves).
(2) For TJ> 90°C, IOS may exceed 1.5 nA for VCM = V−. With TJ= 125°C and V−≤VCM ≤V−+ 0.1 V, IOS ≤5 nA.
(3) This defines operation in floating applications such as the bootstrapped regulator or two-wire transmitter. Output is connected to the V+
terminal of the IC and input common mode is referred to V−(see System Examples). Effect of larger output-voltage swings with higher
load resistance can be accounted for by adding the positive-supply rejection error.
6Submit Documentation Feedback Copyright © 1998–2015, Texas Instruments Incorporated
Product Folder Links: LM10
LM10
www.ti.com
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
Electrical Characteristics, LM10C (continued)
TJ=25°C unless otherwise specified(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
−20 V ≤VCM ≤19.15 V 90 102 dB
Common-mode rejection −20 V ≤VCM ≤19 V 90 102 dB
VS= ±20 V, TMIN ≤TJ≤TMAX (see (1)) 87 dB
−0.2 V ≥V−≥ −39 V 87 96 dB
V+= 1 V, TMIN ≤TJ≤TMAX (see (1)) 84 dB
V+= 1.1 V, TMIN ≤TJ≤TMAX (see (1)) 84 dB
Supply-voltage rejection 1 V ≤V+≤39.8 V 93 106 dB
1.1 V ≤V+≤39.8 V, TMIN ≤TJ≤TMAX (see (1)) 93 106 dB
V−=−0.2 V, TMIN ≤TJ≤TMAX (see (1)) 90 dB
Offset voltage drift 5 μV/°C
Offset current drift 5 pA/°C
Bias current drift TC< 100°C 90 pA/°C
1.2 V ≤VS≤40 V 0.001 0.008 %/V
Line regulation 1.3 V ≤VS≤40 V, TMIN ≤TJ≤TMAX (see (1)) 0.001 0.008 %/V
0≤IREF ≤1 mA, VREF = 200 mV, TMIN ≤TJ≤TMAX (see (1)) 0.01 %/V
0≤IREF ≤1 mA 0.01% 0.15%
Load regulation V+−VREF ≥1 V, TMIN ≤TJ≤TMAX (see (1)) 0.2%
V+−VREF≥1.1 V, TMIN ≤TJ≤TMAX (see (1)) 0.2%
TJ=25°C 25 70 V/mV
Amplifier gain 0.2 V ≤VREF ≤35 V TMIN ≤TJ≤TMAX (see (1)) 15 V/mV
TJ=25°C 190 200 210 mV
Feedback sense voltage TMIN ≤TJ≤TMAX (see (1)) 189 211 mV
TJ=25°C 22 75 nA
Feedback current TMIN ≤TJ≤TMAX (see (1)) 90 nA
Reference drift 0.003 %/°C
TJ=25°C 300 500 μA
Supply current TMIN ≤TJ≤TMAX (see (1)) 570 μA
TJ=25°C 15
1.2 V ≤VS≤40 V μA
TMIN ≤TJ≤TMAX (see (1)) 75
Supply current change TJ=25°C 15
1.3 V ≤VS≤40 V μA
TMIN ≤TJ≤TMAX (see (1)) 75
Copyright © 1998–2015, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: LM10
LM10
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
www.ti.com
6.6 Electrical Characteristics, LM10BL
TJ=25°C unless otherwise specified.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TJ=25°C 0.3 2 mV
Input offset voltage TMIN ≤TJ≤TMAX (see (1)) 3 mV
TJ=25°C 0.1 0.7 nA
Input offset current(2) TMIN ≤TJ≤TMAX (see (1)) 1.5 nA
TJ=25°C 10 20 nA
Input bias current TMIN ≤TJ≤TMAX (see (1)) 30 nA
TJ=25°C 250 500 kΩ
Input resistance TMIN ≤TJ≤TMAX (see (1)) 150 kΩ
VS= ±3.25 V, IOUT = 0 60 300 V/mV
VOUT = ±3.2 V, TMIN ≤TJ≤TMAX (see (1)) 40 V/mV
VS= ±3.25 V, IOUT = 10 mA 10 25 V/mV
VOUT = ±2.75 V, TMIN ≤TJ≤TMAX (see (1)) 4 V/mV
Large signal voltage gain VS= ±0.6 V, IOUT = ±2 mA 1.5 3 V/mV
VS= 0.65 V, IOUT = ±2 mA, TMIN ≤TJ≤TMAX (see (1)) 1.5 3 V/mV
VOUT = ±0.4 V, VCM =−0.4 V, TMIN ≤TJ≤TMAX (see (1)) 0.5 V/mV
VOUT = ±0.3 V, VCM =−0.4 V, TMIN ≤TJ≤TMAX (see (1)) 0.5 V/mV
1.5 V ≤V+≤6.5 V, RL= 500 Ω8 30 V/mV
Shunt gain(3) 0.1 mA ≤IOUT ≤10 mA, TMIN ≤TJ≤TMAX (see (1)) 4 V/mV
−3.25 V ≤VCM ≤2.4 V 89 102 dB
Common-mode rejection −3.25 V ≤VCM ≤2.25 V, TMIN ≤TJ≤TMAX (see (1))
VS= ±3.25 V, TMIN ≤TJ≤TMAX (see (1)) 83 dB
−0.2 V ≥V−≥ −5.4 V 86 96 dB
V+= 1 V, TMIN ≤TJ≤TMAX (see (1)) 80 dB
V+= 1.2 V, TMIN ≤TJ≤TMAX (see (1)) 80 dB
Supply-voltage rejection 1 V ≤V+≤6.3 V 94 106 dB
1.1 V ≤V+≤6.3 V, TMIN ≤TJ≤TMAX (see (1)) 94 106 dB
V−=0.2 V, TMIN ≤TJ≤TMAX (see (1)) 88 dB
Offset voltage drift 2 μV/°C
Offset current drift 2 pA/°C
Bias current drift 60 pA/°C
1.2 V ≤VS≤6.5 V 0.001 0.01 %/V
Line regulation 1.3 V ≤VS≤6.5 V, TMIN ≤TJ≤TMAX (see (1)) 0.001 0.01 %/V
0≤IREF ≤0.5 mA, VREF = 200 mV, TMIN ≤TJ≤TMAX (see (1)) 0.02 %/V
0≤IREF ≤0.5 mA 0.01% 0.1%
Load regulation V+−VREF ≥1 V, TMIN ≤TJ≤TMAX (see (1)) 0.15%
V+−VREF ≥1.1 V, TMIN ≤TJ≤TMAX (see (1)) 0.15%
TJ=25°C 30 70 V/mV
Amplifier gain 0.2 V ≤VREF ≤5.5 V TMIN ≤TJ≤TMAX (see (1)) 20 V/mV
TJ=25°C 195 200 205 mV
Feedback sense voltage TMIN ≤TJ≤TMAX (see (1)) 194 206 mV
(1) These specifications apply for V−≤VCM ≤V+−0.85 V, 1 V (TMIN ≤TJ≤TMAX), 1.2 V, 1.3 V (TMIN ≤TJ≤TMAX) < VS≤VMAX, VREF = 0.2 V
and 0 ≤IREF ≤1 mA, unless otherwise specified: VMAX = 40 V for the standard part and 6.5 V for the low voltage part. The full-
temperature-range operation is −55°C to 125°C for the LM10, −25°C to 85°C for the LM10B(L) and 0°C to 70°C for the LM10C(L). The
specifications do not include the effects of thermal gradients (τ1≃20 ms), die heating (τ2≃0.2 s) or package heating. Gradient effects
are small and tend to offset the electrical error (see curves).
(2) For TJ> 90°C, IOS may exceed 1.5 nA for VCM = V−. With TJ=125°C and V−≤VCM ≤V−+ 0.1 V, IOS ≤5 nA.
(3) This defines operation in floating applications such as the bootstrapped regulator or two-wire transmitter. Output is connected to the V+
terminal of the IC and input common mode is referred to V−(see System Examples). Effect of larger output-voltage swings with higher
load resistance can be accounted for by adding the positive-supply rejection error.
8Submit Documentation Feedback Copyright © 1998–2015, Texas Instruments Incorporated
Product Folder Links: LM10
LM10
www.ti.com
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
Electrical Characteristics, LM10BL (continued)
TJ=25°C unless otherwise specified.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TJ=25°C 20 50 nA
Feedback current TMIN ≤TJ≤TMAX (see (1)) 65 nA
Reference drift 0.002 %/°C
TJ=25°C 260 400 μA
Supply current TMIN ≤TJ≤TMAX (see (1)) 500 μA
6.7 Electrical Characteristics, LM10CL
TJ=25°C unless otherwise specified.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TJ=25°C 0.5 4 mV
Input offset voltage TMIN ≤TJ≤TMAX (see (1)) 5 mV
TJ=25°C 0.2 2 nA
Input offset current(2) TMIN ≤TJ≤TMAX (see (1)) 3 nA
TJ=25°C 12 30 nA
Input bias current TMIN ≤TJ≤TMAX (see (1)) 40 nA
TJ=25°C 150 400 kΩ
Input resistance TMIN ≤TJ≤TMAX (see (1)) 115 kΩ
VS= ±3.25 V, IOUT = 0 40 300 V/mV
VOUT = ±3.2 V, TMIN ≤TJ≤TMAX (see (1)) 25 V/mV
VS= ±3.25 V, IOUT = 10 mA 5 25 V/mV
VOUT = ±2.75 V, TMIN ≤TJ≤TMAX (see (1)) 3 V/mV
Large signal voltage gain VS= ±0.6 V, IOUT = ±2 mA 1 3 V/mV
VS= 0.65 V, IOUT = ±2 mA, TMIN ≤TJ≤TMAX (see (1)) 1 3 V/mV
VOUT = ±0.4 V, VCM =−0.4 V, TMIN ≤TJ≤TMAX (see (1)) 0.75 V/mV
VOUT = ±0.3 V, VCM =−0.4 V, TMIN ≤TJ≤TMAX (see (1)) 0.75 V/mV
1.5 V ≤V+≤6.5 V, RL= 500 Ω6 30 V/mV
Shunt gain(3) 0.1 mA ≤IOUT ≤10 mA, TMIN ≤TJ≤TMAX (see (1)) 4 V/mV
−3.25 V ≤VCM ≤2.4 V 80 102 dB
Common-mode rejection −3.25 V ≤VCM ≤2.25 V, TMIN ≤TJ≤TMAX (see (1)) 80 102 dB
VS= ±3.25 V, TMIN ≤TJ≤TMAX (see (1)) 74 dB
−0.2 V ≥V–≥ −5.4 V 80 96 dB
V+= 1 V, TMIN ≤TJ≤TMAX (see (1)) 74 dB
V+= 1.2 V, TMIN ≤TJ≤TMAX (see (1)) 74 dB
Supply-voltage rejection 1V≤V+≤6.3 V 80 106 dB
1.1 V ≤V+≤6.3 V, TMIN ≤TJ≤TMAX (see (1)) 80 106 dB
V−= 0.2 V, TMIN ≤TJ≤TMAX (see (1)) 74 dB
Offset voltage drift 5 μV/°C
Offset current drift 5 pA/°C
Bias current drift 90 pA/°C
(1) These specifications apply for V−≤VCM ≤V+−0.85 V, 1 V (TMIN ≤TJ≤TMAX), 1.2 V, 1.3 V (TMIN ≤TJ≤TMAX) < VS≤VMAX, VREF = 0.2 V
and 0 ≤IREF ≤1 mA, unless otherwise specified: VMAX = 40 V for the standard part and 6.5 V for the low voltage part. The full-
temperature-range operation is −55°C to 125°C for the LM10, −25°C to 85°C for the LM10B(L) and 0°C to 70°C for the LM10C(L). The
specifications do not include the effects of thermal gradients (τ1≃20 ms), die heating (τ2≃0.2 s) or package heating. Gradient effects
are small and tend to offset the electrical error (see curves).
(2) For TJ> 90°C, IOS may exceed 1.5 nA for VCM = V−. With TJ= 125°C and V−≤VCM ≤V−+ 0.1 V, IOS ≤5 nA.
(3) This defines operation in floating applications such as the bootstrapped regulator or two-wire transmitter. Output is connected to the V+
terminal of the IC and input common mode is referred to V−(see System Examples). Effect of larger output-voltage swings with higher
load resistance can be accounted for by adding the positive-supply rejection error.
Copyright © 1998–2015, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: LM10
LM10
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
www.ti.com
Electrical Characteristics, LM10CL (continued)
TJ=25°C unless otherwise specified.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
1.2 V ≤VS≤6.5 V 0.001 0.02 %/V
Line regulation 1.3 V ≤VS≤6.5 V, TMIN ≤TJ≤TMAX (see (1)) 0.001 0.02 %/V
0≤IREF ≤0.5 mA, VREF = 200 mV, TMIN ≤TJ≤TMAX (see (1)) 0.03 %/V
0≤IREF ≤0.5 mA 0.01% 0.15%
Load regulation V+−VREF ≥1 V, TMIN ≤TJ≤TMAX (see (1)) 0.2%
V+−VREF ≥1.1 V, TMIN ≤TJ≤TMAX (see (1)) 0.2%
TJ=25°C 20 70 V/mV
Amplifier gain 0.2 V ≤VREF ≤5.5 V TMIN ≤TJ≤TMAX (see (1)) 15 V/mV
TJ=25°C 190 200 210 mV
Feedback sense voltage TMIN ≤TJ≤TMAX (see (1)) 189 211 mV
TJ=25°C 22 75 nA
Feedback current TMIN ≤TJ≤TMAX (see (1)) 90 nA
Reference drift 0.003 %/°C
TJ=25°C 280 500 μA
Supply current TMIN ≤TJ≤TMAX (see (1)) 570 μA
10 Submit Documentation Feedback Copyright © 1998–2015, Texas Instruments Incorporated
Product Folder Links: LM10
LM10
www.ti.com
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
6.8 Typical Characteristics
6.8.1 Typical Characteristics (Op Amp)
Figure 2. Common-Mode Limits
Figure 1. Input Current
Figure 3. Output Voltage Drift Figure 4. Input Noise Voltage
Figure 6. Transconductance
Figure 5. DC Voltage Gain
Copyright © 1998–2015, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: LM10
LM10
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
www.ti.com
Typical Characteristics (Op Amp) (continued)
Figure 8. Output Saturation Characteristics
Figure 7. Output Saturation Characteristics
Figure 10. Minimum Supply Voltage
Figure 9. Output Saturation Characteristics
Figure 11. Minimum Supply Voltage Figure 12. Minimum Supply Voltage
12 Submit Documentation Feedback Copyright © 1998–2015, Texas Instruments Incorporated
Product Folder Links: LM10
LM10
www.ti.com
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
Typical Characteristics (Op Amp) (continued)
Figure 14. Typical Stability Range
Figure 13. Output Impedance
Figure 15. Large Signal Response Figure 16. Comparator Response Time For Various Input
Overdrives
Figure 18. Follower Pulse Response
Figure 17. Comparator Response Time For Various Input
Overdrives
Copyright © 1998–2015, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LM10
LM10
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
www.ti.com
Typical Characteristics (Op Amp) (continued)
Figure 20. Rejection Slew Limiting
Figure 19. Noise Rejection
Figure 22. Thermal Gradient Feedback
Figure 21. Supply Current
Figure 24. Shunt Gain
Figure 23. Thermal Gradient Cross-Coupling
14 Submit Documentation Feedback Copyright © 1998–2015, Texas Instruments Incorporated
Product Folder Links: LM10
LM10
www.ti.com
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
Typical Characteristics (Op Amp) (continued)
Figure 25. Shunt Gain Figure 26. Shunt Gain
Figure 28. Shunt Gain
Figure 27. Shunt Gain
Figure 29. Shunt Gain
Copyright © 1998–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM10
LM10
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
www.ti.com
6.8.2 Typical Characteristics (Reference)
Figure 30. Line Regulation Figure 31. Load Regulation
Figure 33. Minimum Supply Voltage
Figure 32. Reference Noise Voltage
Figure 35. Typical Stability Range
Figure 34. Output Saturation
16 Submit Documentation Feedback Copyright © 1998–2015, Texas Instruments Incorporated
Product Folder Links: LM10
LM10
www.ti.com
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
7 Detailed Description
7.1 Overview
The LM10 is a dual-operational amplifier combined with a voltage reference capable of a single-supply operation
down to 1.1 V. It provides high overall performance, making it ideal for many general-purpose applications. The
circuit can also operate in a floating mode, powered by residual voltage, independent of fixed supplies and it is
well-protected from temperature drift.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Operating Characteristics
The LM10 is specified for operation from 1.2 V to 40 V. Many of the specifications apply from –55⁰C to 125⁰C.
Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in
electrical characteristics tables under Specifications and in the Typical Characteristics section.
7.3.2 Common-Mode Voltage Range
The input common-mode voltage range of the LM10 extends from the negative rail to 0.85 V less than the
positive rail.
7.3.3 Operational Amplifier
The minimum operating voltage is reduced to nearly one volt and the current gain is less affected by
temperature, resulting in a fairly flat bias current over temperature.
7.3.4 Voltage Reference
Second-order nonlinearities are compensated for which eliminates the bowed characteristics of conventional
designs, resulting in better temperature stability.
7.4 Device Functional Modes
7.4.1 Floating Mode
To use the device in a floating mode, the operational amplifier output is shorted to V+ which disables the PNP
portion of the output stage. Thus, with a positive input signal, neither halves of the output conducts and the
current between the supply terminals is equal to the quiescent supply current. With negative input signals, the
NPN portion of the output begins to turn on, reaching the short circuit current for a few hundred microvolts
overdrive.
7.4.2 Linear Operation
This device can also operate linearly while in the floating mode. An example of this is shown in the Typical
Application section.
Copyright © 1998–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM10
2
O U T R E F
1
R
V = (1 + )V
R
LM10
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
With heavy amplifier loading to V−, resistance drops in the V−lead can adversely affect reference regulation.
Lead resistance can approach 1 Ω. Therefore, the common to the reference circuitry should be connected as
close as possible to the package.
8.2 Typical Application
* required for capacitive loading
Figure 36. Shunt Voltage Regulator
8.2.1 Design Requirements
Table 1 lists the design parameters for this example.
Table 1. Design Parameters
DESIGN PARAMETERS EXAMPLE VALUE
Ambient Temperature Range –55⁰C to 125⁰C
Supply Voltage Range 1.2 V to 40 V
Common-Mode Input Range (V–) to (V+) – 0.85 V
8.2.2 Detailed Design Procedure
Given that the transfer function of this circuit is:
(1)
the output can be set between 0.2 V and the breakdown voltage of the IC by selecting an appropriate value for
R2. The circuit regulates for input voltages within a saturation drop of the output (typically 0.4 V at 20 mA and
0.15 V at 5 mA). The regulator is protected from shorts or overloads by current limiting and thermal shutdown.
18 Submit Documentation Feedback Copyright © 1998–2015, Texas Instruments Incorporated
Product Folder Links: LM10
LM10
www.ti.com
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
Typical regulation is about 0.05% load and 0.003%/V line. A substantial improvement in regulation can be
effected by connecting the operational amplifier as a follower and setting the reference to the desired output
voltage. This has the disadvantage that the minimum input-output differential is increased to a little more than a
diode drop. If the operational amplifier were connected for a gain of 2, the output could again saturate. But this
requires an additional pair of precision resistors.
The regulator in Figure 36 could be made adjustable to zero by connecting the operational amplifier to a
potentiometer on the reference output. This has the disadvantage that the regulation at the lower voltage settings
is not as good as it might otherwise be.
8.2.3 Application Curve
Figure 37. Frequency Response
8.3 System Examples
Circuit descriptions available in application note AN-211 (SNOA638).
8.3.1 Operational Amplifier Offset Adjustment
(Pin numbers are for 8-pin packages)
Figure 38. Standard Figure 39. Limited Range
Copyright © 1998–2015, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LM10
LM10
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
www.ti.com
System Examples (continued)
(Pin numbers are for 8-pin packages)
Figure 40. Limited Range With Boosted Reference
8.3.2 Positive Regulators
(Pin numbers are for 8-pin packages)
Figure 41. Low Voltage Figure 42. Best Regulation
Use only electrolytic output capacitors.
Figure 43. Zero Output Figure 44. Current Regulator
20 Submit Documentation Feedback Copyright © 1998–2015, Texas Instruments Incorporated
Product Folder Links: LM10
LM10
www.ti.com
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
System Examples (continued)
(Pin numbers are for 8-pin packages)
Required For Capacitive Loading
*Electrolytic
Figure 45. Shunt Regulator Figure 46. Negative Regulator
*VOUT=10−4R3
Figure 47. Precision Regulator Figure 48. Laboratory Power Supply
Figure 49. HV Regulator Figure 50. Protected HV Regulator
Copyright © 1998–2015, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LM10
LM10
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
www.ti.com
System Examples (continued)
(Pin numbers are for 8-pin packages)
*800°C Threshold Is Established By Connecting Balance To VREF.
*Provides Hysteresis
Figure 51. Flame Detector Figure 52. Light Level Sensor
Figure 53. Remote Amplifier Figure 54. Remote Thermocouple Amplifier
10 mA≤IOUT≤50 mA
500°C≤TP≤1500°C
*Gain Trim
Figure 55. Transmitter for Bridge Sensor Figure 56. Precision Thermocouple Transmitter
22 Submit Documentation Feedback Copyright © 1998–2015, Texas Instruments Incorporated
Product Folder Links: LM10
LM10
www.ti.com
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
System Examples (continued)
(Pin numbers are for 8-pin packages)
††Level-shift Trim
*Scale Factor Trim
†Copper Wire Wound
Figure 57. Resistance Thermometer Transmitter Figure 58. Optical Pyrometer
1 mA≤IOUT≤5 mA
‡50 μA≤ID≤500 μA
††Center Scale Trim
†Scale Factor Trim
*Copper Wire Wound
200°C≤Tp≤700°C
1 mA≤IOUT≤5 mA
†Gain Trim Figure 59. Thermocouple Figure 60. Logarithmic Light Sensor
Transmitter
Copyright © 1998–2015, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LM10
LM10
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
www.ti.com
System Examples (continued)
(Pin numbers are for 8-pin packages)
Figure 61. Battery-level Indicator Figure 62. Battery-threshold Indicator
Flashes Above 1.2V Flash Rate Increases
Rate Increases With Above 6V and Below 15V
Voltage Figure 63. Single-cell Voltage Monitor Figure 64. Double-ended Voltage Monitor
*Trim For Span
INPUT †Trim For Zero
10 mV, 100nA
FULL-SCALE Figure 65. Meter Amplifier Figure 66. Thermometer
24 Submit Documentation Feedback Copyright © 1998–2015, Texas Instruments Incorporated
Product Folder Links: LM10
LM10
www.ti.com
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
System Examples (continued)
(Pin numbers are for 8-pin packages)
ZOUT∼680Ω@ 5 kHz
AV≤1k
1≤λ/λ0≤105f1∼100 Hz
f2∼5 kHz
RL∼500
*Max Gain Trim
Figure 67. Light Meter Figure 68. Microphone Amplifier
†Controls “Loop Gain”
*Optional Frequency Shaping
Figure 69. Isolated Voltage Sensor Figure 70. Light-Level Controller
Copyright © 1998–2015, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: LM10
LM10
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
www.ti.com
System Examples (continued)
(Pin numbers are for 8-pin packages)
8.3.3 Reference and Internal Regulator
Figure 71. Reference and Internal Regulator
26 Submit Documentation Feedback Copyright © 1998–2015, Texas Instruments Incorporated
Product Folder Links: LM10
1
AMP_IN+
2
AMP_IN+
3
AMP_IN+
4
V– BAL
6
VOUT
8
AMP_IN+
7
VOUT
AMP_IN–
AMP_IN+
V–
AMP_IN+
VOUT
AMP_IN+
AMP_1–
AMP_IN+
1
VOUT
2
VOUT
2
AMP-IN–
1
AMP_INT–
2
AMP-IN–
1
V+
VOUT
LM10
www.ti.com
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
9 Power Supply Recommendations
The LM10 is specified for operation from 1.2 V to 40 V unless otherwise stated. Many specifications apply from
–55⁰C to 125⁰C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in the Specifications section.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings table.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, good printed-circuit board (PCB) layout practices are
recommended. Low-loss, 0.1-uF bypass capacitors should be connected between each supply pin and ground,
placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable to single-
supply applications.
10.2 Layout Example
Figure 72. Layout Example
Copyright © 1998–2015, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: LM10
LM10
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
11.1.1.1 Definition of Terms
Input offset voltage:That voltage which must be applied between the input terminals to bias the unloaded
output in the linear region.
Input offset current:The difference in the currents at the input terminals when the unloaded output is in the
linear region.
Input bias current:The absolute value of the average of the two input currents.
Input resistance:The ratio of the change in input voltage to the change in input current on either input with the
other grounded.
Large signal voltage gain:The ratio of the specified output voltage swing to the change in differential input
voltage required to produce it.
Shunt gain: The ratio of the specified output voltage swing to the change in differential input voltage required to
produce it with the output tied to the V+terminal of the IC. The load and power source are
connected between the V+and V−terminals, and input common-mode is referred to the V−terminal.
Common-mode rejection:The ratio of the input voltage range to the change in offset voltage between the
extremes.
Supply-voltage rejection:The ratio of the specified supply-voltage change to the change in offset voltage
between the extremes.
Line regulation:The average change in reference output voltage over the specified supply voltage range.
Load regulation:The change in reference output voltage from no load to that load specified.
Feedback sense voltage: The voltage, referred to V−, on the reference feedback terminal while operating in
regulation.
Reference amplifier gain:The ratio of the specified reference output change to the change in feedback sense
voltage required to produce it.
Feedback current: The absolute value of the current at the feedback terminal when operating in regulation.
Supply current:The current required from the power source to operate the amplifier and reference with their
outputs unloaded and operating in the linear range.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
AN-211 New Op Amp Ideas,SNOA638
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
28 Submit Documentation Feedback Copyright © 1998–2015, Texas Instruments Incorporated
Product Folder Links: LM10
LM10
www.ti.com
SNOSBH4E –MAY 1998–REVISED OCTOBER 2015
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1998–2015, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Links: LM10
PACKAGE OPTION ADDENDUM
www.ti.com 7-Feb-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM10BH ACTIVE TO-CAN LMG 8 500 Non-RoHS &
Non-Green Call TI Call TI -40 to 85 ( LM10BH, LM10BH)
LM10BH/NOPB ACTIVE TO-CAN LMG 8 500 RoHS & Green Call TI Level-1-NA-UNLIM -40 to 85 ( LM10BH, LM10BH)
LM10CH ACTIVE TO-CAN LMG 8 500 Non-RoHS &
Non-Green Call TI Call TI 0 to 70 ( LM10CH, LM10CH)
LM10CH/NOPB ACTIVE TO-CAN LMG 8 500 RoHS & Green Call TI Level-1-NA-UNLIM 0 to 70 ( LM10CH, LM10CH)
LM10CLN/NOPB ACTIVE PDIP P 8 40 RoHS & Green Call TI | SN Level-1-NA-UNLIM 0 to 70 LM10CLN
LM10CN/NOPB ACTIVE PDIP P 8 40 RoHS & Green Call TI | SN Level-1-NA-UNLIM 0 to 70 LM
10CN
LM10CWM NRND SOIC NPA 14 50 Non-RoHS
& Green Call TI Call TI 0 to 70 LM10CWM
LM10CWM/NOPB ACTIVE SOIC NPA 14 50 RoHS & Green SN Level-3-260C-168 HR 0 to 70 LM10CWM
LM10CWMX/NOPB ACTIVE SOIC NPA 14 1000 RoHS & Green SN Level-3-260C-168 HR 0 to 70 LM10CWM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
PACKAGE OPTION ADDENDUM
www.ti.com 7-Feb-2021
Addendum-Page 2
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM10CWMX/NOPB SOIC NPA 14 1000 330.0 16.4 10.9 9.5 3.2 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Aug-2015
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM10CWMX/NOPB SOIC NPA 14 1000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Aug-2015
Pack Materials-Page 2
MECHANICAL DATA
NPA0014B
www.ti.com
www.ti.com
PACKAGE OUTLINE
C
8.001-8.509
[.315-.335]
4.19-4.70
[.165-.185]
0.38-1.02
[.015-.040]
SEATING PLANE
1.02 MAX
[.04 MAX]
A
8.890-9.398
[.350-.370]
2.92-3.68
[.1150-.1448]
0.711-0.864
[.028-.034]
12.7 MIN
[.5]
5.72 MAX
[.225 MAX]
8X 0.406-0.483
[.016-.019]
5.715-5.969
[.225-.235]
2.794-3.048
[.1100-.1200]
0.737-1.143
[.0291-.0450]
45 TYP
TO-CAN - 5.72 mm max heightLMG0008A
METAL CYLINDRICAL PACKAGE
4224369/B 08/2018
NOTES:
1. All linear dimensions are in millimeters [inches]. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
1
2
3
4
5
6
7
8
www.ti.com
EXAMPLE BOARD LAYOUT
(45 ) TYP
0.07 [.003] MAX
ALL AROUND
7X 0.07 [.003] MAX
ALL AROUND
( 5.842 [.230])
( 1.4 [.055])
7X ( 1.4 [.055])
METAL
8X ( 0.8 [.0315])
VIA
(R0.05 [.002]) TYP
TO-CAN - 5.72 mm max heightLMG0008A
METAL CYLINDRICAL PACKAGE
4224369/B 08/2018
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 12X
7X SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
1
2
3
4
5
6
7
8
A
SIZE
SCALE 4
PAGE
4OF
4224369 REV
B
REVISIONS ENGINEER / DRAFTERDATEECRDESCRIPTIONREV V. DASIKA / K. SINCERBOX07/10/20182174627RELEASE NEW DRAWINGA V. DASIKA / K. SINCERBOX08/17/20182175848CHANGE TO DUAL DIMENSIONING MM [INCH] FORMATB
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
