BU208A-D - ON Semiconductor

Horizontal Deflection

Transistor

. . . designed for use in televisions.

•Collector–Emitter Voltages VCES 1500 Volts

•Fast Switching — 400 ns Typical Fall Time

•Low Thermal Resistance 1C/W Increased Reliability

•Glass Passivated (Patented Photoglass). Triple Diffused Mesa

Technology for Long Term Stability

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS

ÎÎÎÎÎÎÎÎÎÎÎÎ

Rating

ÎÎÎÎÎ

Symbol

ÎÎÎÎÎÎ

BU208A

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎ

Collector–Emitter Voltage

ÎÎÎÎÎ

VCEO(sus)

ÎÎÎÎÎÎ

700

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎ

Collector–Emitter Voltage

ÎÎÎÎÎ

VCES

ÎÎÎÎÎÎ

1500

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎ

Emitter–Base Voltage

ÎÎÎÎÎ

VEB

ÎÎÎÎÎÎ

5.0

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎ

Collector Current — Continuous

— Peak

ÎÎÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎÎÎ

IC

ICM

ÎÎÎÎÎÎ

Î

ÎÎÎÎ

Î

ÎÎÎÎÎÎ

5.0

7.5

ÎÎÎ

Î

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎ

Base Current — Continuous

— Peak (Negative)

ÎÎÎÎÎ

IB

IBM

ÎÎÎÎÎÎ

4.0

3.5

ÎÎÎ

Adc

ÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎ

Total Power Dissipation @ TC = 95C

Derate above 95C

ÎÎÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎÎÎ

PD

ÎÎÎÎÎÎ

Î

ÎÎÎÎ

Î

ÎÎÎÎÎÎ

12.5

0.625

ÎÎÎ

Î

ÎÎÎ

Watts

W/C

ÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎ

Operating and Storage Junction

Temperature Range

ÎÎÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎÎÎ

TJ, Tstg

ÎÎÎÎÎÎ

Î

ÎÎÎÎ

Î

ÎÎÎÎÎÎ

–65 to +115

ÎÎÎ

Î

ÎÎÎ

C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

THERMAL CHARACTERISTICS

ÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎÎ

Symbol

ÎÎÎÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎ

Thermal Resistance, Junction to Case

ÎÎÎÎÎ

RθJC

ÎÎÎÎÎÎ

1.6

ÎÎÎ

C/W

ÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Lead Temperature for Soldering

Purpose, 1/8″ from Case for 5 Seconds

ÎÎÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎÎÎ

TL

ÎÎÎÎÎÎ

Î

ÎÎÎÎ

Î

ÎÎÎÎÎÎ

275

ÎÎÎ

Î

ÎÎÎ

C

NOTES:

1. Pulsed 5.0 ms, Duty Cycle  10%.

2. See page 3 for Additional Ratings on A Type.

3. Figures in ( ) are Standard Ratings ON Semiconductor Guarantees are Superior.

ON Semiconductor

 Semiconductor Components Industries, LLC, 2001

March, 2001 – Rev. 9 1Publication Order Number:

BU208A/D

BU208A

5.0 AMPERES

NPN SILICON

POWER TRANSISTOR

700 VOLTS

CASE 1–07

TO–204AA

(TO–3)

BU208A

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2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎÎ

Symbol

ÎÎÎÎÎ

Min

ÎÎÎÎ

Typ

ÎÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

OFF CHARACTERISTICS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Collector–Emitter Sustaining Voltage

(IC = 100 mAdc, L = 25 mH)

ÎÎÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎÎÎ

VCEO(sus)

ÎÎÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎÎÎ

700

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

—

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Collector Cutoff Current1ALL TYPES

(VCE = rated VCES, VBE = 0)

ÎÎÎÎÎ

ICES

ÎÎÎÎÎ

—

ÎÎÎÎ

—

ÎÎÎÎ

1.0

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Emitter Base Voltage1

(IC = 0, IE = 10 mAdc)

(IC = 0, IE = 100 mAdc)

ÎÎÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎÎÎ

VEBO

ÎÎÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎÎÎ

5

—

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

—

7

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ON CHARACTERISTICS1

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Current Gain

(IC = 4.5 Adc, VCE = 5 Vdc)

ÎÎÎÎÎ

hFE

ÎÎÎÎÎ

2.25

ÎÎÎÎ

—

ÎÎÎÎ

—

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Collector–Emitter Saturation Voltage

(IC = 4.5 Adc, IB = 2 Adc)

ÎÎÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎÎÎ

VCE(sat)

ÎÎÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎÎÎ

—

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

—

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

1

ÎÎÎ

Î

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Base–Emitter Saturation Voltage

(IC = 4.5 Adc, IB = 2 Adc)

ÎÎÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎÎÎ

VBE(sat)

ÎÎÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎÎÎ

—

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

—

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

1.5

ÎÎÎ

Î

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DYNAMIC CHARACTERISTICS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Current–Gain Bandwidth Product

(IC = 0.1 Adc, VCE = 5 Vdc, ftest = 1 MHz)

ÎÎÎÎÎ

fT

ÎÎÎÎÎ

—

ÎÎÎÎ

4

ÎÎÎÎ

—

ÎÎÎ

MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Capacitance

(VCB = 10 Vdc, IE = 0, ftest = 1 MHz)

ÎÎÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎÎÎ

Cob

ÎÎÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎÎÎ

—

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

125

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

pF

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Time (see test circuit fig. 1)

(IC = 4.5 Adc, IB1 = 1.8 Adc, LB = 10 µH)

ÎÎÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎÎÎ

ts

ÎÎÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎÎÎ

—

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

8

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

—

ÎÎÎ

Î

ÎÎÎ

µs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Fall time (see test circuit fig. 1)

(IC = 4.5 Adc, IB1 = 1.8 Adc, LB = 10 µH)

ÎÎÎÎÎ

tf

ÎÎÎÎÎ

—

ÎÎÎÎ

0.4

ÎÎÎÎ

—

ÎÎÎ

µs

1Pulse test: PW = 300 µs; Duty cycle  2%.

BU208A

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3

Figure 1. Switching Time Test Circuit

+40 V +40 V

1 K 1 K

1N5242 (12 V)

10 K

3

15

1

14 2

16

10 nF

2K7

3K3

2 K

220 680 nF

820 10 nF

MPSU04

10 K

100

1 µF

400 mA

100 Ω

LB

T.U.T.

680 µF

RB

0.56

1 A

1500 V

22 nF

6.5 mH Ly = 1.3 mH

0.5 µF 250 µF

7 mH 0.3 A

FUSE 130 V

POWER

SUPPLY

TBA920

80

60

40

20

040 80 120 160 200

Figure 2. Power Derating

TC, CASE TEMPERATURE (°C)

POWER DISSIPATION (W)

BU208A

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4

BASE DRIVE

The Key to Performance

By now, the concept of controlling the shape of the turn–of f base

current is widely accepted and applied in horizontal deflection

design. The problem stems from the fact that good saturation of the

output device, prior to turn–off, must be assured. This is

accomplished by providing more than enough IB1 to satisfy the

lowest gain output device hFE at the end of scan ICM. Worst–case

component variations and maximum high voltage loading must

also be taken into account.

If the base of the output transistor is driven by a very low

impedance source, the turn–off base current will reverse very

quickly as shown in Figure 3. This results in rapid, but only partial

collector turn–off, because excess carriers become trapped in the

high resistivity collector and the transistor is still conductive. This

is a high dissipation mode, since the collector voltage is rising very

rapidly. The problem is overcome by adding inductance to the base

circuit to slow the base current reversal as shown in Figure 4, thus

allowing access carrier recombination in the collector to occur

while the base current is still flowing.

Choosing the right LB Is usually done empirically since the

equivalent circuit is complex, and since there are several important

variables (ICM, IB1, and hFE at ICM). One method i s to plot fall time

as a function of LB, at the desired conditions, for several devices

within the hFE specification. A more informative method is to plot

power dissipation versus IB1 for a range of values of LB.

This shows the parameter that really matters, dissipation,

whether caused by switching or by saturation. For very low LB a

very narrow optimum is obtained. This occurs when IB1 hFE 

ICM, and therefore would be acceptable only for the “typical”

device with constant ICM. As LB is increased, the curves become

broader and flatter above the IB1. hFE = ICM point as the turn off

“tails” are brought under control. Eventually, i f LB is raised too far ,

the dissipation all across the curve will rise, due to poor initiation

of switching rather than tailing. Plotting this type of curve family

for devices of different hFE, essentially moves the curves to the

left, or right according to the relation IB1 hFE = constant. It then

becomes obvious that, for a specified ICM, an LB can be chosen

which will give low dissipation over a range of hFE and/or IB1. The

only remaining decision is to pick IB1 high enough to

accommodate the lowest hFE part specified. Neither LB nor IB1 are

absolutely critical. Due to the high gain of ON Semiconductor

devices it is suggested that in general a low value of IB1 be used to

obtain optimum efficiency — eg. for BU208A with ICM = 4.5 A

use IB1  1.5 A, at ICM = 4 A use IB1  1.2 A. These values are

lower than for most competition devices but practical tests have

showed comparable efficiency for ON Semiconductor devices

even at the higher level of IB1.

An LB of 10 µH to 12 µH should give satisfactory operation of

BU208A with ICM of 4 to 4.5 A and IB1 between 1.2 and 2 A.

TEST CIRCUIT WAVEFORMS

Figure 3. Figure 4.

IB

IC

IB

IC

(TIME) (TIME)

TEST CIRCUIT OPTIMIZATION

The test circuit may be used to evaluate devices in the

conventional manner, i.e., to measure fall time, storage time, and

saturation voltage. However, this circuit was designed to evaluate

devices by a simple criterion, power supply input. Excessive

power input can be caused by a variety of problems, but it is the

dissipation in the transistor that is of fundamental importance.

Once the required transistor operating current is determined, fixed

circuit values may be selected.

BU208A

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5

14

0.01

Figure 5. DC Current Gain

IC, COLLECTOR CURRENT (A)

4

0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10

12

10

9

8

2.8

0.1

Figure 6. Collector–Emitter Saturation Voltage

IB, BASE CURRENT CONTINUOUS (A)

0.2 0.5 1.0 2.0 10

2.4

2.0

1.6

1.2

1.6

0.1

Figure 7. Base–Emitter Saturation Voltage

IC, COLLECTOR CURRENT (A)

0.2 0.5 1.0 2.0 10

1.5

1.4

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.1

Figure 8. Collector Saturation Region

IC, COLLECTOR CURRENT (A)

0

0.2 0.5 1.0 2.0 5.0 10

0.4

0.3

0.2

0.1

IC/IB = 3

15

1

Figure 9. Maximum Forward Bias Safe Operating Area

VCE, COLLECTOR-EMITTER VOLTAGE (V)

13

11

hFE, DC CURRENT GAIN

VCE = 5 V

, COLLECTOR CURRENT (A)IC

0.001 2 5 10 20 50 100 200 500 1000 2000

1.3

7

6

5

VCE(sat) , COLLECTOR-EMITTER SATURATION

VOLTAGE (V)

IC/IB = 2

VBE, BASE-EMITTER VOLTAGE (V)

5.0

IC/IB = 2

0.8

0.4

5.0

IC = 3.5 A

IC = 2 A

IC = 3 A

IC = 4 A

IC = 4.5 A

10

5

2

1

0.5

0.2

0.1

0.05

0.02

0.01

0.005

0.002

TC ≤ 95°C

IC(max.)

ICM(max.)

1 µs

2

5

10

20

50

100

200

300

1 ms

2 ms

D.C.

BU208,A1

1Pulse width ≤ 20 µs. Duty cycle ≤ 0.25. RBE ≤ 100 Ohms.

VCE(sat) , COLLECTOR-EMITTER SATURATION

VOLTAGE (V)

BONDING WIRE LIMIT

THERMAL LIMIT

SECOND BREAKDOWN LIMIT

DUTY CYCLE ≤ 1%

BU208A

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6

PACKAGE DIMENSIONS

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. ALL RULES AND NOTES ASSOCIATED WITH

REFERENCED TO-204AA OUTLINE SHALL APPLY.

STYLE 1:

PIN 1. BASE

2. EMITTER

CASE: COLLECTOR

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A1.550 REF 39.37 REF

B--- 1.050 --- 26.67

C0.250 0.335 6.35 8.51

D0.038 0.043 0.97 1.09

E0.055 0.070 1.40 1.77

G0.430 BSC 10.92 BSC

H0.215 BSC 5.46 BSC

K0.440 0.480 11.18 12.19

L0.665 BSC 16.89 BSC

N--- 0.830 --- 21.08

Q0.151 0.165 3.84 4.19

U1.187 BSC 30.15 BSC

V0.131 0.188 3.33 4.77

A

N

E

C

K

–T– SEATING

PLANE

2 PL

D

M

Q

M

0.13 (0.005) Y M

T

M

Y

M

0.13 (0.005) T

–Q–

–Y–

2

1

UL

GB

V

H

CASE 1–07

TO–204AA (TO–3)

ISSUE Z

BU208A

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7

Notes

BU208A

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8

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BU208A/D

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