Powerful Energy Meter Chipset ADSST-SALEM-3T chipset can be interfaced to any general-purpose microprocessor to develop state of the art tri-vector or polyphase energy metering solutions with a wide range of basic currents from 1 A to 30 A. By incorporating a comprehensive data set of parameters, including instantaneous measurements, accumulated parameters, and harmonic analysis data, the ADSST-SALEM-3T chipset meets high end energy metering requirements. The ability to easily configure the chipset for various parameters makes it a very flexible solution. FEATURES High accuracy Supports IEC 60687/61036 and ANSI C12.1/12.20 Suitable for class0.5 and class0.2 meter Full four quadrant measurement of parameters SPI(R) compatible serial interface Pulse output with programmable pulse constant as pulses/kWh or Wh/pulse Programmable duty cycle for pulse output Embedded calibration routines for gain and dc offset Software based phase and nonlinearity compensation for current transformers 15 kHz sampling frequency UART mode enables a PC to directly access all computed parameters Flags to indicate tamper conditions Single 3.0 V supply Developer's kit to accelerate design process (See Ordering Guide for separate ordering number.) The phase and nonlinearity compensation for current transformers is done in software (patent pending) without having to use any passive components in the circuit for compensation, thus minimizing variations in accuracy with temperature and time. The ADSST-SALEM-3T measures and computes a large number of parameters essential for high end metering. Table 1. GENERAL DESCRIPTION The ADSST-SALEM-3T energy meter chipset consists of an efficient ADSST-218x digital signal processor (DSP), a fast and accurate 6-channel, 16-bit ADSST-73360LAR sigma-delta analog-to-digital converter (ADC), and metering software. Two chipset versions are available to support differing ranges of operating temperature: The ADSST-EM-3040 chipset is rated at 0C to 70C for commercial applications, while the ADSST-EM3041 chipset operates at -25C to +85C for industrial use. LCD DISPLAY SPI BUS RESISTOR BLOCK DSP CT ADC CT CT C BUTTONS SMPS BOOT FLASH FLASH OPTO ADSST-EM-3040 RTC RS-232 03738-0-001 Parameter RMS Voltage RMS Current Active Power Apparent Power Inductive Reactive Power Capacitive Reactive Power Power Factor Frequency Positive Active Energy Negative Active Energy Apparent Energy Positive Inductive Reactive Energy Negative Inductive Reactive Energy Positive Capacitive Reactive Energy Negative Capacitive Reactive Energy Voltage Magnitude and Phase for All Odd Harmonics up to 21st Order Current Magnitude and Phase for All Odd Harmonics up to 21st Order Each Phase Total Figure 1. Block Diagram of a Functional Meter The ADC and DSP are interfaced to simultaneously acquire voltage and current samples on all three phases and to perform mathematically intensive computations to calculate various instantaneous parameters and perform harmonic analysis. The The ADSST-SALEM-3T offers some excellent features that make the final meter cost-effective and easy to manufacture. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved. ADSST-SALEM-3T TABLE OF CONTENTS Easy Calibration............................................................................ 3 General Description of the ADSST-73360LAR ADC................ 11 Effective Phase Compensation ................................................... 3 Specifications--ADSST-73360LAR ............................................. 12 Ease of Design............................................................................... 3 Quadrant and Other Conventions ............................................. 3 Absolute Maximum Ratings--ADSST-73360LAR .................... 14 ESD Caution................................................................................ 14 General Description of the ADSST-218x DSP ......................... 4 Pin Configuration and Pin Function Descriptions-- ADSST-73360LAR.......................................................................... 15 Architecture Overview ................................................................ 4 Pin Function Descriptions ........................................................ 15 ADSST-218x Common-Mode Pins ........................................... 6 Grounding and Layout .............................................................. 16 Clock Signals ................................................................................. 7 Power-Up Initialization and Data from the ADSST-SALEM-3T.................................................................... 17 RESET ............................................................................................ 7 Recommended Operating Conditions ...................................... 7 ADSST-218x Electrical Characteristics ......................................... 8 Absolute Maximum Ratings--ADSST-218x................................. 9 ESD Caution.................................................................................. 9 Voltage and Current Sensing .................................................... 17 Accuracy of Reference Design Using the ADSST-SALEM-3T Chipset ..................................................... 18 Outline Dimensions ....................................................................... 20 Ordering Guide............................................................................... 21 Pin Configuration--ADSST-218x................................................ 10 REVISION HISTORY 7/04--Revision 0: Initial Version Rev. 0 | Page 2 of 24 ADSST-SALEM-3T EASY CALIBRATION EASE OF DESIGN The ADSST-SALEM-3T chipset has highly advanced calibration routines embedded into the software. Ease of calibration is the key feature in this chipset. By sending specific commands to the ADSST-SALEM-3T chipset, the dc offsets and gains for all voltage and current channels can be calibrated automatically. Active and reactive power calibration is also available for fine-tuning the errors. Designing a complete meter using the ADSST-SALEM-3T is very easy with the ADSST-SALEM-3T-DK developer's kit. The kit in the UART mode enables a user to evaluate and test the computational element by connecting to a PC, without building the complete hardware. QUADRANT AND OTHER CONVENTIONS The metering data computed by the ADSST-SALEM-3T chipset uses the following conventions for various parameters: The meter and calibration constants are stored in an external flash memory, and the lock/unlock calibration feature enables protection of the calibration constants. The ability to upgrade the firmware residing in the flash memory makes the meter adaptable to future needs. EFFECTIVE PHASE COMPENSATION The ADSST-SALEM-3T chipset employs an algorithm (patent pending) for phase compensation. The ADSST-SALEM3T chipset based meter, which is very effective and user friendly, can be calibrated for phase compensation at three current points to cover the complete current range. This also reduces the cost of the end product by reducing the cost of the sensing elements, i.e., current transformers. * Figure 2 gives the quadrant conventions used by the chipset. * Import means power delivered from the utility to the user. * Export means power delivered by the user to the utility. * Total means total of all three phases. Import and export are with reference to consumption. U, I: P: Q: : Magnitude of voltage and current Active Power (U x I x cos ) Reactive Power (U x I x sin ) Phase angle from the standpoint of I with respect to U, always positive in counterclockwise direction. Phase U: L1 = 0 Abs L2 = 240 Abs L3 = 120 Abs ACTIVE IMPORT ACTIVE EXPORT REACTIVE SIN = -1 P-Q- REACTIVE EXPORT QUADRANT II (-90 ) (90 ABS) ACTIVE CAPACITIVE (LEAD) P+Q- QUADRANT I ACTIVE COS = -1 (180 ) (180 ABS) REACTIVE IMPORT ACTIVE COS = +1 I IQ QUADRANT III P-Q+ REACTIVE SIN = +1 (0 ) (0 ABS) QUADRANT IV P+Q+ ACTIVE INDUCTIVE (LAG) (+90 ) (270 ABS) L1, L2, L3 Figure 2. Quadrant Conventions Rev. 0 | Page 3 of 24 03738- 0- 002 ADSST-SALEM-3T GENERAL DESCRIPTION OF THE ADSST-218X DSP This takes place while the processor continues to: The ADSST-218x is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications. * Receive and transmit data through the two serial ports * Receive and/or transmit data through the internal DMA port * Receive and/or transmit data through the byte DMA port * Decrement timer The DSP combines the ADSP-2100 family base architecture (three computational units, data address generators, and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, flag I/O, extensive interrupt capabilities, and on-chip program and data memory. ARCHITECTURE OVERVIEW The ADSST-218x instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every instruction can be executed in a single processor cycle. The ADSST-218x assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development. The ADSST-218x is fabricated in a high speed, low power CMOS process. Every instruction can execute in a single processor cycle. The ADSST-218x's flexible architecture and comprehensive instruction set enable the processor to perform multiple operations in parallel. In one processor cycle, the ADSST-218x can: * Generate the next program address * Fetch the next instruction * Perform one or two data moves * Update one or two data address pointers * Perform a computational operation Figure 3 is the functional block diagram of the ADSST-218x. The processor contains three independent computational units: the ALU, the multiplier/accumulator (MAC), and the shifter. The computational units process 16-bit data directly and have provisions to support multiprecision computations. POWER-DOWN CONTROL FULL MEMORY MODE MEMOR Y DATA ADDRESS GENERATORS DAG1 DAG2 PROGRAM SEQUENCER PROGRAM MEMORY 16K x 24-BIT DATA MEMORY 16K x 16-BIT PROGRAMMABLE I/O AND FLAGS EXTERNAL ADDRESS BUS EXTERNAL DATA BUS PROGRAM MEMORY ADDRESS BYTE DMA CONTROLLER DATA MEMORY ADDRESS PROGRAM MEMORY DATA OR DATA MEMORY DATA ARITHMETIC UNITS ALU MAC SHIFTER SERIAL PORTS SPORT0 TIMER SPORT1 ADSP-2100 BASE ARCHITECTURE EXTERNAL DATA BUS INTERNAL DMA PORT HOST MODE 03738- 0- 008 Figure 3. Functional Block Diagram Rev. 0 | Page 4 of 24 ADSST-SALEM-3T Efficient data transfer is achieved with the use of five internal buses: * Program Memory Address (PMA) Bus Program Memory Data (PMD) Bus * Data Memory Address (DMA) Bus * Data Memory Data (DMD) Bus * Result (R) Bus The ADSST-218x can respond to 11 interrupts. There are up to six external interrupts (one edge sensitive, two level sensitive, and three configurable) and seven internal interrupts generated by the timer, the serial ports (SPORTs), the byte DMA port, and the power-down circuitry. There is also a master RESET signal. The two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. Serial Ports The byte memory and I/O memory space interface supports slow memories and I/O memory-mapped peripherals with programmable wait state generation. External devices can gain control of external buses with bus request/grant signals (BR, BGH, and BG0). One execution mode (go mode) enables the ADSST-218x to continue running from on-chip memory. Normal execution mode requires the processor to halt while buses are granted. The ADSST-218x incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Package Description The ADSST-218x is available in a 100-lead low profile quad flat package (LQFP, refer to Figure 5). Rev. 0 | Page 5 of 24 ADSST-SALEM-3T ADSST-218X COMMON-MODE PINS Table 2. Pin Name BG BGH BMS BR CMS DMS IOMS PMS RD RESET WR No. of Pins 1 1 1 1 1 1 1 1 1 1 1 I/O O O O I O O O O O I O Function Bus Grant Output Bus Grant Hung Output Byte Memory Select Output Bus Request Input Combined Memory Select Output Data Memory Select Output Memory Select Output Program Memory Select Output Memory Read Enable Output Processor Reset Input Memory Write Enable Output IRQ2/ PF7 IRQL1/ PF6 IRQL0/ PF5 IRQE/ PF4 MODE A PF0 MODE B PF1 MODE C PF2 MODE D PF3 CLKIN, XTAL CLKOUT EZ-Port FI, FO FL0, FL1, FL2 GND IRQ1:0 PWD SPORT0 SPORT1 PWDACK VDDEXT VDDEXT VDDINT VDDINT 1 2 1 9 I I/O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I O I/O 3 10 O I 1 5 5 1 4 7 2 4 I I/O I/O O I I I I Edge- or Level-Sensitive Interrupt Request1 Programmable I/O Pin Level-Sensitive Interrupt Requests1 Programmable I/O Pin Level-Sensitive Interrupt Requests1 Programmable I/O Pin Edge-Sensitive Interrupt Requests1 Programmable I/O Pin Mode Select Input-Checked only during RESET Programmable I/O Pin during Normal Operation Mode Select Input-Checked only during RESET Programmable I/O Pin during Normal Operation Mode Select Input-Checked only during RESET Programmable I/O Pin during Normal Operation Mode Select Input-Checked only during RESET Programmable I/O Pin during Normal Operation Clock or Quartz Crystal Input Processor Clock Output For Emulation Use Flag In, Flag Out2 Output Flags Power and Ground Edge- or Level-Sensitive Interrupts Power-Down Control Input Serial Port I/O Pins Serial Port I/O Pins Power-Down Control Output External VDD (2.5 V or 3.3 V) Power (LQFP) External VDD (2.5 V or 3.3 V) Power (Mini-BGA) Internal VDD (2.5 V) Power (LQFP) Internal VDD (2.5 V) Power (Mini-BGA) 1 1 1 1 1 1 1 1 Interrupt/flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices or set as a programmable flag. SPORT configuration determined by the DSP System Control register. Software configurable. 2 Rev. 0 | Page 6 of 24 ADSST-SALEM-3T CLOCK SIGNALS RESET Either a crystal or a TTL compatible clock signal can clock the ADSST-218x. The RESET signal initiates a master reset of the ADSST-2185x. The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to enable the internal clock to stabilize. If RESET is activated any time after power-up, the clock continues to run and does not require stabilization time. If an external clock is used, it should be a TTL compatible signal running at half the instruction rate. The signal is connected to the processor's CLKIN input. When an external clock is used, the XTAL input must be left unconnected. Because the ADSST-218x includes an on-chip oscillator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 4. The capacitor values are dependent on the crystal type and should be specified by the crystal manufacturer. A parallel resonant, fundamental frequency, microprocessor grade crystal should be used. A clock output (CLKOUT) signal is generated by the processor at the processor's cycle rate. This can be enabled and disabled by the CLKODIS bit in the SPORT0 autobuffer control register. The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency. A minimum of 2000 CLKIN cycles ensures that the PLL has locked but does not include the crystal oscillator start-up time. During this power-up sequence, the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the minimum pulse-width specification, tRSP. The RESET input contains some hysteresis; however, if an RC circuit is used to generate the RESET signal, the use of an external Schmitt trigger is recommended. RECOMMENDED OPERATING CONDITIONS CLKIN XTAL CLKOUT DSP 03738- 0- 003 Figure 4. External Crystal Connections Table 3. Parameter VDDINT VDDEXT VINPUT1 TAMB 1 Min 2.37 2.37 VIL = -0.3 0 Max 2.63 3.60 VIH = 3.6 70 Unit V V V C The ADSST-2185x is 3.3 V tolerant (always accepts up to 3.6 V max VIH), but voltage compliance (on output, VOH) depends on the input VDDEXT; because VOH (MAX) = VDDEXT (MAX). This applies to bidirectional pins (D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, A1-A13, PF0-PF7) and input only pins (CLKIN, RESET, BR, DR0, DR1, PWD). Rev. 0 | Page 7 of 24 ADSST-SALEM-3T ADSST-218X ELECTRICAL CHARACTERISTICS Table 4. Parameter VIH High Level Input Voltage1, 2 VIH High Level CLKIN Voltage VIL Low Level Input Voltage1, 3 VOH High Level Output Voltage1, 4, 5 VOL Low Level Output Voltage1, 4, 5 IIH High Level Input Current3 IIL Low Level Input Current3 IOZH Three-State Leakage Current7 IOZL Three-State Leakage Current7 IDD Supply Current (Idle)9 IDD Supply Current (Dynamic)10 IDD Supply Current (Power-Down)12 CI Input Pin Capacitance3, 6 CO Output Pin Capacitance6, 7, 12, 13 Test Conditions @ VDDINT = Max @ VDDINT = Max @ VDDINT = Min @ VDDEXT = Min, IOH = -0.5 mA @ VDDEXT = 3.0 V, IOH = -0.5 mA @ VDDEXT = Min, IOH = -100 A6 @ VDDEXT = Min, IOL = 2 mA @ VDDINT = Max, VIN = 3.6 V @ VDDINT = Max, VIN = 0 V @ VDDEXT = Max, VIN = 3.6 V8 @ VDDEXT = Max, VIN = 0 V8 @ VDDINT = 2.5 V, tCK = 15 ns @ VDDINT = 2.5 V, tCK = 13.3 ns @ VDDINT = 2.5 V, tCK = 13.3 ns11, TAMB = +25C @ VDDINT = 2.5 V, tCK = 15 ns11, TAMB = +25C @ VDDINT = 2.5 V, TAMB = +25C in Lowest Power Mode @ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = +25C @ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = +25C 1 Min 1.5 2.0 Typ Max 0.7 2.0 2.4 VDDEXT - 0.3 0.4 10 10 10 10 9 10 35 38 100 8 8 Unit V V V V V V V A A A A mA mA mA mA mA pF pF Bidirectional pins: D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1-A13, PF0-PF7. Input only pins: RESET, BR, DR0, DR1, PWD. 3 Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD. 4 Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH. 5 Although specified for TTL outputs, all ADSP-2186 outputs are CMOS compatible and will drive to VDDEXT and GND, assuming no dc loads. 6 Guaranteed but not tested. 7 Three-statable pins: A0-A13, D0-D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0-PF7. 8 0 V on BR. 9 Idle refers to ADSST-218x state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND. 10 IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2 and Type 6, and 20% are idle instructions. 11 VIN = 0 V and 3 V. For typical figures for supply currents, refer to the Power Dissipation section. 12 Applies to LQFP package type. 13 Output pin capacitance is the capacitive load for any three-stated output pin. 2 Rev. 0 | Page 8 of 24 ADSST-SALEM-3T ABSOLUTE MAXIMUM RATINGS--ADSST-218X Table 5. Rating Parameter Internal Supply Voltage (VDDINT) External Supply Voltage (VDDEXT) Input Voltage1 Output Voltage Swing2 Operating Temperature Range Storage Temperature Range Min -0.3 V -0.3 V -0.3 V -0.5 V 0C -65C Max +3.0 V +4.0 V +4.0 V VDDEXT + 0.5 V 70C +150C 1 Applies to bidirectional pins (D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1-A13, PF0-PF7) and input-only pins (CLKIN, RESET, BR, DR0, DR1, PWD). 2 Applies to output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-FL0, BGH). Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 9 of 24 ADSST-SALEM-3T A4/IAD3 1 A5/IAD4 2 GND 3 A6/IAD5 4 A7/IAD6 5 A8/IAD7 6 A9/IAD8 7 A10/IAD9 8 A11/IAD10 9 78 D18 77 D17 76 D16 80 GND 79 D19 83 D22 82 D21 81 D20 84 D23 86 FL1 85 FL2 87 FL0 89 PF2 [MODE C] 88 PF3 [MODE D] 91 PWD 90 VDDEXT 92 GND 94 PF0 [MODE A] 93 PF1 [MODE B] 95 BGH 96 PWDACK 98 A1/IAD0 97 A0 100 A3/IAD2 99 A2/IAD1 PIN CONFIGURATION--ADSST-218X 75 D15 74 D14 PIN 1 IDENTIFIER 73 D13 72 D12 71 GND 70 D11 69 D10 68 D9 67 VDDEXT A12/IAD11 10 66 GND A13/IAD12 11 65 D8 64 D7/IWR GND 12 ADSST-218x CLKIN 13 63 D6/IRD TOP VIEW (Not to Scale) XTAL 14 VDDEXT 15 62 D5/IAL 61 D4/IS CLKOUT 16 60 GND 59 VDDINT GND 17 58 D3/IACK VDDINT 18 WR 19 RD 20 57 D2/IAD15 BMS 21 55 D0/IAD13 DMS 22 PMS 23 54 BG 53 EBG IOMS 24 CMS 25 52 BR 51 EBR Figure 5. Pin Configuration for ADSST-218x in 100-Lead LQFP Rev. 0 | Page 10 of 24 EINT 50 ELIN 49 ELOUT 48 EE 46 ECLK 47 EMS 45 SCLK1 42 ERESET 43 RESET 44 GND 41 DR1/FI 40 RFS1/IRQ0 39 VDDEXT 36 DT1/FO 37 TFS1/IRQ1 38 DR0 34 SCLK0 35 RFS0 33 TFS0 32 IRQ2+PF7 30 DT0 31 GND 28 IRQL1+PF6 29 IRQE+PF4 26 IRQL0+PF5 27 56 D1/IAD14 03738- 0- 009 ADSST-SALEM-3T GENERAL DESCRIPTION OF THE ADSST-73360LAR ADC The ADSST-73360LAR is particularly suitable for industrial power metering as each channel samples synchronously, ensuring that there is no (phase) delay between the conversions. The ADSST-73360LAR also features low group delay conversions on all channels. The ADSST-73360LAR is a 6-channel input analog front end processor for general-purpose applications, including industrial power metering or multichannel analog inputs. It features six 16-bit A/D conversion channels, each of which provides 76 dB signal-to-noise ratio over a dc to 4 kHz signal bandwidth. Each channel also features an input programmable gain amplifier (PGA) with gain settings in eight stages from 0 dB to 38 dB. VINP1 SIGNAL CONDITIONING 0/38DB PGA VINN1 An on-chip reference voltage is included with a nominal value of 1.2 V. The ADSST-73360LAR is available in a 28-lead SOIC package. SIGNAL - CONDITIONING DECIMATOR SDI SDIFS SCLK VINP2 SIGNAL CONDITIONING 0/38DB PGA SIGNAL - CONDITIONING DECIMATOR SIGNAL CONDITIONING 0/38DB PGA SIGNAL - CONDITIONING DECIMATOR VINN2 VINP3 VINN3 REFCAP REFERENCE RESET ADSST-73360LAR REFOUT VINP4 SIGNAL CONDITIONING 0/38DB PGA SIGNAL - CONDITIONING DECIMATOR SIGNAL CONDITIONING 0/38DB PGA SIGNAL - CONDITIONING DECIMATOR VINN4 VINP5 VINN5 MCLK SE SDO SDOFS VINP6 SIGNAL CONDITIONING VINN6 SERIAL I/O PORT 0/38DB PGA SIGNAL - CONDITIONING DECIMATOR 03738- 0- 004 Figure 6. ADSST-73360LAR Functional Block Diagram Rev. 0 | Page 11 of 24 ADSST-SALEM-3T SPECIFICATIONS--ADSST-73360LAR (AVDD = 2.7 V to 3.6 V, DVDD = 2.7 V to 3.6 V, DGND = AGND = 0 V, fMCLK = 16.384 MHz, fSCLK = 8.192 MHz, fS = 8 kHz, TA = TMIN to TMAX1, unless otherwise noted.) Table 6. Parameter REFERENCE REFCAP Absolute Voltage, VREFCAP REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, VREFOUT Minimum Load Resistance Maximum Load Capacitance ADC SPECIFICATIONS Maximum Input Range at VIN 2, 3 Min Typ Max Unit Test Conditions 1.08 1.2 50 1.32 V ppm/C 0.1 F Capacitor Required from REFCAP to AGND2 1.08 1 PGA = 38 dB Total Harmonic Distortion PGA = 0 dB PGA = 38 dB Intermodulation Distortion Idle Channel Noise Crosstalk ADC-to-ADC DC Offset Power Supply Rejection Group Delay4, 5 Input Resistance at VIN2, 4 Phase Mismatch 1.32 100 Nominal Reference Level at VIN (0 dBm0) Absolute Gain PGA = 0 dB PGA = 38 dB Signal to (Noise + Distortion) PGA = 0 dB PGA = 0 dB 130 1.2 1.578 -2.85 1.0954 V p-p dBm V p-p -6.02 dBm -1.3 -0.8 71 V k pF +0.6 +0.8 Unloaded Measured Differentially Measured Differentially dB dB 1.0 kHz 1.0 kHz 76 76 dB dB 58 dB 0 Hz to 4 kHz; fS = 8 kHz 0 Hz to 2 kHz; fS = 8 kHz fIN = 60 kHz 0 Hz to 4 kHz; fS = 64 kHz -80 -64 -78 -68 -95 -71 -55 dB dB dB dB dB mV dB 25 50 95 190 25 0.15 0.01 s s s s k6 Degrees Degrees -30 +30 Rev. 0 | Page 12 of 24 0 Hz to 2 kHz; fS = 8 kHz; fIN = 60 kHz 0 Hz to 2 kHz; fS = 64 kHz; fIN = 60 kHz PGA = 0 dB PGA = 0 dB, fS = 64 kHz; SCLK = 16 MHz ADC1 at Idle; ADC2 to ADC6 Input Signal: 60 Hz PGA = 0 dB Input Signal Level at AVDD and DVDD Pins 1.0 kHz, 100 mV p-p Sine Wave 64 kHz Output Sample Rate 32 kHz Output Sample Rate 16 kHz Output Sample Rate 8 kHz Output Sample Rate DMCLK = 16.384 MHz fIN = 1 kHz fIN = 60 Hz ADSST-SALEM-3T Parameter FREQUENCY RESPONSE (ADC)7 Typical Output Frequency (Normalized to fS) 0 0.03125 0.0625 0.125 0.1875 0.25 0.3125 0.375 0.4375 > 0.5 LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IIH, Input Current CIN, Input Capacitance LOGIC OUTPUT VOH, Output High Voltage VOL, Output Low Voltage Three-State Leakage Current POWER SUPPLIES AVDD1, AVDD2 DVDD IDD8 Min Typ Max 0 -0.1 -0.25 -0.6 -1.4 -2.8 -4.5 -7.0 -9.5 < -12.5 Unit Test Conditions dB dB dB dB dB dB dB dB dB dB VDD - 0.8 0 VDD 0.8 10 10 V V A pF VDD - 0.4 0 -10 VDD 0.4 +10 V V A 2.7 2.7 3.6 3.6 V V |IOUT| 100 A |IOUT| 100 A See Table 7 1 Operating temperature range is as follows: -40C to +85C. Therefore, TMIN = -40C and TMAX = +85C. Test conditions: Input PGA set for 0 dB gain (unless otherwise noted). 3 At input to sigma-delta modulator of ADC. 4 Guaranteed by design. 5 Overall group delay will be affected by the sample rate and the external digital filtering. 6 The ADC's input impedance is inversely proportional to DMCLK and is approximated by: (4 x 1011)/DMCLK. 2 7 Frequency response of the ADC measured with input at audio reference level (the input level that produces an output level of 0 dBm0), with 38 dB preamplifier bypassed and input gain of 0 dB. 8 Test Conditions: no load on digital inputs, analog inputs ac-coupled to ground. Table 7. Current Summary (AVDD = DVDD = 3.3 V) Conditions ADCs Only On REFCAP Only On REFCAP and REFOUT Only On All Sections On All Sections Off All Sections Off Digital Current, Max (mA) 25 1.0 3.5 26.5 1.0 0.05 SE 1 0 0 1 1 0 MCLK ON Yes No No Yes Yes No Comments REFOUT Disabled REFOUT Disabled REFOUT Enabled MCLK Active Levels Equal to 0 V and DVDD Digital Inputs Static and Equal to 0 V or DVDD The above values are in mA and are typical values, unless otherwise noted. MCLK = 16.384 MHz; SCLK = 16.384 MHz. Rev. 0 | Page 13 of 24 ADSST-SALEM-3T ABSOLUTE MAXIMUM RATINGS--ADSST-73360LAR (TA = 25C unless otherwise noted) Table 8. Parameter AVDD, DVDD to GND AGND to DGND Digital I/O Voltage to DGND Analog I/O Voltage to AGND Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Thermal Impedance JA (SOIC) Rating -0.3 V to +4.6 V -0.3 V to +0.3 V -0.3 V to DVDD + 0.3 V -0.3 V to AVDD 0C to +70C -65C to +150C 150C 75C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. . ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 14 of 24 ADSST-SALEM-3T PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS--ADSST-73360LAR VINP2 1 28 VINN3 VINN2 2 27 VINP3 VINP1 3 26 VINN4 TOP VIEW VINN1 4 (Not to Scale) 25 VINP4 REFOUT 5 24 VINN5 REFCAP 6 23 VINP5 AVDD2 7 22 VINN6 AGND2 8 21 VINP6 DGND 9 20 AVDD1 DVDD 10 19 AGND1 RESET 11 18 SE SCLK 12 17 SDI MCLK 13 16 SDIFS SDO 14 15 SDOFS NC = NO CONNECT 03738- 0- 005 Figure 7. ADSST-73360LAR Pin Configuration--RW-28 PIN FUNCTION DESCRIPTIONS Table 9. Pin No. 1 2 3 4 5 6 Mnemonic VINP2 VINN2 VINP1 VINN1 REFOUT REFCAP 7 8 9 10 11 AVDD2 AGND2 DGND DVDD RESET 12 SCLK 13 14 MCLK SDO 15 SDOFS 16 SDIFS 17 SDI Function Analog Input to the Positive Terminal of Input Channel 2. Analog Input to the Negative Terminal of Input Channel 2. Analog Input to the Positive Terminal of Input Channel 1. Analog Input to the Negative Terminal of Input Channel 1. Buffered Output of the Internal Reference, which has a nominal value of 1.2 V. Reference Voltage for ADCs. A bypass capacitor to AGND2 of 0.1 F is required for the on-chip reference. The capacitor should be fixed to this pin. The internal reference can be overdriven by an external reference connected to this pin if required. Analog Power Supply Connection. Analog Ground/Substrate Connection. Digital Ground/Substrate Connection. Digital Power Supply Connection. Active Low Reset Signal. This input resets the entire chip, resetting the control registers and clearing the digital circuitry. Output Serial Clock whose rate determines the serial transfer rate to/from the ADSST73360LAR. It is used to clock data or control information to and from the serial port (SPORT). The frequency of SCLK is equal to the frequency of the master clock (MCLK) divided by an integer number that is the product of the external master clock rate divider and the serial clock rate divider. Master Clock Input. MCLK is driven from an external clock signal. Serial Data Output of the ADSST-73360LAR. Both data and control information may be output on this pin and are clocked on the positive edge of SCLK. SDO is in three-state when no information is being transmitted and when SE is low. Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and it is active one SCLK period before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK. SDOFS is in three-state when SE is low. Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and it is valid one SCLK period before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and is ignored when SE is low. Serial Data Input of the ADSST-73360LAR. Both data and control information may be input on this pin and are clocked on the negative edge of SCLK. SDI is ignored when SE is low. Rev. 0 | Page 15 of 24 ADSST-SALEM-3T Pin No. 18 Mnemonic SE 19 20 21 22 23 24 25 26 27 28 AGND1 AVDD1 VINP6 VINN6 VINP5 VINN5 VINP4 VINN4 VINP3 VINN3 Function SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the output pins of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled internally in order to decrease power dissipation. When SE is brought high, the control and data registers of the SPORT are at their original values (before SE was brought low); however, the timing counters and other internal registers are at their reset values. Analog Ground Connection. Analog Power Supply Connection. Analog Input to the Positive Terminal of Input Channel 6. Analog Input to the Negative Terminal of Input Channel 6. Analog Input to the Positive Terminal of Input Channel 5. Analog Input to the Negative Terminal of Input Channel 5. Analog Input to the Positive Terminal of Input Channel 4. Analog Input to the Negative Terminal of Input Channel 4. Analog Input to the Positive Terminal of Input Channel 3. Analog Input to the Negative Terminal of Input Channel 3. GROUNDING AND LAYOUT Since the analog inputs to the ADSST-73360LAR are differential, most of the voltages in the analog modulator are common-mode voltages. The excellent common-mode rejection of the part will remove common-mode noise on these inputs. The analog and digital supplies of the ADSST-73360LAR are independent and separately pinned out to minimize coupling between analog and digital sections of the device. The digital filters on the encoder section provide rejection of broadband noise on the power supplies, except at integer multiples of the modulator sampling frequency. The digital filters also remove noise from the analog inputs, provided the source does not saturate the analog modulator. However, because the resolution of the ADSST-73360LAR's ADC is high and the noise levels from the ADSST-73360LAR are so low, care must be taken with regard to grounding and layout. The printed circuit board that houses the ADSST-73360LAR should be designed in such a way that the analog and digital sections are separated and confined to certain sections of the board. The ADSST-73360LAR pin configuration offers a major advantage in that its analog and digital interfaces are connected on opposite sides of the package. This facilitates the use of ground planes that can be easily separated, as shown in Figure 8. ANALOG GROUND DIGITAL GROUND 03738- 0- 006 Figure 8. Ground Plane Layout A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should be joined in only one place. If this connection is close to the device, it is recommended to use a ferrite bead inductor as shown in Figure 9. Avoid running digital lines under the device for they will couple noise onto the die. The analog ground plane should be enabled to run under the ADSST-73360LAR to avoid noise coupling. The power supply lines to the ADSST-73360LAR should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply lines. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feed-through through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the other side. Good decoupling is important when using high speed devices. All analog and digital supplies should be decoupled to AGND and DGND, respectively, with 0.1 F ceramic capacitors in parallel with 10 F tantalum capacitors. To achieve the best from these decoupling capacitors, they should be placed as close as possible to the device, ideally right up against it. In systems where a common supply voltage is used to drive both the AVDD and DVDD of the ADSST-73360LAR, it is recommended that the system's AVDD supply be used. This supply should have the recommended analog supply decoupling between the AVDD pins of the ADSST-73360LAR and AGND, and the recommended digital supply decoupling capacitors between the DVDD pin and DGND. Rev. 0 | Page 16 of 24 ADSST-SALEM-3T POWER-UP INITIALIZATION AND DATA FROM THE ADSST-SALEM-3T The ADSST-SALEM-3T-EV boot loads the code from the nonvolatile flash memory as shown in the block diagram of a functional meter in Figure 1. The configuration and calibration data also gets loaded from the nonvolatile memory. For further details on boot loading, refer to the ADSST-SALEM-3TDK (Developer's Kit) User Manual. The user manual also describes various commands for instantaneous and computed parameters. Figure 9 shows the input section for the voltage and current sections. Based on the voltage and current values, the GUI software in the ADSST-SALEM-3T-DK computes the values of resistors R1, R2, and R3. The closest available values to those calculated by the GUI software should be selected and used. VOLTAGE INPUT * Handle high surge voltages * Have minimum VA burden * Give approximately 1 V peak headroom to accommodate overvoltages. Current Section R1 TO ADC CHANNEL R2 NEUTRAL The selection of CT ratio and burden resistance should be such that it can: * Handle the complete dynamic range for the current signal input. CURRENT INPUT PHASE CURRENT Potential Section The selection of the potential divider circuit should be such that it can: VOLTAGE AND CURRENT SENSING PHASE VOLTAGE The ADSST-73360LAR has a peak-to-peak input range of VREF - (VREF x 0.6525) to VREF + (VREF x 0.6525); for VREF = 2.5 V, this is 0.856 V to 4.14 V p-p. This limit defines the resistance network on the potential circuits and the burden resistance on the secondary side of the CT. Since the ADSST-73360LAR is a unipolar ADC, the ac potential and current signals have to be offset by some dc level. The reference design has a dc offset of 2.5 V. This limits the peak-to-peak signal range of potential and current to 3.28 V p-p or 1.16 V rms. TO ADC CHANNEL R3 * Give approximately 1 V peak headroom to accommodate loads with high crest factors. NEUTRAL 03738-0-007 Figure 9. Input Section The reference design has a CT with a turns ratio of 1:2500 and burden resistance of 82 . This generates 0.656 V rms or 0.928 V peak at 20 A current. This leaves enough margin for current pulses or low crest factor loads, such as SMPS. The maximum current can be up to 32.768 A. Rev. 0 | Page 17 of 24 ADSST-SALEM-3T ACCURACY OF REFERENCE DESIGN USING THE ADSST-SALEM-3T CHIPSET Overall Accuracy, Power, and Energy Measurement The accuracy figures are measured under typical specified conditions, unless otherwise indicated. Table 10. Test Conditions for Reference Design Using a Metal CT of Class 0.5 Accuracy Parameter Nominal Voltage (Phase to Neutral) VN Maximum Voltage (Phase to Neutral) Nominal Current Maximum Current IMAX Frequency Temperature Nominal Value VN = 230 V 1% 300 V IN = 5 A IMAX = 20 A FN = 50 Hz/60 Hz 10% 23 2C Table 11. Maximum Error (Power and Energies) Current 0.01 IN I < 0.05 IN 0.05 IN I < IMAX 0.02 IN I< 0.1 IN Voltage VN VN VN 0.05 IN I < IMAX VN PF 1.0 1.0 0.5 Lagging 0.8 Leading 0.5 Lagging 0.8 Leading Min PF 1.0 0.5 Lagging Min PF 1.0 0.5 Lagging Min PF 1.0 0.5 Lagging Min Typ Max 0.1 0.1 0.15 0.15 0.1 0.1 0.2 0.2 0.35 0.35 0.2 0.2 Unit % % % % % % Table 12. Unbalanced Load Error Current 0.05 IN I IMAX 0.1 IN I IMAX Voltage VN VN Typ Max 0.15 0.15 0.2 0.2 Unit % % Table 13. Voltage Variation Error Voltage Current VN 10% VN 10% 0.05 IN I IMAX 0.1 IN I IMAX Typ Max 0.05 0.05 0.1 0.1 Unit % % Table 14. Frequency Variation Errors Frequency Current fN 10% fN 10% 0.05 IN I IMAX 0.1 IN I IMAX Typ Max 0.05 0.05 0.1 0.1 Typ Max 0.05 0.1 Unit % % Table 15. Harmonic Distortion Error Current 10% of 3rd Harmonic Current Min 0.05 IN I IMAX Unit % Table 16. Reverse Phase Sequence Error Current 0.1 IN Voltage VN Min Typ Max 0.05 Rev. 0 | Page 18 of 24 Unit % ADSST-SALEM-3T Table 17. Voltage Unbalance Error Current IN Voltage VN + 15% V Min Typ 0.07 Max 0.1 Typ Max 0.1 0.2 Table 18. Starting Current Min Rev. 0 | Page 19 of 24 Unit % of IN Unit % ADSST-SALEM-3T OUTLINE DIMENSIONS 16.00 BSC SQ 1.60 MAX 0.75 0.60 0.45 SEATING PLANE 14.00 BSC SQ 100 1 12 TYP 76 75 PIN 1 12.00 REF TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 10 6 2 0.20 0.09 VIEW A 7 3.5 0 0.08 MAX COPLANARITY SEATING PLANE 25 51 50 26 0.27 0.22 0.17 0.50 BSC VIEW A ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS-026BED Figure 10. 100-Lead Low Profile Quad Flat Package [LQFP] (ST-100) Dimensions shown in millimeters 18.10 (0.7126) 17.70 (0.6969) 28 15 7.60 (0.2992) 7.40 (0.2913) 1 14 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 0.75 (0.0295) x 45 0.25 (0.0098) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 8 1.27 (0.0500) 0.51 (0.0201) SEATING 0.33 (0.0130) 0 BSC 0.31 (0.0122) PLANE 0.20 (0.0079) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 11. 28-Lead Standard Small Outline Package [SOIC] Wide Body (RW-28) Dimensions shown in millimeters and (inches) Rev. 0 | Page 20 of 24 ADSST-SALEM-3T ORDERING GUIDE Part Number1 ADSST-EM-3040 Temperature Range 0C to +70C ADSST-EM-3041 -25C to +85C 1 Processors Included ADSST-2185MKST-300 ADSST-73360LAR ADSST-2185MBST-266 ADSST-73360LAR For developer's kit, order ADSST-SALEM-3T-DK. Rev. 0 | Page 21 of 24 Package ST-100 RW-28 ST-100 RW-28 ADSST-SALEM-3T NOTES Rev. 0 | Page 22 of 24 ADSST-SALEM-3T NOTES Rev. 0 | Page 23 of 24 ADSST-SALEM-3T NOTES (c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03738-0-7/04(0) Rev. 0 | Page 24 of 24