1. Product profile
1.1 General description
250 W LDMOS power transistor for Industrial, Scientific and Medical (ISM) applications at
frequencies from 2400 MHz to 2500 MHz.
The BLF2425M7L250P and BLF2425M7LS250P are designed for high-power CW
applications and are assembled in high performance ceramic packages, available in
eared and earless versions
1.2 Features and benefits
High efficiency
Easy power control
Excellent ruggedness
Excellent thermal stability
Integrated ESD protection
Designed for broadband operation (2400 MHz to 2500 MHz)
Internally matched
Compliant to Directive 2002/95/EC, rega rd in g Re stri ctio n of Hazard ou s Sub stances
(RoHS)
1.3 Applications
RF power amplifiers for CW applications in the 2400 MHz to 2500 MHz frequency
range such as ISM and industrial heating.
BLF2425M7L250P;
BLF2425M7LS250P
Power LDMOS transistor
Rev. 4 — 12 July 2013 Product data sheet
Table 1. Typical perform ance
RF performance at Tcase = 25
C in a common source class-AB production test circuit.
Test signal f VDS PL(AV) GpD
(MHz) (V) (W) (dB) (%)
CW 2450 28 250 15 51
BLF2425M7L250P_2425M7LS250P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 12 July 2013 2 of 11
NXP Semiconductors BLF2425M7L(S)250P
Power LDMOS transistor
2. Pinning information
[1] Connected to flange.
3. Ordering information
4. Limiting values
Table 2. Pinning
Pin Description Simplified outline Graphic symbol
BLF2425M7L250P (SOT539A)
1drain1
2drain2
3gate1
4gate2
5source [1]
BLF2425M7LS250P (SOT539B)
1drain1
2drain2
3gate1
4gate2
5source [1]
5
12
43
4
35
1
2sym117
5
12
43
4
35
1
2sym117
Tabl e 3. Ordering informati on
Type number Package
Name Description Version
BLF2425M7L250P - flanged balanced ceramic package;
2 mounting holes; 4 leads SOT539A
BLF2425M7LS250P - earless flanged balanced ceramic package; 4 leads SOT539B
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage - 65 V
VGS gate-source voltage 0.5 +13 V
Tstg storage temperature 65 +150 C
Tjjunction temperature - 225 C
BLF2425M7L250P_2425M7LS250P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 12 July 2013 3 of 11
NXP Semiconductors BLF2425M7L(S)250P
Power LDMOS transistor
5. Thermal characteristics
6. Characteristics
7. Test information
7.1 Ruggedness in class-AB operation
The BLF2425M7L250P and BLF2425M7LS250P are capable of withstanding a load
mismatch corr es po nd in g to VSWR = 10 : 1 through all phas es und er the follo win g
conditions: VDS =28V; I
Dq =20mA; P
L = 250 W (CW); f = 2450 MHz.
Table 5. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-case) thermal resistance from junction to case Tcase =80C; PL= 250 W 0.19 K/W
Table 6. DC charac teristics
Tj = 25
C per section; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
V(BR)DSS drain-source breakdown
voltage VGS =0V; I
D=2.2mA65--V
VGS(th) gate-source threshold voltage VDS =10 V; I
D= 220 mA 1.5 1.9 2.3 V
IDSS drain leakage current VGS =0 V; V
DS =28V--3A
IDSX drain cut-off current VGS =V
GS(th) +3.75 V;
VDS =10V -39-A
IGSS gate leakage current VGS =11 V; V
DS = 0 V - - 300 nA
gfs forward transcondu ctance VDS =10V; I
D=11A - 16 - S
RDS(on) drain-source on-state
resistance VGS =V
GS(th) + 3.75 V;
ID=7.7A -0.08-
Table 7. RF char acteristics
Test signal: CW at 2450 MHz; RF performance at VDS = 28 V ; IDq = 20 mA; Tcase = 25
C; unless
otherwise specified; in a class-AB production test circuit.
Symbol Parameter Conditions Min Typ Max Unit
Gppower gain PL = 250 W 14 15 - dB
RLin input return loss PL = 250 W - 18 10 dB
Ddrain efficiency PL = 250 W 46 51 - %
BLF2425M7L250P_2425M7LS250P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 12 July 2013 4 of 11
NXP Semiconductors BLF2425M7L(S)250P
Power LDMOS transistor
7.2 Impedance information
7.3 Test circuit
Table 8. Typical impedance
Measured load-pull data half device. Typical values unless otherwise specified. IDq =20mA;
VDS =28V.
ZS and ZL defined in Figure 1.
f ZSZL
(MHz) () ()
2400 2.3 6.3j 3.8 2.7j
2450 3.3 6.0j 2.5 2.9j
2500 4.1 6.0j 3.3 2.3j
Fig 1. Definition of transis tor imp e danc e
001aak544
gate 1
gate 2
drain 2
drain 1
Z
S
Z
L
Printed-Circuit Board (PCB): Rogers RO4350B; thickness = 0.76 mm.
See Table 9 for list of components.
Fig 2. Component layou t for test circuit
&
&
&
&
&
&
&
&
&
&
& 5
5
& &
&
&
&
&
&
&
5
DDD
BLF2425M7L250P_2425M7LS250P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 12 July 2013 5 of 11
NXP Semiconductors BLF2425M7L(S)250P
Power LDMOS transistor
7.4 Graphical data
Table 9. List of components
For test circuit, see Figure 2.
Component Description Value Remarks
C1, C2, C3, C11,
C12, C13 multilayer ceramic chip capacitor 36 pF ATC800B
C4, C7, C14, C16 SMD capacitor 470 nF, 50 V
C5, C8, C15, C17 SMD capacitor 10 F, 50 V
C6, C19 multilayer ceramic chip capacitor 1.4 pF ATC100 B
C9, C10 multilayer ceramic chip capacitor 1.8 pF ATC100 B
C18 electrolytic capacitor 470 F, 63 V
R1 resistor 9.1 SMD 0805
R2, R3 resistor 5.1 SMD 0805
VDS = 28 V; IDq = 20 mA.
(1) f = 2400 MHz
(2) f = 2450 MHz
(3) f = 2500 MHz
VDS = 28 V; IDq = 20 mA.
(1) f = 2400 MHz
(2) f = 2450 MHz
(3) f = 2500 MHz
Fig 3. Power gain and drain efficiency as function of
load power; typical values Fig 4. Power gain and drain efficiency as function of
load power; typical values
DDD
3/G%P
*S
*S
G%G%G%
Ș'
Ș'
*S
*S
Ș'
Ș'
DDD
3/:
*S
*S
G%G%G%
Ș'
Ș'
*S
*S
Ș'
Ș'
BLF2425M7L250P_2425M7LS250P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 12 July 2013 6 of 11
NXP Semiconductors BLF2425M7L(S)250P
Power LDMOS transistor
8. Package outline
Fig 5. Package outline SOT539A
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
SOT539A 12-05-02
10-02-02
0 5 10 mm
scale
p
AF
b
e
D
U2
L
H
Q
c
5
12
43
D1
E
A
w1AB
M M M
q
U1
H1
C
B
M M
w2C
E1
M
w3
UNIT A
mm
Db
11.81
11.56 0.18
0.10 31.55
30.94 13.72 9.53
9.27 17.12
16.10 10.29
10.03
4.7
4.2
ce U2
0.250.25 0.51
w3
35.56
qw
2
w1
F
1.75
1.50
U1
41.28
41.02
H1
25.53
25.27
p
3.30
3.05
Q
2.26
2.01
EE
1
9.50
9.30
inches 0.465
0.455 0.007
0.004 1.242
1.218
D1
31.52
30.96
1.241
1.219 0.540 0.375
0.365 0.674
0.634 0.405
0.395
0.185
0.165 0.0100.010 0.0201.400
0.069
0.059 1.625
1.615
1.005
0.995 0.130
0.120 0.089
0.079
0.374
0.366
H
3.48
2.97
0.137
0.117
L
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
Flanged balanced ceramic package; 2 mounting holes; 4 leads SOT539A
Note
1. millimeter dimensions are derived from the original inch dimensions.
2. recommended screw pitch dimension of 1.52 inch (38.6 mm) based on M3 screw.
BLF2425M7L250P_2425M7LS250P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 12 July 2013 7 of 11
NXP Semiconductors BLF2425M7L(S)250P
Power LDMOS transistor
Fig 6. Package outline SOT539B
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT539B
sot539b_po
12-05-02
13-05-24
Unit(1)
mm max
nom
min
4.7
4.2
11.81
11.56
31.55
30.94
31.52
30.96
9.5
9.3
9.53
9.27
1.75
1.50
17.12
16.10
3.48
2.97
10.29
10.03 0.25
A
Dimensions
Earless flanged balanced ceramic package; 4 leads SOT539B
bc
0.18
0.10
DD
1EE
1e
13.72
FHH
1
25.53
25.27
LQ
2.26
2.01
U1
32.39
32.13
U2w2
0.25
inches max
nom
min
0.185
0.165
0.465
0.455
1.242
1.218
1.241
1.219
0.374
0.366
0.375
0.365
0.069
0.059
0.674
0.634
0.137
0.117
0.405
0.395 0.01
0.007
0.004 0.54 1.005
0.995
0.089
0.079
1.275
1.265 0.01
w3
0 5 10 mm
scale
c
E
Q
E1
e
H
L
b
H1
U1
U2
Dw2
w3
1 2
3 4
D
D
AF
D1
5
Note
1. millimeter dimensions are derived from the original inch dimensions.
BLF2425M7L250P_2425M7LS250P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 12 July 2013 8 of 11
NXP Semiconductors BLF2425M7L(S)250P
Power LDMOS transistor
9. Handling information
10. Abbreviations
11. Revision history
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
Table 10. Abbreviations
Acronym Description
CW Continuous Wave
ESD ElectroStatic Discharge
LDMOS Laterally Diffused Metal-Oxide Semiconductor
SMD Surface Mounted Device
VSWR Voltage Standing-Wave Ratio
Table 11. Revision history
Document ID Release
date Data sheet status Change
notice Supersedes
BLF2425M7L250P_2425M7LS250P v.4 20130712 Product data
sheet - BLF2425M7L250P_2425M7LS250P v.3
Modifications: •The package outline Figure 6 is updated.
BLF2425M7L250P_2425M7LS250P v.3 20130226 Product data
sheet - BLF2425M7L250P_2425M7LS250P v.2
Modifications: •Section 1.1 on page 1: updated
•Section 1.2 on page 1: updated
•Table 4 on page 2: removed row Tcase
•Table 6 on page 3: changed typical value RDS(on)
•Table 7 on page 3: updated
•Figure 1 on page 4: replaced figu re
BLF2425M7L250P_2425M7LS250P v.2 20120906 Objective data
sheet - BLF2425M7L250P_2425M7LS250P v.1
BLF2425M7L250P_2425M7LS250P v.1 20110718 Objective data
sheet --
BLF2425M7L250P_2425M7LS250P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 12 July 2013 9 of 11
NXP Semiconductors BLF2425M7L(S)250P
Power LDMOS transistor
12. Legal information
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[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
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Short data sheet — A short data sheet is an extract from a full data sheet
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
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Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contain s the product specification.
BLF2425M7L250P_2425M7LS250P All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 12 July 2013 10 of 11
NXP Semiconductors BLF2425M7L(S)250P
Power LDMOS transistor
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13. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors BLF2425M7L(S)250P
Power LDMOS transistor
© NXP B.V. 2013. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 12 July 2013
Document identifier: BLF2425M7L250P_2425M7LS250P
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
14. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Thermal characteristics . . . . . . . . . . . . . . . . . . 3
6 Characte ristics. . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 3
7.1 Ruggedness in class-AB operation . . . . . . . . . 3
7.2 Impedance information. . . . . . . . . . . . . . . . . . . 4
7.3 Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
7.4 Graphical data . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 6
9 Handling information. . . . . . . . . . . . . . . . . . . . . 8
10 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . 8
11 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 8
12 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 9
12.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 9
12.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
12.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
12.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10
13 Contact information. . . . . . . . . . . . . . . . . . . . . 10
14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
