The Programmable Logic Data Book Supplement PMOL) GMa eth Nira aes PAP ST ee XILINX OI 1IX* * => XILINX XC4000 Series Table of Contents XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000E and XC4000X Series Features... 0... cn ee eee eee teen ee nene 3 Low-Voltage Versions Available... 0.0.0.0... cee cc een teen eaten nena 3 Additional XC4000X Series Features ..........0. 0.00 e eee e eee 3 Introduction 0... eee eed e eee b eee eee eee eset aaenes 3 Description 2.0... cece tenn e ent ett beeen eet ene ees 4 Taking Advantage of Reconfiguration... ........0.. 0. cc ccc cece ete n eee n ees 4 XC4000E and XC4000X Series Compared to the XC4000 ... ccc eens 5 improvements in XC4000E and XC4000X .. wc cece tee tte nee e teens 5 Additional Improvements in XC4000X Only .........0. 0.0 eee eee eee eee 6 Detailed Functional Description .......0.00 0.0 eee ce tenet e ee ee 6 Basic Building Blocks ........... 00. ccc ee cette eet e nen eens 7 Configurable Logic Blocks (CLBs) ............. ee eee ee ene eee eee eee eee 7 Function Generators... 00... eee tte eneeees 7 FIP-FIOPS 20... ce ee te teeta eee eben e tenes 8 Latches (XC4000X only)... ee tte teen eenaee 8 Clock Input... ete eee n eee teen e ene eee neeee 8 Clock Enable... 0.0... cere ee tent e eee een e eee 8 Set/fReset 0.0... ee etn ett etn eens 9 Global Set/Reset. 0.0.0... 0. cence e ete eee e etree 9 Data inputs and Outputs. 0... ete ete teen et aeee 9 Control Signals... 6... eee eee tebe rte ee ene 9 Using FPGA Flip-Flops and Latches. ...........0 0.00 cece cee eee eee e eee eennes 9 Using Function Generators as RAM....... 0.2.20... 2.0 c cece eee 9 Fast Carry Logic... 0... ee tbe etn eet nee eneee 16 Input/Output Blocks (IOBs). 0.0... ee ee ene enna tne teeta eegtee 18 1OB Input Signals .... 2.00... ett tne ne eteeee 18 IOB Output Signals... 2... eee nents 21 Other 1OB Options ... 0... ee ete eee tenn eens 23 Three-State Buffers... 000. eee enn deere etn ene tneenetee 24 Three-State Buffer Modes 0.0.0.0... 0... cece cece ce erence teen en etee 24 Three-State Buffer Examples .......000.02 0.00 ccc cece tenet ee eeeeee 24 On-Chip Oscillator. 02.00. eee e eee been reer been eens 25 Programmable Interconnect ..... 0 eee cent eee ee eee 26 Interconnect Overview ........0 0.0... c eee eee ene tenn te teenie enn 26 CLB Routing Connections... 0... nent ene 26 Programmable Switch Matrices... 2... ce eet ee tenes 27 Single-Length Lines .. 60.0... c cee eet teen etnies 27 Double-Length Lines. 0.0... ee eee ence ee een ee 29 Quad Lines (XC4000X only)... ce eee erent eens 29 LonglineS 20.06 eee teeter eee 29 Direct Interconnect (XC4000X only)... 0.6 ec eee eee eee eee 30 VO Routing 0... eee eet ene e teen eae 30 Octal /O Routing (XC4000X only)... 6... tte tenet eae 30 Global Nets and Buffers 6.00... eee eee tte e tent eens 33 Global Nets and Buffers (XC4000E only)... 2.0... eee ene 33 Global Nets and Buffers (XC4000X only)... 6... cece eee eee 35 Power Distribution... 00.0... ce tert eee e ete e nee beeen eee 37 Pin Descriptions .....0. 00.0. ee ee ene eee eee ents 37XC4000 Series Tabie of Contents Boundary Scan... en een e eee eee beeen etneeennes 40 Data Registers... 0... cern tree ett nee e eee nanas 40 Instruction Set... een ee ee eee eee ene euanes 42 Bit Sequence... eee tn eer ene eee ene eta t eee neae 42 Including Boundary Scan in a Schematic... 2.0.0.0... 00 ccc ccc eee eet e ne nnee 42 Avoiding Inadvertent Boundary Scan. .... 0.6... ccc eee teen ene ee aee 43 Configuration. 0.0... eee ee ete e eee t tenet eenes 43 Special Purpose Pins .........0 0... cc eee eee eee enn eet ee ean eeeaut 43 Configuration Modes... 0... ce cee entre eee eee enter ee eeneeaee 44 Master Modes... 6... cee eee tree ener e ene te entre eeee 44 Additional Address lines in XC4000 devices ........0.... 0. cece eee eee eee eee 44 Peripheral Modes 0.0.0. cette eee tenet e eee ee renee 44 Slave Serial Mode. 0.0.0... tee eee been eee nnnreeas 44 Setting CCLK Frequency ..... 0. ce eect eee e ene beeen eas 46 Data Stream Format.......00. 00 cece tent bbe e ete eennnees 46 Cyclic Redundancy Check (CRC) for Configuration and Readback.....................- 47 Configuration Sequence. .... 00... cece eee tenet e ene nate e ene nnes 48 Configuration Memory Clear... 0... cnn eee ne en enaes 48 Initialization... 0. cee eee tee eee t tent neeenees 49 Delaying Configuration After Power-Up .... 2.0.0... ee eens 49 Start-Up. ...0.......0...0.. Se ene ete ene nett eee ee 49 DONE Goes High to Signal End of Configuration.............0....0.. cece ee eee 52 Release of User I/O After DONE Goes High ........... 0.02... .0 0 eee eee eee 52 Release of Giobal Set/Reset After DONE Goes High ........... 0.00.2. c eee eae 52 Configuration Complete After DONE Goes High ............ 0... c cece eee eee 52 Configuration Through the Boundary Scan Pins............. 0.02.0. cee eee ene eee 52 Readback 2.0... ee eee tee ten eet n een beeen eeeee 53 Readback Options ....... 0... ccc eee nee nent e eben we eeaeeeae 54 Read Capture... cence eee nee tenn etn te cnet enna 54 Read Abort 2... ee ee ee ee ee eee e eee 54 Clock Select 0.0... 0. ke cece eee eee eee tne tenet anes 54 Violating the Maximum High and Low Time Specification for the Readback Clock .......... 54 Readback with the XChecker Cable... 0... cece eee eee nee 54 Configuration Timing. .... 0... cee eee een ene tet e ee eee eens 56 Slave Serial Mode... 0. eterna ene eben ee ene tenes 56 Master Serial Mode... 0.6... cee te teen ee eee tne ene eee 57 Master Parallel Modes ........ 0... ccc eee ee ttn ne cnet ene een eee 58 Additional Address lines in XC4000 devices ....... 0... ccc cece eee eee 58 Synchronous Peripheral Mode... 2.0... . 0... ee etre nee tenn ene 60 Asynchronous Peripheral Mode ...... 000. ec cee reer tee teen eens 62 Write to FPGA. 0. ee eer eee te eee rene tbe eee eneee 62 Status Read 2.00... eet nee n entree teen neens 62 Device-Specific Pinout Tables ... 0.0... eee ett eens 114 Pin Locations for XC4003E Devices... 1.0... 0... . cee ee ee ete tenes 114 Pin Locations for XC4005E/KL Devices ......0 0.00. cc cect eee eeee 115 Pin Locations for XC400GE Devices... 1.0.0.0... ccc cere tee eens 116 Pin Locations for XC4008E Devices... 1.0.0.0... 0... ccc cece teen eee anes 118 Pin Locations for XC4010E/KL Devices .. 0.0.00... ce tet eens 119 Pin Locations for XC4013E/XL Devices ......0. 0... ec eeee te ee tenes 121 Pin Locations for XC4020E/XL Devices ......0 0... ccc enter n ee entenee 124 Pin Locations for XC4025E, XC4028EX/XL Devices ..........0. 0... eee eee eee ee 126 Pin Locations for XC4036EX/XL. 0 een ene eee eects 129 Pin Locations for XC4044XL Devices... 0.0... eee een teenies 132 Pin Locations for XC4052XL Devices. ......... 0... cece eee ee te teenies 136 Pin Locations for XC4062XL Devices................ 0.200 e eee ee see eee e ences 140 Pin Locations for XC4085XL Devices........... 0.00.2 ceca ee Sheen cence eee e nes 1442: XILINX XC4000E and XC4000X Series Field Programmable Gate Arrays July 30, 1997 (Version 1.2) Product Specification XC4000E and XC4000X Series Features Note: XC4000 Series devices described in this data sheet include the XC4000E family and XC4000X Series. XC4000X Series devices described in this data sheet include the XC4000EX and XC4000XL families. This infor- mation does not apply to the older Xilinx families: XC4000, XC4000A, XC4000D, XC4000H, or XC4000L. For informa- tion on these devices, see the Xilinx WEBLINX at http:// www.xilinx.com. * System featured Field-Programmable Gate Arrays - Select-RAM memory: on-chip ultra-fast RAM with - synchronous write option - dual-port RAM option - Fully PCI compliant (speed grades -2 and faster) - Abundant flip-flops - Flexible function generators - Dedicated high-speed carry logic - Wide edge decoders on each edge - Hierarchy of interconnect lines - Internal 3-state bus capability - 8 global low-skew clock or signal distribution networks System Performance beyond 80 MHz Flexible Array Architecture Low Power Segmented Routing Architecture Systems-Oriented Features - [EEE 1149.1-compatible boundary scan logic support - Individually programmabie output slew rate - Programmable input pull-up or pull-down resistors - 12-mA sink current per XC4000E output * Configured by Loading Binary File - Unlimited reprogrammability Readback Capability - Program verification - Internal node observability Backward Compatible with XC4000 Devices * XACTstep Development System runs on most common computer platforms - Interfaces to popular design environments - Fully automatic mapping, placement and routing - Interactive design editor for design optimization Low-Voltage Versions Available * Low-Voltage Devices Function at 3.0 - 3.6 Volts * XC4000XL: High Performance Low-Voltage Versions of XC4000EX devices Additional XC4000X Series Features Highest Performance 3.3 V XC4000XL Highest Capacity Over 180,000 Usable Gates 5V tolerant I/Os on XC4000XL 0.35 SRAM process for XC4000XL Additional Routing Over XC4000E - almost twice the routing capacity for high-density designs Buffered Interconnect for Maximum Speed e New Latch Capability in Configurable Logic Blocks Improved VersaRing I/O Interconnect for Better Fixed Pinout Flexibility e 12-mA Sink Current Per XC4000X Output Flexible New High-Speed Clock Network - 8 additional Early Buffers for shorter clock delays - Virtually unlimited number of clock signals * Optional Multiplexer or 2-input Function Generator on Device Outputs * 4 Additional Address Bits in Master Parallel Configuration Mode Introduction XC4000 Series high-performance, high-capacity Field Pro- grammable Gate Arrays (FPGAs) provide the benefits of custom CMOS VLSI, while avoiding the initial cost, long development cycle, and inherent risk of a conventional masked gate array. The result of thirteen years of FPGA design experience and feedback from thousands of customers, these FPGAs com- bine architectural versatility, on-chip Select-RAM memory with edge-triggered and dual-port modes, increased speed, abundant routing resources, and new, sophisticated software to achieve fully automated implementation of complex, high-density, high-performance designs. The XC4000E and XC4000X Series currently have 20 members, as shown in Table 1. Note: Ai! functionality in low-voltage families is the same as in the corresponding 5-Volt family, except where numerical references are made to timing or power. July 30, 1997 (Version 1.2)XC4000E and XC4000X Series Field Programmable Gate Arrays Table 1: XC4000E and XC4000X Series Field Programmable Gate Arrays Max Logic | Max. RAM Typical Number Logic Gates Bits Gate Range CLB Total of Max. Device Cells (No RAM) |(No Logic)|(Logic and RAM)*; Matrix CL8s | Flip-Fiops| User /O XC4003E 238 3,000 3,200 2,000 - 5,000 10x 10 100 360 80 XC4005E/XL 466 5,000 6,272 3,000 - 9,000 14x14 196 616 112 XC4006E 608 6,000 8,192 4,000 - 12,000 16x 16 256 768 128 XC4008E 770 8,000 10,368 6,000 - 15,000 18x 18 324 936 144 XC4010E/XL 950 10,000 12,800 7,000 - 20,000 20 x 20 400 1,120 160 XC4013E/XL 1368 13,000 18,432 10,000 - 30,000 24x 24 576 1,536 192 XC4020E/XL 1862 20,000 25,088 13,000 - 40,000 28 x 28 784 2,016 224 XC4025E 2432 25,000 32,768 15,000 - 45,000 32 x 32 1,024 2,560 256 XC4028EX/XL 2432 28,000 32,768 18,000 - 50,000 32 x 32 1,024 2,560 256 XC4036EX/XL 3078 36,000 41,472 22,000 - 65,000 36 x 36 1,296 3,168 288 XC4044XL 3800 44,000 51,200 27,000 - 80,000 40 x 40 1,600 3,840 320 XC4052XL 4598 52,000 61,952 | 33,000- 100,000 | 44x44 1,936 4,576 352 XC4062XL 5472 62,000 73,728 | 40,000- 130,000 | 48x48 2,304 5,376 384 XC4085XL 7448 85,000 100,352 | 55,000 - 180,000 | 56x56 3,136 7,168 448 * Max values of Typical Gate Range include 20-30% of CLBs used as RAM. Description XC4000 Series devices are implemented with a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), interconnected by a powerful hierarchy of versatile routing resources, and surrounded by a perimeter of programmable Input/Output Blocks (IOBs). They have generous routing resources to accommodate the most complex interconnect patterns. The devices are customized by loading configuration data into internal memory cells. The FPGA can either actively read its configuration data from an external serial or byte- parallel PROM (master modes), or the configuration data can be written into the FPGA from an external device (slave and peripheral modes). XC4000 Series FPGAs are supported by powerful and sophisticated software, covering every aspect of design from schematic or behavioral entry, floorplanning, simula- tion, automatic block placement and routing of intercon- nects, to the creation, downloading, and readback of the configuration bit stream. Because Xilinx FPGAs can be reprogrammed an unlimited number of times, they can be used in innovative designs where hardware is changed dynamically, or where hard- ware must be adapted to different user applications. FPGAs are ideal for shortening design and development cycles, and also offer a cost-effective solution for produc- tion rates well beyond 5,000 systems per month. For lowest high-volume unit cost, a design can first be implemented in the XC4000E or XC4000X, then migrated to one of Xilinx compatible HardWire mask-programmed devices. Taking Advantage of Reconfiguration FPGA devices can be reconfigured to change logic function while resident in the system. This capability gives the sys- tem designer a new degree of freedom not available with any other type of logic. Hardware can be changed as easily as software. Design updates or modifications are easy, and can be made to products already in the field. An FPGA can even be recon- figured dynamically to perform different functions at differ- ent times. Reconfigurable logic can be used to implement system self-diagnostics, create systems capable of being reconfig- ured for different environments or operations, or implement multi-purpose hardware for a given application. As an added benefit, using reconfigurable FPGA devices simpli- fies hardware design and debugging and shortens product time-to-market. July 30, 1997 (Version 1.2)$2 XILINX XC4000E and XC4000X Series Compared to the XC4000 For readers already familiar with the XC4000 family of Xil- inx Field Programmable Gate Arrays, the major new fea- tures in the XC4000 Series devices are listed in this section. The biggest advantages of XC4000E and XC4000X devices are significantly increased system speed, greater capacity, and new architectural features, particularly Select-RAM memory. The XC4000X devices also offer many new routing features, including special high-speed clock buffers that can be used to capture input data with minimal delay. Any XC4000E device is pinout- and bitstream-compatibie with the corresponding XC4000 device. An existing XC4000 bitstream can be used to program an XC4000E device. However, since the XC4000E includes many new features, an XC4000E bitstream cannot be loaded into an XC4000 device. XC4000X Series devices are not bitstream-compatibie with equivalent array size devices in the XC4000 or XC4000E families. However, equivalent array size devices, such as the XC4025, XC4025E, XC4028EX, and XC4028XL, are pinout-compatible. Improvements in XC4000E and XC4000X Increased System Speed XC4000E and XC4000X devices can run at synchronous system clock rates of up to 80 MHz, and internal perfor- mance can exceed 150 MHz. This increase in performance over the previous families stems from improvements in both device processing and system architecture. XC4000 Series devices use a sub-micron multi-layer metal process. In addition, many architectural improvements have been made, as described below. The XC4000XL family is a high performance 3.3V family based on 0.354 SRAM technology and supports system speeds to 80 MHz. PCI Compliance XC4000 Series -2 and faster speed grades are fully PCI compliant. XC4000E and XC4000X devices can be used to implement a one-chip PC! solution. Carry Logic The speed of the carry logic chain has increased dramati- cally. Some parameters, such as the delay on the carry chain through a single CLB (Tsyp), have improved by as much as 50% from XC4000 values. See Fast Carry Logic on page 16 for more information. Select-RAM Memory: Edge-Triggered, Synchronous RAM Modes The RAM in any CLB can be configured for synchronous, edge-triggered, write operation. The read operation is not affected by this change to an edge-triggered write. Dual-Port RAM A separate option converts the 16x2 RAM in any CLB into a 16x1 dual-port RAM with simultaneous Read/Write. The function generators in each CLB can be configured as either level-sensitive (asynchronous) single-port RAM, edge-triggered (synchronous) single-port RAM, edge-trig- gered (synchronous) dual-port RAM, or as combinatorial logic. Configurable RAM Content The RAM content can now be loaded at configuration time, so that the RAM starts up with user-defined data. H Function Generator In current XC4000 Series devices, the H function generator is more versatile than in the original XC4000. Its inputs can come not only from the F and G function generators but also from up to three of the four control input lines. The H function generator can thus be totally or partially indepen- dent of the other two function generators, increasing the maximum capacity of the device. 108 Clock Enable The two flip-flops in each 1OB have a common clock enable input, which through configuration can be activated individ- ually for the input or output flip-flop or both. This clock enable operates exactly like the EC pin on the XC4000 CLB. This new feature makes the |OBs more versatile, and avoids the need for clock gating. Output Drivers The output pull-up structure defaults to a TTL-like totem- pole. This driver is an n-channel pull-up transistor, pulling to a voltage one transistor threshold below Vcc, just like the XC4000 family outputs. Alternatively, XC4000 Series devices can be globally configured with CMOS outputs, with p-channel pull-up transistors pulling to Vcc. Also, the configurable pull-up resistor in the XC4000 Series is a p- channel transistor that pulls to Vcc, whereas in the original XC4000 family it is an n-channel transistor that pulls to a voltage one transistor threshoid below Vcc. Input Thresholds The input thresholds of 5V devices can be globally config- ured for either TTL (1.2 V threshold) or CMOS (2.5 V threshold), just like XC2000 and XC3000 inputs. The two global adjustments of input threshold and output level are independent of each other. The XC4000XL family has an July 30, 1997 (Version 1.2)XCAQO0E and XC4000X Series Field Programmable Gate Arrays input threshold of 1.6V, compatible with both 3.3V CMOS and TTL levels. Global Signal Access to Logic There is additional access from global clocks to the F and G function generator inputs. Configuration Pin Pull-Up Resistors During configuration, the three mode pins, MO, M1, and M2, have weak pull-up resistors. For the most popular con- figuration mode, Slave Serial, the mode pins can thus be left unconnected. The three mode inputs can be individually configured with or without weak pull-up or pull-down resistors after configu- ration. The PROGRAM input pin has a permanent weak pull-up. Soft Start-up Like the XC3000A, XC4000 Series devices have Soft Start-up. When the configuration process is finished and the device starts up, the first activation of the outputs is automatically slew-rate limited. This feature avoids poten- tial ground bounce when all outputs are turned on simulta- neously. Immediately after start-up, the slew rate of the individual outputs is, as in the XC4000 family, determined by the individual configuration option. XC4000 and XC4000A Compatibility Existing XC4000 bitstreams can be used to configure an XC4000E device. XC4000A bitstreams must be recompiled for use with the XC4000E due to improved routing resources, although the devices are pin-for-pin compatible. Additional Improvements in XC4000X Only Increased Routing New interconnect in the XC4000X includes twenty-two additional vertical lines in each column of CLBs and twelve new horizontal lines in each row of CLBs. The tweive Quad Lines in each CLB row and column include optional repow- ering buffers for maximum speed. Additional high-perfor- mance routing near the IOBs enhances pin flexibility. Faster Input and Output A fast, dedicated early clock sourced by global clock buffers is available for the IOBs. To ensure synchronization with the regular global clocks, a Fast Capture latch driven by the early clock is available. The input data can be initially loaded into the Fast Capture latch with the early clock, then transferred to the input flip-flop or latch with the low-skew global clock. A programmable delay on the input can be used to avoid hold-time requirements. See IOB Input Sig- nals on page 18 for more information. Latch Capability In CLBs Storage elements in the XC4000X CLB can be configured as either flip-flops or latches. This capability makes the FPGA highly synthesis-compatible. 1OB Output MUX From Output Clock A multiplexer in the 1OB allows the output clock to select either the output data or the IOB clock enable as the output to the pad. Thus, two differant data signals can share a sin- gle output pad, effectively doubling the number of device outputs without requiring a larger, more expensive pack- age. This multiplexer can also be configured as an AND- gate to implement a very fast pin-to-pin path. See IOB Out- put Signals on page 21 for more information. Additional Address Bits Larger devices require more bits of configuration data. A daisy chain of several large XC4000X devices may require a PROM that cannot be addressed by the eighteen address bits supported in the XC4000E. The XC4000X Series therefore extends the addressing in Master Parallel config- uration mode to 22 bits. Detailed Functional Description XC4000 Series devices achieve high speed through advanced semiconductor technology and improved archi- tecture. The XC4000E and XC4000X support system clock rates of up to 80 MHz and internal performance in excess of 150 MHz. Compared to older Xilinx FPGA families, XC4000 Series devices are more powerful. They offer on- chip edge-triggered and dual-port RAM, clock enables on I/ O flip-flops, and wide-input decoders. They are more versa- tile in many applications, especiaily those involving RAM. Design cycles are faster due to a combination of increased routing resources and more sophisticated software. July 30, 1997 (Version 1.2)$< XILINX Basic Building Blocks Xilinx user-programmable gate arrays include two major configurable elements: configurable logic blocks (CLBs) and input/output blocks (IOBs). * CLBs provide the functional elements for constructing the user's logic. * \OBs provide the interface between the package pins and internal signal lines. Three other types of circuits are also available: 3-State buffers (TBUFs) driving horizontal longlines are associated with each CLB. Wide edge decoders are available around the periphery of each device. An on-chip oscillator is provided. Programmable interconnect resources provide routing paths to connect the inputs and outputs of these config- urable elements to the appropriate networks. The functionality of each circuit block is customized during configuration by programming internal static memory cells. The values stored in these memory cells determine the logic functions and interconnections implemented in the FPGA. Each of these available circuits is described in this section. Configurable Logic Blocks (CLBs) Configurable Logic Blocks implement most of the. lagic in an FPGA. The principal CLB elements are shown in Figure 1. Two 4-input function generators (F and G) offer unrestricted versatility. Most combinatorial logic functions need four or fewer inputs. However, a third function generator (H) is pro- vided. The H function generator has three inputs. Either zero, one, or two of these inputs can be the outputs of F and G; the other input(s) are from outside the CLB. The CLB can, therefore, implement certain functions of up to nine variables, like parity check or expandable-identity comparison of two sets of four inputs. Each CLB contains two storage elements that can be used to store the function generator outputs. However, the stor- age elements and function generators can also be used independently. These storage elements can be configured as flip-flops in both XC4000E and XC4000X devices; in the XC4000X they can optionally be configured as latches. DIN can be used as a direct input to either of the two storage elements. Ht can drive the other through the H function generator. Function generator outputs can also drive two outputs independent of the storage element outputs. This versatility increases logic capacity and simplifies routing. Thirteen CLB inputs and four CLB outputs provide access to the function generators and storage elements. These inputs and outputs connect to the programmable intercon- nect resources outside the block. Function Generators Four independent inputs are provided to each of two func- tion generators (F1 - F4 and G1 - G4). These function gen- erators, with outputs labeled F and G, are each capable of implementing any arbitrarily defined Boolean function of four inputs. The function generators are implemented as memory look-up tables. The propagation delay is therefore independent of the function implemented. A third function generator, labeled H, can implement any Boolean function of its three inputs. Two of these inputs can optionally be the F and G' functional generator outputs. Alternatively, one or both of these inputs can come from outside the CLB (H2, HO). The third input must come from outside the block (H1). Signals from the function generators can exit the CLB on two outputs. F or H can be connected to the X output. G or H can be connected to the Y output. A CLB can be used to implement any of the following func- tions: * any function of up to four variables, plus any second function of up to four unrelated variables, plus any third function of up to three unrelated variables! * any single function of five variables * any function of four variables together with some functions of six variables * some functions of up to nine variables. Implementing wide functions in a single block reduces both the number of blocks required and the delay in the signal path, achieving both increased capacity and speed. The versatility of the CLB function generators significantly improves system speed. In addition, the design-software tools can deal with each function generator independently. This flexibility improves cell usage. 1. When three separate functions are generated, one of the function outputs must be captured in a flip-flop internal to the CLB. Only two unregistered function generator outputs are available from the CLB. July 30, 1997 (Version 1.2)XC4000E and XC4000X Series Field Programmable Gate Arrays Cy eee Gy G3 ay Fa Fg Fe Fy K (CLOCK) YQ xQ Dy Configuration Program x6802 Figure 1: Simplified Block Diagram of XC4000 Series CLB (RAM and Carry Logic functions not shown) Flip-Flops The CLB can pass the combinatorial output(s) to the inter- connect network, but can also store the combinatorial results or other incoming data in one or two flip-flops, and connect their outputs to the interconnect network as well. The two edge-triggered D-type flip-flops have common clock (K) and clock enable (EC) inputs. Either or both clock inputs can also be permanently enabled. Storage element functionality is described in Table 2. Latches (XC4000X only) The CLB storage elements can also be configured as latches. The two latches have common clock (K) and clock enable (EC) inputs. Storage element functionality is described in Table 2. Clock Input Each flip-flop can be triggered on either the rising or falling clock edge. The clock pin is shared by both storage ele- ments. However, the clock is individually invertible for each storage element. Any inverter placed on the clock input is automatically absorbed into the CLB. Clock Enable The clock enable signal (EC) is active High. The EC pin is shared by both storage elements. If left unconnected for either, the clock enable for that storage element defaults to the active state. EC is not invertible within the CLB. Table 2: CLB Storage Element Functionality (active rising edge Is shown) Mode K Ec SR D Q Power-Up or GSR X xX x SR x 1 x SR Flip-Flop _f 1* o* D D 0 Q* Xx Q 1 1* 0* x Q Latch 0 T | oF D D Both Xx 0 o* x Q Legend: x Dont care _f Rising edge SR Set or Reset value. Reset is default. 0 Input is Low or unconnected (default value) i* Input is High or unconnected (default value) July 30, 1997 (Version 1.2)Set/Reset An asynchronous storage element input (SR) can be con- figured as either set or reset. This configuration option determines the state in which each flip-flop becomes oper- ational after configuration. It also determines the effect of a Giobal Set/Reset pulse during normal operation, and the effect of a pulse on the SR pin of the CLB. All three set/ reset functions for any single flip-flop are controlled by the same configuration data bit. The set/reset state can be independently specified for each flip-flop. This input can also be independently disabled for either flip-flop. The set/reset state is specified by using the INIT attribute, or by placing the appropriate set or reset flip-flop library symbol. SR is active High. it is not invertible within the CLB. Global Set/Reset A separate Global Set/Reset line (not shown in Figure 1) sets or clears each storage element during power-up, reconfiguration, or when a dedicated Reset net is driven active. This global net (GSR) does not compete with other routing resources; it uses a dedicated distribution network. Each flip-flop is configured as either globally set or reset in the same way that the local set/reset (SR) is specified. Therefore, if a flip-flop is set by SR, it is also set by GSR. Similarly, a reset flip-flop is reset by both SR and GSR. STARTUP Sn IBUE GTS Q3 - Q1Q4 } > CLK DONEIN +} X5260 Figure 2: Schematic Symbols for Global Set/Reset GSR can be driven from any user-programmable pin as a global reset input. To use this global net, place an input pad and input buffer in the schematic or HDL code, driving the GSR pin of the STARTUP symbol. (See Figure 2.) A spe- cific pin location can be assigned to this input using a LOC attribute or property, just as with any other user-program- mable pad. An inverter can optionally be inserted after the input buffer to invert the sense of the Global Set/Reset sig- nal. Alternatively, GSR can be driven from any internal node. Data Inputs and Outputs The source of a storage element data input is programma- ble. It is driven by any of the functions F, G, and H, or by the Direct In (DIN) block input. The flip-flops or latches drive the XQ and YO CLB outputs. $< XILINX Two fast feed-through paths are available, as shown in Figure 1. A two-to-one multiplexer on each of the XQ and YQ outputs selects between a storage element output and any of the control inputs. This bypass is sometimes used by the automated router to repower internal signals. Control Signals Multiplexers in the CLB map the four contro! inputs (C1 - C4 in Figure 1) into the four internal contro! signals (H1, DIN/ H2, SR/HO, and EC). Any of these inputs can drive any of the four internal control signals. When the logic function is enabled, the four inputs are: EC Enable Clock SR/HO Asynchronous Set/Reset or H function generator Input 0 DIN/H2 Direct In or H function generator Input 2 Ht H function generator Input 1. When the memory function is enabled, the four inputs are: EC Enable Clock WE Write Enable DO Data Input to F and/or G function generator D1 Data input to G function generator (16x1 and 16x2 modes) or 5th Address bit (32x1 mode). Using FPGA Flip-Flops and Latches The abundance of flip-flops in the XC4000 Series invites pipelined designs. This is a powerful way of increasing per- formance by breaking the function into smaller subfunc- tions and executing them in parallel, passing on the results through pipeline flip-flops. This method should be seriously considered wherever throughput is more important than latency. To include a CLB flip-flop, place the appropriate library symbol. For example, FOCE is a D-type flip-flop with clock enable and asynchronous clear. The corresponding latch symbol (for the XC4000X only) is called LDCE. In XC4000 Series devices, the flip flops can be used as reg- isters or shift registers without blocking the function gener- ators from performing a different, perhaps unrelated task. This ability increases the functional capacity of the devices. The CLB setup time is specified between the function gen- erator inputs and the clock input K. Therefore, the specified CLB flip-flop setup time includes the delay through the function generator. Using Function Generators as RAM Optional modes for each CLB make the memory look-up tables in the F and G function generators usable as an array of Read/Write memory cells. Available modes are level-sensitive (similar to the XC4000/A/H families), edge- triggered, and dual-port edge-triggered. Depending on the selected mode, a single CLB can be configured as either a 16x2, 32x1, or 16x1 bit array. July 30, 1997 (Version 1.2)XC4000E and XC4000X Series Field Programmable Gate Arrays Supported CLB memory configurations and timing modes for single- and dual-port modes are shown in Table 3. XC4000 Series devices are the first programmable logic devices with edge-triggered (synchronous) and dual-port RAM accessible to the user. Edge-triggered RAM simpli- fies system timing. Dual-port RAM doubles the effective throughput of FIFO applications. These features can be individually programmed in any XC4000 Series CLB. Advantages of On-Chip and Edge-Triggered RAM The on-chip RAM is extremely fast. The read access time is the same as the logic delay. The write access time is slightly slower. Both access times are much faster than any off-chip solution, because they avoid I/O delays. Edge-triggered RAM, also called synchronous RAM, is a feature never before available in a Field Programmable Gate Array. The simplicity of designing with edge-triggered RAM, and the markedly higher achievable performance, add up to a significant improvement over existing devices with on-chip RAM. Three application notes are available from Xilinx that dis- cuss edge-triggered RAM: XC4000E Edge-Triggered and Dual-Port RAM Capability Implementing FIFOs in XC4000E RAM; and Synchronous and Asynchronous FIFO Designs Ail three application notes apply to both XC4000E and XC4000X RAM. Table 3: Supported RAM Modes 16 | 16 | 32 Edge- Level- x x x | Triggered | Sensitive 1 2 1 Timing Timing Single-Pot | Vv] v | Vv V V Dual-Port Vv] | RAM Configuration Options The function generators in any CLB can be configured as RAM arrays in the following sizes: * Two 16x1 RAMs: two data inputs and two data outputs with identical or, if preferred, different addressing for each RAM One 32x1 RAM: one data input and one data output. One F or G function generator can be configured as a 16x1 RAM while the other function generators are used to imple- ment any function of up to 5 inputs. Additionally, the XC4000 Series RAM may have either of two timing modes: e Edge-Triggered (Synchronous): data written by the designated edge of the CLB clock. WE acts as a true clock enable. Level-Sensitive (Asynchronous): an external WE signal acts as the write strobe. The selected timing mode applies to both function genera- tors within a CLB when both are configured as RAM. The number of read ports is also programmabie: * Single Port: each function generator has a common read and write port * Dual Port: both function generators are configured together as a single 16x1 dual-port RAM with one write port and two read ports. Simultaneous read and write operations to the same or different addresses are supported. RAM configuration options are selected by placing the appropriate library symbol. Choosing a RAM Configuration Mode The appropriate choice of RAM mode for a given design should be based on timing and resource requirements, desired functionality, and the simplicity of the design pro- cess. Recommended usage is shown in Tabie 4. The difference between level-sensitive, edge-triggered, and dual-port RAM is only in the write operation. Read operation and timing is identical for all modes of operation. Table 4: RAM Mode Selection Dual-Port Level- Edge- Edge- Sensitive | Triggered | Triggered Use for New Designs? No Yes Yes Size (16x1, Registered) 1/2 CLB 1/2 CLB 1CLB Simultaneous Read/Write No No Yes Relative x 2x 2X (4X Performance effective) RAM Inputs and Outputs The F1-F4 and G1-G4 inputs to the function generators act as address lines, selecting a particular memory cell in each look-up table. The functionality of the CLB control signals changes when the function generators are configured as RAM. The DIN/ H2, Hi, and SR/HO lines become the two data inputs (DO, D1) and the Write Enable (WE) input for the 16x2 memory. When the 32x1 configuration is selected, D1 acts as the fifth address bit and DO is the data input. The contents of the memory cell(s) being addressed are available at the F and G function-generator outputs. They can exit the CLB through its X and Y outputs, or can be cap- tured in the CLB flip-flop(s). Configuring the CLB function generators as Read/Write memory does not affect the functionality of the other por- 10 July 30, 1997 (Version 1.2)tions of the CLB, with the exception of the redefinition of the control signals. In 16x2 and 16x1 modes, the H function generator can be used to implement Boolean functions of F, G, and D1, and the D flip-flops can latch the F, G, H, or DO signals. Single-Port Edge-Triggered Mode Edge-triggered (synchronous) RAM _ simplifies timing requirements. XC4000 Series edge-triggered RAM timing operates like writing to a data register. Data and address are presented. The register is enabled for writing by a logic High on the write enable input, WE. Then a rising or falling clock edge loads the data into the register, as shown in Figure 3. _Twes Twss Twas T, Tons ADDRESS DATA OUT X6461 Figure 3: Edge-Triggered RAM Write Timing Complex timing relationships between address, data, and write enable signals are not required, and the external write enable pulse becomes a simple clock enable. The active edge of WCLK latches the address, input data, and WE sig- $< XILINX nals. An internal write pulse is generated that performs the write. See Figure 4 and Figure 5 for block diagrams of a CLB configured as 16x2 and 32x1 edge-triggered, single- port RAM. The relationships between CLB pins and RAM inputs and outputs for single-port, edge-triggered mode are shown in Table 5. The Write Clock input (WCLK) can be configured as active on either the rising edge (default) or the falling edge. It uses the same CLB pin (K) used to clock the CLB flip-flops, but it can be independently inverted. Consequently, the RAM output can optionally be registered within the same CLB either by the same clock edge as the RAM, or by the oppo- site edge of this clock. The sense of WCLK applies to both function generators in the CLB when both are configured as RAM. The WE pin is active-High and is not invertible within the CLB. Note: The pulse following the active edge of WCLK (Twps in Figure 3) must be less than one millisecond wide. For most applications, this requirement is not overly restrictive; however, it must not be forgotten. Stopping WCLK at this point in the write cycle could result in excessive current and even damage to the larger devices if many CLBs are con- figured as edge-triggered RAM. Table 5: Single-Port Edge-Triggered RAM Signals RAM Signal CLB Pin Function D DO or D1 (16x2, Data In 16x1), DO (32x1) A{3:0] F1-F4 or G1-G4 Address A(4] D1 (32x1) Address WE WE Write Enable WCLK K Clock SPO F or G Single Port Out (Data Out) (Data Out) July 30, 1997 (Version 1.2)XC4000E and XC4000X Series Field Programmable Gate Arrays Cy ee9y Gyo** Gq Ow WRITE 16-LATCH DECODER ARRAY FieeeFa 1of16 X6752 Figure 4: 16x2 (or 16x1) Edge-Triggered Single-Port RAM Cy 89g Gy o99 Gy FyeoeFy READ WRITE PULSE ADDRESS K (CLOCK) WRITE PULSE Figure 5: 32x1 Edge-Triggered Single-Port RAM (F and G addresses are Identical) 12 July 30, 1997 (Version 1.2)$< XILINX Dual-Port Edge-Triggered Mode In dual-port mode, both the F and G function generators are used to create a single 16x1 RAM array with one write port and two read ports. The resulting RAM array can be read and written simultaneously at two independent addresses. Simultaneous read and write operations at the same address are also supported. Dual-port mode always has edge-triggered write timing, as shown in Figure 3. Figure 6 shows a simple model of an XC4000 Series CLB configured as dual-port RAM. One address port, labeled A[3:0], supplies both the read and write address for the F function generator. This function generator behaves the same as a 16x1 single-port edge-triggered RAM array. The RAM output, Single Port Out (SPO), appears at the F func- tion generator output. SPO, therefore, reflects the data at address A[3:0]. The other address port, labeled DPRA(3:0] for Dual Port Read Address, supplies the read address for the G function generator. The write address for the G function generator, however, comes from the address A[3:0]. The output from this 16x1 RAM array, Dual Port Out (DPO), appears at the G function generator output. DPO, therefore, reflects the data at address DPRA[3:0]. Therefore, by using A[3:0] for the write address and DPRA[3:0] for the read address, and reading only the DPO output, a FIFO that can read and write simultaneously is easily generated. Simultaneous access doubles the effec- tive throughput of the FIFO. The relationships between CLB pins and RAM inputs and outputs for dual-port, edge-triggered mode are shown in Table 6. See Figure 7 on page 14 for a block diagram of a CLB configured in this mode. RAM16X1D Primitive DPO (Dual Port Out) Registered DPO SPO (Single Pont Out) Registered SPO xe7es : XC4000 Series Dual-Port RAM, Simple Table 6: Dual-Port Edge-Triggered RAM Signals Write Address for F and G addressed Note: The pulse following the active edge of WCLK (Twps in Figure 3) must be less than one millisecond wide. For most applications, this requirement is not overly restrictive; however, it must not be forgotten. Stopping WCLK at this point in the write cycle could result in excessive current and even damage to the larger devices if many CLBs are con- figured as edge-triggered RAM. Single-Port Level-Sensitive Timing Mode Note: Edge-triggered mode is recommended for all new designs. Level-sensitive mode, also called asynchronous mode, is still supported for XC4000 Series backward-com- patibility with the XC4000 family. Level-sensitive RAM timing is simple in concept but can be complicated in execution. Data and address signals are presented, then a positive pulse on the write enable pin (WE) performs a write into the RAM at the designated address. As indicated by the level-sensitive label, this RAM acts like a latch. During the WE High pulse, changing the data lines results in new data written to the old address. Changing the address lines while WE is High results in spu- rious data written to the new addressand possibly at other addresses as well, as the address lines inevitably do not all change simultaneously. The user must generate a carefully timed WE signal. The delay on the WE signal and the address lines must be care- fully verified to ensure that WE does not become active until after the address lines have settied, and that WE goes inactive before the address lines change again. The data must be stable before and after the falling edge of WE. In practical terms, WE is usually generated by a 2X clock. If a 2X clock is not available, the falling edge of the system clock can be used. However, there are inherent risks in this approach, since the WE pulse must be guaranteed inactive before the next rising edge of the system clock. Several older application notes are available from Xilinx that dis- cuss the design of level-sensitive RAMs. These application notes include XAPP031, Using the XC4000 RAM Capabil- ity and XAPP042, High-Speed RAM Design in XC4000 However, the edge-triggered RAM available in the XC4000 Series is superior to level-sensitive RAM for almost every application. July 30, 1997 (Version 1.2) 13XC4000E and XC4000X Series Fieid Programmable Gate Arrays 4 Cye*9 Cy Gyoe"Gy Fyeeeky (CLOCK) Figure 7: 16x1 Edge-Triggered Dual-Port RAM Figure 8 shows the write timing for level-sensitive, single- port RAM. The relationships between CLB pins and RAM inputs and outputs for single-port level-sensitive mode are shown in Table 7. Figure 9 and Figure 10 show block diagrams of a CLB con- figured as 16x2 and 32x1 level-sensitive, single-port RAM. initlalizing RAM at Configuration Both RAM and ROM implementations of the XC4000 Series devices are initialized during configuration. The ini- tial contents are defined via an INIT attribute or property WRITE PULSE X6748 attached to the RAM or ROM symbol, as described in the schematic library guide. If not defined, all RAM contents are initialized to all zeros, by default. RAM initialization occurs only during configuration. The RAM content is not affected by Global Set/Reset. Table 7: Singie-Port Level-Sensitive RAM Signais or or Twe ADDRESS 1 TAH Tas + WRITE ENABLE / DATA IN Figure 8: Level-Sensitive RAM Write Timing Twe Tos \ pee TH REQUIRED X6462 14 July 30, 1997 (Version 1.2)$< XILINX C199" Enable WRITE DECODER Go Gyere rere Ga 1 of 16 READ ADDRESS Enable DIN WRITE 16-LATCH DECODER ARRAY F Freee Fa 1 of 16 xe746 READ ADDRESS Figure 9: 16x2 (or 16x1) Level-Sensitive Single-Port RAM Cyeee Cy Enable WRITE DECODER GyeeeGy FyeeoF4 1 of 16 READ ADDRESS DIN Enable WRITE DECODER 16-LATCH ARRAY 1 of 16 READ ADDRESS X6749 Figure 10: 32x1 Level-Sensitive Single-Port RAM (F and G addresses are identical) July 30, 1997 (Version 1.2) 16XC4000E and XC4000X Series Field Programmable Gate Arrays Fast Carry Logic Each CLB F and G function generator contains dedicated arithmetic logic for the fast generation of carry and borrow signals. This extra output is passed on to the function gen- erator in the adjacent CLB. The carry chain is independent of normal routing resources. Dedicated fast carry logic greatly increases the efficiency and performance of adders, subtractors, accumulators, comparators and counters. It also opens the door to many new applications involving arithmetic operation, where the previous generations of FPGAs were not fast enough or too inefficient. High-speed address offset calculations in micro- processor or graphics systems, and high-speed addition in digital signal processing are two typical applications. The two 4-input function generators can be configured as a 2-bit adder with built-in hidden carry that can be expanded to any length. This dedicated carry circuitry is so fast and efficient that conventional speed-up methods like carry generate/propagate are meaningless even at the 16-bit level, and of marginal benefit at the 32-bit level. This fast carry logic is one of the more significant features of the XC4000 Series, speeding up arithmetic and counting into the 70 MHz range. The carry chain in XC4000E devices can run either up or down. At the top and bottom of the columns where there are no CLBs above and below, the carry is propagated to the right. (See Figure 11.) In order to improve speed in the high-capacity XC4000X devices, which can potentially have very long carry chains, the carry chain travels upward only, as shown in Figure 12. Additionally, standard intercon- nect can be used to route a carry signal in the downward direction. Figure 13 on page 17 shows an XC4000E CLB with dedi- cated fast carry logic. The carry logic in the XC4000X is similar, except that COUT exits at the top only, and the sig- nal CINDOWN does not exist. As shown in Figure 13, the carry logic shares operand and control inputs with the func- tion generators. The carry outputs connect to the function generators, where they are combined with the operands to form the sums. Figure 14 on page 18 shows the details of the carry logic for the XC4000E. This diagram shows the contents of the box labeled CARRY LOGIC in Figure 13. The XC4000X carry logic is very similar, but a multiplexer on the pass-through carry chain has been eliminated to reduce delay. Addition- aily, in the XC4000X the multiplexer on the G4 path has a memory-programmable 0 input, which permits G4 to directly connect to COUT. G4 thus becomes an additional high-speed initialization path for carry-in. The dedicated carry logic is discussed in detail in Xilinx document XAPP 013: Using the Dedicated Carry Logic in XC4000 This discussion also applies to XC4000E devices, and to XC4000X devices when the minor logic changes are taken into account. The fast carry logic can be accessed by placing special library symbols, or by using Xilinx Relationally Placed Mac- ros (RPMs) that already include these symbois. CLB CLB /-++> CLB +| CLB $f if ff Ti CLB CLB CLB CLB Ze Gt Ft FF CLB CcLB CLB CLB ti if ft Ui CLB CLB /;4++ CLB >| CLB Figure 11: Available XC4000E Carry Propagation Paths CLB }-;-+ CLB }-;-+| CLB }-,-+ CLB Libr 4 CLB i CLB Le CLB i CLB FoF FS CLB Le CLB Le CLB i CLB fo tt cLB i CLB i cLB i CLB X6610 Figure 12: Available XC4000X Carry Propagation Paths (dotted lines use general Interconnect) 16 July 30, 1997 (Version 1.2)$2 XILINX a K Cinup Cout Figure 13: Fast Carry Logic In XC4000E CLB (shaded area not present in XC4000X) S/R X6699 July 30, 1997 (Version 1.2) 17XC4000E and XC4000X Series Field Programmable Gate Arrays oF De a Cour / \ G3- Couto TO m4y te o SoveRstons fo__+\ " Le Hye a : 7 G 1 \ e F3 1 cm t 0 x2000 Cinup Cin DOWN Figure 14: Detail of XC4000E Dedicated Carry Logic Input/Output Blocks (lOBs) User-configurable input/output blocks (IOBs) provide the interface between external package pins and the internal logic. Each |OB controls one package pin and can be con- figured for input, output, or bidirectional signals. Figure 15 shows a simplified biock diagram of the XC4000E IOB. A more complete diagram of the XC4000E 1OB can be found in Figure 40 on page 41, in the Boundary Scan section. Figure 40 includes the boundary scan logic in the lOB. Figure 16 shows a simplified biock diagram of the XC4000X 1OB. The XC4000X IOB contains some special features not included in the XC4000E IOB. These features are highlighted in Figure 16, and discussed throughout this section. When XC4000X special features are discussed, they are clearly identified in the text. Any feature not so identified is present in both XC4Q00E and XC4000X devices. JOB Input Signals Two paths, labeled I1 and I2 in Figure 15 and Figure 16, bring input signals into the array. Inputs also connect to an input register that can be programmed as either an edge- triggered flip-flop or a level-sensitive latch. The choice is made by placing the appropriate library sym- bol. For example, IFD is the basic input flip-flop (rising edge triggered), and ILD is the basic input latch (transparent- High). Variations with inverted clocks are available, and some combinations of latches and flip-flops can be imple- mented in a single OB, as described in the XACT Libraries Guide. The XC4000E inputs can be globally configured for either TTL (1.2V) or 5.0 volt CMOS thresholds, using an option in the bitstream generation software. There is a slight input hysteresis of about 300mV. The XC4000E output levels are also configurable; the two global adjustments of input threshold and output level are independent. inputs on the XC4000XL are TTL compatible and 3.3V CMOS compatible. Outputs on the XC4000XL are pulled to the 3.3V positive supply. The inputs of XC4000 Series 5-Volt devices can be driven by the outputs of any 3.3-Volt device, if the 5-Volt inputs are in TTL mode. Supported sources for XC4000 Series device inputs are shown in Table 8. 18 July 30, 1997 (Version 1.2)$< XILINX Slew Rate Pau Pull-Down I : : Control rt t , r FipFiep |) Li | /~ : - on Pp 9 I LL Output ep - CE Buffer ' Output ' Clock | ' I 1 1 L Flip- Input ' 1 Flop/ Buffer ' o! Latch \ 2 ne 1 ! [ : Qa D ~ 1 1 1 I Clock _! ' 1 ' ' ' 5 1 Enable cE Input | Clock 1 Xx6704 I . Pull-Up/ \ Control Pull-Down I tT 5 Output MUX 1 a t 1 . 1 t 2 : i I I Clock Enable Input Clock 5984 Figure 16: Simplified Block Diagram of XC4000X IOB (shaded areas indicate differences from XC4000E) duly 30, 1997 (Version 1.2) 19XC4000E snd XC4000X Series Field Programmable Gate Arrays Table 8: Supported Sources for XC4000 Series Device Inputs XC4000E/EX | XC4000XL Serles Inputs Series inputs Source 5V, | 5V, 3.3V TTL |CMOS CMOS Any device, Vcc = 3.3 V, V y CMOS outputs XC4000 Series, Vec=5V) | veper y TTL outputs Data Any device, Vcc = 5 V, V v TTL outputs (Voh < 3.7 V) Any device, Vec = 5 V, v V V CMOS outputs XC4000XL 5-Volt Tolerant /Os The I/Os on the XC4000XL are fully 5-volt tolerant even though the Voc is 3.3 volts. This allows 5 V signals to directly connect to the XC4000XL inputs without damage, as shown in Table 8. In addition, the 3.3 volt Vcc can be applied before or after 5 volt signals are applied to the I/Os. This makes the XC4000XL immune to power supply sequencing problems. Registered Inputs The I1 and 12 signals that exit the block can each carry either the direct or registered input signal. The input and output storage elements in each IOB have a common clock enabie input, which, through configuration, can be. activated individually for the input or output flip-flop, or both. This clock enable operates exactly like the EC pin on the XC4000 Series CLB. It cannot be inverted within the IOB. The storage element behavior is shown in Table 9. Table 9: Input Register Functionality (active rising edge is shown) Clock Mode Clock Enable D Qa Power-Up or X x x SR GSR Flip-Flop _f D D 0 xX xX Q Latch 1 1" X Q 0 1% D D Both x 0 x Q Legend: x Dont care _f- Rising edge SR Set or Reset value. Reset is default. o* Input is Low or unconnected (default value) 1 Input is High or unconnected (default value) Optional Delay Guarantees Zero Hold Time The data input to the register can optionally be delayed by several nanoseconds. With the delay enabled, the setup time of the input flip-flop is increased so that normal clock routing does not result in a positive hold-time requirement. A positive hold time requirement can lead to unreliable, temperature- or processing-dependent operation. The input flip-flop setup time is defined between the data measured at the device 1/O pin and the clock input at the IOB (not at the clock pin). Any routing delay from the device clock pin to the clock input of the 1OB must, therefore, be subtracted from this setup time to arrive at the real setup time requirement relative to the device pins. A short speci- fied setup time might, therefore, result in a negative setup time at the device pins, i.e., a positive hold-time require- ment. When a delay is inserted on the data line, more clock delay can be tolerated without causing a positive hoid-time requirement. Sufficient delay eliminates the possibility of a data hold-time requirement at the external pin. The maxi- mum delay is therefore inserted as the default. The XC4000E IOB has a one-tap delay element: either the delay is inserted (default), or it is not. The delay guarantees a zero hold time with respect to clocks routed through any of the XC4000E global clock buffers. (See Global Nets and Buffers (XC4000E only) on page 33 for a description of the global clock buffers in the XC4000E.) For a shorter input register setup time, with non-zero hold, attach a NODELAY attribute or property to the flip-flop. The XC4000X IOB has a two-tap delay element, with choices of a full delay, a partial delay, or no delay. The attributes or properties used to select the desired delay are shown in Table 10. The choices are no added attribute, MEDDELAY, and NODELAY. The default setting, with no added attribute, ensures no hold time with respect to any of the XC4000X clock buffers, including the Global Low-Skew buffers. MEDDELAY ensures no hold time with respect to the Global Early buffers. Inputs with NODELAY may have a positive hold time with respect to all clock buffers. For a description of each of these buffers, see Global Nets and Buffers (XC4000X only) on page 35. Table 10: XC4000X OB Input Delay Element Value When to Use full delay Zero Hold with respect to Global Low- (default, no Skew Buffer, Global Early Buffer attribute added) MEDDELAY Zero Hold with respect to Global Early Butfer NODELAY Short Setup, positive Hold time 20 July 30, 1997 (Version 1.2)$2 XILINX Additional Input Latch for Fast Capture (XC4000X only) The XC4000X IOB has an additional optional latch on the input. This latch, as shown in Figure 16, is clocked by the output clock the clock used for the output flip-flop. rather than the input clock. Therefore, two different clocks can be used to clock the two input storage elements. This additional latch allows the very fast capture of input data, which is then synchronized to the internal clock by the IOB flip-flop or latch. To use this Fast Capture technique, drive the output clock pin (the Fast Capture latching signal) from the output of one of the Global Early buffers supplied in the XC4000X. The second storage element should be clocked by a Global Low-Skew buffer, to synchronize the incoming data to the internal logic. (See Figure 17.) These special buffers are described in Global Nets and Buffers (XC4000X only) on page 35. The Fast Capture latch (FCL) is designed primarily for use with a Global Early buffer. For Fast Capture, a single clock signal is routed through both a Global Early buffer and a Global Low-Skew buffer. (The two buffers share an input pad.) The Fast Capture latch is clocked by the Global Early buffer, and the standard IOB flip-flop or latch is clocked by the Global Low-Skew buffer. This mode is the safest way to use the Fast Capture latch, because the clock buffers on both storage elements are driven by the same pad. There is no external skew between clock pads to create potential problems. To place the Fast Capture latch in a design, use one of the special library symbols, ILFFX or ILFLX. ILFFX is a trans- parent-Low Fast Capture latch followed by an active-High input flip-flop. ILFLX is a transparent-Low Fast Capture latch followed by a transparent-High input latch. Any of the clock inputs can be inverted before driving the library ele- ment, and the inverter is absorbed into the IOB. If a single BUFG output is used to drive both clock inputs, the soft- the desired delay based on the discussion in the previous subsection. OB Output Signals Output signals can be optionally inverted within the IOB, and can pass directly to the pad or be stored in an edge- triggered flip-flop. The functionality of this flip-flop is shown in Table 11. An active-High 3-state signal can be used to place the out- put buffer in a high-impedance state, implementing 3-state outputs or bidirectional 1/O. Under configuration control, the output (OUT) and output 3-state (T) signals can be inverted. The polarity of these signals is independently con- figured for each IOB. The 4-mA maximum output current specification of many FPGAs often forces the user to add external buffers, which are especially cumbersome on bidirectional |/O lines. The XC4000E and XC4000EX/XL devices solve many of these problems by providing a guaranteed output sink current of 12 mA. Two adjacent outputs can be interconnected exter- nally to sink up to 24 mA. The XC4000E and XC4000EX/XL FPGAs can thus directly drive buses on a printed circuit board. By default, the output pull-up structure is configured as a TTL-like totem-pole. The High driver is an n-channel pull-up - transistor, pulling to a voltage one transistor threshold below Vcc. Alternatively, the outputs can be globally config- ured as CMOS drivers, with p-channel pull-up transistors puiling to Vcc. This option, applied using the bitstream gen- eration software, applies to all outputs on the device. It is not individually programmable. in the XC4000XL, all out- puts are pulled to the positive supply rail. Table 11: Output Flip-Flop Functionality (active rising edge is shown) . Clock ware automatically runs the clock through both a Global Low-Skew buffer and a Global Early buffer, and clocks the Mode | Glock | Enable T D Q Fast Capture latch appropriately. Powe x x 0 x SR or Figure 16 on page 19 also shows a two-tap delay on the X 0 0* X Q input. By default, if the Fast Capture latch is used, the Xilinx ; a 7 0 D 5 software assumes a Global Early buffer is driving the clock, Flip-Flop _ and selects MEDDELAY to ensure a zero hold time. Select x x 1 us Zz 0 x 0* Xx Q | ILFFX Legend: x Don't care 1PAD D Qa to internal _/f Rising edge fogie SR Set or Reset value. Reset is default. o* Input is Low or unconnected (default value) * Input is High or unconnected (default value) Zz 3-state BUFGLS X9013 Figure 17: Examples Using XC4000X FCL July 30, 1997 (Version 1.2) 21XC4000E and XC4000X Series Fleid Programmabie Gate Arrays Any XC4000 Series 5-Volt device with its outputs config- ured in TTL mode can drive the inputs of any typical 3.3- Volt device. (For a detailed discussion of how to interface between 5 V and 3.3 V devices, see the 3V Products sec- tion of The Programmable Logic Data Book.) Supported destinations for XC4000 Series device outputs are shown in Table 12. An output can be configured as open-drain (open-collector) by placing an OBUFT symbol in a schematic or HDL code, then tying the 3-state pin (T) to the output signal, and the input pin (1) to Ground. (See Figure 18.) Table 12: Supported Destinations for XC4000 Series Outputs XC4000 Series Outputs Destination 3.3V,| 5V, 5V, CMOS, TTL | CMOS Any typical device, Voc =3.3V) = V Vv | some! CMOS-threshold inputs Any device, Vcc = 5 V, v V V TTL-threshoid inputs Any device, Vcc = 5 V, Unreliable V CMOS-threshold inputs Data 1. Only if destination device has 5-V tolerant inputs OPAD OBUFT xe702 Figure 18: Open-Drain Output Output Slew Rate The slew rate of each output buffer is, by default, reduced, to minimize power bus transients when switching non-criti- cal signals. For critical signals, attach a FAST attribute or property to the output buffer or flip-flop. For XC4000E devices, maximum total capacitive load for simultaneous fast mode switching in the same direction is 200 pF for all package pins between each Power/Ground pin pair. For XC4000X devices, additional internal Power/ Ground pin pairs are connected to special Power and Ground planes within the packages, to reduce ground bounce. Therefore, the maximum total capacitive load is 300 pF between each external Power/Ground pin pair. Maximum loading may vary for the low-voltage devices. For slew-rate limited outputs this total is two times larger for each device type: 400 pF for XC4000E devices and 600 pF for XC4000X devices. This maximum capacitive load should not be exceeded, as it can result in ground bounce of greater than 1.5 V amplitude and more than 5 ns dura- tion. This level of ground bounce may cause undesired transient behavior on an output, or in the internal logic. This restriction is common to all high-speed digital ICs, and is not particular to Xilinx or the XC4000 Series. XC4000 Series devices have a feature called Soft Start- up, designed to reduce ground bounce when all outputs are turned on simultaneously at the end of configuration. When the configuration process is finished and the device starts up, the first activation of the outputs is automatically slew-rate limited. Immediately following the initial activation of the I/O, the slew rate of the individual outputs is deter- mined by the individual configuration option for each !OB. Global Three-State A separate Global 3-State line (not shown in Figure 15 or Figure 16) forces all FPGA outputs to the high-impedance state, unless boundary scan is enabled and is executing an EXTEST instruction. This global net (GTS) does not com- pete with other routing resources; it uses a dedicated distri- bution network. GTS can be driven from any user-programmable pin as a global 3-state input. To use this global net, place an input pad and input buffer in the schematic or HDL code, driving the GTS pin of the STARTUP symbol. A specific pin loca- tion can be assigned to this input using a LOC attribute or property, just as with any other user-programmable pad. An inverter can optionally be inserted after the input buffer to invert the sense of the Global 3-State signal. Using GTS is similar to GSR. See Figure 2 on page 9 for details. Alternatively, GTS can be driven from any internal node. 22 July 30, 1997 (Version 1.2)Output Multiptexer/2-Input Function Generator (XC4000X only) As shown in Figure 16 on page 19, the output path in the XC4000X IOB contains an additional multiplexer not avail- able in the XC4000E IOB. The multiplexer can also be con- figured as a 2-input function generator, implementing a pass-gate, AND-gate, OR-gate, or XOR-gate, with 0, 1, or 2 inverted inputs. The logic used to implement these func- tions is shown in the upper gray area of Figure 16. When configured as a multiplexer, this feature allows two output signals to time-share the same output pad; effec- tively doubling the number of device outputs without requir- ing a larger, more expensive package. When the MUX is configured as a 2-input function genera- tor, logic can be implemented within the IOB itself. Com- bined with a Global Early buffer, this arrangement allows very high-speed gating of a single signal. For example, a wide decoder can be implemented in CLBs, and its output gated with a Read or Write Strobe Driven by a BUFGE buffer, as shown in Figure 19. The critical-path pin-to-pin delay of this circuit is less than 6 nanoseconds. As shown in Figure 16, the 1OB input pins Out, Output Clock, and Clock Enable have different delays and different flexibilities regarding polarity. Additionally, Output Clock sources are more limited than the other inputs. Therefore, the Xilinx software does not move logic into the LOB func- tion generators unless explicitly directed to do so. The user can specify that the IOB function generator be used, by placing special library symbols beginning with the letter O. For example, a 2-input AND-gate in the |OB func- tion generator is called OAND2. Use the symbol input pin labelled F for the signal on the critical path. This signal is .placed on the OK pin the IOB input with the shortest delay to the function generator. Two examples are shown in Figure 20. [PAD > > BUFGE F OPAD fom FAST internal OAND2 logic X9019 Figure 19: Fast Pin-to-Pin Path In XC4000X OMUX2 Do F o 1 OAND2 so Figure 20: AND & MUX Symbols in XC4000X [OB $< XILINX Other iOB Options There are a number of other programmable options in the XC4000 Series OB. Pull-up and Pull-down Resistors Programmable pull-up and pull-down resistors are useful for tying unused pins to Vcc or Ground to minimize power consumption and reduce noise sensitivity. The configurable pull-up resistor is a p-channel transistor that pulls to Vec. The configurable pull-down resistor is an n-channel transis- tor that pulls to Ground. The value of these resistors is 50 kQ 100 kQ This high value makes them unsuitable as wired-AND pull-up resis- tors. The pull-up resistors for most user-programmable IOBs are active during the configuration process. See Table 22 on page 64 for a list of pins with pull-ups active before and dur- ing configuration. After configuration, voltage levels of unused pads, bonded or unbonded, must be valid logic levels, to reduce noise sensitivity and avoid excess current. Therefore, by default, unused pads are configured with the internal pull-up resis- tor active. Alternatively, they can be individually configured with the pull-down resistor, or as a driven output, or to be driven by an external source. To activate the internal pull- up, attach the PULLUP library component to the net attached to the pad. To activate the internal pull-down, attach the PULLDOWN library component to the net attached to the pad. Independent Clocks Separate clock signals are provided for the input and output flip-flops. The clock can be independently inverted for each flip-flop within the lIOB, generating either falling-edge or ris- ing-edge triggered flip-flops. The clock inputs for each |OB are independent, except that in the XC4000X, the Fast Capture latch shares an IOB input with the output clock pin. Early Clock for IOBs (XC4000X only) Special early clocks are available for |OBs. These clocks are sourced by the same sources as the Global Low-Skew buffers, but are separately buffered. They have fewer loads and therefore less delay. The early clock can drive either the 1OB output clock or the IOB input clock, or both. The early clock allows fast capture of input data, and fast clock- to-output on output data. The Global Early buffers that drive these clocks are described in Global Nets and Buffers (XC4000X only) on page 35. Global Set/Reset As with the CLB registers, the Global Set/Reset signal (GSR) can be used to set or clear the input and output reg- isters, depending on the value of the !NIT attribute or prop- erty. The two flip-flops can be individually configured to set July 30, 1997 (Version 1.2) 23XC4000E and XC4000X Series Field Programmable Gate Arrays or clear on reset and after configuration. Other than the glo- bal GSR net, no user-controlied set/reset signal is available to the l/O flip-flops. The choice of set or clear applies to both the initial state of the flip-flop and the response to the Global Set/Reset pulse. See Global Set/Reset on page 9 for a description of how to use GSR. JTAG Support Embedded logic attached to the IOBs contains test struc- tures compatible with IEEE Standard 1149.1 for boundary scan testing, permitting easy chip and board-level testing. More information is provided in Boundary Scan on page 40. Three-State Buffers A pair of 3-state buffers is associated with each CLB in the array. (See Figure 27 on page 28.) These 3-state buffers can be used to drive signals onto the nearest horizontal longlines above and below the CLB. They can therefore be used to implement multiplexed or bidirectional buses on the horizontal longlines, saving logic resources. Programmable pull-up resistors attached to these longlines help to impie- ment a wide wired-AND function. The butfer enable is an active-High 3-state (i.e. an active- Low enable), as shown in Table 13. Another 3-state buffer with similar access is located near each I/O block along the right and left edges of the array. (See Figure 33 on page 32.) The horizontal fonglines driven by the 3-state buffers have a weak keeper at each end. This circuit prevents undefined floating levels. However, it is overridden by any driver, even a pull-up resistor. Special longlines running along the perimeter of the array can be used to wire-AND signals coming from nearby [OBs or from internal longlines. These longlines form the wide edge decoders discussed in Wide Edge Decoders on page 25. Three-State Buffer Modes The 3-state buffers can be configured in three modes: Standard 3-state buffer Wired-AND with input on the | pin Wired OR-AND Standard 3-State Buffer All three pins are used. Place the library element BUFT. Connect the input to the | pin and the output to the O pin. The T pin is an active-High 3-state (i.e. an active-Low enable). Tie the T pin to Ground to implement a standard buffer. Wired-AND with Input on the | Pin The buffer can be used as a Wired-AND. Use the WAND1 library symbol, which is essentially an open-drain buffer. WAND4, WANDS, and WAND 16 are also available. See the XACT Libraries Guide for further information. The T pin is internally tied to the | pin. Connect the input to the | pin and the output to the O pin. Connect the outputs of all the WAND1s together and attach a PULLUP symbol. Wired OR-AND The buffer can be configured as a Wired OR-AND. A High level on either input turns off the output. Use the WORZAND library symbol, which is essentially an open- drain 2-input OR gate. The two input pins are functionally equivalent. Attach the two inputs to the 10 and I1 pins and tie the output to the O pin. Tie the outputs of all the WORZ2ANDs together and attach a PULLUP symbol. Three-State Buffer Examples Figure 21 shows how to use the 3-state buffers to imple- ment a wired-AND function. When all the buffer inputs are High, the pull-up resistor(s) provide the High output. Figure 22 shows how to use the 3-state buffers to imple- ment a multiplexer. The selection is accomplished by the buffer 3-state signal. Pay particular attention to the polarity of the T pin when using these buffers in a design. Active-High 3-state (T) is identical to an active-Low output enable, as shown in Table 13. Table 13: Three-State Buffer Functionality IN T OUT xX 1 Z IN 0 IN Z=D, 0D, 0(0,+D,) #(D,+D,) u u L P "a Dp! e Wann o WORZAND WORZAND Figure 21: Open-Drain Buffers Implement a Wired-AND Function 24 July 30, 1997 (Version 1.2)~100 kaa $< XILINX Z=DytA+DyeB+0g9C+0,N Figure 22: 3-State Buffers Implement a Multiplexer Wide Edge Decoders Dedicated decoder circuitry boosts the performance of wide decoding functions. When the address or data field is wider than the function generator inputs, FPGAs need multi-level decoding and are thus slower than PALs. XC4000 Series CLBs have nine inputs. Any decoder of up to nine inputs is, therefore, compact and fast. However, there is also a need for much wider decoders, especially for address decoding in large microprocessor systems. An XC4000 Series FPGA has four programmable decoders located on each edge of the device. The inputs to each decoder are any of the 1OB 11 signals on that edge plus one local interconnect per CLB row or column. Each row or col- umn of CLBs provides up to three variables or their compli- ments., as shown in Figure 23. Each decoder generates a High output (resistor pull-up) when the AND condition of the selected inputs, or their complements, is true. This is analogous to a product term in typical PAL devices. Each of these wired-AND gates is capable of accepting up to 42 inputs on the XC4005E and 72 on the XC4013E. There are up to 96 inputs for each decoder on the XC4028X and 132 on the XC4052X. The decoders may also be split in two when a larger number of narrower decoders are required, for a maximum of 32 decoders per device. The decoder outputs can drive CLB inputs, so they can be combined with other logic to form a PAL-like AND/OR struc- ture. The decoder outputs can also be routed directly to the chip outputs. For fastest speed, the output should be on the same chip edge as the decoder. Very large PALs can be emulated by ORing the decoder outputs in a CLB. This decoding feature covers what has long been considered a weakness of older FPGAs. Users often resorted to external PALs for simple but fast decoding functions. Now, the dedi- cated decoders in the XC4000 Series device can imple- ment these functions fast and efficiently. To use the wide edge decoders, place one or more of the WAND library symbols (WAND1, WAND4, WANDS, WAND16). Attach a DECODE attribute or property to each WAND symbol. Tie the outputs together and attach a PUL- ry 0, Dy BUFT BUFT BUFT B c N xB486- LUP symbol. Location attributes or properties such as L (left edge) or TR (right half of top edge) should also be used to ensure the correct placement of the decoder inputs. INTERCONNECT Figure 23: XC4000 Series Edge Decoding Example OSC4 Fem FS00K F16K F490 F15 PTT | X6703 Figure 24: XC4000 Series Oscillator Symbol On-Chip Oscillator XC4000 Series devices include an internal oscillator. This oscillator is used to clock the power-on time-out, for config- uration memory clearing, and as the source of CCLK in Master configuration modes. The oscillator runs at a nomi- nal 8 MHz frequency that varies with process, Vcc, and temperature. The output frequency falls between 4 and 10 MHz. July 30, 1997 (Version 1.2) 25XC4000E and XC4000X Series Field Programmabie Gate Arrays The oscillator output is optionally available after configura- tion. Any two of four resynchronized taps of a built-in divider are also available. These taps are at the fourth, ninth, four- teenth and nineteenth bits of the divider. Therefore, if the primary oscillator output is running at the nominal 8 MHz, the user has access to an 8 MHz clock, plus any two of 500 kHz, 16kHz, 490Hz and 15Hz (up to 10% lower for low-volt- age devices). These frequencies can vary by as much as - 50% or +25%. These signals can be accessed by placing the OSC4 library element in a schematic or in HDL code (see Figure 24). The oscillator is automatically disabled after configuration if the OSC4 symbol is not used in the design. Programmable Interconnect All internal connections are composed of metal segments with programmabie switching points and switching matrices to implement the desired routing. A structured, hierarchical matrix of routing resources is provided to achieve efficient automated routing. The XC4000E and XC4000X share a basic interconnect structure. XC4000X devices, however, have additional rout- ing not available in the XC4000E. The extra routing resources allow high utilization in high-capacity devices. All XC4000X-specific routing resources are clearly identified throughout this section. Any resources not identified as XC4000x-specific are present in all XC4000 Series devices. This section describes the varied routing resources avail- able in XC4000 Series devices. The implementation soft- ware automatically assigns the appropriate resources based on the density and timing requirements of the design. Interconnect Overview There are several types of interconnect. * CLB routing is associated with each row and column of the CLB array. IOB routing forms a ring (cailed a VersaRing) around the outside of the CLB array. It connects the I/O with the internal logic blocks. Global routing consists of dedicated networks primarily designed to distribute clocks throughout the device with minimum delay and skew. Global routing can also be used for other high-fanout signals. Five interconnect types are distinguished by the relative length of their segments: single-length lines, double-length lines, quad and octal lines (XC4000X only), and longlines. In the XC4000X, direct connects allow fast data flow between adjacent CLBs, and between iOBs and CLBs. Extra routing is included in the IOB pad ring. The XC4000X also includes a ring of octal interconnect lines near the IOBs to improve pin-swapping and routing to locked pins. XC4000E/X devices include two types of global buffers. These global buffers have different properties, and are intended for different purposes. They are discussed in detail later in this section. CLB Routing Connections A high-level diagram of the routing resources associated with one CLB is shown in Figure 25. The shaded arrows represent routing present only in XC4000X devices. Table 14 shows how much routing of each type is available in XC4000E and XC4000X CLB arrays. Clearly, very large designs, or designs with a great deal of interconnect, will route more easily in the XC4000X. Smaller XC4000E designs, typically requiring significantly less interconnect, do not require the additional routing. Figure 27 on page 28 is a detailed diagram of both the XC4000E and the XC4000X CLB, with associated routing. The shaded square is the programmable switch matrix, present in both the XC4000E and the XC4000X. The L- shaped shaded area is present only in XC4000X devices. As shown in the figure, the XC4000X block is essentially an XC4000E block with additional routing. CLB inputs and outputs are distributed on all four sides, providing maximum routing flexibility. In general, the entire architecture is symmetrical and regular. It is well suited to established placement and routing algorithms. inputs, out- puts, and function generators can freely swap positions within a CLB to avoid routing congestion during the place- ment and routing operation. 26 July 30, 1997 (Version 1.2)$= XILINX Quad Long Global Long Double Single Global Clock Quad Single Double Long Direct Connect Long 4 Carry Direct Clock Chain Connect x5994 Figure 25: High-Level Routing Diagram of XC4000 Serles CLB (shaded arrows Indicate XC4000X only) Tabie 14: Routing per CLB in XC4000 Series Devices XC4000E XC4000X Vertical | Horizontal) Vertical | Horizontal Singles 8 8 8 8 Doubles 4 4 4 4 Quads 0 0 12 12 Longlines 6 6 10 6 Direct 0 0 2 2 Connects Globals 4 0 8 0 Carry Logic 2 0 1 0 Total 24 18 45 32 Programmable Switch Matrices The horizontal and vertical single- and double-length lines intersect at a box called a programmable switch matrix (PSM). Each switch matrix consists of programmable pass transistors used to establish connections between the lines (see Figure 26). For example, a single-length signal entering on the right side of the switch matrix can be routed to a single-length line on the top, left, or bottom sides, or any combination thereof, if multiple branches are required. Similarly, a dou- ble-length signal can be routed to a doubie-length line on any or all of the other three edges of the programmable switch matrix. 2 ss 3 so? eo Y 9 9 Double Singles Six Pass Transistors Per Switch Matrix Daubie Interconnect Point xX6600 Figure 26: Programmable Switch Matrix (PSM) Single-Length Lines Single-length lines provide the greatest interconnect flexi- bility and offer fast routing between adjacent blocks. There are eight vertical and eight horizontal single-length lines associated with each CLB. These lines connect the switch- ing matrices that are located in every row and a column of CLBs. Single-length lines are connected by way of the program- mable switch matrices, as shown in Figure 28. Routing connectivity is shown in Figure 27. Single-length lines incur a delay whenever they go through a switching matrix. Therefore, they are not suitable for rout- ing signals for jong distances. They are normally used to conduct signals within a localized area and to provide the branching for nets with fanout greater than one. July 30, 1997 (Version 1.2) 27XC4000E and XC4000X Series Field Programmabie Gate Arrays QUAD DOUBLE SINGLE DOUBLE LONG DIRECT \ FEEDBACK LONG -____- ee & < Gg 9 we %, Ng ag Ye % Ye ey Oy my % "% e & te % a Qe & oy, [1 Common to XC4000E and XC4000X XC4000X only @B Programmable Switch Matrix Figure 27: Detail of Programmable interconnect Associated with XC4000 Series CLB 28 July 30, 1997 (Version 1.2)$< XILINX Doubles Singles Doubles e601 Figure 28: Single- and Double-Length Lines, with Programmable Switch Matrices (PSMs) Double-Length Lines The double-length lines consist of a grid of metal segments, each twice as long as the single-length lines: they run past two CLBs before entering a switch matrix. Double-length lines are grouped in pairs with the switch matrices stag- gered, so that each line goes through a switch matrix at every other row or column of CLBs (see Figure 28). There are four vertical and four horizontal double-length lines associated with each CLB. These lines provide faster signal routing over intermediate distances, while retaining routing flexibility. Double-iength lines are connected by way of the programmable switch matrices. Routing connectivity is shown in Figure 27. Quad Lines (XC4000X only) XC4000X devices also include twelve vertical and twelve horizontal quad lines per CLB row and column. Quad lines are four times as long as the single-length lines. They are interconnected via butfered switch matrices (shown as dia- monds in Figure 27 on page 28). Quad tines run past four CLBs before entering a buffered switch matrix. They are grouped in fours, with the buffered switch matrices stag- gered, so that each line goes through a buffered switch matrix at every fourth CLB location in that row or column. (See Figure 29.) The buffered switch matrixes have four pins, one on each edge. All of the pins are bidirectional. Any pin can drive any or all of the other pins. Each buffered switch matrix contains one buffer and six pass transistors. It resembles the programmable switch matrix shown in Figure 26, with the addition of a program- mabie buffer. There can be up to two independent inputs x9014 Figure 29: Quad Lines (XC4000X only) and up to two independent outputs. Only one of the inde- pendent inputs can be buffered. The place and route software automaticaily uses the timing requirements of the design to determine whether or not a quad line signal should be buffered. A heavily loaded signal is typically buffered, while a lightly loaded one is not. One scenario is to alternate buffers and pass transistors. This allows both vertical and horizontal quad lines to be buffered at alternating buffered switch matrices. Due to the buffered switch matrices, quad lines are very fast. They provide the fastest available method of routing heavily loaded signals for long distances across the device. Longlines Longlines form a grid of metal interconnect segments that run the entire length or width of the array. Longlines are intended for high fan-out, time-critical signal nets, or nets that are distributed over long distances. In XC4000X devices, quad lines are preferred for critical nets, because the buffered switch matrices make them faster for high fan- out nets. Two horizontal longlines per CLB can be driven by 3-state or open-drain drivers (TBUFs). They can therefore imple- ment unidirectional or bidirectional buses, wide multiplex- ers, or wired-AND functions. (See Three-State Buffers on page 24 for more details.) Each horizontal longline driven by TBUFs has either two (XC4000E) or eight (XC4000X) pull-up resistors. To acti- vate these resistors, attach a PULLUP symbol to the long- line net. The software automatically activates the appropri- ate number of pull-ups. There is also a weak keeper at each end of these two horizontal longlines. This circuit pre- July 30, 1997 (Version 1.2) 29XC4000E and XC4000X Series Field Programmabie Gate Arrays vents undefined floating levels. However, it is overridden by any driver, even a pull-up resistor. Each XC4000E longline has a programmabie splitter switch at its center, as does each XC4000X longline driven by TBUFs. This switch can separate the line into two indepen- dent routing channels, each running half the width or height of the array. Each XC4000X longline not driven by TBUFs has a buff- ered programmable splitter switch at the 1/4, 1/2, and 3/4 points of the array. Due to the buffering, XC4000X longline performance does not deteriorate with the larger array sizes. If the longline is split, the resulting partial longlines are independent. Routing connectivity of the longlines is shown in Figure 27 on page 28. Direct interconnect (XC4000X only) The XC4000X offers two direct, efficient and fast connec- tions between adjacent CLBs. These nets facilitate a data flow from the left to the right side of the device, or from the top to the bottom, as shown in Figure 30. Signals routed on the direct interconnect exhibit minimum interconnect prop- agation delay and use no general routing resources. The direct interconnect is also present between CLBs and adjacent IOBs. Each {OB on the left and top device edges has a direct path to the nearest CLB. Each CLB on the right and bottom edges of the array has a direct path to the near- est two IOBs, since there are two IOBs for each row or col- umn of CLBs. The place and route software uses direct interconnect whenever possible, to maximize routing resources and min- imize interconnect delays. 3] (8 &| |B | | 10B p2 +>{_108_| on CLB Lape CLB CLB os Lob ao Lo neo tot Toft i { } - = | ae CLB mI or] id Ge Be Figure 30: XC4000X Direct Interconnect VO Routing XC4000 Series devices have additional routing around the 108 ring. This routing is called a VersaRing. The VersaRing facilitates pin-swapping and redesign without affecting board layout. Included are eight double-length lines span- ning two CLBs (four IOBs), and four longlines. Giobal lines and Wide Edge Decoder lines are provided. XC4000X devices also include eight octal lines. A high-level diagram of the VersaRing is shown in Figure 31. The shaded arrows represent routing present only in XC4000X devices. Figure 33 on page 32 is a detailed diagram of the XC4000E and XC4000X VersaRing. The area shown includes two IOBs. There are two IOBs per CLB row or column, there- fore this diagram corresponds to the CLB routing diagram shown in Figure 27 on page 28. The shaded areas repre- sent routing and routing connections present only in XC4000X devices. Octal /O Routing (XC4000X only) Between the XC4000X CLB array and the pad ring, eight interconnect tracks provide for versatility in pin assignment and fixed pinout flexibility. (See Figure 32 on page 31.) These routing tracks are called octals, because they can be broken every eight CLBs (sixteen IOBs) by a programma- ble buffer that also functions as a splitter switch. The buffers are staggered, so each line goes through a buffer at every eighth CLB location around the device edge. The octal lines bend around the corners of the device. The lines cross at the corners in such a way that the segment most recently buffered before the turn has the farthest dis- tance to travel before the next buffer, as shown in Figure 32. 30 July 30, 1997 (Version 1.2)$2 XILINX Quad Single Double Long Direct Connect Long Direct Edge Double Long Global Octal Connect Decode Clock X5095 Figure 31: High-Level Routing Diagram of XC4000 Series VersaRing (Left Edge) WED = Wide Edge Decoder, {OB = I/O Block (shaded arrows indicate XC4000X only) Segment with nearest buffer connects to segment with furthest buffer e e e e e e X8015 Figure 32: XC4000X Octal /O Routing July 30, 1997 (Version 1.2) 31XC4000E and XC4000X Series Field Programmable Gate Arrays UAD DOUBLE SINGLE DOUBLE LONG <PVDD>YF Br-QO OA DIRECT LONG <o & & -Y % % a % Q & Xe (-) Common to XC4000E and XC4000X XC4000X only Figure 33: Detail of Programmable interconnect Associated with XC4000 Series OB (Left Edge) 32 July 30, 1997 (Version 1.2)$< XILINX IOB inputs and outputs interface with the octal lines via the single-length interconnect lines. Single-length lines are also used for communication between the octals and dou- ble-length lines, quads, and longlines within the CLB array. Segmentation into buffered octals was found to be optimal for distributing signals over long distances around the device. Global Nets and Buffers Both the XC4000E and the XC4000X have dedicated glo- bal networks. These networks are designed to distribute clocks and other high fanout control signals throughout the devices with minimal skew. The global buffers are described in detail in the following sections. The text descriptions and diagrams are summarized in Table 15. The table shows which CLB and IOB clock pins can be sourced by which global buffers. In both XC4000E and XC4000X devices, placement of a library symbol called BUFG results in the software choos- ing the appropriate clock buffer, based on the timing requirements of the design. The detailed information in these sections is included only for reference. Global Nets and Buffers (XC4000E only) Four vertical longlines in each CLB column are driven exclusively by special global buffers. These longlines are in addition to the vertical longlines used for standard inter- connect. The four global lines can be driven by either of two types of global buffers. The clock pins of every CLB and IOB can also be sourced from local interconnect. Tabie 15: Clock Pin Access Two different types of clock buffers are available in the XC4000E: * Primary Global Buffers (BUFGP) * Secondary Global Buffers (BUFGS) Four Primary Global buffers offer the shortest delay and negligible skew. Four Secondary Global buffers have slightly longer delay and slightly more skew due to poten- tially heavier loading, but offer greater flexibility when used to drive non-clock CLB inputs. The Primary Global buffers must be driven by the semi- dedicated pads. The Secondary Global buffers can be sourced by either semi-dedicated pads or internal nets. Each CLB column has four dedicated vertical Global lines. Each of these lines can be accessed by one particular Pri- mary Global buffer, or by any of the Secondary Global buff- ers, as shown in Figure 34. Each corner of the device has one Primary buffer and one Secondary buffer. IOBs along the left and right edges have four vertical global longlines. Top and bottom !OBs can be clocked from the global lines in the adjacent CLB column. A global buffer should be specified for all timing-sensitive global signal distribution. To use a global buffer, place a BUFGP (primary buffer), BUFGS (secondary buffer), or BUFG (either primary or secondary buffer) element in a schematic or in HDL code. If desired, attach a LOC attribute or property to direct placement to the designated location. For example, attach a LOC=L attribute or property to a BUFGS symbol to direct that a buffer be placed in one of the two Secondary Global buffers on the left edge of the device, or a LOC=BL to indicate the Secondary Global buffer on the bottom edge of the device, on the left. XC4000X Local L&R | T&B inter- BUFGLS | surce | BUFGE | connect All CLBs in Quadrant V 1 1 7 5 7 All CLBs in Device V v IOBs on Adjacent Vertical V Half Edge IOBs on Adjacent Vertical Full Edge IOBs on Adjacent Horizontal Half Edge (Direct) IOBs on Adjacent Horizontal Half Edge (through CLB globals) IOBs on Adjacent Horizontal Full Edge (through CLB globals) L = Left, R = Right, T = Top, B = Bottom July 30, 1997 (Version 1.2)XC4000E and XC4000X Serles Field Programmable Gate Arrays A a =) a BUFGS il 3 BUFGP PGCKI CH> SGCK4 SGCKi PGaCKs 4 BUFGP BUFGS locals y locals Hoa fod] | 108) ( lop . | Any BUFGS: { Any BUFGS | . One BUFGP One BUFGP 108} E per Global Line p : ( per Global Line loB BUFGS BUFGP SGCK3 SGCK2 @ 2 PGCK3 BUFGP | | li lf BUFGS (OB (OB 10B 1OB eed Figure 34: XC4000E Global Net Distribution BUFGLS (oB 108 108 fl BUFGLS GCK1 GCKS a a Wl 4 GCK7 - GCK6 < BUFGE BUFGE BUFGLS BUFGE 2 | 2 lg lg BUFGE BUFGLS BB $|| 3% LJ |_ x BUFGLS 8, poste seed X88) BUFGLS xe SUFGLS 8, locals tocats BUFGLS locals 4 8 jocals CO a & oa [4 108 CLB CLOCKS CLB CLOCKS 108 ] 108 + cuocks (PER COLUMN) (PERCOLUMN) Gogg _ : locals locals : : 1 locals 0B tocals : = rT CLB CLOCKS CLB CLOCKS = ion [4 CLOCKS = (PER COLUMN) (PER COLUMN) Locks | B-] 108 N 8 8 locals 4 8 locals SUFGLS Be] jocats _| |__tocals _ 8, BUFGLS BUFGLS 6, 8, BUFGLS x4 OH x8 pos ae ; xe aa XB [ Gi8d ] | 2 2 a a s 8 a BUFGLS BUFGE 3 & 3 s BUFGE BUFGLS BUFGE BUFGE 4 < GCK2 GCK3 4 4 GCK4 = GCKS BUFGLS 1OB 108 {OB OB BUFGLS 9018 Figure 35: XC4000X Global Net Distribution July 30, 1997 (Version 1.2)$< XILINX Global Nets and Buffers (XC4000X only) Eight vertical longlines in each CLB column are driven by special global buffers. These longlines are in addition to the vertical longlines used for standard interconnect. The glo- bal lines are broken in the center of the array, to allow faster distribution and to minimize skew across the whole array. Each half-column global line has its own buffered multi- plexer, as shown in Figure 35. The top and bottom global lines cannot be connected across the center of the device, as this connection might introduce unacceptable skew. The top and bottom halves of the global lines must be sepa- rately driven although they can be driven by the same global buffer. The eight global lines in each CLB column can be driven by either of two types of global buffers. They can also be driven by internal logic, because they can be accessed by single, double, and quad lines at the top, bottom, half, and quarter points. Consequently, the number of different clocks that can be used simultaneously in an XC4000X device is very large. There are four global lines feeding the IOBs at the left edge of the device. IOBs along the right edge have eight global lines. There is a single global line along the top and bottom edges with access to the lOBs. All OB global lines are bro- ken at the center. They cannot be connected across the center of the device, as this connection might introduce unacceptable skew. OB global lines can be driven from two types of global buff- ers, or from local interconnect. Alternatively, top and bottom IOBs can be clocked from the global lines in the adjacent CLB column. Two different types of clock buffers are available in the XC4000Xx: * Global Low-Skew Buffers (BUFGLS) * Global Early Buffers (BUFGE) Global Low-Skew Buffers are the standard clock buffers. They should be used for most internal clocking, whenever a large portion of the device must be driven. Global Early Buffers are designed to provide a faster clock access, but CLB access is limited to one-fourth of the device. They also facilitate a faster I/O interface. Figure 35 is a conceptual diagram of the global net struc- ture in the XC4000X. Global Early buffers and Global Low-Skew buffers share a single pad. Therefore, the same IPAD symbol can drive one buffer of each type, in parallel. This configuration is particu- larly useful when using the Fast Capture latches, as described in IOB Input Signals on page 18. Paired Global Early and Global Low-Skew buffers share a common input; they cannot be driven by two different signals. Choosing an XC4000X Clock Buffer The clocking structure of the XC4000X provides a large variety of features. However, it can be simple to use, with- out understanding all the details. The software automati- cally handles clocks, along with all other routing, when the appropriate clock buffer is placed in the design. In fact, if a buffer symbol called BUFG is placed, rather than a specific type of buffer, the software even chooses the buffer most appropriate for the design. The detailed information in this section is provided for those users who want a finer level of control over their designs. If fine control is desired, use the following summary and Table 15 on page 33 to choose an appropriate clock buffer. * The simplest thing to do is to use a Global Low-Skew buffer. Ifa faster clock path is needed, try a BUFG. The software will first try to use a Global Low-Skew Buffer. If timing requirements are not met, a faster buffer will automatically be used. fa single quadrant of the chip is sufficient for the clocked logic, and the timing requires a faster clock than the Global Low-Skew buffer, use a Global Early buffer. Global Low-Skew Buffers Each corner of the XC4000X device has two Global Low- Skew buffers. Any of the eight Global Low-Skew buffers can drive any of the eight vertical Global lines in a column of CLBs. In addition, any of the buffers can drive any of the four vertical lines accessing the IOBs on the left edge of the device, and any of the eight vertical lines accessing the lOBs on the right edge of the device. (See Figure 36 on page 36.) IOBs at the top and bottom edges of the device are accessed through the vertical Global lines in the CLB array, as in the XC4000E. Any Global Low-Skew buffer can, therefore, access every IOB and CLB in the device. The Global Low-Skew buffers can be driven by either semi- dedicated pads or internal logic. To use a Global Low-Skew buffer, instantiate a BUFGLS element in a schematic or in HDL code. If desired, attach a LOC attribute or property to direct placement to the desig- nated location. For example, attach a LOC=T attribute or property to direct that a BUFGLS be placed in one of the two Global Low-Skew buffers on the top edge of the device, or a LOC=TR to indicate the Giobal Low-Skew buffer on the top edge of the device, on the right. July 30, 1997 (Version 1.2)XC4000E and XC4000X Series Fieid Programmable Gate Arrays a ae 2a > a < AS XB753 Figure 36: Any BUFGLS (GCK1 - GCK8) Can Drive Any or All Clock Inputs on the Device Global Early Buffers Each corner of the XC4000X device has two Global Early buffers. The primary purpose of the Giobal Early buffers is to provide an earlier clock access than the potentially heavily-loaded Global Low-Skew buffers. A clock source applied to both buffers will result in the Global Early clock edge occurring several nanoseconds earlier than the Glo- bal Low-Skew buffer clock edge, due to the lighter loading. Global Early buffers also facilitate the fast capture of device inputs, using the Fast Capture latches described in IOB Input Signals on page 18. For Fast Capture, take a single clock signal, and route it through both a Global Early buffer and a Global Low-Skew buffer. (The two buffers share an input pad.) Use the Global Early buffer to clock the Fast Capture latch, and the Global Low-Skew buffer to clock the normal input flip-flop or latch, as shown in Figure 17 on page 21. The Global Early buffers can also be used to provide a fast Clock-to-Out on device output pins. However, an early clock in the output flip-flop |OB must be taken into consideration when calculating the internal clock speed for the design. The Global Early buffers at the left and right edges of the chip have slightly different capabilities than the ones at the top and bottom. Refer to Figure 37, Figure 38, and Figure 35 on page 34 while reading the following explana- tion. Each Global Early buffer can access the eight vertical Glo- bal lines for all CL.Bs in the quadrant. Therefore, only one- fourth of the CLB clock pins can be accessed. This restric- tion is in large part responsible for the faster speed of the buffers, relative to the Global Low-Skew buffers. CLB CLB Vv CLB ! A Figure 37: Left and Right BUFGEs Can Drive Any or All Clock Inputs in Same Quadrant or Edge (GCK1 is shown. GCK2, GCKS and GCK6 are similar.) The left-side Global Early buffers can each drive two of the i four vertical lines accessing the |OBs on the entire left edge of the device. The right-side Global Early buffers can each drive two of the eight vertical lines accessing the IOBs on the entire right edge of the device. (See Figure 37.) Each left and right Global Early buffer can also drive half of the IOBs along either the top or bottom edge of the device, using a dedicated line that can only be accessed through the Global Early buffers. The top and bottom Global Early buffers can drive half of the 1OBs along either the left or right edge of the device, as shown in Figure 38. They can only access the top and bot- tom IOBs via the CLB global lines. 8 7 > [os < Vv CLB : A 1 CLB CLB PLeo= | ii < 2 P| 108 1 | 108 I< 3 4 Figure 38: Top and Bottom BUFGEs Can Drive Any or All Clock Inputs In Same Quadrant (GCK8 is shown. GCK3, GCK4 and GCK7 are similar.) 36 July 30, 1997 (Version 1.2)The top and bottom Global Early buffers are about 1 ns slower clock to out than the left and right Global Early buff- ers. The Global Early buffers can be driven by either semi-ded- icated pads or internal logic. They share pads with the Glo- bal Low-Skew buffers, so a single net can drive both global buffers, as described above. To use a Global Early buffer, place a BUFGE element in a schematic or in HDL code. If desired, attach a LOC attribute or property to direct placement to the designated location. For example, attach a LOC=T attribute or property to direct that a BUFGE be placed in one of the two Global Early buffers on the top edge of the device, ora LOC=TR to indicate the Global Early buffer on the top edge of the device, on the right. Power Distribution Power for the FPGA is distributed through a grid to achieve high noise immunity and isolation between logic and I/O. inside the FPGA, a dedicated Vcc and Ground ring sur- rounding the logic array provides power to the I/O drivers, as shown in Figure 39. An independent matrix of Vcc and Ground lines supplies the interior logic of the device. This power distribution grid provides a stabie supply and ground for all internal logic, providing the external package power pins are all connected and appropriately decoupled. Typically, a 0.1 uF capacitor connected between each Vcc pin and the boards Ground plane will provide adequate decoupling. Output buffers capable of driving/sinking the specified 12 mA loads under specified worst-case conditions may be capable of driving/sinking up to 10 times as much current under best case conditions. Noise can be reduced by minimizing external load capaci- tance and reducing simultaneous output transitions in the same direction. It may also be beneficial to locate heavily loaded output buffers near the Ground pads. The I/O Block output buffers have a slew-rate limited mode (default) which should be used where output rise and fall times are not speed-critical. $< XILINX Ground and Vee Ring for VO Drivers | Veo Co Logic Power Grid X5422 Figure 39: XC4000 Series Power Distribution Pin Descriptions There are three types of pins in the XC4000 Series devices: Permanently dedicated pins User I/O pins that can have special functions e Unrestricted user-programmabie |/O pins. Before and during configuration, all outputs not used for the configuration process are 3-stated with a 50 kQ - 100 kQ pull-up resistor. After configuration, if an [OB is unused it is configured as an input with a 50 kQ - 100 kQ pull-up resistor. XC4000 Series devices have no dedicated Reset input. Any user I/O can be configured to drive the Global Set/ Reset net, GSR. See Global Set/Reset on page 9 for more information on GSR. XC4000 Series devices have no Powerdown control input, as the XC3000 and XC2000 families do. The XC3000/ XC2000 Powerdown control also 3-stated all of the device /O pins. For XC4000 Series devices, use the global 3-state net, GTS, instead. This net 3-states ail outputs, but does not place the device in low-power mode. See IOB Output Signals on page 21 for more information on GTS. Device pins for XC4000 Series devices are described in Table 16. Pin functions during configuration for each of the seven configuration modes are summarized in Table 22 on page 64, in the Configuration Timing section. July 30, 1997 (Version 1.2) 37XC4000E and XC4000X Series Field Programmable Gate Arrays Table 16: Pin Descriptions Pin Name vo During Config. vo After Config. Pin Description Permanently Dedicated Pins vcc Eight or more (depending on package) connections to the nominal +5 V supply voltage (+3.3 V for low-voltage devices). All must be connected, and each must be decoupled with a 0.01 - 0.1 pF capacitor to Ground. GND Eight or more (depending on package type) connections to Ground. All must be con- nected. CCLK lorO During configuration, Configuration Clock (CCLK) is an output in Master modes or Asyn- chronous Peripheral mode, but is an input in Slave mode and Synchronous Peripheral mode. After configuration, CCLK has a weak pull-up resistor and can be selected as the Readback Clock. There is no CCLK High time restriction on XC4000 Series devices, ex- cept during Readback. See Violating the Maximum High and Low Time Specification for the Readback Clock on page 54 for an explanation of this exception. DONE vO DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it indicates the completion of the configuration process. As an input, a Low level on DONE can be configured to delay the global logic initialization and the enabling of outputs. The optional pull-up resistor is selected as an option in the XACT step program that cre- ates the configuration bitstream. The resistor is included by default. PROGRAM is an active Low input that forces the FPGA to clear its configuration mem- ory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA finishes the current clear cycle and executes another complete clear cycle, before it goes into a WAIT state and releases INIT. The PROGRAM pin has a permanent weak pull-up, so it need not be externally pulled up to Vcc. User I/O Pins That Can Have Special Functions RDY/BUSY Oo vO During Peripheral mode configuration, this pin indicates when it is appropriate to write another byte of data into the FPGA. The same status is also available on D7 in Asyn- chronous Peripheral mode, if a read operation is performed when the device is selected. After configuration, RDY/BUSY is a user-programmable 1/O pin. RDY/SUSY is pulled High with a high-impedance pull-up prior to INIT going High. RCLK vO During Master Parallel configuration, each change on the AO-A17 outputs (AO - A21 for XC4000X) is preceded by a rising edge on ROLK, a redundant output signal. RCLK is useful for clocked PROMS. It is rarely used during configuration. After configuration, RCLK is a user-programmable I/O pin. MO, M1, M2 | (MO), O (M1), 1 (M2) As Mode inputs, these pins are sampled after INIT goes High to determine the configu- ration made to be used. After configuration, MO and M2 can be used as inputs, and M1 can be used as a 3-state output. These three pins have no associated input or output registers. During configuration, these pins have weak pull-up resistors. For the most popular con- figuration mode, Slave Serial, the mode pins can thus be left unconnected. The three mode inputs can be individually configured with or without weak pull-up or pull-down re- sistors. A pull-down resistor value of 4.7 kQ is recommended. These pins can only be used as inputs or outputs when called out by special schematic definitions. To use these pins, place the library components MDO, MD1, and MD2 in- stead of the usual pad symbols. input or output buffers must still be used. TDO lf boundary scan is used, this pin is the Test Data Output. If boundary scan is not used, this pin is a 3-state output without a register, after configuration is completed. This pin can be user output only when called out by special schematic definitions. To use this pin, place the library component TDO instead of the usual pad symbol. An out- put buffer must still be used. duly 30, 1997 (Version 1.2)$< XILINX Table 16: Pin Descriptions (Continued) Pin Name vo During Config. vo Atter Config. Pin Description TDI, TCK, TMS vO orl (STAG) lf boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select inputs respectively. They come directly from the pads, bypassing the IOBs. These pins can aiso be used as inputs to the CLB logic after configuration is completed. if the BSCAN symbol is not placed in the design, all boundary scan functions are inhib- ited once configuration is completed, and these pins become user-programmable I/O. In this case, they must be called out by special schematic definitions. To use these pins, place the library components TDI, TCK, and TMS instead of the usual pad symbols. In- put or output buffers must still be used. HDC High During Configuration (HDC) is driven High until the I/O go active. It is available as a contro! output indicating that configuration is not yet completed. After configuration, HDC is a user-programmable I/O pin. tbc VO Low During Configuration (LDC) is driven Low until the I/O go active. Itis available as a control output indicating that configuration is not yet completed. After configuration, LDC is a user-programmable I/O pin. vO vo Before and during contiguration, INIT is a bidirectional signal. A 1 kQ - 10 kQ extemal pull-up resistor is recommended. As an active-Low open-drain output, INIT is held Low during the power stabilization and internal clearing of the configuration memory, As an active-Low input, it can be used to hold the FPGA in the internal WAIT state before the start of configuration. Master mode devices stay in a WAIT state an additional 30 to 300 us after INIT has gone High. During configuration, a Low on this output indicates that a configuration data error has occurred. After the I/O go active, INIT is a user-programmabie I/O pin. PGCKi1 - PGCK4 (XC4000E only) Weak Pull-up lor VO Four Primary Global inputs each drive a dedicated internal global net with short delay and minimal skew. if not used to drive a global buffer, any of these pins is a user-pro- grammable I/O. The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad symbol connected directly to the input of a BUFGP symbol is automatically placed on one of these pins. SGCK1 - SGCK4 (XC4000E only) Weak | Pull-up lor /O Four Secondary Global inputs each drive a dedicated internal global net with short delay and minimal skew. These internal global nets can also be driven from internal logic. If not used to drive a global net, any of these pins is a user-programmable I/O pin. The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global Buff- ers. Any input pad symbol connected directly to the input of a BUFGS symbol is auto- matically placed on one of these pins. GCK1 - GCK8 (XC4000X only) Weak Pull-up tor /O Eight inputs can each drive a Global Low-Skew buffer. In addition, each can drive a Glo- bal Early buffer. Each pair of global buffers can also be driven from intemal logic, but must share an input signal. If not used to drive a global buffer, any of these pins is a user-programmable I/O. Any input pad symbo! connected directly to the input of a BUFGLS or BUFGE symbol is automatically placed on one of these pins. 50, CSi, WS, RS VO These four inputs are used in Asynchronous Peripheral mode. The chip is selected when CSO is Low and CS1 is High. While the chip is selected, a Low on Write Strobe (WS) loads the data present on the DO - D7 inputs into the internal data buffer. A Low on Read Strobe (RS) changes D7 into a status output High if Ready, Low if Busy and drives DO - D6 High. In Express mode, CS1 is used as a serial-enable signal for daisy-chaining. WS and RS should be mutually exclusive, but if both are Low simultaneously, the Write Strobe overrides. After configuration, these are user-programmable I/O pins. AQ -A17 vO During Master Parallel configuration, these 18 output pins address the configuration EPROM. After configuration, they are user-programmable [/O pins. July 30, 1997 (Version 1.2) 39XC4000E and XC4000X Series Field Programmabie Gate Arrays Table 16: Pin Descriptions (Continued) vo vO During | After Pin Name _ | Config. | Config. Pin Description A18 - A21 During Master Parallel configuration with an XC4000X master, these 4 output pins add (XC4000X oO /O |4 more bits to address the configuration EPROM. After configuration, they are user-pro- only) grammable I/O pins. (See Master Paraile! Configuration section for additional details.) DO - D7 I vO During Master Parallel and Peripheral configuration, these eight input pins receive con- figuration data. After configuration, they are user-programmable I/O pins. During Slave Serial or Master Serial configuration, DIN is the serial configuration data DIN t /O __|input receiving data on the rising edge of CCLK. During Parallel configuration, DIN is the DO input. After configuration, DIN is a user-programmable I/O pin. During configuration in any mode but Exprass mode, DOUT is the serial configuration data output that can drive the DIN of daisy-chained slave FPGAs. DOUT data changes on the falling edge of CCLK, one-and-a-half CCLK periods after it was received at the DOUT oO VO |DIN input. In Express mode, DOUT is the status output that can drive the CS1 of daisy-chained FPGAs, to enable and disable downstream devices. After configuration, DOUT is a user-programmable I/O pin. Unrestricted User-Programmable V/O Pins Weak These pins can be configured to be input and/or output after configuration is completed. vO Pull-up VO _|Before configuration is completed, these pins have an internal high-value pull-up resis- tor (50 kQ - 100 kQ) that defines the logic level as High. Boundary Scan The bed of nails has been the traditional method of testing electronic assemblies. This approach has become less appropriate, due to closer pin spacing and more sophisti- cated assembly methods like surface-mount technology and multi-layer boards. The IEEE Boundary Scan Standard 1149.1 was developed to facilitate board-level testing of electronic assemblies. Design and test engineers can imbed a standard test logic structure in their device to achieve high fault coverage for I/O and internal logic. This structure is easily implemented with a four-pin interface on any boundary scan-compatible IC. IEEE 1149.1-compati- ble devices may be serial daisy-chained together, con- nected in parallel, or a combination of the two. The XC4000 Series implements IEEE 1149.1-compatible BYPASS, PRELOAD/SAMPLE and EXTEST boundary scan instructions. When the boundary scan configuration option is selected, three normal user I/O pins become ded- icated inputs for these functions. Another user output pin becomes the dedicated boundary scan output. The details of how to enable this circuitry are covered later in this sec- tion. By exercising these input signals, the user can serially load commands and data into these devices to control the driv- ing of their outputs and to examine their inputs. This method is an improvement over bed-of-nails testing. It avoids the need to over-drive device outputs, and it reduces the user interface to four pins. An optional fifth pin, a reset for the control logic, is described in the standard but is not implemented in Xilinx devices. The dedicated on-chip logic implementing the IEEE 1149.1 functions includes a 16-state machine, an instruction regis- ter and a number of data registers. The functional details can be found in the IEEE 1149.1 specification and are also discussed in the Xilinx application note XAPP 017: Bound- ary Scan in XC4000 Devices Figure 40 on page 41 shows a simplified block diagram of the XC4000E Input/Output Block with boundary scan implemented. XC4000X boundary scan logic is identical. Figure 41 on page 42 is a diagram of the XC4000 Series boundary sean logic. It includes three bits of Data Register per IOB, the IEEE 1149.1 Test Access Port controller, and the Instruction Register with decodes. XC4000 Series devices can also be configured through the boundary scan logic. See Readback on page 53. Data Registers The primary data register is the boundary scan register. For each IOB pin in the FPGA, bonded or not, it includes three bits for In, Out and 3-State Control. Non-IOB pins have appropriate partial bit population for In or Out only. PRO- GRAM, CCLK and DONE are not included in the boundary scan register. Each EXTEST CAPTURE-DR state captures all In, Out, and 3-state pins. The data register also includes the following non-pin bits: TDO.T, and TDO.O, which are always bits 0 and 1 of the data register, respectively, and BSCANT.UPD, which is 40 July 30, 1997 (Version 1.2)always the last bit of the data register. These three bound- ary scan bits are special-purpose Xilinx test signals. The other standard data register is the single flip-flop BYPASS register. It synchronizes data being passed through the FPGA to the next downstream boundary scan device. The FPGA provides two additional data registers that can be specified using the BSCAN macro. The FPGA provides 3-State TS Scan Input Clock IK. GLOBAL SA FLUP-FLOP/LATCH 3: XILINX two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are the decodes of two user instructions. For these instructions, two corresponding pins (BSCAN.TDO1 and BSCAN.TDO2) allow user scan data to be shifted out on TDO. The data register clock (BSCAN.DRCK) is available for control of test logic which the user may wish to imple- ment with CLBs. The NAND of TCK and RUN-TEST-IDLE is also provided (BSCAN.IDLE). XxS792, Figure 40: Block Diagram of XC4000E IOB with Boundary Scan (some details not shown). XC4000X Boundary Scan Logic is Identical. July 30, 1997 (Version 1.2) 4XCA000E and XC4000X Series Field Programmable Gate Arrays oa | o | p i a rao a a By q J bt LE fe fe foe ee a od 4In a Qi a | po] LE wes ' Lr = to pb a Go p p7 LE 1 10B.a o O REGISTER 108 7 INSTRUCTION REGISTER 1) Hee ol ey pe a r po] LE Loprtoe oat HTH HH KH KH Kee 1 ad a) a o + r po] LE 1 108 a DATAOUT UPDATE EXTEST SHE! CLOCK DATA CAPTURE REGISTER Figure 41: XC4000 Series Boundary Scan Logic Instruction Set The XC4000 Series boundary scan instruction set also includes instructions to configure the device and read back the configuration data. The instruction set is coded as shown in Table 17. Bit Sequence The bit sequence within each IOB is: in, Out, 3-State. The input-only MO and M2 mode pins contribute only the In bit to the boundary scan I/O data register, while the output- only M1 pin contributes all three bits. The first two bits in the VO data register are TDO.T and TDO.O, which can be used for the capture of internal sig- nals. The final bit is BSCANT.UPD, which can be used to drive an internal net. These locations are primarily used by Xilinx for internal testing. From a cavity-up view of the chip (as shown in XDE or Epic), starting in the upper right chip corner, the boundary scan data-register bits are ordered as shown in Figure 42. The device-specific pinout tables for the XC4000 Series include the boundary scan locations for each |OB pin. BSDL (Boundary Scan Description Language) files for XC4000 Series devices are available on the Xilinx FTP site. xaor8 including Boundary Scan in a Schematic If boundary scan is only to be used during configuration, no special schematic elements need be included in the sche- matic or HDL code. In this case, the special boundary scan pins TDI, TMS, TCK and TDO can be used for user func- tions after configuration. To indicate that boundary scan remain enabled after config- uration, place the BSCAN library symbol and connect the TDI, TMS, TCK and TDO pad symbols to the appropriate pins, as shown in Figure 43. Even if the boundary scan symbol is used in a schematic, the input pins TMS, TCK, and TDI can still be used as inputs to be routed to internal logic. Care must be taken not to force the chip into an undesired boundary scan state by inadvertently applying boundary scan input patterns to these pins. The simplest way to prevent this is to keep TMS High, and then apply whatever signal is desired to TDI and TCK. 42 July 30, 1997 (Version 1.2)$< XILINX Table 17: Boundary Scan instructions Instruction Test VO Data 2 11 10 | Setectead [TPO SourCE! souice 0 0 0 EXTEST DR DR 0 0 1 SAMPLE/ DR Pin/Logic PRELOAD 0 1 0 USER 1 BSCAN. | User Logic TDO1 0 1 1 USER 2 BSCAN. | User Logic THd2 1 0 0 | READBACK | Readback | Pin/Logic Data 1 0 1 |CONFIGURE], DOUT Disabled 1 1 0 Reserved ~ _ 1 1 1 BYPASS Bypass _ Register Bit 0 ( TOO end) TDO.T Bit TDO.O Br { Top-edge IOBs (Right to Left) { Left-edge 1OBs (Top to Bottom) MO1T MD1.0 MD1.1 M001 MD2.! { Bottom-edge 10Bs (Leto Fit { Right-edge 10Bs (Bottom to Top) (TDi end) B SCANT.UPD Figure 42: Boundary Scan Bit Sequence Avoiding Inadvertent Boundary Scan If TMS or TCK is used as user I/O, care must be taken to ensure that at least one of these pins is held constant dur- ing configuration. in some applications, a situation. may occur where TMS or TCK is driven during configuration. This may cause the device to go into boundary scan mode and disrupt the configuration process. To prevent activation of boundary scan during configura- tion, do either of the following: * TMS: Tie High to put the Test Access Port controller in a benign RESET state TCK: Tie High or Lowdon't toggle this clock input. For more information regarding boundary scan, refer to the Xilinx Application Note XAPP 017.001, Boundary Scan in XC4000E Devices. Optional To User Logic ISUF (a> Tol Too} _{Too> (Ms > ms DRCK b (tex >} tex WEI | ra User From { Toor SEL1 - Logic User Logic 4 Jipo2 sete X2675 Figure 43: Boundary Scan Schematic Example Configuration Configuration is the process of loading design-specific pro- gramming data into one or more FPGAs to define the func- tional operation of the internal blocks and_ their interconnections. This is somewhat like loading the com- mand registers of a programmabie peripheral chip. XC4000 Series devices use several hundred bits of configuration data per CLB and its associated interconnects. Each con- figuration bit defines the state of a static memory cell that controls either a function look-up table bit, a multiplexer input, or an interconnect pass transistor. The XACTstep development system translates the design into a netlist file. it automatically partitions, places and routes the logic and generates the configuration data in PROM format. Special Purpose Pins Three configuration mode pins (M2, M1, MQ) are sampled prior to configuration to determine the configuration mode. After configuration, these pins can be used as auxiliary connections. M2 and MO can be used as inputs, and M1 can be used as an output. The XACTstep development sys- tem does not use these resources unless they are explicitly specified in the design entry. This is done by placing a spe- cial pad symbol called MD2, MD1, or MDO instead of the input or output pad symbol. In XC4000 Series devices, the mode pins have weak puil- up resistors during configuration. With all three mode pins High, Slave Serial mode is selected, which is the most pop- ular configuration mode. Therefore, for the most common configuration mode, the mode pins can be left uncon- nected. (Note, however, that the internal pull-up resistor value can be as high as 100 kQ.) After configuration, these pins can individually have weak pull-up or pull-down resis- tors, as specified in the design. A pull-down resistor value of 4.7 kQ is recommended. These pins are located in the lower left chip corner and are near the readback nets. This location allows convenient routing if compatibility with the XC2000 and XC3000 family conventions of MO/RT, M1/RD is desired. July 30, 1997 (Version 1.2)XC4000E and XC4000X Series Field Programmable Gate Arrays Configuration Modes XC4000E devices have six configuration modes. XC4000X devices have the same six modes, plus an additional con- figuration mode. These modes are selected by a 3-bit input code applied to the M2, M1, and MO inputs. There are three self-loading Master modes, two Peripheral modes, and a Serial Slave mode, which is used primarily for daisy- chained devices. The coding for mode selection is shown in Table 18. . Table 18: Configuration Modes Mode M2 | M1 | MO) CCLK Data Master Serial 0 | 0 | O | output Bit-Serial Slave Serial 1 1 1 input Bit-Serial Master 1 0 | O | output | Byte-Wide, Parallel Up increment from 00000 Master 1 1 0 | output | Byte-Wide, Parallel Down decrement from 3FFFF Peripheral 0 1 1 input Byte-Wide Synchronous Peripheral 1 0 1 | output | Byte-Wide Asynchronous Reserved 0 1 0 _ _ Reserved 0 0 1 _~ Note: * Peripheral Synchronous can be considered byte- wide Slave Paraliel A detailed description of each configuration mode, with tim- ing information, is included later in this data sheet. During configuration, some of the 1/O pins are used temporarily for the configuration process. All pins used during configura- tion are shown in Table 22 on page 64. Master Modes The three Master modes use an internat oscillator to gener- ate a Configuration Clock (CCLK) for driving potential slave devices. They also generate address and timing for exter- nal PROM(s) containing the configuration data. Master Parallel (Up or Down) modes generate the CCLK signal and PROM addresses and receive byte parallel data. The data is internally serialized into the FPGA data-frame format. The up and down selection generates starting addresses at either zero or 3FFFF (3FFFFF when 22 address lines are used), for compatibility with different microprocessor addressing conventions. The Master Serial mode generates CCLK and receives the configuration data in serial form from a Xilinx serial-configuration PROM. CCLK speed is selectable as either 1 MHz (default) or 8 MHz. Configuration always starts at the default siow fre- quency, then can switch to the higher frequency during the first frame. Frequency tolerance is -50% to +25%. Additional Address lines in XC4000 devices The XC4000X devices have additional address lines (A18- A21) allowing the additional address space required to daisy-chain several large devices. The extra address lines are programmable in XC4000EX devices. By default these address lines are not activated. In the default mode, the devices are compatible with existing XC4000 and XC4000E products. If desired, the extra address lines can be used by specifying the address lines option in bitgen as 22 (bitgen -g AddressLines:22). The lines (A18-A21) are driven when a master device detects, via the bitstream, that it should be using all 22 address lines. Because these pins will initially be pulled high by internal pull-ups, designers using Master Parallel Up mode should use external pull down resistors on pins A18-A21. If Master Parallel Down mode is used external resistors are not necessary. All 22 address lines are always active in Master Parallel modes with XC4000XL devices. The additional address lines behave identically to the lower order address lines. If the Address Lines option in bitgen is set to 18, it will be ignored by the XC4000XL device. The additional address lines (A18-A21) are not available in the PC84 package. Peripheral Modes The two Peripheral modes accept byte-wide data from a bus. A RDY/BUSY status is available as a handshake sig- nal. in Asynchronous Peripheral mode, the internal oscilia- tor generates a CCLK burst signal that serializes the byte- wide data. CCLK can also drive slave devices. In the syn- chronous mode, an externally supplied clock input to CCLK serializes the data. Slave Serial Mode In Slave Serial mode, the FPGA receives serial configura- tion data on the rising edge of CCLK and, after loading its configuration, passes additional data out, resynchronized on the next falling edge of CCLK. Multiple slave devices with identical configurations can be wired with parallel DIN inputs. In this way, multiple devices can be configured simultaneously. Serial Daisy Chain Multiple devices with different configurations can be con- nected together in a daisy chain, and a single combined bitstream used to configure the chain of slave devices. To configure a daisy chain of devices, wire the CCLK pins of all devices in parallel, as shown in Figure 51 on page 56. Connect the DOUT of each device to the DIN of the next. The lead or master FPGA and following slaves each passes resynchronized configuration data coming from a single source. The header data, including the length count, duly 30, 1997 (Version 1.2)$< XILINX is passed through and is captured by each FPGA when it recognizes the 0010 preamble. Following the length-count data, each FPGA outputs a High on DOUT until it has received its required number of data frames. After an FPGA has received its configuration data, it passes on any additional frame start bits and configuration data on DOUT. When the total number of configuration clocks applied after memory initialization equals the value of the 24-bit length count, the FPGAs begin the start-up sequence and become operational together. FPGA V/O are normally released two CCLK cycles after the last configura- tion bit is received. Figure 47 on page 51 shows the start- up timing for an XC-4000 Series device. The daisy-chained bitstream is not simply a concatenation of the individual bitstreams. The PROM file formatter must be used to combine the bitstreams for a daisy-chained con- figuration. Multi-Family Daisy Chain All Xilinx FPGAs of the XC2000, XC3000, and XC4000 Series use a compatible bitstream format and can, there- fore, be connected in a daisy chain in an arbitrary sequence. There is, however, one limitation. The lead device must belong to the highest family in the chain. If the chain contains XC4000 Series devices, the master nor- mally cannot be an XC2000 or XC3000 device. The reason for this rule is shown in Figure 47 on page 51. Since all devices in the chain store the same length count value and generate or receive one common sequence of CCLK pulses, they all recognize length-count match on the same CCLK edge, as indicated on the left edge of Figure 47. The master device then generates additional CCLK pulses until it reaches its finish point F. The different families generate or require different numbers of additiorial CCLK pulses until they reach F. Not reaching F means that the device does not really finish its configuration, although DONE may have gone High, the outputs became active, and the internal reset was released. For the XC4000 Series device, not reaching F means that readback cannot be ini- tiated and most boundary scan instructions cannot be used. The user has some control over the relative timing of these events and can, therefore, make sure that they occur at the proper time and the finish point F is reached. Timing is con- trolled using options in the bitstream generation software. XC3000 Master with an XC4000 Series Slave Some designers want to use an inexpensive lead device in peripheral mode and nave the more precious I/O pins of the XC4000 Series devices all available for user /O. Figure 44 provides a solution for that case. This solution requires one CLB, one !OB and pin, and an internal oscillator with a frequency of up to 5 MHz as a clock source. The XC3000 master device must be config- ured with late Internal Reset, which is the default option. One CLB and one IOB in the lead XC3000-family device are used to generate the additional CCLK pulse required by the XC4000 Series devices. When the lead device removes the internal RESET signal, the 2-bit shift register responds to its clock input and generates an active Low output signal for the duration of the subsequent clock period. An external connection between this output and CCLK thus creates the extra CCLK pulse. > oeT Output Connect Reset to CCLK o 0 1 0 Activa Low Output Active High Output o 1 ate, : x5223 Figure 44: CCLK Generation for XC3000 Master Driving an XC4000 Series Slave July 30, 1997 (Version 1.2) 45XC4000E and XC4000X Series Field Programmable Gate Arrays Setting CCLK Frequency For Master modes, CCLK can be generated in either of two frequencies. In the default slow mode, the frequency ranges from 0.5 MHz to 1.25 MHz for XC4000E and XC4000EX devices and from 0.6 MHz to 1.8 MHz for XC4000XL devices. In fast CCLK mode, the frequency ranges from 4 MHz to 10 MHz for XC4000EX devices and from 5 MHz to 15 MHz for XC4000XL devices. The fre- quency is selected by an option when running the bitstream generation software. If an XC4000 Series Master is driving an XC3000- or XC2000-family slave, slow CCLK mode must be used. In addition, an XC4000XL device driving a XC4000E or XC4000EX should use slow mode. Slow mode is the default. Table 19: XC4000 Series Data Stream Formats All Other Data Type Modes (DO...) Fill Byte 11111111b Preamble Code 0010b Length Count COUNT(23:0) Fill Bits 1111b Start Field Ob Data Frame DATA{n-1:0) CRC. or Constant xox (CRC) Field Check or 0110b Extend Write Cycle _ Start-Up Bytes xh LEGEND: Unshaded Once per bitstream Light Once per. data frame One Data Stream Format The data stream (bitstream) format is identical for all con- figuration modes. The data stream formats are shown in Table 19. Bit-serial data is read from left to right, and byte-paralle! data is effec- tively assembled from this serial bitstream, with the first bit in each byte assigned to DO. The configuration data stream begins with a string of eight ones, a preamble code, followed by a 24-bit length count and a separator field of ones. This header is followed by the actual configuration data in frames. The length and number of frames depends on the device type (see Table 20 and Table 21). Each frame begins with a start field and ends with an error check. A postamble code is required to signal the end of data for a single device. In ail cases, additional start-up bytes of data are required to provide four clocks for the startup sequence at the end of configuration. Long daisy chains require additional startup bytes to shift the last data through the chain. All startup bytes are dont-cares; these bytes are not included in bitstreams created by the Xilinx software. A selection of CRC or non-CRC error checking is allowed by the bitstream generation software. The non-CRC error checking tests for a designated end-of-frame field for each frame. For CRC error checking, the software calculates a running CRC and inserts a unique four-bit partial check at the end of each frame. The 11-bit CRC check of the last frame of an FPGA includes the last seven data bits. Detection of an error results in the suspension of data load- ing and the pulling down of the INIT pin. In Master modes, CCLK and address signals continue to operate externally. The user must detect INIT and initialize a new configuration by pulsing the PROGRAM pin Low or cycling Vcc. 46 July 30, 1997 (Version 1.2)Seibert ies. Mase aN rs tebeht natin ed step be SL PPD $2 XILINX Table 20: XC4000E Program Data Device XC4003E | XC400SE | XC4006E | XCSO08E | XCA010E | XC4013E | XC4020E | XC4025E Max Logic Gates 3,000 5,000 6,000 8,000 10,000 13,000 20,000 25,000 CLBs 100 196 256 324 400 576 784 1,024 (Row x Col.) (10x10) | (14x14) | (16x16) | (18x18) | (20x20) | (24x24) | (28x28) | (32x 32) 1OBs 80 112 128 144 160 192 224 256 Flip-Flops 360 616 768 936 1,120 1,536 2,016 2,560 Horizontal 20 28 32 36 40 48 56 64 Longlines TBUFs per 12 16 18 20 22 26 30 34 Longline Bits per Frame 126 166 186 206 226 266 306 346 Frames 428 572 644 716 788 932 1,076 1,220 Program Data 53,936 94,960 119,792 147,504 | 178,096 | 247,920 | 329,264 | 422,128 PROM Size 53,984 95,008 119,840 | 147,552 | 178,144 | 247,968 | 329,312 | 422,176 (bits) Notes: 1. Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1+ 1 start bit + 4 error check bits Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1 Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits PROM Size = Program Data + 40 (header) + 8 2. The user can add more one bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra one bits, even for extra leading ones at the beginning of the header. Table 21: XC4000EX/XL Program Data Device XC4005 | XC4010 | XC4013 | XC4020 | XC4028 | XC4036 | XC4044 | XC4052 | XC4062 | XC4085 Max Logic Gates | 5,000 | 10,000 | 13,000 | 20,000 | 28,000 | 36,000 | 44,000 | 52,000 | 62,000 | 85,000 CLBs 196 400 576 784 1,024 | 1,296 1,600 1,936 2,304 3,136 (Row x Column) | 14x 14 | 20x 20 | 24x 24 | 28 x 28 | 32x 32 | 36x36) 40x40 | 44x44 | 48x48 | 56x56 lOBs 112 160 192 224 256 288 320 352 384 448 Flip-Flops 616 1,120 | 1,536 | 2,016 | 2,560 | 3,168 3,840 4,576 5,376 7,168 Bits per Frame 205 277 325 373 421 469 517 565 613 709 Frames 741 1,023 | 1,217 | 1,399 | 1,587 | 1,775 1,963 2,151 2,339 2,715 Program Data 151,910 | 283,376 | 393,580 | 521,832 | 668,132 | 832,480 | 1,014,876) 1,215,320 1,433,812) 1,924,940 PROM Size (bits) | 151,960 | 283,424 | 393,632 | 521,880 | 668,184 | 832,528 | 1,014,928) 1,215,368] 1,433,864! 1,924,992 Notes: 1. Bits per frame = (12 x number of rows) + 8 for the top + 16 for the bottom + 8 + 1 start bit + 4 error check bits. Frames = (47 x number of columns) + 27 for the left edge + 52 for the right edge + 4. Program data = (bits per frame x number of frames) + 5 postambie bits. PROM size = (program data + 40 header bits + 8 start bits) rounded up to the nearest byte. 2. The user can add more one bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of any frame, following the four error check bits. However, the Length Count vaiue must be adjusted for all such extra one bits, even for extra leading ones at the beginning of the header.t Cyclic Redundancy Check (CRC) for performs an identical calculation on the bitstream and com- Configuration and Readback pares the result with the received checksum. Each data frame of the configuration bitstrearn has four error bits at the end, as shown in Table 19. if a frame data error is detected during the loading of the FPGA, the con- figuration process with a potentially corrupted bitstream is terminated. The FPGA pulls the INIT pin Low and goes into a Wait state. The Cyclic Redundancy Check is a method of error detec- tion in data transmission applications. Generally, the trans- mitting system performs a calculation on the serial bitstream. The result of this calculation is tagged onto the data stream as additional check bits. The receiving system July 30, 1997 (Version 1.2) 47XC4000E and XC4000X Series Field Programmable Gate Arrays During Readback, 11 bits of the 16-bit checksum are added to the end of the Readback data stream. The checksum is computed using the CRC-16 CCITT polynomial, as shown in Figure 45. The checksum consists of the 11 most signifi- cant bits of the 16-bit code. A change in the checksum indi- cates a change in the Readback bitstream. A comparison to a previous checksum is meaningful only if the readback data is independent of the current device state. CLB out- puts should not be included (Read Capture option not used), and if RAM is present, the RAM content must be unchanged. Statistically, one error out of 2048 might go undetected. Configuration Sequence There are four major steps in the XC4000 Series power-up configuration sequence. * Configuration Memory Clear Initialization * Configuration Start-Up The full process is illustrated in Figure 46. Configuration Memory Clear When power is first applied or is reapplied to an FPGA, an internal circuit forces initialization of the configuration logic. When Vcc reaches an operational level, and the circuit passes the write and read test of a sample pair of configu- tation bits, a time delay is started. This time delay is nomi- nally 16 ms, and up to 10% longer in the low-voltage devices. The delay is four times as long when in Master Modes (MO Low), to allow ample time for all slaves to reach a stable Vcc. When all INIT pins are tied together, as rec- ommended, the longest delay takes precedence. There- fore, devices with different time delays can easily be mixed and matched in a daisy chain. This delay is applied only on power-up. It is not applied when reconfiguring an FPGA by pulsing the PROGRAM pin x2 X15 xt Gith}_}) )-2EEEEP EPR SERIAL DATA IN oo tit LAST DATA FRAME >| as]i4}isfia]iifiol 9 fay 7] ets) }- CRC ~ CHECKSUM > 0 5 E & Readback Data Stream xe Figure 45: Circuit for Generating CRC-16 =H LOC Output = L, HDC Output SAMPLE/PRELOAD BYPASS VO Active EXTEST SAMPLE PRELOAD BYPASS USER 1 If Boundary Scan USER 2 fs Selected CONFIGURE READBACK xeare Figure 46: Power-up Configuration Sequence July 30, 1997 (Version 1.2)Low. During this time delay, or as long as the PROGRAM input is asserted, the configuration logic is held in a Config- uration Memory Clear state. The configuration-memory frames are consecutively initialized, using the internal oscil- lator. At the end of each complete pass through the frame addressing, the power-on time-out delay circuitry and the level of the PROGRAM pin are tested. If neither is asserted, the logic initiates one additional clearing of the configura- tion frames and then tests the INIT input. Initialization During initialization and configuration, user pins HDC, LDC, INIT and DONE provide status outputs for the system inter- face. The outputs CDC, INIT and DONE are held Low and HDC is held High starting at the initial application of power. The open drain INIT pin is released after the final initializa- tion pass through the frame addresses. There is a deliber- ate delay of 50 to 250 us (up to 10% longer for low-voltage devices) before a Master-mode device recognizes an inac- tive INIT. Two internal clocks after the INIT pin is recognized as High, the FPGA samples the three mode lines to deter- mine the configuration mode. The appropriate interface lines become active and the configuration preamble and data can be loaded.Configuration The 0010 preamble code indicates that the following 24 bits represent the length count. The length count is the total number of configuration clocks needed to load the com- plete configuration data. (Four additional configuration clocks are required to complete the configuration process, as discussed. below.) After the preamble and the length count have been passed through to ail devices in the daisy chain, DOUT is held High to prevent frame start bits from reaching any daisy-chained devices. A specific configuration bit, early in the first frame of a mas- ter device, controls the configuration-clock rate and can increase it by a factor of eight. Therefore, if a fast configu- ration clock is selected by the bitstream, the slower clock rate is used until this configuration bit is detected. Each frame has a start field followed by the frame-configu- ration data bits and a frame error field. If a frame data error is detected, the FPGA halts loading, and signals the error by pulling the open-drain INIT pin Low. After all configura- tion frames have been loaded into an FPGA, DOUT again follows the input data so that the remaining data is passed on to the next device. Delaying Configuration After Power-Up There are two methods of delaying configuration after power-up: put a logic Low on the PROGRAM input, or pull the bidirectional INIT pin Low, using an open-collector (open-drain) driver. (See Figure 46 on page 48.) A Low on the PROGRAM input is the more radical approach, and is recommended when the power-supply $< XILINX rise time is excessive or poorly defined. As jong as PRO- GRAM Is Low, the FPGA keeps clearing its configuration memory. When goes High, the configuration memory is cleared one more time, followed by the begin- ning of configuration, provided the INIT input is not exter- nally held Low. Note that a Low on the PROGRAM input automatically forces a Low on the INIT output. The XC4000 Series PROGRAM pin has a permanent weak pull-up. Using an open-collector or open-drain driver to hold INIT Low before the beginning of configuration causes the FPGA to wait after completing the configuration memory clear operation. When INIT is no longer held Low exter- nally, the device determines its configuration mode by cap- turing its mode pins, and is ready to start the configuration process. A master device waits up to an additional 250 us to make sure that any slaves in the optional daisy chain have seen that INIT is High. Start-Up Start-up is the transition from the configuration process to the intended user operation. This transition involves a change from one clock source to another, and a change from interfacing parallel or serial configuration data where most outputs are 3-stated, to normal operation with I/O pins active in the user-system. Start-up must make sure that the user-logic wakes up gracefully, that the outputs become active without causing contention with the configuration sig- nals, and that the internal flip-flops are released from the global Reset or Set at the right time. Figure 47 describes start-up timing for the three Xilinx fam- ilies in detail. The configuration modes can use any of the four timing sequences. To access the internal start-up signals, place the STARTUP library symbol. Start-up Timing Different FPGA families have different start-up sequences. The XC2000 family goes through a fixed sequence. DONE goes High and the internal global Reset is de-activated one CCLK period after the /O become active. The XC3000A family offers some flexibility. DONE can be programmed to go High one CCLK period betore or after the I/O become active. independent of DONE, the internal global Reset is de-activated one CCLK period before or after the I/O become active. The XC4000 Series offers additional flexibility. The three events DONE going High, the internal Set/Reset being de-activated, and the user I/O going active can all occur in any arbitrary sequence. Each of them can occur one CCLK period before or after, or simultaneous with, any of the others. This relative timing is selected by means of soft- ware options in the bitstream generation software. July 30, 1997 (Version 1.2) 49XC4000E and XC4000X Series Field Programmable Gate Arrays The default option, and the most practical one, is for DONE to go High first, disconnecting the configuration data source and avoiding any contention when the {/Os become active one clock later. Reset/Set is then released another clock period later to make sure that user-operation starts from stable internal conditions. This is the mast common sequence, shown with heavy lines in Figure 47, but the designer can modify it to meet particular requirements. Normally, the start-up sequence is controlled by the internal device oscillator output (CCLK), which is asynchronous to the system clock. XC4000 Series offers another start-up clocking option, UCLK_NOSYNC. The three events described above need not be triggered by CCLK. They can, as a configuration option, be triggered by a user clock. This means that the device can wake up in synchronism with the user system. When the UCLK_SYNC option is enabled, the user can externally hold the open-drain DONE output Low, and thus Stall all further progress in the start-up sequence until DONE is released and has gone High. This option can be used to force synchronization of several FPGAs to a com- mon user clock, or to guarantee that all devices are suc- cessfully configured before any I/Os go active. If either of these two options is selected, and no user clock is specified in the design or attached to the device, the chip could reach a point where the configuration of the device is complete and the Done pin is asserted, but the outputs do not become active. The solution is either to recreate the bit- stream specifying the start-up clock as CCLK, or to supply the appropriate user clock. Start-up Sequence The Start-up sequence begins when the configuration memory is full, and the total number of configuration clocks received since INIT went High equals the loaded value of the tength count. The next rising clock edge sets a flip-flop QO, shown in Figure 48. Q0 is the leading bit of a 5-bit shift register. The outputs of this register can be programmed to control three events. * The release of the open-drain DONE output * The change of configuration-related pins to the user function, activating all |OBs. The termination of the global Set/Reset initialization of all CLB and !OB storage elements. The DONE pin can also be wire-ANDed with DONE pins of other FPGAs or with other external signals, and can then be used as input to bit Q3 of the start-up register. This is called Start-up Timing Synchronous to Done in and is selected by either CCLK_SYNC or UCLK_SYNC. When DONE is not used as an input, the operation is called Start-up Timing Not Synchronous to DONE In, and is selected by either CCLK_NOSYNC or UCLK_NOSYNC. As a configuration option, the start-up control register beyond QO can be clocked either by subsequent CCLK pulses or from an on-chip user net called STARTUP.CLK. These signals can be accessed by placing the STARTUP library symbol. Start-up from CCLK lf CCLK is used to drive the start-up, QO through Q3 pro- vide the timing. Heavy lines in Figure 47 show the default timing, which is compatible with XC2000 and XC3000 devices using early DONE and late Reset. The thin lines indicate all other possible timing options. 50 July 30, 1997 (Version 1.2)XC2000 XxC3000 XC4000E/K ! CCLK_NOSYNC XC4000E/X CCLK_SYNC XC4OQ00E/X UCLK_SYNC Di Dist Dis2 i Synchronization ty. $< XILINX g bength Count Match ft COL Patiod F = Finished, no more tion clocks needed Daisy-chain lead device must have latest F Heavy lines describe default timing Uncertainty j<_| UCLK Period xa024 Figure 47: Start-up Timing July 30, 1997 (Version 1.2) $1XC4000E and XC4000X Series Fieid Programmable Gate Arrays Start-up from a User Clock (STARTUP.CLK) When, instead of CCLK, a user-supplied start-up clock is selected, Q1 is used to bridge the unknown phase relation- ship between CCLK and the user clock. This arbitration causes an unavoidable one-cycle uncertainty in the timing of the rest of the start-up sequence. DONE Goes High to Signal End of Configuration XC4000 Series devices read the expected length count from the bitstream and store it in an internal register. The length count varies according to the number of devices and the composition of the daisy chain. Each device also counts the number of CCLKs during configuration. Two conditions have to be met in order for the DONE pin to go high: the chip's internal memory must be full, and * the configuration length count must be met, exactly. This is important because the counter that determines when the length count is met begins with the very first CCLK, not the first one after the preamble. Therefore, if a stray bit is inserted before the preamble, or the data source is not ready at the time of the first CCLK, the internal counter that holds the number of CCLKs will be one ahead of the actual number of data bits read. At the end of configuration, the configuration memory will be full, but the number of bits in the internal counter will not match the expected length count. As a consequence, a Master mode device will continue to send out CCLKs until the internal counter turns over to zero, and then reaches the correct length count a second time. This will take several seconds [2 CCLK period] which is sometimes interpreted as the device not configur- ing at all. If it is not possible to have the data ready at the time of the first CCLK, the problem can be avoided by increasing the number in the length count by the appropriate value. The XACT User Guide includes detailed information about man- ually altering the length count. The DONE pin for each device goes High when the device has received its quota of configuration data. Wiring the DONE pins of several devices together delays start-up of all devices until all are fully configured. Note that DONE is an open-drain output and does not go High unless an internal pull-up is activated or an external pull-up is attached. The internal pull-up is activated as the default by the bitstream generation software. Release of User /O After DONE Goes High By default, the user I/O are released one CCLK cycle after the DONE pin goes High. if CCLK is not clocked after DONE goes High, the outputs remain in their initial state 3-stated, with a 50 kQ - 100 kQ pull-up. The delay from DONE High to active user I/O is controlled by an option to the bitstream generation software. Release of Global Set/Reset After DONE Goes High By default, Global Set/Reset (GSR) is released two CCLK cycles after the DONE pin goes High. If CCLK is not clocked twice after DONE goes High, all flip-flops are held in their initial set or reset state. The delay from DONE High to GSR inactive is controlled by an option to the bitstream generation software. Configuration Complete After DONE Goes High Three full CCLK cycles are required after the DONE pin goes High, as shown in Figure 47 on page 51. if CCLK is not clocked three times after DONE goes High, readback cannot be initiated and most boundary scan instructions cannot be used. Configuration Through the Boundary Scan Pins XC4000 Series devices can be configured through the boundary scan pins. The basic procedure is as follows: * Power up the FPGA with INIT held Low (or drive the PROGRAM pin Low for more than 300 ns followed by a High while holding INIT Low). Holding INIT Low allows enough time to issue the CONFIG command to the FPGA. The pin can be used as 1/O after configuration if a resistor is used to hold INIT Low. * Issue the CONFIG command to the TMS input * Wait for INIT to go High * Sequence the boundary scan Test Access Port to the SHIFT-DR state : Toggle TCK to clock data into TDI pin. The user must account for all TCK clock cycles after INIT goes High, as all of these cycles affect the Length Count compare. For more detailed information, refer to the Xilinx application note XAPP017, Boundary Scan in XC4000 Devices This application note also applies to XC4000E and XC4000X devices. 52 July 30, 1997 (Version 1.2)$< XILINX as ates STARTUP DONE iN * (OBs OPERATIONAL PER CONFIGURATION * GLOBAL SET/RESET OF ALL CLB AND 1OB FLIP-FLOP STARTUP,GSR CONTROLLED BY STARTUP SYMBOL IN THE USER SCHEMATIC (SEE STARTUP.GTS LIBRARIES GUIDE) QTS INVERT ats > LOA 1 GLOBAL 3-STATE OF ALL 108s as a * [> ? DONE FINISHED * Lif! | ENABLES BOUNDARY o , READBACK AND lf CONTROLS THE OSCHLATOR ao at a2 a3 ae 1 LENGTH COUNT =I) Ss @ dba oq 0 D oa dp at >K pom > K >K * pail >, aK CLEAR MEMORY I 4 L 4 * CCLK mel io STARTUP.CLK 1 USER NET a * Figure 48: Start-up Logic Readback The user can read back the content of configuration mem- ory and the level of certain internal nodes without interfer- ing with the normal operation of the device. Readback not only reports the downloaded configuration bits, but can also include the present state of the device, represented by the content of all flip-flops and latches in CLBs and !OBs, as well as the content of function genera- tors used as RAMs. Note that in XC4000 Series devices, configuration data is not inverted with respect to configuration as it is in XC2000 and XC3000 families. XC4000 Series Readback does not use any dedicated pins, but uses four internal nets (RDBK. TRIG, RDBK.DATA, RDBK.RIP and RDBK.CLK) that can be routed to any IOB. To access the internal Readback signals, place the READ- % CONFIGURATION BIT OPTIONS SELECTED SY USER iN "MAKEBITS" BACK library symbol and attach the appropriate pad sym- bois, as shown in Figure 49. After Readback has been initiated by a Low-to-High transi- tion on RDBK.TRIG, the RDBK.RIP (Read In Progress) output goes High on the next rising edge of RDBK.CLK. Subsequent rising edges of this clock shift out Readback data on the RDBK.DATA net. Readback data does not include the preamble, but starts with five dummy bits (all High) followed by the Start bit (Low) of the first frame. The first two data bits of the first frame are always High. Each frame ends with four error check bits. They are read back as High. The last seven bits of the last frame are also read back as High. An additional Start bit (Low) and an 11-bit Cyclic Redundancy Check (CRC) signature follow, before RDBK.RIP returns Low. July 30, 1997 (Version 1.2)XC4000E and XC4000X Series Field Programmabie Gate Arrays IF UNCONNECTED, DEFAULT !S CCLK Cux| [Mdd> READ_TRIGGER > TRIG DATA > READ_DATA [MOi> READBACK OBUF RiP IBUF Figure 49: Readback Schematic Example Readback Options Readback options are: Read Capture, Read Abort, and Ciock Select. They are set with the bitstream generation software. Read Capture When the Read Capture option is selected, the readback data stream includes sampled values of CLB and IOB sig- nals. The rising edge of RDBK.TRIG latches the inverted values of the four CLB outputs, the [OB output flip-flops and the input signals I1 and 12. Note that while the bits describ- ing configuration (interconnect, function generators, and RAM content) are notinverted, the CLB and IOB output sig- nals are inverted. When the Read Capture option is not selected, the values of the capture bits reflect the configuration data originally written to those memory locations. If the RAM capability of the CLBs is used, RAM data are available in readback, since they directly overwrite the F and G function-table configuration of the CLB. RDBK.TRIG is located in the lower-left corner of the device, as shown in Figure 50. Read Abort When the Read Abort option is selected, a High-to-Low transition on RDBK.TRIG terminates the readback opera- tion and prepares the logic to accept another trigger. After an aborted readback, additional clocks (up to one readback clock per configuration frame) may be required to re-initialize the control logic. The status of readback is indi- cated by the output contro! net ROBK.RIP) ADBK.RIP is High whenever a readback is in progress. Clock Select CCLK is the default clock. However, the user can insert another clock on RDBK.CLK. Readback control and data are clocked on rising edges of RDBK.CLK. ff readback must be inhibited for security reasons, the readback control nets are simply not connected. RDBK.CLK is located in the lower right chip corner, as shown in Figure 50. x1786 PROGRAMMABLE /- INTERCONNECT x1787 Figure 50: READBACK Symbol in Graphical Editor Violating the Maximum High and Low Time Specification for the Readback Clock The readback clock has a maximum High and Low time specification. In some cases, this specification cannot be met. For example, if a processor is controlling readback, an interrupt may force it to stop in the middle of a readback. This necessitates stopping the clock, and thus violating the specification. The specification is mandatory only on clocking data at the end of a frame prior to the next start bit. The transfer mech- anism will load the data to a shift register during the last six clock cycles of the frame, prior to the start bit of the follow- ing frame. This loading process is dynamic, and is the source of the maximum High and Low time requirements. Therefore, the specification only applies to the six clock cycles prior to and including any start bit, including the clocks before the first start bit in the readback data stream. At other times, the frame data is already in the register and the register is not dynamic. Thus, it can be shifted out just like a regular shift register. The user must precisely calculate the location of the read- back data relative to the frame. The system must keep track of the position within a data frame, and disable inter- rupts before frame boundaries. Frame lengths and data formats are listed in Table 19, Table 20 and Table 21. Readback with the XChecker Cable The XChecker Universal Download/Readback Cable and Logic Probe uses the readback feature for bitstream verifi- cation. It can also display selected internal signals on the PC or workstation screen, functioning as a low-cost in-cir- cuit emulator. 54 July 30, 1997 (Version 1.2)22 XILINX XC4000E/EX/XL Program Readback Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. The following guidelines reflect worst-case values over the recommended operating conditions. Finished ? Internal Net 4 rdbk. TRIG . ; G)Trtrc LIS AD a PRT VSN. a Tacn(5) rdbk.RIP- o oo \ 1h rdbk.DATA Komen DUMMY xX VALID x VALID / ue \ ~ TRORO (7) x1790 E/EX Description Symbol Min Max Units rdbk. TRIG rdbk. TRIG setup to initiate and abort Readback | 1 Trrac 200 - ns rdbk. TRIG hold to initiate and abort Readback 2 Trert 50 - ns rdelk.1 rdbk.DATA delay 7 Trerp - 250 ns rdbk.RIP delay 6 Trear - 250 ns High time 5 TroH 250 500 ns Low time 4 Tree 250 500 ns Note 1: Timing parameters apply to all speed grades. Note 2: If rdok. TRIG is High prior to Finished, Finished will trigger the first Readback. XL Description Symbol Min Max Units tdbk. TRIG rdbk. TRIG setup to initiate and abort Readback | 1 Tatrc 200 - ns rdbk. TRIG hold to initiate and abort Readback 2 Treat 50 - ns rdelk.1 rdbk. DATA delay 7 Trerp - 250 ns rdbk.RIP delay 6 Trerr - 250 ns High time 5 Trecu 250 500 ns Low time 4 Tree 250 500 ns Note 1: Timing parameters apply to all speed grades. Note 2: if rdbk. TRIG is High prior to Finished, Finished will trigger the first Readback. July 30, 1997 (Version 1.2) 55ae lal iat XC4000E and XC4000X Series Field Programmable Gate Arrays Configuration Timing The seven configuration modes are discussed in detaif in this section. Timing specifications are included. Slave Serial Mode In Slave Serial mode, an external signal drives the CCLK input of the FPGA. The serial configuration bitstream must be available at the DIN input of the lead FPGA a short setup time before each rising CCLK edge. The lead FPGA then presents the preamble dataand all data that overflows the lead deviceon its DOUT pin. NOTE: M2, M1, MO can be shorted to Ground If not used as /O There is an internal delay of 0.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the sub- sequent rising CCLK edge. Figure 51 shows a full master/slave system. An XC4000 Series device in Slave Serial mode should be connected as shown in the third device from the left. Slave Serial mode is selected by a <111> on the mode pins (M2, M1, M0). Slave Serial is the default mode if the mode pins are left unconnected, as they have weak pull-up resis- tors during configuration. NOTE: M2, M1, MO can be shorted to Vcc if not used as YO XCA000E/K Veo 1} coi CuK MASTER XC1700D +8V XC4000E/X, XC3100A SERIAL Sor XC5200 SLAVE ccux CLK vPr SLAVE ON DATA PROGRAM ie ce cEG|}-_ ->>| Program roam] RESET wt RESETIOE p~| DONE iNT > oF int > {Low Rlaset Option Used} L DONE nit cal PROGRAM | X9025 Figure 51: Master/Slave Serial Mode Circuit Diagram DIN Bitn @)Toce ~~ @) Teen t+ Teer J cue < @ Ton ++*@ Teco (Output) Bitn-1 Bitn X5379 Description Symbol Min Max Units DIN setup 1 Tocc 20 ns DIN hold 2 Toop 0 ns DIN to DOUT 3 Teco 30 ns CCLK High time 4 Tocu 45 ns Low time 5 Toot 45 ns Frequency Foc 10 MHz Note: Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High. Figure 52: Slave Serial Mode Programming Switching Characteristics 56 July 30, 1997 (Version 1.2)Master Serial Mode In Master Serial mode, the CCLK output of the lead FPGA drives a Xilinx Serial PROM that feeds the FPGA DIN input. Each rising edge of the CCLK output increments the Serial PROM internal address counter. The next data bit is put on the SPROM data output, connected to the FPGA DIN pin. The lead FPGA accepts this data on the subsequent rising CCLK edge. The lead FPGA then presents the preamble dataand all data that overflows the lead deviceon its DOUT pin. There is an internal pipeline delay of 1.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. In the bitstream generation software, the user can specify Fast ConfigRate, which, starting several bits into the first CCLK (Output) @) Tews $< XILINX frame, increases the CCLK frequency by a factor of eight. For actual timing values please refer to page 4-67. Be sure that the serial PROM and slaves are fast enough to support this data rate. XC2000, XC3000/A, and XC3100A devices do not support the Fast ConfigRate option. The SPROM CE input can be driven from either [DC or DONE. Using [BC avoids potential contention on the DIN pin, if this pin is configured as user-I/O, but CDC is then restricted to be a permanently High user output after con- figuration. Using DONE can also avoid contention on DIN, provided the early DONE option is invoked. Figure 51 on page 56 shows a full master/siave system. The feftmost device is in Master Serial mode. Master Serial mode is selected by a <000> on the mode pins (M2, M1, MO). y~ Toscx Serial Data In LX eX _\ sens ee Ket KX 3223 Description Symbo! Min Max Units DIN setup 1 Tosek 20 ns CCLK DIN hold 2 Texps 0 ns Notes: 1. At power-up, Vcc must ris from 2.0 V to Vcc min in tess than 25 ms, otherwise delay configuration by pulling PROGRAM Low until Vcc is valid. 2. Master Serial mode timing is based on testing in stave mode. Figure 53: Master Serial Mode Programming Switching Characteristics July 30, 1997 (Version 1.2) 57XC4000E and XC4000X Series Field Programmable Gate Arrays Master Parallel Modes in the two Master Parallel modes, the lead FPGA directly addresses an industry-standard byte-wide EPROM, and accepts eight data bits just before incrementing or decre- menting the address outputs. The eight data bits are serialized in the lead FPGA, which then presents the preamble dataand all data that over- flows the lead deviceon its DOUT pin. There is an inter- nal delay of 1.5 CCLK periods, after the rising CCLK edge that accepts a byte of data (and also changes the EPROM address) until the falling CCLK edge that makes the LSB (DO) of this byte appear at DOUT. This means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. The PROM address pins can be incremented or decre- mented, depending on the mode pin settings. This option allows the FPGA to share the PROM with a wide variety of microprocessors and microcontrollers. Some processors must boot from the bottom of memory (all zeros) while oth- ers must boot from the top. The FPGA is flexible and can load its configuration bitstream from either end of the mem- ory. Master Parallel Up mode is selected by a <100> on the mode pins (M2, M1, MO). The EPROM addresses start at 00000 and increment. Master Parallel Down mode is selected by a <110> on the mode pins. The EPROM addresses start at 3FFFF and decrement. Additional Address lines in XC4000 devices The XC4000X devices have additional address lines (A18- A21) allowing the additional address space required to daisy-chain several large devices. The extra address lines are programmable in XC4000EX devices. By default these address lines are not activated. In the default mode, the devices are compatible with existing XC4000 and XC4000E products. If desired, the extra address lines can be used by specifying the address lines option in bitgen as 22 (bitgen -g AddressLines:22). The lines (A18-A21) are driven when a master device detects, via the bitstream, that it should be using all 22 address lines. Because these pins will initially be pulled high by internal pull-ups, designers using Master Parallel Up mode should use external pull down resistors on pins A18-A21. If Master Parallel Down mode is used external resistors are not necessary. All 22 address lines are always active in Master Parallel modes with XC4000XL devices. The additional address lines behave identically to the lower order address lines. If the Address Lines option in bitgen is set to 18, it will be ignored by the XC4000XL device. The additional address lines (A18-A21) are not available in the PC84 package. HIGH TQ DIN OF OPTIONAL or DAISY.CHAINED FPGAS 47KQ LOW ONG - | | NC Mo M1 M2 TO CCLK OF OPTIONAL ~ DAISY-CHAINED FPGAS NOTE:MO can be shorted to Ground if not used az MO MT M2 as. vec Als DIN pout - ais [ EPROM (8K x8) > 47KQ AIlgT <-> | (OR LARGER) ocuK USER CONTROL OF HIGHER int Ai3f- ORDER PROM ADDRESS BITS XC4Q00E/K M2 ata CAN BE USED TO SELECT BETWEEN SLAVE ALTERNATIVE CONFIGURATIONS 1 ail a PROGRAM ato Ato PROGRAM re) a8 E mT D7 re) AB 06 a7 ar D7 D5 a6 AB 06 Ds AS AS Ds 03 MA AA oa 02 a3 aa 3 ot Ag a2 2 Do at wT AI o1 a0 a0 bo DONE CE pe] CE DATA BUS 8 BUS ig PROGRAM Figure 54: Master Parallel Mode Circuit Diagram 58 July 30, 1997 (Version 1.2)$< XILINX (oueess x Address for Byte n Address for Byte n+ 1 ~ @Trac -D7 D0-D Byte x RCLK (output) S / 7 CCLKs CCLK CCLK a , (output) DOUT (output) x De XK D7 Byte n-1 x6078 Description Symbol Min Max Units Delay to Address valid 1 Trac 0 200 ns RCLK Data setup time 2 Tore 60 ns Data hold time 3 Treo 0 ns Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAM Low until Vec is valid. 2. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge). This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than 500 ns. EPROM data output has no hold-time requirements. Figure 55: Master Parallel Mode Programming Switching Characteristics July 30, 1997 (Version 1.2) 59XC4000E and XC4000X Serles Fleid Programmable Gate Arrays Synchronous Peripheral Mode Synchronous Peripheral mode can also be considered Slave Parallel mode. An external signal drives the CCLK input(s) of the FPGA(s). The first byte of parallel configura- tion data must be available at the Data inputs of the lead FPGA a short setup time before the rising CCLK edge. Subsequent data bytes are clocked in on every eighth con- secutive rising CCLK edge. The same CCLK edge that accepts data, also causes the RDY/BUSY output to go High for one CCLK period. The pin name is a misnomer. In Synchronous Peripheral mode it is really an ACKNOWLEDGE signal. Synchronous operation does not require this response, but it is a meaningful signal for test purposes. Note that RDY/BUSY is pulled High with a high-impedance pullup prior to INIT going High. The lead FPGA serializes the data and presents the pre- amble data (and all data that overflows the lead device) on its DOUT pin. There is an internal delay of 1.5 CCLK peri- ods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. In order to complete the serial shift operation, 10 additional CCLK rising edges are required after the last data byte has been loaded, plus one more CCLK cycle for each daisy- chained device. Synchronous Peripheral mode is selected by a <011> on the mode pins (M2, M1, MO). NOTE: M2 can be shorted to Ground if not used as VO NYC 4.7kQ N/C | | | L Lj of MO Mi M2 MO M1 M2 CLOCK CCLK CCLK OPTIONAL 8 DAISY-CHAINED DATA BUS 7+] p, FPGAs DOUT DIN DOUT F voc XC4000E/X XC4000E/X Ty SYNCHRO- SLAVE } NOUS 47ka $ PERIPHERAL CONTROL 1 ADY/BUSY _ SIGNALS INIT DONE INIT DONE 4.7 kQ PROGRAM + PROGRAM PROGRAM Figure 56: Synchronous Peripheral Mode Circuit Diagram X9027 60 July 30, 1997 (Version 1.2)4k $< XILINX 1 st iNiT ) BYTEO XXX TY BYTE 1 OUT DOUT KoXtX2zXsXe Xs Xe Xz 0X1 1 ! RDY/BUSY {_ [N X6096 Description Symbol Min Max Units (High) setup time Tic 5 ps DO - D7 setup time Toc 60 ns DO - D7 hold time Top 0 ns CLK CCLK High time Tocx 50 ns CCLK Low time Teo. 60 ns CCLK Frequency Foc 8 MHz Notes: 1. Peripherat Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the first data byte on the eecond rising edge of CCLK after INIT goes High. Subsequent data bytes are clocked in on every eighth consecutive rising edge of CCLK. 2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does not require such a 3. The pin name RDY, isa misnomer. In Synchronous Peripheral mode this is really an ACKNOWLEDGE signal. 4, Note that data starts to shift out serially on the DOUT pin 0.5 GCLK periods after it was loaded in parallel. Therefore, additional CCLK pulses are clearly required after the last byte has been loaded. Figure 57: Synchronous Peripheral Mode Programming Switching Characteristics July 30, 1997 (Version 1.2) 61XC4000E and XC4000X Series Field Programmable Gate Arrays Asynchronous Peripheral Mode Write to FPGA Asynchronous Peripheral mode uses the trailing edge of the logic AND condition of WS and C56 being Low and RS and CS1 being High to accept byte-wide data from a micro- processor bus. In the lead FPGA, this data is loaded into a double-buffered UART-like parailel-to-serial converter and is serially shifted into the internal logic. The lead FPGA presents the preamble data (and all data that overflows the lead device) on its DOUT pin. The RDY/ BUSY output from the lead FPGA acts as a handshake sig- nal to the microprocessor. RDY/BUSY goes Low when a byte has been received, and goes High again when the byte-wide input buffer has transferred its information into the shift register, and the buffer is ready to receive new data. A new write may be started immediately, as soon as the RDY/BUSY output has gone Low, acknowledging receipt of the previous data. Write may not be terminated until RDY/BUSY is High again for one CCLK period. Note that RDY/BUSY is pulled High with a high-impedance pull- up prior to INIT going High. The Jength of the BUSY signal depends on the activity in the UART. If the shift register was empty when the new byte was received, the BUSY signal lasts for only two CCLK periods. If the shift register was still full when the new byte was received, the BUSY signal can be as long as nine CCLK periods. Note that after the last byte has been entered, only seven of its bits are shifted out. CCLK remains High with DOUT equal to bit 6 (the next-to-last bit) of the last byte entered. SALA ee Fite Mines gd egy The READY/BUSY handshake can be ignored if the delay from any one Write to the end of the next Write is guaran- teed to be longer than 10 CCLK periods. Status Read The logic AND condition of the C50, CStand RS inputs puts the device status on the Data bus. * D7 High indicates Ready * D7 Low indicates Busy * DO through D6 go unconditionally High It is mandatory that the whole start-up sequence be started and completed by one byte-wide input. Otherwise, the pins used as Write Strobe or Chip Enable might become active outputs and interfere with the final byte transfer. If this transfer does not occur, the start-up sequence is not com- pleted all the way to the finish (point F in Figure 47 on page 51). In this case, at worst, the internal reset is not released. At best, Readback and Boundary Scan are inhibited. The length-count value, as generated by the XACTstep soft- ware, ensures that these problems never occur. Although RDY/BUSY is brought out as a separate signal, microprocessors can more easily read this information on one of the data lines. For this purpose, D7 represents the RDyY/SUSY status when RS is Low, WS is High, and the two chip select lines are both active. Asynchronous Peripheral mode is selected by a <101> on the mode pins (M2, M1, MO). NC Ne a we _~__, L* | | Mo M2 MG Mt M2 DATA 8 BUS 00-7 ceLK OPTIONAL COLK DAISY-CHAINED FPGAS. _ BOUT DIN DOUT | vec ADDRESS ADDRESS bret XC4000E/X sus ASYNCHRO- XC4000E/X NOUS SLAVE a7ka a7 og PERIPHERAL RS we CONTROL ROY/BUSY SIGNALS __ INIT INT DONE DONE REPROGRAM #ROGRAN aM 47kQ x9028 Figure 58: Asynchronous Peripheral Mode Circult Diagram 62 July 30, 1997 (Version 1.2)$< XILINX Write to LCA WEST AS,cst Geaeetey Do-D7 RDY/BUSY Dour \ Provou Bye be Yo XY Xo Yo X6097 Description Symbol Min Max Units Effective Write time 1 Toa 100 ns (C560, WS=Low; RS, CS1=High) Write DIN setup time 2 Too 60 ns DIN hold time 3 Tep 0 ns RDY/BUSY delay after end of 4 Twrre 60 ns Write or Read RDY /RDY/BUSY active after beginning 7 60 ns of Read RDY/BUSY Low output (Note 4) 6 Tausy 2 9 CCLK periods Notes: 1. Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High. 2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte processing and the phase of the internal timing generator for CCLK. 3. CCLK and DOUT timing is tested in slave mode. 4. Tgusy indicates that the double-buffered parailel-to-serial converter is not yet ready to receive new data. The shortest Tausy occurs when a byte is loaded into an empty parallel-to-serial converter. The longest Tgysy occurs when a new word is loaded into the input register before the second-level buffer has started shifting out data. This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS. RDY/BUSY will go active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but write may not be terminated until RDY/BUSY has been High for one CCLK period. Figure 59: Asynchronous Peripheral Mode Programming Switching Characteristics July 30, 1997 (Version 1.2) 63XC4000E and XC4000X Series Field Programmable Gate Arrays Table 22: Pin Functions During Configuration CONFIGURATION MODE <M2:M1:M0> SLAVE MASTER SYNCH. ASYNCH. MASTER MASTER USER SERIAL SERIAL PERIPHERAL | PERIPHERAL | PARALLEL DOWN| PARALLEL UP OPERATION <2:1:1> :1:1> <1:0:1> <t:1:0 <1 VO vo vO DONE CCLK vO vO vO vo vo vo vo vo 0 vo vO SGCK4-GCK5-I/O TDI-VO TCK-I/O TMS-I/O vO PGCK4-GCK6-1/O vO vO VO vO vO vO vO vO vO vO vO VO vo SGCK1-GCK7-VO PGCK1-GCK8-1/O vO vO vo vO vo ALL OTHERS * XC4000X only Notes 1. A shaded table cell represents a 50 kQ2 - 100 kQ pull-up before and during configuration. 2. (1) represents an input; (O) represents an output. 3. is an open-drain output during configuration. 64 July 30, 1997 (Version 1.2)$= XILINX Configuration Switching Characteristics Veo - T por PROGRAM y | z 5 CCLK OUTPUT or INPUT y~ IR RE-PROGRAM " > (+ <300ns Mo, M1, M2 ( x \ (Required) VALID DONE RESPONSE X1832 _ <300 ns Master Modes (XC4000E/EX) Description Symbol Min Max Units MO = High Tpor 10 40 ms Power-On Reset MO = Low Teor 40 130 ms Program Latency Tp, 30 200 HS per CLB column CCLK (output) Detay Ticck 40 250 ps CCLK (output) Period, slow Took 640 2000 ns CCLK (output) Period, fast Teck 80 250 ns Master Modes (XC4000XL) Description Symbol Min Max Units MO = High Tpor 10 40 ms Power-On Reset MO = Low Tpor 40 130 ms Program Latency Tp; 30 200 pS per CLB column CCLK (output) Delay Tieck 40 250 ps CCLK (output) Period, slow Teocik 540 1600 ns CCLK (output) Period, fast Teck 67 200 ns Slave and Peripheral Modes(All) Description Symbol Min Max Units Power-On Reset Tpor 10 33 ms Program Latency Tpy 30 200 Lis per CLB column CCLK (input) Delay (required) Ticek 4. pS CCLK (input) Period (required) Tock 100 ns July 30, 1997 (Version 1.2)XC4000E and XC4000X Series Fieid Programmable Gate Arrays XC4000XL Switching Characteristics Definition of Terms In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families. Values are subject to change. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final. All specifications subject to change without notice. XC4000XL Absolute Maximum Ratings Symbol Description Value Units Voc Supply voltage relative to GND -0.5 to 4.0 Vv Vin Input voltage relative to GND (Note 1) -0.5 to 5.5 Vv Vrs Voltage applied to 3-state output (Note 1) -0.5 to 5.5 Vv Vect Longest Supply Voltage Rise Time from 1V to 3V 50 ms Tste Storage temperature (ambient) -65 to +150 C Tsar Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 C rT Junction temperature Ceramic packages +150 C 4 Plastic packages +125 C Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device ping may undershoot to -2.0 V or overshoot to + 7.0 V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being timited to 200 mA. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those fisted under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. XC4000XL Recommended Operating Conditions Symbol Description Min Max Units Supply voltage relative to GND, T, = 0C to +85C | Commercial 3.0 3.6 Vv Voc Supply voltage relative to GND, T, = -40C to Industrial 3.0 3.6 Vv +100C Vin High-level input voltage 50% of Voc 5.5 Vv Vir Low-level input voltage 0 30% of Voc Vv Tin Input signal transition time 250 ns Notes: At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C. Input and output measurement thrashald is ~40% of Voc. July 30, 1997 (Version 1.2)$< XILINX XC4000XL DC Characteristics Over Recommended Operating Conditions Symbol Description Min Max Units Von High-level output voltage @ Igy = -4.0 MA, Voc min (LVTTL) 2.4 Vv High-level output voltage @ Io. = -500 pA, (LVCMOS) 90% Voc Vv Vor Low-level output voltage @ ig, = 12.0 MA, Voge min (LVTTL) (Note 1) 0.4 Vv Low-level output voltage @ iq, = 1500 nA, (LVCMOS) 10%Veco| V Vor Data Retention Supply Voltage (below which configuration data may be lost) 2.5 Vv loco | Quiescent FPGA supply current (Note 2) 5 mA i Input or output leakage current -10 +10 HA Input capacitance (sample tested) BGA, SBGA, PQ, HQ, MQ 10 pF Cin packages PGA packages 16 pF lnPU Pad pull-up (when selected) @ V,,, = OV (sample tested) 0.02 0.25 mA IRPp | Pad pull-down (when selected) @ V,, = 3.6V (sample tested) 0.02 0.15 mA TALE Horizontal Longline pull-up (when selected) @ logic Low 0.3 2.0 mA Note 1: With up to 64 pins simultaneously sinking 12 mA. Note 2: With no output current loads, no active input or Longline pull-up resistors, ali //O pins Tri-stated and floating. July 30, 1997 (Version 1.2) 67XC4000E and XC4000X Series Field Programmabie Gate Arrays XC4000XL Global Buffer Switching Characteristic Guidelines oye et apes Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible 1OB and CLB flip-flops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Speed Grade Units Description Symbol Device From pad through Global Low Skew buffer, to any clock K Teis XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL From pad through Global Early buffer, to any clock K in same quadrant Tee XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL Note: Parameters are for BUFGE #s 1, 2, 5 and 6. Add 1.4 ns for BUFGE #s 3, 4, 7 and 8. July 30, 1997 (Version 1.2)$< XILINX XC4000XL CLB Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000XL devices and expressed in nanoseconds unless otherwise noted. Speed Grade 3 -2 1 Description Symbol Min Max Min Max Min Max Combinatorial Delays Googe F/G inputs to X/Y outputs F/G inputs via H to X/Y outputs F/G inputs via transparent latch to Q outputs C inputs via SR/HO via H to X/Y outputs C inputs via H1 via H to X/Y outputs C inputs via DIN/H2 via H to X/Y outputs C inputs via EC, DIN/H2 to YQ, XQ output (bypass) | T, CLB Fast Carry Logic Operand inputs (F1, F2, G1, G4) to COUT Add/Subiract input (F3) to COUT initialization inputs (F1, F3) to COUT CIN through function generators to X/Y outputs CIN to COUT, bypass function generators Sequential Delays Clock K to Flip-Flop outputs Q Clock K to Latch outputs Q Setup Time before Clock K F/G inputs F/G inputs via H C inputs via HO through H C inputs via H1 through H C inputs via H2 through H C inputs via DIN C inputs via EC C inputs via S/R, going Low (inactive) CIN input via F/G CIN input via F/G and H Units Hold Time after Clock K a oe F/G inputs Text 0 0 0 ns F/G inputs via H Toxin 0 0 0 ns C inputs via SR/HO through H ToKHHo 0 0 0 ns C inputs via H1 through H TexHH1 0 0 0 ns C inputs via DIN/H2 through H Tornre 0 0 Q ns C inputs via DIN/H2 Texpi 0 0 0 ns C inputs via EC Tokec 0 0 0 ns C inputs via SR, going Low (inactive) Texr 0 0 0 ns Clock Clock High time Clock Low time Set/Reset Direct Width (High) Delay from C inputs via S/R, going High to Q Global Set/Reset Minimum GSR Pulse Width Delay from GSR input to any Q Note 1 Tura Toggle Frequency (MHz) (Note 2) Frog 166 179 200 MHz Note 1: For values per device, see Globalis Set/Reset entries on page 4-82. Note 2: Maximum flip-flop toggle rate for export contro! purposes. July 30, 1997 (Version 1.2) 69XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000XL CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000XL devices and are expressed in nanoseconds unless otherwise noted. Speed Grade 3 -2 -1 Single Port RAM Units Size Symbol | Min | Max | Min | Max | Min | Max Write Operation Address write cycle time (clock K period) | 16x2 | Twos 9.0 8.4 7.7 ns 32x1 Twers 9.0 8.4 7.7 ns Clock K pulse width (active edge) 16x2 | Twes 45 42 3.9 ns 32x1 Twets 4.5 4.2 3.9 ns Address setup time before clock K 16x2 | Tags 2.2 2.0 1.7 ns 32x1 Tasts 2.2 2.0 1.7 ns Address hold time after clock K 16x2 | Tans 0 0 0 ns 32x1 Tants 0 0 0 ns DIN setup time before clock K 16x2 | Toss 2.0 1.9 17 ns 32x1 Tpsts 2.5 2.3 2.1 ns DIN hoid time after clock K 16x2 | Tons 0 0 0 ns 32x1 Touts 0 Q 0 ns WE setup time before clock K 16x2 | Twss 2.0 1.8 1.6 ns 32x1 Twsts 1.8 1.7 1.5 ns WE hold time after clock K 16x2 | Twus 0 0 0 ns 32x1 Twuts 0 0 0 ns Data valid after clock K 16x2_ | Twos 32x1 TwotTs Speed Grade Dual Port RAM Units Write Operation Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hoid time after clock K Data valid after clock K Notes: Timing for the 16 x1 RAM option is identical to 16 x 2 RAM timing.Applicable Read timing specifications are identical to Asynchronous (Level Sensitive) Read timing. 70 July 30, 1997 (Version 1.2)$< XILINX XC4000XL CLB RAM Synchronous (Edge-Triggered) Write Timing ~__ Twes ADDRESS DATA OUT Tpsps Toxps ADDRESS DATA OUT July 30, 1997 (Version 1.2) 71XC4000E and XC4000X Series Fleld Programmable Gate Arrays XC4000XL CLB RAM Asynchronous (Level-Sensitive) Write and Read Operation Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the Static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation nettist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000XL devices and are expressed in nanoseconds unless otherwise noted. Synchronous RAM is recommended for new designs. Speed Grade 3 2 1 Units Description | Size | Symbol Write Operation Address write cycle time 16x2 | Twe . . 32x1 | Twer 10.6 9.2 8.0 ns Write Enable pulse width (High) 16x2 | Twp 5.3 46 4.0 ns 32x11 Twet 5.3 4.6 4.0 ns Address setup time before WE 16x2 |Tas 2.7 2.3 2.0 ns 32x1 | Tast 2.9 2.5 2.2 ns Address hold time after end of WE | 16x2 | Tay 2.7 2.3 2.0 ns 32x11 | Taunt 2.7 2.3 2.0 ns DIN setup time before end of WE 16x21 Tops 14 0.9 0.8 ns 32x1 | Tost 11 0.9 0.8 ns DIN hold time after end of WE 16x2) | Toy 9.4 8.1 6.9 ns 32x1 | Tour 9.4 8.1 6.9 ns Read Operation Address read cycle time 16x2 | Tre 45 3.1 2.6 ns 32x1 | Trot 6.5 5.5 3.8 ns Data valid after address change 16x2 | Tio 1.6 1.5 1.3 ns (no Write Enable) 32x1 | Tito 2.7 2.2 Read Operation, Clocking Data Into Flip-Flop 2.4 ns Address setup time before clock K | 16x2) | Tick 1.3 11 1.0 ns 32x1 | Truck 2.3 2.0 1.8 ns Read During Write Data valid after WE goes active 16x2. | Two (DIN stable before WE) 32x1 | Twot Data valid after DIN 16x2 | Topo (DIN changes during WE) 32x1_ | Toor Read During Write, Clocking Data Into Filp-Flop WE setup time before clock K 16x2 | Twex 7.3 6.4 5.5 ns 32x1 TWCKT 9.3 8.1 7.0 ns Data setup time before clock K 16x2 | Tock 72 July 30, 1997 (Version 1.2)$< XILINX XC4000XL CLB RAM Asynchronous (Level-Sensitive) Timing Characteristics Two ADDRESS WRITE ~e- TAS Twe 1 T AHe| WRITE ENABLE DATA IN REQUIRED READ WITHOUT WRITE X,Y OUTPUTS READ, CLOCKING DATA INTO FLIP-FLOP as Tick >< Too >| cane | | TCoKO VALID VALID (OLD (NEW) XQ, YQ OUTPUTS READ DURING WRITE WRITE ENABLE _ TDoH DATA IN {stable during WE} X, Y OUTPUTS VALID VALID DATA IN (changing during WE) OLD NEW X, Y OUTPUTS READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP Twe WRITE ENABLE [+ Twek ~_ Tock cen | a beTeKo XQ, YQ OUTPUTS July 30, 1997 (Version 1.2) 73XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000XL Pin-to-Pin Output Parameter Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and norma! clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. XC4000XL Output Flip-Flop, Clock to Out Speed Grade 3 -2 ] Description Symbol Device Global Low Skew Clock to Output using OFF | Tickor XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL Global Early Clock to Output using OFF [Ticxeor | XC4005XL Values are for BUFGE #s 1, 2, 5 and 6. Add XC4010XL 1.4 ns for BUFGE #s 3, 4, 7 and 8. XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL For output SLOW option add Tstow All Devices OFF = Output Flip Flop Notes: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible OB and CLB flip-flops are clocked by the gicbal clock net. Output timing is measured at ~50% Vog threshold with 35 pF external capacitive load. Units 74 July 30, 1997 (Version 1.2)$< XILINX XC4000XL Output MUX, Clock to Out Speed Grade 3 -2 1 Unite Description Symbol Device Max Max Max " Global Low Skew Clock to Output using Teepe XC4005XL 7.8 6.8 5.9 ns OMUX XC4010XL 8.4 7.3 6.3 ns XC4013XL 8.8 7.6 6.6 ns XC4020XL 9.2 8.0 6.9 ns XC4028XL. 9.6 8.3 7.2 ns XC4036XL 10.0 8.7 75 ns XC4044XL 10.5 9.1 79 ns XC4052XL 10.9 9.5 8.2 ns XC4062XL 11.4 9.9 8.6 ns XC4085XL 12.3 10.7 9.3 ns Global! Early Clock to Output using OMUX Tperpr XC4005XL 7.1 6.3 5.6 ns Values are for BUFGE #s 1, 2, 5 and 6. Add XC4010XL 7.3 6.4 5.6 ns 1.4 ns for BUFGE #s 3, 4, 7 and 8. XC4013XL 76 6.6 5.7 ns XC4020XL 7.7 6.7 6.0 ns XC4028XL 8.0 6.9 6.0 ns XC4036XL 8.2 7.2 6.2 ns XC4044XL 8.6 7.5 6.5 ns XC4052XL 9.2 8.0 6.9 ns XC4062XL 10.0 8.8 7.6 ns XC4085XL 11.0 9.6 8.6 ns For output SLOW option add Tstow All Devices 3.0 2.5 2.0 ns OMUX = Output MUX Notes: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible {OB and CLB flip-flops are clocked by the global clock net. Output timing is measured at ~60% Voc threshold with 35 pF external capacitive load. July 30, 1997 (Version 1.2) 75XC4000E and XC4000X Series Fleld Programmable Gate Arrays XC4000XL Pin-to-Pin Input Parameter Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. XC4000XL Global Low Skew Clock, Set-Up and Hold Speed Grade. -3 2 1 Units Description Symbol Device Min Min Min " Input Setup Time, using Global Low Skew | Tpsp XC4005XL 8.8 7.6 6.6 ns clock and IFF (full delay) XC4010XL 9.0 7.8 6.8 ns XC4013XL 6.4 6.0 5.6 ns XC4020XL 8.8 7.6 6.6 ns XC4028XL 9.8 8.5 7.4 ns XC4036XL 6.6 6.2 5.8 ns XC4044XL 10.6 9.2 8.0 ns xC4052XL 11.2 9.7 8.4 ns XC4062XL 6.8 6.4 6.0 ns XC4085XL 12.7 11.0 9.6 ns input Hold Time, using Global Low Skew =| Tpyip XC4005XL. 0 0 0 ns clock and IFF (full delay) XC4010XL 0 0 0 ns XC4013XL 0 0 0 ns XC4020XL 0 0 0 ns XC4028XL 0 0 0 ns XC4036XL 0 0 0 ns XC4044XL 0 0 0 ns XC4052XL 0 0 0 ns XC4062XL 0 0 0 ns XC4085XL 0 0 0 IFF = input Flip-Flop or Latch Note: Setup time is measured with the fastest route and the lightest load. Use the static under given design conditions. Hold time is measured using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer to determine the setup and hold times under given design conditions. 76 July 30, 1997 (Version 1.2)$< XILINX XC4000XL BUFGE #s 3, 4, 7, and 8 Global Early Clock, Set-Up and Hold for IFF and FCL SpeedGrade[ -3 2 I Uni Description Symbol Device Min Min Min nits Input Setup Time XC4005XL 8.4 79 74 ns Global Early clock and IFF (partial delay) | Tpsep XC4010XL 10.3 9.0 7.8 ns Global Early clock and FCL (partial delay) | Tprsep XC4013XL 5.4 4.9 4.4 ns XC4020XL 9.8 9.3 8.8 ns XC4028XL 12.7 41.0 9.6 ns XC4036XL 6.4 5.9 5.4 ns XC4044XL 13.8 12.0 10.4 ns XC4052XL. 14.5 12.7 11.0 ns XC4062XL 8.4 79 7.4 ns XC4085XL 14.5 12.7 11.0 ns Input Hold Time XC4005XL 0 ) ns Global Early clock and IFF (partial delay) | Tpyep XC4010XL 0 0 ns Global Early clock and FCL (partial delay) | Tecuep XC4013XL 0 0 ns XC4020XL 0 0 ns XC4028XL 0 0 ns XC4036XL 0.8 0.8 ns XC4044XL 0 0 ns XC4052XL 0 0 ns XC4062XL 1.5 ns XC4085XL ns IFF = Input Flip-Flop or Latch XC4000XL BUFGE #s 1, 2, 5, and 6 Global Early Clock, Set-Up and Hold for [FF and FCL SpeedGrade] _-3_ 2 I Units Description Symbo! Device Min Min Min Input Setup Time XC4005XL 9.0 8.5 8.0 ns Globai Early clock and IFF (partial delay) | Tpsep XC4010XL 11.9 10.4 9.0 ns Global Early clock and FCL (partial delay) | Tprsep XC4013XL 6.4 5.9 5.4 ns XC4020XL 10.8 10.3 9.8 ns XC4028XL 14.0 12.2 10.6 ns XC4036XL 7.0 6.6 6.2 ns XC4044XL 14.6 12.7 11.0 ns XC4052XL 16.4 14.3 12.4 ns XC4062XL 9.0 8.6 8.2 ns XC4085XL 16.7 14.5 12.6 ns Input Hold Time XC4005XL 0 0 0 ns Global! Early clock and IFF (partial delay) | Tpyep XC4010XL 0 0 0 ns Global Early clock and FCL (partial delay) | TprHep XC4013XL 0 0 0 ns XC4020XL 0 0 0 ns XC4028XL 0 0 0 ns XC4036XL 0 0 0 ns XC4044XL 0 0 0 ns XC4052XL 0 0 0 ns XC4062XL 0.8 0.8 0.8 ns XC4085XL 0 0 0 ns FCL = Fast Capture Latch vod Notes: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the farthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer to determine the setup and hold times under given design condi- tions. July 30, 1997 (Version 1.2) 77XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000XL IOB Input Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction ternperature). Speed Grade[ _-3 2 i Units Description Symbol Device Min Min Min Clocks aL ee Delay from FCL enable (OK) active edge to IFF | Toxix All devices clock (IK) active edge Propagation Delays : ce Max Max Pad to 11, 12 Trip All devices 1.6 14 1.2 ns Pad to !1, 12 via transparent input latch, no delay | Tp,, All devices 2.6 2.2 1.9 ns Pad to I1, I2 via transparent input latch, Tppil XC4005XL. 13.7 11.9 10.4 ns partial delay XC4010XL 9.3 8.1 7.0 ns XC4013XL 9.2 8.0 7.0 ns XC4020XL 16.9 14.7 12.8 ns XC4028XL 17.0 14.8 12.9 ns XC4036XL 9.8 8.6 7.4 ns XC4044XL 16.9 14.7 12.8 ns XC4052XL 17.8 15.5 13.5 ns XC4062XL 10.2 9.0 8.4 ns XC4085XL 20.2 17.5 15.3 ns Pad to 11, 12 via transparent input latch, full delay | Tppx, XC4005XL 11.0 9.6 8.4 ns XC4010XL 10.8 9.4 8.2 ns XC4013XL 411.0 9.6 8.4 ns XC4020XL 14.9 12.9 11.3 ns XC4028XL 14.0 12.2 10.6 ns XC4036XL 11.9 10.4 9.0 ns XC4044XL 14.1 12.3 10.7 ns XC4052XL 14.3 12.5 10.9 ns XC4062XL 12.7 11.0 10.3 ns XC4085XL 19.6 17.1 14.9 ns FCL = Fast Capture Latch, IFF = Input Flip-Flop or Latch 78 July 30, 1997 (Version 1.2)$< XILINX XC4000XL IOB Input Switching Characteristic Guidelines (Continued) Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the Static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Speed Grade Description Propagation Delays Pad to I1, i2 via transparent FCL and input latch, no delay Units Pad to !1, 12 via transparent FCL and input latch, partial delay Propagation Delays Clock (IK) to 11, 12 (flip-flop) Clock (IK) to 11, 12 (latch enable, active Low) FCL Enable (OK) active edge to 11, 12 (via transparent standard input latch) Tika Tree Tox. Global Set/Reset Minimum GSR Pulse Width Delay from GSR input to any Q Trai XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL. All devices All devices All devices All devices XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL. XC4052XL XC4062XL XC4085XL FCL = Fast Capture Latch 25.1 27.2 29.1 34.4 10.4 7.0 7.0 12.9 12.5 7.4 12.8 13.5 8.4 15.3 1.3 1.4 27 8.5 10.5 12.0 14.0 15.5 17.0 19.0 20.5 22.0 26.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns July 30, 1997 (Version 1.2) 79XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000XL IOB Input Switching Characteristic Guidelines (Continued) Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the Static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). 3 2 1 Units Description Symbol Device Min Min Min Setup Times ae 8 ee (ee Pad to Clock (IK), no delay Trick All devices 1.7 1.5 1.3 ns Pad to Clock (IK), partial delay Trickp XC4005XL 12.3 13.1 9.3 ns XC4010XL 7.9 6.9 6.0 ns XC4013XL 7.8 6.9 5.9 ns XC4020XL 78 13.5 11.7 ns XC4028XL 15.6 13.6 11.8 ns XC4036XL 8.4 7.3 6.3 ns XC4044XL 15.5 13.5 11.8 ns XC4052XL 16.4 14.3 12.4 ns XC4062XL 8.9 7.7 7.3 ns XC4085XL 18.8 16.3 14.2 ns Pad to Clock (IK), full delay Tpickp XC4005XL 9.7 8.4 7.3 ns XC4010XL 9.4 8.2 7.1 ns XC4013XL 9.7 8.4 7.3 ns XC4020XL 13.5 11.7 10.2 ns XC4028XL 12.6 10.9 9.5 ns XC4036XL 10.5 9.1 7.9 ns XC4044XL 12.7 11.0 9.6 ns XC4052XL 12.9 11.3 9.8 ns XC4062XL 11.3 9.8 9.2 ns XC4085XL 18.2 15.9 13.8 ns Pad to Clock (IK), via transparent Fast | Tpickr All devices 2.4 2.1 1.8 ns Capture Latch, no delay Pad to Clock (IK), via transparent Fast | Tpicxrp XC4005XL 12.9 11.2 9.8 ns Capture Latch, partial delay XC4010XL 8.5 7.4 6.4 ns XC4013XL 8.4 7.3 6.4 ns XC4020XL 16.1 14.0 12.2 ns XC4028XL 16.3 14.2 12.3 ns XC4036XL 9.0 7.9 6.8 ns XC4044XL 16.2 14.1 12.2 ns XC4052XL 17.0 14.8 12.9 ns XC4062XL 9.6 8.3 78 ns XC4085XL 19.4 16.8 14.7 ns Pad to Fast Capture Latch Enable Tpock All devices 0.7 0.6 0.5 ns (OK), no delay Setup Times Clock Enable (EC) to Clock (IK) Hold Times All Hold Times Note: Input pad setup and hold times are specified with respect to the internal clo i ip id ti the clock input pin, see the Global Low Skew Clock and Global Early Clock Set-up and Hold tables on pages 4-79 and 4-80. 80 July 30, 1997 (Version 1.2)$< XILINX XC4000XL IOB Output Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless otherwise noted. Values apply to all XC4000XL devices and are expressed in nanoseconds unless otherwise noted. Speed Grade 3 -2 71 Unit nits Description Symbol Min Max Min | Max | Min Max Propagation Delays Clock (OK) to Pad Toxpor 5.0 44 3.8 ns Output (O) to Pad Topr 41 3.6 3.1 ns 3-state to Pad hi-Z (slew-rate independent) | TrsHz 4.4 3.8 3.3 ns 3-state to Pad active and valid TTSONE 41 3.6 3.1 ns Output (O) to Pad via Fast Output MUX Torpr 5.5 4.8 4.2 ns Setup and Hold Times Output (O) to clock (OK) setup time Took 05 0.4 0.3 ns Output (O) to clock (OK) hold time Toxo 0 0 0 ns Clock Enable (EC) to clock (OK) setup Tecok 0 0 0 ns Clock Enable (EC) to clock (OK) hold ToKec 0.3 0.2 0.1 ns Clock Clock High Clock Low Global Set/Reset Minimum GSR pulse width Turaw 19.8 17.3 ns Delay from GSR input to any Pad Treo XC4005XL 15.9 13.8 12.0 ns XC4010XL 18.5 16.1 14.0 ns XC4013XL 20.5 17.8 15.5 ns XC4020XL 23.2 20.1 17.5 ns XC4028XL 25.1 21.9 19.0 ns XC4036XL 27.1 23.6 20.5 ns XC4044XL 29.7 25.9 22.5 ns XC4052XL . 276 24.0 ns XC4062XL . 29.3 25.5 ns XC4085XL 33.9 29.5 ns Slew Rate Adjustment : : For output SLOW option add Note : Output timing is measured at ~50% Vgc threshold, with 35 pF external capacitive loads. Note 2: For PCI applications, based on a 50 pF external capacitive load, add 400 ps to the propagation delay values. July 30, 1997 (Version 1.2) 81XCA000E and XC4000X Series Field Programmable Gate Arrays XC4000XL Horizontal Longline Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative vaiues. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Speed Grade 3 -2 Description Max Units TBUF driving a Horizontal Longline Symbol Device Max Note 1: These values are for a minimum ioad with the driver paced as far as possible from the active pullup(s). Fewer than the specified number of pullup resistors can be used, if desired. Using fewer pullups reduces power consumption but increases delays. Use the static timing analyzer to determine delays if fewer pullups are used. | going High or Low to Horizontal Longline going | Tio; XC4005XL. High or Low, while T is Low. Buffer is constantly XC4010XL active. XC4013XL XC4020XL XC4028XL . . . XC4036XL 11.6 10.1 8.8 ns XC4044XL 12.3 10.7 9.3 ns XC4052XL 13.6 11.8 10.3 ns XC4062XL 14.9 13.0 11.3 ns XC4085XL 18.0 15.6 13.6 ns T going Low to Horizontal Longline going from re- | Ton XC4005XL 5.6 4.9 4.2 ns sistive pull-up or floating High to active Low. XC4010XL 7.4 6.5 5.6 ns TBUF configured as open-drain or active XC4013XL 8.4 7.3 6.3 ns buffer with | = Low. XC4020XL 9.4 8.2 7.1 ns XC4028XL 10.5 9.1 7.9 ns XC4036XL 12.3 10.7 9.3 ns XC4044XL 13.0 11.3 9.8 ns XC4052XL 14.3 12.5 10.8 ns XC4062XL 15.6 13.6 11.8 ns XC4085XL. 18.6 16.3 144 ns T going High to Horizontal Longline going from =| Tpus XC4005XL 6.6 5.8 5.0 ns Low to High, pulled up by two resistors. (Note 1) XC4010XL 10.5 9.1 7.9 ns XC4013XL 7.9 6.9 6.0 ns XC4020XL 9.0 7.8 6.8 ns XC4028XL 14.6 12.7 11.1 ns XC4036XL 14.4 12.5 10.9 ns XC4044XL 17.4 15.1 13.2 ns XC4052XL. 18.8 16.3 14.2 ns XC4062XL 17.9 15.6 13.5 ns XC4085XL. 82 July 30, 1997 (Version 1.2)$< XILINX XC4000XL Horizontal Longline Switching Characteristic Guidelines (Continued) Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific; more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Ail timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Speed Grade 3 2 1 Units Description Device TBUF driving half a Horizontal Longline oo a I going High or Low to half of a Horizontal Longline | Tri01 XC4005XL 3.2 2.8 2.4 ns going High or Low, while T is Low. Buffer is con- XC4010XL 3.6 3.1 2.7 ns stantly active. XC4013XL 3.8 3.3 2.9 ns XC4020XL 41 3.6 3.1 ns XC4028XL 44 3.8 3.3 ns XC4036XL 48 4.2 3.6 ns XC4044XL 5.0 4.4 3.8 ns XC4052XL 5.3 46 4.0 ns XC4062XL 5.6 49 4.2 ns XC4085XL 6.3 5.5 48 ns T going Low to half of a Horizontal Longline going | THon XC4005XL 3.8 3.3 2.9 ns from resistive pull-up or floating High to active XC4010XL 42 3.7 3.2 ns Low. TBUF configured as open-drain or active XC4013XL 45 3.9 3.4 ns buffer with | = Low. XC4020XL 48 4.2 3.6 ns XC4028XL 5.0 4.4 3.8 ns XC4036XL 5.4 47 41 ns XC4044XL 5.7 5.0 43 ns XC4052XL 6.0 .2 45 ns XC4062XL 6.2 5.4 47 ns XC4085XL 7.0 6.1 5.3 ns T going High to half of a Horizontal Longline going | Tupus XC4005XL 41 3.6 3.1 ns from Low to High, pulled up by four resistors. XC4010XL 5.2 4.5 3.9 ns (Note 1) XC4013XL 4.3 3.7 3.2 ns XC4020XL 48 4.1 3.6 ns XC4028XL 6.6 5.8 5.0 ns XC4036XL 5.3 4.6 4.0 ns XC4044XL 7.6 6.6 5.8 ns XC4052XL 8.1 7.0 6.1 ns XC4062XL 6.5 5.7 49 ns XC4085XL 9.5 8.3 7.2 ns Note: These values include a minimum load of one output, spaced as far as possible from the active pullup(s). Use the static timing analyzer to determine the delay for each destination. Note 1: Fewer than the specified number of pullup resistors can be used, if desired. Using fewer puliups reduces power consumption but increases delays. Use the static timing analyzer to determine delays if fewer pullups are used. July 30, 1997 (Version 1.2) 83XC4000E and XC4000X Series Field Programmabie Gate Arrays XC4000XL Wide Decoder Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Speed Grade 3 -2 -1 Unit Description Symbol Device Max Max Max ms Full length, two pull-ups, Twar2 XC4005XL 7.0 6.1 5.3 ns inputs from IOB |-pins XC4010XL 10.6 9.2 8.0 ns XC4013XL 9.1 7.9 6.9 ns XC4020XL. 8.7 7.6 6.6 ns XC4028XL 14.0 12.2 10.6 ns XC4036XL. 11.6 10.1 8.8 ns XC4044XL 16.3 14.2 12.3 ns XC4052XL 17.4 15.2 13.2 ns XC4062XL 19.6 17.1 148 ns XC4085XL 21.6 18.7 16.3 ns Half length, two pull-ups, Twao2 XC4005XL 5.4 47 41 ns inputs from IOB I-pins XC4010XL 7.3 6.4 5.5 ns XC4013XL 6.5 5.7 49 ns XC4020XL 6.2 5.4 47 ns XC4028XL 9.0 7.9 6.8 ns XC4036XL 8.0 6.9 6.0 ns XC4044XL 10.2 8.8 7.7 ns XC4052XL. 10.7 9.3 8.1 ns XC4062XL 11.7 10.2 8.8 ns XC4085XL 12.5 10.8 9.4 ns Notes: These delays are specified from the decoder input to the decoder output. Fewer than the specified number of pullup resistors can be used, if desired. Using fewer pullups reduces power consumption but increases delays. Use the static timing analyzer to determine delays if fewer pullups are used. 84 July 30, 1997 (Version 1.2)$2 XILINX XC4000EX Switching Characteristics Definition of Terms In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families. Values are subject to change. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final. All specifications subject to change without notice. XC4000EX Absolute Maximum Ratings Symbol Description Value Units Vec Supply voltage relative to GND -0.5 to +7.0 Vv Vin Input voltage relative to GND (Note 1) -0.5 to Voc +0.5 Vv Vis Voltage applied to 3-state output (Note 1) -0.5 to Voc +0.5 Vv Voct Longest Supply Voltage Rise Time from 1 V to 4 V 50 ms Tst Storage temperature (ambient) -65 to +150 C Tsoi Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 C + Junction temperature Ceramic packages +150 C 4 Plastic packages +125 C Notes: 1. Maximum DC overshoot or undershcot above V,, or below GND must be limited to sither 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to Voc + 2.0 V, provided this over- or undershoot lasts less than 20 ns. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional! operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. XC4000EX Recommended Operating Conditions Symbol Description Min Max | Units Supply voltage relative to GND, Ty = 0 C to +85C Commercial 4.75 5.25 Vv Vee Supply voltage relative to GND, T; = -40C to +100C = | Industrial 4.5 5.5 Vv High-level input voltage TTL inputs 2.0 Voc Vv VK CMOS inputs 70% | 100% | Voc Low-level input voltage TTL inputs 0 0.8 Vv Vie CMOS inputs 0 20% | Voc Tin Input signal transition time 250 ns Notes: At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C. Input and output measurement thresholds for TTL are 1.5 V. Input and output measurement thresholds for CMOS are 2.5 V. All timing parameters are specified for Commercial temperature range only. July 30, 1997 (Version 1.2) 85XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000EX DC Characteristics Over Recommended Operating Conditions Symbol Description Min Max | Units Von High-level output voltage @ toy = -4.0 mA, Vee min TTL outputs 2.4 Vv High-level output voltage @ Io, = -1.0 MA CMOS outputs Voc-0.5 Vv Vor Note 1) output voltage @ Iq, = 12.0 MA, Veg min TTL outputs 0.4 Vv CMOS outputs 0.4 Vv Vor Data Retention Supply Voltage (below which configuration data may be lost) 3.0 Vv leco Quiescent FPGA supply current (Note 2) 25 mA I Input or output leakage current -10 +10 pA Input capacitance (sample tested) BGA, SBGA, PQ, 10 pF Cin HQ, MQ packages PGA packages 16 pF lepu Pad pull-up (when selected) @ V;, = 0 V (sample tested) 0.02 0.25 mA InPD Pad pull-down (when selected) @ V, = 5.5 V (sample tested) 0.02 0.25 mA late Horizontal Longline pull-up (when selected) @ logic Low 0.3 2.0 mA Note 1: With up to 64 pins simultaneously sinking 12 mA. Note 2: With no output current loads, no active input or Longline pull-up resistors, all package pins at Vec or GND. XC4000EX Global Buffer Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. Ali devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible 1OB and CLB flip-flops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Speed Grade -4 -3 2 -1 Units Description Symbol Device Max Max Max Max From pad through Global Low Skew buffer, | Te_s XC4028EX 9.2 75 6.4 ns to any clock K XC4036EX 9.8 7.9 7.1 ns From pad through Globai Early buffer, Tee XC4028EX 5.7 4.4 4.2 ns to any clock K in same quadrant XC4036EX 5.9 46 4.4 ns July 30, 1997 (Version 1.2)$< XILINX XC4000EX Longline and Wide Decoder Timing Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605, All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000EX devices unless otherwise noted. Fewer than the specified number of pullup resistors can be used, if desired. Using fewer pullups reduces power consumption but increases delays. Use the static timing analyzer to determine delays if fewer pullups are used. XC4000EX Horizontal Longline Switching Characteristic Guidelines Speed Grade] -4 3 -2 1 Units Description TBUF driving a Horizontal Longline | going High or Low to Horizontal Longline going High XC-4028EX or Low, while T is Low. Buffer is constantly active. XC4036EX fF 16.5 13.6 13.2 ns T going Low to Horizontal Longline going from resis- | Toy XC4028EX] 14.7 12.1 11.7 ns tive pull-up or floating High to active Low. TBUF con- XC4036EX J 17.4 14.4 14.0 ns figured as open-drain or active buffer with | = Low. T going High to Horizontal Longline going from Low to | Tpys XC4028EX ns High, pulled up by two resistors. (Note 1) TBUF driving Half a Horizontal Longline | going High or Low to half of a Horizontal Longline go- XC4036EX XC4028EX ing High or Low, while T is Low. Buffer is constantly XC4036EX] 7.3 6.0 5.7 ns active. T going Low to half of a Horizontal Longline going from | Tuox XC4028EX]T 7.2 6.4 5.4 ns resistive pull-up or floating High to active Low. TBUF XC4036EXf 8.2 6.8 6.5 ns configured as open-drain or active buffer with | = Low. T going High to half of a Horizontal Longline going THpua XC4028EX ns from Low to High, pulled up by four resistors. (Note 1) XC4036EX ns Note: These values include a minimum load of one output, spaced as far as possible from the activated pullup(s). Use the static timing analyzer to determine the delay for each destination. XC4000EX Wide Decoder Switching Characteristic Guidelines Speed Grade 4 3 2 1 Units Description Symbol Device Max | Max | Max | Max Full length, two pull-ups, inputs from 1OB I-pins Tware XC4028EX ns XC4036EX ns Full length, two pull-ups, inputs from internal logic Tware. | XC4028EX ns XC4036EX ns Half length, two pull-ups, inputs from IOB I-pins Twao2 XC4028EX ns XC4036EX ns Half length, two pull-ups, inputs from intemal logic Twaoa. | XC4028EX ns XC4036EX ns Notes: These delays are specified from the decoder input to the decoder output. July 30, 1997 (Version 1.2) 87XC4000E and XC4000X Series Fieid Programmabie Gate Arrays XC4000EX CLB Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000EX devices unless otherwise noted. Speed Grade ~4 3 -2 | Units Description Combinatorial Delays F/G inputs to X/Y outputs . . . F/G inputs via H to X/Y outputs Tio 3.8 3.2 2.7 ns F/G inputs via transparent latch to Q outputs =| Tito 3.2 2.7 2.5 ns C inputs via SR/HO via H to X/Y outputs C inputs via H1 via H to X/Y outputs C inputs via DIN/H2 via H to X/Y outputs C inputs via EC, DIN/H2 to YQ, XQ output (bypass) CLB Fast Carry Logic Operand inputs (F1, F2, G1, G4) to COUT Add/Subtract input (F3) to COUT Initialization inputs (F1, F3) to COUT CIN through function generators to X/Y outputs GIN to COUT, bypass function generators Sequential Delays Clock K to Flip-Flop outputs Q Clock K to Latch outputs Q Setup Time before Clock K F/G inputs F/G inputs via H C inputs via HO through H C inputs via H1 through H C inputs via H2 through H C inputs via DIN C inputs via EC C inputs via S/R, going Low (inactive) CIN input via F'/G CIN input via F'/G and H Hold Time after Clock K F/G inputs F/G inputs via H C inputs via SR/HO through H C inputs via H1 through H C inputs via DIN/H2 through H C inputs via DIN/H2 C inputs via EC C inputs via SR, going Low (inactive) Clock Clock High time Clock Low time Set/Reset Direct Width (High) Delay from C inputs via S/R, going High to 0 Global Set/Reset Minimum GSR Pulse Width Delay from GSR input to any Q (XC4028EX) Delay from GSR input to any Q (XC4036EX) Toggle Frequency (Note 1) slooeoa000 Note 1: Maximum flip-flop toggle rate for export control purposes. 88 July 30, 1997 (Version 1.2)$2 XILINX XC4000EX CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines Testing of switching parameters is modeled after testing methods specified by MiL-M-38510/605. Ail devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4Q000EX devices unless otherwise noted. Speed Grade 4 3 2 1 Single Port RAM Units Size | Symbol | Min | Max | Min | Max | Min | Max | Min | Max Write Operation : : 0 Address write cycle time (clock K period) | 16x2 | Twes 11.0 9.0 9.0 ns 32x1 |Twers 11.0 9.0 9.0 ns Clock K pulse width (active edge) 16x2_ | Twes 5.5 45 4.5 ns 32x1 Twets 5.5 4.5 4.5 ns Address setup time before clock K 16x2 | Tass 2.7 2.3 2.2 ns 32x1 Tasts 2.6 2.2 2.2 ns Address hold time after clock K 16x2 | Tans 0 0 0 ns 32x1 Tayts 0 0 0 ns DIN setup time before clock K 16x2 | Toss 24 2.0 2.0 ns 32x1 Tosts 29 2.5 2.5 ns DIN hoid time after clock K 16x2 | Tous 0 0 0 ns 32x1 Touts 0 QO 0 ns WE setup time before clock K 16x2 | Twss 2.3 2.0 2.0 ns 32x11 Twsts 2.1 1.8 1.8 ns WE hold time after clock K 16x2 | Twus 0 0 0 ns 32x11 TwHts 0 0 0 ns Data valid after clock K 16x2_ | Twos 8.2 6.8 6.8 ns 32x1 Twots 10.1 8.4 8.2 ns Notes: Timing for the 16x1 RAM option is identical to 16x2 RAM timing. Applicable Read timing specifications are identical to Level-Sensitive Read timing. Speed Grade 4 3 -2 -1 Dual-Port RAM Units Size | Symbol | Min | Max | Min | Max | Min | Max] Min | Max Write Operation Address write cycie time (clock K period) | 16x1 | Twops 411.0 9.0 ns Clock K pulse width (active edge) 16x1 | Tweps ns Address setup time before clock K 16x1 | Tasps ns Address hold time after clock K 16x1 | Taups ns DIN setup time before clock K 16x1 | Tpsps ns DIN hold time after clock K 16x1 | Touos ns WE setup time before clock K 16x1 | Twsps ns WE hold time after clock K 16x1 | Twrps ns Data valid after clock K 16x1 | Twoos ns Note: Applicable Read timing specifications are identical to Level-Sensitive Read timing. duly 30, 1997 (Version 1.2) 89XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000EX CLB RAM Synchronous (Edge-Triggered) Write Timing T poss DHS Tass ADDRESS | DATA OUT & X6461 XC4000EX CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing WCLK (K) T wsDS WE T s q DSDS DHDS ADDRESS [feos DATA OUT [ae X6474 July 30, 1997 (Version 1.2)$< XILINX XC4000EX CLB RAM Asynchronous (Level-Sensitive) Write and Read Operation Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000EX devices unless otherwise noted. Note: Timing for the 16x1 RAM option is identical to 16x2 RAM timing. Speed Grade -2 1 Units Description | Size | Symbol | Min Min Min Min | Max Write Operation Address write cycle time 16x2 | Twe . . 32x1_ | Twer 10.6 9.2 8.0 ns Write Enable pulse width (High) 16x2 | Twe 5.3 46 4.0 ns 32x1 Twpt 5.3 4.6 4.0 ns Address setup time before WE 16x2 | Tas 2.8 2.4 2.0 ns 32x1_ | Tast 2.9 2.5 2.0 ns Address hoid time after end of WE | 16x2 | Tan 1.7 1.4 1.4 ns 32x1_ | Tan 1.7 1.4 1.4 ns DIN setup time before end of WE 16x2 | Tps 32x1 | Tost DIN hold time after end of WE 16x2 | Tow 32x1 | Tout Read Operation Address read cycle time 16x2 | Taco 32x1 Tact Data valid after address change 16x2 | Tito (no Write Enable) 32x1 | Tino Read Operation, Clocking Data into Filp-Flop Address setup time before clock K | 16x2 | Tick 32x1 | Tick Read During Write Data valid after WE goes active 16x2 | Two (DIN stable before WE) 32x1_ | Twot Data valid after DIN 16x2 | Tpo (DIN changes during WE) 32x1_ | Toot Read During Write, Clocking Data into Flip-Flop WE setup time before clack K 16x2 | Twew 32x1 Twexr Data setup time before clock K 16x2 | Tock 32x1 Tocxt July 30, 1997 (Version 1.2) 91ideas Sorat pia XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000EX CLB RAM Asynchronous (Level-Sensitive) Timing Characteristics Twe ADDRESS / WRITE \~ Tas fr Twe TAH] WRITE ENABLE DATA IN REQUIRED READ WITHOUT WRITE X,Y OUTPUTS READ, CLOCKING DATA INTO FLIP-FLOP I Tick t Tor > CLOCK | TeKo VALID VALID XQ, YQ OUTPUTS {OLD) (NEW) READ DURING WRITE Twe WRITE ENABLE | TDH DATA IN (stable during WE) pe X, Y OUTPUTS VALID am VALID DATA IN (changing during WE) OwD NEW he Too X, Y OUTPUTS VALIO VALIO (PREVIOUS) READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP 1 WP WRITE ENABLE { Twek "} Tock ~ CLOCK [| MTCKO XQ, YQ GUTPUTS. 92 July 30, 1997 (Version 1.2)$< XILINX XC4000EX Pin-to-Pin Output Parameter Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XC4000EX devices unless otherwise noted. XC4000EX Output Flip-Flop, Clock to Out Speed Grade 4 3 -2 -1 Units Description Symbol Device Max Max Max Max Global Low Skew Clock to TTL Tickor | XC4028EX 16.6 13.7 12.4 ns Output (fast) using OFF XC4036EX 17.2 14.1 13.1 ns Global Early Clock to TTL Output (fast) using | Tickeor | XC4028EX 13.1 10.6 10.2 ns OFF XC4036EX 13.3 10.8 10.4 ns OFF = Output Flip Flop XC4000EX Output MUX, Clock to Out Speed Grade 4 3 -2 -1 Units Description Symbol Device Max Max Max Max Global Low Skew Clock to TTL Tpepr XC4028EX 15.9 13.1 11.8 ns Output (fast) using OMUX XC4036EX 16.5 13.5 12.5 ns Global Early Clock to TTL Output (fast) us- | Tpeepr XC4028EX 12.4 10.0 9.6 ns ing OMUX XC4036EX ns OMUX = Output MUX Notes: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible [OB and CLB flip-flops are clocked by the global clock net. Output timing is measured at TTL threshold with 35 pF external capacitive load. Set-up time is measured with the fastest route and the lightest load. Hold time is measured using the farthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer to determine the setup and hold times under given design conditions. XC4000EX Output Level and Slew Rate Adjustments The following table must be used to adjust output parameters and output switching characteristics. July 30, 1997 (Version 1.2) Speed Grade 4 3 2 1 Description Symbol Device Max Max Max Max | Units For TTL output FAST add T+TLoF All Devices 0 0 0 ns For TTL output SLOW add T+tLo All Devices 2.9 2.4 2.4 ns For CMOS FAST output add Teomosor All Devices 1.0 0.8 0.8 ns For CMOS SLOW output add Temoso All Devices 3.0 3.0 ns 93XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000EX Pin-to-Pin Input Parameter Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XC4Q00EX devices unless otherwise noted XC4000EX Global Low Skew Clock, Set-Up and Hold , using 8. clock and IFF (full delay) XC4036EX 8.0 ; 0 clock and IFF (fult delay) XC4036EX 0 = or XC4000EX Global Early Clock, Set-Up and Hold for IFF Input EP 6.5 and IFF (partial delay) XC4036EX 6.5 input Hold using 0 and IFF (partial delay) XC4036EX 0 = or Note: Set-up parameters are for BUFGE #s 3, 4, 7 and 8. Add 1.6 ns for BUFGE #s 1, 2, 5 and 6. XC4000EX Global Early Clock, Set-Up and Hold for FCL Input using clock | Tpgsep 3.4 and FCL (partial delay) XC4036EX 4.4 Hold clock PFHEP X' 0 and FCL (partial delay) XC4036EX 0 Notes: For CMOS output levels, see the Output Level and Siew Rate Adjustments tables on page 10. Setup time is measured with the fastest route and the lightest load. Use the static timing analyzer to determine the setup time under given design conditions. Hold time is measured using the farthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer to determine the setup and hold times under given design conditions. Note:Set-up parameters are for BUFGE #s 3, 4, 7 and 8. Add 1.2 ns for BUFGE #s 1, 2, 5 and 6. XC4000EX Input Threshold and Slew Rate Adjustments The following table must be used to adjust input parameters and input switching characteristics. Speed Grade 4 3 -2 -1 Description Symbol Device Max Max Max Max Units For TTL input add Tru All Devices 0 0 0 ns For CMOS input add Temost All Devices 0.2 ns 94 July 30, 1997 (Version 1.2)$< XILINX XC4000EX IOB Input Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4Q00EX devices unless otherwise noted. Propagation Delays Clock (IK) to !1, 12 (flip-flop) Clock (IK) to 11, 12 (latch enable, active Low) FCL Enable (OK) active edge to 11, l2 (via transparent standard input latch) Global Set/Reset All devices All devices on evICes Speed Grade 4 3 - 1 Units Description Symbol | Device Min Min Min Min Clocks LS z Delay from FCL enable (OK) active edge tolFF | Tox, | Alidevices] 3.2 2.6 2.6 ns clock (IK) active edge Propagation Delays S Max Max Max Pad to |1, [2 Trip Alldevices [2.2 1.9 1.8 Pad to |1, I2 via transparent input latch, no delay | Tey, All devices 3.8 3.2 3.0 Pad to 11, l2 via transparent input latch, TppL; XC4028EX | 13.3 11.1 10.9 partial delay XC4036EX J 14.5 121 11.9 Pad to I1, !2 via transparent input latch, full delay | Teo) XC4028EX J 18.2 15.2 14.9 XC4036EX | 19.4 16.2 15.9 Pad to I, 12 via transparent FCL and input latch, | Tpez All devices 5.3 4.4 42 ns no delay Pad to I1, 12 via transparent FCL and input latch, | Tppppy | XC4028EX] 13.6 11.3 11.1 ns partial delay XC4036EX ns ns Minimum GSR Pulse Width Turw | Alldevices] 13.0 | 11.5 | 11.5 ns Delay from GSR input to any Q Trri XC4028EX | 22.8 19.0 19.0 ns Delay from GSR input to any Q Tari XC4036EX J 24.0 21.0 21.0 ns FCL = Fast Capture Latch, IFF = Input Flip-Flop or Latch ; u Notes: For CMOS output levels, see the Output Level and Slew Rate Adjustments table on page 10. For setup and hold times with respect to the clock input pin, see the Giobal Low Skew Clock and Global Early Clock Set-up and Hold tables on page 11. 95 July 30, 1997 (Version 1.2)XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000EX IOB Input Switching Characteristic Guidelines (Continued) Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000EX devices unless otherwise noted. Speed Grade 4 3 2 A Units Setup Times (TTL or CMOS Inputs) Clock Enable (EC) to Clock (IK) Description Symbol Device Min Min Min Min Setup Times S ae Pad to Clock (JK), no delay Trick All devices 2.5 2.0 2.0 ns Pad to Clock (IK), partial delay Tpickp XC4028EX 10.8 9.0 9.0 ns XC4036EX 12.0 10.0 10.0 ns Pad to Clock (IK), full delay Tricxp XC4028EX 15.7 13.1 13.1 ns XC4036EX 16.9 14.1 14.1 ns Pad to Clock (IK), via transparent Fast | Tpickr All devices 3.9 3.3 3.3 ns Capture Latch, no delay Pad to Clock (IK), via transparent Fast | Tpickrp | XC4028EX 12.3 10.2 10.2 ns Capture Latch, partial delay XC4036EX 13.5 11.2 11.2 ns Pad to Fast Capture Latch Enable (OK), | Tpock All devices 0.8 0.7 0.7 ns no delay Pad to Fast Capture Latch Enable (OK), |Tpockp | XC4028EX 9.1 partial delay XC4036EX 10.3 Hold Times All devices | 0.3 Notes: For CMOS output levels, see the Output Level and Slew Rate Adjustments table on page 10. Pad to Clock (IK), no delay Tikes All devices 0 partial delay Tikpip All devices 0 full delay Tikpip All devices 0 Pad to Clock (IK) via transparent Fast Capture Latch, no delay TikFPt All devices 0 0 0 ns partial delay TikFPIP All devices 0 0 0 ns full delay TikFPip All devices 0 0 0 ns Clock Enable (EC) to Clock (IK), no delay Tikec All devices 0 0 0 ns partial delay Tikecp All devices 0 0 0 ns full delay Tikecp All devices 0 0 0 ns Pad to Fast Capture Latch Enable (Ok), no delay Top! All devices 0 0 ns partial delay Toxpip All devices 0 0 ns For setup and hold times with respect to the clock input pin, see the Global Low Skew Clock and Global Early Clock Set-up and Hold tables on page 11. July 30, 1997 (Version 1.2)$< XILINX XC4000EX I!OB Output Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless otherwise noted. Values apply to all XC4000EX devices unless otherwise noted. Speed Grade -4 3 -2 1 Description Symbol! | Min | Max | Min | Max | Min | Max] Min Propagation Delays Clock (OK) to Pad Output (0) to Pad . 3-state to Pad hi-Z (stew-rate independent) Trsyz 49 44 41 ns 3-state to Pad active and valid TTsone 6.2 5.2 5.0 ns Output MUX Select (OK) to Pad Toxrpr 6.7 5.6 5.4 ns Fast Path Output MUX Input (EC) to Pad Toerpr 6.2 51 5.0 ns Slowest Path Output MUX tnput (O) to Pad Setup and Hold Times Output (O) to clock (OK) setup time Output (O) to clock (OK) hold time Clock Enable (EC) to clock (OK) setup Tecox Clock Enable (EC) to clock (OK) hold Toxec Clock Clock High Clock Low Global Set/Reset Minimum GSR pulse width Delay from GSR input to any Pad (XC4028EX) Delay from GSR input to any Pad (XC4036EX) | Taro 31.4 Units Oo COC Sf ooo; 0 0 ns 0 11.5 11.5 25.2 25.0 27.2 27.0 ns Notes: Output timing is measured at TTL threshold, with 35pF external capacitive loads. For CMOS output levels, see the Output Level and Slew Rate Adjustments table on page 10 July 30, 1997 (Version 1.2) 97XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000E Switching Characteristics Definition of Terms In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final. XC4000E Absolute Maximum Ratings Symbol Description Value Units Veco Supply voltage relative to GND -0.5 to +7.0 Vv Vin Input voltage relative to GND (Note 1) ; -0.5 to Vog +0.5 Vv Vig Voltage applied to 3-state output (Note 1) -0.5 to Ver +0.5 Vv Tste Storage temperature (ambient) -65 to +150 C TsoL Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 C Ty Junction temperature Ceramic packages +150 C Plastic packages +125 C Note 1: Maximum DC overshoot or undershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V ar overshoot to Vcc + 2.0 V, provided this over- or undershoot jasts less than 20 ns. Note 2: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. XC4000E Recommended Operating Conditions Symbol Description Min Max | Units Vec Supply voltage relative to GND, Ty = -0 C to +85C Commercial 4.75 .25 Vv Supply voltage relative to GND, T, = -40C to +100C _| Industrial 45 5.5 Vv Supply voltage relative to GND, Tc = -55C to+125C =| Military 45 5.5 Vv Vin High-ievel input voltage TTL inputs 2.0 Voc V CMOS inputs 70% 100% | Voc Vit Low-level input voltage TTL inputs 0 0.8 Vv CMOS inputs 0 20% Veco Tin Input signal transition time 250 ns Note: At junction samperatures above those listed as Recommended Operating Conditions, all delay parameters increase by 0.35% per C. Input and output Measurement thresholds are: 1.5V for TTL and 2.5V for CMOS. 1. Notwithstanding the definition of the above terms, all specifications are subject to change without notice. 98 July 30, 1997 (Version 1.2)XC4000E DC Characteristics Over Operating Conditions Symbol Description Min Max | Units Von High-level output voltage @ Ip, = -4.0MA, Veco min TTL outputs 2.4 Vv High-ievel output voltage @ Ip, = -1.0MA, Voc min CMOS outputs Voc-0.5 v Voi Low-level output voitage @ Io, = 12.0MA, Voc min TTL outputs 0.4 Vv (Note 1) CMOS outputs 0.4 v loco Quiescent FPGA supply current (Note 2) Commercial 3.0 mA Industrial 6.0 mA Military 6.0 mA I Input or output leakage current -10 +10 pA Cin Input capacitance (sample tested) PQFP and MQFP 10 pF packages Other packages 16 pF laine Pad pull-up (when selected) @ Vy = OV (sample tested) -0.02 -0.25 mA IRL Horizontal Longline pull-up (when selected) @ logic Low 0.2 2.5 mA Note 1: With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins. Note 2: With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the FPGA configured with a MakeBits Tie option. * Characterized Only. XC4000E Global Buffer Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where ail accessible IOB and CLB flip-flops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, refiecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simuiation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature) Speed Grade 4 3 -2 -1 Description Symbol Device Max Max Max Max Units From pad through Tee XC4003E 7.0 4.7 Primary buffer, XC4005E 7.0 47 to any clock K XC4006E 7.5 5.3 XC4008E 8.0 6.1 XC4010E 11.0 6.3 XC4013E 11.5 6.8 XC4020E 12.0 7.0 XC4025E 12.5 7.2 From pad through Tsg XC4003E 75 5.2 Secondary buffer, XC4005E 7.5 5.2 to any clock K XC4006E 8.0 5.8 XC4008E 8.5 6.6 XC4010E 11.5 6.8 XC4013E 12.0 7.3 XC4020E 12.5 7.5 XC4025E 13.0 7.7 July 30, 1997 (Version 1.2) 99Bele XCA000E and XC4000X Series Field Programmabie Gate Arrays XC4000E Horizontal Longline Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. The following guidelines reflect worst-case values over the recommended operating conditions. Speed Grade 4 Description Max TBUF driving a Horizontal Longline (LL): [os ae | going High or Low to LL going High or | Tio; XC4003E Low, while T is Low. XCAnoCE Buffer is constantly active. XC4008E (Note1) XC4010E 8.0 XC4013E 9.0 XC4020E 10.0 XC4025E 11.0 | going Low to LL going from resistive Tiog =| XC4003E 5.0 pull-up High to active Low. er Cacoee ee TBUF configured as open-drain. XC4008E 84 XC4010E 10.5 (Note1) XC4013E 11.0 XC4020E 12.0 XC4025E 12.0 T going Low to LL going from resistive Ton XC4003E 5.5 pull-up or floating High to active Low Gaooce zo TBUF configured as open-drain or active XC4008E 80 buffer with | = Low. XC4010E 8.5 XC4013E 87 XC4020E 11.0 (Note1) XC4025E 11.0 T going High to TBUF going inactive, Torr | All devices 18 not driving LL T going High to LL going from Low to Tpus XAO0SE 20.0 14.0 14.0 ' 20 ns i i i A005E A . . .! ns High, pulled up by a single resistor. XC4006E 250 18.0 18.0 160 ns XC4008E 27.0 20.0 20.0 16.0 ns (Note 1) XC4010E 29.0 22.0 22.0 18.0 ns XC4013E 32.0 26.0 26.0 21.0 ns XC4020E 35.0 32.5 32.5 26.0 ns XC4025E 42.0 39.1 39.1 - ns T going High to LL going from Low to Tpur x CAOOSE 20 7.0 60 54 ns | i 400! . . . . ns High, pulled up by two resistors. XCAD06E 415 9.0 77 65 ns XC4008E 12.5 10.0 8.5 75 ns (Note1) XC4010E 13.5 11.0 9.4 8.0 ns XC4013E 15.0 13.0 11.7 9.4 ns XC4020E 16.0 14.8 14.8 10.5 ns XC4025E 18.0 16.5 16.5 = ns Note 1: | These values include a minimum load. Use the static timing analyzer to determine the delay for each destination. 100 duly 30, 1997 (Version 1.2)XC4000E Wide Decoder Switching Characteristic Guidelines $< XILINX Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. The following guidelines reflect worst-case values over the recommended operating conditions. Notes: These delays are specified from the decoder input to the decoder output. Speed Grade 4 3 -2 -1 Description Symbol Device Max Max Max Max Units Full length, both pull-ups, Twar XC4003E 9.2 5.0 5.0 43 ns inputs from IOB I-pins XC4005E 9.5 6.0 6.0 5.1 ns XC4006E 12.0 7.0 7.0 6.0 ns XC4008E 12.5 8.0 8.0 6.5 ns XC4010E 15.0 9.0 9.0 7.5 ns XC4013E 16.0 11.0 11.0 8.6 ns XC4020E 17.0 13.9 13.9 10.1 ns XC4025E 18.0 16.9 16.9 Full length, both pull-ups, TwarL | XC4003E 12.0 7.0 7.0 inputs from internal logic XC4005E 12.5 8.0 8.0 XC4006E 14.0 9.0 9.0 XC4008E 16.0 10.0 10.0 XC4010E 18.0 11.0 11.0 XC4013E 19.0 13.0 13.0 XC4020E 20.0 15.5 16.5 XC4025E 21.0 18.9 18.9 Haif length, one pull-up, Twao XC4003E 10.5 6.0 6.0 inputs from IOB I-pins XC4005E 10.5 7.0 7.0 XC4006E 13.5 8.0 8.0 XC4008E 14.0 9.0 9.0 XC4010E 16.0 10.0 10.0 XC4013E 17.0 12.0 12.0 XC4020E 18.0 15.0 15.0 XC4025E 19.0 17.6 17.6 Half length, one pull-up, TwaoL XC4003E 12.0 8.0 8.0 inputs from internal logic XC4005E 12.5 9.0 9.0 XC4006E 14.0 10.0 10.0 XC4008E 16.0 11.0 11.0 XC4010E 18.0 12.0 12.0 XC4013E 19.0 14.0 14.0 XC4020E 20.0 16.8 16.8 XC4025E 21.0 19.6 19.6 Fewer than the specified number of pullup resistors can be used, if desired. Using fewer pullups reduces power consumption but increases delays. Use the static timing analyzer to determine delays if fewer pullups are used. July 30, 1997 (Version 1.2) 101XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000E CLB Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. Speed Grade 2 1 Description Min Combinatorial Delays Symbol Units Cin input via F/G Cin input via F/G and H F/G inputs to X/Y outputs Tito 2.7 2.0 1.6 13 ns F/G inputs via H to X/Y outputs Tino 4.7 4.3 2.7 2.2 ns C inputs via SR through H to X/Y outputs TuHoo 41 3.3 2.4 1.9 ns C inputs via H to X/Y outputs THH10 3.7 3.6 2.2 1.6 ns C inputs via DIN through H to X/Y outputs | TrHy20 45 3.6 2.6 1.9 ns CLB Fast Carry Logic oS a : ae ae Operand inputs (F1, F2, G1, G4) to COUT | Topcy 3.2 2.6 2.1 1.7 ns Add/Subtract input (F3) to COUT 2.5 ns Initialization inputs (F1, F3) to COUT 1.2 ns CIN through function generators to 1.8 ns X/Y outputs CIN to COUT, bypass function generators 0.5 ns Sequential Delays a I : cela Clock K to outputs Q 1.9 ns Setup Time before Clock K ee F/G inputs 1.8 ns F/G inputs via H 2.8 ns C inputs via HO through H 2.4 ns C inputs via H1 through H 2.1 ns C inputs via H2 through H 2.5 ns C inputs via DIN 1.0 ns C inputs via EC 2.0 ns C inputs via S/R, going Low (inactive) 1.5 ns 102 July 30, 1997 (Version 1.2)$< XILINX XC4000E CLB Switching Characteristic Guidelines (continued) Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to- date information, use the vaiues provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. Speed Grade ~4 3 -2 -1 Units Description Symbol n Hold Time after Clock K ee F/G inputs Tox 0 0 0 0 ns F/G inputs via H Tekin 0 0 0 0 ns C inputs via HO through H TeKHHOo 0 0 0 0 ns C inputs via H1 through H ToKHHt 0 0 0 0 ns C inputs via H2 through H TexHHe 0 0 0 0 ns C inputs via DIN Texoi 0 0 0 0 ns C inputs via EC Toxec 0 0 0 0 ns C inputs via SR, going Low (inactive) Texr 0 0 0 0 ns Clock : De Clock High time . . . ns Clock Low time . ns Set/Reset Direct co Te Width (High) . . . . ns Delay from C inputs via S/R, . . . . ns going High to Q Master Set/Reset (Note 1) Width (High or Low) Twaw | 13.0 11.5 115 10.0 ns Delay from Global Set/Reset nettoQ | Tura 23.0 18.7 17.4 15.0 | ns Global Set/Reset inactive to first Tmrk active clock K edge Toggle Frequency (Note 2) Frog 111 125 125 Note 1: Timing is based on the XC4005E. For other devices see the XACT timing calculator. Note 2: Export Control Max. flip-flop toggle rate. July 30, 1997 (Version 1.2) 103XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. . Speed Grade -4 -3 -2 -1 Single Port RAM Units Size | Symbol Write Operation - : Address write cycle time (clock K period) Twes . 32x1 | Twers | 15.0 14.4 11.6 8.0 ns Clock K pulse width (active edge) 16x2 | Twes 7.5 |1ms| 7.2 |1ms| 5.8 |}1ms] 4.0 ns 32x1 | Twets | 7.5 |1ms| 7.2 |ims| 5.8 |1msf 4.0 ns Address setup time before clock K 16x2 | Tass 28 2.4 2.0 15 ns 32x1 | Tasts 2.8 2.4 2.0 1.5 ns Address hold time after clock K 16x2 | Tas 0 0 0 0 ns 32x1 TaHTs 0 0 0 0 ns DIN setup time before clock K 16x2 | Toss 3.5 3.2 2.7 1.5 ns 32x11 Tpsts 2.5 1.9 1.7 15 ns DIN hold time after clock K 16x2 | Tors 0 0 0 0 ns 32x1 Touts 0 0 0 0 ns WE setup time before clock K 16x2 | Twss 2.2 2.0 1.6 1.5 ns 32x1 | Twsts | 2.2 2.0 1.6 1.5 ns WE hold time after clock K 16x2 | Twos 0 0 0 32x1 Twrts 0 0 0 Data valid after clock K 16x2 | Twos 10.3 8.8 32x11 Twors 11.6 10.3 Notes: Timing for the 16x1 RAM option is identical to 16x2 RAM timing. Applicable Read timing specifications are identical to Levei-Sensitive Read timing. Speed Grade 4 3 -2 | Dual-Port RAM Units Size | Symbol | Min | Max | Min | Max | Min | Max} Min | Max Write Operation L : Address write cycle time (clock K period) | 16x1 | Tweps | 15.0 9.0 11.6 8.0 ns Clock K pulse width (active edge) 16x1 | Tweps ims] 45 | ims | 5.8 |1ms] 4.0 ns Address setup time before clock K 16x1 | Tasps 7.5 2.5 2.1 1.5 ns Address hold time after clock K 16x1 | Taps 2.8 0 0 0 ns DIN setup time before clock K 16x1 | Tosps 0 2.5 1.6 15 ns DIN hold time after clock K 16x1 | Toxos 2.2 0 0 0 ns WE setup time before clock K 16x1 | Twsps 0 1.8 1.6 15 ns WE hold time after clock K 16x1|TwHos | 2.2 0 0 0 ns Data valid after clock K 16x1 |Twops | 0.3 | 10.0 7.8 7.0 6.5 ns Note: Applicable Read timing specifications are identical to Level-Sensitive Read timing. 104 July 30, 1997 (Version 1.2)$= XILINX XC4000E CLB RAM Synchronous (Edge-Triggered) Write Timing Sen . WCLK (K) } T wss WE T, Tors DSS ADDRESS DATA OUT X6461 XC4000E CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing ADDRESS DATA OUT X6474 July 30, 1997 (Version 1.2) 105XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. Read Operation, Clocking Data Into Flip-Flop Speed Grade 4 -2 -1 Units Description | Size | Symbol Write Operation Address write cycle time 16x2 | Two 8.0 8.0 8.0 8.0 ns 32x1_ | Twer 8.0 8.0 8.0 8.0 ns Write Enable pulse width (High) 16x2 | Twp 4.0 4.0 4.0 4.0 ns 32x1_ | Twet 4.0 40 4.0 4.0 ns Address setup time before WE 16x2 | Tas 2.0 2.0 2.0 2.0 ns 32x1_ | Tast 2.0 2.0 2.0 2.0 ns Address hold time after endof WE | 16x2 | Tay 2.5 2.0 2.0 2.0 ns 32x1 | Tant 2.0 2.0 2.0 2.0 ns DIN setup time before end of WE 16x2 | Tps 4.0 2.2 0.8 0.8 ns 32x1_ | Tost 5.0 2.2 0.8 0.8 ns DIN hold time after end of WE 16x2 | Tox 32x1 Tout Read Operation Address read cycle time 16x2 | Tac 32x11 Tret Data valid after address change 16x2_ | Tio 2.7 1.8 1.6 1.6 ns (no Write Enable) 32x1 | Tio 4.7 3.2 2.7 2.7 ns Read During Write, Clocking Data into Fil WE setup time before clock K 32x1 16x2 Address setup time before clock K 16x2 | Tick . . . . 32x1 | Tuck 6.1 4.6 3.9 3.9 ns Read During Write Data valid after WE goes active (DIN | 16x2 | Two 10.0 6.0 4.9 4.9 ns stable before WE) 32x1 | Twor 12.0 7.3 5.6 5.6 ns Data valid after DIN 16x2 (DIN changes during WE) 32x1 Data setup time before clock K 32x1 16x2 Note: Timing for the 16x1 RAM option is identical to 16x2 RAM timing. 106 July 30, 1997 (Version 1.2)$< XILINX XC4000E CLB Level-Sensitive RAM Timing Characteristics Two ADDRESS WRITE WRITE ENABLE DATA IN REQUIRED READ WITHOUT WRITE -t TILO X.Y OUTPUTS VALID VALID ZZ READ, CLOCKING DATA INTO FLIP-FLOP Tick t Too >| CLOCK | TeKo VALID VALID XQ, YO OUTPUTS (OLD (NEW) READ DURING WRITE Twe WRITE ENABLE | TDH DATAIN (stable during WE) pT i X, Y OUTPUTS VALID VALID DATA IN (changing during WE) OLD NEW VALID XY OUTPUTS (PREVIOUS) READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP 7 WP WRITE ENABLE TWCK Tock | coe | _ ToKo XQ, YQ OUTPUTS July 30, 1997 (Version 1.2) 107XC4000E and XC4000X Series Fleld Programmable Gate Arrays XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL. /O) Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XC4000E devices unless otherwise noted. Speed Grade 4 -3 -2 -1 Units Description Symbol Device Global Clock to Output Tickor XC4003E 12.5 10.2 8.7 5.8 ns ; XC4005E 14.0 10.7 9.1 6.2 ns (fast) using OFF XC4006E 14.5 10.7 9.1 6.4 ns XC4008E 15.0 10.8 9.2 6.6 ns Tro cr |? | ~~ ((Max) XC4010E 16.0 10.9 9.3 6.8 ns >_f>____-+ : XC4013E 16.5 11,0 9.4 7.2 ns Global Delay : XC4020E 17.0 11.0 10.2 74 ns sate XC4025E 17.0 12.6 10.8 - ns Global Clock to Output Ticko XC4003E 16.5 14.0 11.5 7.8 ns (slew-limited) using OFF xcsoose | tes | iar | 20 ea | ons XC4008E 19.0 14.8 12.1 8.6 ns Tro or | (Max) XC4010E 20.0 14.9 12.2 8.8 ns o_p>____] : XC4013E 20.5 15.0 12.8 9.2 ns Global Goc:4e-Outpul Delay XC4020E 21.0 15.4 12.8 9.4 ns wean XC4025E 21.0 15.3 13.0 - ns Input Setup Time, using IFF Tpsur xo#003e 2.5 23 28 i 8 ns (no delay) XC4006E 1.9 1.0 1.0 0.6 ns oI , XC4008E 1.4 0.6 0.6 0.2 ns int - (Min) XC4010E 1.0 0.2 0.2 0 ns oeeue Tra XC4013E 0.5 0 0 0 ns time | C>->-~ XC4020E 0 0 0 0 ns Time = XC4025E 0 0 0 - ns Input Hold Time, using IFF TpHF XC4003E 40 49 40 1 8 ns 4005 4, . - . ns (no delay) XC4006E 5.0 47 47 2.0 ns D> ; XC4008E 6.0 5.1 5.1 2.5 ns ; (Min) XC4010E 6.0 55 5.5 25 ng oat Tre XC4013E 7.0 6.5 5.5 3.0 ns tine | C>--> XC4020E 75 6.7 5.7 3.5 ns = XC4025E 8.0 7.0 5.9 ~ ns Input Setup Time, using IFF Trsu CAE 85 70 80 50 ns (with delay) XC4006E 8.5 7.0 6.0 5.0 ng ; XC4008E 8.5 7.0 6.0 5.0 ns meh Cd (Min) XC4010E 85 7.0 6.0 5.0 ns sete Tro ad XC4013E 8.5 7.0 6.0 5.0 ns wee) Oy oS XC4020E 9.5 7.0 68 5.0 ns _ XC4025E 9.5 7.6 68 - ns Input Hold Time, using IFF Tey rCageE 8 9 ns o ns (with delay) XC4006E 0 0 0 0 ns > ; XC4008E oO 0 0 0 ns iret (Min) XC4010E 0 0 0 0 ns Set-Up Tra ad XC4013E 0 0 0 o ns Hod) oS XC4020E 0 0 0 0 ns me = XC4025E 0 0 0 ~ ns OFF = Output Flip-Flop IFF = input Flip-Flop or Latch 108 July 30, 1997 (Version 1.2)UE SR intra ris mica tee nine kona $2 XILINX XC4000E IOB Input Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. Ail devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XC4000E devices unless otherwise noted. Speed Grade ~4 3 -2 1 Units Description Min | Max n Propagation Delays (TTL Inputs) Pad to 11, 12 Pad to I1, I2 via transparent Teip All devices 3.0 2.5 2.0 1.4 ns latch, no delay with delay Tex All devices 4.8 3.6 3.6 2.8 ns Teou XC4003E 10.4 9.3 6.9 6.4 ns XC4005E 10.8 9.6 7.4 6.5 ns XC4006E 10.8 10.2 8.1 6.9 ns XC4008E 10.8 10.6 8.2 7.0 ns XC4010E 11.0 10.8 8.3 7.3 ns XC4013E 11.4 11.2 9.8 8.4 ns XC4020E 13.8 12.4 11.6 9.0 ns XC4025E 13.8 13.7 12.4 - ns Propagation Delays (CMOS Inputs : cee Pad to I, i2 Tpipc |All devices 5.5 41 3.7 1.9 ns Pad to I1, 12 via transparent latch, no delay Tpric |All devices 8.8 6.8 6.2 3.3 ns with delay Tepvic | XC4003E 12.4 11.0 6.9 ns XC4005E 13.2 11.9 7.0 ns XC4006E 13.4 12.1 7.4 ns XC4008E 13.8 12.4 7.4 ns XC4010E 14.0 12.6 7.8 ns XC4013E 14.4 13.0 9.0 ns XC4020E 15.6 14.0 9.5 ns XC4025E ns Propagation Delays [eee ae Clock (IK) to I, {2 (flip-flop) Tixrt All devices ns Clock (IK) to H1, 12 (latch enable, active Low) = [Tix1) All devices 6.2 4.0 3.9 ns Hold Times (Note 1) La, eS Pad to Clock (IK), no delay Tip; |All devices} 0 0 0 ns with delay Tixpip |All devices} 0 0 0 ns Clock Enable (EC) to Clock (IK), no delay Tixec |All devices] 1.5 1.6 0.9 0 ns with delay Tikecp |All devices| 0 0 0 0 ns Note 1: Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. Note 2: __ Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull- up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. July 30, 1997 (Version 1.2) 109XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000E IOB Input Switching Characteristic Guidelines (continued) Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4Q00E devices unless otherwise noted. Speed Grade 4 -3 -2 -1 Description Max Unite Setup Times (TTL inputs) ee / Pad to Clock (IK), nodelay | Tpicx |All devices | 4.0 2.6 2.0 1.5 ns with delay Tpickp XC4003E 10.9 8.2 6.0 48 ns XC4005E | 10.9 8.7 6.1 5.1 ns XC4006E | 10.9 9.2 6.2 5.8 ns XC4008E | 11.1 9.6 6.3 5.8 ns XC4010E | 11.3 9.8 6.4 6.0 ns XC4013E | 11.8 10.2 7.9 7.6 ns XC4020E | 14.0 11.4 9.4 8.2 ns XC4025E Setup Time (CMOS Inputs) | ae Pad to Clock (IK), no delay PICKC devices | 6.0 . ns with delay Trickoc XC4003E | 12.0 5.3 ns XC4005E | 12.0 5.6 ns XC4006E | 12.3 6.3 ns XC4008E | 12.8 6.3 ns XC4010E | 13.0 6.5 ns XC4013E | 13.5 . 7.9 ns XC4020E | 16.0 12.1 8.1 ns XC4025E Clock Enable (EC) to Clock (IK), no delay Tecix | All devices| 3.5 2.5 2.1 1.5 ns with delay Tecikp | XC4003E | 10.4 8.1 4.3 4.3 ns XC4005E | 10.4 8.5 5.6 5.0 ns XC4006E | 10.4 9.1 6.7 6.0 ns XC4008E | 10.4 9.5 6.9 6.0 ns XC4010E | 10.7 9.7 7.1 6.5 ns XC4013E | 11.1 10.1 9.0 8.0 ns XC4020E | 14.0 11.3 10.6 9.0 ns XC4025E | 14.0 11.3 11.0 - ns Global Set/Reset (Note 3) |. oe Delay from GSR net Trai 12.0 7.8 6.8 6.8 ns through Q to 11, 12 GSR width Twrw 13.0 11.5 11.5 10.0 ns GSR inactive to first active Twrt Clock (IK) edge Note 1: Input pad setup and hoid times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull- up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. Note 3: Timing is based on the XC4005E. For other devices see the XACT timing calculator. 110 July 30, 1997 (Version 1.2)hy: aback pte $< XILINX XC4000E IOB Output Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MiL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. Speed Grade 4 3 -2 -1 unit Description Symbol | Min | Max | Min | Max | Min | Max | Min] Max | -" Br tion Delays . re Se ole - - - - (TTL Output Leveis) Clock (OK) to Pad, fast ToKpor 75 6.5 4.5 3.0 ns slew-rate limited! Toxpos 11.5 9.5 7.0 5.0 ns Output (O) to Pad, fast Topr 8.0 5.5 4.8 3.2 ns slew-rate limited; Tops 12.0 8.5 7.3 5.2 ns 3-state to Pad hi-Z Trsuz 5.0 4.2 3.8 3.0 ns (slew-rate independent) 3-state to Pad active and valid, fast TTSONF 9.7 8.1 7.3 6.8 ns slew-rate limited | _T- 13.7 11.1 9.8 8.8 ns Propagation Delays : a (CMOS Output Levels) Clock (OK) to Pad, fast Toxporc 9.5 78 7.0 4.0 ns slew-rate limited Toxposc 13.5 11.6 10.4 7.0 ns Output (O) to Pad, fast Toprc 10.0 9.7 8.7 4.0 ns slew-rate limited| Topsc 14.0 13.4 12.1 6.0 ns 3-state to Pad hi-Z Trsyzc 5.2 4.3 3.9 3.9 ns (slew-rate independent) 3-state to Pad active and valid, fast TTSONFC 9.1 7.6 6.8 slew-rate limited| Trgonsc 13.1 11.4 10.2 Note 1: Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the affect of capacitive loads on ground bounce, see the Additional XC4000 Data section of the Programmable Logic Data Book. Note 2: __ Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull- up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. July 30, 1997 (Version 1.2) 111XCAQQOE and XC4000X Series Field Programmable Gate Arrays XC4000E IOB Output Switching Characteristic Guidelines (continued) Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless otherwise noted. Values apply to all XC4000E devices unless otherwise noted. Speed Grade -4 3 -2 1 Units Description Setup and Hold Output (O) to clock (OK) setup time Output (O) to clock (OK) hold time Clock Enable (EC) to clock (OK) setup Clock Enable (EC) to clock (OK) hold Clock Clock High Clock Low Global Set/Reset (Note 3) : Delay from GSR net to Pad Treo 15.0 11.8 8.7 7.0 ns GSR width Turw 13.0 11.5 11.5 ns GSR inactive to first active _Twro clock (OK) edge Note 1: Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall times are approximately two times ionger than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the Additional XC4000 Data section of the Programmable Logic Data Book. Note 2: __ Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull- up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. Note 3: Timing is based on the XC4005E. For other devices see the XACT timing calculator. 112 July 30, 1997 (Version 1.2)$= XILINX XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to- date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. Speed Grade 4 3 -2 1 Units Description Symboi | Min Max Min Max Min Max Min Max n Setup and Hold a Input (TDI) to clock (TCK) Trpitcx | 30.0 30.0 30.0 20.0 ns setup time Input (TD}) to clock (TCK) TreKTbI 0 0 0 0 ns hold time Input (TMS) to clock (TCK) | Trustcx | 15.0 15.0 15.0 10.0 ns setup time Input (TMS) to clock (TCK) =| Trcxtms 0 0 0 0 ns hold time Propagation Delay Clock (TCK) to Pad (TDO) Clock Clock (TCK) High . . . . Clock (TCK) Low Trek 5.0 5.0 5.0 4.0 ns Fuax (MHz) Fax 15.0 15.0 15.0 25.0 ns Note 1: Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. Note 2: Output timing is measured at pin threshold, with 50pF external capacitive toads (incl. test fixture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the Additional XC4000 Data section of the Programmable Logic Data Book. Note 3: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull- up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. July 30, 1997 (Version 1.2) 113XC4000E and XC4000X Serles Field Programmable Gate Arrays Device-Specific Pinout Tables Device-specific tables include all packages for each XC4000 and XC4000X Series device. They follow the pad locations around the die, and include boundary scan register locations.. Pin Locations for XC4003E Devices Name PC84 | PQ100 | VQ100 | PG120 | Bndry Scan PC84 | PQ100 | VQ100 | PG120 | Bndry Scan P3 32 P91 35 38 4 44 47 50 53 56 59 Pad J12 Lig K1t uit M1 NI M10 1 62 65 vo vo va vo 5/5/97 Additional XC4003E Package Pins PG120 At 5/5/97 114 July 30, 1997 (Version 1.2)+ HE He eh wee eet $< XILINX Pin Locations for XC4005E/XL Devices The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. XC4005EXL | PC | PG] VQ | TQ | PG | PQ | PQ [Bndry Pad Name 84 | 100 144 160 | 208 | Scan Pad Name 84 | 100 | 100++| 144 | 156+ | 160 | 208 | Scan GND - : - | P45 | Fi4 | P51 | Pe7 | - 29 PI vO - - - | P46 | Fi5 | P52 | Ps | 193 vO : : - | Pa7 | E16 | P53 | P69 | 196 86 vO Pas | P34 | P3i | Pas | Fie | P54 | P70 | 199 87 vO P39 | P35 | P32 | Pao | Gia | P55 | P71 | 202 vO - | P36 | Pas | P50 | Gis | P56 | P74 | 205 vO - | P37 | P34 | P51 | Gie | P57 | P75 | 208 i) P40 | P3s | Pas | P52 | His | P58 | P76 | 211 1/0 (INTT) P41 | P39 | P36 | P53 | H15 | P59 | P77 | 214 VCC Paz | P40 | P37 | P54 [| Hi4 | P60 | P7a | - GND P43 [P41 | Pas | P55 | Ji4 | P61 | P79 | - vO P44 | P42 | P39 | P56 | J15 | Pee | P80 | 217 vO P45 | P43 | P40 | P57 | v16 | Pea | Pai | 220 vO - | P44 | P41 | P58 | Ki6 | Ped [ Paz | 223 vO - | P45 | P42 | P59 | K15 | Pes | Pas | 226 : vO P46 | P46 | P43 | Peo | Ki4 | P66 | P86 | 229 vO P47 | P47 | Paa {| Pei | Lie | Pe7 | Pa7 | 232 vO = - - | Pe2 | M16 | Pea | Pas | 235 vO - - - | Pea | Lis | Peg | Pag | 238 GND = - - | P64] Lia | P70 [ P90 | - vO [| P48 | Pas | P45 | Pes | P16 | P73 | P95 | 241 vO Pag | P49 | Pas | Pes | mi4 | P74 | P96 | 244 V0 - - - | Pe7 | NiS | P75 { P97 | 247 vO = - - | Pes | P15 | P76 | Pos | 250 vO P50 | P50 | P47 | P69 | Ni4 | P77 | P99 | 253 VO, SGCK3 ft, P51 | P5t | P4a | P70 | Ri6 | P78 [P100| 256 GCK4 tt GND P52 | P52 | P49 | P71 | Pi4 | P79 [Pioi| - DONE ps3 | P53 | P50 | P72 | R15 | Peo [Pios| - VCC P54 | P54 | P51 | P73 | P13 | Pei [P106/ - [PROGRAM pss | P55 | P52 | P74 | R14 | Pe2 [P1o8s| - vO (07) P56 | P56 | P53 | P75 | T16 | P83 |P109| 259 VO, PGCK3t, P57 | P57 | P54 | P76 | T15 | P84 [P110| 262 GCKStt vO . - - | P77 | R13 | Pes [Pitt | 265 vO 5 > - | P78 | Pi2 | Pas [Pit2/ 268 VO (D6) P58 | P58 | P55 | P79 | Tia | P87 [P113| 271 vO - | P59 | P56 | Pao | T13 | Pes [P114[ 274 GND 5 - - | Pei | Pit | Pot [Ptig{ - vO - - - | Pa2 | R11 | P92 |P120[ 277 | vO - = - | Pas | T11 | P93 |Pi2t| 280 ; O (D5) Psg | Peo | P57 | Pa4 | T10 | P94 | P1221] 283 | 0 (C50) Peo | P61 P58 | P85 | P10 | Pes |P123| 286 i) - | Pe2 P59 | Pas | R10 | P96 |Pi26| 289 vO - | P63} Peo | Pa7 | T9 | Po7 |P127| 202 VO (D4) P61 | Pea | Pet | Pes | AS | Pes |Pi28] 295 vO P62 | P65 | P62 | Peg | P9 | P99 [P1209] 298 VCC Pes | Pes | P63 | P90 | RB |Pico|Pi30/ - GND P64 | P67 | Pe4 | P91 | Pa [Pi01[P131| - VO (D3) P65 | Pes | Pas | Po2 | Ta |P102|P132] 301 VO (AS) Pe | Peo | Pes | P93 | Ty |P103/Pi33| 304 vo - | P70 | Pe7 | P94 | T |P104|P134| 307 VO - : - | P95 | R7_ [P105/P135{ 310 VO (D2) P67 | P71 | Pes | P96 | P7 | P106/P138/ 313 vO Pes | P72 | Peg | P97 | TS |P107|P139| 316 vO - > - [| Pes | Re |P108/P140[ 319 VO - - - | Peg | T4 |[P109|P141| 322 GND : - - |[Pi0o! Pe [P1i0/Pi42| - VO (B1) Peg | P73 | P70 [P101| T3 [P113/P147| 325 [WO (RCLK, P70 | P74 | P71 |P102| PS |P114/P1481 328 RDY/BUSY) vO - - - [P103| R4 |P115|P149{ 331 vO - - - [Pi04] R3 | P116|Pi50[ 334 1/0 (DO, DIN) P71 | P75 | P72 |P105| Pa |P117|P151| 337 July 30, 1997 (Version 1.2) 115XC4000E and XC4000X Series Fieid Programmable Gate Arrays PG156 vo 6/10/97 tT =E only tt = XL only Additional XC4005E/XL Package Pins TQ144 6/5/97 | N.C. Pin: ] A 5/5/97 Pin Locations for XC4006E Devices 84 144 | 156 | 160 | 208 Pad 156 160 116 July 30, 1997 (Version 1.2)$2 XIL Rsk aE INX XC4006E Pc [| Ta | PG | PQ |] PQ | Bndry Pad Name ga | 144 | 156 | 160 | 208 Scan vo - Pos | Te | P104 | P134 349 vO - Pos | R7 | P105 | P1365 352 VO (D2) Pe7 | Pos | P7 | P106 | P1338 385 vo Pes | Pov | T5 | P107 | P1390 358 VO - Pes | Re | P1068 | P1409 361 vO - Peg | T4 | Ptog | P14t 364 GND - | P100 | P | Piio | P142 - vO - - RS | Ptit | Pi45 367 vO - - - | Pii2 | P146 370 VO (D1) Peo | P101 | 13 | P113 | P147 373 VO (ACLK, P70 | P102 | P5 | Pi14 | P148 376 RDY/BUSY) va - Pi03 | Ra | P1is | P149 379 vO - P104 | R3 | P116 | P150 382 VO (DO, DIN) P71 | P1o5 | Pa | Pt17 | P151 385 VO, SGCK4 (DOUT) | P72 [Pi0e | T2 | Pi18 | P152 388 CCLK p73 | P107 | R2 | Pii9 | Pi53 - VCC P74 | P108 | P3 | P120 | P154 - 0, TDO P75 | Pio9 | Ti | Pi21 | P1590 0 GND P76 | Pi10 | N3_ | P122 | Pi60 - VO (AO, WS) P77 | Piti | Ri | P123 | P16t 2 VO, PGCK4 (At) P7s | Pit2 | P2 | Pi24 | P162 5 vO - P113 | N2 | P125 | P163 8 vo + Pi14 M3 Pi26 | P164 1 VO (CS1, A2) P79 | P115 | Pi | P127 | P165 14 VQ (A3) Pso | P116 | Ni | P128 | P166 17 vO - Pi17 | M2 | P129 | P167 20 vO - : M1 | P130 | P168 23 GND - | Pia [ 3 | P131 | P171 - vo - P119 L2 P1i32 | P172 26 vo - Pi20 | Li | P133 | P173 29 VO (AA) Pet | Pi2i | K3 | P134 | P174 32 VO (A5) Pa2 | Pi2z2 | K2 | Pi35 | P175 35 vo - | Pi23 | Ki | P137 | P178 38 vO - Pi24 | J1 | Pi3s | P179 41 VO (A6) Pe3 | Pi25 | J2 | P139 | P180 44 V0 (A7) Pea | Pi26 | J3 | P140 | P181 47 GNO Pi | Pi27 | He | P14i [| P1s2 - 5/5/97 Additional XC4006E Package Pins PQ160 N.C. Pins | [__Pize | I - - : 5/5/97 PQ208 PI 1 P66 P91 36 76 6/5/97 July 30, 1997 (Version 1.2) 117XC4000E and XC4000X Series Fieid Programmable Gate Arrays Pin Locations for XC4008E Devices 8 0 5 4 5 P16 7 8 9 118 July 30, 1997 (Version 1.2)$< XILINX Additional XC4008E Package Pins PGi91 Pin Locations for XC4010E/XL Devices The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. Pay xcao1oen. | PC | Pa | Ta Ta | PG BG xeaooext | pc | pa | ra | pa | ta | PG Bc | BG Pad Name | 84 |roott|tasts| 160 [r7ett| tert | PO | gost | sett cor PadNeme | 84 |100tt) 144t+ tert | 191 228t voc P2_| a2 | Pi2e | P142 | P155 | VCC" | Ptea| vec | voc"| _- - | - VO (AB) P3 | P93 | Pizo|Pi43/P156e] J3 [Pis4| ES | C10 | 2 - | - VO (AS) Pa | Poa [P190|P144|P157| v2 _|P185|_B7 | Dio | 65 vO (19) ~ | Pes |P131|P145|Pis8|_J1 |Piee| a7 | a9 |_68 vO (18) ~ | Pee |Pig2(Pi46[P159| H1 |Pis7|_c7 | 59 | 71 vO - | - |.- |_- |Pieo| H2 [Pies] p7 | co | 74 vO ~T7[ 1 -_ [Piet] 43 [Piso] _e7 | 09 |_77 VO (AT0) Ps | Poy |P1a3|P147|Pi62| Gi |Pi90| As | Aa | 80 VO (A11) P | Pos |P134|/Pias|Pie3| G2 |Pi91| Be | Bs | 93 VEC -~- |- |- _- |vec} - [vee [vee] - vo ~ | _- [pias [Pi49/Pie4| Fi [Pieo| as | Be | 86 vO [= [P136[P1s0|P165| e+ |Pi93|_ps | _A5 | a9 GND 7 [= _[P137[ P51 | P1866 | GND*| P1s4| GND" |GND"| _- i) ~~ - | - | - | - | F2 [Pies] pe | ce | 92 vO ee ee Ge vo - | -_|_-_|P182|Piea[ ci [Pis7[ aa | a4 | 98 7) ~ |. |_-[P153/Pie9| 2 [P98] 6 | cs | 101 VO (A12) P7 | Peo |P138|P154|P170|_F3_|Piea| B4 | B4 | 104 VO (Ai3) Pa |P100|P139|Piss|P171| b2 |P200| os | a3 | 107 vo - |_- |pi4o[Pt5e/P172| 81 |P201| a3 | a3 | 110 vO ; P141 | Pis7/P173| 3 |P202| Fe | B2 | 113 vO (At) Po | Pi |Pia2|Ptse|Pi74| c2 |P203| a2 | a2 | 116 vO, SGCK1 Tf, | P10 | _P2 |P143/ P1591 Pi75| B2 |P204| ca | c3 | 119 GCK8 tt (A15} VCC Pit | P38 _|P144|Pi60 | Pi78| VOC" | P20s| VOG | VGC"| _- GND Pi2| Pa | Pi | Pt | Pt {GND*| P2 [GND*|GND*| - VO, PGCKit, |P13| Ps | p2 | P2 | P2 | c3 | es | D4 | Bt | 122 GCKItt (At6} VO (A17) Pi4| Pe | Pa | P3 | P3 | c4 | Ps | Bi | ca | 125 July 30, 1997 (Version 1.2) 119XC4000E and XC4000X Series Field Programmabie Gate Arrays XCAQIOEKL | PC | PQ | TQ | PQ | TQ | PG PadNeme | 94 |100tt|+44tt| 160 |17et+| sate | AO Al3 | P36 ui P55 | P55 | P74 K2 P1153] K3 1| P57 P76 | P84 120 July 30, 1897 (Version 1.2)$< XILINX xeswoen. | pc | pa | ra | pa | ta | pa | PY | Ba | Ba | Brdry BG225 Padame | e4 | root] vert) 160 /17ett| tort | HO | 2ast | asett| scan GND Pi | Poi [P127/P141/P154/GND*|P182/GND"|GND*| _- 6/9/97 * Pads labelled GND* or VCC* are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. t =E only Tt = XL only Additional XC4010E/XL Package Pins PQ/MHQ208 Pine PA BG256 VCC Pins Cia D D7 Dii_| Di4_| bis | E20 Fi FA FI7 G4 GI? Ka Li7 Pais! Pa Pi7 | P19 Re RA RI? U6 U7 uI0 | uid] UTS v7 |__w20 - GND Pins Al a7 Da D8 DIS | bi? | G20 H4 HI7 NB Na NI7 ua UB uig_| ut7 | _wi4 : : : - N.C. Pins AG a Ais | B13_| 66 C4 C7 8 cis] Cie D5 p12 | E19 F2 F3 Fis__|_Fi9_| at Hi H2 H20 3 4 m4__| M19 Nt N2 NIB P20 Rg Ti T18 | _U20 v9 vig vi5_|_W wo |_wi0 | wis _|_wie | ve 9 vis | _14 : : : : 5/27/97 Pin Locations for XC4013E/XL Devices The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. XC4013E oe | at] ra | wt Jpama] ro] eo | fa [20 Jeary] | mc, A7,/ 2 tr, [Pomel ro, ea | ha | 2, [easy Pad Name| 14tt | 160 | 176tr| 208 | 22a | 225+ | 325 | 288tt | Scan Pad Name 240 ve Pize | Pi42| Piss | Pies | VGC" | vc" | Patz| voc | - VO (A14) | P142 | P158| Pi74 | P203 | C2 | A2 | P2ss| AZ | 140 VO (Aa) _| Pt29 | P143 | Pise | Pies | Ja | e8 | P213| Cio | 74 vo, P143 | P1509) P175 | P204 | B2 | C3 | Pe39) C3 | 143 vO (As) | P1390 | P144| Pis7 | 185 | _J2 | 87 | P24] Dio | 77 ScKe H Ve at P1a1 |P145| Pisa | Piss | vt | Av | P2is{ Ao | 60 (A18) HO ag | Pz [PH PieB | Prey [HT [Or [rzi6 | Be | a8 ve Se Tre ee ee vO -_|_-_ | P1e0 | Pres | H2 | 07 | P2i7] co | 66 vO cKt : Pe | P2 | Pe | Pa | C3 | Da | P2 | BI | 146 Me) - -_| Piet | Pies | Ha | Ev | Pete| bs | 69 @CK tt VO (Ain) | Pi33 | P147| Pie2| Pi90 | Gi | AS | P220{ AB | 92 (At6) VO(A11) | P134 | P148 | P1639 | P1i91 | G2 B6 | P221 88 95 VO (A17) P3 PS PS PS C4 Bt PS C2 149 voG : : : -_| VOC" | VCC" | Paa2 | vCCt | - v0 p4 | Pa | Pa | Pe | Ba | c2 [ Pa | De | 152 VO : : - -_| H4 | C6 | P223| AGB | 98 vO Ps [ps | Ps | Pr | cs | 5 | Ps | Ds | 155 vO - - - -__| G4 | F7 | pae4 | 7 | 101 vO, Tor Pe | Ps | Pe | Pa | Az | O38 | Pe | G4 | 158 VO P135 | P149 | Pi64 | P192 Ft AS | P225 BE 104 vO, TCK P7 P7 P7 Pg B4 Ct P7 Ct 161 9) P136 | P150 | P165 | P193 E1 BS | P226 AS 107 vO 7 PB PS P10 C D2 P8 D1 164 GND P137 | P151 | P166 | P194 | GNO*| GND*| P227 | GND* + vO - PQ Pg Pil Aa G6 PS 3 167 VO - - - P195 F2 D | P2268 ce 110 vo . . ~ P12 BS 4 P10 E2 170 vo : - P167 | P196 ot cs | P229 BS 113 vO . . . P13 BS DI Pit El 173 i) -__|Pis2| pies | Pi97 | ci | aa | P230| A4 | 116 vO . 7 . DS) Es | P12 | Fa) 176 i) - [ptsa| Pree | P1968 | E2 | Ee | P2a1] cS | i190 7) 7 7 7 7 pe | 2 | Pia} F2179 VO (A12)_| P1386 |P154| Pi7o | Pi99 | Fs | B4 | Pea] B4 | 122 GND Pa] P10 | Pio | Pia 1GND*TGND*| Pia | Guo VO(At3) | P139 | P155| Pi71 | P200 | O02 DS | P233 A3 125 vo Pg P11 | Pit P15 AA F5 P15 G3 182 vo : : : - Fa | A3 | P234| DS | 128 vo Pio | Piz| Pi2 | Pie | AS | E1 | Pig | G2 | 186 VO : - : - E4 | C4 | P235| C4 | 131 vo,Tws | Pit | Pia [P13 [ Pt7 | B7 | Fa [| Pi7 [ G1 | 188 vO Pi40 | P1s6| Piz2 | P201 | Bi | B3 | P236/ B3 | 134 vO Pi2 | Pi4| P14 | Pie | As | Fa | Pia | H3 | 191 vO P141 | P157| P173 | P2o2 | Ea | Fe | P2a7| B2 | 197 duly 30, 1997 (Version 1.2) 121XC4000E and XC4000X Series Field Programmable Gate Arrays P1680 F13 | P163 122 July 30, 1997 (Version 1.2)$ XILINX XOmise) ut | pa | HT |pama) pa | ec | FY | ga |enary Pad ntame | M4tt| 180 | 476t| 208 | 229 | za5| HO | osett | scan 7) pp ~_| 8s | Gio | Pies | Gia | sa vO a A? | 18 | P165 | Fie | 54a GND Pioo |Pito| Pi22 | P142 |GND*|GND*| Pies | GND | - vO ~ To Po - | R6 | Ela | Pte7 | Fie | S47 vO oe 7 _|-AS | Fiz [P16 | 19 | 850 uO ~ p= | - Pras | vs | 13 | P169 | p20 | 553 vO a a VO . Pitt | P123 | P145 U5 F114} P171 DIS 569 v0 ~_[Pa12 | P1e4 | Pte | Te | Dia | Prve| G20 | 62 VO (D1) P101 | P113] P125 ; Pi47 | V3_| E12 | Pi7a | E17 | 565 VO (ROLK, | P1o2 | P114] P126 | P148 | v2 | c15 | P174/ Dia | 56a RDY/ BUSY) vO P103 | P115 | P127 | Pi49 | U4 | DIS | PI75 | C19 | S71 vO P104 | P116 | P128 | P150 | TS | Ci4 | P76 | Beo | 574 VO (DG, P105 | P117| P129 | P151 | U3 | FIO | Pi77,| C18 | 577 DIN) vO, P1o6 | P118| P130 | P152 | T4 | BI5 | P178| BIS | 580 SGCK4 f, GCK6 tt (BOUT) CCLK P107 | P119| P13t | P153 | V1 | C13 | P179 | A20 : vcc P108 | P120 | P132 | P154 | VCC*) VCC"| P180 | VCC : 0, TDO Pi09 | Pi2t | P133 | Pis9 | U2 | Ais | P181 | A19 GND P110 | P122 | P1394 | P160 | GND*|GND*| P1682 | GND* : we P111 | P123) P135 | P161 | TS | A14 | Pt83[ B18 2 vO, P12 | P124| P136 | P162 | Ut | B13 | P1684} B17 5 PGCK4 f, GCK7 tt (At) vO P113 | P125| P1387 | P163 | P3 | E11 | Pi85 | C17 8 vo Pi14 | Pi26| P1386 | Pi64 | R2 | C12 | Pis6| D16 1 VO(CSi, | P1415 | P127] Piaa | Pies | T2 | A13 [-P187] AiB | 14 Aa) VO (A3) Pit | P128| Pi40 | Pi66 | N3 | B12 | P1838 | A17 17 vO : : : : P4 Fo | Pigg | C16 20 vO : - : : N4 | Dii | P190 | BI6 23 vO Pit7 | Pi29 | Pi4i | P167 | Pe | Ai2 | Pigt | Ai6 26 vO : P130 | Pi42 | P1683 | T1 | C11 | Pi92| C15 29 vO : : : P169 | Rt | B11 | P1938 | Bis 32 vO : + : P170 | N2 | E10 | Pi84 | A15 35 GND P1178 | P131 | P143 | P171 | GND*|GND*|:P196 | GND* : vO P119 | Pi32| Pi44 | Pi72 | Pt | Att |.P197 | B14 38 vo Pi20 | Pi33 | Pi45 | P173 | Ni | D10 | Pi9s | Al4 41 vO - - . : M4 | C10 | P199 | C13 44 vo : : : : L4 | Bio |'P200 | B13 47 vec : : : : Vvec* | vCC* | P201 | VCC" : WO (Aa) P121 | P134| P146 | P174 | M2 | A10 |'P202 | C12 50 VO (A5) Pi22 | P1325 | P147 | Pi75 | M1 be |.P203 | B12 53 vo : : P1438 | Pi76 | 13 Cg | P2056 | Al2 56 vo : P136 | P149 | P177 | L2 Be | P206 | B11 59 vO Pi23 | P137 | P150 | P1787) Lt AS | P207 | Cit 62 (A21) tt vO P124 | P138| P151 | P179 | Kt ES | P208 | Alt 65 (A20) tt VO (A6) Pi25 | P139 | P152 | Pi80 | K2 cs | P209 | A10 68 VO (A7) Pi26 | Pidd | P153 | P1681 | KS BB | P210 | B10 71 GND P127 | P141| P154 | Pi82 | GND*|GND*|:P211 | GND* : 6/9/97 * Pads labelled GND* or VCC" are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. t+ =E only, tt = XL only Additional XC4013E/XL Package Pins PQHa2068 H2 H9 H10 Ka Ms The BG225 package pins in this table are bonded to an internal Ground plane on the XC4013E die. They must all be externally con- nected to Ground. PQ/HQ240 95 + Pins marked with this symbol are used for Ground connections on some revisions of the device. These pins may not physically con- nect to anything on the current device revision. However, they should be extemally connected to Ground, if possible. BG2s6 July 30, 1997 (Version 1.2) 123tenant chy * etaninhy She bs Mites artes wt tle SBS HE ARUR 2 dat otibs oeisigeatrorae og wera tee XC4000E and XC4000X Serles Field Programmable Gate Arrays Pin Locations for XC4020E/XL Devices The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. XCaOQEXL | HT | PQ | HT | HQ2eet | PG BG | Bndry PG | Ho2sct Bodry Pag Pas Pas P129 | P143 | P1s6 P164 P190 | P144 | P157 P1865 P131 | P146 | P158 P186 P1a2 P159 : P1860 5/6|8/5/3/5/5 63 a2 c AS B D5 5/5/S/5/6 |S 427 430 436 442 445 448 451 454 18)8 124 July 30, 1997 (Version 1.2)6/24/97 + =E only tt = XL only Additional XC4020E/XL Package Pins PQ/HQ208 N.C. Pins PI P3 P51 P52 P53 P54 P102 P104 P105 P107 P155 P156 P157 P158 P206 P207 P208 : 5/5/97 5/5/97 PO/HQ240 + Pins marked with this symbol are used for Ground connections on some revisions of the device. These pins may not physically con- nect to anything on the current device revision. However, they should be externally connected to Ground, if possible. BG256 July 30, 1997 (Version 1.2) 125XC4000E and XC4000X Series Field Programmable Gate Arrays Pin Locations for XC4025E, XC4028EX/XL Devices The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. xC4028 | HQ | HO | PG | HO | BG | PG | HO | BG /[Bndry EX/XL | 160tt | 206 | 223 | 240 | 256tt| 299 | 304 | 352+ Pad Name xc4oze | HQ | HQ | PG | HQ | BG | PG | HQ | BG |Bndry EX/XL 208} | 223t | 240 | 256t | 299 | 304 | 352 | Scan Pad Name oO P184 P185 vO P186 vO VO vo vO P244| V23 P242 | 25 1 126 July 30, 1997 (Version 1.2)$< XILINX XC4025E, PG | HQ | BG xc4o28 | HQ | HQ | PG | HQ | BG | PG | HQ | BG |Bndry 22at | 240 | 256tt EXML |160tt| 2084 | 223 | 240 | 256+! 299 | 304 | 352+ | Scan Pad Name 18 re) -~_| Pee | Ris |Pi1o| vie | Ris |Pi6s| AD? | 550 vO P71 | Pes | Tia | Pi11| Wi7 | P16 |P164| AES | 553 8 vO P72 | Pea | P17 [P112] Yia | v20 |P163/ AES | 556 7 GND - : - - [GND* (GND? - (GND; - VCC - - - -_[vcec"[vee*[- vec"; - "0 - - - - -__| R17 |P162| AD6 | 559 vO - - - 5 ~__| 118 |Pt61| AC? | 562 vO P73 | Pes | Nie |P113| Uie | U9 [P160| AF4 | 565 vO P74 | Pos | T17 |P1t4| vi7 | vio [P159| AFS | 568 10 P75 | P97 | Ri7 | P115| wWia | Rie [P1568 | ADS | 571 vO P76 | Pos | P16 |Piie| Yi9 | T17 [P157| AES | 574 vO P77_| P99 [ Uia [P117| Vis | Uie [Pi156| AD4 | 577 vO, P7s |P100| Tie |P11e| wi9 | x20 [P155| ACS | 580 SGCK3 ft, GCK4 + GND P79 |P101 |GND*| P119 | GND* |GND* | P154 |GND*|__- DONE P80 |P103| U17 [P120| Y20 | vis [Pis3| ADs | - vCG Pat_|P106 | VCC" | P121 | VCC" | vCC* |P152|vcc*| - |PRO- Pe2 [Pios| via [Pi22| vie | U17 /Pi51| aca | - GRAM vO (07) | P83 [Pio9| T15 |P123| Ui9 | Wie [P150| AD2 | 583 VO, Pea |P110| Ute [Pi24| Uta | Wis | Pi49| AC3 | 586 PGCKS t, GCKS5 + vO Pas [P1i1| 114 |P125| T17 | T15 [P1438] ABs | 589 vO Pas [P112[ Uis |P126| v20 | Ute |P147| ADI | 592 vO - -_| R14 |P127/ U20 | Vi7 | Pi46[ Aad | 595 vO - - | R13 | Pize| Tis | x18 [P145| AAS | 598 vO - - : : -__[ Ui5 | P144] AB2 | 601 vO 5 : - > - | 114 [P143{ AC1 | 604 voc 5 : - - [vec [vee"| - [vec| - GND - - - -_[GND*[GND*| - [GND*| - VO (D6) P87 |P113] V17 |P129| T19 | Wi7 | Pi142| Y3 607 vO Pes |P114{ Vie |Pi30| T20 | Vie |P141[ AA2 | 610 vO Pag |P115| 113 |Piat| Ais | x17 [P140[ AAI | 613 vo P90 (P116[ Ui4 [P132| Ris | Ui4 [P139[ wa | 616 vO -_|P117| vis [Pia3 | R20 | vis [Pi3a[ w3 | 619 vO -__[P118| via [P134/ Pia | 713 [P137| Y2 | 622 vO : : : . - W116 |P136/ Y1 625 vO - : - - - [wis [P135| v4 [| 628 GND P91 | P119 [GND*| P135 | GND* [GND*|[P134[GND*| _- 7) : -_| R12 |P136| P20 | Ui3 [P133| V3 | 631 vO - - | Rit | Pia7| Nip | vi4 [P132[ we | 634 vO P92 |P120/ Ui3 [Piae| Ni9 | wi4 |[P131| U4 | 637 vO P93 |P121| Vi3 |P139 | N20 | V13 |P130} U3 640 VCC : -_|vCC*|P140 | vec" |vcc*|P129|vcc"| - vO (05 Pa4 | Pi22| ui2 (P14i| Mi7 | Ti2 [P127| ve | 643 VO (C86) | Pes [P123| vi2 |P142/ Mia | x14 [Pi26/ vi | 646 vO : - - - - | ui2 |Pi25| U2 | 649 vO - - 5 - - [| wia |Pi2z4| T2 | 652 GND - - -__|P143/GND*[GND*| - |GND*| - vO = 5 - - - | x13 [Piz3a| Ti | 655 vO - - . - M19 | V12 |P122| R4 658 vO - | Pi24[T11 [Pi44/ M20 | wi2 [P121[ R3 | 661 vO - | P125| uit | P145| Lig | 111 [Pi2z0| R2 | 664 v0 Pes |P126| V1i |P146/ Lis | x12 [Pii9| At | 667 vO P97 [P127| Vio |P147/ 120 | u11 [Pi18| P3 | 670 vO (D4) | P98 [Pi28] U10 |P148| K20 | Vit |P117| P2 | 673 i) Pes | P129| 110 | P1409) Ki9 | Wii [Piie| Pi | 676 vec P1600 | P130 [VGG* | Pi50 | vCc* [vcc*|P115|vcc" | - GND P101 | P131 [GND*| P151 | GND* |GND*|P114 [GND*|_- vO (D3)_|P102 [Pi32| Ta | Pis2| Kia | wio [P113| N2 | 679 vO (AS) | P103 | P133} Us |Pi53] Ki7 | vio |P112| N4 | 682 vO P104|P134] v9 |P154/ J20 | T10 [P111| N3 | 685 vO P1065 | P135| Va |P155{ 419 | Uio [Pit] M1 | 688 Nis |P107 vO - |Pia6{ Us |Pi56|] J18 | x9 |P109| M2 | 691 5 | P108 i) - | P137{ Ta |P157| Ji7 | we |P10a[ M3 | 694 Ni7 |P109 Te) - 5 - - {| Heo | x8 [P107| M4 | 697 July 30, 1997 (Version 1.2) 127XC4000E and XC4000X Series Field Programmable Gate Arrays xC4028 EX/XL, HQ | HQ | PG | HQ | BG | PG | HO | BG |Bndry GOTT) 208 | 223+ | 240 | 256tt | 289 | 304 | 3524 | Scan SGCK4 t, GCK6 fe L4 K2 3 K3 L2 + B18] B/B/B/SiAia] 28 82 * Pads labelled GND* or VCC are internally bonded to Ground or VCC planes within the associated package. They have no direct connection to any specific package pin. t =E only tt = XL only t= EX, XL only Additional XC4025E, XC4028EX/XL Package Pins HO208 PG223 HOQ240 { GND Pine | l P204 I P219 | 5/0/07 Note: These pins may be N.C. for this device revision, however for compatability with other devices in this package, these pins should be tied to GND. 128 July 30, 1997 (Version 1.2)$: XILINX Has04 N.C. Pins Pit |. Psa | +Pi2e | P2065 | Peet Pe4. | =PI0O| | Pi7e | P24 | - 5/15/97 Note: In XC4025 (no extension) devices in the HQ304 package, P101 is a No Connect (N.C.) pin. P101 is Vcc in XC4025E and XC4028EX/XL devices. Where necessary for compatibility, this pin can be left unconnected. Pin Locations for XC4036EX/XL The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. July 30, 1997 (Version 1.2) 129XC4000E and XC4000X Series Fieid Programmable Gate Arrays AH10 AH36 | AK8 130 July 30, 1997 (Version 1.2)July 30, 1997 (Version 1.2) 131XC4000E and XC4000X Series Field Programmable Gate Arrays XC4036EXXL | PQ | HQ | HQ | HQ | BG | PG | BG | Bndry PG411 Pad Name 160t | 206Tt| 240 | 304 | 352 | 411 | 432 | Scan VCC Pins GND P141 | P1982 | P21 | P39 | GND* | GND* | GND* - A3 Atl A21 A31 C39 06 BT797 : F36 J Lae wi AA39 Alt * Pads labelled GND* or VCC" are intemally bonded to Ground or VCC AL39 AP4 AT34 AU AW9 AW19 planes within the associated package. They have no direct connection to AW29 Awa? : Guo Pine : : : an ~ specific package pin AQ Aig A29 A37 C1 p14 tt = XL only D20 026 D34 F4 139 4 P4 P38 w39 Y4 Y36 AAI - AF4 AFS6 AJ39 Au AP36 AT6 Additional XC4036EX/XL Package Pins aTI4 ATz0 AT26 AUS AWS Wit Awa2t AWS31 - : - : Ha208 N.C. Pins N.C. Pins A13 BE B34 C7 C15 C23 PI P3 P51 P52 P53 C25 ca3 D8 Di2 D30 D32 P54 P102 P104 P10S P107 E? 23 37 F2 F18 F22 Pi5S PI56 P157 Pi58 P2068 G5 H34 J5 K36 K38 Ls P207 P208 : - - L35 Ng P38 R3 v2 WS 5/15/97 W35 38 AAS? AB2 AC3 AC39 AF2 AFS Ads AK2 AK38 AL35 ANT ANS APB AP3O AP38 AR37 Ha240 AT2 AT30 AUS AUS AUIS AUI5 GND Fine AUI7 AU2s AUS? AV AV26 AV34 AWI5 AW23 AW25 AW35 : - [_ P204 | P219 I : I : | : | ei6/97 : 6/17/97 The Ground (GND) package pins in the above table should be externally connected to Ground if possible; however, they can be BG432 left unconnected if necessary for compatibility with other devices. VCC Pins Al Ait A2t Aa1 c3 C29 Dit D2t ui L4 128 L3t AAI AAA AA28 AA3I AHI1 AH21 HQ304 AS As29 ALA FED AL21 AL31 i N.C. Pins GND Pins (Pu P24 [pss P100 [P1268 he rT AT ro Ald Ala i piv | P205 {Pose | P261 | - Aas A258 A29 A30 BI Be 5/15/97 B30 B31 Gt 31 Di6 G1 G31 A J31 Pi P31 T4 T28 Vi v31 ACI AC3i AEI BG352 AE31 AH16 AN Assi AKi AK2 VOC Pins AK30 AK31 AL2 AL3 AL7 ALg A10 Al7 B2 B25 D7 D132 AL14 AL18 AL23 AL25 AL29 ALO big G23 H4 Ki K28 N23 N.C. Pins P4 Ut U28 w23 4 ACB A4 AS A15 A28 Bs Bi2 ACT4 AC20 AE2 AE25 AFIO AFI7 817 B21 B25 ca Cis C17 GND Pins D Di3 p20 D23 D26 E2 Al A2 AS AB Ai4 A1a Fi F4 F28 F29 F30 F31 A22 A25 A26 BI B26 E1 G3 M3 M4 M28 M30 N1 E26 Ht H26 Ni P26 wi N2 Neg N30 v2 v28 wi W26 ABI AB26 AEI AE26 AFI We W26 W3t v1 3t AC4 AF2 AFS AFS AFI3 AF19 AF22 AD2 AD30 AD31 AE4 AF29 AF30 AF25 AF26 7 7 7 AGI AHS AHO AHI AH23 AIS N.C. Pine AlB AJt2 ANS Au20 AJ26 AKI C8 [ ' l AKI7 AK24 AK27 ALIS | ALI7 : 6/16/97 5/15/97 Pin Locations for XC4044XL Devices XC4044XL Ha | Ha | HQ | BG PG | BG Pad Name 160 | 208 | 240 | 352 | 411 | 432 vo -_| Ptea | P21e | Did v6 A19 P143 O (At0) P147 | Pi90 | P220| Ai | U3 | B19 VO (A11) P148 | Pig1 | Peet | BI Ri | cig ' ~ VCC - - -__| vec" | vec" | vec 7 7 GND : : -__| GND* | GND* | GND* Pi45 | Pig6 | P2is vo - - - | C16 | US | DI9 Pi46 vO - - : Bi7 | 14 | A20 7 vO - : : Bie | P2 | B20 vO - : : Aig | Ni | C20 132 July 30, 1997 (Version 1.2)$< XILINX 8G Reg July 30, 1997 (Version 1.2) 133XC4000E and XC4000X Series Fieid Programmable Gate Arrays XC4044XL HQ | HQ | HQ | BG | PG | 8G Pad Name 160 | 208 | 240 | 352 | 411 | 432 vO 5 : P74_| AE20 | P34 | AH22 vo - AF20 | 435 | AJ23 vO 5 5 -__[acis | 137 | AKe3 GND P51_| P67 | P75 | GND* | GND | GND* vO ps2_| Pes | P76 | ADIs | Mae | Ajeo va P53 | Peo | P77 | AES | R36 | AKe2 vO p54 | P70 | P78 | ACI7 | Hae | AL22 vo pss_| P7i_| p79 | ADI? | 134 | Aled VCC ; ; Pao | voc | veo" | voc" Te) ; P72_| Pai | AEis | N37 | AH20 v0 - P7a_| Paz | Aria | N39 | AKSi vO : : - [| acte | uss | AK20 ie) - - - [ante | A390 | Alig i) : - -__|_AEI17 | M36 | AL20 i) : - - | afte | va4_ | AHI8 GND ; 5 Pea | GND" | GND* | GND* veC ; ; -__| veo* | voc: | vec vO - : -_|_AFi6 | R37_| AKi9 vO : ; A oe vO : 5 Pes | ADIS | 136 | ALI9 vO 5 5 Pes | AES | vse | AKi8 i) ps6 | P74 | pee | AFIS | u37 | AHI7 vO P57_| P75 | P87_| ADI4 | Uso | Ali7 v0 - : - ; was_| AKI7 vO - : : -__| ac3e | ALI7 vO Psa | P76 | Pea | AEI4 | vas | AJ6 vO (INIT) P59 | P77 | Pag | AFi4 | wa7 | AKi6 vCc Peo | P78 | Pao | voc* | voc* | voc" GND Pt_| P79 | Pei | GND* | GND* | GND" vo Pe2 | P80 | P92 | AEI3 | Y34 | ALI6 vO P63 | Pet | Psa | Acta | AC37 | AHI5 ie) 5 5 - : Yas_| ALIS vO : 5 - -__ | AA37 | Adis v0 Pes | Ps2 | P94 | ADIs | AB3S | AKIS i) Pes | P83 | P95 | AFI2 | ADae | AsI4 ) ; Pea | P96 | AEI2 | AAS5 | AHI4 vo ; pas | P97 | ADI2 | AES7 | AKi4 v0 = : -__| ACt2 [| AB36 | ALIA v0 = : -_|_AFi? [| AD38 | AKI3 vec 5 =| voor | voc | vec GND = - Pee | GND* | GND" | GND* ie) : : | AEM | ABa4 | Agta i) : 5 ~ [| AD11 | AES9 | AHT3 i) 5 i - | ABto | AMa6 | ALI2 v0 5 : > [acti | AC35 | AKi2 vO ; : Peg | AF9 | AGaO | AHi2 vO : -__| P100 | ADIO | AGS7 | Adi vec : -__| Pior | voc* | vec* | vec vO P66 | Pa | Pioz | AeE9 | AD34 | ALiO vO P67_| P87 | Pio3| ADS | AN3O | AKIO vO Pes | Pas | P104 | ACIO | AES | AHO vO Peg | Peg | Pios | Ar7 | AH38 | AKO GND P70_| P90 | P106 | GND* | GND* | GND* vO 5 - ~ | Age | Ala7 | ALB vO 5 : - | _abe | AG36 | AH10 ie) 5 -_ [P107 | ace | AF34 | Als Te) ; -__| P108 | Are | AH36 | Ake VO : : : : AK38 ASB v0 5 5 : -__|_AP38 [| AHO vO : Poi_| P09 | AE? | AKS6 | AK7 v0 : Pe2 | P1i0 | AD? | AM34 | ALG i) P71_| P93 _| Pitt | Aee | AH34 | AJ7 vO P72 | P94 | Pit2| AES | Avgs | AHB GND 5 5 -__ | GND* [| GND | GND* vec - - -__| veo" | vec* | veces vO = 5 -__[_AD6 | AL37 | AK6 vO : - -__| AC? | ATs8 | ALS vo P7a_| P95 | Pita | AF4 | AM38 | AH7 i) P74_| Pee | Pii4 | AF3._| AN37 | AJ6 vo 5 5 AE4 | AK34 | AK5S Te) : 5 -__|_Ac [ AR39 | AL4 vO p75 | Pov | P11s | ADS | ANOS | AK4 vO P76 Pos P116 AES AL33 AHS vo P77_| P99 | Pti7 | Ab4 | AV38 | AK VO, GCK4 P7s | P100 | Ptia | ACS | AT36 | AJ4 134 July 30, 1997 (Version 1.2)$2 XILINX P138 P139 Pi4t 78 P179 P180 81 P182 * Pads labelled GND* or VCC* are intemally bonded to Ground or VCC planes within the associated package. They have no direct connection to any specific package pin. Additional XC4044XL. Package Pins HO208 Pt HQ240 [ GND Pins ] {_paog [| pai foo. TT 5/29/97 Note: These pins may be N.C. for this device revision, however for compatability with other devices in this package, these pins should be tied to GND. BG352 July 30, 1997 (Version 1.2) 135XC4000E and XC4000X Series Field Programmabie Gate Arrays BG432 CC Pins At Alt A2t A31 c3 C29 Dit D21 ul L4 L28 L31 AAI AAd AA28 AASI AHi1 AH21 Ala AJ29 ALI AL11 Al21 ALS : : : : GND Pins A2 Ag AZ AQ Al4 Als A23 A25 A29 A320 Bi B2 B30 B31 ci C31 D6 Gt G31 J1 J31 P41 P31 T4 T28 v1 V31 ACt AC31 AE1 AES1 AH16 AST AJ31 AK1 AK2 AK30 AK31 AL2 AL3 ALT ALS AL14 AL18 AL23 AL25 At29 AL30 . N.C. Pins A4 A28 Bi2 B21 cB D 013 Dzo D26 E2 F4 F2a F29 M3 M4 M28 M30 Wt w2e 1 Y3t AE4 AF29 AF30 AGt AHG6 AH19 AJ5 AMM2 AJ20 AJ26 AK11 AK2?7 - : 5/29/97 Pin Locations for XC4052XL Devices Pad Name 240 B29 028 029 E29 030 GND* F28 F29 136 July 30, 1997 (Version 1.2)$2 XILINX July 30, 1997 (Version 1.2) 137XC4000E and XC4000X Series Field Programmable Gate Arrays XC4052XL HO PG BG BG XC4052XL Ha PG BG BG Pad Name 240 ait 432 560 Pad Name 240 4 432 560 vO : 38 ALI5 ANI7 GND - GND* | GND* | GND* vo - AA37 AHS AKi6 VO (D6) P1429 AV32 AFI A GND - GNO* [ GND* [ GND* vO P130 AU31 AD4 AF4 vO P94 AB38 | AKi5 | AM16 i) P131 AR31 AD3 AGS vo Pos AD36 As4 AL15 vo P132 AP28 AE2 AES vO P96 AAS AH14 | AKI5 vO - AP30 AD2 AH1 vO PO7 AES7 | AKI4 AN5 vo - AT30 AC4 AF3 vO - AB36 ALI3 AN15 GND - GND* | GND* [ GND* vO - AD38 | AK13 | AMi4 vo P133 AT32 AC3 AES vec - voc" | VCC* vec" vo P134 AV30 AD1 ACS GND Pos GND* | GND" | GND* vO - AR29 AG2 AEt ie) - AB34 AJ13 AL14 vO - AP26 AB4 ADS vO - AESO | AHI3 | AKi4 GND P135 GND* | GNO* [ GND vO - AM36 | AL12 Asi4 vO P136 AU29 AB3 AC4 vO - Aca5 | AKi2 | AN13 vO P137 AV28 AB2 AD2 vo - AL35 A12 AM13 vO P138 AT28 ABI ABS v0 - AF36 AK11 ALI3 vO P139 AR25 AAS AC3 GND - GND* | GND* [ GND* VCC P140 Vcc" vec" | voc vO P99 AG3a | AH12 | AKi2 VO (D5) P4141 AP24 AA2 AAS vO P100 AG37 Adit ANI1 VO (C80) P142 AU27 Y2 AB3 VCG Pi01 vec" | voc* | vcc GND - GND [ GND* | GND* vO P102 AD34 ALO AJi2 vo ; AR27 4 AB2 i) P103 AN39__| AK10 ALT vO - Aw27 3 AA4 v0 P104 AESS AJ10 AKT vO - AU2S Yi AAS vO P105 AH38 AKS AMi0 vO - AV26 wi Y5 GND P106 GND* [ GND* [ GND" vO - AT24 wa Y3 vO - AJ37 ALS AL10 V0 - AR23 w3 2 vO - AG35 | AH10 AJ11 GND Pi43_ [| GND* | GND* | GND* vO P107 AF34 AJ ANQ VCG 5 vec* | vec [| vcct vO P108 AH36 AK8 AK10 vo - AW25 w2 WS GND - GND" | GND* | GND vo - AW23 v2 w4 ie) - AK38 AJB AN? vo - AP22 V4 w3 vO - AP38 AHO AJ9 vO - AV24 va wi vO P109 AK36 AK7 AL7 vO P144 AU23 ut v3 vo Pi10_| AM34 AL6 AKB ie) P145 AT22 u2 V5 vO Pitt AH34 Al? AN6 GND . GND* [ GND* [ GND* vO Pi12 AJ35 AH8 AM6 vO P146 AR21 U4 V4 GND - GND* [ GND* | GND* vO P147 AV22 U3 v2 VCC - vec* | Vcc voc* VO (D4) P148 AP20 T1 U5 vo - AL37 AK6 AJB vo P149 AU21 T2 U4 vO - AT38 ALS AL6 VCC P150 vec" [ voc [| vcct ie) P1173 | AM38 AH7 AK7 GND Pi51 GND* | GND* | GND* vO P1i4 AN37 AJG AM5 1/0 (D3) P1s2 AUI9 T3 U3 vO - AK34 AK5 AM4 1/0 (RS) P153 AV20 Rt T2 vO - AR3Q AL4 AJ? 0 Pis4 AV18 R2 T4 GND - GND* | GND* | GND* ie) P1655 ARI9 R4 Ri vO - AR37 AHG ALS GND - GND* [ GND" | GND* vO - AU37 ASS AK6 vO P156 ATI8 A3 R3 vO P115 AN35 AK4 ANS VO P157_ | AW17 P2 Ra VO P16 AL33 AHS AKS vO : AVi6 P3 AS VO P1417 AV38 AK3 AJ6 vO : AP18 P4 P2 VO, GCK4 P118 AT36 Al4 AL4 VO - AUI7 Ni P3 GND Pii9 | GND* [| GND* | GND* vo : AW15 N2 P4 DONE P120 ARS AH4 AIS VCG - vcec* | VCC* VCC" voc P121 vec | vcc* [| vcc GND P158_ GND* | GND" | GND* PROGRAM P122 AN33 AHS AM1 vo - ARI7 N3 Ni W/O (D7) Pi23_ | AMa2 Al2 AHS vO : ATI6 N4 PS VO, GCKS5 P124 AP34 AG4 AJ4 vO - AV14 Mt N2 vO Pi25 | AWs9 AG3 AKS vO - AW13 M2 NS vO P126 AN31 AH2 AH4 vo : AU15 M3 NS vO - AV36 AHI ALI vO - AU13 M4 M3 vO - GES AF4 AGS GND - GND* | GND* | GND* GND : GND* | GND* | GND* 1/0 (D2) P159 AR15 L2 M4 vO P127 AP32 AF3 AJB vO P160 AP16 13 ut vO P128 AU35 AG2 AK2 VCC P161 vec | voc | vcc* i) > AV34 AGI AG4 v0 P162 AV12 Ki K2 ie) - AW35 AES AH3 vo P163 AR13 K2 L4 vO - AW33 AES AF5 vO P164 AUII K3 J vO : AU33 AF2 Al2 vO P65 ATI2 K4 K3 VGC - voc" [| vcec* | vcc GND P166_| GND* | GND* | GND" 138 July 30, 1997 (Version 1.2)$2 XILINX BG 560 GND* E18 15 6 16 1 GND* * Pads labelled GND* or VCC are internally bonded to Ground or VCC planes within the associated package. They have no direct connection to any specific package pin. Additional XC4052XL Package Pins a240 [ GND Pins | Lpeos [| Pata] - fo - J - J - JT | 6/3/97 Note: These pins may be N.C. for this device revision, however for compatability with other devices in this package, these pins should be tied to GND. Poa A3 Ji A Ag 6/3/07 July 30, 1997 (Version 1.2) 139XC4000E and XC4000X Series Field Programmable Gate Arrays PG560 CC Pins A4 A10 A16 A22 A26 A30 B2 B13 Big B32 c3 C31 C32 D1 D33 E5 Hi K33 Mi N32 R2 T33 v1 Ww32 AA2 ABS3 AD1 AF33 AK1 AK4 AK33 AL2 AL3 AL31 AM2 AM15 AM21 AM32 AN4 ANS AN12 AN18 AN24 AN3O . . : : : GND Pins A7 Al2 Al4 Ala A20 A24 A29 A32 Bt B6 Bg B15 B23 B27 B31 c2 Ei F32 G2 G33 J32 K1 L2 M33 Pi P33 Rs2 1 V33 we v1 33 ABI AG32 AD33 AE2 AG1 AG32 AH2 AJ33 AL32 AM3 AM7 AM11 AM19 | AM25 AM28 AM33 AN2 ANS AN10 AN14 ANI6 AN20 AN22 AN27 N.C. Ping Al A8& Aig A23 A27 A28 A33 Ba Bi2 Bi B26 cE ca C12 C22 C26 D10 B13 O16 018 D22 Des E2 E10 E19 E21 E24 E32 E33 H2 3 H5 H31 H32 J4 431 K5 Keg L3 L31 M2 M5 M30 N4 N3o N3i T3 TS T30 T32 U1 U2 U33 Vv32 4 Yeo AAI AAS3 AB4 AB30 AC! AC2 AC33 AD4 AD5 AD29 AD30 AE4 AE30 AE31 AF1 AF2 AF31 AF32 AG2 AMO AJ13 AJI6 AJ18 AJ21 AJ24 AKg AK13 AK18 AL26 AMB AM9 AM12 AM23 AM26 AM27 6/20/97 Pin Locations for XC4062XL Devices Pad Name HQ240 BG432 PG475 BGS60 D17 Y2 17 Al? Y4 WS 8 B17 18 : U3 8 : 19 9 9 9 140 July 30, 1997 (Version 1.2)$< XILINX Ha240 BG432 PGATS BG432 PG475 July 30, 1997 (Version 1.2) 141XC4Q00E and XC4000X Series Field Programmable Gate Arrays HO240 BG432 PGA75 BG560 in Name HQ240 BG432 PG475 BG560 is) P104 AJ10 AJ37 AKI1 L35 AJ25 vo P105 AKO AG35 AM10 R35 AN29 GND P106 GND* GND* GND* 1 AN28 vO : ALB AK40 AL10 vO : AH10 AK38 AJt1 H40 AM26 vo P107 AJ9 AL37 ANOS P38 AK24 vO P108 AK8 AL39 AK10 439 AL25 vo : - AM38 AM9 R37 AJ23 vO : : AM40 ALQ J41 AN26 GND : GNO* GND* GND* AL24 vO : AJS AN41 AN? vo : AHS AM36 AJQ L39 vo P109 AK7 AK36 AL7 vo P110 AL6 AU41 AK8 vo P1114 AJ7 AN39 AN6 vo P112 AH8 AP40 AM6 GND : GNO* GND* GND* voc : vcc* voc" vCcc* vo . AK6 AR41 AJB vo : AL5 ALSS AL6 vO P113 AH7 AV40 AK? vo P114 AJB AN37 AMS vO : AK5 AT38 AM4 vO : AL4 AP38 AJ7 GND : GND* GND* GND* vO : AH6 AT40 ALS vo : AJ5 AW39 AK6 vO P115 AK4 AP36 AN3 VO P116 AH5 AU37 AK5 VO P117 AK3 AR37 ASE VO, GCK4 P118 AJ4 AU39 AL4 GND P119 GND* GND* GND* DONE P120 AH4 AR35 ASS vcc Pi21 vcc* VCC" vcc* P122 AH3 AN35 AMi VO (07) P123 AJ2 AU35 AHS VO, GCKS Pi24 AG4 AV38 Ad4 vO Pi25 AG3 AT34 AK3 vo Pi26 AH2 BA39 AH4 vO : AH1 AU33 AL1 vO : AF4 AY38 AGS GND : GND* GND* GND* VO P127 AF3 AV36 AJB vo Pi28 AG2 AR31 AK2 vO : AG1 AR33 AG4 ie} : AE4 AV32 AH3 vO : AE3 BA37 AF5 vO : AF2 AY36 AJ2 vcc : vcc* vcc* vcc* GND : GND* GND* GND* vO (D6) P129 AFI AV34 AJ1 vO P130 AD4 BA35 AF4 vo P131 AD3 AU31 AGS vo P132 AE2 AY34 AES vo : AD2 AT30 AH1 vo - AC4 AW33 AF3 GND : GND* GND* GND* vO : : BA33 AF1 vo : - AV30 AD4 vo P133 AC3 AY32 AES vo P134 Ad1 AU29 AC5 VO : AC2_._AW31 AE1 vo : AB4siBA1 AD3 GND P135 GND* GND* GND* VO P136 ABS AR27 AC4 vo P137 AB2 AT28 AD2 vo P1386 AB1 AY30 ABS vo P139 AAS AW29 AC3 VvCC P140 vcc* vec" vcc* VO (D5) P141 AA2 BAZo | AAS 142 July 30, 1997 (Version 1.2)Rte GATES wet ee $< XILINX BG432 PG475 8G560 G4 D2 G5 Ci F4 D3 Fs E4 July 30, 1997 (Version 1.2) 143XC4000E and XC4000X Series Field Programmable Gate Arrays XC-4062XL PG475 Pad Name HQ240 BGA32 PG475 BG560 vO : : AC3 B16 vO : A15 AB6 B17 vo : C16 AB2 C17 (0 (A6) P209 Bis AB4 E17 VO (A7) P210 A16 AAS D17 GND Pati GND* GND* GND* 6/16/97 * Pads labelled GND* or VCC" are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. Additional XC4062XL Package Pins HQ240 GND Pins | [| P204 [| Pag | - | : l : | - | 5/5/97 5/5/97 Note: These pins may be N.C. for this device revision, however for compatability with other devices in this package, these pins should BGS60 be tied to GND. VCC Pins A4 Ato A16 A22 A26 A30 B2 B13 B19 832 c3 c31 C32 1 BG432 033 ES Hi K33 M1 N32 R2 VCC Pins 733 v1 wa2 AA2 AB33 AD1 AF33 Al Ait A21 A3i c3 C29 Dit AKi AK4 AK33 AL2 AL3 AL31 AM2 D21 1 L4 L2e L31 AAI AAS AM15 AM21 AM32 AN4 ANS AN12 AN18 AA28 AA31 AH11 AH21 AJ. AJ29 ALI AN24 AN30 : - - - - AL11 AL21 AL31 - - - - GND Pins GND Pins A7 A12 Al4 A1B A20 A24 A29 A2 A3 AZ Ag Al4 A18 A23 A32 81 B6 Bg B15 B23 B27 A25 A29 A30 Bi B2 B30 831 B31 C2 Et F32 G2 G33 J32 ci C31 D16 Qi G31 dt J31 K1 L2 M33 Pt P33 Ree T1 PI P31 14 T28 Vi v31 ACI v33 we Yi Y33 ABI AC32_ | ADS3 AC31 AEI AE31 AH16 AJIT AJ31 AKI AE2 AGI AG32 AH2 AJ33 AL32 AMS AK2 AK30 AK31 AL2 AL3 AL7 ALO AM11 AM19 AM25 AM28 AM33 AM7 AN2 AL14 AL18 AL23 AL25 AL29 AL30 : ANS AN10 AN14 AN16 AN20 AN22 AN27 N.C, Pins N.C. Pins ce - | - : - [- [| - Al Aa A23 A27 A28 A33 BB 5/5/97 812 ce C12 C22 C26 D13 b22 D25 E2 E10 E13 E24 E32 E33 H3 HS H31 J4 K29 13 31 M2 M5 M30 N4 N30 N31 4 Y29 AAI AAS3 AB4 AB30 ACt AC2 AC33 AD5 AD29 AE4 AE30 AF2 AF31 AF32 AG2 AS10 AJ13 AJ21 AJ24 AK9 AK13_ | AK25 ALB AL12 AL22 AL26 AM8 Am12 | AM23 | AM27 ANt AN23 | AN33 : Pin Locations for XC4085XL. Devices BGS60 PG559 Pad Name 144 July 30, 1997 (Version 1.2)July 30, 1997 (Version 1.2) 145ee Bip XC4000E and XC4000X Series Field Programmable Gate Arrays BGaseo PGS559 1 AJ12 146 July 30, 1997 (Version 1.2)vo vO July 30, 1997 (Version 1.2) 147ai XC4000E and XC4000X Series Fieid Programmable Gate Arrays BG560 Passe 5 J 13 AT18 vo vO vo GND VO vO vO v0 IGND Additional XC4085XL Package Pins BG560 VCC Pins A4 At Ai6 A22 A26 A30 B2 B13 BI9 B32 C3 C31 C32 Di D33 ES Hi K33 M1 N32 R2 T33 vi w32 AA2 ABS3 ADI AF33 AKt AK4 AK33 AL2 AL3 AL31 AM2 AMI5 | AM21_| AM32 [| AN4 ANS ANi2 | AN18 AN24 | AN3O : - : - : GND Pins AZ Ai2 Al4 Ais A20 A24 A29 A32 B1 B6 Bg Bid B23 B27 B3i C2 Ei F32 G2 G33 J32 KI L2 M33 PA P33 A382 T1 v33 w2 YI Y33 ABI Acs2_|[ AD33 AE2 AGI AG32 AH2 AJ33 AL32 AM3 AMi1 | AMi9 | AM25 [| AM2s8 | AM33 | AM7 AN2 ANS ANiO | ANi4 [| ANI | AN20 | AN22 | AN27 N.C. Pins Ai__| 433 [| ace [| AN1 | ANSS [_ - - 6/4/97 148 July 30, 1997 (Version 1.2)5/8/97 * Pads labelled GND* or VCC" are intemaily bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. +=E only, tt = XL only July 30, 1997 (Version 1.2) 149XC4000E and XC4000X Series Field Programmable Gate Arrays Ordering Information Example: Device Type XC4013E-3HQ240C Speed Grade 6 5 4 3 2 1 PC = Plastic Lead Chip Carrier PQ = Plastic Quad Flat Pack VQ = Very Thin Quad Flat Pack TQ = Thin Quad Flat Pack LL Temperature Range C = Commercial (Ty = 0 to +85C) | = Industrial (Ty = -40 to +100C) M = Military (Tc = -55 to+ 125C) Number of Pins Package Type BG = Bail Grid Array PG = Ceramic Pin Grid Array HQ = High Heat Dissipation Quad Flat Pack MQ = Metal Quad Flat Pack CB = Top Brazed Ceramic Quad Flat Pack > XILINX The Programmable Logic Company x9020 Headquarters Xilinx, Inc. 2100 Logic Drive San Jose, CA 95124 U.S.A. Tel: 1 (800) 255-7778 or 1 (408) 559-7778 Fax: 1 (800) 559-7114 Net: hotline @xilinx.com Web: http:/Avww.xilinx.com North America Irvine, California (714) 727-0780 Englewood, Colorado (303) 220-7541 Sunnyvale, Califomia (408) 245-9850 Schaumburg, Illinois (847) 605-1972 Nashua, New Hampshire (603) 891-1098 Raleigh, North Carolina (919) 846-3922 West Chester, Pennsylvania (610) 430-3300 Dallas, Texas (972) 960-1043 Europe Xilinx, Ltd. Byfleet, United Kingdom Tel: (44) 1-932-349403 Net: ukhelp@ xilinx.com Xilinx Sarl Jouy en Josas, France Tel: (33) 1-34-63-01-01 Net: frhelp @xilinx.com Xilinx, AB c/o Dipcom Electronics Kista, Sweden Tel: (46) 8-752-24-70 Xilinx GmbH Munich, Germany Tel: (49) 89-93088-0 Net: dihelp @ xilinx.com Japan Xilinx, K.K. Tokyo, Japan Tel: (81) 3-3297-9191 Hong Kong Xilinx Asia Pacific Hong Kong Tel: (852) 2424-5200 Net: hongkong @ xilinx.com Korea Xilinx Korea Seoul, Korea Tel: (82) 2-761-4277 Fax: (82) 2-761-4278 1997 Xilinx, Inc. All rights reserved. The Xilinx name and the Xilinx logo are registered trademarks, all XC-designated products are trademarks, and the Pro- grammable Logic Company is a service mark of Xilinx, Inc. All other trademarks and registered trademarks are the property of their respective owners. Xilinx, Inc. does not assume any liability arising out of the application or use of any product described herein; nor does it convey any license under its patent, copy- right or maskwork rights or any rights of others. Xilinx, Inc. reserves the right te make changes, at any time, in order to improve reliability, function or design and to supply the best product possible, Xilinx, Inc. cannot assume responsibility for the use of any circuitry described other than circuitry entirely embodied in its prod- ucts. Products are manufactured under one or more of the following U.S. Patents: (4,847,612; 5,012,135; 4,967,107; 5,023,606; 4,940,909; 5,028,821; 4,870,302; 4,706,216; 4,758,985; 4,642,487; 4,695,740; 4,713,567; 4,750,155; 4,821,233; 4,746,822; 4,820,937; 4,783,607; 4,855,669; 5,047,710; 5,068,603; 4,855,619; 4,835,418; and 4,902,910. Xilinx, Inc. cannot assume responsibility for any circuits shown nor represent that they are free from patent infringement or of any other third party right. Xilinx, Inc. assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. 150 duly 30, 1997 (Version 1.2)