Document Number: 91052 www.vishay.com
S11-1048-Rev. C, 30-May-11 1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
Power MOSFET
IRF740AS, SiHF740AS, IRF740AL, SiHF740AL
Vishay Siliconix
FEATURES
•Halogen-free According to IEC 61249-2-21
Definition
• Low Gate Charge Qg Results in Simple Drive
Requirement
• Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
• Fully Characterized Capacitance and
Avalanche Voltage and Current
• Effective Coss specified
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
• Switch Mode Power Supply (SMPS)
• Uninterruptible Power Supply
• High speed Power Switching
TYPICAL SMPS TOPOLOGIES
• Single Transistor Flyback Xfmr. Reset
• Single Transistor Forward Xfmr. Reset (Both for US Line
Input Only)
Note
a. See device orientation.
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 12.6 mH, Rg = 25 , IAS = 10 A (see fig. 12).
c. ISD 10 A, dI/dt 330 A/μs, VDD VDS, TJ 150 °C.
d. 1.6 mm from case.
e. Uses IRF740A, SiHF740A data and test conditions.
PRODUCT SUMMARY
VDS (V) 400
RDS(on) ()V
GS = 10 V 0.55
Qg (Max.) (nC) 36
Qgs (nC) 9.9
Qgd (nC) 16
Configuration Single
N-Channel MOSFET
G
D
S
D
2
PAK (TO-263)
GD
S
I
2
PAK (TO-262)
GDS
ORDERING INFORMATION
Package D2PAK (TO-263) D2PAK (TO-263) D2PAK (TO-263) I2PAK (TO-262)
Lead (Pb)-free and Halogen-free SiHF740AS-GE3 SiHF740ASTRL-GE3aSiHF740ASTRR-GE3aSiHF740AL-GE3
Lead (Pb)-free IRF740ASPbF IRF740ASTRLPbFaIRF740ASTRRPbFaIRF740ALPbF
SiHF740AS-E3 SiHF740ASTL-E3aSiHF740ASTR-E3aSiHF740AL-E3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS 400 V
Gate-Source Voltage VGS ± 30
Continuous Drain CurrenteVGS at 10 V TC = 25 °C ID
10
ATC = 100 °C 6.3
Pulsed Drain Currenta, e IDM 40
Linear Derating Factor 1.0 W/°C
Single Pulse Avalanche Energyb, e EAS 630 mJ
Avalanche CurrentaIAR 10 A
Repetiitive Avalanche EnergyaEAR 12.5 mJ
Maximum Power Dissipation TA = 25 °C PD
3.1 W
TC = 25 °C 125
Peak Diode Recovery dV/dtc, e dV/dt 5.9 V/ns
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 150 °C
Soldering Recommendations (Peak Temperature) for 10 s 300d
* Pb containing terminations are not RoHS compliant, exemptions may apply
www.vishay.com Document Number: 91052
2S11-1048-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRF740AS, SiHF740AS, IRF740AL, SiHF740AL
Vishay Siliconix
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width 300 μs; duty cycle 2 %.
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS.
d. Uses IRF740A, SiHF740A data and test conditions.
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient (PCB
Mounted, Steady-State)aRthJA -40
°C/W
Maximum Junction-to-Case (Drain) RthJC -1.0
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0, ID = 250 μA 400 - - V
VDS Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mAd-0.48-V/°C
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V
Gate-Source Leakage IGSS V
GS = ± 30 V - - ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = 400 V, VGS = 0 V - - 25 μA
VDS = 320 V, VGS = 0 V, TJ = 125 °C - - 250
Drain-Source On-State Resistance RDS(on) V
GS = 10 V ID = 6.0 Ab- - 0.55
Forward Transconductance gfs VDS = 50 V, ID = 6.0 Ad4.9 - - S
Dynamic
Input Capacitance Ciss VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5d
- 1030 -
pF
Output Capacitance Coss - 170 -
Reverse Transfer Capacitance Crss -7.7-
Output Capacitance Coss VGS = 0 V
VDS = 1.0 V, f = 1.0 MHz - 1490 -
VDS = 320 V, f = 1.0 MHz - 52 -
Effective Output Capacitance Coss eff. VDS = 0 V to 320 Vc, d -61-
Total Gate Charge Qg
VGS = 10 V ID = 10 A, VDS = 320 V,
see fig. 6 and 13b, d
--36
nC Gate-Source Charge Qgs --9.9
Gate-Drain Charge Qgd --16
Turn-On Delay Time td(on)
VDD = 200 V, ID = 10 A,
Rg = 10 , RD = 19.5 , see fig. 10b, d
-10-
ns
Rise Time tr -35-
Turn-Off Delay Time td(off) -24-
Fall Time tf -22-
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current ISMOSFET symbol
showing the
integral reverse
p - n junction diode
--10
A
Pulsed Diode Forward CurrentaISM --40
Body Diode Voltage VSD TJ = 25 °C, IS = 10 A, VGS = 0 Vb--2.0V
Body Diode Reverse Recovery Time trr TJ = 25 °C, IF = 10 A, dI/dt = 100 A/μsb, d - 240 360 ns
Body Diode Reverse Recovery Charge Qrr -1.92.9μC
Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
S
D
G
Document Number: 91052 www.vishay.com
S11-1048-Rev. C, 30-May-11 3
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRF740AS, SiHF740AS, IRF740AL, SiHF740AL
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Fig. 1 - Typical Output Characteristics
Fig. 2 - Typical Output Characteristics
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
91052_01
Bottom
To p
VGS
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
4.5 V
20 µs Pulse Width
TJ = 25 °C
4.5 V
V
DS
, Drain-to-Source Voltage (V)
I
D
, Drain-to-Source Current (A)
102
0.1
10-2
1
10
1100.1 102
VDS, Drain-to-Source Voltage (V)
ID, Drain-to-Source Current (A)
Bottom
To p
VGS
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
4.5 V
20 µs Pulse Width
TJ = 150 °C
91052_02
4.5 V
102
0.1
1
10
1100.1 102
20 µs Pulse Width
VDS = 50 V
ID, Drain-to-Source Current (A)
VGS, Gate-to-Source Voltage (V)
5.0 6.0 7.0 8.0 9.0 10.0
4.0
91052_03
102
0.1
1
10
TJ = 25 °C
TJ = 150 °C
I
D
= 10 A
V
GS
= 10 V
3.0
0.0
0.5
1.0
1.5
2.0
2.5
TJ, Junction Temperature (°C)
RDS(on), Drain-to-Source On Resistance
(Normalized)
91052_04
- 60 - 40 - 20 0 20 40 60 80 100 120 140 160
www.vishay.com Document Number: 91052
4S11-1048-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRF740AS, SiHF740AS, IRF740AL, SiHF740AL
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
1
10
10 102
C, Capacitance (pF)
V
DS,
Drain-to-Source Voltage (V)
Ciss
Crss
Coss
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
91052_05
105
102
103
104
1103
Q
G
, Total Gate Charge (nC)
V
GS
, Gate-to-Source Voltage (V)
20
16
12
8
0
4
04020 3010
V
DS
= 80 V
V
DS
= 200 V
For test circuit
see figure 13
V
DS
= 320 V
91052_06
I
D
= 10 A
102
10
V
SD
, Source-to-Drain Voltage (V)
I
SD
, Reverse Drain Current (A)
0.2 1.0
0.80.60.4
V
GS
= 0 V
91052_07
TJ = 25 °C
TJ = 150 °C
1
0.1
1.41.2
10 µs
100 µs
1 ms
10 ms
Operation in this area limited
by RDS(on)
VDS, Drain-to-Source Voltage (V)
ID, Drain Current (A)
TC = 25 °C
TJ = 150 °C
Single Pulse
102
1
10
10 102103
91052_08
Document Number: 91052 www.vishay.com
S11-1048-Rev. C, 30-May-11 5
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRF740AS, SiHF740AS, IRF740AL, SiHF740AL
Vishay Siliconix
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10a - Switching Time Test Circuit
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms
ID, Drain Current (A)
TC, Case Temperature (°C)
0.0
2.0
4.0
6.0
8.0
10.0
25 1501251007550
91052_09
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
RD
VGS
Rg
D.U.T.
10 V
+
-
VDS
VDD
VDS
VGS
10
1
0.1
10-2
10-5 10-4 10-3 10-2 0.1 1 10
PDM
t1
t2
t1, Rectangular Pulse Duration (s)
Thermal Response (ZthJC)
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
Single Pulse
(Thermal Response)
D = 0.50
0.20
0.05
0.02
0.01
91052_11
0.10
10-3
A
Rg
IAS
0.01 Ω
tp
D.U.T
L
VDS
+
-VDD
Driver
15 V
20 V
IAS
VDS
tp
www.vishay.com Document Number: 91052
6S11-1048-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRF740AS, SiHF740AS, IRF740AL, SiHF740AL
Vishay Siliconix
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Fig. 13a - Basic Gate Charge Waveform
Fig. 12d - Typlical Drain-to-Source Voltage
vs. Avalanche Current
Fig. 13b - Gate Charge Test Circuit
1400
0
400
600
800
1000
1200
25 150
125
10075
50
Starting TJ, Junction Temperature (°C)
EAS, Single Pulse Avalanche Energy (mJ)
Bottom
To p
ID
4.5 A
6.3 A
10 A
91052_12c
200
QGS QGD
QG
V
G
Charge
VGS
560
480
520
540
1.0 6.0
5.0
4.03.0
2.0
I
AV
, Avalanche Current (A)
V
DSav
, Avalanche Voltage (V)
580
9.0
8.0
7.0
91052_12d
500
10.0
D.U.T.
3 mA
VGS
VDS
IGID
0.3 µF
0.2 µF
50 kΩ
12 V
Current regulator
Current sampling resistors
Same type as D.U.T.
+
-
Document Number: 91052 www.vishay.com
S11-1048-Rev. C, 30-May-11 7
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRF740AS, SiHF740AS, IRF740AL, SiHF740AL
Vishay Siliconix
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91052.
P.W. Period
dI/dt
Diode recovery
dV/dt
Ripple ≤ 5 %
Body diode forward drop
Re-applied
voltage
Reverse
recovery
current
Body diode forward
current
VGS = 10 Va
ISD
Driver gate drive
D.U.T. lSD waveform
D.U.T. VDS waveform
Inductor current
D = P.W.
Period
+
-
+
+
+
-
-
-
Peak Diode Recovery dV/dt Test Circuit
VDD
• dV/dt controlled by Rg
• Driver same type as D.U.T.
• ISD controlled by duty factor “D”
• D.U.T. - device under test
D.U.T. Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
Rg
Note
a. VGS = 5 V for logic level devices
VDD
Document Number: 91364 www.vishay.com
Revision: 15-Sep-08 1
Package Information
Vishay Siliconix
TO-263AB (HIGH VOLTAGE)
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
5
4
13
L1
L2
D
BB
E
H
B
A
Detail A
A
A
c
c2
A
2 x e
2 x b2
2 x b
0.010 A B
MM ± 0.004 B
M
Base
metal
Plating b1, b3
(b, b2)
c1
(c)
Section B - B and C - C
Scale: none
Lead tip
4
34
(Datum A)
2CC
BB
5
5
View A - A
E1
D1
E
4
4
B
H
Seating plane
Gauge
plane
0° to 8°
Detail “A”
Rotated 90° CW
scale 8:1
L3 A1
L4
L
MILLIMETERS INCHES MILLIMETERS INCHES
DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.
A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 -
A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420
b 0.51 0.99 0.020 0.039 E1 6.22 - 0.245 -
b1 0.51 0.89 0.020 0.035 e 2.54 BSC 0.100 BSC
b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625
b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110
c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066
c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070
c2 1.14 1.65 0.045 0.065 L3 0.25 BSC 0.010 BSC
D 8.38 9.65 0.330 0.380 L4 4.78 5.28 0.188 0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
AN826
Vishay Siliconix
Document Number: 73397
11-Apr-05
www.vishay.com
1
RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead
0.635
(16.129)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.420
(10.668)
0.355
(9.017)
0.145
(3.683)
0.135
(3.429)
0.200
(5.080)
0.050
(1.257)
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Revision: 12-Mar-12 1Document Number: 91000
Disclaimer
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Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.