74HC237 3-to-8 line decoder, demultiplexer with address latches Rev. 7 -- 29 January 2016 Product data sheet 1. General description The 74HC237 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC237 is specified in compliance with JEDEC standard no. 7A. The 74HC237 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC237 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the 74HC237 acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE remains HIGH. The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH. The 74HC237 is ideally suited for implementing non-overlapping decoders in 3-state systems and strobes (stored address) applications in bus-oriented systems. 2. Features and benefits Combines 3-to-8 decoder with 3-bit latch Multiple input enable for easy expansion or independent controls Active HIGH mutually exclusive outputs Low-power dissipation ESD protection: HBM JESD22-A114F exceeds 2 000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC237D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC237DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74HC237 Nexperia 3-to-8 line decoder, demultiplexer with address latches 4. Functional diagram /( < < < $ $ ,1387 /$7&+(6 $ < 72 '(&2'(5 < < < < ( ( DDE Fig 1. Functional diagram '; & '* /( < < < $ $ ,1387 /$7&+(6 $ 72 < '(&2'(5 < < < < ;< & ' ' ' ( DDE Logic symbol 74HC237 Product data sheet (1 ( Fig 2. DDE Fig 3. IEC logic symbol All information provided in this document is subject to legal disclaimers. . Rev. 7 -- 29 January 2016 2 of 17 (c) Nexperia B.V. 2017. All rights reserved 74HC237 Nexperia 3-to-8 line decoder, demultiplexer with address latches $ /$7&+ $ /( < $ /( < $ /$7&+ $ /( $ /( < $ /$7&+ $ /( < $ /( < /( < < < ( DDE ( Fig 4. Logic diagram 5. Pinning information 5.1 Pinning +& $ 9&& $ < $ < /( < ( < ( < *1' +& $ 9&& $ < $ < /( < ( < ( < < < *1' < < < DDE Fig 5. Pin configuration SO16 74HC237 Product data sheet < DDQ Fig 6. Pin configuration SSOP16 All information provided in this document is subject to legal disclaimers. . Rev. 7 -- 29 January 2016 3 of 17 (c) Nexperia B.V. 2017. All rights reserved 74HC237 Nexperia 3-to-8 line decoder, demultiplexer with address latches 5.2 Pin description Table 2. Pin description Symbol Pin Description A0 to A2 1, 2, 3 data input LE 4 latch enable input (active LOW) E1 5 data enable input 1 (active LOW) E2 6 data enable input 2 (active HIGH) Y0 to Y7 15, 14, 13, 12, 11, 10, 9, 7 output GND 8 ground (0 V) VCC 16 supply voltage 6. Functional description Table 3. Function table Enable Input Output LE E1 E2 A0 A1 A2 Y0 H L H X X X stable X H X X X X L L L L L L L L X X L X X X L L L L L L L L L L H L L L H L L L L L L L H L L L H L L L L L L L H L L L H L L L L L H H L L L L H L L L L L L H L L L L H L L L H L H L L L L L H L L L H H L L L L L L H L H H H L L L L L L L H [1] Y1 Y2 Y3 Y4 Y5 Y6 Y7 H = HIGH voltage level; L = LOW voltage level; X = don't care; Z = high-impedance OFF-state. 74HC237 Product data sheet All information provided in this document is subject to legal disclaimers. . Rev. 7 -- 29 January 2016 4 of 17 (c) Nexperia B.V. 2017. All rights reserved 74HC237 Nexperia 3-to-8 line decoder, demultiplexer with address latches 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage 0.5 +7 V IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V - 20 mA IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V - 20 mA IO output current VO = 0.5 V to (VCC + 0.5 V) - 25 mA ICC supply current - +50 mA IGND ground current - 50 mA Tstg storage temperature 65 +150 C - 500 mW total power dissipation Ptot [1] Conditions Min [1] SO16 and SSOP16 packages Max Unit For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. For SSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC supply voltage VI Min Typ Max Unit 2.0 5.0 6.0 V input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature t/V input transition rise and fall rate 74HC237 Product data sheet Conditions 40 +25 +125 C VCC = 2.0 V - - 625 ns/V VCC = 4.5 V - 1.67 139 ns/V VCC = 6.0 V - - 83 ns/V All information provided in this document is subject to legal disclaimers. . Rev. 7 -- 29 January 2016 5 of 17 (c) Nexperia B.V. 2017. All rights reserved 74HC237 Nexperia 3-to-8 line decoder, demultiplexer with address latches 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage Tamb = 25 C Conditions Min Typ VCC = 2.0 V 1.5 VCC = 4.5 V 3.15 VCC = 6.0 V 4.2 VCC = 2.0 V - VCC = 4.5 V - VCC = 6.0 V Tamb = 40 C to +85 C Tamb = 40 C to Unit +125 C Max Min Max Min Max 1.2 - 1.5 - 1.5 - V 2.4 - 3.15 - 3.15 - V 3.2 - 4.2 - 4.2 - V 0.8 0.5 - 0.5 - 0.5 V 2.1 1.35 - 1.35 - 1.35 V - 2.8 1.8 - 1.8 - 1.8 V IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1.0 - 1.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 A CI input capacitance - 3.5 - - - - - pF 74HC237 Product data sheet All information provided in this document is subject to legal disclaimers. . Rev. 7 -- 29 January 2016 6 of 17 (c) Nexperia B.V. 2017. All rights reserved 74HC237 Nexperia 3-to-8 line decoder, demultiplexer with address latches 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 10. Symbol Parameter tpd propagation delay Tamb = 25 C Conditions An to Yn; see Figure 7 VCC = 2.0 V 74HC237 Product data sheet Min Max Min Max - 52 160 - 200 - 240 ns 19 32 - 40 - 48 ns 16 - - - - - ns - 15 27 - 34 - 41 ns [1] VCC = 2.0 V - 61 190 - 240 - 285 ns VCC = 4.5 V - 22 38 - 48 - 57 ns VCC = 5 V; CL = 15 pF - 19 - - - - - ns - 18 32 - 41 - 48 ns VCC = 2.0 V - 47 145 - 180 - 220 ns VCC = 4.5 V - 17 29 - 36 - 44 ns VCC = 5 V; CL = 15 pF - 14 - - - - - ns - 14 25 - 31 - 38 ns VCC = 2.0 V - 47 145 - 180 - 220 ns VCC = 4.5 V - 17 29 - 36 - 44 ns VCC = 5 V; CL = 15 pF - 14 - - - - - ns VCC = 6.0 V - 14 25 - 31 - 38 ns [1] VCC = 6.0 V set-up time Max - E2 to Yn; see Figure 7 tsu Typ - E1to Yn; see Figure 8 pulse width Min VCC = 5 V; CL = 15 pF VCC = 6.0 V tW Unit VCC = 4.5 V LE to Yn; see Figure 7 transition time Tamb = 40 C to +125 C [1] VCC = 6.0 V tt Tamb = 40 C to +85 C Yn; see Figure 7 and Figure 8 [1] [2] VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 50 11 - 65 - 75 - ns VCC = 4.5 V 10 4 - 13 - 15 - ns VCC = 6.0 V 9 3 - 11 - 13 - ns VCC = 2.0 V 50 6 - 65 - 75 - ns VCC = 4.5 V 10 2 - 13 - 15 - ns VCC = 6.0 V 9 2 - 11 - 13 - ns LE HIGH; see Figure 9 An to LE; see Figure 9 All information provided in this document is subject to legal disclaimers. . Rev. 7 -- 29 January 2016 7 of 17 (c) Nexperia B.V. 2017. All rights reserved 74HC237 Nexperia 3-to-8 line decoder, demultiplexer with address latches Table 7. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 10. Tamb = 25 C Symbol Parameter Conditions th An to LE; see Figure 9 Min hold time [1] Max Tamb = 40 C to +125 C Min Min Max Max Unit - VCC = 2.0 V 30 3 - 40 - 45 - ns VCC = 4.5 V 6 1 - 8 - 9 - ns VCC = 6.0 V power dissipation capacitance CPD Typ Tamb = 40 C to +85 C [3] CL = 50 pF; f = 1 MHz; VI = GND to VCC 5 1 - 7 - 8 - ns - 60 - - - - - pF tpd is the same as tPLH and tPHL. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs. 11. Waveforms $Q(/( LQSXW 90 W3+/