Intel(R) 41110 Serial to Parallel PCI Bridge Datasheet Product Features x8 PCI Express to Single PCIX/PCI bus bridge PCI Express Specification, Revision 1.0a Support for single x8, single x4 or single x1 PCI Express operation. Supports 64-bit PCI-X 133 MHz, 100 MHz and 66 MHz as well as PCI 66 MHz and 33 MHz for mixed PCI/PCI-X modes and frequency bus/device operation 64-bit addressing support 32-bit CRC (cyclic redundancy checking) covering all transmitted data packets. 16-bit CRC on all link message information. Raw bit-rate on the data pins of 2.5 Gbit/s, resulting in a raw bandwidth per pin of 250 MB/s. Maximum realized bandwidth on PCI Express interface is 2 GB/s (in x8 mode) in each direction simultaneously, for an aggregate of 4 GB/s. PCI Local Bus Specification, Revision 2.3. PCI-to-PCI Bridge Specification, Revision 1.1. PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b 64-bit 66 MHz, 3.3 V, NOT 5 V tolerant. On Die Termination (ODT) with 8.3K pull-up to 3.3V for PCI signals. Six external REQ/GNT Pairs for internal arbiter on segment A. Programmable bus parking on either the last agent or always on the 41110 Bridge 2-level programmable round-robin internal arbiter with Multi-Transaction Timer (MTT) External PCI clock-feed support for asynchronous primary and secondary domain operation. 64-bit addressing for upstream and downstream transactions Downstream LOCK# support. No upstream LOCK# support. PCI fast Back-to-Back capable as target. Up to four active and four pending upstream memory read transactions Up to two downstream delayed (memory read, I/O read/write and configuration read/ write) transaction. Tunable inbound read prefetch algorithm for PCI MRM/MRL commands Device hiding support for secondary PCI devices. Secondary bus Private Memory support via Opaque memory region Local initialization via SMBus Secondary side initialization via Type 0 configuration cycles. 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Copyright (c) 2006, Intel Corporation 2 Contents Contents 1 Introduction.................................................................................................................................... 7 1.1 1.2 2 About This Document ........................................................................................................... 7 Product Overview ................................................................................................................. 7 Signal Description ......................................................................................................................... 8 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 On Die Termination (ODT).................................................................................................... 8 PCI Express Interface........................................................................................................... 9 PCI Bus Interface................................................................................................................10 PCI Bus Interface 64-Bit Extension ....................................................................................11 PCI Bus Interface Clocks and, Reset and Power Management .........................................12 Interrupt Interface ...............................................................................................................12 Reset Straps .......................................................................................................................12 SMBus Interface .................................................................................................................14 Miscellaneous Pins .............................................................................................................14 Electrical and Thermal Characteristics .....................................................................................16 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 4 DC Voltage and Current Specifications ..............................................................................16 41110 Bridge Power Consumption .....................................................................................16 Power Delivery Guidelines..................................................................................................17 Input Characteristic Signal Association ..............................................................................18 DC Input Characteristics .....................................................................................................18 DC Characteristic Output Signal Association .....................................................................18 DC Output Characteristics ..................................................................................................19 PCI Express Interface DC Specifications ...........................................................................19 AC Specifications................................................................................................................25 Voltage Filter Specifications ...............................................................................................26 VCC15 and VCC33 Voltage Requirements ........................................................................27 Timing Specifications ..........................................................................................................28 Reference and Compensation Pins ....................................................................................36 Thermal Specifications .......................................................................................................37 Package Specification and Ballout ............................................................................................39 4.1 4.2 4.3 Package Specification ........................................................................................................39 Signal List, sorted by Ball Location.....................................................................................41 Signal List, sorted by Signal Name.....................................................................................45 Figures 1 2 3 4 5 6 7 8 Minimum Transmitter Timing and Voltage Output Compliance Specification.............................22 Compliance Test/Measurement Load.........................................................................................23 Minimum Receiver Eye Timing and Voltage Compliance Specification .....................................23 Voltage Requirements VCC33 versus VCC15 ...........................................................................27 PCI Output Timing ......................................................................................................................31 PCI Input Timing .........................................................................................................................31 PCI-X 3.3V Clock Waveform ......................................................................................................33 41110 Bridge Reference and Compensation Circuit Implementations .......................................37 3 Contents 9 41110 Bridge Package Dimensions (Top View) ......................................................................... 39 10 41110 Bridge Package Dimensions (Side View) ........................................................................ 40 Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 4 ODT Signals ................................................................................................................................. 8 PCI Express Interface Pins........................................................................................................... 9 PCI Interface Pins....................................................................................................................... 10 PCI Interface Pins: 64-Bit Extensions......................................................................................... 11 PCI Clock and Reset Pins .......................................................................................................... 12 Interrupt Interface Pins ............................................................................................................... 12 Reset Strap Pins......................................................................................................................... 13 SMBus Interface Pins ................................................................................................................. 14 Miscellaneous Pins ..................................................................................................................... 14 Intel(R) 41110 Bridge DC Voltage Specifications ......................................................................... 16 41110 Bridge Maximum Voltage Plane Currents ....................................................................... 16 41110 Bridge Thermal Voltage Plane Currents .......................................................................... 17 Watts .......................................................................................................................................... 17 DC Characteristics Input Signal Association .............................................................................. 18 DC Input Characteristics............................................................................................................. 18 DC Characteristic Output Signal Association ............................................................................. 18 DC Output Characteristic............................................................................................................ 19 Differential Transmitter (TX) DC Output Specifications .............................................................. 19 Differential Receiver (RX) DC Input Specifications .................................................................... 21 DC Specifications for PCI and PCI-X 3.3 V Signaling ................................................................ 24 DC Specification for Input Clock Signals .................................................................................... 25 DC Specification for Output Clock Signals ................................................................................. 25 Conventional PCI 3.3V AC Characteristics ................................................................................ 25 PCI-X 3.3V AC Characteristics ................................................................................................... 26 Differential Transmitter (TX) AC Output Specifications .............................................................. 28 Differential Receiver (RX) AC Input Specifications..................................................................... 29 PCI Interface Timing................................................................................................................... 30 PCI-X 3.3V Signal Timing Parameters ....................................................................................... 31 PCI and PCI-X Clock Timings .................................................................................................... 34 41110 Bridge Clock Timings....................................................................................................... 35 41110 Bridge Thermal Specifications ......................................................................................... 38 Torsional Clip Heatsink Thermal Solution .................................................................................. 38 Signal List, sorted by Ball Name................................................................................................. 41 Signal List, sorted by Signal Name............................................................................................. 45 Contents Revision History Date Revision Description February 2006 002 Updated Product Features section, Copyright page, Section 2.6, and several tables. January 2006 001 Initial release. 5 Contents This page intentionally left blank. 6 Datasheet -- 41110 Bridge Introduction 1.1 1 About This Document This document provides information on the Intel(R) 41110 Serial to Parallel PCI Bridge, including a functional overview, signal descriptions, mechanical data, package signal location and bus functional waveforms. 1.2 Product Overview The Intel(R) 41110 Serial to Parallel PCI Bridge (also called the 41110 Bridge) integrates one PCI Express to PCI/PCI-X bridge. The bridge follows the PCI-to-PCI Bridge programming model. The PCI Express port is compatible with the PCI Express Specification, Revision 1.0a. The PCI interface is compatible with the PCI Local Bus Specification, Revision 2.3 and PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b. 7 41110 Bridge -- Datasheet Signal Description 2 The "#" symbol at the end of a signal name indicates that the active, or asserted state, occurs when the signal is at a low voltage level. When "#" is not present after the signal name, the signal is asserted when at the high voltage level. The following notations are used to describe the signal type: 2.1 I: Input pin O: Output pin OD: Open-drain Output pin I/O: Bidirectional Input/Output pin I/OD: Bidirectional Input/Open-drain Output pin On Die Termination (ODT) The 41110 Bridge incorporates on-die termination for most of the PCI interface signals. This eliminates the need for the system designer to incorporate external pull-up resistors in the design. The following signals have an on die termination of 8.33K +40%: Table 1. ODT Signals A_ACK64# A_AD[63:32] A_CBE#[7:4] A_DEVSEL# A_FRAME# A_GNT#[5:0] A_IRDY# A_PAR A_PAR64 A_PERR# A_LOCK# A_REQ#[5:0] A_REQ64# A_SERR# A_STOP# A_TRDY# A_INTA# 8 Datasheet -- 41110 Bridge A_ACK64# A_INTB# A_INTC# A_INTD# TCK TDI TDO TMS 2.2 PCI Express Interface Table 2. PCI Express Interface Pins Signal REFCLKp/ REFCLKn I/O I Description PCI Express Reference Clocks: 100 MHz differential clock pair. PCI Express Serial Data Transmit: PCI Express differential data transmit signals. PETp[7:0]/ PETn[7:0] O X8 Mode: All PETp[7:0]/ PETn[7:0] are used X4 Mode: Only PETp[3:0]/ PETn[3:0] are used x1 Mode: Either PETp[0]/ PETn[0] is used or PETp[7]/ PETn[7] is used PCI Express Serial Data Receive: PCI Express differential data receive signals. PERp[7:0]/ PERn[7:0] I X8 Mode: All PERp[7:0]/ PERn[7:0] are used X4 Mode: Only PERp[3:0]/ PERn[3:0] are used x1 Mode: Either PERp[0]/ PERn[0] is used or PERp[7]/ PERn[7] is used PE_RCOMP[1:0] I Total 36 PCI Express Compensation Inputs: Analog signals. Connect to a 24.91% pull-up resitor to 1.5V. A single resistor can be used for both signals. 9 41110 Bridge -- Datasheet 2.3 PCI Bus Interface Table 3. PCI Interface Pins (Sheet 1 of 2) Signal A_AD[31:0] I/O Description I/O PCI Address/Data: These signals are a multiplexed address and data bus. During the address phase or phases of a transaction, the initiator drives a physical address on A_AD[31:0]. During the data phases of a transaction, the initiator drives write data, or the target drives read data. No External pull-up resistors are required on the system board for these signals. A_C/BE#[3:0] I/O Bus Command and Byte Enables: These signals are a multiplexed command field and byte enable field. During the address phase or phases of a transaction, the initiator drives the transaction type on C/BE#[3:0]. When there are two address phases, the first address phase carries the dual address command and the second address phase carries the transaction type. For both read and write transactions, the initiator drives byte enables on C/BE#[3:0] during the data phases. No External pull-up resistors are required on the system board for these signals. A_PAR I/O Parity: Even parity calculated on 36 bits - AD[31:0] plus C/BE[3:0]#. It is calculated on all 36 bits regardless of the valid byte enables. It is generated for address and data phases. It is driven identically to the AD[31:0] lines, except it is delayed by exactly one PCI clock. It is an output during the address phase for all 41110 Bridge initiated transactions and all data phases when the 41110 Bridge is the initiator of a PCI write transaction, and when it is the target of a read transaction. 41110 Bridge checks parity when it is the initiator of PCI read transactions and when it is the target of PCI write transactions. No External pull-up resistors are required on the system board for these signals. A_DEVSEL# I/O Device Select: The bridge asserts DEVSEL# to claim a PCI transaction. As a target, the 41110 Bridge asserts DEVSEL# when a PCI master peripheral attempts an access an address destined for PCI Express. As an initiator, DEVSEL# indicates the response to a 41110 Bridge initiated transaction on the PCI bus. DEVSEL# is tri-stated from the leading edge of A_RST#. DEVSEL# remains tri-stated by the 41110 Bridge until driven as a target. No External pull-up resistors are required on the system board for these signals. A_FRAME# I/O Frame: FRAME# is driven by the Initiator to indicate the beginning and duration of an access. While FRAME# is asserted data transfers continue. When FRAME# is negated the transaction is in the final data phase. No External pull-up resistors are required on the system board for these signals. A_IRDY# I/O Initiator Ready: IRDY# indicates the ability of the initiator to complete the current data phase of the transaction. A data phase is completed when both IRDY# and TRDY# are sampled asserted. No External pull-up resistors are required on the system board for these signals. A_TRDY# I/O Target Ready: Indicates the ability of the target to complete the current data phase of the transaction. A data phase is completed when both TRDY# and IRDY# are sampled asserted. TRDY# is tri-stated from the leading edge of RST#. TRDY# remains tri-stated by the 41110 Bridge until driven as a target. No External pull-up resistors are required on the system board for these signals. A_STOP# A_PERR# I/O I/O Stop: Indicates that the target is requesting an initiator to stop the current transaction. No External pull-up resistors are required on the system board for these signals. Parity Error: Driven by an external PCI device when it receives data that has a parity error. Driven by 41110 Bridge when, as a initiator it detects a parity error during a read transaction and as a target during write transactions. No External pull-up resistors are required on the system board for these signals. A_SERR# I System Error: The 41110 Bridge samples SERR# as an input and conditionally forwards it to the PCI Express. No External pull-up resistors are required on the system board for these signals. 10 Datasheet -- 41110 Bridge Table 3. PCI Interface Pins (Sheet 2 of 2) Signal I/O A_REQ#[5:0] I A_GNT#[5:0] O Description PCI Requests: REQ# receives request inputs into the internal arbiter. No External pull-up resistors are required on the system board for these signals. PCI Grants: GNT# is the bus grant output corresponding to request input bits[5:0] from the internal arbiter. GNT# indicates that an initiator can start a transaction on the PCI bus. No External pull-up resistors are required on the system board for these signals. A_M66EN I/OD 66 MHz Enable: This input signal from the PCI Bus indicates the speed of the PCI Bus. If it is high then the Bus speed is 66 MHz and if it is low then the bus speed is 33 MHz. This signal will be used to generate appropriate clock (33 or 66 MHz) on the PCI Bus. Use an approximately 8.2K resistor to pull to VCC33 or pull-down to ground. A_PCIXCAP A_LOCK# I O PCI-X Capable: Indicates whether all devices on the PCI bus are PCI-X devices, so that the 41110 Bridge can switch into PCI-X mode. Use an approximately 8.2K resistor to pull to VCC33. PCI Lock: Indicates an exclusive bus operation and may require multiple transactions to complete. This signal is an output from the bridge when it is initiating exclusive transactions on PCI. LOCK# is ignored when PCI masters are granted the bus. Locked transaction do not propagate upstream. No External pull-up resistors are required on the system board for these signals. Total 59 2.4 PCI Bus Interface 64-Bit Extension Table 4. PCI Interface Pins: 64-Bit Extensions Signal A_AD[63:32] A_C/BE#[7:4] I/O I/O I/O Description PCI Address/Data: These signals are a multiplexed address and data bus. This bus provides an additional 32 bits to the PCI bus. During the data phases of a transaction, the initiator drives the upper 32 bits of 64-bit write data, or the target drives the upper 32 bits of 64-bit read data, when REQ64# and ACK64# are both asserted. Bus Command and Byte enables upper 4 bits: These signals are a multiplexed command field and byte enable field. For both reads and write transactions, the initiator will drive byte enables for the AD[63:32] data bits on C/BE7:4] during the data phases when REQ64# and ACK64# are both asserted. A_PAR64 A_REQ64# A_ACK64# Total I/O PCI interface upper 32 bits parity: This carries the even parity of the 36 bits of AD[63:32] and C/ BE#[7:4] for both address and data phases. I/O PCI interface request 64-bit transfer: This is asserted by the initiator to indicate that the initiator is requesting a 64-bit data transfer. It has the same timing as FRAME#. When the 41110 Bridge is the initiator, this signal is an output. When the 41110 Bridge is the target this signal is an input. I/O PCI interface acknowledge 64-bit transfer: This is asserted by the target only when REQ64# is asserted by the initiator, to indicate the target ability to transfer data using 64 bits. It has the same timing as DEVSEL#. 39 11 41110 Bridge -- Datasheet 2.5 PCI Bus Interface Clocks and, Reset and Power Management Table 5. PCI Clock and Reset Pins Signal A_CLKO[6:0] I/O O Description PCI Clock Output: 33/66/100/133 MHz clock for a PCI device. A_CLK[6] must be connected to the respective A_CLKIN input. for feeding the PCI interface logic. Unused clock outputs may be disabled via the "Offset 43: PCLKC - PCI Clock Control" register and should be treated as no connects on the board. Note: A_CLKIN A_RST# A_PME# Registers are listed in the Intel(R) 41110 Serial to Parallel PCI Bridge Developer's Manual. I PCI Clock In: This signal is PCI clock feedback input. This pin should be connected to the corresponding A_CLKO[6] through a 221% series resistor. O PCI Reset: The bridge asserts RST# to reset devices that reside on the secondary PCI bus. I PCI Power Management Event: PCI bus power management event signal. This is a shared open drain input from all the PCI cards on the corresponding PCI bus segment. This is a level sensitive signal that will be converted to a PME event on PCI Express. This pin does not have on-die 8.3K pull-up. This pull-up must be provided externally. Total 2.6 10 Interrupt Interface This section lists the interrupt interface signals. There is one set of interrupt signals for the standard INTA:INTD PCI signals. Table 6. Signal A_INTA# A_INTB# A_INTC# A_INTD# Total 2.7 Interrupt Interface Pins I/O I Description Interrupt Request Bus: The interrupt lines from PCI interrupts INTA#:INTD# can be routed to these interrupt lines. Refer to the Intel(R) 41110 Serial to Parallel PCI Bridge Design Guide for more information on device numbering. 4 Reset Straps The following signals are used for static configuration. These signals are all sampled on the rising edge of PERST#. 12 Datasheet -- 41110 Bridge Table 7. Reset Strap Pins Signal A_133EN I/O Description I PCI-X 133 MHz Enable: This pin, when high, allows the PCI-X segment to run at 133 MHz when A_PCIXCAP is sampled high. When low, the PCI-X segment will only run at 100 MHz when A_PCIXCAP is sampled high. Use an approximately 8.2K resistor to pull to VCC33 or pull-down to ground. Internal Test Modes: Straps 6, 2:0 should be pulled low and straps 5:3 must be pulled high for normal operation. A_STRAP A_STRAP[6:0] I 0 1 2 3 4 5 6 Logic Level `0' `0' `0' `1' `1' `1' `0' Use approximately an 8.2K resistor to pull-up to VCC33 or pull-down to VSS A_TEST[2:1] CFGRETRY I I Internal Test Modes: These straps should be pulled high to VCC33. Use approximately an 8.2K resistor to pull-up to VCC33. Configuration Retry: This pin, when sampled high sets the Configuration Cycle Retry Bit (bit 3) in the Bridge Initialization Register at Offset FC. If no local initialization is needed, this pin should be pulled low to VSS. Refer to the Intel(R) 41110 Serial to Parallel PCI Bridge Design Guide for more information. STRAP_V_1 I Pull up to VCC33 STRAP_V_2 I Pull up to VCC33 STRAP_V_3 I Pull up to VCC33 STRAP_V_4 I Pull up to VCC33 STRAP_V_5 I Pull up to VCC33 STRAP_V_6 I Pull up to VCC33 STRAP_V_7 I Pull up to VCC33 STRAP_V_8 I Pull up to VCC33 STRAP_V_9 I Pull up to VCC33 STRAP_V_10 I Pull up to VCC33 STRAP_V_11 I Pull up to VCC33 STRAP_V_12 I Pull up to VCC33 STRAP_V_13 I Pull up to VCC33 STRAP_V_14 I Pull up to VCC33 STRAP_V_15 I Pull down to GND Total 27 13 41110 Bridge -- Datasheet 2.8 SMBus Interface Table 8. SMBus Interface Pins Signal I/O Description SMBCLK I/OD SMBus Clock: This signal should be pulled to 3.3V via an 8.2K resistor. SMBDAT I/OD SMBus Data: This signal should be pulled to 3.3V via an 8.2K resistor. SMBus Addressing Straps: These straps set the SMBus Address for 41110 Bridge. The address is determined as indicated below: SMBUS[5] SMBUS[3:1] I Bit 7 `1' Bit 6 `1' Bit 5 SMBUS[5] Bit 4 `0' Bit 3 SMBUS[3] Bit 2 SMBUS[2] Bit 1 SMBUS[1] These signals (bits 5, 3:1) should be pulled up to 3.3V or down to ground. Sampled at the rising edge of PERST#. Total 6 2.9 Miscellaneous Pins Table 9. Miscellaneous Pins Signal CFGRST# I/O Description O Configuration Reset: This signal is asserted low when ever the bridge goes through a fundamental reset (PERST#, RSTIN#, or PCI Express Reset). This signal should be used to indicate when the local initialization methods should be executed. Refer to the Intel(R) 41110 Serial to Parallel PCI Bridge Design Guide for more information. 14 PERST# I PCI Express Fundamental Reset: When low, asynchronously resets the internal logic (including sticky bits). RSTIN# I Reset In: When Asserted, this signal asynchronously resets the internal logic and asserts A_RST# output. This signal should be pulled high for adapter card usage. TCK I TAP Clock In: This is the input clock to the JTAG TAP controller. Acceptable frequency is 0-16MHz If not utilizing JTAG, this signal can be left as a no connect. TDI I Test Data In: This is the serial data input to the JTAG BSCAN shift register chain and to the JTAG BSCAN control logic. This is latched in on the rising edge of TCK. If not utilizing JTAG, this signal can be left as a no connect. TDO O Test Data Output: This is the serial data output from the JTAG BSCAN logic If not utilizing JTAG, this signal can be left as a no connect. Datasheet -- 41110 Bridge Signal I/O Description TMS I Test Mode Select: This signal controls the TAP controller state machine to move to different states and is sampled on the rising edge of TCK. If not utilizing JTAG, this signal can be left as a no connect. TRST# I Test Reset In: This signal is used to asynchronously reset the JTAG BSCAN logic. If not utilizing JTAG, connect this signal to ground through a 1K pulldown resistor. RESERVED[8:1] I Reserved: (8 pins) These input pins should be pulled low Use an approximately 8.2K resistor to pull-down to ground. NC[19:18], NC[16:1] A_NC[10:1] O No Connect: (39 pins) These output pins should be left floating RESERVED O No Connect RESERVED O No Connect CMODE I/O This signal requires an external pull-up, 8.2K to 3.3V Total 47 15 41110 Bridge -- Datasheet Electrical and Thermal Characteristics 3 3.1 DC Voltage and Current Specifications 3.1.1 41110 Bridge DC Specifications Table 10. Intel(R) 41110 Bridge DC Voltage Specifications Symbol Parameter Min Typ Max Unit VCC15 Intel(R) 41110 Bridge Core 1.425 1.5 1.575 V VCC15 PCI-X I/O Voltage 1.425 1.5 1.575 V VCCAPE Analog PCI Express Voltage 1.455 1.5 1.545 V VCCAPCI[2:0] Analog PCI Voltages 1.455 1.5 1.545 VCCBGPE Analog Bandgap Voltage 2.425 2.5 2.575 VCCPE PCI Express Interface Voltage 1.46 1.5 1.55 V VCC33 PCI Bus Interface Voltage 3.0 3.3 3.6 V PTDP Thermal Design Power 8 W Notes 1 2 1. Transient tolerance 5 mV above 1 MHz at package pin under DC load conditions. 2. Transient tolerance 10 mV above 1 MHz at package pin under DC load conditions. 3.2 41110 Bridge Power Consumption Table 11 provides details on the maximum draw from the power planes by the 41110 Bridge for use in voltage regulation. Table 11. 41110 Bridge Maximum Voltage Plane Currents Power Plane Maximum Voltage Plane Current (Amps) Frequency (MHz) 133 100 66 Number of Slots 1 2 4 IVCC15 (core 1.5V) 1.68 1.61 1.55 IVCC15 (I/O 1.5V) 0.22 0.22 0.22 IVCCPE (PCI Express 1.5V) 0.69 0.69 0.69 IVCC33 (PCI/PCI-X Mode 1 3.3V) 1.05 1.14 1.22 Table 12 provides details on the maximum nominal draw from the power planes by the 41110 Bridge for use in thermal design. 16 Datasheet -- 41110 Bridge Table 12. 41110 Bridge Thermal Voltage Plane Currents Power Plane Table 13. 3.3 Thermal Voltage Plane Current (Amps) Frequency (MHz) 133 100 66 Number of Slots 1 2 4 IVCC15 (core 1.5V) 1.24 1.18 1.11 IVCC15 (I/O 1.5V) 0.22 0.22 0.22 IVCCPE (PCI Express 1.5V) 0.69 0.69 0.69 IVCC33 (PCI/PCI-X Mode 1 3.3V) 0.99 1.04 1.10 Watts Frequency (MHz) 133 100 66 Max Watts 6.9 7 7.1 Power Delivery Guidelines Please refer to the Intel(R) 41110 Serial to Parallel PCI Bridge Design Guide. 17 41110 Bridge -- Datasheet 3.4 Input Characteristic Signal Association Table 14. DC Characteristics Input Signal Association Symbol Signals Interrupt Signals: A_INTx (X = A-D)#, VIH1/VIL1 PCI Signals: A_AD[63:0], A_CBE[7:0]#, A_PAR, A_DEVSEL#, A_FRAME#, A_IRDY#, A_TRDY#, A_STOP#, A_PERR#, A_SERR#, A_REQ[5:0]#, A_M66EN, A_133EN, A_PCIXCAP, A_PAR64, A_REQ64#, A_ACK64#, Clock Signals (3.3 V Only): A_CLKI, Miscellaneous Signals: PERST# VIH2/VIL2 PCI Express Signals: REFCLK, REFCLK#, PETP[7:0], PETN[7:0], PE_RCOMP[1:0] VIH3/VIL3 SMB Signals: SMBDAT, SMBCLK 3.5 DC Input Characteristics Table 15. DC Input Characteristics 3.3 V Signal Symbol Parameter Unit Min Max VIL1 Input Low Voltage -0.5 0.35 VCC33 V VIH1 Input High Voltage 0.5 VCC33 VCC33 +0.5 V Symbol Parameter Max VIL2 Input Low Voltage N/A V VIH2 Input High Voltage N/A V VIL3 Input Low Voltage 0.6 V VIH3 Input High Voltage VCC33 + 0.5 V 3.6 DC Characteristic Output Signal Association Table 16. DC Characteristic Output Signal Association Symbol VOH1/VOL1 Signals PCI Signals: A_AD[63:0], A_CBE[7:0]#, A_PAR, A_DEVSEL#, A_FRAME#, A_IRDY#, A_TRDY#, A_STOP#, A_PERR#, A_M66EN, A_GNT[6:0]#, A_LOCK#, A_PAR64, A_REQ64#, A_ACK64#, PCI Clock Signals (3.3 V Only): A_CLKO[6:0], A_RST#, Miscellaneous Signals: CFGRST 18 VOH2/VOL2 PCI Express Signals: PERP[7:0], PERN[7:0] VOH3/VOL3 SMBus Signals: SMBDAT, SMBCLK Datasheet -- 41110 Bridge 3.7 DC Output Characteristics Table 17. DC Output Characteristic 3.3 V Signal Symbol Parameter Unit Min VOL1 Output Low Voltage VOH1 Output High Voltage Symbol 0.1VCC33 (5 V) Iout = 6 mA V 0.9VCC33 Parameter Notes Max (3.3 V) Iout = 1500 uA (5 V) Iout = -2 mA V Max (3.3 V) Iout = -500 uA Unit Notes VOL2 Output Low Voltage N/A V VOH2 Output High Voltage N/A V VOL3 Output Low Voltage 0.4 V IOL4=14 mA VOH3 Output High Voltage N/A V Open Drain 3.8 PCI Express Interface DC Specifications 3.8.1 Differential Transmitter (TX) DC Output Specifications Table 18 defines the DC specifications of parameters for the differential output at all transmitters (TXs). The parameters are specified at the component pins. Table 18. Differential Transmitter (TX) DC Output Specifications (Sheet 1 of 2) Symbol Parameter Min VTX-DIFFp-p Differential Peak to Peak Output Voltage 0.80 VTX-DE-RATIO De-Emphasized Differential Output Voltage (Ratio) -3.0 Nom -3.5 Max Units 1.2 V -4.0 dB Comments VTX-DIFFp-p = 2*|VTX-D+-VTX-D-| See Note 1. This is the ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a transition See Note 1. VTX-CM-ACp VTX-CM-ACp = CM-DC AC Peak Common Mode Output Voltage 20 mV |VTX-D+ + vTX-D-| / 2 - vTX- vTX-CM-DC = DC(avg) of / 2 during L0 |VTX-D+ + VTX-D-| See Note 1. VTX-CM-DCACTIVE-IDLEDELTA Absolute Delta of DC Common Mode Voltage During L0 and Electrical Idle |VTX-CM-DC [during L0] - VTX-CM-IdleDC[during electrical idle]| <= 100mv 0 100 mV VTX-CM-DC = DC(avg) of |VTX-D+ + VTX-D-| / 2 [electrical idle] See Note 1. 19 41110 Bridge -- Datasheet Table 18. Differential Transmitter (TX) DC Output Specifications (Sheet 2 of 2) |VTX-CM-DC-D+ [during L0] - VTX-CM-DC-D[During L0.]|<=25mV VTX-CM-DCLINE-DELTA Absolute Delta of DC Common Mode Voltage between D+ and D-. VTX-CM-DC-D+ = DC(avg) of |VTX-D+| 0 25 mV [during L0] VTX-CM-DC-D- = DC(avg) of |VTX-D-| [during L0] See Note 1. VTX-IDLEDIFFp VTX-RCVDETECT Electrical Idle Differential Peak Output Voltage 0 20 mV VTX-IDLE-DIFFp =|VTX-Idle-D+ -VTx-Idle-D|<=20mV See Note 1. The amount of voltage change allowed during Receiver Detection. 600 mV The total amount of voltage change that a transmitter can apply to sense whether a low impedance receiver is present. RLTX-DIFF Differential Return Loss 12 dB Measured over 50 MHz to 1.25 GHz See Note 2. RLTX-CM Common Mode Return Loss 6 dB Measured over 50 MHz to 1.25 GHz See Note 2. ZTX-DIFF-DC DC Differential TX Impedance 80 120 Ohms TX DC Differential Mode Low impedance 5k 20k Ohms TX DC High Impedance. IMP-DC Transmitter Common Mode High Impedance State (DC) CTX AC Coupling Capacitor 75 200 nF All transmitters shall be AC coupled. The AC coupling is required either within the media or within the transmitting component itself. ZTX-COMHigh- 100 1. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 2, "Compliance Test/Measurement Load" on page 23 and measured over any 250 consecutive TX UIs. (Also refer to the Transmitter Compliance Eye Diagram as shown in Minimum Transmitter Timing and Voltage Output Compliance Specification.) 2. The transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss measurements is 50W to ground for both the D+ and D- line (i.e., as measured by a Vector Network Analyzer with 50W probes - see Figure 2). Note that the series capacitors CTX is optional for the return loss measurement. 20 Datasheet -- 41110 Bridge 3.8.2 Differential Receiver (RX) DC Input Specifications Table 19 defines the DC specifications of parameters for all differential Receivers (RXs). The parameters are specified at the component pins. Table 19. Differential Receiver (RX) DC Input Specifications Symbol VRX-DIFFp-p VRX-CM-ACp Parameter Min Differential Input Peak to Peak Voltage 0.175 Nom Max Units 1.200 V Comments VRX-DIFFp-p = 2*|VRX-D+ - VRX-D-| See Note 1. VRX-CM-AC= |VRX-D+ + VRX-D-|/2- VRX-CM-DC AC Peak Common Mode Input Voltage 150 mV VRX-CM-DC = DC(avg) of |VRX-D++VRX-D-|/2 during L0 See Note 1. RLRX-DIFF Differential Return Loss 15 dB RLRX-CM Common Mode Return Loss 6 dB ZRX-DIFF-DC DC Differential Input Impedance 80 DC Input Common Mode Input Impedance 40 Initial DC Input Common Mode Input Impedance 5 ZRX-COM-DC ZRX-COM-INITIAL-DC ZRX-COM-HIGH-IMP-DC VRX-IDLE-DET-DIFFp-p 100 120 Ohms Measured over 50 MHz to 1.25 GHz See Note 2. Measured over 50 MHz to 1.25 GHz See Note 2 RX DC Differential Mode impedance. See Note 3. 50 60 Ohms RX DC Common Mode impedance 50 ?+/-20% tolerance. See Notes 1 and 3. 50 60 Ohms RX DC Common Mode impedance allowed when the receiver terminations are first powered on. See Note 4. Powered Down DC Input Common Mode Input Impedance 200 k Electrical Idle Detect Threshold 65 Ohms RX DC Common Mode impedance when the receiver terminations are not powered (i.e., no power). See Note 5. 175 mV VRX-IDLE-DET-DIFFp-p =2*|VRX-D+ VRX-D-| Measured at the package pins of the Receiver. 1. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 2, "Compliance Test/Measurement Load" on page 23 should be used as the RX device when taking measurements (also refer to the Receiver Compliance Eye Diagram as shown in Figure 3, "Minimum Receiver Eye Timing and Voltage Compliance Specification" on page 23). If the clocks to the RX and TX are not derived from the same clock chip the TX UI must be used as a reference for the eye diagram. 2. The receiver input impedance shall result in a differential return loss greater than or equal to 15 dB and a common mode return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss measurements for is 50 to ground for both the D+ and D- line (i.e., as measured by a Vector Network Analyzer with 50 probes - see Figure 2). Note: that the series capacitors CTX is optional for the return loss measurement. 3. Impedance during all operating conditions. 4. The Rx DC Common Mode Impedance that must be present when the receiver terminations are first enabled to ensure that the Receiver Detect occurs properly. Compensation of this impedance can start immediately and the (ZRX-COM-DC)RxDC Common Mode Impedance must be with in the specified range by the time Detect is entered. 21 41110 Bridge -- Datasheet 5. The Rx DC Common Mode Impedance that exists when the receiver terminations are disabled or when no power is present. This helps ensure that the Receiver Detect circuit will not falsely assume a receiver is powered on when it is not. Figure 1. Minimum Transmitter Timing and Voltage Output Compliance Specification There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in time using the jitter median to locate the center of the eye diagram. The different eye diagrams will differ in voltage depending whether it is a transition bit or a de-emphasized bit. The eye diagram must be valid for any 250 consecutive UIs. An appropriate average TX UI must be used as the interval for measuring the eye diagram. 3.8.3 Compliance Test and Measurement Load The AC timing and voltage parameters must be verified at the measurement point, as specified by the device vendor within 0.2 inches of the package pins, into a test/measurement load shown in Figure 2. Note: 22 The allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from D+ and D- not being exactly matched in length at the package pin boundary. If the vendor does not explicitly state where the measurement point is located, the measurement point is assumed to be the D+ and D-package pins. Datasheet -- 41110 Bridge Figure 2. Compliance Test/Measurement Load The test load is shown at the transmitter package reference plane, but the same Test/Measurement load is applicable to the receiver package reference plane. CTX is an optional portion of the measurement test load. The measurement should be taken on the opposite side of the capacitor from the package, and the value of the CTX must be in the range of 75 nF to 200 nF. . Figure 3. Minimum Receiver Eye Timing and Voltage Compliance Specification The RX eye diagram must be aligned in time using the jitter median to locate the center of the eye diagram. The eye diagram must be valid for any 250 consecutive UIs. An appropriate average TX UI must be used as the interval for measuring the eye diagram. 23 41110 Bridge -- Datasheet 3.8.4 PCI and PCI-X Interface DC Specifications Table 20 summarizes the DC specifications for 3.3V signaling. Table 20. DC Specifications for PCI and PCI-X 3.3 V Signaling Symbol Parameter Min Max Units VCC33 Supply Voltage 3.0 3.6 V Vih Input High Voltage 0.5 VCC33 VCC33 +0.5 V Vil Input Low Voltage -0.5 0.3VCC33 V Vipu Input Pull-up Voltage 0.7VCC33 Iil Input Leakage Current Voh Output High Voltage Vol Output Low Voltage Cin Input Pin Capacitance Notes V 10 A 0 < Vin < VCC33 V Iout = -500 A 0.1VCC33 V Iout = 1500 A 10 pF 0.9VCC33 5 Condition 1 2 Cclk A_CLKIN Pin Capacitance 8 pF CIDSEL IDSEL Pin Capacitance 8 pF 3 Lpin Pin Inductance 20 nH 4 IOff A_PME# input leakage 1 A - Vo 3.6 VCC33 off or floating 5 1. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs. 2. Absolute maximum pin capacitance for a PCI/PCIX input except A_CLKIN and A_IDSEL. 3. For conventional PCI only, lower capacitance on this input-only pin allows for non-resistive coupling to A_AD[xx]. PCI-X configuration transactions drive the AD bus four clocks before A_FRAME# asserts (see Section 2.7.2.1, "Configuration Transaction Timing," in the PCI-X Protocol Addendum to the PCI Local Bus Specification Revision 2.0a). 4. For conventional PCI, this is a recommendation, not an absolute requirement. For PCI-X, this is a requirement. 5. This input leakage is the maximum allowable leakage into the A_PME# open drain driver when power is removed from VCC33 of the component. This assumes that no event has occurred to cause the device to attempt to assert A_PME#. 24 Datasheet -- 41110 Bridge 3.8.4.1 Input Clock DC Specifications Table 21. DC Specification for Input Clock Signals Symbol CLK100 Parameter Input Low Voltage Min Max -0.5 Units 0.8 V CLK100 Input High Voltage 2.0 VCC3.3 + 0.5 V CLK133 Input Low Voltage -0.5 0.8 V CLK133 Input High Voltage 2.0 VCC3.3 + 0.5 V Units Condition 3.8.4.2 Output Clock DC Specifications Table 22. DC Specification for Output Clock Signals Symbol Parameter CLK33 Output Low Voltage CLK33 Output High Voltage CLK66 Output Low Voltage CLK66 Output High Voltage CLK100 Output Low Voltage CLK100 Output High Voltage CLK133 Output Low Voltage CLK133 Output High Voltage 2.4 0.4 2.4 0.4 2.4 0.4 2.4 AC Specifications 3.9.1 PCI and PCI-X AC Characteristics Table 23. Conventional PCI 3.3V AC Characteristics Ioh(AC) Parameter Switching Current High Iol(AC) Switching Current Low Ich Icl Max 0.4 3.9 Sym Min Condition Min Vout = 0.7VCC33 Vout = 0.3VCC33 V Iol = 1 mA V Ioh= -1 mA V Iol = 1 mA V Ioh= -1 mA V Iol = 1 mA V Ioh= -1 mA V Iol = 1 mA V Ioh= -1 mA Max -32VCC33 -12VCC33 Vout = 0.18VCC33 Unit mA mA 38VCC33 1 mA Vout = 0.6VCC33 16VCC33 mA High Clamp Current VCC33 + 4 > Vin VCC33 + 1 25 + (Vin - VCC33 - 1) / 0.015 mA Low Clamp Current -3 < Vin -1 -25 + (Vin + 1) / Note 1 mA 0.015 slewr Output Rise Slew Rate 0.3VCC33 to 0.6VCC33 1 4 V/ns 2 slewf Output Fall Slew Rate 0.6VCC33 to 0.3VCC33 1 4 V/ns 2 25 41110 Bridge -- Datasheet 1. In conventional PCI switching, current characteristics for A_REQ# and A_GNT# are permitted to be one half of that specified here; i.e., half size drivers may be used on these signals. This specification does not apply to CLK and RSTIN# which are system outputs. "Switching Current High" specifications are not relevant to A_SERR# which is an open drain output. 2. This parameter is to be interpreted as the cumulative edge rate across the specified range rather than the instantaneous rate at any point within the transition range. For more details on slew rate measurement conditions please refer to the PCI-X Electrical and Mechanical Addendum to the PCI Local Bus Specification, Revision 2.0a Table 24. PCI-X 3.3V AC Characteristics Sym Parameter Condition Min -74(VCC33 Vout) 0 < VCC33 - Vout 3.6V Ioh(AC) Switching Current High Icl Ich Switching Current Low Low Clamp Current Unit Note mA 0 < VCC33 - Vout 1.2V -32 (VCC33 - Vout) mA 1 1.2V < VCC33 - Vout 1.9V -11 (VCC33 Vout) - 25.2 mA 1 1.9V < VCC33 - Vout 3.6V -1.8 (VCC33 Vout) - 42.7 mA 1 0 Vout 3.6V Iol(AC) Max 100Vout mA 0 < Vout 1.3V 48Vout 1 1.3V < Vout 3.6V 5.7Vout + 55 1 -3V < Vin 0.8875V -40 + (Vin + 1) / 0.005 mA -0.8875V < Vin -0.625V -25 + (Vin + 1) / 0.015 mA 0.8875V < Vin - VCC33 -4V 40 + (Vin - VCC33 - 1) / 0.005 mA 0.625V < Vin - VCC33 0.8875V 25 + (Vin - VCC33 - 1) / 0.015 mA High Clamp Current slewr Output Rise Slew Rate 0.3VCC33 to 0.6VCC33 1 4 V/ns 2 slewf Output Fall Slew Rate 0.6VCC33 to 0.3VCC33 1 4 V/ns 2 1. In conventional PCI switching, current characteristics for A_REQ# and A_GNT# are permitted to be one half of that specified here; i.e., half size drivers may be used on these signals. This specification does not apply to CLK and RST# which are system outputs. "Switching Current High" specifications are not relevant to A_SERR#, which is an open drain output. 2. This parameter is to be interpreted as the cumulative edge rate across the specified range rather than the instantaneous rate at any point within the transition range. For more details on slew rate measurement conditions please refer to the PCI-X Electrical and Mechanical Addendum to the PCI Local Bus Specification, Revision 2.0a. 3.10 Voltage Filter Specifications The 41110 Bridge requires voltage filtering to reduce noise on critical voltage planes. There are two filter types necessary on the platform: 26 Datasheet -- 41110 Bridge * Analog Voltage Filter (PCI-Express and PCI) * Bandgap Filter Note: For filter specifications, refer to the Intel(R) 41110 Serial to Parallel PCI Bridge Design Guide. 3.11 VCC15 and VCC33 Voltage Requirements The 41110 Bridge requires that the VCC33 voltage rail be equal to or no less than 0.5V below VCC15 (absolute voltage value) at all times during 41110 Bridge operation, including during system power up and power down. In other words, the following must always be true: VCC33 (VCC15 -0.5V) Figure 4 graphically illustrates this requirement. This can be accomplished by placing a diode (with a voltage drop < 0.5V) between VCC15 and VCC33. Anode will be connected to VCC15 and cathode will be connected to VCC33. Figure 4. Voltage Requirements VCC33 versus VCC15 27 41110 Bridge -- Datasheet 3.12 Timing Specifications 3.12.1 PCI Express Interface Timing 3.12.1.1 Differential Transmitter (TX) AC Output Specifications Table 25 defines the AC specifications of parameters for the differential output at all transmitters (TXs). The parameters are specified at the component pins. Table 25. Differential Transmitter (TX) AC Output Specifications Symbol UI Parameter Unit Interval Min 399.88 Nom 400 Max 400.12 Units ps Comments Each UI is 400 ps +/300 ppm. UI does not account for SSC dictated variations. See Note 1. TTX-EYE Minimum TX Eye Width 0.70 UI The maximum transmitter jitter can be derived as TTX-MAXJITTER = 1 - TTX-EYE = .3 UI See Notes 2 and 3. TTX-EYE-MEDIAN-to-MAX-JITTER Maximum time between the jitter median and maximum deviation for the median TTX-RISE, TTX-FALL D+/D- TX Output Rise/Fall Time TTX-IDLE-MIN Minimum time spent in Electrical Idle TTX-IDLE-SETTO-IDLE TTX-IDLE-RCVDETECT-MAX LTX-SKEW UI Jitter is defined as the measurement variation of the crossing points (VTX-DIFFp-p = 0V) in relation to an appropriate average TX UI. See Notes 2 and 3. 0.125 UI See Notes 2 and 4. 50 UI Minimum time a transmitter must be in electrical idle. 0.15 Maximum time to transition to a valid Electrical Idle after sending an Electrical Idle ordered-set 20 UI After sending an electrical idle orderedset, the transmitter must meet all electrical idle specifications within this time. Maximum time spent in Electrical Idle before initiating a receiver detect sequence. 100 ms Maximum time spent in Electrical Idle before initiating a receiver detect sequence. Lane-to-Lane Output Skew 500 ps Between any two Lanes within a single Transmitter. 1. No test load is necessarily associated with this value. 2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 2, "Compliance Test/Measurement Load" on page 23 and measured over any 250 consecutive TX UIs. (Also 28 Datasheet -- 41110 Bridge refer to the Transmitter Compliance Eye Diagram as shown in Minimum Transmitter Timing and Voltage Output Compliance Specification.) 3. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the transmitter collected over any 250 consecutive TX UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. 4. Measured between 20-80% at Transmitter package pins into a test load as shown in Figure 2 for both VTX-D+ and VTX-D-. 3.12.1.2 Differential Receiver (RX) AC Input Specifications Table 26 defines the AC specifications of parameters for all differential Receivers (RXs). The parameters are specified at the component pins. Table 26. Differential Receiver (RX) AC Input Specifications Symbol UI TRX-EYE Parameter Unit Interval Minimum Receiver Eye Width Min 399.88 Nom 400 Max 400.12 0.4 Units ps UI Comments The UI is 400 ps +/-300 ppm. UI does not account for SSC dictated variations. See Note 1. The maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived asTRX-MAX-JITTER =1 -TRXEYE =0.6 UI See Notes 2 and 3. TRX-EYEMEDIAN-to- MAX-JITTER TRX-IDLE-DETDIFF- ENTERTIME LRX-SKEW Maximum time between the jitter median and maximum deviation from the median. Unexpected Electrical Idle Enter Detect Threshold Integration Time Total Skew 0.3 UI Jitter is defined as the measurement variation of the crossing points (VRX- DIFFp-p = 0 V) in relation to an appropriate average TX UI. See Notes 2 and 3. 10 20 ms An unexpected electrical idle (VRXmust be recognized no longer than TRXIDLE-DET- DIFF-ENTERTIME to signal an unexpected idle condition. ns Across all Lanes on a port. This includes variation in the length of a skip ordered-set (e.g., COM and 1 to 5 SKP symbols) at the RX as well as any delay differences arising from the interconnect itself. DIFFp-p <VRX-IDLE-DET- DIFFp-p) 1. No test load is necessarily associated with this value. 2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 2, "Compliance Test/Measurement Load" on page 23 should be used as the RX device when taking measurements (also refer to the Receiver Compliance Eye Diagram as shown in Figure 3, "Minimum Receiver Eye Timing and Voltage Compliance Specification" on page 23). If the clocks to the RX and TX are not derived from the same clock chip the TX UI must be used as a reference for the eye diagram. 3. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total .6 UI jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the RX and TX are not derived from the same clock chip, the appropriate average TX UI must be used as the reference for the eye diagram. 29 41110 Bridge -- Datasheet 3.12.2 PCI and PCI-X Interface Timing Table 27. PCI Interface Timing Functional Operating Range (VCC33 = 3.3 V + 5%, Tcase=0C to 105C) 66 MHz Symbol Parameter Min 33 MHz Max Min Max Units Notes Tval CLK to Signal Valid Delay; bused signals 2 6 2 11 ns 1, 2, 3 Tval(ptp) CLK to Signal Valid Delay; point-to-point signals 2 6 2 12 ns 1, 2, 3 Ton Float to Active Delay 2 ns 1, 7 Toff Active to Float Delay ns 1, 7 Tsu Input Setup Time to CLK; Bused signals 3 7 ns 3, 4, 8 Tsu(ptp) Input Setup Time to CLK; point-to-point 5 10,12 ns 3, 4 Th Input Hold Time from CLK 0 0 ns 4 Trst Reset Active Time after power stable 1 1 ms 5 Trst-clk Reset Active Time after CLK stable 100 100 s 5 Trst-off Reset Active to output float delay ns 5, 6 Trrsu PaREQ64# to RSTIN# setup time 10 Trrh RSTIN# to PaREQ64# hold Time 0 Trhfa RSTIN# high to first configuration access 225 225 clocks Trhff RSTIN# high to first PaFRAME# Assertion 5 5 clocks Tpvrh Power Valid to RSTIN# High 100 100 ms 2 14 28 40 40 10 50 0 clocks 50 ns 9 1. It is important that all driven signal transitions drive to their Voh or Vol level within one Tcyc. 2. Minimum times are measured at the package pin (not the test point) with the load circuit shown in the PCI-X Electrical and Mechanical Addendum, Revision 2.0a. Maximum times are measured with the test point and load circuit shown in the PCI-X Electrical and Mechanical Addendum, Revision 2.0a. 3. A_REQ_[5:0]# and A_GNT_[5:0]# are point-to-point signals and have different input setup times than do bused signals. A_GNT_[5:0]# and A_REQ_[5:0]# have a setup of 5 ns at 66 MHz. All other signals are bused. 4. See Section 3.12, "Timing Specifications" on page 28 and the measurement conditions in the PCI-X Electrical and Mechanical Addendum, Revision 2.0a. 5. If A_M66EN is asserted, CLK is stable when it meets the requirements in the PCI Local Bus Specification Revision 2.3. RSTIN# is asserted and deasserted asynchronously with respect to CLK. 6. When A_M66EN is asserted, the minimum specification for Tval(min), Tval(ptp)(min), and Ton may be reduced to 1 ns if a mechanism is provided to guarantee a minimum value of 2 ns when A_M66EN is deasserted. 7. For purposes of active/float timing measurements, the Hi-Z or "off" state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time. Refer to the PCI Local Bus Specification Revision 2.3 for more details. 9. Maximum value is also limited by delay to the first transaction (Trhff). 30 Datasheet -- 41110 Bridge Figure 5. PCI Output Timing Figure 6. PCI Input Timing Table 28. PCI-X 3.3V Signal Timing Parameters (Sheet 1 of 2) Sym Parameter PCI-X 133 Min Tval CLK to Signal Valid Delay 0.7 Max 3.8 PCI-X 66 Min 0.7 Units Notes Max 3.8 ns 1, 2, 8 31 41110 Bridge -- Datasheet Table 28. PCI-X 3.3V Signal Timing Parameters (Sheet 2 of 2) Ton Float to Active Delay Toff Active to Float Delay 0 0 ns 1, 6, 8 ns 1, 6, 8 Tsu Input Setup Time to CLK 1.2 1.7 ns 3, 7 Th Input Hold Time from CLK Trst Reset Active Time after power stable 0.5 0.5 ns 3 1 1 ms 4 Trst-clk Reset Active Time after CLK stable 100 100 s 4 Trst-off Reset Active to output float delay ns 4 Trrsu PaREQ64# to RSTIN# setup time 10 Trrh RSTIN# to PaREQ64# hold Time 0 Trhfa RSTIN# high to first configuration access 226 226 clocks Trhff RSTIN# high to first PaFRAME# Assertion 5 5 clocks Tpvrh Power valid to RSTIN# high 100 100 ms Tprsu PCI-X initialization pattern to RSTIN# setup time 10 10 clocks Tprh RSTIN# to PCI-X initialization pattern hold time 0 Trlcx Delay from RSTIN# low to CLK frequency change 0 7 7 40 40 10 50 50 0 0 0 ns 50 50 ns ns 7 7 ns 1. See the timing measurement conditions in Section 3.12, "Timing Specifications" on page 28. 2. Minimum times are measured at the package pin (not the test point) with the load circuit shown in the PCI-X Electrical and Mechanical Addendum, Revision 2.0a. Maximum times are measured with the test point and load circuit shown in PCI-X Electrical and Mechanical Addendum, Revision 2.0a. 3. See the timing measurement conditions in Section 3.12, "Timing Specifications" on page 28 and the PCI-X Electrical and Mechanical Addendum, Revision 2.0a. 4. RST# is asserted and deasserted asynchronously with respect to CLK. 5. For purposes of Active/Float timing measurements, the Hi-Z or "off" state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification 6. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time. 7. Maximum value is also limited by delay to the first transaction (Trhfa). The PCI-X initialization pattern control signals after the rising edge of RSTIN# must be deasserted no later than two clocks before the first PaFRAME# and must be floated no later than one clock before PaFRAME# is asserted. 8. Device must meet this specification independent of how many outputs switch simultaneously. 32 Datasheet -- 41110 Bridge 3.12.3 PCI and PCI-X Clock Specification Clock measurement conditions are the same for PCI-X devices as for conventional PCI devices in a 3.3V signaling environment except for voltage levels specified in Table 29, "PCI and PCI-X Clock Timings" on page 34. The same spread-spectrum clocking techniques are allowed in PCI-X as for 66 MHz conventional PCI. If a device includes a PLL, that PLL must track the input variations of spread-spectrum clocking specified in Table 29. Figure 7. PCI-X 3.3V Clock Waveform 33 41110 Bridge -- Datasheet Table 29. PCI and PCI-X Clock Timings PCI-X 133 Symbol T cyc PCI-X 66 PCI 66 PCI 33 Parameter CLK Cycle Time Min Max Min Max Min Max Min Max Units Notes Average 7.5 20 15 20 15 30 30 ns 1,3,4 Absolute Minimum 7.375 14.8 14.8 29.7 ns 1,3 Thigh CLK high time 3 6 6 11 ns Tlow CLK low time 3 6 6 11 ns Tjit CLK Period Jitter 125 -125 200 -200 200 -200 300 -300 ps 5 1.5 4 1 4 V/ns 2 Slew Rate -- CLK slew rate 1.5 4 1.5 4 Spread Spectrum Requirements fmod Modulation frequency 30 33 30 33 30 33 kHz fspread Frequency spread -1 0 -1 0 -1 0 % 1. For clock frequencies above 33 MHz, the clock frequency may not change beyond the spread-spectrum and jitter limits except while RSTIN# is asserted. 2. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in the PCI-X Electrical and Mechanical Addendum, Revision 2.0a. 3. The minimum clock period must not be violated for any single clock cycle (i.e. accounting for all system jitter). 4. Average Tcyc is measured over any 1 s period of time and must include all sources of clock variation. 5. Period jitter is the deviation between any single period of the clock, Tcyc, and the average period of the clock, Tcyc(average). 34 Datasheet -- 41110 Bridge 3.12.4 41110 Bridge Clock Timings Table 30. 41110 Bridge Clock Timings Symbol Parameter Min Max Units Notes Tperiod Average Period 10.0 10.2 ns 6 Trise Rise time across 600 mV 300 600 ps 7,8 Tfall Fall time across 600 mV 300 600 ps -- Rise/Fall Matching -- Cross point at 1 V Tccjitter Cycle to Cycle jitter CLK100 7,8 20% 0.51 45 7,9 0.76 V 200 ps -- Duty Cycle 55 % -- Maximum voltage allowed at input 1.45 V -- Minimum voltage allowed at input -200 mV -- Rising edge ringback -- Falling edge ring back 0.85 V 0.35 V CLK133 Tperiod Average Period 7.5 7.65 ns 6 Trise Rise time across 600 mV 300 600 ps 7,8 Tfall Fall time across 600 mV 300 600 ps 7,8 -- Rise/Fall Matching -- Cross point at 1V Tccjitter 20% 0.51 Cycle to Cycle jitter 45 7,9 0.76 V 125 ps 55 % -- Duty Cycle -- Maximum voltage allowed at input 1.45 V -- Minimum voltage allowed at input -200 mV -- Rising edge ringback -- Falling edge ring back 0.85 10 V 0.35 V CLK33 CLK period 30.0 N/A ns 1,2 Thigh CLK high time 12.0 N/A ns 3 Tlow CLK low time 12.0 N/A ns 4 -- Rising edge rate 1.0 4.0 V/ns 5 -- Falling edge rate 1.0 4.0 V/ns 5 Trise CLK rise time 0.5 2.0 ns 5 Tfall CLK fall time 0.5 2.0 ns 5 Tperiod 1. Period, jitter, offset and skew measured on rising edge @ 1.5V for 3.3V clocks. 35 41110 Bridge -- Datasheet 2. 3. 4. 5. The average period over any 1 us period of time must be greater than the minimum specified period. Thigh is measured at 2.4V for non-host outputs. Tlow is measured at 0.4V for all outputs. For 3.3V clocks Trise and Tfall are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.4V (1 mA) JEDEC Specification. 6. Measured at crossing point. 7. Measured from Vol = 0.2V to Voh = 0.8V. 8. Still simulating to determine [0.2-0.8 V] or [0.3-0.9 V]. 9. Determined as a fraction of 2*(Trise - Tfall) / (Trise + Tfall). 10.Period jitter is the deviation between any single period of the clock, Tcyc, and the average period of the clock, Tcyc(average). 3.12.4.1 Spread Spectrum Clocking Spread spectrum clocking can be used on the 41110 Bridge to reduce energy. Spread Spectrum clocking is a common technique used by system designers to meet FCC emissions, where the frequency is deliberately shifted around to spread the energy off of the peak. The following is to be observed when using Spread Spectrum clocking: * All device timings (including jitter, skew, min/max clock period, output rise/fall time) MUST meet the existing non-spread spectrum specifications * All non-spread Host and PCI functionality must be maintained in the spread spectrum mode (includes all power management functions.) * The minimum clock period cannot be violated. The preferred method is to adjust the spread technique to not allow for modulation above the nominal frequency. This technique is often called "down-spreading". The modulation profile in a modulation period can be expressed as: Equations: (1 - ) f nom + 2 f m f nom t = f (1 + ) f nom - 2 f m f nom t 1 ; 2 fm 1 1 <t < , when fm 2 fm when 0 < t < where: fnom is the nominal frequency in the non-SSC mode fm is the modulation frequency fm is the modulation amount t is time. 3.13 Reference and Compensation Pins The 41110 Bridge has one reference pin and two compensation pins: * PE_RCOMP[1:0] are two separate pins that provide voltage compensation for the PCI Express interface on the 41110 Bridge. The nominal compensation voltage is 0.5V. An external 24.9 1% pull-up resistor should be used to connect to VCC15. A single pull-up resistor can be used to for both of these signals. * RCOMP is an analog PCI interface compensation pin to the 41110 Bridge. A 100 1% pulldown resistor should be used to connect the RCOMP pin to ground. 36 Datasheet -- 41110 Bridge All three of these implementations are shown in Figure 8. Figure 8. 41110 Bridge Reference and Compensation Circuit Implementations 3.14 Thermal Specifications Refer to the 6700PXH 64-bit PCI Hub Thermal/Mechanical Design Guide for Intel 6700PXH 64bit PCI Hub (PXH). 3.14.1 Power For TDP specifications, refer to Table 31. FC-BGA packages have poor heat transfer capability into the board and have minimal thermal capability without thermal solutions. Intel recommends that system designers plan for a heatsink when using the 41110 Bridge component. 3.14.2 Die Temperature To ensure proper operation and reliability of the 41110 Bridge component, the die temperatures must be at or below the values specified in Table 31. System and/or component level thermal solutions are required to maintain die temperatures below the maximum temperature specifications. 37 41110 Bridge -- Datasheet Table 31. 41110 Bridge Thermal Specifications Parameter Maximum Tcase 95oC Max Note: Mode 1: PCI-X 66MHz, 64-bit, 4 slots/devices 3.14.3 Thermal Solution Component Suppliers Table 32. Torsional Clip Heatsink Thermal Solution Part Intel Part Number Supplier (Part Number) Heatsink Assembly includes: Unidirectional Fin Heatsink Thermal Interface Material C76435-001 CCI/ACK C76434-001 CCI/ACK Torsional Clip Unidirectional Fin Heatsink (31.0 x 31.0 x 12.2mm) Thermal Interface (Chomerics T-710) Note: 38 A69230-001 Chomerics 69-12-22066-T710 Heatsink Attach Clip C17725-001 CCI/ACK Solder-Down Anchor A13494-005 Foxconn (HB96030-DW) Contact Information Harry Lin (USA) 714-739-5797 hlinack@aol.com Monica Chih (Taiwan) 866-2-29952666, x131 monica_chih@ccic.com.tw Harry Lin (USA) 714-739-5797 hlinack@aol.com Monica Chih (Taiwan) 866-2-29952666, x131 monica_chih@ccic.com.tw Todd Sousa (USA) 360-606-8171 tsousa@parker.com Harry Lin (USA) 714-739-5797 hlinack@aol.com Monica Chih (Taiwan) 866-2-29952666, x131 monica_chih@ccic.com.tw Julia Jiang (USA) 408-919-6178 juliaj@foxconn.com The enabled components may not be currently available from all suppliers. Contact the supplier directly to verify time of component availability. Datasheet -- 41110 Bridge Package Specification and Ballout 4.1 4 Package Specification The 41110 Bridge is in a 567-ball FCBGA package, 31mm X 31mm in size, with a 1.27mm ball pitch (see Figure 9 and Figure 10). Figure 9. 41110 Bridge Package Dimensions (Top View) Handling Exclusion Area 0.547 in. 0.491 in. Die Keepout Area 0.291 in. 0.247 in. 41110 Die 17.00 mm 21.00 mm 31.00 mm 0.200 in. 17.00 mm 21.00 mm 31.00 mm 39 41110 Bridge -- Datasheet Figure 10. 41110 Bridge Package Dimensions (Side View) Substrate 2.4450.102 mm 2.0100.099 mm 0.840.05 mm Decoup Cap Die 0.7 mm Max 0.20 See Note 4. 0.20 -C- Seating Plane 0.4350.025 mm See Note 3 See Note 1 Notes: 1. Primary datum -C- and seating plan are defined by the spherical crowns of the solder balls (shown before motherboard attach). 2. All dimensions and tolerances conform to ANSI Y14.5M-1994 3. BGA has a pre-SMT height of 0.5 mm and post-SMT height of 0.41-0.46 mm 4. Shown before motherboard attach; FCBGA has a convex (dome shape) orientation before reflow and is expected to have a slightly concave (bowl shaped) orientation after reflow. Note: Primary datum -C- and seating plane are defined by the spherical crowns of the solder balls. Note: All dimensions and tolerances conform to ANSI Y14.5M-1982 40 Datasheet -- 41110 Bridge 4.2 Signal List, sorted by Ball Location Table 33. Ball Signal List, sorted by Ball Name (Sheet 1 of 4) Signal Name Ball Signal Name Ball Signal Name A1 A2 A3 VCC33 STRAP_V_4 C1 C2 C3 D# VSS STRAP_V_9 E1 E2 E3 NC4 VSS NC9 A4 A5 A6 VSS NC2 TDO C4 C5 C6 NC4 VSS NC18 E4 E5 E6 NC2 VSS STRAP_V_1 A7 A8 A9 VCC33 VSS PETN[5] C7 C8 C9 SMBCLK VSS PERN[5] E7 E8 E9 TMS VSS TDI A10 A11 PETP[5] C10 C11 PERN[4] PERP[4] E10 E11 VSS PETP[7] A12 A13 A14 VSSBGPE VCCPE C12 C13 C14 VCCPE PERN[2] VCCBGPE E12 E13 E14 PERN[6] VSS PERN[0] A15 A16 A17 PERN[1] PERP[1] VSS C15 C16 C17 VCCPE REFCLKP REFCLKN E15 E16 E17 PERP[0] PE_RCOMP[0] A_PCIXCAP A18 A19 A20 SMBUS[3] STRAP_V_15 VSS C18 C19 C20 A_STRAP0 A_STRAP3 VSS E18 E19 E20 CFGRST# NC6 VSS A21 A22 A23 A_STRAP4 NC3 A_NC2 C21 C22 C23 RESERVED1 VCC33 VSS E21 E22 E23 A_NC10 A_NC8 VSS A24 B1 B2 VSS NC7 NC1 C24 D1 D2 A_INTD# STRAP_V_10 NC3 E24 F1 F2 VCC33 VCC33 NC B3 B4 B5 STRAP_V_3 STRAP_V_5 STRAP_V_2 D3 D4 D5 NC6 STRAP_V_6 VCC33 F3 F4 F5 NC NC STRAP_V_7 B6 B7 B8 NC19 TCK CFGRETRY D6 D7 D8 NC5 STRAP_V_12 SMBDAT F6 F7 F8 NC7 NC9 NC8 B9 B10 B11 PERP[5] VSS PETN[4] D9 D10 D11 PETN[6] PETP[6] VSS F9 F10 F11 TRST# PERP[7] PETN[7] B12 B13 B14 PETP[4] VSS PETN[2] D12 D13 D14 PERP[6] PERP[2] VSS F12 F13 F14 VCCPE PETN[0] PETP[0] B15 B16 B17 PETP[2] VSS PE_RCOMP[1] D15 D16 D17 PETN[1] PETP[1] VSS F15 F16 F17 VSS VSSAPE PERST# B18 B19 B20 VCC33 RESERVED SMBUS[2] D18 D19 D20 A_STRAP1 A_STRAP5 SMBUS[5] F18 F19 F20 NC1 A_STRAP6 RESERVED4 B21 B22 B23 RESERVED2 A_STRAP2 A_TEST2 D21 D22 D23 RESERVED3 A_NC6 A_INTC# F21 F22 F23 A_NC9 A_TEST1 A_NC4 B24 A_NC1 D24 A_NC3 F24 A_INTB# 41 41110 Bridge -- Datasheet Table 33. 42 Signal List, sorted by Ball Name (Sheet 2 of 4) Ball Signal Name Ball Signal Name Ball Signal Name G1 G2 G3 NC VSS NC J1 J2 J3 VSS NC NC L1 L2 L3 NC NC VCC15 G4 G5 G6 NC VSS NC J4 J5 J6 VSS NC NC L4 L5 L6 NC NC VCC33 G7 G8 G9 NC VSS NC J7 J8 J9 NC VCCAPCI1 VSS L7 L8 L9 NC NC VSS G10 G11 G12 PERN[7] VSS PERN[3] J10 J11 J12 VCCPE VSS VCCPE L10 L11 L12 VCC15 VSS VCC15 G13 G14 PETP[3] VSS J13 J14 VSS VCCPE L13 L14 VSS VCC15 G15 G16 G17 VCCAPE SMBUS[1] VSS J15 J16 J17 VSS VCC15 A_AD[63] L15 L16 L17 VSS VCC15 A_AD[59] G18 G19 G20 NC11 NC12 VSS J18 J19 J20 A_CBE5# VSS A_PAR64 L18 L19 L20 VSS A_AD[58] A_AD[43] G21 G22 G23 A_NC5 A_NC7 VSS J21 J22 J23 A_AD[47] VSS A_AD[46] L21 L22 L23 VSS A_REQ4# A_AD[42] G24 H1 H2 A_INTA# NC NC J24 K1 K2 A_GNT1# NC VSS L24 M1 M2 VSS H3 H4 H5 VCC33 NC NC K3 K4 K5 NC NC VSS M3 M4 M5 NC VSS NC H6 H7 H8 VSS NC NC K6 K7 K8 NC NC VSS M6 M7 M8 NC VSS NC14 H9 H10 H11 NC VSS VCCPE K9 K10 K11 VCC15 VSS VCC15 M9 M10 M11 VCC15 VSS VCC15 H12 H13 H14 PERP[3] PETN[3] VSS K12 K13 K14 VSS VCC15 VSS M12 M13 M14 VSS VCC15 VSS H15 H16 H17 VCCPE RSTIN# A_CBE4# K15 K16 K17 VCC15 VSS A_AD[61] M15 M16 M17 VCC15 VSS A_AD[57] H18 H19 H20 VCC33 A_CBE6# A_CBE7# K18 K19 K20 A_AD[60] A_AD[62] VSS M18 M19 M20 A_AD[56] VCC33 NC15 H21 H22 H23 VCC33 A_AD[49] A_AD[48] K21 K22 K23 NC13 A_AD[45] VSS M21 M22 M23 A_AD[41] VCC15 A_AD[40] H24 VCC33 K24 A_AD[44] M24 NC Datasheet -- 41110 Bridge Table 33. Ball Signal List, sorted by Ball Name (Sheet 3 of 4) Signal Name Ball Signal Name Ball Signal Name N1 N2 N3 VSS NC R1 R2 R3 VSS NC NC U1 U2 U3 STRAP_V_11 NC VSS N4 N5 N6 NC VSS NC R4 R5 R6 VSS STRAP_V_14 NC16 U4 U5 U6 NC NC VSS N7 N8 N9 NC NC VSS R7 R8 R9 VCC33 VCCAPCI2 VSS U7 U8 U9 NC NC VCC33 N10 N11 N12 VCC15 VSS VCC15 R10 R11 R12 VCC15 VSS VCC15 U10 U11 U12 STRAP_V_13 RESERVED VSS N13 N14 VSS VCC15 R13 R14 VSS VCC15 U13 U14 A_CLKIN A_CLKO[4] N15 N16 N17 VSS VCC15 A_AD[55] R15 R16 R17 VSS VCC15 VCCAPCI3 U15 U16 U17 VSS A_CLKO[5] A_CLKO[3] N18 N19 N20 A_REQ3# A_AD[54] VSS R18 R19 R20 A_AD[51] VSS A_AD[50] U18 U19 U20 VSS A_STOP# A_DEVSEL# N21 N22 N23 A_AD[39] A_AD[38] VSS R21 R22 R23 A_LOCK# VSS A_AD[35] U21 U22 U23 VSS A_TRDY# A_GNT5# N24 P1 P2 NC STRAP_V_8 R24 T1 T2 A_AD[34] NC VSS U24 V1 V2 VSS VSS NC P3 P4 P5 VSS NC NC T3 T4 T5 NC NC10 VCC33 V3 V4 V5 NC VCC33 NC P6 P7 P8 VSS NC NC T6 T7 T8 NC NC VSS V6 V7 V8 NC VSS NC P9 P10 P11 VCC15 VSS VCC15 T9 T10 T11 VCC15 VSS VCC15 V9 V10 V11 NC VSS RCOMP P12 P13 P14 VSS VCC15 VSS T12 T13 T14 VSS VCC15 VSS V12 V13 V14 VCC15 VSS A_CLKO[0] P15 P16 P17 VCC15 VSS A_AD[53] T15 T16 T17 VCC15 VSS VCC33 V15 V16 V17 A_CLKO[6] VCC15 A_CLKO[2] P18 P19 P20 VSS A_AD[52] A_PERR# T18 T19 T20 A_M66EN A_SERR# VCC33 V18 V19 V20 A_REQ2# VSS A_133EN P21 P22 P23 VSS A_AD[37] A_AD[36] T21 T22 T23 A_AD[33] A_AD[32] VCC33 V21 V22 V23 A_PME# VSS A_FRAME# P24 VSS T24 CMODE V24 A_IRDY# 43 41110 Bridge -- Datasheet Table 33. 44 Signal List, sorted by Ball Name (Sheet 4 of 4) Ball Signal Name Ball Signal Name Ball Signal Name W1 W2 W3 NC VCC33 NC AA1 AA2 AA3 VCC33 NC NC AC1 AC2 AC3 NC NC VCC15 W4 W5 W6 NC VSS NC AA4 AA5 AA6 VSS NC NC AC4 AC5 AC6 NC NC VCC33 W7 W8 W9 NC VSS NC AA7 AA8 AA9 VSS NC NC AC7 AC8 AC9 NC NC VSS W10 W11 W12 NC VCC33 NC AA10 AA11 AA12 VSS NC NC AC10 AC11 AC12 NC NC VSS W13 W14 A_REQ5# VSS AA13 AA14 VSS A_GNT4# AC13 AC14 A_AD[15] A_CBE1# W15 W16 W17 A_AD[30] A_CLKO[1] VSS AA15 AA16 AA17 A_AD[31] VSS A_RST# AC15 AC16 AC17 VSS A_AD[11] A_AD[9] W18 W19 W20 A_AD[25] A_GNT0# VSS AA18 AA19 AA20 A_AD[26] VSS A_CBE3# AC18 AC19 AC20 VSS A_AD[7] A_AD[5] W21 W22 W23 A_REQ0# A_REQ1# VSS AA21 AA22 AA23 A_AD[21] VSS A_AD[18] AC21 AC22 AC23 VSS A_AD[2] A_AD[0] W24 Y1 Y2 A_AD[16] NC NC AA24 AB1 AB2 A_CBE2# NC VSS AC24 AD1 AD2 A_REQ64# VSS NC Y3 Y4 Y5 VSS NC NC AB3 AB4 AB5 NC NC VSS AD3 AD4 AD5 NC VSS NC Y6 Y7 Y8 VCC15 NC NC AB6 AB7 AB8 NC NC VCC33 AD6 AD7 AD8 NC VSS NC Y9 Y10 Y11 VCC33 NC NC AB9 AB10 AB11 NC NC VSS AD9 AD10 AD11 NC VSS NC Y12 Y13 Y14 VSS A_GNT3# A_GNT2# AB12 AB13 AB14 NC A_PAR VCC33 AD12 AD13 AD14 A_AD[14] Y15 Y16 Y17 VCC33 A_AD[28] A_AD[27] AB15 AB16 AB17 A_AD[12] A_AD[29] VSS AD15 AD16 AD17 A_AD[13] VSS A_AD[10] Y18 Y19 Y20 VSS A_AD[23] A_AD[22] AB18 AB19 AB20 A_AD[8] A_AD[24] VCC15 AD18 AD19 AD20 A_CBE0# VCC33 A_AD[6] Y21 Y22 Y23 VCC33 A_AD[19] A_AD[17] AB21 AB22 AB23 A_AD[3] A_AD[20] VSS AD21 AD22 AD23 A_AD[4] VSS A_AD[1] Y24 VCC33 AB24 A_ACK64# AD24 VSS Datasheet -- 41110 Bridge 4.3 Signal List, sorted by Signal Name Table 34. Signal List, sorted by Signal Name (Sheet 1 of 4) Ball Signal Name Ball Signal Name Ball Signal Name V20 AB24 AC23 AD23 AC22 AB21 AD21 AC20 AD20 AC19 AB18 AC17 AD17 AC16 AB15 AD15 AD14 AC13 W24 Y23 AA23 Y22 AB22 AA21 Y20 Y19 AB19 W18 AA18 Y17 Y16 AB16 W15 AA15 T22 T21 R24 R23 P23 P22 N22 N21 M23 M21 L23 L20 K24 K22 J23 J21 H23 A_133EN A_ACK64# A_AD[0] A_AD[1] A_AD[2] A_AD[3] A_AD[4] A_AD[5] A_AD[6] A_AD[7] A_AD[8] A_AD[9] A_AD[10] A_AD[11] A_AD[12] A_AD[13] A_AD[14] A_AD[15] A_AD[16] A_AD[17] A_AD[18] A_AD[19] A_AD[20] A_AD[21] A_AD[22] A_AD[23] A_AD[24] A_AD[25] A_AD[26] A_AD[27] A_AD[28] A_AD[29] A_AD[30] A_AD[31] A_AD[32] A_AD[33] A_AD[34] A_AD[35] A_AD[36] A_AD[37] A_AD[38] A_AD[39] A_AD[40] A_AD[41] A_AD[42] A_AD[43] A_AD[44] A_AD[45] A_AD[46] A_AD[47] A_AD[48] H22 R20 R18 P19 P17 N19 N17 M18 M17 L19 L17 K18 K17 K19 J17 AD18 AC14 AA24 AA20 H17 J18 H19 H20 U13 V14 W16 V17 U17 U14 U16 V15 U20 V23 W19 J24 Y14 Y13 AA14 U23 V24 G24 F24 D23 C24 B24 A23 D24 F23 G21 D22 G22 A_AD[49] A_AD[50] A_AD[51] A_AD[52] A_AD[53] A_AD[54] A_AD[55] A_AD[56] A_AD[57] A_AD[58] A_AD[59] A_AD[60] A_AD[61] A_AD[62] A_AD[63] A_CBE0# A_CBE1# A_CBE2# A_CBE3# A_CBE4# A_CBE5# A_CBE6# A_CBE7# A_CLKIN A_CLKO[0] A_CLKO[1] A_CLKO[2] A_CLKO[3] A_CLKO[4] A_CLKO[5] A_CLKO[6] A_DEVSEL# A_FRAME# A_GNT0# A_GNT1# A_GNT2# A_GNT3# A_GNT4# A_GNT5# A_IRDY# A_INTA# A_INTB# A_INTC# A_INTD# A_NC1 A_NC2 A_NC3 A_NC4 A_NC5 A_NC6 A_NC7 E22 F21 E21 R21 T18 AB13 J20 E17 P20 V21 W21 W22 V18 N18 L22 W13 AC24 AA17 T19 U19 C18 D18 B22 C19 A21 D19 F19 F22 B23 U22 B2 E4 D2 E1 G3 D3 B1 G4 E3 F4 B8 E18 T24 AB1 AC2 AD2 AD3 AB4 AC4 A_NC8 A_NC9 A_NC10 A_LOCK# A_M66EN A_PAR A_PAR64 A_PCIXCAP A_PERR# A_PME# A_REQ0# A_REQ1# A_REQ2# A_REQ3# A_REQ4# A_REQ5# A_REQ64# A_RST# A_SERR# A_STOP# A_STRAP0 A_STRAP1 A_STRAP2 A_STRAP3 A_STRAP4 A_STRAP5 A_STRAP6 A_TEST1 A_TEST2 A_TRDY# B_NC1 B_NC2 B_NC3 B_NC4 B_NC5 B_NC6 B_NC7 B_NC8 B_NC9 B_NC10 CFGRETRY CFGRST# CMODE NC NC NC NC NC NC 45 41110 Bridge -- Datasheet Table 34. 46 Signal List, sorted by Signal Name (Sheet 2 of 4) Ball Signal Name Ball Signal Name Ball Signal Name AC5 AD5 AD6 AB7 AC7 AD8 AB9 AD9 AB10 AC10 AD11 W1 Y2 AA2 AA3 AB3 Y4 Y5 W6 AA6 W7 Y7 Y8 AA8 W9 Y10 AA9 R2 R3 P1 P4 P5 N3 N4 M2 M3 L1 L2 K3 K4 J2 J3 H4 H1 H2 P7 P8 N6 N7 M5 M6 L5 L7 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC K6 K7 J6 J7 H5 H8 AC8 AB12 Y1 AA5 G9 H9 G6 G7 W10 V9 V8 T7 V6 U7 U8 T3 U4 J5 K1 Y11 AA11 W12 L8 U5 F2 G1 F3 C1 W3 AC11 H7 U2 L4 AB6 T6 T1 V5 AA12 AC1 N8 V2 V3 W4 F18 A5 A22 C4 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC1 NC2 NC3 NC4 D6 E19 F6 F8 F7 T4 G18 G19 K21 M8 M20 R6 C6 B6 E16 B17 E14 A15 C13 G12 C10 C9 E12 G10 E15 A16 D13 H12 C11 B9 D12 F10 F17 F13 D15 B14 H13 B11 A9 D9 F11 F14 D16 B15 G13 B12 A10 D10 E11 V11 C17 C16 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC18 NC19 PE_RCOMP[0] PE_RCOMP[1] PERN[0] PERN[1] PERN[2] PERN[3] PERN[4] PERN[5] PERN[6] PERN[7] PERP[0] PERP[1] PERP[2] PERP[3] PERP[4] PERP[5] PERP[6] PERP[7] PERST# PETN[0] PETN[1] PETN[2] PETN[3] PETN[4] PETN[5] PETN[6] PETN[7] PETP[0] PETP[1] PETP[2] PETP[3] PETP[4] PETP[5] PETP[6] PETP[7] RCOMP REFCLKN REFCLKP Datasheet -- 41110 Bridge Table 34. Signal List, sorted by Signal Name (Sheet 3 of 4) Ball Signal Name Ball Signal Name Ball Signal Name B19 U11 C21 B21 D21 F20 E6 B5 B3 A3 B4 D4 F5 P2 C3 D1 U1 D7 U10 R5 A19 H16 C7 D8 G16 B20 A18 D20 B7 E9 A6 E7 F9 J16 K9 K11 K13 K15 L3 L10 L12 L14 L16 M9 M11 M13 M15 M22 N10 N12 N14 N16 P9 P11 RESERVED RESERVED RESERVED1 RESERVED2 RESERVED3 RESERVED4 STRAP_V_1 STRAP_V_2 STRAP_V_3 STRAP_V_4 STRAP_V_5 STRAP_V_6 STRAP_V_7 STRAP_V_8 STRAP_V_9 STRAP_V_10 STRAP_V_11 STRAP_V_12 STRAP_V_13 STRAP_V_14 STRAP_V_15 RSTIN# SMBCLK SMBDAT SMBUS[1] SMBUS[2] SMBUS[3] SMBUS[5] TCK TDI TDO TMS TRST# VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 P13 P15 R10 R12 R14 R16 T9 T11 T13 T15 V12 V16 Y6 AB20 AC3 A2 A7 B18 C22 D5 E24 F1 H3 H18 H21 H24 L6 M19 R7 T5 T17 T20 T23 U9 V4 W2 W11 Y9 Y15 Y21 Y24 AA1 AB8 AB14 AC6 AD19 J8 R8 R17 G15 C14 A14 C12 C15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCCAPCI1 VCCAPCI2 VCCAPCI3 VCCAPE VCCBGPE VCCPE VCCPE VCCPE F12 H11 H15 J10 J12 J14 A4 A8 A17 A20 A24 B10 B13 B16 C2 C5 C8 C20 C23 D11 D14 D17 E2 E5 E8 E10 E13 E20 E23 F15 G2 G5 G8 G11 G14 G17 G20 G23 H6 H10 J1 J4 J9 J11 J13 J15 J19 J22 K2 K5 K8 K10 K12 K14 VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 47 41110 Bridge -- Datasheet Table 34. 48 Signal List, sorted by Signal Name (Sheet 4 of 4) Ball Signal Name Ball Signal Name Ball Signal Name K16 K20 K23 L9 L11 L13 L15 L18 L21 L24 M4 M7 M10 M12 M14 M16 N2 N5 N9 N11 N13 N15 N20 N23 P3 P6 P10 P12 P14 P16 P18 P21 P24 R1 R4 R9 R11 R13 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS R15 R19 R22 T2 T8 T10 T12 T14 T16 U3 U6 U12 U15 U18 U21 U24 V1 V7 V10 V13 V19 V22 W5 W8 W14 W17 W20 W23 Y3 Y12 Y18 AA4 AA7 AA10 AA13 AA16 AA19 AA22 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AB2 AB5 AB11 AB17 AB23 AC9 AC12 AC15 AC18 AC21 AD1 AD4 AD7 AD10 AD16 AD22 AD24 F16 A13 A1 A11 A12 M1 M24 N1 N24 AD12 AD13 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSAPE VSSBGPE Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Intel: QG41110 S L93U