Order Number: 310182-002US
February 200 6
Intel® 41110 Serial to Parallel PCI Bridge
Datasheet
Product Features
■x8 PCI Expr ess to Singl e PCI X/PCI bus
bridge
■PCI Express Specification, Revision 1.0a
■Suppor t for single x8, sin gle x4 or single x1
PCI Express operati on.
■Suppor ts 64-bit PCI-X 133 MHz, 100 MHz
and 66 MHz as well as PCI 66 MHz and 33
MHz for mixed PCI/PCI-X modes and
frequency bus /device operation
■64-bit addressing sup port
■32-bit CRC (cyclic redundancy checking)
covering all transmitted data packets.
■16-bit CRC on all link message
information.
■Raw b i t-rate on the da ta pi ns of 2. 5 Gbit/s,
resulting in a raw bandwidth per pin of
250 MB/s.
■Maximum realized bandwidth on PCI
Express interface is 2 GB/s (in x8 mod e) in
each direction simultaneously, for an
aggregate of 4 GB/s.
■PCI Local Bus Specification, Revision 2.3.
■PCI-to-PCI Bridge Specification,
Revision 1.1.
■PCI-X Addendum to the PCI Local Bus
Specification, Revision 1.0b
■64-bit 66 MHz, 3.3 V, NOT 5 V tolerant.
■On Die Termination (ODT) with 8.3K Ω
pull-up to 3.3V for PCI signals.
■Six external REQ/GNT Pairs for internal
arbiter on segment A.
■Programmable bus parking on either the
last agent or always on the 41110 Bridge
■2-level programm able r ound-robin inter nal
arbiter with Multi-Transaction Timer
(MTT)
■External PCI clock-feed support for
asynchronous primary and secondary
domain operation.
■64-bi t address i ng for ups tream and
downstream transactions
■Downstream LOCK# support.
■No upstream LOCK# support.
■PCI fast Back-to-Back capable as target.
■Up to four active and four pending
upstream memory read transactions
■Up to two downstream delayed (memory
read, I/O read/write and config uration read/
write) transaction.
■Tunab le inbound read prefetch algorithm
for PCI MRM/MRL commands
■Device hiding support for secondary PCI
devices.
■Secondary bus Privat e Memory s uppor t via
Opaque memor y region
■Local initialization via SMBus
■Secondary side initialization via Type 0
configuration cycles.
2
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The Intel® 41110 Serial to Parallel PCI Bridge may contain design defects or errors known as errata which may cause the product to deviate from
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Copyright © 2006, Intel Corporation
3
Contents
Contents
1 Introduction....................................................................................................................................7
1.1 About This Document .... ....... ...... ....... ...... ....... ...... ...... ....... ...... ....... ...... ....... ...... ...................7
1.2 Product Overview .................................................................................................................7
2 Signal Description.........................................................................................................................8
2.1 On Die Termination (ODT)....................................................................................................8
2.2 PCI Express Interface...........................................................................................................9
2.3 PCI Bus Interface................................................................................................................10
2.4 PCI Bus Interface 64-Bit Extension ....................................................................................11
2.5 PCI Bus Interface Clocks and, Reset and Power Management .........................................12
2.6 Interrupt Interface ...............................................................................................................12
2.7 Reset Straps.................. ....... ...... ....... ...... ....... ...... ...... ....... ...... ....... ...... ....... ...... ....... ..........12
2.8 SMBus Interface .................................................................................................................14
2.9 Miscellaneou s Pi ns............... ...... ....... ...... ....... ...... ...... ....... ...... ....... ...... ....... ................... ....14
3 Electrical and Thermal Characteristics.....................................................................................16
3.1 DC Voltage and Current Specifications ..............................................................................16
3.2 41110 Bridge Powe r Consum ption............................. ....... ...... ....... ................... ....... ...... ....16
3.3 Power Delivery Guidelines..................................................................................................17
3.4 Input Characteristic Signal Association ..............................................................................18
3.5 DC Input Characteristics.....................................................................................................18
3.6 DC Characteristic Output Signal Association .....................................................................18
3.7 DC Output Characteristics..................................................................................................19
3.8 PCI Express Interface DC Specifications ...........................................................................19
3.9 AC Specificatio ns........... ....... ...... ....... ...... ................... ....... ...... ....... ................... ....... ..........25
3.10 Voltage Filter Specifications ...............................................................................................26
3.11 VCC15 and VCC33 Voltage Requirements........................................................................27
3.12 Timing Specifications..........................................................................................................28
3.13 Reference and Compensation Pins....................................................................................36
3.14 Thermal Specifications .......................................................................................................37
4 Package Specification and Ballout............................................................................................39
4.1 Package Specification ........................................................................................................39
4.2 Signal List, sorted by Ball Location.....................................................................................41
4.3 Signal List, sorted by Signal Name.....................................................................................45
Figures
1 Minimum Transmitter Timing and Voltage Output Compliance Specification.............................22
2 Compliance Test/Measurement Load.........................................................................................23
3 Minimum Receiver Eye Timing and Voltage Compliance Specification .....................................23
4 Voltage Requirements VCC33 versus VCC15 ...........................................................................27
5 PCI Output Timing......................................................................................................................31
6 PCI Input Timing.........................................................................................................................31
7 PCI-X 3.3V Clock Waveform ......................................................................................................33
8 41110 Bridge Reference and Compensation Circuit Implementations.......................................37
4
Contents
9 41110 Bridge Package Dimensions (Top View).........................................................................39
10 41110 Bridge Package Dimensions (Side View)........................................................................40
Tables
1 ODT Signals .................................................................................................................................8
2 PCI Express Interface Pins...........................................................................................................9
3 PCI Interface Pins.......................................................................................................................10
4 PCI Interface Pins: 64-Bit Extensions.........................................................................................11
5 PCI Clock and Reset Pins..........................................................................................................12
6 Interrupt Interface Pins ...............................................................................................................12
7 Reset Strap Pins.........................................................................................................................13
8 SMBus Interface Pins.................................................................................................................14
9 Miscellaneou s Pi ns................... ....... ...... ....... ...... ....... ...... ...... .................... ...... ....... ...... ..............14
10 Intel® 41110 Bridge DC Voltage Specifications.........................................................................16
11 41110 Bridge Maximum Voltage Plane Currents .......................................................................16
12 41110 Bridge Thermal Voltage Plane Currents..........................................................................17
13 Watts ..........................................................................................................................................17
14 DC Characteristics Input Signal Association ..............................................................................18
15 DC Input Characteristics.............................................................................................................18
16 DC Characteristic Output Signal Association .............................................................................18
17 DC Output Characteristic............................................................................................................19
18 Differential Transmitter (TX) DC Output Specifications..............................................................19
19 Differential Receiver (RX) DC Input Specifications ....................................................................21
20 DC Specificati ons for PCI and PCI-X 3.3 V Signa ling ..... ...... ....... ...... ....... ...... ....... ...... ..............24
21 DC Specification for Input Clock Signals....................................................................................25
22 DC Specification for Output Clock Signals.................................................................................25
23 Conventional PCI 3.3V AC Characteristics ................................................................................25
24 PCI-X 3.3V AC Characteristics...................................................................................................26
25 Differential Transmitter (TX) AC Output Specifications ..............................................................28
26 Differential Receiver (RX) AC Input Specifications.....................................................................29
27 PCI Interface Timing...................................................................................................................30
28 PCI-X 3.3V Signal Timing Parameters .......................................................................................31
29 PCI and PCI-X Clock Timings ....................................................................................................34
30 41110 Bridge Clock Timings.......................................................................................................35
31 41110 Bridge Thermal Specifications.........................................................................................38
32 Torsional Clip Heatsink Thermal Solution ..................................................................................38
33 Signal List, sorted by Ball Name.................................................................................................41
34 Signal List, sorted by Signal Name.............................................................................................45
5
Contents
Revision History
Date Revision Description
February 2006 002 Updated Product Features section, Copyright page, Section 2.6, and several tables.
January 2006 001 Initial release.
6
Contents
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Datasheet — 41110 Bridge
7
Introduction 1
1.1 About This Document
This document provides information on the Intel® 41110 Serial to Parallel PCI Bridge, including a
functio nal over view, signal descripti ons, mechanical data, package signal location and bus
functional waveforms.
1.2 Product Overview
The Intel® 4111 0 S erial to Parallel PCI Bridge (also called the 41110 Bridge) integrates one PCI
Express t o PCI/ PCI-X br idge. T he bridge fo llo ws the PC I-to-PC I Brid ge progr amming model. The
PCI Express port is compatibl e with the PCI Express Specification, Revision 1.0a. The PCI
interface is compatible with the PCI Local Bus Specification, Revision 2.3 and PCI-X Ad dendum to
the PCI Local Bus Specification, Revision 1.0b.
41110 Bridge — Datasheet
8
Signal Description 2
The “#” symbol at the end of a sig nal name indi cates that the active, o r asserted st ate , occur s when
the signal is at a low voltage level. When “#” is not present after the signal name, the signal is
asserted when at the high voltage level. The following notations are used to describe the signal
type:
I: Input pin
O: Output pin
OD: Open-drain Output pin
I/O: Bidirectional Input/Output pin
I/OD: Bidirectional Input/Open -drain Output pin
2.1 On Die Termination (ODT)
The 41110 Bridge incorporates on-die termination for most of the PCI interface signals. This
eliminates the need for the system designer to incorporate external pull-up resistors in the design.
The following signals have an on die termination of 8.33K Ω +40%:
Table 1. ODT Signals
A_ACK64#
A_AD[63:32]
A_CBE#[7:4]
A_DEVSEL#
A_FRAME#
A_GNT#[5:0]
A_IRDY#
A_PAR
A_PAR64
A_PERR#
A_LOCK#
A_REQ#[5:0]
A_REQ64#
A_SERR#
A_STOP#
A_TRDY#
A_INTA#
Datasheet — 41110 Bridge
9
2.2 PCI Express Interface
Table 2. PCI Express Interface Pins
A_INTB#
A_INTC#
A_INTD#
TCK
TDI
TDO
TMS
A_ACK64#
Signal I/O Description
REFCLKp/
REFCLKn IPCI Express Reference Clocks: 100 MHz differential clock pair.
PETp[7:0]/
PETn[7:0] O
PCI Express Serial Data Transmit: PCI Express differential data t ransmit
signals.
X8 Mode: All PETp[7:0]/ PETn[7:0] are used
X4 Mode: Only PETp[3:0]/ PETn[3:0] are used
x1 Mode: Either PETp[0]/ PETn[0 ] is used or PETp[7]/ PET n[7] is used
PERp[7:0]/
PERn[7:0] I
PCI Express Serial Data Receive: PCI Express differential data receive
signals.
X8 Mode: All PERp[7:0]/ PERn[7:0] are used
X4 Mode: Only PERp[3:0]/ PERn[3:0] are used
x1 Mode: Either PERp[0]/ PERn[0] is used or PERp[7]/ PERn[7] is used
PE_RCOMP[1:0] I PCI Express Compensation Inputs: Analog signals. Connect to a
24.9Ω±1% pull-up resitor to 1.5V. A single resistor can be used for both
signals.
Total 36
41110 Bridge — Datasheet
10
2.3 PCI Bus Interface
Table 3. PCI Interface Pins (Sheet 1 of 2)
Signal I/O Description
A_AD[31:0] I/O
PCI Address/Data: These signals are a multiplexed address and data bus. During the address
phase or phases of a t ransaction, the initiator drives a physical address on A_AD[31:0]. During the
data phases of a transaction, the initiator drives write data, or the target drives read data.
No External pull-up resistors are required on the system board for these signals.
A_C/BE#[3:0] I/O
Bus Comm a nd and Byte Enables: These signals are a multiplexed command field and byte
enable field. During the address phase or phases of a transaction, the initiator drives the
transaction type on C/BE#[3:0]. When there are two address phases, the first address phase
carries the dual address command and the second address phase carries the transaction type.
For both read and write transactions, the initiator drives byte enables on C/BE#[3:0] during the
data phases.
No External pull-up resistors are required on the system board for these signals.
A_PAR I/O
Parity: Even parity calculated on 36 bits - AD[31:0] plus C/BE[3:0]#. It is calculated on all 36 bits
regardless of the valid byte enables. It is generated for address and data phases. It is driven
identically to the AD[31:0] lines, except it is delayed by exactly one PCI clock. It is an output during
the address phase for all 41110 Bridge initiated transactions and all data phases when the 41110
Bridge is the initiator of a PCI write transaction, and when it is the target of a read transaction.
411 10 Bridge chec ks parity when it is the initiator of PCI read transactions and when it is the target
of PCI write transactions.
No External pull-up resistors are required on the system board for these signals.
A_DEVSEL# I/O
Device Select: The bridge asserts DEVSEL# to claim a PCI transaction. As a target, the 41110
Bridge asserts DEVSEL# when a PCI master peripheral attempts an access an address destined
for PCI Express. As an initiator, DEVSEL# indicates the response to a 41110 Bridge initiated
transaction on the PCI bus. DEVSEL# is tri-stated from the leading edge of A_RST#. DEVSEL#
remains tri-stated by the 41110 Bridge until driven as a target.
No External pull-up resistors are required on the system board for these signals.
A_FRAME# I/O
Frame: FRAME# is driven by the Initiator to indicate the beginning and duration of an access.
While FRAME# is asserted data transfers continue. When FRAME# is negated the transaction is
in the final data phase.
No External pull-up resistors are required on the system board for these signals.
A_IRDY# I/O In itiator Re a dy : IRDY# indicates the ability of the initiator to complete the current data phase of
the transaction. A data phase is completed when both IRDY# and TRDY# are sampled asserted.
No External pull-up resistors are required on the system board for these signals.
A_TRDY# I/O
Target Ready: Indicates the ability of the target to complete the current data phase of the
transaction. A data phase is completed when both TRDY# and IRDY# are sampled asserted.
TRDY# is tri-stated from the leading edge of RST#. TRDY# remains tri-stated by the 41110 Bridge
until driven as a target.
No External pull-up resistors are required on the system board for these signals.
A_STOP# I/O Stop: Indicates that the target is requesting an initiator to stop the current transaction.
No External pull-up resistors are required on the system board for these signals.
A_PERR# I/O
Parity Error: Driven by an external PCI device when it receives data that has a parity error . Driven
by 41110 Bridge when, as a initiator it detects a parity error during a read transaction and as a target
during write transactions.
No External pull-up resistors are required on the system board for these signals.
A_SERR# I System Error: The 41110 Bridge sa mples SE RR# as an input and conditionally forwards it to the
PCI Express.
No External pull-up resistors are required on the system board for these signals.
Datasheet — 41110 Bridge
11
2.4 PCI Bus Interface 64-Bit Extension
A_REQ#[5:0] I PCI Requests: REQ# receives request inputs into the internal arbiter.
No External pull-up resistors are required on the system board for these signals.
A_GNT#[5:0] O PCI Grants: GNT# is the bus grant output corresponding to request input bits[5:0] from the
internal arbiter. GNT# indicates that an initiator can start a transaction on the PCI bus.
No External pull-up resistors are required on the system board for these signals.
A_M66EN I/OD
66 MHz Enable: This input signal from the PCI Bus indicates the speed of the PCI Bus. If it is high
then the Bus speed is 66 MHz and if it is low then the bus speed is 33 MHz. This signal will be
used to generate appropriate clock (33 or 66 MHz) on the PCI Bus.
Use an approximately 8.2KΩ resistor to pull to VCC33 or pull-down to ground.
A_PCIXCAP IPCI-X Capable: Indicates whether all devices on the PCI bus are PCI-X devices, so that the
41110 Bridge can switch into PCI-X mode. Use an approximately 8.2KΩ resistor to pull to VCC33.
A_LOCK# O
PCI Lock: Indicates an exclusive bus operation and may require mult iple transactions to
complete. This signal is an output from the bridge when it is initiating exclusive transactions on
PCI. LOCK# is ignored when PCI masters are granted the bus. Locked transaction do not
propagate upstream.
No External pull-up resistors are required on the system board for these signals.
Total 59
Table 4. PCI Interface Pins: 64-Bit Extensions
Signal I/O Description
A_AD[63:32] I/O
PCI Address/Data: These signals are a multiplexed address and data bus. This bus provides an
additional 32 bits to the PCI bus. During the data phases of a transaction, the initiator drives the
upper 32 bits of 64-bit write data, or the target drives the upper 32 bits of 64-bit read data, when
REQ64# and ACK64# are both asserted.
A_C/BE#[7:4] I/O
Bus Command and Byte enables upper 4 bits: These signals are a multiplexed command field and
byte enable field. For both reads and write transactions, the initiator will drive byte enables for the
AD[63:32] data bits on C/BE7:4] during the data phases when REQ64# and ACK64# are both
asserted.
A_PAR64 I/O PCI interface upper 32 bits parity: This carries the even parity of the 36 bits of AD[63:32] and C/
BE#[7:4] for both address and data phases.
A_REQ64# I/O PCI interface request 64-bit transfer: This is asserted by the initiator to indicate that the initiator is
requesting a 64-bit data transfer. It has the same timing as FRAME#. When the 41110 Bridge is the
initiator, this signal is an output. When the 41110 Bridge is the target this signal is an input.
A_ACK64# I/O PCI interface acknowledge 64-bit transfer: This is asserted by the target only when REQ64# is
asserted by the initiator, to indicate the target ability to transfer data using 64 bits. It has the same
timing as DEVSEL#.
Total 39
Table 3. PCI Interface Pins (Sheet 2 of 2)
Signal I/O Description
41110 Bridge — Datasheet
12
2.5 PCI Bus Interface Clocks and, Reset and Power
Management
2.6 Interrupt Interface
This section lists the interrupt interface signals. There is one set of interrupt signals for the standard
INTA:INTD PCI signals.
2.7 Reset Straps
The following signals are used for static configuration. These signals are all sampled on the rising
edge of PERST#.
Table 5. PCI Clock and Reset Pins
Signal I/O Description
A_CLKO[6:0] O
PCI Clock Output: 33/66/100/133 MHz clock for a PCI device. A_CLK[6] must be connected to the
respective A_CLKIN input. for feeding the PCI interface logic. Unused clock outputs may be
disabled via the “Offset 43: PCLKC – PCI Clock Control” register and should be treated as no
connects on the board.
Note: Registers are listed in the Intel® 41110 Serial to Parallel PCI Bridge
Developer’s Manual.
A_CLKIN IPCI C lock In: This signal is PCI clock feedback input. This pin should be connected to the
corresponding A_CL KO[6] through a 22Ω±1% series res istor.
A_RST# OP CI Reset: The bridge asserts RST# to reset devices that reside on the secondary PCI bus.
A_PME# I
PCI Po wer Ma nagement Event: PCI bus power management event signal. This is a shared open
drain input from all the PCI cards on the corresponding PCI bus segment. This is a level sensitive
signal that will be converted to a PME event on PCI Express.
This pin does not have on-die 8.3K pull-up. This pull-up must be provided externally.
Total 10
Table 6. Interrupt Inte rface Pins
Signal I/O Description
A_INTA#
A_INTB#
A_INTC#
A_INTD# I
Interrupt Request Bus: The interrupt lines fr om PCI interrupt s INTA#:INTD# can be routed to these
interrupt lines.
Refer to the Intel® 41110 Serial to Parallel PCI Bridge Design Guide for more information on device
numbering.
Total 4
Datasheet — 41110 Bridge
13
Table 7. Reset Strap Pins
Signal I/O Description
A_133EN I
PCI-X 133 MHz Enable: This pin, when high, allows the PCI-X segment to
run at 133 MHz when A_PCIXCAP is sampled high. When low, the PCI-X
segment will only run at 100 M H z when A _PCIXC AP is samp led high.
Use an approximately 8.2KΩ resistor to pull to VCC33 or pull-down to
ground.
A_STRAP[6:0] I
Internal Test Modes: Straps 6, 2:0 should be pulled low and straps 5:3
must be pulled high for normal operation.
A_STRAP Logic Level
0‘0’
1‘0’
2‘0’
3‘1’
4‘1’
5‘1’
6‘0’
Use approximately an 8.2KΩ resistor to pull-up to VCC33 or pull-down to
VSS
A_TEST[2:1] IInternal Test Modes: These straps should be pulled high to VCC33.
Use approximately an 8.2KΩ resistor to pull-up to VCC33.
CFGRETRY I
Configurati on R etry: This pin, when sampled high sets the Configuration
Cycle Retry Bit (bit 3) in the Bridge Initialization Register at Offset FC.
If no local initialization is needed, this pin should be pulled low to VSS.
Refer to the Intel® 41110 Serial to Parallel PCI Bridge Design Guide for
more information.
STRAP_V_1 I Pull up to VCC33
STRAP_V_2 I Pull up to VCC33
STRAP_V_3 I Pull up to VCC33
STRAP_V_4 I Pull up to VCC33
STRAP_V_5 I Pull up to VCC33
STRAP_V_6 I Pull up to VCC33
STRAP_V_7 I Pull up to VCC33
STRAP_V_8 I Pull up to VCC33
STRAP_V_9 I Pull up to VCC33
STRAP_V_10 I Pull up to VCC33
STRAP_V_11 I Pull up to VCC33
STRAP_V_12 I Pull up to VCC33
STRAP_V_13 I Pull up to VCC33
STRAP_V_14 I Pull up to VCC33
STRAP_V_15 I Pull down to GND
Total 27
41110 Bridge — Datasheet
14
2.8 SMBus Interface
Table 8. SMBus Interface Pins
2.9 Mi scellane ous Pins
Table 9. Miscellaneous Pins
Signal I/O Description
SMBCLK I/OD SMBus Clock: This signal should be pulled to 3.3V via an 8.2KΩ
resistor.
SMBDAT I/OD SMBus Data: This signal should be pulled to 3.3V via an 8.2KΩ
resistor.
SMBUS[5]
SMBUS[3:1] I
SMBus Addressing Strap s : These straps set the SMBus Address for
41110 Bridge. The address is determined as indicated below:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
‘1’
‘1’
SMBUS[5]
‘0’
SMBUS[3]
SMBUS[2]
SMBUS[1]
These signals (bits 5, 3:1) should be pulled up to 3.3V or down to
ground. Sampled at the rising edge of PERST#.
Total 6
Signal I/O Description
CFGRST# O
Configur ation R e set: This signal is asserted low when ever the bridge
goes through a fundamental reset (PERST#, RSTIN#, or PCI Express
Reset). This signal should be used to indicate when the local
initialization methods should be executed.
Refer to the Intel® 41110 Serial to Parallel PCI Bridge Design Guide for
more information.
PERST# I PCI Express Fundamental Reset: When low, asynchronous ly resets
the internal logic (including sticky bits).
RSTIN# I Reset In: When Asserted, this signal asynchronously resets the internal
logic and asserts A_RST# output. This signal should be pulled high for
adapter card usage.
TCK I TAP Clock In: This is the input clock to the JTAG TAP controller.
Acceptable frequency is 0-16MHz
If not utilizing JTAG, this signal can be left as a no connect.
TDI I
Test Data In: This is the serial data input to the JTAG BSCAN shift
register chain and to the JTAG BSCAN control logic. This is latched in
on the rising edge of TCK.
If not utilizing JTAG, this signal can be left as a no connect.
TDO O Test Data Output: This is the serial data output from the JTAG BSCAN
logic
If not utilizing JTAG, this signal can be left as a no connect.
Datasheet — 41110 Bridge
15
TMS I
Test Mode Select: This signal controls the TAP controller state
machine to move to different states and is sampled on the rising edge of
TCK.
If not utilizing JTAG, this signal can be left as a no connect.
TRST# I
Test Reset In: This signal is used to asynchronously reset the JTAG
BSCAN logic.
If not utilizing JTAG, connect this signal to ground through a 1KΩ pull-
down resistor.
RESERVED[8:1] I Reserved: (8 pins) These input pins should be pulled low
Use an approximately 8.2KΩ resistor to pull-down to ground.
NC[19:18], NC[16:1]
A_NC[10:1] ONo Connect: (39 pins) These output pins should be left floating
RESERVED O No Connect
RESERVED O No Connect
CMODE I/O This signal requires an external pull-up, 8.2KΩ to 3.3V
Total 47
Signal I/O Description
41110 Bridge — Datasheet
16
Electrical and Thermal Characteristics 3
3.1 DC Voltage and Current Specifications
3.1.1 41110 Brid ge DC Specifications
1. Transient tolerance ±5 mV above 1 MHz at package pin under DC load conditions.
2. Transient tolerance ±10 mV above 1 MHz at package pin under DC load conditions.
3.2 41110 Bridge Power Consumption
Table 11 provides det ails on the max imum draw from the p ower planes by th e 41 1 10 Bridge f or use
in voltage regulation.
Table 11. 41110 Bridge Maximum Voltage Plane Currents
Table 12 provides details on the maximum nominal draw from the power planes by the 41110
Bridge for use in thermal design.
Table 10. Intel® 41110 Bridge DC Voltage Specifications
Symbol Parameter Min Typ Max Unit Notes
VCC15 Intel® 41110 Bridge Core 1.425 1.5 1.575 V
VCC15 PCI-X I/O V oltage 1.425 1.5 1.575 V
VCCAPE Analog PCI Express Voltage 1.455 1.5 1.545 V 1
VCCAPCI[2:0] Analog PCI Voltages 1.455 1.5 1.545
VCCBGPE Analog Bandgap Voltage 2.425 2.5 2.575 2
VCCPE PCI Express Interface Voltage 1.46 1.5 1.55 V
VCC33 PCI Bus Interface Voltage 3.0 3.3 3.6 V
PTDP Thermal Design Power 8 W
Power Plane Maximum Voltage Plane Current (Amps)
Frequency (MHz) 133 100 66
Number of Slots 1 2 4
IVCC15 (core 1.5V) 1.68 1.61 1.55
IVCC15 (I/O 1.5V) 0.22 0.22 0.22
IVCCPE (PCI Express 1.5V) 0.69 0.69 0.69
IVCC33 (PCI/PCI-X Mode 1 3.3V) 1.05 1.14 1.22
Datasheet — 41110 Bridge
17
Table 12. 41110 Bridge Thermal Voltage Plane Currents
3.3 Power Delivery Guidelines
Please refer to the Intel® 4111 0 Ser ial to Parallel PCI Brid ge Design Guide.
Power Plane Thermal Voltage Plane Current (Amps)
Frequency (MHz) 133 100 66
Number of Slots 1 2 4
IVCC15 (core 1.5V) 1.24 1.18 1.11
IVCC15 (I/O 1.5V) 0.22 0.22 0.22
IVCCPE (PCI Express 1.5V) 0.69 0.69 0.69
IVCC33 (PCI/PCI-X Mode 1 3.3V) 0.99 1.04 1.10
Table 13. Watts
Frequency (MHz) 133 100 66
Max Watts 6.9 7 7.1
41110 Bridge — Datasheet
18
3.4 Input Characteristic Signal Association
3.5 DC Input Characteristics
3.6 DC Characteristi c Output Signal Association
Table 14. DC Characteristics Input Signal Association
Symbol Signals
VIH1/VIL1
Interrupt Signals: A_INTx (X = A-D)#,
PCI Si gnals: A_AD[63:0], A_CBE[7:0]#, A_PAR, A_DEVSEL#, A_FRAME#, A_IRDY#,
A_TRDY#, A_STOP#, A_PERR#, A_SERR#, A_R EQ[5:0] #, A_M66EN, A_133EN ,
A_PCIXCAP, A_PAR64, A_REQ64#, A_ACK64#,
Clock Signals (3.3 V Only): A_CLKI,
Miscellaneous Signals: PERST#
VIH2/VIL2 PCI Express Signals: REFCLK, REFCLK#, PE TP[7:0 ], PETN[7:0], PE_RCOMP [1 :0]
VIH3/VIL3 SMB Signals: SMBDAT, SMBCLK
Table 15. DC Input Characteristics
Symbol Parameter 3.3 V Signal Unit
Min Max
VIL1 Input Low Volt age -0.5 0.35 VCC33 V
VIH1 Input High Voltage 0.5 VCC33 VCC33 +0.5 V
Symbol Parameter Max
VIL2 Input Low Voltage N/A V
VIH2 Input High Voltage N/A V
VIL3 Input Low Voltage 0.6 V
VIH3 Input High V oltage VCC33 + 0.5 V
Table 16. DC Characteristic Output Signal Association
Symbol Signals
VOH1/VOL1
PCI Si gnals: A_AD[63:0], A_CBE[7:0]#, A_PAR, A_DEVSEL#, A_FRAME#, A_IRDY#,
A_TRDY#, A_STOP#, A_PERR#, A_M66EN, A_GNT[ 6:0]#, A_LOCK#, A_PAR64,
A_REQ64#, A_ACK64# ,
PCI Clock Signals (3.3 V Only): A_CLKO[6:0], A_RST#,
Miscellaneous Signals: CFGRST
VOH2/VOL2 PCI Express Signals: PERP[7:0], PERN[7:0]
VOH3/VOL3 SMBus Si gna ls: SMBDAT, SMBCLK
Datasheet — 41110 Bridge
19
3.7 DC Output Characteristics
3.8 PCI Express Interfa ce DC Specifications
3.8.1 Differential Transmitter (TX) DC Output Specifications
Table 18 defines the DC specifications of parameters for the differential output at all transmitters
(TXs). The parameters are specified at the component pins.
Table 17. DC Output Characteristic
Symbol Parameter 3.3 V Signal Unit Notes
Min Max
VOL1 Output Low Volt age 0.1VCC33 V (5 V) Iout = 6 m A
(3.3 V) Iout = 1500 uA
VOH1 Output High Volt age 0.9VCC33 V (5 V) Iout = -2 mA
(3.3 V) Iout = -500 uA
Symbol Parameter Max Unit Notes
VOL2 Output Low Voltage N/A V
VOH2 Output High Volt age N/A V
VOL3 Output Low Volt age 0.4 V IOL4=14 mA
VOH3 Output High Volt age N/A V Open Drain
Table 18. Differential Transmitter (TX) DC Output Specifications (Sheet 1 of 2)
Symbol Parameter Min Nom Max Units Comments
VTX-DIFFp-p Differential Peak to
Peak Output
Voltage 0.80 1.2 V VTX-DIFFp-p = 2*|VTX-D+-VTX-D-|
See Note 1.
VTX-DE-RATIO De-Emphasized
Differential Output
Voltage (Ratio) -3.0 -3.5 -4.0 dB
This is the ratio of the VTX-DIFFp-p of the
second and following bits after a
transition divided by the VTX-DIFFp-p of
the first bit after a transition
See Note 1.
VTX-CM-ACp AC Peak
Common Mode
Output Voltage 20 mV
VTX-CM-ACp = |VTX-D+ + vTX-D-| / 2 – v TX-
CM-DC
vTX-CM-DC = DC(avg) of |VTX-D+ + VTX-D-|
/ 2 during L0
See Note 1.
VTX-CM-DC-
ACTIVE-IDLE-
DELTA
Absolute Delta of
DC Common Mode
Voltage During L0
and Electrical Idle
0 100 mV
|VTX-CM-DC [during L0] – VTX-CM-Idle-
DC[during electrical idle]| <= 100mv
VTX-CM- DC = DC(avg) of |VTX-D+ + VTX-D-|
/ 2 [electrical idle]
See Note 1.
41110 Bridge — Datasheet
20
1. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 2,
“Compliance Test/Measurement Load” on page 23 and measured over any 250 consecutive TX UIs. (Also
refer to the Transmitter Compliance Eye Diagram as shown in Minimum Transmitter Timi ng and Voltage
Output Compliance Specification.)
2. The transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a
common mode return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This
input impedance requirement applies to all valid input levels. The reference impedance for return loss
measurements is 50W to ground for both the D+ and D- line (i.e., as measured by a V ector Network Analyzer
with 50W probes – see Figure 2). Note that the series capacitors CTX is optional for the return loss
measurement.
VTX-CM-DC-
LINE-DELTA
Absolute Delta of
DC Common Mode
V oltage between D+
and D-.
025mV
|VTX-CM-DC-D+ [during L0] – VTX-CM-DC-D-
[During L0.]|<=25mV
VTX-CM-DC-D+ = DC(avg) of |VTX-D+|
[during L0]
VTX-CM-DC-D- = DC(avg) of |VTX-D-|
[during L0]
See Note 1.
VTX-IDLE-
DIFFp
Electrical Idle
Differential Peak
Output Vo ltage 020mV
VTX-ID LE-DIFFp =|VTX-Idle-D+ -VTx-Idle-D-
|<=20mV
See Note 1.
VTX-RCV-
DETECT
The amount of
voltage change
allowed during
Receiver Detection.
600 mV
The total amount of voltage change that
a transmitter can apply to sense
whether a low impedance receiver is
present.
RLTX-DIFF Differential Return
Loss 12 dB Measured over 50 MHz to 1.25 GHz
See Note 2.
RLTX-CM Common Mode
Return Loss 6dB
Measured over 50 MHz to 1.25 GHz
See Note 2.
ZTX-DIFF-DC DC Differential TX
Impedance 80 100 120 Ohms TX DC Differential Mode Low
impedance
ZTX-COM-
High-
IMP-DC
Transmitter
Common Mode
High Impedance
State (DC)
5 k 20k Ohms TX DC High Impedance.
CTX AC Coupling
Capacitor 75 200 nF
All transmitters shall be AC coupled.
The AC coupling is required either
within the media or within the
transmitting component itself.
Table 18. Differential Transmitter (TX) DC Output Specifications (Sheet 2 of 2)
Datasheet — 41110 Bridge
21
3.8.2 Differential Receiver (RX) DC Input Specifications
Table 19 defines the DC specifications of parameters for all differential Receivers (RXs). The
parameters are specified at the component pins.
1. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 2,
“Compliance Test/Measurement Load” on page 23 should be used as the RX device when taking
measurements (also refer to the Receiver Compliance Eye Diagram as shown in Figure 3, “Minimum
Receiver Eye Timing and Voltage Compliance Specification” on page 23). If the clocks to the RX and TX are
not derived from the same clock chip the TX UI must be used as a reference for the eye diagram.
2. The receiver input impedance shall result in a differential return loss greater than or equal to 15 dB and a
common mode return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This
input impedance requirement applies to all valid input levels. The reference impedance for return loss
measurements for is 50 Ω to ground for both the D+ and D- line (i.e., as measured by a Vector Network
Analyzer with 50Ω probes - see Figure 2). Note : that th e se r i e s c a pacito rs CTX is optional for the return loss
measurement.
3. Impedance during all operating conditions.
4. The Rx DC Common Mode Impedance that must be present when the receiver terminations are first enabled
to ensure that the Receiver Detect occurs properly. Compensation of this impedance can start immediately
and the (ZRX-COM-DC)RxDC Common Mode Impedance must be with in the specified range by the time
Detect is entered.
Table 19. Differential Receiver (RX) DC Input Specifications
Symbol Parameter Min Nom Max Units Comments
VRX-DIFFp-p Differential Input
Peak to Peak
Voltage 0.175 1.200 V VRX-DIFFp-p = 2*|VRX-D+ - VRX-D-|
See Note 1.
VRX-CM-ACp AC Peak
Common Mode
Input Voltage 150 mV
VRX-CM-AC=
|VRX-D+ + VRX-D-| /2– VRX-CM-DC
VRX-CM-DC =
DC(avg) of |VRX-D++VRX-D-|/2 during
L0
See Note 1.
RLRX-DIFF Differential
Return Loss 15 dB Measured over 50 MHz to 1.25 GHz
See Note 2.
RLRX-CM Common Mode
Return Loss 6dB
Measured over 50 MHz to 1.25 GHz
See Note 2
ZRX-DIFF-DC DC Differential
Input Impedance 80 100 120 Ohms RX DC Differential Mode
impedance.
See Note 3.
ZRX-COM-DC DC Inpu t
Common Mode
Input Impedance 40 50 60 Ohms RX DC Common Mode impedance
50 ?+/-20% tolerance.
See Notes 1 and 3.
ZRX-COM-INITIAL-DC Initial DC Input
Common Mode
Input Impedance 55060Ohms
RX DC Common Mode impedance
allowed when the receiver
terminations are first powered on.
See Note 4.
ZRX-COM-HIGH-IMP-DC
Powered Down
DC Input
Common Mode
Input Impedance
200 k Ohms
RX DC Common Mode impedance
when the receiver terminations are
not powered (i.e., no power).
See Note 5.
VRX-IDLE-DET-DIFFp-p Electrical Idle
Detect Threshold 65 175 mV
VRX-IDLE-DET-DIFFp-p =2*|VRX-D+ -
VRX-D-|
Measured at the package pins of
the Receiver.
41110 Bridge — Datasheet
22
5. The Rx DC Common Mode Impedance that exists when the receiver terminations are disabled or when no
power is present. This helps ensure that the Receiver Detect circuit will not falsely assume a receiver is
powered on when it is not.
There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be
aligned in time using the jitter median to locate the center of the eye diagram. The different eye
diagrams will differ in voltage depending whether it is a transition bit or a de-emphasized bit.
The eye diagram must be valid for any 250 consecutive UIs. An appropriate average TX UI must
be used as the interval for measuring the eye diagram.
3.8.3 Compliance Test and Measurement Load
The AC timing and voltage parameters must be verified at the measurement point, as specified by
the device vendor within 0.2 inches of the package pins, into a test/measurement load shown in
Figure 2.
Note: The allowance of the measurement point to be within 0.2 inches of the package pins is meant to
acknowledge that pa ckage/board r outing may b enefit from D+ and D- not bei ng exactly matched in
length at the package pin boundary. If the vendor does not explicitly state where the measurement
point is located, the measuremen t poin t is assumed to be the D+ and D-package pins.
Figure 1. Minimum Transmitter Timing and Voltage Output Compliance Specification
Datasheet — 41110 Bridge
23
The test load is shown at the transmitter package reference plane, but the same Test/Measurement
load is applicable to the receiver package reference plane. CTX is an optional portion of the
measurement test load. The measurement should be taken on the opposite side of the capacitor
from the package, and the value of the CTX must be in the range of 75 nF to 200 nF.
.
The RX eye diagram must be aligned in time using the jitter median to locate the center of the eye
diagram. The eye diagram must be valid for any 250 consecutive UIs. An appropriate average TX
UI must be used as the interval for measuring the eye diagram.
Figure 2. Compliance Test/Measurement Load
Figure 3. Minimum Receiver Eye Timing and Voltage Compliance Specification
41110 Bridge — Datasheet
24
3.8.4 PCI and PCI - X Interfac e DC Spe cifications
Table 20 summarizes the DC specifications for 3.3V signaling.
Table 20. DC Specifications for PCI and PCI-X 3.3 V Signaling
Symbol Parameter Min Max Units Condition Notes
VCC33 Supply Voltage 3.0 3.6 V
Vih Input High Voltage 0.5 VCC33 VCC33 +0.5 V
Vil Input Low Voltage -0.5 0.3VCC33 V
Vipu Input Pull-up Voltage 0.7VCC33 V
Iil Input Leakage Current ±10 µA0 < V
in < VCC 3 3 1
Voh Output High Voltage 0.9VCC33 V Iout = -500 µA
Vol Output Low Voltage 0.1VCC33 V Iout = 1500 µA
Cin Input Pin Capacitance 10 pF 2
Cclk A_CLKIN Pin Capacitance 5 8 pF
CIDSEL IDSEL Pin Capacitance 8 pF 3
Lpin Pin Inductance 20 nH 4
IOff A_PME# input leakage - 1 µAVo ≤ 3.6 VCC33 off or
floating 5
1. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.
2. Absolute maximum pin capacitance for a PCI/PCIX input except A_CLKIN and A_IDSEL.
3. For conventional PCI only, lower capacitance on this input-only pin allows for non-resistive coupling to
A_AD[xx]. PCI-X configuration transactions drive the AD bus four clocks before A_FRAME# asserts (see Sec-
tion 2.7.2.1, “Configuration T ransaction Timing,” in the PCI-X Protocol Addendum to the PCI Local Bus Spec-
ification Revision 2.0a).
4. For conventional PCI, this is a recommendation, not an absolute requirement. For PCI-X, this is a require-
ment.
5. This input leakage is the maximum allowable leakage into the A_PME# open drain driver when power is re-
moved from VCC33 of the component . This assumes that no event has occurred to cause the dev ice to at-
tem p t to a ss ert A_PME#.
Datasheet — 41110 Bridge
25
3.8.4.1 Input Clock DC Specifications
3.8.4.2 Output Clock DC Specifications
3.9 AC Specificatio ns
3.9.1 PCI and PCI-X AC Ch aracteristics
Table 21. DC Specification for Input Clock Signals
Symbol Parameter Min Max Units
CLK100 Input Low V oltage -0.5 0.8 V
CLK100 Input High Voltage 2.0 VCC3.3 + 0.5 V
CLK133 Input Low V oltage -0.5 0.8 V
CLK133 Input High Voltage 2.0 VCC3.3 + 0.5 V
Table 22. DC Specification for Output Clock Signals
Symbol Parameter Min Max Units Condition
CLK33 Output Low Voltage 0.4 V Iol = 1 mA
CLK33 Output High Voltage 2.4 V Ioh= -1 mA
CLK66 Output Low Voltage 0.4 V Iol = 1 mA
CLK66 Output High Voltage 2.4 V Ioh= -1 mA
CLK100 Output Low Voltage 0.4 V Iol = 1 mA
CLK100 Output High Voltage 2.4 V Ioh= -1 mA
CLK133 Output Low Voltage 0.4 V Iol = 1 mA
CLK133 Output High Voltage 2.4 V Ioh= -1 mA
Table 23. Conventional PCI 3.3V AC Characteristics
Sym Parameter Condition Min Max Unit Note
Ioh(AC) Switching Current
High Vout = 0.7VCC33 -32VCC33 mA
Vout = 0.3VCC33 -12VCC33 mA 1
Iol(AC) Switching Current
Low
Vout = 0.18VCC33 38VCC33 mA
Vout = 0.6VCC33 16VCC33 mA 1
Ich High Clamp Current VCC33 + 4 > Vin
VCC33 + 1
25 + (Vin –
VCC33 – 1) /
0.015 mA
Icl Low Clamp Current -3 < Vin -1 -25 + (Vin + 1) /
0.015 mA
slewrOutput Rise Slew
Rate 0.3VCC33 to
0.6VCC33 14V/ns2
slewfOutput Fall Slew
Rate 0.6VCC33 to
0.3VCC33 14V/ns
2
41110 Bridge — Datasheet
26
1. In conventional PCI switching, current characteristics for A_REQ# and A_GNT# are permitted to be one half
of that specified here; i.e., half size drivers may be used on these signals. This specification does not apply to
CLK and RSTIN# which are system outputs. “Switching Current High” specifications are not relevant to
A_SERR# which is an open drain output.
2. This parameter is to be interpreted as the cumulative edge rate across the specified range rather than the
instantaneous rate at any point within the transition range. For more details on slew rate measurement
conditions please refer to the PCI-X Electrical and Mechanical Addendum to the PCI Local Bus Specification,
Revision 2.0a
1. In conventional PCI switching, current characteristics for A_REQ# and A_GNT# are permitted to be one half
of that specified here; i.e., half size drivers may be used on these signals. This specification does not apply to
CLK and RST# which are system outputs. “Switching Current High” specifications are not relevant to
A_SERR#, which is an open drain output.
2. This parameter is to be interpreted as the cumulative edge rate across the specified range rather than the
instantaneous rate at any point within the transition range. For more details on slew rate measurement
conditions please refer to the PCI-X Electrical and Mechanical Addendum to the PCI Local Bus Specification,
Revision 2.0a.
3.10 Volt age Filter Specifications
The 41110 Bridge requires voltage filtering to reduce noise on critical voltage planes. There are
two filter types necessary on the platform:
Table 24. PCI-X 3.3V AC Characteristics
Sym Parameter Condition Min Max Unit Note
Ioh(AC) Switching Current High
0 < VCC33 –
Vout 3.6V -74(VCC33 -
Vout)mA
0 < VCC33 –
Vout 1.2V -32 (VCC33 –
Vout)mA 1
1.2V < VCC33 –
Vout 1.9V -11 (V CC33 -
Vout) – 25.2 mA 1
1.9V < VCC33 –
Vout 3.6V -1.8 (VCC33 -
Vout) – 42.7 mA 1
Iol(AC) Swit ching Current Low
0 Vout 3.6V 100V out mA
0 < Vout 1.3V 48V out 1
1.3V < Vout
3.6V 5.7Vout + 55 1
Icl Low Clamp Current
-3V < Vin ≤ -
0.8875V -40 + (Vin + 1) /
0.005 mA
-0.8875V < Vin ≤
-0.625V -25 + (Vin + 1) /
0.015 mA
Ich High Clamp Current
0.8875V < Vin –
VCC33 ≤ -4V
40 + (Vin –
VCC33 - 1) /
0.005 mA
0.625V < Vin –
VCC33 ≤
0.8875V
25 + (Vin –
VCC33 - 1) /
0.015 mA
slewrOutput Rise Slew Rate 0.3VCC33 to
0.6VCC33 14V/ns2
slewfOutput Fall Slew Rate 0.6VCC33 to
0.3VCC33 14V/ns2
Datasheet — 41110 Bridge
27
•Analog Voltage Filter (PCI-Express and PCI)
•Bandgap Filter
Note: For filter specifications, refer to the Intel® 41110 Serial to Parallel PCI Bridge Design G uide.
3.11 VCC15 and VCC33 Volt age Requirements
The 41110 Bridge requires that the VCC33 voltage rail be equal to or no less than 0.5V below
VCC15 (absolute voltage value) at all times during 41110 Bridge operation, including during
system power up and power down. In other words, the following must always be true:
VCC33 ≥ (VCC15 –0.5V)
Figure 4 graphically illustrates this requirement. This can be accomplished by placing a diode (with
a voltage drop < 0.5V) between VCC15 and VCC33. Anode will be connected to VCC15 and
cathode will be connected to VCC33.
Figure 4. Voltage Requirements VCC33 versus VCC15
41110 Bridge — Datasheet
28
3.12 Timing Specifications
3.12.1 PCI Express Interface Timing
3.12.1.1 Differential Transmitter (TX) AC Output Specifications
Table 25 defines the AC specifications of parameters for the differential output at all transmitters
(TXs). The parameters are specified at the component pins.
1. N o test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 2,
“Compliance Test/Measurement Load” on page 23 and measured over any 250 consecutive TX UIs. (Also
Table 25. Differential Transmitter (TX) AC Output Specifications
Symbol Parameter Min Nom Max Units Comments
UI Unit Interval 399.88 400 400.12 ps
Each UI is 400 ps +/-
300 ppm. UI does not
account for SSC
dictated variations.
See Note 1.
TTX-EYE Minimum TX Eye
Width 0.70 UI
The maxi mum
transmitter jitter can be
derived as TTX-MAX-
JITTER = 1 - TTX-EYE =
.3 UI
See Notes 2 and 3.
TTX-EYE-MEDIAN-to-MAX-JITTER
Maximum time
between the jitter
median and
maximum
deviation for the
median
0.15 UI
Jitter is defined as the
measurement variation
of the crossing points
(VTX-DIFFp-p = 0V) in
relation to an
appropriate average
TX UI. See Notes 2
and 3.
TTX-RISE, TTX-FALL D+/D- TX Outpu t
Rise/Fall Time 0.125 UI See Notes 2 and 4.
TTX-IDLE-MIN Minimu m time
spent in Electrical
Idle 50 UI Minimum time a
transmitter must be in
electrical idle.
TTX-IDLE-SET-
TO-IDLE
Maximum time to
transition to a
valid Electrical
Idle after sending
an Electrical Idle
ordered-set
20 UI
After sending an
electrical idle ordered-
set, the transmitter
must meet all electrical
idle specifications
within this time.
TTX-IDLE-RCV-
DETECT-MAX
Maximum time
spent in Electrical
Idle before
initiating a
receiver detect
sequence.
100 ms
Maxi mum tim e spe nt i n
Electrical Idle before
initiating a receiver
detect sequence.
LTX-SKEW Lane-to-Lane
Output Skew 500 ps Between any two
Lanes within a single
Transmitter.
Datasheet — 41110 Bridge
29
refer to the Transmitter Compliance Eye Diagram as shown in Minimum Transmitter Timing and Voltage
Output Compliance Specification.)
3. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX =
0.30 UI for the transmitter collected over any 250 consecutive TX UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER
specification ensures a jitter distribution in which the median and the maximum deviation from the median is
less than half of the total TX jitter budget collected over any 250 consec utive TX UIs. It should be noted that
the median is not the same as the mean. The jitter median describes the point in time where the number of
jitter points on either side is approximately equal as opposed to the averaged time value.
4. Measured between 20-80% at Transmitter package pins into a test load as shown in Figure 2 for both VTX-D+
and VTX-D-.
3.12.1.2 Differential Receiver (RX) AC Input Specifications
Table 26 defines the AC specifications of parameters for all differential Receivers (RXs). The
parameters are specified at the component pins.
1. No test load is necessarily associated with this value.
2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 2,
“Compliance Test/Measurement Load” on page 23 should be used as the RX device when taking
measurements (also refer to the Receiver Compliance Eye Diagram as shown in Figure 3, “Minimum
Receiver Eye Timing and Voltage Compliance Specification” on page 23). If the clocks to the RX and TX are
not derived from the same clock chip the TX UI must be used as a reference for the eye diagram.
3. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the
transmitter and interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER
specification ensures a jitter distribution in which the median and the maximum deviation from the median is
less than half of the total .6 UI jitter budget collected over any 250 consecutive TX UIs. It should be noted that
the median is not the same as the mean. The jitter median describes the point in time where the number of
jitter points on either side is approximately equal as opposed t o the averaged time value. If the clocks to the
RX and TX are not derived from the same clock chip, the appropriate average TX UI must be used as the
reference for the eye diagram.
Table 26. Differential Receiver (RX) AC Input Specifications
Symbol Parameter Min Nom Max Units Comments
UI Unit Interval 399.88 400 400.12 ps T he UI is 400 ps +/-300 ppm. UI
does not account for SSC dictated
variations. See Note 1.
TRX-EYE Minimum
Receiver Ey e
Width 0.4 UI
The maximum interconnect media
and transmitter jitter that can be
tolerated by the receiver can be
derived asTRX-MAX-JITTER =1 -TRX-
EYE =0.6 UI
See Notes 2 and 3.
TRX-EYE-
MEDIAN-to-
MAX-JITTER
Maximum time
between the jitter
median and
maximum
deviation from
the median.
0.3 UI
Jitter is defined as the
measurement variation of the
crossing points (VRX- DIFFp-p = 0 V)
in relation to an appropriate
average TX UI.
See Notes 2 and 3.
TRX-IDLE-DET-
DIFF-
ENTERTIME
Unexpected
Electrical Idle
Enter Dete c t
Threshold
Integration Time
10 ms
An unexpected electrical idle (VRX-
DIFFp-p <VRX-IDLE-DET- DIFFp -p) must
be recognized no longer than TRX-
IDLE-DET- DIFF-ENTERTIME to signal
an unexpected idle condition.
LRX-SKEW Total Skew 20 ns
Across all Lanes on a port. This
includes variation in the length of a
skip ordered-set (e.g., COM and 1
to 5 SKP symbols) at the RX as well
as any delay differences arising
from the interconnect itself.
41110 Bridge — Datasheet
30
3.12.2 PCI and PC I-X Interface Timing
1. It is important that all driven signal transitions drive to their Voh or Vol level within one Tcyc.
2. Minimum times are measured at the package pin (not the test point) with the load circuit shown in the PCI-X
Electrical and Mechanical Addendum, Revision 2.0a. Maximum times are measured with the test point and
load circuit shown in the PCI-X Electrical and Mechanical Addendum, Revision 2.0a.
3. A _REQ_[5:0]# and A_GNT_ [5:0]# are point-to-point signals and have different input setup times than do
bused signals. A_GNT_[5:0]# and A_REQ_[5:0]# have a setup of 5 ns at 66 MHz. All other signals are
bused.
4. S ee Section 3. 12, “Timing Specifications” on page 28 and the measurement conditions in the PCI- X Elect rical
and Mechanical Addendum, Revision 2.0a.
5. If A_M66EN is asserted, CLK is stable when it meets the requirements in the PCI Local Bus Spec ification
Revision 2.3. RSTIN# is asserted and deasserted asynchrono usly with respect to CLK.
6. When A_M66EN is asserted, the mi nimum specification for Tval(min ), Tval(ptp)(min), and Ton may be reduced
to 1 ns if a mechanism is provided to guarantee a minimum value of 2 ns when A_M66EN is deasserted.
7. For purposes of active/float timing measurements, the Hi-Z or “off” state is defined to be when the total
current delivered through the component pin is less than or equal to the leakage current specification.
8. S etup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at
the same time. Refer to the PCI Local Bus Specification Revision 2.3 for more details.
9. M axim um value is also limited by delay to the first transaction (Trhff).
Table 27. PCI Interface Timing
Functional Operating Range (VCC33 = 3.3 V + 5%, Tcase=0°C to 105°C)
66 MHz 33 MHz
Symbol Parameter Min Max Min Max Units Notes
Tval CLK to Signal Valid Delay;
bused signals 2 6 2 11 ns 1, 2, 3
Tval(ptp) CLK to Signal Valid Delay;
point-to-point signals 2 6 2 12 ns 1, 2, 3
Ton Float to Active Delay 2 2 ns 1, 7
Toff Acti v e to F lo a t D e lay 14 28 ns 1, 7
Tsu Input Setup Time to CLK;
Bused signals 3 7 ns 3, 4, 8
Tsu(ptp) Input Setup Time to CLK;
point-to-point 5 10,12 ns 3, 4
ThInput Hold Time from CLK 0 0 ns 4
Trst Reset Ac tive Ti me after p o wer
stable 11ms5
Trst-clk Reset Active T ime af te r CLK
stable 100 100 µs5
Trst-off Reset Active to output float delay 40 40 ns 5, 6
Trrsu PaREQ64# to RSTIN# setup time 10 10 clocks
Trrh RSTIN# to PaREQ64# hold Time 0 50 0 50 ns 9
Trhfa RSTIN# high to first configuration
access 225 225 clocks
Trhff RSTI N # hig h to fir st PaFR AME#
Assertion 55clocks
Tpvrh Power Valid to RSTIN# High 100 100 ms
Datasheet — 41110 Bridge
31
Figure 5. PCI Output Timing
Figure 6. PCI Input Timing
Table 28. PCI-X 3.3V Signal Timing Parameters (Sheet 1 of 2)
Sym Parameter PCI-X 133 PCI-X 66 Units Notes
Min Max Min Max
Tval CLK to Signal Valid Delay 0.7 3. 8 0.7 3.8 ns 1, 2, 8
41110 Bridge — Datasheet
32
1. S ee the timing measurement conditions in Section 3.12, “Timing Specifications” on page 28.
2. Minimum times are measured at the package pin (not the test point) with the load circuit shown in the PCI-X
Electrical and Mechanical Addendum, Revision 2.0a. Maximum times are measured with the test point and
load circuit shown in PCI-X Electrical and Mechanical Addendum, Revision 2.0a.
3. S ee the timing measurement conditions in Section 3.12, “Timing Specifications” on page 28 and the PCI-X
Electrical and Mechanical Addendum, Revision 2.0a.
4. RST# is asserted and deasserted asynchronously with respect to CLK.
5. Fo r purpos es of Active/Float timing measur ements, the Hi-Z or "off" state is defined to be when the total
current delivered through the component pin is less than or equal to the leakage current specification
6. S etup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at
the same time.
7. M axim um value is also limited by delay to the first transaction (Trhfa). The PCI-X initialization pattern control
signals after the rising edge of RSTIN# must be deasserted no later than two clocks before the first
PaFRAME# and must be floated no later than one clock before PaFRAME# is asserted.
8. D evice must meet this specification independent of how many outputs switch simultaneously.
Ton Float to Act i ve D e l a y 0 0 ns 1, 6, 8
Toff Acti ve to Floa t D el a y 7 7 ns 1, 6 , 8
Tsu Input Setup Time to CLK 1.2 1.7 ns 3, 7
ThInput Hold Time from CLK 0.5 0.5 ns 3
Trst Reset Ac tiv e Time after power
stable 11ms4
Trst-clk Reset Active Time after CLK stable 100 100 µs4
Trst-off Reset Active to output float delay 40 40 ns 4
Trrsu PaREQ64# to RSTIN# setup time 10 10 ns
Trrh RSTIN# to PaREQ64# hold Time 0 50 0 50 ns 7
Trhfa RSTIN# high to first configuration
access 226 226 clocks
Trhff RSTI N # hig h to fi rst PaF R AME#
Assertion 55clocks
Tpvrh Power valid to RSTIN# high 100 100 ms
Tprsu PCI-X initialization pattern to
RSTIN# setup time 10 10 clocks
Tprh RSTIN# to PCI-X initialization
pattern hold time 0 50 0 50 ns 7
Trlcx Delay from RSTIN# low to CLK
frequency change 00ns
Table 28. PCI-X 3.3V Signal Timing Parameters (Sheet 2 of 2)
Datasheet — 41110 Bridge
33
3.12.3 PCI and PCI-X Clock Specification
Clock measurement conditions are the same for PCI-X devices as for conventional PCI devices in a
3.3V si gn aling envir onmen t ex cept for volt age l evels s pecifi ed i n Table 29, “PCI and PCI- X Clock
Timings” on page 34. The same spread-spectrum clocking techniques are allowed in PCI-X as for
66 MHz conventional PCI. If a device includes a PLL, that PLL must track the input variations of
spread-spectrum clocking specified in Table 29.
Figure 7. PCI-X 3.3V Clock Waveform
41110 Bridge — Datasheet
34
1. For clock frequencies above 33 MHz, the clock frequency may not change beyond the spread-spectrum and
jitter limits except while RSTIN# is asserted.
2. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in the
PCI-X Electrical and Mechanical Addendum, Revis ion 2.0a.
3. The minimum clock period must not be violated for any single clock cycle (i.e. accounting for all system jitter).
4. Average Tcyc is measured over any 1 µs period of time and must include all sources of clock variation.
5. Period jitter is the deviation between any single period of the clock, Tcyc, and the average period of the clock,
Tcyc(average).
Table 29. PCI and PCI-X Clock Timings
Symbol Parameter PCI-X 133 PCI-X 66 PCI 66 PCI 33
Min Max Min Max Min Max Min Max Units Notes
Tcyc CLK Cycle
Time
Average 7.5 20 15 20 15 30 30 ∞ns 1,3,4
Absolute
Minimum 7.375 14.8 14.8 29.7 ns 1,3
Thigh CLK high
time 36611ns
Tlow CLK low
time 36611ns
Tjit CLK Period
Jitter 125 -125 200 -200 200 -200 300 -300 ps 5
Slew Rate
—CLK slew
rate 1.5 4 1.5 4 1.5 4 1 4 V/ns 2
Spread Spectrum Requirements
fmod Modulation
frequency 30 33 30 33 30 33 kHz
fspread Frequency
spread -10-10-10 %
Datasheet — 41110 Bridge
35
3.12.4 41110 Bridge Clock Timings
1. Period, jitter, offset and skew measured on rising edge @ 1.5V for 3.3V clocks.
Table 30. 41110 Bridge Clock Timings
Symbol Parameter Min Max Units Notes
CLK100
Tperiod Average Period 10.0 10. 2 ns 6
Trise Rise time across 600 mV 300 600 ps 7,8
Tfall Fall time across 600 mV 300 600 ps 7,8
— Rise/Fall Matching 20% 7,9
— Cross point at 1 V 0.51 0.76 V
Tccjitter Cycle to Cycle jitter 200 ps
—Duty Cycle4555%
— Maximum voltage allowed at input 1.45 V
— Minimum voltage allowed at input -200 mV
— Ri sing edge ringback 0.85 V
— Falling edge ring back 0.35 V
CLK133
Tperiod Average Period 7.5 7.65 ns 6
Trise Rise time across 600 mV 300 600 ps 7,8
Tfall Fall time across 600 mV 300 600 ps 7,8
— Rise/Fall Matching 20% 7,9
— Cross point at 1V 0.51 0.76 V
Tccjitter Cycle to Cycle jitter 125 ps 10
—Duty Cycle 45 55%
— Maximum voltage allowed at input 1.45 V
— Minimum voltage allowed at input -200 mV
— Rising edge ringback 0.85 V
— Falling edge ring back 0.35 V
CLK33
Tperiod CLK period 30.0 N/A ns 1,2
Thigh CLK high time 12.0 N/A ns 3
Tlow CLK low time 12.0 N/A ns 4
— Rising edge rate 1.0 4.0 V /ns 5
— Falling edge rate 1.0 4.0 V/ns 5
Trise CLK rise time 0.5 2.0 ns 5
Tfall CLK fall time 0.5 2.0 ns 5
41110 Bridge — Datasheet
36
2. The average period over any 1 us period of time must be greater than the minimum specified period.
3. Thigh is measured at 2.4V for non-host outputs.
4. Tlow is measured at 0.4V for all outputs.
5. For 3.3V clocks Trise and Tfall are measured as a transition t hrough the threshold region Vol = 0.4V and V oh =
2.4V (1 mA) JEDEC Specification.
6. Measured at crossing point.
7. Measured from Vol = 0.2V to Voh = 0.8V.
8. Still simulating to determine [0.2–0.8 V] or [0.3–0.9 V].
9. D eterm ined as a fraction of 2*(Trise – Tfall) / (Trise + Tfall).
10.Period jitter is the deviation between any single period of the clock, Tcyc, and the average period of the clock,
Tcyc(average).
3.12.4.1 Spread Spectrum Clocking
Spread spectrum clocking can be used on the 41110 Bridge to reduce energy. Spread Spectrum
clocking is a common technique used by system designers to meet FCC emissions, where the
frequency is deliberately shifted ar ound to spread the en erg y of f of the peak. The following is to be
observed when using Spread Spectrum clocking:
•All device timings (includ ing jitter, skew, min/max clock period, output rise/fall time) MUST
meet the existing non-spread spectrum specifications
•All non-spread Host and PCI functionality mus t be main tain ed in the spread sp ectrum mod e
(includes all power management functions.)
•The minimum clock period cannot be violated. The preferred method is to adjust the spread
technique to not allow for modulation above the nominal frequency. This technique is often
called “down-spreading”. The modulation profile in a modulation period can be expressed as:
Equations:
where:
fnom is the nominal frequency in the non-SSC mode
fm is the modulation frequency
fm is the modulation amount
t is ti me.
3.13 Reference and Compensation Pins
The 41110 Bridge has one reference pin and two compensation pins:
•PE_RCOMP[1:0] are two separate pins that provide voltage compensation for the PCI
Express interface on the 41110 Bridge. The nominal compensation voltage is 0.5V. An
external 24.9 ±1% pull-up resistor should be used to connect to VCC15. A single pull-up
resistor can be used to for both of these signals.
•RCOMP is an analog PCI interface compensation pin to the 41110 Bridge. A 100 ±1% pull-
down resistor should be used to connect the RCOMP pin to ground.
⎪
⎪
⎩
⎪
⎪
⎨
⎧
<<⋅⋅⋅−+
<<⋅⋅⋅+−
=, )(
; )(
mm
nommnom
m
nommnom
f1
t
f21
when tff2f1
f21
t0when tff2f1
f
δδ
δδ
Datasheet — 41110 Bridge
37
All three of these implementations are shown in Figure 8.
Figure 8. 41110 Bridge Reference and Compensation Circuit Implementations
3.14 Thermal Specifications
Refer to the 6700PXH 64-bit PCI Hub Thermal/Mechanical Design Guide for Intel 6700PXH 64-
bit PCI Hub (PXH).
3.14.1 Power
For TDP specifications, refer to Table 31. FC -BGA p ackages ha ve poor heat transfer capability
into the board and have minimal thermal capability without thermal solutions. Intel recommends
that system designers plan for a heatsink when using the 41110 Bridge component.
3.14.2 Die Temperature
To ensure proper operation and reliability of the 41110 Bridge component, the die temperatures
must be at or below the values specified in Table 31. System and/or component level thermal
solutions are required to maintain die temperatures below the maximum temperature
specifications.
41110 Bridge — Datasheet
38
Table 31. 41110 Bridge Thermal Specifications
Note: Mode 1: PCI-X 66M Hz, 64-bit, 4 slots/devi ces
3.14.3 Thermal Solution Component Suppliers
Table 32. Torsional Clip Heatsink Thermal Solution
Note: The enabled components may not be currently available from all suppliers. Contact the supplier
directly to verify time of component availability.
Parameter Maximum
Tcase 95oC Max
Part Intel Part Number Supplier
(Part Number) Contact Information
Heatsink Assembly includes:
Unidirectional Fin Heatsink
Thermal Interface Material
Tors ional Clip
C76435-001 CCI/ACK
Harry Lin (USA)
714-739-5797
hlinack@aol.com
Monica Chih (Taiwan)
866-2-29952666, x131
monica_chih@ccic.com.tw
Unidirectional Fin Heatsink
(31.0 x 31.0 x 12.2mm) C76434-001 CCI/ACK
Harry Lin (USA)
714-739-5797
hlinack@aol.com
Monica Chih (Taiwan)
866-2-29952666, x131
monica_chih@ccic.com.tw
Thermal Interface
(Chomerics T-710) A69230-001 Chomerics
69-12-22066-T710
Todd Sousa (USA)
360-606-8171
tsousa@parker.com
Heatsink Attach Clip C17725-001 CCI/ACK
Harry Lin (USA)
714-739-5797
hlinack@aol.com
Monica Chih (Taiwan)
866-2-29952666, x131
monica_chih@ccic.com.tw
Solder-Down Anchor A13494-005 Foxconn
(HB96030-DW)
Julia Jiang (USA)
408-919-6178
juliaj@foxconn.com
Datasheet — 41110 Bridge
39
Package Specification and Ballout 4
4.1 Package Specification
The 41110 Bridge is in a 567-ball FCBGA package, 31mm X 31mm in size, with a 1.27mm ball
pitch (see Figure 9 and Figure 10 ).
Figure 9. 41110 Bridge Package Dimen sions (Top View )
41110
Die
Die
Keepout
Area
Handling
Exclusion
Area 0.491 in.
0.291 in.
17.00 m m 21.00 m m 31.00 m m
17.00 m m
21.00 mm
31.00 mm
0.247 in.
0.200 in.
0.547 in.
41110 Bridge — Datasheet
40
Figure 10. 41110 Bridge Package Dimensions (Side View)
Note: Primary datum -C- and seating plane are defined by the spherical crowns of the solder balls.
Note: All dimensions and toler ances con form to AN SI Y14.5M-1982
0.20
0.20 -C-
2.445±0.102 m m
2.010±0.099 mm
0.84±0.05 m m
0.435±0.025 m m
See No te 3
Sea ting Plane
0.7 mm Max
S ee No te 1
Substrate Decoup
Cap See N ote 4.
Notes:
1. Prim ary datum -C- and seating plan are defined b y the spherical crown s of the solder balls (show n before m otherboard attach).
2. All dim ensions and tolerances conform to AN SI Y 14.5M-1994
3. BG A has a pre-SM T height of 0.5 mm and post-SMT height of 0.41-0.46 m m
4. Shown before mo therboard attach; FC B G A has a co nvex (dom e shape ) orientation before reflow and is expected to have a slightly
conc ave (bowl shaped) orientation after reflow .
Die
Datasheet — 41110 Bridge
41
4.2 Signal List, sorted by Ball L ocation
Table 33. Signal List, sorted by Ball Name (Sheet 1 of 4)
Ball Signal Name Ball Signal Name Ball Signal Name
A1 C1 D# E1 NC4
A2 VCC33 C2 VSS E2 VSS
A3 STRAP_V_4 C3 STRAP_V_9 E3 NC9
A4 VSS C4 NC4 E4 NC2
A5 NC2 C5 VSS E5 VSS
A6 TDO C6 NC18 E6 STRAP_V_1
A7 VCC33 C7 SMBCLK E7 TMS
A8 VSS C8 VSS E8 VSS
A9 PETN[5] C9 PERN[5] E9 TDI
A10 PETP[5] C10 PERN[4] E10 VSS
A11 C11 PERP[4] E11 PETP[7]
A12 C12 VCCPE E12 PERN[6]
A13 VSSBGPE C13 PERN[2] E13 VSS
A14 VCCPE C14 VCCBGPE E14 PERN[0]
A15 PERN[1] C15 VCCPE E15 PERP[0]
A16 PERP[1] C16 REFCLKP E16 PE_RCOMP[0]
A17 VSS C17 REFCLKN E17 A_PCIXCAP
A18 SMBUS[3] C18 A_STRAP0 E18 CFGRST#
A19 STRAP_V_15 C19 A_STRAP3 E19 NC6
A20 VSS C20 VSS E20 VSS
A21 A_STRAP4 C21 RESERVED1 E21 A_NC10
A22 NC3 C22 VCC33 E22 A_NC8
A23 A_NC2 C23 VSS E23 VSS
A24 VSS C24 A_INTD# E24 VCC33
B1 NC7 D1 STRAP_V_10 F1 VCC33
B2 NC1 D2 NC3 F2 NC
B3 STRAP_V_3 D3 NC6 F3 NC
B4 STRAP_V_5 D4 STRAP_V_6 F4 NC
B5 STRAP_V_2 D5 VCC33 F5 STRAP_V_7
B6 NC19 D6 NC5 F6 NC7
B7 TCK D7 STRAP_V_12 F7 NC9
B8 CFGRETRY D8 SMBDAT F8 NC8
B9 PERP[5] D9 PETN[6] F9 TRST#
B10 VSS D10 PETP[6] F10 PERP[7]
B11 PETN[4] D11 VSS F11 PETN[7]
B12 PETP[4] D12 PERP[6] F12 VCCPE
B13 VSS D13 PERP[2] F13 PETN[0]
B14 PETN[2] D14 VSS F14 PETP[0]
B15 PETP[2] D15 PETN[1] F15 VSS
B16 VSS D16 PETP[1] F16 VSSAPE
B17 PE_RCOMP[1] D17 VSS F17 PERST#
B18 VCC33 D18 A_STRAP1 F18 NC1
B19 RESERVED D19 A_STRAP5 F19 A_STRAP6
B20 SMBUS[2] D20 SMBUS[5] F20 RESERVED4
B21 RESERVED2 D21 RESERVED3 F21 A_NC9
B22 A_STRAP2 D22 A_NC6 F22 A_TEST1
B23 A_TEST2 D23 A_INTC# F23 A_NC4
B24 A_NC1 D24 A_NC3 F24 A_INTB#
41110 Bridge — Datasheet
42
Ball Signal Name Ball Signal Name Ball Signal Name
G1 NC J1 VSS L1 NC
G2 VSS J2 NC L2 NC
G3 NC J3 NC L3 VCC15
G4 NC J4 VSS L4 NC
G5 VSS J5 NC L5 NC
G6 NC J6 NC L6 VCC33
G7 NC J7 NC L7 NC
G8 VSS J8 VCCAPCI1 L8 NC
G9 NC J9 VSS L9 VSS
G10 PERN[7] J10 VCCPE L10 VCC15
G11 VSS J11 VSS L11 VSS
G12 PERN[3] J12 VCCPE L12 VCC15
G13 PETP[3] J13 VSS L13 VSS
G14 VSS J14 VCCPE L14 VCC15
G15 VCCAPE J15 VSS L15 VSS
G16 SMBUS[1] J16 VCC15 L16 VCC15
G17 VSS J17 A_AD[63] L17 A_AD[59]
G18 NC11 J18 A_CBE5# L18 VSS
G19 NC12 J19 VSS L19 A_AD[58]
G20 VSS J20 A_PAR64 L20 A_AD[43]
G21 A_NC5 J21 A_AD[47] L21 VSS
G22 A_NC7 J22 VSS L22 A_REQ4#
G23 VSS J23 A_AD[46] L23 A_AD[42]
G24 A_INTA# J24 A_GNT1# L24 VSS
H1 NC K1 NC M1
H2 NC K2 VSS M2 NC
H3 VCC33 K3 NC M3 NC
H4 NC K4 NC M4 VSS
H5 NC K5 VSS M5 NC
H6 VSS K6 NC M6 NC
H7 NC K7 NC M7 VSS
H8 NC K8 VSS M8 NC14
H9 NC K9 VCC15 M9 VCC15
H10 VSS K10 VSS M10 VSS
H11 VCCPE K11 VCC15 M11 VCC15
H12 PERP[3] K12 VSS M12 VSS
H13 PETN[3] K13 VCC15 M13 VCC15
H14 VSS K14 VSS M14 VSS
H15 VCCPE K15 VCC15 M15 VCC15
H16 RSTIN# K16 VSS M16 VSS
H17 A_CBE4# K17 A_AD[61] M17 A_AD[57]
H18 VCC33 K18 A_AD[60] M18 A_AD[56]
H19 A_CBE6# K19 A_AD[62] M19 VCC33
H20 A_CBE7# K20 VSS M20 NC15
H21 VCC33 K21 NC13 M21 A_AD[41]
H22 A_AD[49] K22 A_AD[45] M22 VCC15
H23 A_AD[48] K23 VSS M23 A_AD[40]
H24 VCC33 K24 A_AD[44] M24
Table 33. Signal List, sorted by Ball Name (Sheet 2 of 4)
Datasheet — 41110 Bridge
43
Ball Signal Name Ball Signal Name Ball Signal Name
N1 R1 VSS U1 STRAP_V_11
N2 VSS R2 NC U2 NC
N3 NC R3 NC U3 VSS
N4 NC R4 VSS U4 NC
N5 VSS R5 STRAP_V_14 U5 NC
N6 NC R6 NC16 U6 VSS
N7 NC R7 VCC33 U7 NC
N8 NC R8 VCCAPCI2 U8 NC
N9 VSS R9 VSS U9 VCC33
N10 VCC15 R10 VCC15 U10 STRAP_V_13
N11 VSS R11 VSS U11 RESERVED
N12 VCC15 R12 VCC15 U12 VSS
N13 VSS R13 VSS U13 A_CLKIN
N14 VCC15 R14 VCC15 U14 A_CLKO[4]
N15 VSS R15 VSS U15 VSS
N16 VCC15 R16 VCC15 U16 A_CLKO[5]
N17 A_AD[55] R17 VCCAPCI3 U17 A_CLKO[3]
N18 A_REQ3# R18 A_AD[51] U18 VSS
N19 A_AD[54] R19 VSS U19 A_STOP#
N20 VSS R20 A_AD[50] U20 A_DEVSEL#
N21 A_AD[39] R21 A_LOCK# U21 VSS
N22 A_AD[38] R22 VSS U22 A_TRDY#
N23 VSS R23 A_AD[35] U23 A_GNT5#
N24 R24 A_AD[34] U24 VSS
P1 NC T1 NC V1 VSS
P2 STRAP_V_8 T2 VSS V2 NC
P3 VSS T3 NC V3 NC
P4 NC T4 NC10 V4 VCC33
P5 NC T5 VCC33 V5 NC
P6 VSS T6 NC V6 NC
P7 NC T7 NC V7 VSS
P8 NC T8 VSS V8 NC
P9 VCC15 T9 VCC15 V9 NC
P10 VSS T10 VSS V10 VSS
P11 VCC15 T11 VCC15 V11 RCOMP
P12 VSS T12 VSS V12 VCC15
P13 VCC15 T13 VCC15 V13 VSS
P14 VSS T14 VSS V14 A_CLKO[0]
P15 VCC15 T15 VCC15 V15 A_CLKO[6]
P16 VSS T16 VSS V16 VCC15
P17 A_AD[53] T17 VCC33 V17 A_CLKO[2]
P18 VSS T18 A_M66EN V18 A_REQ2#
P19 A_AD[52] T19 A_SERR# V19 VSS
P20 A_PERR# T20 VCC33 V20 A_133EN
P21 VSS T21 A_AD[33] V21 A_PME#
P22 A_AD[37] T22 A_AD[32] V22 VSS
P23 A_AD[36] T23 VCC33 V23 A_FRAME#
P24 VSS T24 CMODE V24 A_IRDY#
Table 33. Signal List, sorted by Ball Name (Sheet 3 of 4)
41110 Bridge — Datasheet
44
Ball Signal Name Ball Signal Name Ball Signal Name
W1 NC AA1 VCC33 AC1 NC
W2 VCC33 AA2 NC AC2 NC
W3 NC AA3 NC AC3 VCC15
W4 NC AA4 VSS AC4 NC
W5 VSS AA5 NC AC5 NC
W6 NC AA6 NC AC6 VCC33
W7 NC AA7 VSS AC7 NC
W8 VSS AA8 NC AC8 NC
W9 NC AA9 NC AC9 VSS
W10 NC AA10 VSS AC10 NC
W11 VCC33 AA11 NC AC11 NC
W12 NC AA12 NC AC12 VSS
W13 A_REQ5# AA13 VSS AC13 A_AD[15]
W14 VSS AA14 A_GNT4# AC14 A_CBE1#
W15 A_AD[30] AA15 A_AD[31] AC15 VSS
W16 A_CLKO[1] AA16 VSS AC16 A_AD[11]
W17 VSS AA17 A_RST# AC17 A_AD[9]
W18 A_AD[25] AA18 A_AD[26] AC18 VSS
W19 A_GNT0# AA19 VSS AC19 A_AD[7]
W20 VSS AA20 A_CBE3# AC20 A_AD[5]
W21 A_REQ0# AA21 A_AD[21] AC21 VSS
W22 A_REQ1# AA22 VSS AC22 A_AD[2]
W23 VSS AA23 A_AD[18] AC23 A_AD[0]
W24 A_AD[16] AA24 A_CBE2# AC24 A_REQ64#
Y1 NC AB1 NC AD1 VSS
Y2 NC AB2 VSS AD2 NC
Y3 VSS AB3 NC AD3 NC
Y4 NC AB4 NC AD4 VSS
Y5 NC AB5 VSS AD5 NC
Y6 VCC15 AB6 NC AD6 NC
Y7 NC AB7 NC AD7 VSS
Y8 NC AB8 VCC33 AD8 NC
Y9 VCC33 AB9 NC AD9 NC
Y10 NC AB10 NC AD10 VSS
Y11 NC AB11 VSS AD11 NC
Y12 VSS AB12 NC AD12
Y13 A_GNT3# AB13 A_PAR AD13
Y14 A_GNT2# AB14 VCC33 AD14 A_AD[14]
Y15 VCC33 AB15 A_AD[12] AD15 A_AD[13]
Y16 A_AD[28] AB16 A_AD[29] AD16 VSS
Y17 A_AD[27] AB17 VSS AD17 A_AD[10]
Y18 VSS AB18 A_AD[8] AD18 A_CBE0#
Y19 A_AD[23] AB19 A_AD[24] AD19 VCC33
Y20 A_AD[22] AB20 VCC15 AD20 A_AD[6]
Y21 VCC33 AB21 A_AD[3] AD21 A_AD[4]
Y22 A_AD[19] AB22 A_AD[20] AD22 VSS
Y23 A_AD[17] AB23 VSS AD23 A_AD[1]
Y24 VCC33 AB24 A_ACK64# AD24 VSS
Table 33. Signal List, sorted by Ball Name (Sheet 4 of 4)
Datasheet — 41110 Bridge
45
4.3 Signal List, sorted by Signal Name
Table 34. Signal List, sorted by Signal Name (Sheet 1 of 4)
Ball Signal Name Ball Signal Name Ball Signal Name
V20 A_133EN H22 A_AD[49] E22 A_NC8
AB24 A_ACK64# R20 A_AD[50] F21 A_NC9
AC23 A_AD[0] R18 A_AD[51] E21 A_NC10
AD23 A_AD[1] P19 A_AD[52] R21 A_LOCK#
AC22 A_AD[2] P17 A_AD[53] T18 A_M66EN
AB21 A_AD[3] N19 A_AD[54] AB13 A_PAR
AD21 A_AD[4] N17 A_AD[55] J20 A_PAR64
AC20 A_AD[5] M18 A_AD[56] E17 A_PCIXCAP
AD20 A_AD[6] M17 A_AD[57] P20 A_PERR#
AC19 A_AD[7] L19 A_AD[58] V21 A_PME#
AB18 A_AD[8] L17 A_AD[59] W21 A_REQ0#
AC17 A_AD[9] K18 A_AD[60] W22 A_REQ1#
AD17 A_AD[10] K17 A_AD[61] V18 A_REQ2#
AC16 A_AD[11] K19 A_AD[62] N18 A_REQ3#
AB15 A_AD[12] J17 A_AD[63] L22 A_REQ4#
AD15 A_AD[13] AD18 A_CBE0# W13 A_REQ5#
AD14 A_AD[14] AC14 A_CBE1# AC24 A_REQ64#
AC13 A_AD[15] AA24 A_CBE2# AA17 A_RST#
W24 A_AD[16] AA20 A_CBE3# T19 A_SERR#
Y23 A_AD[17] H17 A_CBE4# U19 A_STOP#
AA23 A_AD[18] J18 A_CBE5# C18 A_STRAP0
Y22 A_AD[19] H19 A_CBE6# D18 A_STRAP1
AB22 A_AD[20] H20 A_CBE7# B22 A_STRAP2
AA21 A_AD[21] U13 A_CLKIN C19 A_STRAP3
Y20 A_AD[22] V14 A_CLKO[0] A21 A_STRAP4
Y19 A_AD[23] W16 A_CLKO[1] D19 A_STRAP5
AB19 A_AD[24] V17 A_CLKO[2] F19 A_STRAP6
W18 A_AD[25] U17 A_CLKO[3] F22 A_TEST1
AA18 A_AD[26] U14 A_CLKO[4] B23 A_TEST2
Y17 A_AD[27] U16 A_CLKO[5] U22 A_TRDY#
Y16 A_AD[28] V15 A_CLKO[6] B2 B_NC1
AB16 A_AD[29] U20 A_DEVSEL# E4 B_NC2
W15 A_AD[30] V23 A_FRAME# D2 B_NC3
AA15 A_AD[31] W19 A_GNT0# E1 B_NC4
T22 A_AD[32] J24 A_GNT1# G3 B_NC5
T21 A_AD[33] Y14 A_GNT2# D3 B_NC6
R24 A_AD[34] Y13 A_GNT3# B1 B_NC7
R23 A_AD[35] AA14 A_GNT4# G4 B_NC8
P23 A_AD[36] U23 A_GNT5# E3 B_NC9
P22 A_AD[37] V24 A_IRDY# F4 B_NC10
N22 A_AD[38] G24 A_INTA# B8 CFGRETRY
N21 A_AD[39] F24 A_INTB# E18 CFGRST#
M23 A_AD[40] D23 A_INTC# T24 CMODE
M21 A_AD[41] C24 A_INTD# AB1 NC
L23 A_AD[42] B24 A_NC1 AC2 NC
L20 A_AD[43] A23 A_NC2 AD2 NC
K24 A_AD[44] D24 A_NC3 AD3 NC
K22 A_AD[45] F23 A_NC4 AB4 NC
J23 A_AD[46] G21 A_NC5 AC4 NC
J21 A_AD[47] D22 A_NC6
H23 A_AD[48] G22 A_NC7
41110 Bridge — Datasheet
46
Ball Signal Name Ball Signal Name Ball Signal Name
AC5NC K6 NC D6NC5
AD5 NC K7 NC E19 NC6
AD6 NC J6 NC F6 NC7
AB7NC J7 NC F8NC8
AC7 NC H5 NC F7 NC9
AD8 NC H8 NC T4 NC10
AB9 NC AC8 NC G18 NC11
AD9 NC AB12 NC G19 NC12
AB10 NC Y1 NC K21 NC13
AC10 NC AA5 NC M8 NC14
AD11 NC G9 NC M20 NC15
W1 NC H9 NC R6 NC16
Y2 NC G6 NC C6 NC18
AA2 NC G7 NC B6 NC19
AA3 NC W10 NC E16 PE_RCOMP[0]
AB3 NC V9 NC B17 PE_RCOMP[1]
Y4 NC V8 NC E14 PERN[0]
Y5 NC T7 NC A15 PERN[1]
W6 NC V6 NC C13 PERN[2]
AA6 NC U7 NC G12 PERN[3]
W7 NC U8 NC C10 PERN[4]
Y7 NC T3 NC C9 PERN[5]
Y8 NC U4 NC E12 PERN[6]
AA8 NC J5 NC G10 PERN[7]
W9 NC K1 NC E15 PERP[0]
Y10 NC Y11 NC A16 PERP[1]
AA9 NC AA11 NC D13 PERP[2]
R2 NC W12 NC H12 PERP[3]
R3 NC L8 NC C11 PERP[4]
P1 NC U5 NC B9 PERP[5]
P4 NC F2 NC D12 PERP[6]
P5 NC G1 NC F10 PERP[7]
N3 NC F3 NC F17 PERST#
N4 NC C1 NC F13 PETN[0]
M2 NC W3 NC D15 PETN[1]
M3 NC AC11 NC B14 PETN[2]
L1 NC H7 NC H13 PETN[3]
L2 NC U2 NC B11 PETN[4]
K3 NC L4 NC A9 PETN[5]
K4 NC AB6 NC D9 PETN[6]
J2 NC T6 NC F11 PETN[7]
J3 NC T1 NC F14 PETP[0]
H4 NC V5 NC D16 PETP[1]
H1 NC AA12 NC B15 PETP[2]
H2 NC AC1 NC G13 PETP[3]
P7 NC N8 NC B12 PETP[4]
P8 NC V2 NC A10 PETP[5]
N6 NC V3 NC D10 PETP[6]
N7 NC W4 NC E11 PETP[7]
M5 NC F18 NC1 V11 RCOMP
M6 NC A5 NC2 C17 REFCLKN
L5 NC A22 NC3 C16 REFCLKP
L7 NC C4 NC4
Table 34. Signal List, sorted by Signal Name (Sheet 2 of 4)
Datasheet — 41110 Bridge
47
Ball Signal Name Ball Signal Name Ball Signal Name
B19 RESERVED P13 VCC15 F12 VCCPE
U11 RESERVED P15 VCC15 H11 VCCPE
C21 RESERVED1 R10 VCC15 H15 VCCPE
B21 RESERVED2 R12 VCC15 J10 VCCPE
D21 RESERVED3 R14 VCC15 J12 VCCPE
F20 RESERVED4 R16 VCC15 J14 VCCPE
E6 STRAP_V_1 T9 VCC15 A4 VSS
B5 STRAP_V_2 T11 VCC15 A8 VSS
B3 STRAP_V_3 T13 VCC15 A17 VSS
A3 STRAP_V_4 T15 VCC15 A20 VSS
B4 STRAP_V_5 V12 VCC15 A24 VSS
D4 STRAP_V_6 V16 VCC15 B10 VSS
F5 STRAP_V_7 Y6 VCC15 B13 VSS
P2 STRAP_V_8 AB20 VCC15 B16 VSS
C3 STRAP_V_9 AC3 VCC15 C2 VSS
D1 STRAP_V_10 A2 VCC33 C5 VSS
U1 STRAP_V_11 A7 VCC33 C8 VSS
D7 STRAP_V_12 B18 VCC33 C20 VSS
U10 STRAP_V_13 C22 VCC33 C23 VSS
R5 STRAP_V_14 D5 VCC33 D11 VSS
A19 STRAP_V_15 E24 VCC33 D14 VSS
H16 RSTIN# F1 VCC33 D17 VSS
C7 SMBCLK H3 VCC33 E2 VSS
D8 SMBDAT H18 VCC33 E5 VSS
G16 SMBUS[1] H21 VCC33 E8 VSS
B20 SMBUS[2] H24 VCC33 E10 VSS
A18 SMBUS[3] L6 VCC33 E13 VSS
D20 SMBUS[5] M19 VCC33 E20 VSS
B7 TCK R7 VCC33 E23 VSS
E9 TDI T5 VCC33 F15 VSS
A6 TDO T17 VCC33 G2 VSS
E7 TMS T20 VCC33 G5 VSS
F9 TRST# T23 VCC33 G8 VSS
J16 VCC15 U9 VCC33 G11 VSS
K9 VCC15 V4 VCC33 G14 VSS
K11 VCC15 W2 VCC33 G17 VSS
K13 VCC15 W11 VCC33 G20 VSS
K15 VCC15 Y9 VCC33 G23 VSS
L3 VCC15 Y15 VCC33 H6 VSS
L10 VCC15 Y21 VCC33 H10 VSS
L12 VCC15 Y24 VCC33 J1 VSS
L14 VCC15 AA1 VCC33 J4 VSS
L16 VCC15 AB8 VCC33 J9 VSS
M9 VCC15 AB14 VCC33 J11 VSS
M11 VCC15 AC6 VCC33 J13 VSS
M13 VCC15 AD19 VCC33 J15 VSS
M15 VCC15 J8 VCCAPCI1 J19 VSS
M22 VCC15 R8 VCCAPCI2 J22 VSS
N10 VCC15 R17 VCCAPCI3 K2 VSS
N12 VCC15 G15 VCCAPE K5 VSS
N14 VCC15 C14 VCCBGPE K8 VSS
N16 VCC15 A14 VCCPE K10 VSS
P9 VCC15 C12 VCCPE K12 VSS
P11 VCC15 C15 VCCPE K14 VSS
Table 34. Signal List, sorted by Signal Name (Sheet 3 of 4)
41110 Bridge — Datasheet
48
Ball Signal Name Ball Signal Name Ball Signal Name
K16 VSS R15 VSS AB2 VSS
K20 VSS R19 VSS AB5 VSS
K23 VSS R22 VSS AB11 VSS
L9 VSS T2 VSS AB17 VSS
L11 VSS T8 VSS AB23 VSS
L13 VSS T10 VSS AC9 VSS
L15 VSS T12 VSS AC12 VSS
L18 VSS T14 VSS AC15 VSS
L21 VSS T16 VSS AC18 VSS
L24 VSS U3 VSS AC21 VSS
M4 VSS U6 VSS AD1 VSS
M7 VSS U12 VSS AD4 VSS
M10 VSS U15 VSS AD7 VSS
M12 VSS U18 VSS AD10 VSS
M14 VSS U21 VSS AD16 VSS
M16 VSS U24 VSS AD22 VSS
N2 VSS V1 VSS AD24 VSS
N5 VSS V7 VSS F16 VSSAPE
N9 VSS V10 VSS A13 VSSBGPE
N11 VSS V13 VSS A1
N13 VSS V19 VSS A11
N15 VSS V22 VSS A12
N20 VSS W5 VSS M1
N23 VSS W8 VSS M24
P3 VSS W14 VSS N1
P6 VSS W17 VSS N24
P10 VSS W20 VSS AD12
P12 VSS W23 VSS AD13
P14 VSS Y3 VSS
P16 VSS Y12 VSS
P18 VSS Y18 VSS
P21 VSS AA4 VSS
P24 VSS AA7 VSS
R1 VSS AA10 VSS
R4 VSS AA13 VSS
R9 VSS AA16 VSS
R11 VSS AA19 VSS
R13 VSS AA22 VSS
Table 34. Signal List, sorted by Signal Name (Sheet 4 of 4)
