Features * * * * * * * * * * * * * Supply voltage up to 40 V RDSon typ. 0.5 @ 25C, max. 1 @ 150C Up to 1.5 A output current Three half-bridge outputs formed by three high-side and three low-side drivers Capable to switch all kinds of loads such as DC motors, bulbs, resistors, capacitors and inductors No crossover current Very low quiescent current Is < 10 A in stand-by mode vs. total temperature range Outputs short-circuit protected Overtemperature protection for each switch and overtemperature prewarning Undervoltage protection Various diagnosis functions such as shorted output, open load, overtemperature and power-supply fail Serial data interface, daisy chain capable, up to 2 MHz clock frequency SO14 power package Description T6818 / T6828 are fully protected driver interfaces designed in 0.8-m BCDMOS technology. It is used to control up to 3 different loads by a microcontroller i n a u t o m o t i v e a n d i n d u s t r i a l applications. Each of the 3 high-side and 3 low-side drivers is capable to drive currents up to 1.5 A. The drivers are internally connected to form 3 half-bridges and can be controlled separately from a standard serial data interface. Therefore all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. The IC design especially supports the applications of H-bridges to drive DC motors. Triple Half Bridge DMOS Output Driver with Serial Input Control T6818 T6828 Protection is guaranteed in terms of s h o r t - c i r c u i t c o n d i t i o n s , o v e r temperature and undervoltage. Various diagnosis functions and a very low quiescent current in stand-by-mode opens a wide range of applications. Automotive qualification referring to conducted interferences, EMC protection and 2 kV ESD protection gives added value and enhanced quality for demanding up-market applications. Ordering Information Extended Type Number Package Remarks T6818-TBS SO14 Power package, tubed T6818-TBQ SO14 Power package with head slug, taped and reeled T6828-TBS SO14 Power package, tubed T6828-TBQ SO14 Power package with head slug, taped and reeled Rev. A1, 07-Nov-01 Preliminary Information 1 (16) Preliminary Information Block Diagram Figure 1. n. u. n. u. O C S n. u. n. u. n. u. n. u. n. u. n. u. H S 3 Input register Output register DI 5 P S F O P L S C D n. u. n. u. L S 3 H S 2 L S 2 H S 1 L S 1 S R R 3 Serial interface n. u. n. u. n. u. n. u. H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 VS Charge pump T P CLK 6 CS UV protection 4 Fault detect INH Fault detect Fault detect 11 10 Control logic DO 9 VCC Power-on reset 1 7 Fault detect Fault detect 2 OUT3 2 (16) Fault detect 12 OUT2 Thermal protection 8 14 GND GND GND GND 13 OUT1 T6818 / T6828 Rev. A1, 07-Nov-01 T6818 / T6828 Pin Configuration Figure 2. GND OUT3 VS CS DI CLK GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 GND OUT1 OUT2 VCC INH DO GND Pin Description Pin Symbol Function 1 GND T6818: Ground; reference potential; internal connection to Pin 7, 8 and 14; cooling tab T6828: Additional connection to heat slug 2 OUT3 Half bridge-output 3; formed by internally connected Power-MOS high-side switch 3 and low-side switch 3 with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and open load 3 VS Power supply for output stages OUT1, OUT2 and OUT3, internal supply 4 CS Chip select input; 5-V CMOS logic level input with internal pull up; low = serial communication is enabled, high = disabled 5 DI Serial data input; 5-V CMOS logic level input with internal pull down; receives serial data from the control device; DI expects a 16-bit control word with LSB being transferred first 6 CLK Serial clock input; 5-V CMOS logic level input with internal pull down; controls serial data input interface and internal shift register (fmax = 2 MHz) 7 GND Ground; see Pin 1 8 GND Ground; see Pin 1 9 DO Serial data output; 5-V CMOS logic level tristate output for output (status) register data; sends 16-bit status information to the C (LSB is transferred first); output will remain tristated, unless device is selected by CS = low, therefore, several ICs can operate on one data output line only. 10 INH Inhibit input; 5-V logic input with internal pull down; low = stand-by, high = normal operating 11 VCC Logic supply voltage (5V) 12 OUT2 Half bridge-output 2; see Pin 2 13 OUT1 Half bridge-output 1; see Pin 2 14 GND Ground; see Pin 1 Preliminary Information Rev. A1, 07-Nov-01 3 (16) Preliminary Information Functional Description Serial Interface Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, Pin DO is in tristate condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Figure 3. Data transfer CS DI SRR LS1 HS1 LS2 HS2 LS3 HS3 n. u. n. u. n. u. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S1L S1H S2L S2H S3L S3H n. u. n. u. n. u. n. u. n. u. n. u. SCD OPL PSF n. u. n. u. n. u. OCS n. u. n. u. CLK DO TP Input Data Protocol Bit 4 (16) Input Register Function 0 SRR Status register reset (high = reset; the bits PSF, OPL and SCD in the output data register are set to low) 1 LS1 Controls output LS1 (high = switch output LS1 on) 2 HS1 Controls output HS1 (high = switch output HS1 on) 3 LS2 See LS1 4 HS2 See HS1 5 LS3 See LS1 6 HS3 See HS1 7 n. u. Not used 8 n. u. Not used 9 n. u. Not used 10 n. u. Not used 11 n. u. Not used 12 n. u. Not used 13 OCS Overcurrent shutdown (high = overcurrent shutdown is active) 14 n. u. Not used 15 n. u. Not used T6818 / T6828 Rev. A1, 07-Nov-01 T6818 / T6828 Output Data Protocol Output (Status) Register Bit Function 0 TP Temperature prewarning: high = warning 1 Status LS1 high = output is on, low = output is off; not affected by SRR 2 Status HS1 high = output is on, low = output is off; not affected by SRR 3 Status LS2 Description see LS1 4 Status HS2 Description see HS1 5 Status LS3 Description see LS1 6 Status HS3 Description see HS1 7 n. u. Not used 8 n. u. Not used 9 n. u. Not used 10 n. u. Not used 11 n. u. Not used 12 n. u. Not used 13 SCD Short circuit detected: set high, when at least one high-side or low-side switch is switched off by a short circuit condition. Bits 1 to 6 can be used to detect the shorted switch. 14 OPL Open load detected: set high, when at least one active high sideor low side-switch sinks/sources a current below the open load threshold current. 15 PSF Power-supply fail: undervoltage at Pin VS detected After power-on reset, the input register has the following status Bit 15 Bit 14 Bit 13 (OCS) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 (HS3) Bit 5 (LS3) Bit 4 (HS2) Bit 3 (LS2) Bit 2 (HS1) Bit 1 (LS1) Bit 0 (SRR) x x H x x x x x x L L L L L L L Power-Supply Fail In case of undervoltage at Pin VS the Power-Supply Fail bit (PSF) in the output register is set and all outputs are disabled. An undervoltage condition is only detected if it occurs over the undervoltage detection delay time tdUV. After the undervoltage occurred the outputs are enabled immediately. The PSF bit keeps high until it is reset by the SRR bit in the input register. Open-Load Detection If the current through a high side or low side switch in ON-state does not reach the open load detection threshold, the open load detection bit (OPL) in the output register is set. The OPL bit keeps high until it is reset by the SRR bit in the input register. An open load condition is only detected if it occurs over the open load detection delay time tdSd. Overtemperature Protection If the junction temperature at one or more switches exceeds the thermal prewarning threshold TjPW set, the temperature prewarning bit (TP) in the output register is set. When Preliminary Information Rev. A1, 07-Nov-01 5 (16) Preliminary Information temperature falls below the thermal prewarning threshold TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word: with CS = high to low the state of TP appears at Pin DO. After the C has read this information CS is set high and the data transfer is interrupted without affecting the state of input and output registers. If the junction temperature at one or more switches exceeds the thermal shutdown threshold Tj switch off, all outputs are disabled and the corresponding bits in the output register are set to low. The outputs can be enabled again when the temperature falls below the thermal shutdown threshold Tjswitchon and writing a high to the SRR bit in the input register. Thermal prewarning and shutdown threshold have hysteresis. Short-Circuit Protection The output currents are limited by a current regulator. If the overcurrent shutdown bit (OCS) in the input register is set, the concerned output is switched off after a short delay time (tdSd ) when the current exceeds the overcurrent limitation and shutdown threshold. In this case the short-circuit detection bit (SCD) is set and the corresponding status bit in the output register is set to low. For OCS = low the overcurrent shutdown is inactive. In this case the SCD bit is set also if the current exceeds the overcurrent limitation and shutdown threshold, but the outputs are not affected. By writing a high to the SRR bit in the input register the SCD bit is reset and the disabled outputs are enabled. Inhibit To inhibit the T6818 / T6828, switch Pin 10 (INH) to 0 V. In this case all output switches are turned off and the data in the output register are deleted. The current consumption is reduced to less than 10 A out of VS and less than 20 A out of VCC. The outputs are switched to tristate. The output switches can be activated again by switching Pin 10 (INH) to 5 V which initiates an internal power-on reset. 6 (16) T6818 / T6828 Rev. A1, 07-Nov-01 T6818 / T6828 Absolute Maximum Ratings All values refer to GND pins Parameter Supply voltage Pin 3 Symbol Value Unit VVS -0.3 to 40 V Supply voltage t<0.5s; IS>-2A Pin 3 VVS -1 V Logic supply voltage Pin 11 VVCC -0.3 to 7 V Logic input voltage Pins 4 to 6, 10 VCS,VDI, VCLK, VINH -0.3 to VVCC+0.3 V Logic output voltage Pin 9 Input current Pins 4 to 6, 10 Output current Pin 9 Output current Reverse conducting current (tpulse = 150 s) VDO -0.3 to VVCC+0.3 V ICS,IDI, ICLK, IINH -10 to +10 mA IDO -10 to +10 mA Pins 2, 12 and 13 IOut3, IOut2, IOut1 Internal limited, see output specification Pins 2, 12 and 13 towards Pin 3 IOut3, IOut2, IOut1 17 A Junction-temperature range TJ -40 to 150 C Storage-temperature range TSTG -55 to 150 C Thermal Resistance Parameter Test Conditions Symbol Value Unit RthJP 30 K/W RthJA 65 K/W RthJP 5 K/W RthJA 30 K/W T6818 Measured to GND Pins 1, 7, 8, 14 Junction - pin Junction - ambient T6828 Measured to heat slug, GND Pins 1, 7, 8, 14 Junction - pin Junction - ambient Operating Range Parameter Symbol Value 1) Unit Supply voltage VVS VUV to 40 V Logic supply voltage VVCC 4.75 to 5.25 V VCS,VDI, VCLK, VINH -0.3 to VVCC V fCLK 2 MHz Tj -40 to 150 C Logic input voltage Serial interface clock frequency Junction-temperature range Preliminary Information Rev. A1, 07-Nov-01 7 (16) Preliminary Information Noise and Surge Immunity Parameter Test Conditions Conducted interferences ISO 7637-1 Interference suppression VDE 0879 Part 3 ESD (Human Body Model) ESD S 5.1 ESD (Machine Model) JEDEC A115A Value Level 4 1) Level 6 2 kV 200 V Electrical Characteristics 7.5 V < VVS < 40 V; 4.5 V < VVCC < 5.5 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. No. 1 Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Current Consumption 1.1 Quiescent current (VS ) VVS < 16 V, INH = low 3 IVS 1 5 A A 1.2 Quiescent current (VCC) 4.75 V < VVCC < 5.25 V, INH = low 11 IVCC 15 25 A A 1.3 Supply current (VS) VVS <16 V normal operating, all outputs off 3 IVS 4 6 mA A 1.4 Supply current (VCC) 4.75 V < VVCC < 5.25 V, normal operating 11 IVCC 350 500 A A 11 VVCC 3.4 3.9 4.4 V A tdPor 30 95 160 s A 5.5 7.0 V A V B 40 s A 2 Undervoltage Detection, Power-On Reset 2.1 Power-on reset threshold 2.2 Powe-on reset delay time After switching on VCC 2.3 Undervoltagedetection threshold VCC = 5 V 3 VUv 2.4 Undervoltagedetection hysteresis VCC = 5 V 3 VUv 2.5 Undervoltagedetection delay time 3 0.6 tdUV 10 Thermal Prewarning and Shutdown 3.1 Thermal prewarning TjPW set 120 145 170 C B 3.2 Thermal prewarning TjPW reset 105 130 155 C B 3.3 Thermal prewarning hysteresis TjPW C B 3.4 Thermal shutdown Tj switch off 150 175 200 C B 3.5 Thermal shutdown Tj switch on 135 160 185 C B 3.6 Thermal shutdown hysteresis Tj switch off C B 15 15 *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 8 (16) T6818 / T6828 Rev. A1, 07-Nov-01 T6818 / T6828 Electrical Characteristics 7.5 V < VVS < 40 V; 4.5 V < VVCC < 5.5 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 3.7 Ratio thermal shutdown / thermal prewarning Tj switch off / TjPW set 1.05 1.2 B 3.8 Ratio thermal shutdown / thermal prewarning Tj switch on / TjPW reset 1.05 1.2 B 4 4.1 Output Specification (OUT1-OUT3) On resistance IOut = 1.5 A 2, 12, 13 RDS On L 1 B On resistance IOut = -1.5 A 2, 12, 13 RDS On H 1 B 4.3 Source output leakage current VOut1-3 = 0 V, output stages off 2, 12, 13 IOut1-3 A A 4.4 Sink output leakage current VOut1-3 = VVS, output stages off 2, 12, 13 IOut1-3 300 A A 4.5 High-side switch reverse diode forward voltage IOut = 1.5 A 2, 12, 13 VOut1-3 -VVS 1.3 V A 4.6 Low-side switch reverse diode forward voltage IOut = -1.5 A 2, 12, 13 VOut1-3 -1.3 V A 4.7 Source overcurrent limitation and shutdown threshold 2, 12, 13 IOut1-3 -2.5 -2 -1.5 A A 4.8 Sink overcurrent limitation and shutdown threshold 2, 12, 13 IOut1-3 1.5 2 2.5 A A 4.9 Overcurrent shutdown delay time tdSd 10 40 s A 4.10 Source open-load detection threshold 2, 12, 13 IOut1-3 -45 -30 -15 mA A 4.11 Sink open-load detection threshold 2, 12, 13 IOut1-3 15 30 45 mA A 4.12 Open-load detection delay time tdSd 200 600 s A 4.13 Source output switch on delay 1) VVS = 13 V, RLoad = 30 tdon 5 15 s A 4.14 Sink output switch on delay 1) VVS = 13 V, RLoad = 30 tdon 15 25 s A 4.15 Source output switch off delay 1) VVS = 13 V, RLoad = 30 tdoff 5 15 s A 4.16 Sink output switch off delay 1) VVS = 13 V, RLoad = 30 tdoff 1 2 s A 4.2 -15 *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Preliminary Information Rev. A1, 07-Nov-01 9 (16) Preliminary Information Electrical Characteristics 7.5 V < VVS < 40 V; 4.5 V < VVCC < 5.5 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. No. Parameters 4.17 Dead time between corresponding highand low-side switches 5 Test Conditions Pin VVS = 13 V, RLoad = 30 Symbol Min. tdon -tdoff Typ. Max. Unit Type* 1 s B 0.3 x VVCC V A V A Logic Inputs DI, CLK, CS, INH 5.1 Input voltage lowlevel threshold 4-6, 10 VIL 5.2 Input voltage highlevel threshold 4-6, 10 VIH 5.3 Hysteresis of input voltage 4-6, 10 VI 50 500 mV B 5.4 Pull-down current Pin DI, CLK, INH VDI, VCLK, VINH = VCC 5, 6, 10 IPD 10 60 A A 5.5 Pull-up current Pin CS VCS = 0 V 4 IPU -50 -10 A A V A 10 A A 6 0.7rVVC C Serial Interface - Logic Output DO 6.2 Output-voltage high level IOL = -2 mA 9 VDOH VVCC0.7 V 6.3 Leakage current (tristate) VCS = VCC 0V < VDO < VVCC 9 IDO -10 7 Inhibit Input - Timing 7.1 Standby setup time tIINHsethl 100 s A 7.2 Standby setup time tIINHsetlh 100 s A *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 10 (16) 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level. Device not in stand-by for t >1ms T6818 / T6828 Rev. A1, 07-Nov-01 T6818 / T6828 Serial Interface - Timing Parameters Test Conditions Timing Chart No. Symbol Min. Typ. Max. Unit DO enable after CS falling edge CDO = 100 pF 1 tENDO 200 ns DO disable after CS rising edge CDO = 100 pF 2 tDISDO 200 ns DO fall time CDO = 100 pF - tDOf 100 ns DO rise time CDO = 100 pF - tDOr 100 ns DO valid time CDO = 100 pF 10 tDOVal 200 ns CS setup time 4 tCSSethl 225 ns CS setup time 8 tCSSetlh 225 ns CS high time 9 tCSh 500 ns CLK high time 5 tCLKh 225 ns CLK low time 6 tCLKl 225 ns CLK period time - tCLKp 500 ns CLK setup time 7 tCLKSethl 225 ns CLK setup time 3 tCLKSetlh 225 ns DI setup time 11 tDIset 40 ns DI hold time 12 tDIHold 40 ns Preliminary Information Rev. A1, 07-Nov-01 11 (16) Preliminary Information Figure 4. Serial interface timing with chart numbers 1 2 CS DO 9 CS 4 7 CLK 5 3 6 8 DI 11 CLK 10 12 DO Inputs DI, CLK, CS: High level = 0.7 x VCC, low level = 0.3 x VCC Output DO: High level = 0.8 x VCC, low level = 0.2 x VCC 12 (16) T6818 / T6828 Rev. A1, 07-Nov-01 T6818 / T6828 Application Circuit Figure 5. Vcc U5021M Enable Trigger Vs n. u. n. u. O C S n. u. n. u. n. u. n. u. n. u. n. u. H S 3 Input register Output register CLK 5 P S F O P L S C D n. u. n. u. H S 2 L S 2 H S 1 L S 1 BYT41D S R R 3 Serial interface n. u. n. u. n. u. n. u. H S 3 L S 3 H S 2 L S 2 H S 1 13 V L T S P 1 6 UV protection 4 Fault detect INH V Batt Charge pump CS C VS Fault detect Fault detect Vcc 11 10 Control logic DO 9 Vcc VCC 5V Power-on reset 1 GND + DI L S 3 + Reset Watchdog 7 GND Fault detect Fault detect Fault detect Thermal protection 2 12 OUT3 8 14 GND GND 13 OUT1 OUT2 Vcc M Application Notes M It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possible to the power supply and GND pins. Recommended value for capacitors at VS: Electrolytic capacitor C > 22 F in parallel with a ceramic capacitor C = 100 nF. Value for electrolytic capacitor depends on external loads, conducted interferences and reverse conducting current IOutzx (see Absolute Maximum Ratings). Recommended value for capacitors at VCC: Electrolytic capacitor C > 10 F in parallel with a ceramic capacitor C = 100 nF. To reduce thermal resistance it is recommended to place cooling areas on the PCB as close as possible to GND pins. Preliminary Information Rev. A1, 07-Nov-01 13 (16) Preliminary Information Package Information Package SO14 5.2 4.8 Dimensions in mm 8.75 3.7 1.4 0.25 0.10 0.4 1.27 6.15 5.85 7.62 14 0.2 3.8 8 technical drawings according to DIN specifications 1 14 (16) 7 T6818 / T6828 Rev. A1, 07-Nov-01 T6818 / T6828 Ozone Depleting Substances Policy Statement It is the policy of Atmel Germany GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. Preliminary Information Rev. A1, 07-Nov-01 15 (16) A tmel Wireless & Microcontrollers Sales Offices France 3, Avenue du Centre 78054 St.-Quentin-en-Yvelines Cedex Tel: +33 1 30 60 70 00 Fax: +33 1 30 60 71 11 Germany Erfurter Strasse 31 85386 Eching Tel: +49 89 319 70 0 Fax: +49 89 319 46 21 Kruppstrasse 6 45128 Essen Tel: +49 201 247 30 0 Fax: +49 201 247 30 47 Theresienstrasse 2 74072 Heilbronn Tel: +49 7131 67 36 36 Fax: +49 7131 67 31 63 Italy Via Grosio, 10/8 20151 Milano Tel: +39 02 38 03 71 Fax: +39 02 38 03 72 34 Sweden Kavallerivaegen 24, Rissne 17402 Sundbyberg Tel: +46 8 587 48 800 Fax: +46 8 587 48 850 United Kingdom Easthampstead Road Bracknell Berkshire RG12 1LX Tel: +44 1344 707 300 Fax: +44 1344 427 371 USA Western 2325 Orchard Parkway San Jose, California 95131 Tel: +1 408 441 0311 Fax: +1 408 436 4200 USA Eastern 1465 Route 31, Fifth floor Annandale New Jersey 08801 Tel: +1 908 848 5208 Fax: +1 908 848 5232 Spain Principe de Vergara, 112 28002 Madrid Tel: +34 91 564 51 81 Fax: +34 91 562 75 14 Hong Kong Room #1219, Chinachem Golden Plaza 77 Mody Road, Tsimhatsui East East Kowloon, Hong Kong Tel: +852 23 789 789 Fax: +852 23 755 733 Korea 25-4, Yoido-Dong, Suite 605, Singsong Bldg. Youngdeungpo-Ku 150-010 Seoul Tel: +822 785 1136 Fax: +822 785 1137 Rep. of Singapore Keppel Building #03-00 25 Tampines Street 92, Singapore 528877 Tel: +65 260 8223 Fax: +65 787 9819 Taiwan, R.O.C. 8F-2, 266 Sec.1 Wen Hwa 2 Rd. Lin Kou Hsiang, 244 Taipei Hsien Tel: +886 2 2609 5581 Fax: +886 2 2600 2735 Japan Tonetsushinkawa Bldg. 1-24-8 Shinkawa Chuo Ku Tokyo 104-0033 Tel: +81 3 3523 3551 Fax: +81 3 3523 7581 Web Site http://www.atmel-wm.com (c) Atmel Germany GmbH 2001. Atmel Germany GmbH makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel Germany GmbH's Terms and Conditions. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel Germany GmbH are granted by the Company in connection with the sale of AtmelGermany GmbH products, expressly or by implication. Atmel Germany GmbH's products are not authorized for use as critical components in life support devices or systems. Data sheets can also be retrieved fron the Internet: http://www.atmel-wm.com Rev. A1, 07-Nov-01