1 (16)
Preliminary Information
Features
•Supply voltage up to 40 V
•RDSon typ. 0.5 Ω @ 25°C, max. 1 Ω @ 150°C
•Up to 1.5 A output current
•Three half-bridge outputs formed by three high-side and three low-side drivers
•Capable to switch all kinds of loads such as DC motors, bulbs, resistors, capacitors
and inductors
•No crossover current
•Very low quiescent current Is < 10 µA in stand-by mode vs. total temperature range
•Outputs short-circuit protected
•Overtemperature protection for each switch and overtemperature prewarning
•Undervoltage protection
•Various diagnosis functions such as shorted output, open load, overtemperature and
power-supply fail
•Serial data interface, daisy chain capable, up to 2 MHz clock frequency
•SO14 power packag e
Description
T6818 / T682 8 are fully protected dr iver interfaces designed in 0.8-µm BCDMOS
technology. It is used to control up to 3 different loads by a microcontroller in auto-
motive and industrial applications.
Each of the 3 high-side and 3 low-si de dr i vers is capable to drive currents up to 1. 5 A .
The dri vers are i nte rnally con nec te d to for m 3 h alf -b ridges and c an be c ontrol le d s ep-
arately from a standar d serial da ta interface. Therefore all k inds of load s such as
bulbs, resisto rs, capac i tor s and ind uc tor s can be combined . The IC des ign especial ly
supports the applications of H-bridges to drive DC motors.
Protec tion is g uarante ed in terms o f short-circuit conditions, overtemp erature
and undervoltage. Various diagnosis functions and a ver y low quiescent current in
stand -by-mode o pens a wid e range of applica tions. Automo tive qualific ation referring
to conducted interferences, EMC protection and 2 kV ESD protection gives added
value and enhanced quality for demanding up-market applications .
Ordering Information
Extended Type Numbe r Package Remarks
T6818-TBS SO14 Power package, tubed
T6818-TBQ SO14 Power package with head slug, taped and
reeled
T6828-TBS SO14 Power package, tubed
T6828-TBQ SO14 Power package with head slug, taped and
reeled
Triple Half
Bridg e DMOS
Output Driver
with Serial Input
Control
T6818
T6828
Rev. A1, 07-Nov-01
2 (16)
Preliminary Information
T6818 /
T6828
Rev. A1, 07-Nov-01
Block Diag ram
Figure 1.
DI
CLK
INH
DO
CS UV
protection
Serial interface
Input register
Output register
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
O
C
Sn.n. n. n.n.n.
P
S
F
O
P
L
S
C
D
n.
u. H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
T
P
OUT3
VS
VCC
Thermal
protection
Control
logic Power-on
reset
Charge
pump
OUT2 OUT1
n.n.
u.
GND
n.
u. n.
u. n.
u. n.
u. n.
u.
u. u. u. u. u. u. u. 3
11
1
7
8
14
21213
5
6
4
10
9
GND
GND
GND
Fault
detect
Fault
detect
Fault
detect
Fault
detect Fault
detect Fault
detect
3 (16)
Preliminary Information
T6818 / T6828
Rev. A1, 07-Nov-01
Pin Configuration
Figure 2.
GND
OUT3
VS
CS
DI
CLK
GND
GND
OUT1
OUT2
VCC
INH
DO
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Pin Description
Pin Symbol Function
1GND T6818: Ground; reference potential; internal connection to Pin 7, 8 and 14; cooling tab
T6828: Additional connection to heat slug
2OUT3 Half bridge-output 3; formed by internally connected Power-MOS high-side switch 3 and low-side switch
3 with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short
and open l oad
3VS Power supply for output stages OUT1, OUT2 and OUT3, internal supply
4CS Chip select input; 5-V CMOS logic level input with internal pull up;
low = serial communication is enabled, high = disabled
5DI Serial data inpu t; 5-V CMOS log ic le vel input with int ernal pull do wn; receives serial data from the control
device; DI expects a 16-bit control word with LSB being transferred first
6CLK Serial clock input; 5-V CMOS logic level input with internal pull down;
controls serial data input interface and internal shift register (fmax = 2 MHz)
7GND Ground; see Pin 1
8GND Ground; see Pin 1
9DO Serial data output; 5-V CMOS logic level tristate output for output (status) register data; sends 16-bit
status information to the µC (LSB is transferred first); output will remain tristated, unless device is
selected by CS = low, therefore, several ICs can operate on one data output line only.
10 INH Inhibit input; 5-V logic input with internal pull down; low = stand-by,
high = normal operating
11 VCC Logic supply voltage (5V)
12 OUT2 Half bridge-output 2; see Pin 2
13 OUT1 Half bridge-output 1; see Pin 2
14 GND Ground; see Pin 1
4 (16)
Preliminary Information
T6818 /
T6828
Rev. A1, 07-Nov-01
Functional Description
Serial Interfac e Data transfer starts with the falling edge of the CS signal. Data must appear at DI syn-
chroniz ed to CLK and are accept ed on the falling edg e of the CLK signal. LSB (bit 0,
SRR) ha s to be transferr ed first. Executi on of ne w input data is en abled on t he risin g
edge of the CS signal . When CS is high, Pin DO is in tristate condi tion. This output is
enabled on the falling edge of CS. Output data will change their state with the rising
edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is
transferred first.
Figure 3. Data transfer
Input Data Protocol
Bit Input Register Function
0SRR
Status regis ter rese t (high = res et; the bit s PSF, OPL an d SCD in
the output data register are set to low)
1LS1 Controls output LS1 (high = switch output LS1 on)
2HS1 Controls outpu t HS1 (high = switch out put HS1 on)
3LS2 See LS1
4HS2 See HS1
5LS3 See LS1
6HS3 See HS1
7n. u. Not used
8n. u. Not used
9n. u. Not used
10 n. u. Not used
11 n. u. Not used
12 n. u. Not used
13 OCS Overcurrent shutdown (high = overcurrent shutdown is active)
14 n. u. Not used
15 n. u. Not used
SRR LS1 HS1 LS2 HS2 LS3 HS3 n. u. n. u. n. u. n. u. n. u. n. u. OCS n. u. n. u.
CS
DI
CLK
DO TP S1LS1HS2LS2HS3LS3Hn. u.n. u. n. u. n. u. n. u. n. u. SCD OPL PSF
0123456789101112131415
5 (16)
Preliminary Information
T6818 / T6828
Rev. A1, 07-Nov-01
Output Data Protoc ol
After power-on reset, the input register has the following status
Power-Supply Fail In case of unde rvo ltag e a t P in VS th e P owe r-S upply F ail b it (PSF ) in the outp ut reg is ter
is set an d all outputs are disabled. An undervoltag e condition is only detecte d if it
occur s ov er th e u nde rvol tag e d etec ti on de lay t ime t dUV. After the un derv olt age oc c urre d
the outputs are enabled immediately. The PSF bit keeps high until it is reset by the SRR
bit in the input register.
Open-Load Detection If the current through a high side or low side switch in ON-state does not reach the open
load detection threshold, the open load detection bit (OPL) in the output register is set.
The OPL bit keeps high until it is reset by the SRR bit in the input register. An open load
condition is only detected if it occurs over the open load detection delay time tdSd.
Overtemperature
Protection If the junction temperature at one or more switches exceeds the thermal prewarning
threshold TjPW set, the temperature prewarning bit (TP) in the output register is set. When
Bit Output (Status)
Register Function
0 TP Temperature prewarning: high = warni n g
1Status LS1 high = output is on, low = output is off; not affected by SRR
2Status HS1 high = output is on, low = output is off; not affected by SRR
3Status LS2 Description see LS1
4Status HS2 Description see HS1
5Status LS3 Description see LS1
6Status HS3 Description see HS1
7n. u. Not used
8n. u. Not used
9n. u. Not used
10 n. u. Not used
11 n. u. Not used
12 n. u. Not used
13 SCD Short circuit detected: set high, when at least one high-side or
low -side switch is switched of f b y a sho rt circuit conditi on. Bits 1
to 6 can be used to detect the shorted switch.
14 OPL Open lo ad dete cted: s et hig h, when a t leas t one ac tiv e h igh side -
or low side-switch sinks/sources a current below the open load
threshold current.
15 PSF Power-supply fail: undervoltage at Pin VS detected
Bit 15 Bit 14 Bit 13
(OCS) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6
(HS3) Bit 5
(LS3) Bit 4
(HS2) Bit 3
(LS2) Bit 2
(HS1) Bit 1
(LS1) Bit 0
(SRR)
xxHxxxxxxLLLLLLL
6 (16)
Preliminary Information
T6818 /
T6828
Rev. A1, 07-Nov-01
temperature falls below the thermal prewarning threshold TjPW rese t, the bit TP is reset.
The TP bit can be re ad wi thou t trans fer rin g a co mpl ete 16-bi t data w ord: wit h CS = hig h
to low the state of TP appears at Pin DO. After the µC has read this information CS is
set high and the data tran sfer is in terrup ted withou t affecti ng the state of input and out-
put registers.
If the junctio n temperat ure at o ne or mor e switch es exceed s the ther mal shutd own
threshold Tj switch off, all outputs are disabled and the corresponding bits in the output reg-
ister are set to low. The outputs can be enabled again when the temperature falls below
the thermal shutdown threshol d Tjswitchon and writing a high to the SRR bit in the i nput
register. Thermal prewarning and shutdown threshold have hysteresis.
Short-Circuit Pr otection The output cu rrents are limited by a curr ent regulator. If the overcu rrent shutdown bit
(OCS) in the input register is set, the concerned output is switched off after a short
delay time (tdSd) when the current exceeds the overcurrent l imitation a nd shutdown
threshold. In this case the short-circuit detection bit (SCD) is set and the corresponding
status bi t in th e outp ut regi st er is set to low. For O CS = low the ov er cu rren t sh utdo wn is
inactive. In this case the SCD bit is set also if the current exceeds the overcurrent limita-
tion and shutdown threshold, but the outputs are not affected. By wr iting a high to the
SRR bit in the input register the SCD bit is reset and the disabled outputs are enabled.
Inhibit To inhibit the T6818 / T6828, switch Pin 10 (INH) to 0 V.
In this case all output switches are turned off and the data in the output register are
deleted. The current consumption is reduced to less than 10 µA out of VS and less than
20 µA out of VCC. The outputs are switched to tristate. The output switches can be acti-
vated again by switching Pin 10 (INH) to 5 V which initiates an internal power-on reset.
7 (16)
Preliminary Information
T6818 / T6828
Rev. A1, 07-Nov-01
Absolute Maxim u m Ratings
All values refer to GND pins
Parameter Symbol Value Unit
Supply voltage Pin 3 VVS -0.3 to 40 V
Supply voltage t<0.5s; IS>-2A Pin 3 VVS -1 V
Logic supply voltage Pin 11 VVCC -0.3 to 7 V
Logic input voltage Pins 4 to 6, 10 VCS,VDI, VCLK,
VINH -0.3 to VVCC+0.3 V
Logic output voltage Pin 9 VDO -0.3 to VVCC+0.3 V
Input current Pins 4 to 6, 10 ICS,IDI, ICLK, IINH -10 to +10 mA
Output curr ent Pin 9 IDO -10 to +10 mA
Output curr ent Pins 2, 12 and
13 IOut3, IOut2, IOut1 Internal limited, see
output specification
Reverse conducting current
(tpulse = 150 µs)
Pins 2, 12 and
13 towards Pin
3IOut3, IOut2, IOut1 17 A
Junction-temperature range TJ-40 to 150 °C
Storage-temperature range TSTG -55 to 150 °C
Thermal Resistance
Parameter Test Conditions Symbol Value Unit
T6818
Junction – pin Measured to GND
Pins 1, 7, 8, 14 RthJP 30 K/W
Junction – ambient RthJA 65 K/W
T6828
Junction – pin Measured to heat slug, GND
Pins 1, 7, 8, 14 RthJP 5K/W
Junction – ambient RthJA 30 K/W
Operating Range
Parameter Symbol Value Unit
Supply voltage VVS VUV 1) to 40 V
Logic supply voltage VVCC 4.75 to 5.25 V
Logic input voltage
V
CS
,V
DI
, V
CLK
,
V
INH
-0.3 to VVCC V
Serial interface clock frequency fCLK 2MHz
Junction-temperature range Tj-40 to 150 °C
8 (16)
Preliminary Information
T6818 /
T6828
Rev. A1, 07-Nov-01
Noi s e a n d Surge Im munit y
Parameter Test Conditions Value
Conducted interferences ISO 7637–1Level 4
1)
Interference suppression VDE 0879 Part 3 Level 6
ESD (Human Body Model) ESD S 5.1 2 kV
ESD (Machine Model) JEDEC A115A 200 V
Electrical Characteristics
7.5 V < VVS < 40 V; 4.5 V < VVCC < 5.5 V; INH = High; -40°C < Tj < 150°C; unless otherwise specified,
all values refer to GND pins.
No. Parameters Test Conditions Pin Symbol Mi n. Ty p. Max. Unit Type*
1 Current Consumption
1.1 Quiescent current
(VS )VVS < 16 V,
INH = low 3 IVS 1 5 µA A
1.2 Quiescent current
(VCC)
4.75 V < V
VCC
<
5.25 V, INH = low
11 IVCC 15 25 µA A
1.3 Supply current (VS) VVS <16 V
normal operating,
all outputs off 3 IVS 4 6 mA A
1.4 Supply current (VCC) 4.75 V < VVCC <
5.25 V,
normal operating 11 IVCC 350 500 µA A
2 Undervoltage Detection, Power-On Reset
2.1 Power-on reset
threshold 11 VVCC 3.4 3.9 4.4 V A
2.2 Powe-on reset
delay time After switching on
VCC tdPor 30 95 160 µs A
2.3 Undervoltage-
detection threshold VCC = 5 V 3 VUv 5.5 7.0 V A
2.4 Undervoltage-
detection hysteresis VCC = 5 V 3 ∆VUv 0.6 V B
2.5 Undervoltage-
detection delay time tdUV 10 40 µs A
3 Thermal Prewarning and Shutdown
3.1 Thermal prewarning TjPW set 120 145 170 °C B
3.2 Thermal prewarning TjPW reset 105 130 155 °C B
3.3 Thermal prewarning
hysteresis ∆TjPW 15 °C B
3.4 Thermal shutdown Tj s witch off 150 175 200 °C B
3.5 Thermal shutdown Tj s witch on 135 160 185 °C B
3.6 Thermal shutdown
hysteresis ∆Tj switch off 15 °C B
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
9 (16)
Preliminary Information
T6818 / T6828
Rev. A1, 07-Nov-01
3.7 Ratio thermal
shutdown / thermal
prewarning
Tj switch off /
TjPW set 1.05 1.2 B
3.8 Ratio thermal
shutdown / thermal
prewarning
Tj switch on /
TjPW reset 1.05 1.2 B
4 Output Specification (OUT1-OUT3)
4.1 On resistance IOut = 1.5 A 2, 12,
13 RDS On L 1ΩB
4.2 On resistance IOut = -1.5 A 2, 12,
13 RDS On H 1ΩB
4.3 Source output
leakage current VOut1-3 = 0 V,
output stages off 2, 12,
13 IOut1-3 -15 µA A
4.4 Sink output leakage
current VOut1-3 = VVS,
output stages off 2, 12,
13 IOut1-3 300 µA A
4.5 High-sid e switch
re verse d iode fo rward
voltage IOut = 1.5 A 2, 12,
13 VOut1-3 –VVS 1.3 V A
4.6 Low-side switch
re verse d iode fo rward
voltage IOut = -1.5 A 2, 12,
13 VOut1-3 -1.3 V A
4.7 Sour ce overcurr ent
limitation and
shutdown threshold
2, 12,
13 IOut1-3 -2.5 -2 -1.5 A A
4.8 Sink overcurrent
limitation and
shutdown threshold
2, 12,
13 IOut1-3 1.5 22.5 A A
4.9 Overcurrent
shutdown delay time tdSd 10 40 µs A
4.10 Source open-load
detection threshold 2, 12,
13 IOut1-3 -45 -30 -15 mA A
4.11 Sink open-load
detection threshold 2, 12,
13 IOut1-3 15 30 45 mA A
4.12 Open-load detect ion
delay time tdSd 200 600 µs A
4.13 Sourc e output swit ch
on delay 1) VVS = 13 V,
RLoad = 30 Ωtdon 515 µs A
4.14 Sink output swi t ch on
delay 1) VVS = 13 V,
RLoad = 30 Ωtdon 15 25 µs A
4.15 Sourc e output swit ch
off delay 1) VVS = 13 V,
RLoad = 30 Ωtdoff 515 µs A
4.16 Sink output swi tch off
delay 1) VVS = 13 V,
RLoad = 30 Ωtdoff 1 2 µs A
Electrical Characteristics
7.5 V < VVS < 40 V; 4.5 V < VVCC < 5.5 V; INH = High; -40°C < Tj < 150°C; unless otherwise specified,
all values refer to GND pins.
No. Parameters Test Conditions Pin Symbol Mi n. Ty p. Max. Unit Type*
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
10 (16)
Preliminary Information
T6818 /
T6828
Rev. A1, 07-Nov-01
Note: 1. Dela y time be tween rising edge o f CS after d ata tr ans mission and s wit ch on output stages to 90% of fi nal level. Device not in
stand-by for t >1ms
4.17 Dead time between
corresponding high-
and low-side switches
VVS = 13 V,
RLoad = 30 Ωtdon -tdoff 1µs B
5 Logic Inputs DI, CLK, CS, INH
5.1 Input v ol tag e lo w -
level threshold 4-6,
10 VIL 0.3 ×
VVCC V A
5.2 Input v ol tag e high -
level threshold 4-6,
10 VIH 0.7
r
VVC
CV A
5.3 Hysteresis of input
voltage 4-6,
10 ∆VI50 500 mV B
5.4 Pull-down current Pin
DI, CLK, INH VDI, VCLK, VINH = VCC 5, 6,
10 IPD 10 60 µA A
5.5 Pull-up current
Pin CS VCS = 0 V 4 IPU -50 -10 µA A
6 Serial Interface – Logic Output DO
6.2 Output-voltage high
level IOL = -2 mA 9 VDOH VVCC-
0.7 V V A
6.3 Leakage current
(tristate) VCS = VCC
0V < VDO < VVCC 9 IDO -10 10 µA A
7Inhibit Input - Timing
7.1 Standby setup time tIINHsethl 100 µs A
7.2 Standby setup time tIINHsetlh 100 µs A
Electrical Characteristics
7.5 V < VVS < 40 V; 4.5 V < VVCC < 5.5 V; INH = High; -40°C < Tj < 150°C; unless otherwise specified,
all values refer to GND pins.
No. Parameters Test Conditions Pin Symbol Mi n. Ty p. Max. Unit Type*
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
11 (16)
Preliminary Information
T6818 / T6828
Rev. A1, 07-Nov-01
Serial Interfac e – Timing
Parameters Test
Conditions Timing
Chart No. Symbol Min. Typ. Max. Unit
DO enable after CS falling edge CDO = 100 pF 1 tENDO 200 ns
DO disable after CS rising edge CDO = 100 pF 2 tDISDO 200 ns
DO fall time CDO = 100 pF - tDOf 100 ns
DO rise time CDO = 100 pF - tDOr 100 ns
DO valid time CDO = 100 pF 10 tDOVal 200 ns
CS setup time 4 tCSSethl 225 ns
CS setup time 8 tCSSetlh 225 ns
CS high time 9 tCSh 500 ns
CLK high time 5 tCLKh 225 ns
CLK low time 6 t CLKl 225 ns
CLK period time - tCLKp 500 ns
CLK setup time 7 tCLKSethl 225 ns
CLK setup time 3 tCLKSetlh 225 ns
DI setup tim e 11 tDIset 40 ns
DI hold time 12 tDIHold 40 ns
12 (16)
Preliminary Information
T6818 /
T6828
Rev. A1, 07-Nov-01
Figure 4. Serial interface timing with chart numbers
CS
DO
1 2
CS
CLK
4
5
6
7
9
83
DI
CLK
DO
10 12
11
Inputs DI, CLK , CS: High level = 0.7 x VCC, low level = 0.3 x VCC
Output DO: High level = 0.8 x VCC, low level = 0.2 x VCC
13 (16)
Preliminary Information
T6818 / T6828
Rev. A1, 07-Nov-01
Application Circuit
Figure 5.
Application Notes It is strongly recommended to connect the blocking capacitors at VCC and VS as close a s
possible to the power supply and GND pins.
Recommended value for capacitors at VS:
Electrolytic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. Value
for electrolytic capacitor depends o n external loads, conducted interferences and
reverse conducting current IOutzx (see Absolute Maximum Ratings).
Recommended value for capacitors at VCC:
Electrolytic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF.
To redu ce ther mal res istan ce it is r ecomm ended to place co oling areas on the PCB as
close as possible to GND pins.
DI
CLK
INH
DO
CS UV
protection
Serial interface
Input register
Output register
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
O
C
Sn.n. n. n.n.n.
P
S
F
O
P
L
S
C
D
n.
u. H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
T
P
OUT3
VS
VCC
Thermal
protection
Control
logic Power-on
reset
Charge
pump
OUT2 OUT1
n.n.
u.
GND
n.
u. n.
u. n.
u. n.
u. n.
u.
u. u. u. u. u. u. u. 3
11
1
7
8
14
21213
5
6
4
10
9
GND
GND
GND
Fault
detect
Fault
detect
Fault
detect
Fault
detect Fault
detect Fault
detect
Vcc
5 V
Vcc
++
13 V
BYT41D
Vs
+
VBat
t
µC
U5021M
Watchdog
Vcc
Vcc
Reset
Trigger
Enable
MM
14 (16)
Preliminary Information
T6818 /
T6828
Rev. A1, 07-Nov-01
Package Information
technical drawings
according to DIN
specifications
Package SO1 4
Dimensions in mm
0.25
0.10
8.75
0.4
1.27 7.62
1.4
5.2
4.8
3.7
3.8
6.15
5.85
0.2
14 8
17
15 (16)
Preliminary Information
T6818 / T6828
Rev. A1, 07-Nov-01
Ozone Depleting Substances Policy Statement
It is the policy of Atmel Germany GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems
with respect to their impact on the health and safety of our employees and the public, as well as their impact on
the environment.
It is par ticu lar concer n to con trol or eliminate r eleases of tho se substances into the atmosphere which are known as
ozone depleting substances (ODSs).
The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid
their use wi thin the next ten years. Var io us nation al and i nter n ational in itiati ves are pres sing for an ear lier ba n on t hese
substances.
Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed
in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.
Atmel Germany GmbH can certify that our semiconductors are not manuf actured with ozone depleting substances and
do not contain suc h substa nc es.
© Atm el Germany Gm bH 2001.
Atmel Ger many GmbH makes no warranty for t he use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel Ger many GmbH’s Ter ms and Conditions. The Company assume s no resp onsibility for any errors which may appear in
this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commit-
ment to update the information contained herein. No licenses to patents or other intellectual proper ty of Atmel Ger many GmbH are granted by
the Company in connection with the sale of AtmelGermany GmbH products, expressly or by implication. Atmel Germany GmbH’s products are
not authorized fo r use as critical components in life suppor t devices or systems.
Data sheets can also be retrieved fron the Inter net: http://www. atmel-wm.com
Rev. A1, 07-Nov-01
Atmel Wireless & Microcontrollers Sal es Offices
France
3, Avenue du Centre
78054 St.-Quentin-en-Yvelines
Cedex
Tel: +33 1 30 60 70 00
Fax: +33 1 30 60 71 11
Germany
Erfurter Strasse 31
85386 Eching
Tel: +49 89 31 9 70 0
Fax: +49 89 319 46 21
Kruppstrasse 6
45128 Essen
Tel: +49 201 247 30 0
Fax: +49 201 247 30 47
Theresienstrasse 2
74072 Heilbronn
Tel: +49 71 31 67 36 3 6
Fax: +49 7131 67 31 63
Italy
Via Grosio, 10/8
20151 Milano
Tel: +39 02 38 03 71
Fax: +39 02 38 03 72 34
Spain
Principe de Vergara, 112
28002 Madrid
Tel: +34 91 56 4 51 81
Fax: +34 91 562 75 14
Sweden
Kavallerivaegen 24, Rissne
17402 Sundbyberg
Tel: +46 8 587 48 800
Fax: +46 8 587 48 850
United Kingdom
Easthampstead Road
Bracknell
Berkshire RG12 1LX
Tel: +44 1344 707 300
Fax: +44 1344 427 371
USA Western
2325 Orchard Parkway
San Jose, California 95131
Tel: +1 408 441 0311
Fax: +1 408 436 4200
USA Eastern
1465 Route 31, Fifth floor
Annandale
New Jers ey 08801
Tel: +1 908 848 5208
Fax: +1 908 848 5232
Hong Kong
Room #1219,
Chinachem Golden Plaza
77 Mody Road, Tsimhatsui East
East Kowloon, Hong Kong
Tel: +852 23 789 789
Fax: +852 23 755 733
Korea
25-4 , Yoido-Do ng, Suit e 605,
Sing song Bldg.
Youngdeungpo-Ku
150-010 Seoul
Tel: +822 785 1136
Fax: +822 785 1137
Rep. of Singapore
Keppel Building #03-00
25 Tampines Street 92,
Singapore 528877
Tel: +65 260 8223
Fax: +65 787 9819
Taiwan, R.O.C.
8F-2, 266 S ec.1 Wen Hw a 2 Rd.
Lin Kou Hsiang,
244 Taipei Hsien
Tel : +886 2 2609 5581
Fax: +886 2 2600 2735
Japan
Tonetsushinkawa Bldg.
1-24-8 Shinkawa Chuo Ku
Tokyo 104-0033
Tel: +81 3 3523 3551
Fax: +81 3 3523 7581
Web Site
http://www.atmel-wm.com
