1995 Microchip Technology Inc. DS21134A-page 1
FEATURES
• Voltage operating range; 4.5V to 5.5V
• Low power CMOS technology
- 3 mA maximum write current
- 200
µ
A typical read current
- 10
µ
A standby current typical at 5.5V
-5
µ
A standby current typical at 4.5V
• Organized as 8 blocks of 256 bytes (8 x 256 x 8)
• 1 MHz SE2.bus two wire protocol
• Schmitt trigger inputs for noise suppression
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 4 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
• 10,000,000 ERASE/WRITE cycles guaranteed
• Data retention > 200 years
• 8 pin DIP and 8-lead SOIC packages
• Available for extended temperature ranges
- Commercial: 0
°
C to +70
°
C
- Industrial: -40
°
C to +85
°
C
DESCRIPTION
The Microchip Technology Inc. 24FC16 is a 16K-bit
Electrically Erasable PROM. The device is organized
as 8 blocks of 256 x 8-bit memory with a high-speed
1MHz SE2.bus whose protocol is functionally
equivalent to the industry-standard I
2
C bus. The
24FC16 also has a page-write capability for up to
16 bytes of data. The 24FC16 is available in the
standard 8-pin DIP and 8-lead SOIC packages.
PACKAGE TYPE
BLOCK DIAGRAM
24FC16
8-lead SOIC
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
VSS
24FC16
DIP
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
VSS
I/O
CONTROL
LOGIC
EEPROM ARRA Y
(8 x 256 x 8)
PAGE LATCHES
HV GENERATOR
SENSE AMP
R/W CONTROL
MEMORY
CONTROL
LOGIC XDEC
YDEC
VCC
VSS
SCL
WP
SDA
24FC16
16K 5.0V 1MHz CMOS Serial EEPROM
I
2
C is a trademark of Philips Corporation
This document was created with FrameMaker404
24FC16
DS21134A-page 2
1995 Microchip Technology Inc.
1.0 ELECTRICAL CHARA CTERISTICS
1.1 Maximum Ratings*
V
CC
........................................................................7.0V
All inputs and outputs w.r.t. V
SS
.... -0.3V to V
CC
+1.0V
Storage temperature ..........................-65
°
C to +150
°
C
Ambient temp. with power applied .....-65
°
C to +125
°
C
Soldering temperature of leads (10 seconds) ..+300
°
C
ESD protection on all pins
......................................≥
4 kV
*Notice:
Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1: PIN FUNCTION TABLE
Name Function
V
SS
Ground
SDA Serial Address/Data I/O
SCL Serial Clock
WP Write Protect Input
V
CC
+4.5V to 5.5V Power Supply
A0, A1, A2
No Internal Connection
TABLE 1-2: DC CHARACTERISTICS
FIGURE 1-1: BUS TIMING START/STOP
Vcc = +4.5V to +5.5V
Commercial (C): Tamb = 0
°
C to +70
°
C
Industrial (I): Tamb = -40
°
C to +85
°
C
Parameter Symbol Min Max Units Conditions
WP, SCL and SDA pins:
High level input voltage V
IH
0.7 V
CC
—V
Low level input voltage V
IL
— 0.3 V
CC
V
Hysteresis of Schmitt trigger
inputs V
HYS
0.05 V
CC
— V Note 1
Low level output voltage V
OL
— 0.40 V I
OL
= 3.0 mA
Input leakage current I
LI
-10 10
µ
AV
IN
= 0.1V to V
CC
Output leakage current I
LO
-10 10
µ
AV
OUT
= 0.1V to V
CC
Pin capacitance
(all inputs/outputs) C
INT
—10pFV
CC
= 5.0V (Note 1)
Tamb = 25
°
C, F
CLK
= 1MHz
Operating current I
CC
write
I
CC
read —
—3
1mA
mA V
CC
= 5.5V, SCL = 1MHz
Standby current I
CCS
— 100
µ
AV
CC
= 5.5V, SDA = SCL = V
CC
Note 1: This parameter is periodically sampled and not 100% tested.
SCL
SDA
START STOP
VHYS TSU:STO
THD:STA
TSU:STA
1995 Microchip Technology Inc. DS21134A-page 3
24FC16
TABLE 1-3: AC CHARACTERISTICS
FIGURE 1-2: BUS TIMING DATA
Parameter Symbol 1 MHz Bus Units Remarks
Min Max
Clock frequency F
CLK
0 1000 kHz
Clock high time
THIGH
500 — ns
Clock low time T
LOW
500 — ns
SDA and SCL rise time T
R
— 300 ns Note 1
SDA and SCL fall time T
F
— 100 ns Note 1
START hold time T
HD
:
STA
250 — ns After this period the first clock pulse is
generated
START setup time T
SU
:
STA
250 — ns Only relevant for repeated START
Data input hold time T
HD
:
DAT
0—ns
Data input setup time T
SU
:
DAT
100 — ns
STOP setup time T
SU
:
STO
250 — ns
Output valid from clock T
AA
— 400 ns Note 2
Bus free time T
BUF
500 — ns Time the bus must be free before a
new transmission can start
Write cycle time T
WR
— 10 ms Byte or page
Note 1: Not 100 percent tested.
Note 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 100 ns) of the falling edge of SCL to avoid unintended generation of START or STOPs.
SCL
SDA
IN
SDA
OUT
TSU:STA
TSP
TAA
TF
TLOW
THIGH
THD:STA THD:DAT TSU:DAT TSU:STO
TBUF
TAA
TR
24FC16
DS21134A-page 4
1995 Microchip Technology Inc.
2.0 FUNCTIONAL DESCRIPTION
The 24FC16 supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver . The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP, while the 24FC16 works as slave.
Both, master and slave can operate as transmitter or
receiver but the master device determines which mode
is activated.
3.0 BUS CHARA CTERISTICS
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1 Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2 Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START. All
commands must be preceded by a START.
3.3 Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP. All
operations must be ended with a STOP.
3.4 Data Valid (D)
The state of the data line represents valid data when,
after a START, the data line is stable for the duration of
the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START and
terminated with a STOP. The number of the data bytes
transferred between the STARTs and STOPs is
determined by the master device and is theoretically
unlimited, although only the last sixteen will be stored
when doing a write operation. When an overwrite does
occur it will replace data in a first in first out fashion.
3.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24FC16) will leave the data line
HIGH to enable the master to generate the STOP.
Note: The 24FC16 does not generate any
acknowledge bits if an internal
programming cycle is in progress.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL
SDA
(A) (B)
START
(C) (A)(D) (D)
Address
or
Acknowledge
Valid
Data Allowed
to Change STOP
ConditionCondition
1995 Microchip Technology Inc. DS21134A-page 5
24FC16
4.0 BUS CHARA CTERISTICS
4.1 Device Addressing and Operation
A control byte is the first byte received following the
START from the master device. The control byte
consists of a four bit control code, for the 24FC16 this
is set as 1010 binary for read and write operations. The
next three bits of the control byte are the block select
bits (B2, B1, B0). They are used by the master device
to select which of the eight 256 word blocks of memory
are to be accessed. These bits are in effect the three
most significant bits of the word address. It should be
noted that the protocol limits the size of the memory to
eight blocks of 256 words, therefore the protocol can
support only one 24FC16 per system.
The last bit of the control byte defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the START, the 24FC16 monitors the SDA
bus checking the device type identifier being
transmitted, upon a 1010 code the slave device outputs
an acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the 24FC16 will select a read
or write operation.
Operation Control
Code Block Select R/W
Read 1010 Block Address 1
Write 1010 Block Address 0
FIGURE 4-1: CONTROL BYTE
ALLOCATION
1B1
B0
B2010
SLA VE ADDRESS
START READ/WRITE
A
R/W
24FC16
DS21134A-page 6 1995 Microchip Technology Inc.
5.0 WRITE OPERATION
5.1 Byte Write
Following the START from the master, the device code
(4-bits), the block address (3-bits), and the R/W bit
which is a logic low is placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow after it has generated an acknowledge bit during
the ninth clock cycle. Therefore the next byte
transmitted by the master is the word address and will
be written into the address pointer of the 24FC16. After
receiving another acknowledge signal from the
24FC16 the master device will transmit the data word
to be written into the addressed memory location. The
24FC16 acknowledges again and the master
generates a STOP. This initiates the internal write
cycle, and during this time the 24FC16 will not generate
acknowledge signals (Figure 5-1).
5.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24FC16 in the same way as
in a byte write. But instead of generating a STOP the
master transmits up to sixteen data bytes to the
24FC16 which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a STOP. After the receipt of
each word, the four lower order address pointer bits are
internally incremented by one. The higher order seven
bits of the word address remains constant. If the master
should transmit more than sixteen words prior to
generating the STOP, the address counter will roll over
and the previously received data will be overwritten. As
with the byte write operation, once the STOP is
received an internal write cycle will begin (Figure 8-1).
FIGURE 5-1: BYTE WRITE
BUS ACTIVITY :
MASTER
SDA LINE
BUS ACTIVITY
CONTROL
BYTE
A
C
K
S
T
A
R
T
WORD
ADDRESS
A
C
K
S
T
O
P
A
C
K
DATA
SP
1995 Microchip Technology Inc. DS21134A-page 7
24FC16
6.0 A CKNO WLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the STOP for a write command has
been issued from the master, the device initiates the
internally timed write cycle. ACK polling can be initiated
immediately. This involves the master sending a
START followed by the control byte for a write
command (R/W = 0). If the device is still busy with the
write cycle, then no ACK will be returned. If the cycle is
complete, then the device will return the ACK and the
master can then proceed with the next read or write
command (see Figure 6-1 for flow diagram).
FIGURE 6-1: ACKNOWLEDGE POLLING
FLOW
Did Device
Acknowledge
(ACK = 0)?
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Next
Operation
No
Yes
7.0 WRITE PROTECTION
The 24FC16 can be used as a serial ROM when the
WP pin is connected to VCC. Programming will be
inhibited and the entire memory will be write-protected.
24FC16
DS21134A-page 8 1995 Microchip Technology Inc.
8.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
8.1 Current Address Read
The 24FC16 contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous access (either a read or write operation) was
to address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to one, the 24FC16
issues an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24FC16
discontinues transmission (Figure 8-2).
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24FC16 as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24FC16 will then
issue an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
does generate a STOP and the 24FC16 discontinues
transmission (Figure 8-3).
FIGURE 8-1: PAGE WRITE
FIGURE 8-2: CURRENT ADDRESS READ
FIGURE 8-3: RANDOM READ
BUS
MASTER
SDA LINE
BUS
CONTROL
BYTE WORD
ADDRESS (n)
S
T
O
P
S
T
A
R
T
A
C
K
A
C
K
A
C
K
ACTIVITY:
ACTIVITY:
A
C
K
A
C
K
DATA n + 1 DATA n +15
S
DATA n
P
CONTROL
A
C
K
S
T
A
R
T
S
T
O
P
BYTE DATA n
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
A
C
K
N
O
PS
SDA LINE
BUS
CONTROL
BYTE
S
T
O
P
S
T
A
R
T
A
C
K
A
C
K
ACTIVITY: A
C
K
N
O
DATA n
WORD
ADDRESS (n)
S
T
A
R
T
CONTROL
BYTE
A
C
K
PSS
BUS ACTIVITY
MASTER
1995 Microchip Technology Inc. DS21134A-page 9
24FC16
8.3 Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24FC16 transmits
the first data byte, the master issues an acknowledge
as opposed to a STOP in a random read. This directs
the 24FC16 to transmit the next sequentially
addressed 8-bit word (Figure 8-4).
To provide sequential reads the 24FC16 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
8.4 Noise Protection
The 24FC16 employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.5V at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
FIGURE 8-4: SEQUENTIAL READ
A
C
K
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
CONTROL
BYTE
DATA n DATA n+1 DATA n+2 DATA n+X
A
C
K
A
C
K
A
C
KN
O
A
C
K
S
T
O
P
P
24FC16
DS21134A-page 10 1995 Microchip Technology Inc.
9.0 PIN DESCRIPTIONS
9.1 SDA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to VCC (typical 1KΩ, must consider total bus
capacitance and maximum rise/fall times).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the STARTs and STOPs.
9.2 SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
9.3 WP
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to VCC (typical 1KΩ, must consider total bus
capacitance and maximum rise/fall times).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOPs.
9.4 A0, A1, A2
These pins are not used by the 24FC16. They may be
left floating or tied to either VSS or VCC.
1995 Microchip Technology Inc. DS21134A-page 11
24FC16
NOTES:
24FC16
DS21134A-page 12 1995 Microchip Technology Inc.
24FC16 Product Identification System
To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed
sales offices.
Package: P = PDIP
SN = 150 mil SOIC (JEDEC standard)
Temperature Blank = 0°C to +70°C
Range: I= -40°C to +85°C
Device: 24FC16 16K, 1MHz, CMOS, Serial EEPROM
24FC16T 16K, 1MHz, CMOS, Serial EEPROM (Tape & Reel)
24FC16 - /P
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Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty
is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property
rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip.
No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights
reserved. All other trademarks mentioned herein are the property of their respective companies.
All rights reserved. 1995, Microchip Technology Incorporated, USA.
