© Semiconductor Components Industries, LLC, 2017
January, 2017 − Rev. 9 1Publication Order Number:
MC74HC4051A/D
MC74HC4051A,
MC74HC4052A,
MC74HC4053A
Analog Multiplexers/
Demultiplexers
High−Performance Silicon−Gate CMOS
The MC74HC4051A, MC74HC4052A and MC74HC4053A utilize
silicon−gate CMOS technology to achieve fast propagation delays,
low ON resistances, and low OFF leakage currents. These analog
multiplexers/demultiplexers control analog voltages that may vary
across the complete power supply range (from VCC to VEE).
The HC4051A, HC4052A and HC4053A are identical in pinout to
the metal−gate MC14051AB, MC14052AB and MC14053AB. The
Channel−Select inputs determine which one of the Analog
Inputs/Outputs i s t o b e connected, by means of an analog switch, to the
Common Output/Input. When the Enable pin is HIGH, all analog
switches are turned off.
The Channel−Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors they are compatible with LSTTL
outputs.
These devices have been designed so that the ON resistance (Ron) is
more linear over input voltage than Ron of metal−gate CMOS analog
switches.
For a multiplexer/demultiplexer with injection current protection,
see HC4851A and HC4852A.
Features
•Fast Switching and Propagation Speeds
•Low Crosstalk Between Switches
•Diode Protection on All Inputs/Outputs
•Analog Power Supply Range (VCC − VEE) = 2.0 to 12.0 V
•Digital (Control) Power Supply Range (VCC − GND) = 2.0 to 6.0 V
•Improved Linearity and Lower ON Resistance Than Metal−Gate
Counterparts
•Low Noise
•In Compliance with the Requirements of JEDEC Standard No. 7A
•Chip Complexity: HC4051A − 184 FETs or 46 Equivalent Gates
HC4052A − 168 FETs or 42 Equivalent Gates
HC4053A − 156 FETs or 39 Equivalent Gates
•NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•These Devices are Pb−Free, Halogen Free/BFR−Free and are RoHS
Compliant
This document contains information on some products that are still under development.
ON Semiconductor reserves the right to change or discontinue these products without
notice.
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MARKING DIAGRAMS
SOIC−16
TSSOP−16
1
16
HC405xAG
AWLYWW
HC40
5xA
ALYWG
G
1
16
SOIC−16 WIDE
1
16
HC405xA
AWLYWWG
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
ORDERING INFORMATION
x = 1, 2 or 3
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G= Pb−Free Package
(Note: Microdot may be in either location)
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
SOIC−16 WIDE
DW SUFFIX
CASE 751G
4051
ALYWG
G
QFN16
1
QFN16
MN SUFFIX
CASE 485AW
MC74HC4051A, MC74HC4052A, MC74HC4053A
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2
LOGIC DIAGRAM
MC74HC4051A
Single−Pole, 8−Position Plus Common Off
X0 13
X1 14
X2 15
X3 12
X4 1
X5 5
X6 2
X7 4
A11
B10
C9
ENABLE 6
MULTIPLEXER/
DEMULTIPLEXER
X
3
ANALOG
INPUTS/
CHANNEL
INPUTS
PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
COMMON
OUTPUT/
INPUT
1516 14 13 12 11 10
21 34567
VCC
9
8
X2 X1 X0 X3 A B C
X4 X6 X X7 X5 Enable VEE GND
Pinout: MC74HC4051A (Top View)
OUTPUTS
SELECT
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
FUNCTION TABLE − MC74HC4051A
Control Inputs
ON Channels
Enable Select
CBA
X0
X1
X2
X3
X4
X5
X6
X7
NONE
L
L
L
L
L
L
L
L
HX = Don’t Care
LOGIC DIAGRAM
MC74HC4052A
Double−Pole, 4−Position Plus Common Off
X0 12
X1 14
X2 15
X3 11
Y0 1
Y1 5
Y2 2
Y3 4
A10
B9
ENABLE 6
X SWITCH
Y SWITCH
X
13
ANALOG
INPUTS/OUTPUTS
CHANNEL‐SELECT
INPUTS PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
COMMON
OUTPUTS/INPUTS
L
L
H
H
X
L
H
L
H
X
FUNCTION TABLE − MC74HC4052A
Control Inputs
ON ChannelsEnable Select
BA
X0
X1
X2
X3
L
L
L
L
H
X = Don’t Care
Pinout: MC74HC4052A (Top View)
1516 14 13 12 11 10
21 34567
VCC
9
8
X2 X1 X X0 X3 A B
Y0 Y2 Y Y3 Y1 Enable VEE GND
Y
3
Y0
Y1
Y2
Y3 NONE
MC74HC4051A, MC74HC4052A, MC74HC4053A
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3
LOGIC DIAGRAM
MC74HC4053A
Triple Single−Pole, Double−Position Plus Common Off
X0 12
X1 13
A11
B10
C9
ENABLE 6
X SWITCH
Y SWITCH
X
14
ANALOG
INPUTS/OUTPUTS
CHANNEL‐SELECT
INPUTS
PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
COMMON
OUTPUTS/INPUTS
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
FUNCTION TABLE − MC74HC4053A
Control Inputs
ON ChannelsEnable Select
CBA
L
L
L
L
L
L
L
L
H
X = Don’t Care
Pinout: MC74HC4053A (Top View)
1516 14 13 12 11 10
21 34567
VCC
9
8
Y X X1 X0 A B C
Y1 Y0 Z1 Z Z0 Enable VEE GND
Z0
Z0
Z0
Z0
Z1
Z1
Z1
Z1
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
X0
X1
X0
X1
X0
X1
X0
X1
NONE
Y0 2
Y1 1Y
15
Z0 5
Z1 3Z
4
Z SWITCH
NOTE: This device allows independent control of each switch.
Channel−Select Input A controls the X−Switch, Input B controls
the Y−Switch and Input C controls the Z−Switch
MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC Positive DC Supply Voltage (Referenced to GND)
(Referenced to VEE)–0.5 to +7.0
–0.5 to +14.0 V
VEE Negative DC Supply Voltage (Referenced to GND) –7.0 to +5.0 V
VIS Analog Input Voltage VEE − 0.5 to
VCC + 0.5 V
Vin Digital Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V
IDC Current, Into or Out of Any Pin ±25 mA
PDPower Dissipation in Still Air, SOIC Package†
TSSOP Package† 500
450 mW
Tstg Storage Temperature Range –65 to +150 _C
TLLead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package 260
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74HC4051A, MC74HC4052A, MC74HC4053A
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4
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC Positive DC Supply Voltage (Referenced to GND)
(Referenced to VEE)2.0
2.0 6.0
12.0 V
VEE Negative DC Supply Voltage, Output (Referenced to GND) −6.0 GND V
VIS Analog Input Voltage VEE VCC V
Vin Digital Input Voltage (Referenced to GND) GND VCC V
VIO*Static or Dynamic Voltage Across Switch 1.2 V
TAOperating Temperature Range, All Package Types –55 +125 _C
tr, tfInput Rise/Fall Time VCC = 2.0 V
(Channel Select or Enable Inputs) VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
0
1000
600
500
400
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
*For voltage drops across switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may
contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted
Symbo
l
Parameter Condition VCC
V
Guaranteed Limit
Unit
−55 to 25°C≤85°C≤125°C
VIH Minimum High−Level Input Voltage,
Channel−Select or Enable Inputs Ron = Per Spec 2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
VIL Maximum Low−Level Input Voltage,
Channel−Select or Enable Inputs Ron = Per Spec 2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
Iin Maximum Input Leakage Current,
Channel−Select or Enable Inputs Vin = VCC or GND,
VEE = − 6.0 V 6.0 ±0.1 ±1.0 ±1.0 mA
ICC Maximum Quiescent Supply
Current (per Package) Channel Select, Enable and
VIS = VCC or GND; VEE = GND
VIO = 0 V VEE = − 6.0 6.0
6.0 1
410
40 20
80
mA
MC74HC4051A, MC74HC4052A, MC74HC4053A
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DC CHARACTERISTICS — Analog Section
Symbo
l
Parameter Condition VCC VEE
Guaranteed Limit
Unit
−55 to 25°C≤85°C≤125°C
Ron Maximum “ON” Resistance Vin = VIL or VIH; VIS = VCC to
VEE; IS ≤ 2.0 mA
(Figures 1, 2)
4.5
4.5
6.0
0.0
− 4.5
− 6.0
190
120
100
240
150
125
280
170
140
W
Vin = VIL or VIH; VIS = VCC or
VEE (Endpoints); IS ≤ 2.0 mA
(Figures 1, 2)
4.5
4.5
6.0
0.0
− 4.5
− 6.0
150
100
80
190
125
100
230
140
115
DRon Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
Vin = VIL or VIH;
VIS = 1/2 (VCC − VEE);
IS ≤ 2.0 mA
4.5
4.5
6.0
0.0
− 4.5
− 6.0
30
12
10
35
15
12
40
18
14
W
Ioff Maximum Off−Channel Leakage
Current, Any One Channel Vin = VIL or VIH;
VIO = VCC − VEE;
Switch Off (Figure 3) 6.0 − 6.0 0.1 0.5 1.0 mA
Maximum Off−ChannelHC4051A
Leakage Current, HC4052A
Common Channel HC4053A
Vin = VIL or VIH;
VIO = VCC − VEE;
Switch Off (Figure 4)
6.0
6.0
6.0
− 6.0
− 6.0
− 6.0
0.2
0.1
0.1
2.0
1.0
1.0
4.0
2.0
2.0
Ion Maximum On−ChannelHC4051A
Leakage Current, HC4052A
Channel−to−Channel HC4053A
Vin = VIL or VIH;
Switch−to−Switch =
VCC − VEE; (Figure 5)
6.0
6.0
6.0
− 6.0
− 6.0
− 6.0
0.2
0.1
0.1
2.0
1.0
1.0
4.0
2.0
2.0
mA
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbo
l
Parameter VCC
V
Guaranteed Limit
Unit
−55 to 25°C≤85°C≤125°C
tPLH,
tPHL Maximum Propagation Delay, Channel−Select to Analog Output
(Figure 9) 2.0
3.0
4.5
6.0
270
90
59
45
320
110
79
65
350
125
85
75
ns
tPLH,
tPHL Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10) 2.0
3.0
4.5
6.0
40
25
12
10
60
30
15
13
70
32
18
15
ns
tPLZ,
tPHZ Maximum Propagation Delay, Enable to Analog Output
(Figure 11) 2.0
3.0
4.5
6.0
160
70
48
39
200
95
63
55
220
110
76
63
ns
tPZL,
tPZH Maximum Propagation Delay, Enable to Analog Output
(Figure 11) 2.0
3.0
4.5
6.0
245
115
49
39
315
145
69
58
345
155
83
67
ns
Cin Maximum Input Capacitance, Channel−Select or Enable Inputs 10 10 10 pF
CI/O Maximum Capacitance Analog I/O 35 35 35 pF
(All Switches Off) Common O/I: HC4051A
HC4052A
HC4053A
130
80
50
130
80
50
130
80
50
Feed−through 1.0 1.0 1.0
CPD Power Dissipation Capacitance (Figure 13)* HC4051A
HC4052A
HC4053A
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
pF
45
80
45
*Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.
MC74HC4051A, MC74HC4052A, MC74HC4053A
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ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Symbo
l
Parameter Condition VCC
VVEE
V
Limit*
Unit
25°C
BW Maximum On−Channel Bandwidth
or Minimum Frequency Response
(Figure 6)
fin = 1MHz Sine Wave; Adjust fin Voltage
to Obtain 0dBm at VOS; Increase fin
Frequency Until dB Meter Reads −3dB;
RL = 50W, CL = 10pF
2.25
4.50
6.00
−2.25
−4.50
−6.00
‘51 ‘52 ‘53 MHz
80
80
80
95
95
95
120
120
120
−Off−Channel Feed−through
Isolation (Figure 7) fin = Sine Wave; Adjust fin Voltage to
Obtain 0dBm at VIS
fin = 10kHz, RL = 600W, CL = 50pF
2.25
4.50
6.00
−2.25
−4.50
−6.00
−50
−50
−50
dB
fin = 1.0MHz, RL = 50W, CL = 10pF
2.25
4.50
6.00
−2.25
−4.50
−6.00
−40
−40
−40
−Feedthrough Noise.
Channel−Select Input to Common
I/O (Figure 8)
Vin ≤ 1MHz Square Wave (tr = tf = 6ns);
Adjust RL at Setup so that IS = 0A;
Enable = GND RL = 600W, CL = 50pF
2.25
4.50
6.00
−2.25
−4.50
−6.00
25
105
135
mVPP
RL = 10kW, CL = 10pF
2.25
4.50
6.00
−2.25
−4.50
−6.00
35
145
190
−Crosstalk Between Any Two
Switches (Figure 12)
(Test does not apply to HC4051A)
fin = Sine Wave; Adjust fin Voltage to
Obtain 0dBm at VIS
fin = 10kHz, RL = 600W, CL = 50pF
2.25
4.50
6.00
−2.25
−4.50
−6.00
−50
−50
−50
dB
fin = 1.0MHz, RL = 50W, CL = 10pF
2.25
4.50
6.00
−2.25
−4.50
−6.00
−60
−60
−60
THD Total Harmonic Distortion
(Figure 14) fin = 1kHz, RL = 10kW, CL = 50pF
THD = THDmeasured − THDsource
VIS = 4.0VPP sine wave
VIS = 8.0VPP sine wave
VIS = 11.0VPP sine wave
2.25
4.50
6.00
−2.25
−4.50
−6.00
0.10
0.08
0.05
%
*Limits not tested. Determined by design and verified by qualification.
Figure 1a. Typical On Resistance, V
CC
− V
EE
= 2.0 V Figure 1b. Typical On Resistance, V
CC
− V
EE
= 3.0 V
250
200
150
100
50
0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Ron , ON RESISTANCE (OHMS)
100
80
60
40
20
0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.25
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Ron , ON RESISTANCE (OHMS)
25°C
-55°C
125°C
25°C
-55°C
125°C
2.0
0
300 180
160
140
120
02.5 2.75 3.0
MC74HC4051A, MC74HC4052A, MC74HC4053A
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Figure 1c. Typical On Resistance, V
CC
− V
EE
= 4.5 V Figure 1d. Typical On Resistance, V
CC
− V
EE
= 6.0 V
120
100
80
60
40
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Ron , ON RESISTANCE (OHMS)
75
60
45
30
15
0 1.0 2.0 3.0 4.0 5.0 6.03.5 4.5 5.5
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Ron , ON RESISTANCE (OHMS)
20
0
25°C
-55°C
125°C
25°C
-55°C
125°C
90
105
00.5 1.5 2.5
Figure 1e. Typical On Resistance, V
CC
− V
EE
= 9.0 V
01
70
60
50
40
30
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Ron , ON RESISTANCE (OHMS)
20
10
234 56789
25°C
-55°C
125°C
80
0
Figure 1f. Typical On Resistance, V
CC
− V
EE
= 12.0 V
01
60
50
40
30
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Ron , ON RESISTANCE (OHMS)
20
10
234 89101112
25°C
-55°C
125°C
0576
Figure 2. On Resistance Test Set−Up
PLOTTER
MINI COMPUTER
PROGRAMMABLE
POWER
SUPPLY
DC ANALYZER
VCC
DEVICE
UNDER TEST
+-
VEE
ANALOG IN COMMON OUT
GND
MC74HC4051A, MC74HC4052A, MC74HC4053A
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Figure 3. Maximum Off Channel Leakage Current,
Any One Channel, Test Set−Up Figure 4. Maximum Off Channel Leakage Current,
Common Channel, Test Set−Up
Figure 5. Maximum On Channel Leakage Current,
Channel to Channel, Test Set−Up Figure 6. Maximum On Channel Bandwidth,
Test Set−Up
Figure 7. Off Channel Feedthrough Isolation,
Test Set−Up Figure 8. Feedthrough Noise, Channel Select to
Common Out, Test Set−Up
OFF
OFF
6
7
8
16
COMMON O/I
VCC
VEE
VIH
NC
A
VCC
VEE
VCC
OFF
OFF
6
7
8
16
COMMON O/I
VCC
VEE
VIH
ANALOG I/O
VCC
VEE
VCC
ON
OFF
6
7
8
16
COMMON O/I
VCC
VEE
VIL
VCC
VEE
VCC
N/C
A
ANALOG I/O
ON
6
7
8
16
VCC
VEE
0.1mF
CL*
fin
RL
dB
METER
*Includes all probe and jig capacitance
OFF
6
7
8
16
VCC
VEE
0.1mF
CL*
fin
RL
dB
METER
*Includes all probe and jig capacitance
VOS
VOS
RL
VIS
VIL or VIH
CHANNEL SELECT
ON/OFF
6
7
8
16
VCC
VEE
CL*
RL
*Includes all probe and jig capacitance
CHANNEL SELECT
TEST
POINT
COMMON O/I
11
VCC
OFF/ON
ANALOG I/O
RL
RL
VCC
GND
Vin ≤1 MHz
tr = tf = 6 ns
MC74HC4051A, MC74HC4052A, MC74HC4053A
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Figure 9a. Propagation Delays, Channel Select
to Analog Out Figure 9b. Propagation Delay, Test Set−Up Channel
Select to Analog Out
Figure 10a. Propagation Delays, Analog In
to Analog Out Figure 10b. Propagation Delay, Test Set−Up
Analog In to Analog Out
Figure 11a. Propagation Delays, Enable to
Analog Out Figure 11b. Propagation Delay, Test Set−Up
Enable to Analog Out
VCC
GND
CHANNEL
SELECT
ANALOG
OUT 50%
tPLH tPHL
50% ON/OFF
6
7
8
16
VCC
CL*
*Includes all probe and jig capacitance
CHANNEL SELECT
TEST
POINT
COMMON O/I
OFF/ON
ANALOG I/O
VCC
VCC
GND
ANALOG
IN
ANALOG
OUT 50%
tPLH tPHL
50%
ON
6
7
8
16
VCC
CL*
*Includes all probe and jig capacitance
TEST
POINT
COMMON O/I
ANALOG I/O
ON/OFF
6
7
8
ENABLE
VCC
ENABLE 90%
50%
10%
tftr
VCC
GND
ANALOG
OUT
tPZL
ANALOG
OUT
tPZH
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
10%
90%
tPLZ
tPHZ
50%
50%
ANALOG I/O
CL*
TEST
POINT
16
VCC
1kW
1
2
1
2
POSITION 1 WHEN TESTING tPHZ AND tPZH
POSITION 2 WHEN TESTING tPLZ AND tPZL
MC74HC4051A, MC74HC4052A, MC74HC4053A
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RL
Figure 12. Crosstalk Between Any Two
Switches, Test Set−Up Figure 13. Power Dissipation Capacitance,
Test Set−Up
Figure 14a. Total Harmonic Distortion, Test Set−Up Figure 14b. Plot, Harmonic Distortion
0
-10
-20
-30
-40
-50
- 100 1.0 2.0 3.125
FREQUENCY (kHz)
dB
-60
-70
-80
-90
FUNDAMENTAL FREQUENCY
DEVICE
SOURCE
ON
6
7
8
16
VEE CL*
*Includes all probe and jig capacitance
OFF
RL
RL
VIS
RLCL*
VOS
fin
0.1mF
ON/OFF
6
7
8
16
VCC
CHANNEL SELECT
NC
COMMON O/I
OFF/ON
ANALOG I/O
VCC
A
11
VCC
VEE
ON
6
7
8
16
VCC
VEE
0.1mF
CL*
fin
RL
TO
DISTORTION
METER
*Includes all probe and jig capacitance
VOS
VIS
APPLICATIONS INFORMATION
The Channel Select and Enable control pins should be at
VCC or GND logic levels. VCC being recognized as a logic
high and GND being recognized as a logic low. In this
example: VCC = +5V = logic high
GND = 0V = logic low
The maximum analog voltage swings are determined by
the supply voltages VCC and VEE. The positive peak analog
voltage should not exceed VCC. Similarly, the negative peak
analog voltage should not go below VEE. In this example,
the difference between VCC and VEE is ten volts. Therefore,
using the configuration of Figure 15, a maximum analog
signal of ten volts peak−to−peak can be controlled. Unused
analog inputs/outputs may be left floating (i.e., not
connected). However, tying unused analog inputs and
outputs to VCC or GND through a low value resistor helps
minimize crosstalk and feed−through noise that may be
picked up by an unused switch.
Although used here, balanced supplies are not a
requirement. The only constraints on the power supplies are
that: VCC − GND = 2 to 6 volts
VEE − GND = 0 to −6 volts
VCC − VEE = 2 to 12 volts
and VEE ≤ GND
When voltage transients above VCC and/or below VEE are
anticipated on the analog channels, external Germanium or
Schottky diodes (Dx) are recommended as shown in Figure
16. These diodes should be able to absorb the maximum
anticipated current surges during clipping.
MC74HC4051A, MC74HC4052A, MC74HC4053A
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11
ANALOG
SIGNAL
Figure 15. Application Example Figure 16. External Germanium or
Schottky Clipping Diodes
a. Using Pull−Up Resistors b. Using HCT Interface
Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs
ON
6
7
8
16
+5V
-5V
ANALOG
SIGNAL
+5V
-5V
+5V
-5V
11
10
9
TO EXTERNAL CMOS
CIRCUITRY 0 to 5V
DIGITAL SIGNALS
ON/OFF
7
8
16
VCC
VEE
VEE
Dx
VCC
Dx
VEE
Dx
VCC
Dx
ANALOG
SIGNAL
ON/OFF
6
7
8
16
+5V
VEE
ANALOG
SIGNAL
+5V
VEE
+5V
VEE
11
10
9
R
*
R R
LSTTL/NMOS
CIRCUITRY
+5V
* 2K ≤ R ≤ 10K
ANALOG
SIGNAL
ON/OFF
6
7
8
16
+5V
VEE
ANALOG
SIGNAL
+5V
VEE
+5V
VEE
11
10
9
LSTTL/NMOS
CIRCUITRY
+5V
HCT
BUFFER
Figure 18. Function Diagram, HC4051A
13 X0
14 X1
15 X2
12 X3
1X4
5X5
2X6
4X7
3X
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
11
A
10
B
9
C
6
ENABLE
MC74HC4051A, MC74HC4052A, MC74HC4053A
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12
Figure 20. Function Diagram, HC4053A
Figure 19. Function Diagram, HC4052A
13 X1
12 X0
1Y1
2Y0
3Z1
5Z0
14 X
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
11
A
10
B
9
C
6
ENABLE
12 X0
14 X1
15 X2
11 X3
1Y0
5Y1
2Y2
4Y3
3Y
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
10
A
9
B
6
ENABLE
13 X
15 Y
4Z
MC74HC4051A, MC74HC4052A, MC74HC4053A
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13
ORDERING INFORMATION
Device Package Shipping†
MC74HC4051ADG SOIC−16
(Pb−Free)
48 Units / Rail
MC74HC4051ADR2G 2500 Units / Tape & Reel
NLV74HC4051ADR2G* 2500 Units / Tape & Reel
MC74HC4051ADWG SOIC−16 WIDE
(Pb−Free)
48 Units / Rail
MC74HC4051ADWR2G 1000 Units / Tape & Reel
NLVHC4051ADWR2G* 1000 Units / Tape & Reel
MC74HC4051ADTG TSSOP−16
(Pb−Free)
96 Units / Rail
MC74HC4051ADTR2G 2500 Units / Tape & Reel
NLVHC4051ADTR2G* 2500 Units / Tape & Reel
NLVHC4051AMNTWG*
(In Development) QFN16
(Pb−Free) 3000 Units / Tape & Reel
MC74HC4052ADG SOIC−16
(Pb−Free)
48 Units / Rail
MC74HC4052ADR2G 2500 Units / Tape & Reel
NLV74HC4052ADR2G* 2500 Units / Tape & Reel
MC74HC4052ADWG SOIC−16 WIDE
(Pb−Free) 48 Units / Rail
MC74HC4052ADWR2G 1000 Units / Tape & Reel
MC74HC4052ADTG
TSSOP−16
(Pb−Free)
96 Units / Rail
MC74HC4052ADTR2G 2500 Units / Tape & Reel
NLV74HC4052ADTR2G* 2500 Units / Tape & Reel
NLVHC4052ADTR2G* 2500 Units / Tape & Reel
NLVHC4052AMNTWG*
(In Development) QFN16
(Pb−Free) 3000 Units / Tape & Reel
MC74HC4053ADG SOIC−16
(Pb−Free)
48 Units / Rail
MC74HC4053ADR2G 2500 Units / Tape & Reel
NLV74HC4053ADR2G* 2500 Units / Tape & Reel
MC74HC4053ADWG
SOIC−16 WIDE
(Pb−Free)
48 Units / Rail
NLV74HC4053ADWRG* 1000 Units / Tape & Reel
MC74HC4053ADWR2G 1000 Units / Tape & Reel
NLV74HC4053ADWR2G* 1000 Units / Tape & Reel
MC74HC4053ADTG TSSOP−16
(Pb−Free)
96 Units / Rail
MC74HC4053ADTR2G 2500 Units / Tape & Reel
NLVHC4053ADTR2G* 2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
MC74HC4051A, MC74HC4052A, MC74HC4053A
www.onsemi.com
14
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F
ISSUE B
ÇÇÇ
ÇÇÇ
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
SECTION N−N
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
16X REFK
N
N
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MC74HC4051A, MC74HC4052A, MC74HC4053A
www.onsemi.com
15
PACKAGE DIMENSIONS
SOIC−16 WB
CASE 751G−03
ISSUE D
D
14X
B16X
SEATING
PLANE
S
A
M
0.25 B S
T
16 9
81
hX 45_
M
B
M
0.25
H8X
E
B
A
eT
A1
A
L
C
qNOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D10.15 10.45
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
q0 7
__
11.00
16X 0.58
16X
1.62 1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MC74HC4051A, MC74HC4052A, MC74HC4053A
www.onsemi.com
16
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
6.40
16X
0.58
16X 1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
16
89
8X
MC74HC4051A, MC74HC4052A, MC74HC4053A
www.onsemi.com
17
PACKAGE DIMENSIONS
QFN16, 2.5x3.5, 0.5P
CASE 485AW
ISSUE O
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
DIM MIN MAX
MILLIMETERS
A
A1 0.00 0.05
A3
b0.20 0.30
D2.50 BSC
D2 0.85 1.15
E3.50 BSC
E2
e0.50 BSC
K0.20 ---
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
0.20 REF
b
D2
L
PIN ONE
E2
1
8
15
10
D
E
B
A
C0.15
C0.15
2X
2X
e
2
16X
16X
0.10 C
0.05 C
A B
NOTE 3
A
16X
K
A1
(A3)
SEATING
PLANE
C0.08
C0.10
0.80 1.00
L0.35 0.45
1.85 2.15
L1
DETAIL A
L
ALTERNATE TERMINAL
CONSTRUCTIONS
L
ÇÇÇ
ÇÇÇ
ÉÉÉ
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
DETAIL B
*For additional information on our Pb−Free strategy and solderin
g
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
2.80
3.80
1.10
0.50
0.60
16X 0.30
16X
DIMENSIONS: MILLIMETERS
1
REFERENCE
TOP VIEW
SIDE VIEW
NOTE 4
C
0.15 C A B
0.15 C A B
DET AIL A
BOTTOM VIEW
e/2
L1 --- 0.15
2.10
PITCH
PACKAGE
OUTLINE
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