LF412 (AV national Semiconductor LF412 Low Offset, Low Drift Dual JFET Input Operational Amplifier General Description These devices are low cost, high speed, JFET input opera- tional amplifiers with very low input offset voltage and guar- anteed input offset voltage drift. They require low supply current yet maintain a large gain bandwidth product and fast slew rate. In addition, well matched high voltage JFET input devices provide very low input bias and oftset currents. LF 412 dual is pin compatible with the LM1558, allowing de- signers to immediately upgrade the overall performance of existing designs. These amplifiers may be used in applications such as high speed integrators, fast D/A converters, sample and hold circuits and many other circuits requiring low input offset voltage and drift, low input bias current, high input imped- ance, high slew rate and wide bandwidth. Features Internally trimmed offset voltage 1 mV (max) Input offset voltage drift 10 wV/C (max) Low input bias current 50 pA Low input noise current 0.01 pA/VHz 3 MHz (min) High slew rate Low supply current 10V/us (min) a o 2 s @ Wide gain bandwidth . a 1.8 mA/Amplifier a a High input impedance 10120 Low total harmonic distortion Ay = 10, S0.02% R= 10k, Vo= 20 Vp-p, BW= 20 Hz-20 kHz Bm Low 1/f noise corner 50 Hz m Fast settling time to 0.01% 2 ps Typical Connection Ordering Information Connection Diagrams a LF412XYZ oy X indicates electrical grade Y indicates temperature range M" for military Metal Can Package C for commercial ve Z_ indicates package type HY op NN DUTPUTA r OurpurB Ne INVERTING INVERTING INPUT A INPUT & NOW INVERTING NON. INVERTING -Vee (WPUT A INPUT & Y Simplified Schematic Note. Pin 4 comected to case 1/2 Dual Order Number LF412AMH, LF412MH, LF412CH or LF412MH/883* Yer O See NS Package Number HO8A Dual-In-Line Package Vo guTeuT A vt ~ + INVERTING INPUT A OUTPUT B NONANVERTING _3 ' INPUT A INVERTING INPUT B ve 4 NOWINVERTING INPUT B INTERNALLY INTERNALLY TRIMMED TOP VIEW TRIMME D TL/H/5656-1 Vee O= Available per JM38510/11905 Order Number LF412ACN, LF412CN or LF412MJ/883* See NS Package Number JO8A or NOSE 1-70Absolute Maximum Ratings If Mliitary/Aerospace specified devices are required, Distributors for availability and specifications. (Note 9) please contact the National Semiconductor Sales Office/ LF412A LF412 H Package N Package Supply Voltage +22V +18V Power Dissipation (Note 10) (Note 3) 670 mW Differential input Voltage +38V +30V. = Tj max 150C 115C {nput voltage Range 8jq (Typical) 152C/W 115C/W (Note 1) +19V +15V Operating Temp. Range (Note 4) (Note 4) Output Short Circuit Storage Temp. 65C<Ta<150C65C<Ta< 150C Ouration (Note 2) Continuous Continuous Range Lead Temp. (Soldering, 10 sec.) 260C 260C ESD Tolerance (Note 11) 1700V 1700V DC Electrical Characteristics (note 5) LF412A LF412 Symbol Parameter Conditions Units Min Typ | Max | Min Typ | Max Vos Input Offset Voltage Rg = 10 kf, Ta = 25C 0.5 1.0 1.0 3.0 mV AVos/AT | Average TC of Input Rg = 10 k (Note 6) Offset Voltage ? 10 7 20 | avec los Input Offset Current Vg= 15V Tj=25C 25 100 25 100 pA (Notes 5 and 7) J)=70C 2 2 nA Tj= 125C 25 25 nA \g Input Bias Current Vg= +15V Tp= 25C 50 200 50 200 pA (Notes 5 and 7) T= 70C 4 4 nA T= 125C 50 50 nA Rin Input Resistance T)= 25C 1012 1012 2 AVoL Large Signal Voltage | Vg= + 15V, Vo= +10V, Gain Ry = 2k, Ta= 25C 50 | 200 25 | 200 Vimv Over Temperature 25 200 16 200 V/mVv Vo Output Voltage Swing | Vg= + 15V, R, = 10k 413.6 12] +13.5 Vv Vom Input Common-Mode +16] +19.5 417 +145 v Voltage Range 165 115 Vv CMAR Common-Mode Rg <10k 80 4100 70 400 dB Rejection Ratio PSAR Supply Voltage (Note 8) 80 100 70 100 dB Rejection Ratio Is Supply Current Vo = OV,RL = 3.6 5.6 3.6 6.5 mA AC Electrical Characteristics (note 5) Symbol Parameter Conditions LFA12A LF412 Units Min Typ Max | Min Typ Max Amplifier to Amplifier Ta = 28C, f= 1 H2z-20 kHz _ _ Coupling (Input Referred) 120 120 aB SR Slew Rate Vg = 15V, Ta= 28C 10 15 8 15 V/us GBW Gain-Bandwidth Product | Vg= +15V, Ta=25C 4 2.7 4 MHz en Equivalent Input Noise Ta = 25C, Rg = 1000, 25 25 nvi\Hz Voltage f=1 kHz in Equivalent Input Noise Ta= 28C, f=1 kHz 0.01 0.01 pas iiz Current 1-71 ZedLF412 Note 1: Uniess otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voitage. Note 2: Any of the amplifier outputs can be shorted ta ground indefintaly, however, more than one should not be simultaneously shorted as the maximum junction temperature will be exceeded. Note 3: For operating at elevated temperature, these devices must be derated based on a thermal resistance of Oia. Note 4: These devices are available in both the commercial temperatura range 0C<Ta-. 70C and the military temperature range 55C <T,s 125C. The temperature range is designated by the position just before the package type in the device number. A 'C indicates the commercial temperature range and an M indicates the military temperature range. The military temperature range is available in 'H" package only. In all cases the maximum operating temperature is limited by internal junction temperature T) max. Note 5: Uniass otharwise specified, the specifications apply over the full temperature range and for Vs + 20V for the LF412A and for Vg= + 15V for the LF412. Vos, la. and Igs are measured at Von = 0. Note 6: The LF412A is 100% tasted to this specification. The LF412 is sample lested on a per amplifier basis to insure at least 65% of the amplifiers meet this specification. Note 7: The input bias currents are junction leakage currents which approximately double for every 10C increase in the junction temperature, Ty). Due to limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, Pp. T)=Ta+ %a Pp where 8), is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum. Note 8: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice, Vg = 6Vto +15V. Note 9: Alefar to RETS412X for LF412MH and LF412MJ military specifications. Note 10: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate outside guaranteed limits. Note 11: Human body madel. 1.5 kf in series with 100 pF. Typical Performance Characteristics a 10 20 30 40 OUTPUT SINK CURRENT (mA) 0 5 0 1% 20 2 SUPPLY VOLTAGE (+ ) Input Bias Current Input Bias Current Supply Current Vg = 15V Vem = OV s = T= 28C =z = +15V 3 2 i z z = 2 oa 3 = 199 = 2 Z 3 = E z z 10 3 1 ~ -5 Q 5 10 ~80-25 0 28 80 75 100 125 0 0 68 2 28 COMMON-MODE VOLTAGE (V) TEMPERATURE (C) SUPPLY VOLTAGE (+) Positive Common-Mode Negative Common-Mode Input Voltage Limit input Voltage Limit Positive Current Limit 23 | aetaths tase ~% eetzhs Wg 15V = 2 &=-2 % 3 g 3 10 g ri 15 4 -15 5S z 2 8 gw 8 g-10 E 2 Ee E Bros ze Zz 3 % 3 5 2 Q a 0 @ 5 10 18 2 2% oO -5 -@ -18 -2% -25 o 10 20 0 a POSITIVE SUPPLY NEGATIVE SUPPLY OUTPUT SOURCE CURRENT {mA} VOLTAGE (V) VOLTAGE () ; Negative Current Limit Output Voltage Swing Output Voltage Swing % = + 15V fi =2k Ta=25C 3 40 = - 55C r ~ 1D a Es gf g2 E z 126C] | 25C z z 20 oe o s 2 -5 a 3 E a - o g 1 Q a 01 1 10 A, DUTPUT LOAD (ki) TL/H/5856~2Typical Performance Characteristics (continued) UNITY GAIN COMMON-MODE REJECTION RATIO (dB) DISTORTION (%) SANOWIOTH (MHz) OPEN LOOP VOLTAGE GAIN (V/) 5.5 wa > w -~ wo on 3 2.5 -50-25 0 0.2 1M 10k Gain Bandwidth 2 50 75 100 125 TEMPERATURE (C) Distortion vs Frequency Vex t15 | | h=2ee tt 100 10 100 1k 10k FREQUENCY (Hz) 100k Common-Mode Rejection Ratio Vs= + 15V RL =2k Tas 25C ba CMAR = 20 LOG + + 0 | ~ OPEN LOOP VOLTAGE: - Ya NN GAIN [ Vom 2k tL 10 100 1k 10k 100K 1M 10M FREQUENCY (Hz) Open Loop Voltage Gain RL = 2k 58C s Tas 125C 5 10 18 2 SUPPLY VOLTAGE ( + V) DUTPUT VOLFAGE SWANG (Vp-p) OUTPUT IMPEDANCE (12) Bode Plot 01 10 FREQUENCY (MHz) Undistorted Output Voltage Swing x0 3 10 [s= +15 A =2k Ta= 28C Ay=? < 1% DIST 10k 100k 1M FREQUENCY {Hz} Power Supply Rejection Ratio Vg= + 15 W=2sre 10-100 tk Ss 10k FREQUENCY (Hz) 100k 14 Output impedance 100 1k 10 FREQUENCY (Hz) 100k 1 Slew Rate rs) a4 2 a 18 16 at te 12 | R aah 10 L ll -580~258 0 25 SO 75 100 125 TEMPERATURE (C) Open Loop Frequency 10 Response OPEN LOOP VOLTAGE GAIN (dB) 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz} Equivalent Input Nolse Voltage 2 22 5: zy 33 Ss ~ = 1 100k 10K FREQUENCY {Hz} 100% Inverter Settling Time OUTPUT VOLTAGE SWING FROM OV () 01 1 10 SETTLING TIME (us) TL/H/566-3LF412 Pulse Response pF, = 2 ko, c, = 10 pF Small Signal Inverting OUTPUT VOLTAGE SWING (50 av/DIV) TIME (0.2 us /DtV) Large Signal Inverting OUTPUT VOLTAGE SWING (5/01) nn TIME (2 us/DIV) Small Signal Non-Inverting Z f ae 25 E ws ME O.2 870M) Large Signal Non-Inverting OUTPUT VOLTAGE SWING (6v/0Ny) TIME (2 us/DIV) Current Limit (Ay = 1002) OUTPUT VOLTAGE SWING (VOY) Application Hints The LF412 series of JFET input dual op amps are internally trimmed (BI-FET IITM) providing very low input offset volt- ages and guaranteed input offset voltage drift. These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily be ac- commodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will cause a reversal of the phase to the output and force the amplifier output to the corresponding high or low state. TIME (5 8 /O1V) TL/H/5656~4 Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. in neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output, however, if both inputs exceed the limit, the output of the amplifier may be forced to a high state. The amplifiers will operate with a common-mode input volt- age equal to the positive supply; however, the gain band- width and slew rate may be decreased in this condition. When the negative common-mode voltage swings to within 3V of the negative supply, an increase in input offset voltage may occur, 1-74Application Hints (Continues) Each amplifier is individually biased by a zener reference which allows normal circuit operation on +6.0V power sup- plies. Supply voltages less than these may result in lower gain bandwidth and slew rate. The amplifiers will drive a 2 kf. load resistance to +10V over the full temperature range. If the amplifier is forced to drive heavier load currents, however, an increase in input offset voltage may occur on the negative voltage swing and finally reach an active current limit on both positive and neg- ative swings. Precautions should be taken to ensure that the power sup- ply for the integrated circuit never becomes reversed in po- larity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the result- ing forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in or- der to ensure stability. For example, resistors from the out- put to an input should be placed with the body close to the input to minimize pick-up and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel rasistance and capaci- tance from the input of the device (usually the inverting in- put) to AC ground set the frequency of the pole. In many instances the frequancy of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately 6 times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. 1-75 Zales)LF412 Typical Application Single Supply Sample and Hold INVERTER Vc 1=HOLO oH O=SAMPLE Detailed Schematic vec Om + - 13 4 arz as a4 au eT as } 5 RS | q 2 2 a 4 an a? J On fc a6 | pF 3 Re 1 } ea 33 7, Sas Pa avo oe > 20x yar au A 1, ay e 3 a ex Re " 52 no 4 o- TL/H/5656-9