_______________General Description
The MAX532 is a complete, dual, serial-input, 12-bit
multiplying digital-to-analog converter (MDAC) with out-
put amplifiers. No external user trims are required to
achieve full specified performance. The MAX532’s 3-
wire serial interface minimizes the number of package
pins, so it uses less board space than parallel-interface
parts. The interface is SPI™, QSPI™ and Microwire™
compatible. A serial output, DOUT, allows cascading
of two or more MAX532s and read-back of the data
written to the device.
The device’s serial interface minimizes digital-noise
feedthrough from its logic pins to its analog outputs.
Serial interfacing also simplifies opto-coupler-isolated
or transformer-isolated applications.
The MAX532 is specified with ±12V to ±15V power sup-
plies. All logic inputs are TTL and CMOS compatible. It
comes in space-saving 16-pin DIP and wide SO packages.
________________________Applications
Automatic Test Equipment
Arbitrary Waveform Generators
Programmable-Gain Amplifiers
Motion Control Systems
Servo Controls
____________________________Features
♦Two 12-Bit MDACs with Output Amplifiers
♦Fast, 6MHz 3-Wire Interface
♦SPI, QSPI, and Microwire Compatible
♦±12V Output Swing
♦±10mA Output Current
♦2.5µs Settling Time to ±1/2LSB
♦Guaranteed Monotonic Over Temperature
♦Low Integral Nonlinearity: ±1/2LSB Max
♦Low Gain Tempco: 2ppm/°C
♦Operates from ±12V to ±15V Supplies
♦Power-On Reset
♦Available in 16-Pin DIP and Wide SO Packages
______________Ordering Information
MAX532
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
________________________________________________________________
Maxim Integrated Products
1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VDD
LDAC
CS
DIN
AGNDA
VOUTA
VREFA
RFBA
TOP VIEW
DOUT
SCLK
DGND
VSS
RFBB
VREFB
VOUTB
AGNDB
DIP/Wide SO
MAX532
__________________Pin Configuration
DACA
LATCH
24-BIT SHIFT
REGISTER
DACB
LATCH
DACA
RFBA
VOUTA
DOUT
RFBB
VOUTB
AGNDB
AGNDA
VREFA
DIN
SCLK
CS
LDAC
VREFB
DACB
VDD
VSS DGND
MAX532
________________Functional Diagram
Call toll free 1-800-998-8800 for free samples or literature.
19-0046; Rev. 1; 3/94
PART TEMP. RANGE PIN-PACKAGE
MAX532ACPE 0°C to +70°C 16 Plastic DIP
MAX532BCPE 0°C to +70°C 16 Plastic DIP
MAX532ACWE 0°C to +70°C 16 Wide SO
MAX532BCWE 0°C to +70°C 16 Wide SO
MAX532BC/D 0°C to +70°C Dice*
™Microwire is a trademark of National Semiconductor Corp. SPI and QSPI are trademarks of Motorola, Inc.
±1/2
±1
±1/2
±1
±1
ERROR
(LSBs)
Ordering Information continued on last page.
* Contact factory for dice specifications.
MAX532
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
2 _______________________________________________________________________________________
Pin Voltages
VDD to DGND, AGNDA, AGNDB........................-0.3V to +17V
VSS to DGND, AGNDA, AGNDB (Note 1) ..........+0.3V to -17V
VREFA, VREFB.............................(VSS - 0.3V) to (VDD + 0.3V)
AGNDA, AGNDB.....................(DGND - 0.3V) to (VDD + 0.3V)
VOUTA, VOUTB...........................(VSS - 0.3V) to (VDD + 0.3V)
RFBA, RFBB.................................(VSS - 0.3V) to (VDD + 0.3V)
SCLK, DIN, DOUT, LDAC, CS ..(DGND - 0.3V) to (VDD + 0.3V)
DOUT Sink Current .............................................................20mA
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C) ..........842mW
Wide SO (derate 9.52mW/°C above +70°C)................762mW
CERDIP (derate 10.00mW/°C above +70°C)...............800mW
Operating Temperature Ranges:
MAX532_C__ ......................................................0°C to +70°C
MAX532_E__....................................................-40°C to +85°C
MAX532_MJE ................................................-55°C to +125°C
Junction Temperatures:
MAX532_C__, E__........................................................+150°C
MAX532_MJE...............................................................+175°C
Storage Temperature Range........................... -65°C to +160°C
Lead Temperature (soldering, 10sec)........................... +300°C
ELECTRICAL CHARACTERISTICS
(VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA and VREFB = +10V, RL= 2kΩ,
CL= 100pF, VOUT_ connected to RFB_, TA= TMIN to TMAX, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
PARAMETER CONDITIONS MIN TYP MAX UNITSSYMBOL
Resolution
INL
12 Bits
Relative Accuracy ±1 LSB
Differential Nonlinearity Guaranteed monotonic ±1 LSB
±1/2MAX532A
MAX532B
±2
TA= +25°C, MAX532_ ±3Zero-Code Offset Error DAC latch loaded
with all 0s ±4 mV
TA= TMIN to TMAX, MAX532B
±5 µV/°CDAC latch loaded with all 0s
±2MAX532A
TA= +25°C, DAC latch
loaded with all 1s ±5MAX532B
±0.5 ±3.0 %
81013kΩ
±2 ppm/°C
of FSR
Gain Error TA= TMIN to TMAX, DAC
latch loaded with all 1s ±7
LSB
MAX532B ±4MAX532A
TA= TMIN to TMAX, MAX532A
Zero-Code Offset
Temperature Coefficient
Gain-Error Temperature
Coefficient
VREFA, VREFB Input
Resistance
VREFA, VREFB Input
Resistance Matching
STATIC PERFORMANCE (Note 1)
REFERENCE INPUTS (VREFA, VREFB)
Note 1: If VSS is open-circuited with V DD and either AGND applied, the VSS pin will float positive, exceeding the Absolute Maximum Ratings.
A Schottky diode connected between V SS and GND ensures the maximum ratings will not be exceeded.
MAX532
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA and VREFB = +10V, RL= 2kΩ, CL= 100pF,
VOUT_ connected to RFB_, TA= TMIN to TMAX, unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITSSYMBOL
VINL
VOL
Input Low Voltage 0.8 V
ISINK = 5mA 0.08 0.4
Output Voltage Low ISINK = 16mA 0.2 V
VINH
Input High Voltage 2.4 V
Input Current Digital inputs at 0V or VDD ±1 µA
8 pFInput Capacitance (Note 2)
ILKG
Output High Leakage VDOUT = 0V to VDD ±10 µA
COUT 15 pF
DC Output Impedance 0.2 Ω
Short-Circuit Current VOUTA, VOUTB connected to AGNDA, AGNDB 20 mA
Output Voltage Swing V
VDD
Positive Supply Voltage 11.4 16.5 V
VSS
Negative Supply Voltage -11.4 -16.5 V
±0.035
PSRPower-Supply Rejection
±0.035
LSB/%
IDD
Positive Supply Current Output unloaded 510mA
ISS
Negative Supply Current Output unloaded 46mA
Settling time to within 1/2 LSB of final DAC value; DAC
latch alternately loaded with all 0s and all 1s 2.5 µs
Slew Rate 8 V/µs
DAC latch alternately loaded with 011...11 and 100...00 60 nV-s
Output High Capacitance
(Note 2)
∆Full scale/∆VDD, VDD = 11.4V to 16.5V, VREF = -8.9V,
DAC latches loaded with all 1s
∆Full scale/∆VSS, VSS = -11.4V to -16.5V, VREF = 8.9V,
DAC latches loaded with all 1s
VREFA to VOUTB -100
Channel-to-Channel
Isolation VREFB to VOUTA -100
dB
Voltage-Output
Settling Time
Digital-to-Analog
Glitch Impulse
VREFA = 20Vp-p 10kHz
sine wave; DAC latches
loaded with all 0s
VREFB = 20Vp-p 10kHz
sine wave; DAC latches
loaded with all 0s
(VDD - 2.5)
to
(VSS + 2.5)
DIGITAL INPUTS (SCLK, DIN,
LDAC
,
CS
)
DIGITAL OUTPUT (DOUT) (Note 3)
ANALOG OUTPUTS (VOUTA, VOUTB)
POWER REQUIREMENTS
AC CHARACTERISTICS
MAX532
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA and VREFB = +10V, RL= 2kΩ, CL= 100pF,
VOUT_ connected to RFB_, TA= TMIN to TMAX, unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITSSYMBOL
VREF = 100mVp-p sine wave;
DAC latch loaded with all 1s 1.0 MHz
VREF = 20Vp-p 10kHz sine wave;
DAC latch loaded with all 0s -77 dB
Full-Power Bandwidth 125 kHz
THDTotal Harmonic Distortion -90 dB
Output Noise Voltage 0.1Hz to 10Hz 2 µVRMS
Digital Crosstalk DACA code all 1s, DACB code transition from all 0s to all 1s 10 nV-s
Digital Feedthrough CS = 1; transitions on SCLK, LDAC, DIN 1.1 nV-s
PARAMETER
tCL
CONDITIONS MIN TYP MAX
SCLK Pulse Width Low
UNITSSYMBOL
fCLK
tCH 80 ns
tDS 50 ns
tCSS1
CS Rise to SCLK Rise Setup Time
SCLK Clock Frequency
50 ns
tCSS0
CS Fall to SCLK Rise Setup Time
6.25 MHz
50 ns
tDH
DIN to SCLK Rise Hold Time 0 ns
SCLK Pulse Width High 80 ns
Multiplying Feedthrough
Error
Unity-Gain Small-Signal
Bandwidth
VREF = 20Vp-p sine wave;
DAC latch loaded with all 1s
VREF = 6VRMS, 1kHz sine wave;
DAC latch loaded with all 1s
Note 1: Static performance tested at VDD = +15V, VSS = -15V. Performance over supplies guaranteed by PSR test.
Note 2: Guaranteed by design. Not subject to production testing.
Note 3: Open-drain output.
TIMING CHARACTERISTICS
(VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V) (Notes 4, 5)
tCSH0
SCLK Fall to CS Fall Hold Time 5 ns
tCSH1
SCLK Rise to CS Rise Hold Time 80 ns
tCSW
CS Pulse Width High 120 ns
tDO
SCLK Fall to DOUT Valid (Note 6) CL= 20pF, RPULL-UP = 1kΩto 5V 0 200 ns
tDV
CS Fall to DOUT Enable (Note 7) CL= 20pF, RPULL-UP = 1kΩto 5V 100 ns
tTR
CS Rise to DOUT Disable (Note 7) CL= 20pF, RPULL-UP = 1kΩto 5V 60 ns
tLDAC
LDAC Pulse Width Low 60 ns
tLDACS
CS Rise to LDAC Fall Setup Time 100 ns
DIN to SCLK Rise Setup Time
Note 4: All input signals are specified with tR= tF≤5ns. Logic input swing is 0V to 5V.
Note 5: See Figure 1.
Note 6: Timing is for SCLK fall to DOUT fall to 0.8V, or for SCLK fall to DOUT rise to 2.4V. Additional time must be added for any
larger passive RC pull-up delay.
Note 7: DOUT enable: DOUT falls to 4.5V from 5.0V. DOUT disable: DOUT rises to 0.5V from 0V.
MAX532
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
_________________________________________________________________________________________________
5
25
010 1k 10k
OUTPUT VOLTAGE SWING
vs. RESISTIVE LOAD
10
20
LOAD RESISTANCE (Ω)
VOUT (Vp-p)
100
15
5
VREF = 20Vp-p at 1kHz
010 100k
NOISE SPECTRAL DENSITY
100
300
FREQUENCY (Hz)
NOISE SPECTRAL DENSITY (nV Hz)
200
100 1k 10k
VREF = 0V
DAC CODE = 11...111
GAIN = -1
5
-40 100 10k 10M
LARGE-SIGNAL FREQUENCY RESPONSE
FREQUENCY (Hz)
GAIN (dB)
-5
0
-10
-15
-30
1k 100k 1M
VREF = 20Vp-p
DAC CODE = 11...111
GAIN = -1
-20
-25
-35
5
-25 100 10k 10M
SMALL-SIGNAL FREQUENCY RESPONSE
FREQUENCY (Hz)
GAIN (dB)
-5
0
-10
-15
-20
1k 100k 1M
VREF = 100mVp-p
DAC CODE = 11...111
-35
-85 1k 100k
MULTIPLYING FEEDTHROUGH ERROR
-75
FREQUENCY (Hz)
ATTENUATION (dB)
-65
-50
-45
-40
-55
-60
-70
-80
10k 1M
VREFA = 20Vp-p
VREFB = AGNDB
DAC CODE = 00...00
-94
-106 100 1k 10k
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (BANDWIDTH = 80kHz)
-102
FREQUENCY (Hz)
THD (dB)
-100
-98
-96
-104
VREF = 6VRMS
DAC CODE = 111...111
-60
-100 100 10k 100k
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (BANDWIDTH > 500kHz)
-75
-65
FREQUENCY (Hz)
THD (dB)
1k
-70
-90
-80
-85
-95
VREF = 6VRMS
DAC CODE = 111...111
__________________________________________Typical Operating Characteristics
(VDD = 15V, VSS = -15V, RL= 2kΩ, CL= 100pF, unless otherwise noted.)
MAX532
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
6 _______________________________________________________________________________________
______________________________________________________________Pin Description
A
AGNDA
A = VOUTA, 5V/div
TIMEBASE = 2µs/div
VREFA = ±10V SQUARE WAVE
LARGE-SIGNAL PULSE RESPONSE
____________________________Typical Operating Characteristics (continued)
(VDD = 15V, VSS = -15V, RL= 2kΩ, CL= 100pF, unless otherwise noted.)
PIN NAME FUNCTION
1RFBA Feedback Resistor for DACA
2 VREFA Reference Input for DACA
3 VOUTA Voltage Output for DACA
4 AGNDA Analog Ground for DACA
5 AGNDB Analog Ground for DACB
6 VOUTB Voltage Output for DACB
7 VREFB Reference Input for DACB
8 RFBB Feedback Resistor for DACB
9VSS Negative Supply Voltage
10 DGND Digital Ground
11 SCLK Serial Clock Input
12 DOUT Serial Data Output. Open-drain N-channel MOSFET output: requires external pull-up resis-
tor. Data on DOUT changes on the falling edge of SCLK. Serial output data is delayed 24
clock cycles from DIN.
13 DIN Serial Data Input. CMOS- and TTL-compatible input. Data is clocked into DIN on the rising
edge of SCLK. CS must be low for data to be clocked in.
16 VDD Positive Supply Voltage
15 LDAC Asynchronous Load DAC Input, active low. DAC latches are updated when CS is high and
LDAC is low.
14 CS Chip-Select Input, active low. Data is shifted in and out when CS is low. DAC latches are
updated when CS is high and LDAC is low.
A
AGNDA
A = VOUTA, 50mV/div
TIMEBASE = 2µs/div
VREFA = ±100mV SQUARE WAVE
SMALL-SIGNAL PULSE RESPONSE
MAX532
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
_______________________________________________________________________________________ 7
Figure 1. Timing Diagram
tCSHO tCH
tCSSO tCL
tDH
tDS
tDV tD0
tCSH1
tCSS1
tCSW
tLDACS
tTR
tLDAC
CS
SCLK
DIN
DOUT
LDAC
D0 D1
Q0 Q1
D23
Q23 D0
DACS
UPDATED
____________________________________________________________Timing Diagrams
MAX532
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
8 _______________________________________________________________________________________
Figure 2. 3-Wire Interface Timing Diagram (LDAC = DGND)
CS
SCLK
DIN
DOUT
D1 D0 ............................................
MSB DACB
MSB DACB FROM
PREVIOUS WRITE
MSB DACALSB DACB LSB DACA
MSB DACA FROM
PREVIOUS WRITE
D23 D16 D15 D14 D13 D12 D11..........
.....................................
Q22 Q16 Q15 Q14 Q13 Q12 Q11.......... Q1 Q0 D23 D23Q23
DACS
UPDATED
Figure 3. 4-Wire Inferface Timing Diagam
CS
SCLK
DIN
DOUT
LDAC
D1 D0 ............................................
MSB DACB
MSB DACB FROM
PREVIOUS WRITE
MSB DACALSB DACB LSB DACA
MSB DACA FROM
PREVIOUS WRITE
D23 D16 D15 D14 D13 D12 D11..........
...................................
Q22 Q16 Q15 Q14 Q13 Q12 Q11.......... Q1 Q0 D23 D23Q23
DACS
UPDATED
_______________________________________________Timing Diagrams (continued)
MAX532
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
_______________________________________________________________________________________ 9
Figure 4. Connections for Microwire
SCLK
DIN
DOUT
CS
LDAC
SK
SO
SI
I/O
I/O
MAX532
MICROWIRE
PORT
5V
1k
THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE
MAX532, BUT MAY BE USED FOR READ-BACK PURPOSES.
Figure 5. Connections for SPI
DOUT
DIN
SCLK
CS
LDAC
MISO
MOSI
SCK
I/O
I/O
MAX532
SPI
PORT
SS
5V
CPOL = 0,CPHA = 0
1k
THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX532,
BUT MAY BE USED FOR READ-BACK PURPOSES.
_______________Detailed Description
Digital Interface
The MAX532 is Microwire and SPI compatible (Figures
4 and 5). Both DACs are programmed by writing three
8-bit words (see Figures 2 and 3, and the
Functional
Diagram
). Serial data is clocked into the data registers
MSB first, with DACB information preceding DACA
information. Data is clocked in on the rising edge of
SCLK while CS is low. With CS high, data can not be
clocked into DIN, and DOUT is high impedance. SCLK
can be driven at rates up to 6.25MHz.
The MAX532 uses either a 3-wire or a 4-wire serial
interface. Three wires may be used (CS, DIN, SCLK)
by tying LDAC low. With LDAC low, the DACs are
updated simultaneously when CS goes high (see
Figure 2 and the
Functional Diagram
). The 3-wire inter-
face may be used if the MAX532 is used alone, or if two
or more MAX532s are cascaded (DOUT of one device
tied to DIN of the other) (Figure 6).
The 4-wire interface (LDAC, CS, DIN, SCLK) is required
if several serial devices are tied to the same data line,
and it is desirable to update them simultaneously
(Figure 7). With the 4-wire interface, the DACs are
updated when LDAC goes low (see Figure 3 and the
Functional Diagram
).
A serial output, DOUT, allows cascading of two or more
MAX532s and allows read-back of the data written to
the device’s 24-bit shift register. The data at DOUT is
delayed 24 clock cycles from the data at DIN (see
Figures 2 and 3, and the
Functional Diagram
). DOUT
is an open-drain N-channel MOSFET that requires an
external pull-up resistor (typically 1kΩif pulled up to
+5V, and 3kΩif pulled up to +12V or +15V). Logic lev-
els are guaranteed with sink currents up to 5mA (see
Electrical Characteristics
). Output data changes on the
falling edge of SCLK when CS is low. If CS is high,
DOUT is three-state (high-impedance).
Daisy-Chaining Devices
Any number of MAX532s can be daisy-chained by con-
necting the DOUT pin of one device (with a pull-up
resistor) to the DIN pin of the following device in the
chain (Figure 6).
When daisy-chaining devices, tCSS0 (CS low to SCLK
high), must be the greater of tDV + tDS or tDS + (tRC + tTR
- tCS), where tCSW is the CS pulse width used in the sys-
tem and the term (tRC + tTR - tCSW) accounts for the time
spent charging the DOUT capacitance with the external
pull-up resistor. So, for tRC < 250ns, tCSS0 is simply tDV
+ tDS. Calculate t RC using the following equation:
tRC = RPx C x ln (VPULL-UP/(VPULL-UP - 2.4V))
where VPULL-UP is the voltage that the pull-up resistor
is connected to, RPis the value of the pull-up resistor,
and C is the capacitance at DOUT. Values of tRC are
given in Table 1.
MAX532
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
10 ______________________________________________________________________________________
Figure 6. Daisy-chained or individual MAX532s are simultaneously updated by bringing CS high when using the 3-wire interface
(LDAC = DGND).
SCLK
DIN
CS
TO OTHER
SERIAL DEVICES
MAX532
SCLK
DIN
CS
DOUT
LDAC
+5V +5V +5V
RP
RP
1k 1k
MAX532
SCLK
DIN
CS
DOUT
LDAC
MAX532
SCLK
DIN
CS
DOUT
LDAC
SCLK
DIN
CS
MAX532
SCLK
DIN
CS LDAC
RP
1k
Figure 7. Multiple devices sharing a common DIN line may be simultaneously updated by bringing LDAC low. CS1, CS2, CS3, . . .,
are driven separately, thus controlling which data are written to devices 1, 2, 3, . . . .
CS
LDAC
SCLK
DIN
CS
LDAC
SCLK
DIN
MAX532
CS
LDAC
SCLK
DIN
TO OTHER
SERIAL DEVICES
MAX532
MAX532
DIN
SCLK
LDAC
CS1
CS2
CS3
With the values of tRC given in Table 1, tCSS0 is always
given by tDV + tDS. For different values of R or C, tRC
must be calculated to determine tCSS0.
Additionally, the maximum clock frequency is limited to
1
fCLK (max) = ————————————— .
2 x (tDO + tRC -15ns + tDS)
For example, with tRC = 15ns (5V ±10% supply with
1kΩpull-up), the maximum clock frequency is 2MHz.
Digital-to-Analog Section
Figure 8 shows a simplified circuit diagram for one of
the DACs and the output amplifier.
A segmented scheme is used to improve linearity,
whereby the two MSBs of the 12-bit data word are
decoded to drive the three switches, SA, SB, and SC.
The remaining ten bits drive the switches S0 through S9
in a standard R-2R ladder configuration.
Each of the switches, SA, SB, and SC, steers 1/4 of the
total reference current with the remaining 1/4 passing
through the R-2R section.
The output amplifier and feedback resistor perform the
current-to-voltage conversion, giving the following:
VOUT_ = -D x VREF_,
where _ denotes A or B, and D is the fractional representa-
tion of the digital word. (D can be set from 0 to 4095/4096.)
MAX532
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
______________________________________________________________________________________ 11
VPULL-UP (V) C (pF) RP(kΩ)t
RC (ns)
4.5 20 1 15
4.5 35 1 27
4.5 50 1 38
4.5 100 1 76
4.5 150 1 114
11.4 20 3 14
11.4 35 3 25
11.4 50 3 35
11.4 100 3 71
11.4 150 3 106
13.5 20 3 12
13.5 35 3 21
13.5 50 3 29
13.5 100 3 59
13.5 150 3 88
Table 1. t RC Delay Times
RR R
2R 2R 2R 2R 2R 2R 2R
SC SB SA S9 S8 S0 R/2 RFB_
VOUT_
AGND_
SHOWN FOR ALL 1s ON DAC
VREF_
Figure 8. Simplified D/A Circuit Diagram
DACA
AGNDAVSS
DGND
RFBA
VOUTA VOUT
VIN
-12V to -15V
VDD
VREFA
+12V to +15V
MAX532
Figure 9. Unipolar Binary Operation
MAX532
Output Amplifiers
The output amplifiers are stable with any combination
of resistive loads ≥2kΩand capacitive loads ≤100pF.
They are internally compensated, and settle to ±0.01%
FSR (1/2LSB) in 2.5µs.
Unipolar Configuration
Figure 9 shows DACA connected for unipolar binary
operation. Similar connections apply for DACB. When
VIN is an AC signal, the circuit performs two-quadrant
multiplication. Table 2 shows the codes for this circuit.
Bipolar Operation
Figure 10 shows the MAX532 connected for bipolar
operation. The coding is offset binary, as shown in
Table 3. When VIN is an AC signal, the circuit performs
four-quadrant multiplication. To maintain gain error
specifications, resistors R1, R2, and R3 should be ratio-
matched to 0.01%.
__________Applications Information
Layout, Grounding, and Bypassing
For best system performance, use printed circuit boards
with separate analog and digital ground planes. Wire-
wrap boards are not recommended. The two ground
planes should be tied together at the low-impedance
power-supply source, as shown in Figure 11.
The board layout should ensure that digital and analog
signal lines are kept separate from each other as much
as possible. Do not run analog and digital lines parallel
to one another.
The output amplifiers are sensitive to high-frequency
noise in the VDD and VSS power supplies. Bypass
these supplies to the analog ground plane with 0.1µF
and 10µF bypass capacitors. Minimize capacitor lead
lengths for best noise rejection.
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
12 ______________________________________________________________________________________
1111 1111 1111 -VIN x (4095/4096)
1000 0000 0000 -VIN x (2048/4096) = -1/2VIN
0000 0000 0001 -VIN x (1/4096)
0000 0000 0000 0V
DAC Latch Contents
Table 2. Unipolar Code Table
1LSB = VIN/4096
DAC_
AGND_ VSS
DGND
RFB_
VOUT_
VIN
-12V to -15V
VDD
VREF_
+12V to +15V
MAX532
VOUT
R1
20k
R2
20k
R3
10k
Figure 10. Bipolar Operation
VDD VSS AGNDA AGNDB DGND
MAX532
+15V -15V AGND +5V DGND
ANALOG
SUPPLY DIGITAL
SUPPLY
DIGITAL
CIRCUITRY
+5V DGND
Figure 11. Power-Supply Grounding
Table 3. Bipolar Code Table
DAC Latch Contents
1111 1111 1111 +VIN x (2047/2048)
1000 0000 0001 +VIN x (1/2048)
1000 0000 0000 0V
0111 1111 1111 -VIN x (1/2048)
1LSB = VIN/2048
0000 0000 0000 -VIN + (2048/2048) = -VIN
MSB LSB Analog Output, VOUT MSB LSB Analog Output, VOUT
MAX532
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
______________________________________________________________________________________ 13
DACA
AGNDA
VOUTA
MAX532
RFBA R/2
3
2
VREFA
1
VIN
4
R
2
4096
CODE
VOUT
VIN =-4096
CODE
VOUT
Figure 12. Programmable-Gain Amplifer
Programmable-Gain Amplifier (PGA)
The DAC/amplifier combination, along with access to
the feedback resistors, makes the MAX532 ideal as a
programmable-gain amplifier. In this application, the
DAC functions as a programmable resistor in the feed-
back loop. This type of configuration is shown in Figure
12, and is suitable for AC gain control. The DAC code
controls the gain for the PGA. As the code decreases,
the effective DAC resistance increases, and so the gain
also increases. The transfer function is given by:
VOUT/VIN = -REQA/RFBA,
where RFBA is the value of the feedback resistor (R/2),
and REQA is the effective DAC resistance controlled
by the digital input code:
R 4096
REQA = —— (————) ,
2 CODE
where CODE is the DAC code in decimal.
The transfer function is thus:
VOUT -4096
——— = ———
VIN CODE
The code may be programmed between 1 and (212 -1).
The zero code is not allowed, as it results in an open-
loop amplifier response.
Power-On Reset
On power-up, the internal DAC latches are set to
00 . . . . .00.
MAX532
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
14 ______________________________________________________________________________________
___________________Chip Topography
CS
DIN
SCLK
DOUT
VOUTA
AGNDA
AGNDB
VOUTB
VREFA RFBA VDD LDAC
DGND
VSS RFBB
VREFB VSS
0.250"
(6.35mm)
0.140"
(3.56mm)
TRANSISTOR COUNT: 1324;
SUBSTRATE CONNECTED TO VDD.
PART TEMP. RANGE PIN-PACKAGE
MAX532AEPE 16 Plastic DIP
MAX532BEPE -40° C t o + 85°C 16 Plastic DIP
MAX532AEWE -40°C to +85°C 16 Wide SO
-40° C t o + 85°C 16 Wide SO
MAX532AMJE 16 CERDIP**
ERROR
(LSBs)
±1/2
±1
±1/2
±1
±1/2
**Contact factory for availability and processing to MIL-STD-883B.
__Ordering Information (continued)
MAX532BMJE -5 5 ° C t o +125°C 16 CERDIP** ±1
-40°C to +85°C
MAX532BEWE -55°C to +125°C
MAX532
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
______________________________________________________________________________________ 15
________________________________________________________Package Information
C
AA2
E1
D
E
eA
eB
A3
B1
B
DIM
A
A1
A2
A3
B
B1
C
D
D1
E
E1
e
eA
eB
L
α
MIN
–
0.015
0.125
0.055
0.016
0.050
0.008
0.745
0.005
0.300
0.240
–
0.115
0˚
MAX
0.200
–
0.150
0.080
0.022
0.065
0.012
0.765
0.030
0.325
0.280
0.400
0.150
15˚
MIN
–
0.38
3.18
1.40
0.41
1.27
0.20
18.92
0.13
7.62
6.10
–
2.92
0˚
MAX
5.08
–
3.81
2.03
0.56
1.65
0.30
19.43
0.76
8.26
7.11
10.16
3.81
15˚
INCHES MILLIMETERS
2.54 BSC
7.62 BSC
0.100 BSC
0.300 BSC
A1
L
D1
e
21-587A
α16-PIN PLASTIC
DUAL-IN-LINE
PACKAGE
L
DIM
A
A1
B
C
D
E
e
H
h
L
α
MIN
0.093
0.004
0.014
0.009
0.398
0.291
0.394
0.010
0.016
0˚
MAX
0.104
0.012
0.019
0.013
0.413
0.299
0.419
0.030
0.050
8˚
MIN
2.35
0.10
0.35
0.23
10.10
7.40
10.00
0.25
0.40
0˚
MAX
2.65
0.30
0.49
0.32
10.50
7.60
10.65
0.75
1.27
8˚
INCHES MILLIMETERS
α
HE
D
e
A
A1 C
h x 45˚
0.127mm
0.004in.
B
1.27 BSC0.050 BSC
21-589B
16-PIN PLASTIC
SMALL-OUTLINE
(WIDE)
PACKAGE
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16
____________________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1994 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
MAX532
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
