S3C8478/C8475/P8475 1 PRODUCT OVERVIEW PRODUCT OVERVIEW SAM87RC PRODUCT FAMILY Samsung's new SAM87RC family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Timer/counters with selectable operating modes are included to support real-time operations. Many SAM87RC microcontrollers have an external interface that provides access to external memory and other peripheral devices. A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to one interrupt level at a time. S3C8478/C8475 MICROCONTROLLER The S3C8478/C8475 single-chip 8-bit microcontroller is designed for useful 10-bit resolution A/D converter, UART, PWM application field. Its powerful SAM87RC CPU architecture includes. The internal register file is logically expanded to increase the on-chip register space. The S3C8478/C8475 has 8/16K bytes of on-chip program ROM. Following Samsung's modular design approach, the following peripherals are integrated with the SAM87RC core: -- Large number of programmable I/O ports (42 SDIP: 34 pins, 44 QFP: 36 pins) -- One asynchronous UART module -- Analog-to-digital converter with eight input channels and 10-bit resolution -- One 8-bit basic timer for watchdog function -- One 8-bit timer/counter with three operating modes (Timer 0) -- One general-purpose 16-bit timer/counters with three operating modes (Timer 1) The S3C8478/C8475 is a versatile general-purpose microcontroller that is ideal for use in a wide range of electronics applications requiring complex timer/counter, PWM, capture, and UART. It is available in a 42-pin SDIP or 44-pin QFP package. OTP The S3C8475 is an OTP (One Time Programmable) version of the S3C8478/C8475 microcontroller. The S3C8475 microcontroller has an on-chip 16K-byte one-time-programmable EPROM instead of a masked ROM. The S3C8475 is comparable to the S3C8478/C8475, both in function in D.C. electrical characteristics and in pin configuration. 1-1 PRODUCT OVERVIEW S3C8478/C8475/P8475 FEATURES CPU UART * * One UART module * Full duplex serial I/O interface with three UART modes SAM87RC CPU core Memory * 272-byte general purpose register area * 8/16K-byte internal program memory A/D Converter * Eight analog input pins Instruction Set * 10-bit conversion resolution * 79 instructions * 20 s conversion time (10 MHz CPU clock) * IDLE and STOP instructions added for power-down modes Buzzer Frequency Output * 200 Hz to 20 kHz signal can be generated Instruction Execution Time * 333 ns at 12 MHz fOSC (minimum) Interrupts Oscillator Frequency * 1 MHz to 12 MHz external crystal oscillator * Maximum 12 MHz CPU clock * 14 interrupt sources and 14 vectors * Eight interrupt levels Operating Temperature Range * Fast interrupt processing * - 40C to + 85C General I/O Operating Voltage Range * Five I/O ports (total 36 pins) * * Four bit-programmable ports * Two n-channel open-drain output port Package Types * Timer/Counters * One 8-bit basic timer for watchdog function * One 8-bit timer/counter with three operating modes (timer 0) * One 16-bit general-purpose timer/counters with three operation modes (timer 1) 1-2 1.8 V to 5.5 V 42-pin SDIP, 44-pin QFP S3C8478/C8475/P8475 PRODUCT OVERVIEW BLOCK DIAGRAM Basic Timer XIN XOUT P0.0-P0.7 P1.0-P1.5 T0, T1CK, T1, BUZ, RxD, TxD Port 0 Port 1 OSC T0(CAP) T0(PWM) Timer 0 T1(CAP) T1(PWM) Timer 1 Port I/O and Interrupt Control Port 2 P2.0-P2.7 INT0-INT7 Port 3 P3.0-P3.7 ADC0-ADC7 SAM87RC CPU ADC0-ADC7 ADC P1.4/RxD P1.5/TxD UART P1.3/BUZ P4.0-P4.3 BUZ 8/16-Kbyte ROM 272-byte Register File Port 4 P4.4-P4.5 Figure 1-1. Block Diagram 1-3 PRODUCT OVERVIEW S3C8478/C8475/P8475 PIN ASSIGNMENTS P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P4.3 P4.2 VDD VSS XOUT XIN TEST P4.1 P4.0 RESET P2.0/INT0 P2.1/INT1 P2.2/INT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S3C8478 S3C8475 42-SDIP (Top-View) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P1.0/T0 (CAP/PWM) P1.1/T1CK P1.2/T1 (CAP/PWM) P1.3/BUZ P1.4/RxD P1.5/TxD P3.7/ADC7 P3.6/ADC6 P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS AVREF P2.7/INT7 P2.6/INT6 P2.5/INT5 P2.4/INT4 P2.3/INT3 Figure 1-2. Pin Assignment Diagram (42-Pin SDIP Package) 1-4 PRODUCT OVERVIEW 44 43 42 41 40 39 38 37 36 35 34 P4.4 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0/T0(CAP/PWM) P1.1/T1CK P1.2/T1(CAP/PWM) P1.3/BUZ S3C8478/C8475/P8475 1 2 3 4 5 6 7 8 9 10 11 S3C8478 S3C8475 44-QFP (Top-View) 33 32 31 30 29 28 27 26 25 24 23 P1.4/RxD P1.5/TxD P3.7/ADC7 P3.6/ADC6 P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS RESET P2.0/INT0 P2.1/INT1 P2.2/INT2 P2.3/INT3 P2.4/INT4 P2.5/INT5 P2.6/INT6 P2.7/INT7 P4.5 AVREF 12 13 14 15 16 17 18 19 20 21 22 P0.1 P0.0 P4.3 P4.2 VDD VSS XOUT XIN TEST P4.1 P4.0 Figure 1-3. Pin Assignment Diagram (44-Pin QFP Package) 1-5 PRODUCT OVERVIEW S3C8478/C8475/P8475 Table 1-1. S3C8478/C8475 Pin Descriptions Pin Name Pin Type P0.0-P0.7 I/O P1.0-P1.5 Circuit Number Pin Number Share Pins Nibble-programmable I/O port for Schmitt trigger input or push-pull, open-drain output. Pull-up resistors are assignable by software. E 8-1 (2-1, 43-38) - I/O Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors are assignable by software. Port 1 pin can also by used as alternative function (T0, T1CK, T1, BUZ, RxD, TxD) D 42-37 (37-32) T0, T1CK, T1, BUZ, RxD, TxD P2.0-P2.7 I/O Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors are assignable by software. Port 2 pins can also be used as external interrupt. D 19-26 (13-20) INT0INT7 P3.0-P3.7 I/O Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors are assignable by software. Port 3 pins can also be used as A/D converter by software. F 29-36 (24-31) ADC0ADC7 P4.0-P4.3 I/O Bit-programmable I/O port for Schmitt trigger input or push-pull, open-drain output. Pull-up resistors are assingable by software. E 17-16, 10-9 (11-10, 4-3) - P4.4-P4.5 O Push-pull output only C (44, 21) - XIN, XOUT - Crystal or ceramic oscillator signal for system clock. - 14, 13 (8, 7) - RESET I System reset signal input pin. B 18 (12) - TEST I Test signal input pin (for factory use only; muse be connected to VSS) - 15 (9) - AVREF, AVSS - A/D converter reference voltage input and ground - 27, 28 (22, 23) - VDD, VSS - Voltage input pin and ground - 11, 12 (5, 6) - Timer 0 capture input or PWM output pin D 42 (37) P1.0 Timer 1 external clock input pin D 41 (36) P1.1 T0 T1CK I/O I Pin Description T1 I/O Timer 1 capture input or PWM output pin D 40 (35) P1.2 BUZ O 200Hz-20kHz frequency output for buzzer sound D 39 (34) P1.3 RxD I/O UART receive and transmit input or output D 38 (33) P1.4 TxD O UART transmit output D 37 (32) P1.5 INT0-INT7 I External interrupt input E 19-26 (13-20) P2.0-P2.7 ADC0ADC7 I A/D converter input F 29-36 (24-31) P3.0-P3.7 NOTE: Pin numbers shown in parentheses "( )" are for the 44-pin QFP package. 1-6 S3C8478/C8475/P8475 PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS VDD VDD P-Channel P-Channel Data In Out N-Channel N-Channel Output DIsable Figure 1-4. Pin Circuit Type A Figure 1-6. Pin Circuit Type C VDD VDD Pull-Up Resistor Pull-up Enable Data In Output DIsable Circuit Type C In/Out Schmitt Trigger Data Figure 1-5. Pin Circuit Type B Figure 1-7. Pin Circuit Type D 1-7 PRODUCT OVERVIEW S3C8478/C8475/P8475 VDD PNE 47 K VDD Pull-up Enable P-CH In/Out Data N-CH Output DIsable Schmitt Trigger Figure 1-8. Pin Circuit Type E VDD Pull-up Enable Data Output DIsable Circuit Type C Data TO ADC Figure 1-9. Pin Circuit Type F 1-8 In/Out S3C8478/C8475/P8475 14 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this chapter, S3C8478/C8475 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: -- Absolute maximum ratings -- Input/output capacitance -- D.C. electrical characteristics -- A.C. electrical characteristics -- Oscillation characteristics -- Oscillation stabilization time -- Data retention supply voltage in stop mode -- UART timing characteristics in mode 0 -- A/D converter electrical characteristics 14-1 ELECTRICAL DATA Table A 1. Absolute Maximum Ratings = 25 C) Parameter Supply Voltage Symbol Conditions Rating Unit VDD - - 0.3 to + 6.5 V Input Voltage VI All ports - 0.3 to VDD + 0.3 V Output Voltage VO All output ports - 0.3 to VDD + 0.3 V Output Current High I OH One I/O pin active - 18 mA All I/O pins active - 60 One I/O pin active + 30 Total pin current for ports 1, 2, and 3 + 100 Total pin current for ports 0 and 4 + 200 Output Current Low Operating Temperature Storage Temperature 14-2 I OL mA TA - - 40 to + 85 C TSTG - - 65 to + 150 C S3C8478/C8475/P8475 ELECTRICAL DATA Table 14-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input High Voltage Symbol VIH1 Output High Typ Max Unit 0.8 VDD - VDD V - 0.2 VDD V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VIL3 Ports 0, 1, 2, 3, 4 and RESET XIN and XOUT VOH IOH = - 1 mA VDD = 4.5 to 5.5 V VDD-1.0 - - VDD = 4.5 to 5.5 V - 0.4 2.0 V 0.4 2.0 V - 1 uA VIL1 Voltage Output Low Voltage Min Ports 0, 1, 2, 3 ,4 and RESET XIN, and XOUT VIH3 Input Low Voltage Test Conditions VDD-0.1 - 0.1 Ports 0, 1, 2, 3, 4 VOL1 IOL = 15 mA Port 0, and 4 VOL2 IOL = 4 mA VDD = 4.5 to 5.5 V Ports 1, 2, and 3 ILIH1 All input pins except VIN = VDD ILIH2 and RESET ILIH2 XIN, and XOUT ILIL1 All input pins except VIN = 0 V ILIL2 ILIL2 XIN, and XOUT VIN = 0 V Output High Leakage Current ILOH All output pins VOUT = VDD - - 2 uA Output Low Leakage Current ILOL All output pins VOUT = 0 V - - -2 uA Pull-up Resistor RP1 VIN = 0 V, Ports 0-4 VDD = 5 V 30 47 70 K RP1 RESET VDD = 5 V 100 200 350 IDD1 RUM mode 12 MHz CPU clock VDD = 4.5 to 5.5 V - 10 20 3 MHz CPU clock VDD = 1.8 to 2.2 V 1.1 3 Idle mode 12 MHz CPU clock VDD = 4.5 to 5.5 V 4 8 3 MHz CPU clock VDD = 1.8 to 2.2 V 0.6 1.5 Stop mode VDD = 4.5 to 5.5 V 0.1 5 0.1 3 Input High Leakage Current Input Low Leakage Current Supply Current IDD2 IDD3 - VIN = VDD VDD = 1.8 to 2.2 V 20 - - -1 uA - 20 - - mA uA 14-3 ELECTRICAL DATA S3C8478/C8475/P8475 Table 14-3. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 4.5 V to 5.5 V) Parameter Interrupt Input High, Low Width RESET Input Low Width Symbol Conditions Min Typ Max Unit tINTH, tINTL Ports 2 VDD = 5 V 10 % - 200 - ns tRSL Input VDD = 5 V 10 % - 1 - s tINTL tINTH tRST 0.8 VDD 0.2 VDD Figure 14-1. Input Timing Measurement Points 14-4 S3C8478/C8475/P8475 ELECTRICAL DATA Table 14-4. Oscillation Characteristics (TA = - 40 C + 85 C) Oscillator Clock Circuit Test Condition Min Typ Max Unit 1 - 12 MHz Main Crystal or VDD = 4.5 V to 5.5 V Ceramic VDD = 2.7 V to 4.5 V 8 VDD = 1.8 V to 2.7 V 3 XIN XOUT C1 C2 External Clock VDD = 4.5 V to 5.5 V (Main System) VDD = 2.7 V to 4.5 V 8 VDD = 1.8 V to 2.7 V 3 XIN XOUT 1 - 12 MHz 14-5 ELECTRICAL DATA S3C8478/C8475/P8475 Main Oscillator Frequency (Divided by 4) CPU Clock 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz 2 MHz 1 2 3 4 5 6 7 1.8 V 2.7 V Supply Voltage (V) CPU clock = 1/n x oscillator frequency (n = 4, 8 or 64) Figure 14-2. Operating Voltage Range Table 14-5. Oscillation Stabilization Time (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Test Condition Min Typ Max Unit Main Crystal f OSC > 1.0 kHz; - - 20 ms Main Ceramic Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. - - 10 ms External Clock (Main System) XIN input High and Low width (tXH, tXL) 25 - 500 ns Oscillator tWAIT when released by a reset (1) - 216/fOSC - ms Stabilization Wait Time tWAIT when released by an interrupt (2) - - - ms NOTES: 1. fOSC is the oscillator frequency. 2. The duration of the oscillator stabilization wait time, tWAIT, when it is released by an interrupt is determined by the settings in the basic timer control register, BTCON. 14-6 S3C8478/C8475/P8475 ELECTRICAL DATA Table 14-6. UART Timing Characteristics in Mode 0 (10 MHz) (TA = - 40C to + 85C, VDD = 1.8 V to 5.5 V, Load capacitance = 80 pF) Parameter Symbol Min Typ Max Unit tSCK 500 tCPU x 6 700 ns Output data setup to clock rising edge tS1 300 tCPU x 5 - Clock rising edge to input data valid tS2 - - 300 Output data hold after clock rising edge tH1 tCPU - 50 tCPU - Input data hold after clock rising edge tH2 0 - - Serial port clock High, Low level width tHIGH, tLOW 200 tCPU x 3 400 Serial port clock cycle time NOTES: 1. All timings are in nanoseconds (ns) and assume a 10-MHz CPU clock frequency. 2. The unit tCPU means one CPU clock period. tHIGH 0.8 V DD 0.2 V DD t LOW t SCK Figure 14-3. Waveform for UART Timing Characteristics 14-7 SHIFT CLOCK DATA OUT DATA IN NOTE: tS1 D0 tSCK VALID tH1 tS2 D1 VALID t H2 D2 VALID VALID D3 tH1 tS2 tS1 tSCK Input data hold after clock rising edge Output data hold after clock rising edge Clock rising edge to input data valid Output data setup to clock rising edge Serial port clock cycle time The symbols shown in this diagram are defined as follows: tH2 D4 VALID D5 VALID D6 VALID D7 VALID 14-8 S3C8478/C8475/P8475 ELECTRICAL DATA Figure 14-4. A.C. Timing Waveform for the UART Module S3C8478/C8475/P8475 ELECTRICAL DATA Table 14-7. Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Symbol Conditions Data Retention Supply Voltage VDDDR Stop mode Data Retention Supply Current IDDDR Stop mode, VDDDR = 1.8 V Min Typ Max Unit 1.8 - 5.5 V - 0.1 5 A NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads. RESET occurs ~ ~ Oscillation Stabilzation Time Stop Mode Data Retention Mode ~ ~ VDD Normal Operating Mode VDDDR Execution of STOP Instrction RESET tWAIT NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC. Figure 14-5. Stop Mode Release Timing When Initiated by a Reset VOUT VDD A = 0.2 VDD B = 0.4 VDD C = 0.6 VDD D = 0.8 VDD VSS A B C D VIN Figure 14-6. Schmitt Trigger Input Characteristics 14-9 ELECTRICAL DATA S3C8478/C8475/P8475 Table 14-8. A/D Converter Electrical Characteristics (TA = - 40C to + 85C, VDD = 2.7 V to 5.5 V, VSS = 0 V) Parameter Symbol Test Conditions VDD = 5.12 V Min Typ Max Unit - - 3 LSB Total accuracy - Integral linearity error ILE CPU clock = 8 MHz AVREF = 5.12 V - 2 Differential linearity error DLE AVSS = 0 V - 1 Offset error of top EOT 1 3 Offset error of bottom EOB 1 2 Conversion time (1) tCON 20 - - s Analog input voltage VIAN - AVSS - AVREF V Analog input impedance RAN - 2 - - M ADC reference voltage AVREF - 2.5 - VDD V ADC reference ground AVSS - VSS - VSS + 0.3 V Analog input current IADIN AVCC = VCC = 5 V - - 10 A Analog block current (2) IADC AVCC = VCC = 5 V - 1 3 mA AVCC = VCC = 3 V 0.5 1.5 AVCC = VCC = 5 V power down mode 100 500 f OSC = 10 MHz (3) NOTES: 1. "Conversion time" is the time required from the moment a conversion operation starts until it ends. 2. IADC is operating current during A/D conversion. 3. fOSC is the main oscillator clock. 14-10 nA S3C8478/C8475/P8475 ELECTRICAL DATA Digital Output 11 1111 1111 11 1111 1110 11 1111 1101 . . . . . 00 0000 0010 00 0000 0001 00 0000 0000 AVSS VEOB Analog Input V2 V(K-1) V(K) VEOT AVREF 1LSB = (VEOT-VEOB)/1022 DLE(K) = {(V(K)-V(K-1))-1LSB}/1LSB ILE(K) = {V(K)-(1LSB x K + VEOB)}/1LSB DLE = MAX{DLE(K)} ILE = MAX{ILE(K)} Figure 14-7. Definition of DLE and ILE 14-11 S3C8478/C8475/P8475 15 MECHANICAL DATA MECHANICAL DATA OVERVIEW This section contains the following information about the device package: -- Package dimensions in millimeters -- Pad diagram #22 0.2 5 42-SDIP-600 +0 - 0 .1 .05 0-15 15.24 14.00 0.2 #42 0.50 0.1 (1.77) NOTE: 1.00 0.1 1.778 5.08 MAX 39.10 0.2 3.30 0.3 39.50 MAX 3.50 0.2 #21 0.51 MIN #1 Dimensions are in millimeters. Figure 15-1. 42-SDIP-600 Package Dimensions 15-1 MECHANICAL DATA S3C8478/C8475/P8475 13.20 0.3 0-8 10.00 0.2 10.00 0.2 + 0.10 - 0.05 0.10 MAX 44-QFP-1010 0.80 0.20 13.20 0.3 0.15 #44 #1 + 0.10 0.35 - 0.05 0.80 0.05 MIN (1.00) 2.05 0.10 2.30 MAX NOTE: Dimensions are in millimeters. Figure 15-2. 44-QFP-1010 Package Dimensions 15-2 S3C8478/C8475/P8475 16 S3P8475 OTP S3P8475 OTP OVERVIEW The S3P8475 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C8478/C8475 microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is accessed by serial data format. The S3P8475 is fully compatible with the S3C8478/C8475, both in function in D.C. electrical characteristics and in pin configuration. Because of its simple programming requirements, the S3P8475 is ideal as an evaluation chip for the S3C8478/C8475. P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 SDAT/P4.3 SCLK/P4.2 VDD/VDD VSS/VSS XOUT XIN VPP/TEST P4.1 P4.0 RESET/RESET RESET P2.0/INT0 P2.1/INT1 P2.2/INT2 NOTE: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S3P8475 (42-SDIP) Top-View 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P1.0/T0(CAP/PWM) P1.1/T1CK P1.2/T1(CAP/PWM) P1.3/BUZ P1.4/RxD P1.5/TxD P3.7/ADC7 P3.6/ADC6 P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS AVREF P2.7/INT7 P2.6/INT6 P2.5/INT5 P2.4/INT4 P2.3/INT3 The bolds indicate an OTP pin name. Figure 16-1. S3P8475 Pin Assignments (42-SDIP Package) 16-1 S3C8478/C8475/P8475 44 43 42 41 40 39 38 37 36 35 34 P4.4 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0/T0(CAP/PWM) P1.1/T1CK P1.2/T1(CAP/PWM) P1.3/BUZ S3P8475 OTP 1 2 3 4 5 6 7 8 9 10 11 S3P8475 (44-QFP) Top-View 33 32 31 30 29 28 27 26 25 24 23 P1.4/RxD P1.5/TxD P3.7/ADC7 P3.6/ADC6 P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS RESET/RESET RESET P2.0/INT0 P2.1/INT1 P2.2/INT2 P2.3/INT3 P2.4/INT4 P2.5/INT5 P2.6/INT6 P2.7/INT7 P4.5 AVREF 12 13 14 15 16 17 18 19 20 21 22 P0.1 P0.0 SDAT/P4.3 SCLK/P4.2 VDD/VDD VSS/VSS XOUT XIN VPP/TEST P4.1 P4.0 NOTE: The bolds indicate an OTP pin name. Figure 16-2. S3P8475 Pin Assignments (44-QFP Package) 16-2 S3C8478/C8475/P8475 S3P8475 OTP Table 16-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function P4.3 SDAT 9(3) I/O P4.2 SCLK 10(4) I Serial clock pin. Input only pin. TEST VPP 14(16) I Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is aplied, OTP is in reading mode. (Option) RESET RESET 18(12) I Chip Initialization VDD/VSS VDD/VSS 11(5)/12(6) - Logic power supply pin. VDD should be tied to +5 V during programming. Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. NOTE: ( ) means 44 QFP package. Table 16-2. Comparison of S3C8475 and S3C8478/C8475 Features Characteristic S3C8475 S3C8478/C8475 Program Memory 16-Kbyte EPROM 8/16-Kbyte mask ROM Operating Voltage (VDD) 1.8 V to 5.5 V 1.8 V to 5.5 V OTP Programming Mode VDD = 5 V, VPP (EA) = 12.5 V Pin Configuration 42 SDIP/44 QFP 42 SDIP/44 QFP EPROM Programmability User Program 1 time Programmed at the factory OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (TEST) pin of the S3C8475, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 16-3 below. Table 16-3. Operating Mode Selection Criteria VDD VPP (TEST) REG/ MEM ADDRESS (A15-A0) R/W MODE 5V 5V 0 0000H 1 EPROM read 12.5 V 0 0000H 0 EPROM program 12.5 V 0 0000H 1 EPROM verify 12.5 V 1 0E3FH 0 EPROM read protection NOTE: "0" means Low level; "1" means High level. 16-3