25AA1024/25LC1024 1 Mbit SPITM Bus Serial Flash Device Selection Table Part Number VCC Range Page Size Temp. Ranges Packages 25LC1024 2.5-5.5V 256 Byte I,E P, SM, MF 25AA1024 1.8-5.5V 256 Byte I P, SM, MF Features Description * Max. clock 20 MHz * Flash and byte-level serial EEPROM operation * Low-power CMOS technology - Max. Write Current: 5 mA at 5.5V, 20 MHz - Read Current: 10 mA at 5.5V, 20 MHz - Standby Current: 1A at 5.5V (Deep powerdown) * 131,072 x 8-bit organization * Byte and Page (256 byte page) Write Operations (5 ms max.) * Electronic Signature for device ID * Self-timed ERASE and WRITE cycles - Sector Erase (1 second/sector typical) - Bulk Erase (2 seconds typical) * Sector write protection (32K byte/sector) - Protect none, 1/4, 1/2 or all of array * Built-in write protection - Power-on/off data protection circuitry - Write enable latch - Write-protect pin * High reliability - Endurance: 100,000 erase/write cycles * Temperature ranges supported; - Industrial (I): -40C to +85C - Automotive (E): -40C to +125C The Microchip Technology Inc. 25AA1024/25LC1024 (25XX1024*) is a 1024 Kbit serial reprogrammable Flash memory with both Flash and byte-level serial EEPROM functions. The memory is accessed via a simple Serial Peripheral InterfaceTM (SPITM) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled by a Chip Select (CS) input. The 25XX1024 is available in standard packages including 8-lead PDIP and SOIC, and advanced 8-lead DFN package. Pb-free (Pure Sn) finish is also available. Package Types (not to scale) (MF) CS 1 VSS 4 Name Function CS Chip Select Input SO Serial Data Output WP Write-Protect VSS Ground SI Serial Data Input SCK Serial Clock Input HOLD Hold Input VCC Supply Voltage 2003 Microchip Technology Inc. (P, SM) 8 VCC 7 HOLD 6 SCK 5 SI CS SO 1 2 WP VSS 3 4 25LC1024 SO 2 WP 3 Pin Function Table PDIP/SOIC DFN 25LC1024 * Standard and Pb-free packages available Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. 8 7 VCC HOLD 6 SCK SI 5 SPI is a registered trademark of Motorola Semiconductor. *25XX1024 is used in this document as a generic part number for the 25AA1024, 25LC1024 devices. Preliminary DS21836A-page 1 25AA1024/25LC1024 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings () VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature .................................................................................................................................-65C to 150C Ambient temperature under bias ...............................................................................................................-40C to 125C ESD protection on all pins ..........................................................................................................................................4 kV NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Param. No. Sym. Characteristic TA = -40C to +85C TA = -40C to +125C Industrial (I): Automotive (E): Min. Max. Units VCC = 1.8V to 5.5V VCC = 2.5V to 5.5V Test Conditions D001 VIH1 High-level input voltage .7 VCC VCC +1 V Low-level input voltage -0.3 0.3 VCC V VCC 2.7V -0.3 0.2 VCC V VCC < 2.7V Low-level output voltage -- 0.4 V IOL = 2.1 mA -- 0.2 V IOL = 1.0 mA, VCC < 2.5V VCC -0.5 -- V IOH = -400 A D002 VIL1 D003 VIL2 D004 VOL D005 VOL D006 VOH High-level output voltage D007 ILI Input leakage current 1 A CS = VCC, VIN = VSS TO VCC D008 ILO Output leakage current 1 A CS = VCC, VOUT = VSS TO VCC D009 CINT Internal capacitance (all inputs and outputs) -- 7 pF TA = 25C, CLK = 1.0 MHz, VCC = 5.0V (Note) D010 ICC Read -- -- 10 mA 5 mA VCC = 5.5V; FCLK = 20.0 MHz; SO = Open VCC = 2.5V; FCLK = 10.0 MHz; SO = Open -- -- 5 3 mA mA VCC = 5.5V VCC = 2.5V -- -- 20 A 10 A CS = VCC = 5.5V, Inputs tied to VCC or VSS, 125C CS = VCC = 5.5V, Inputs tied to VCC or VSS, 85C 1 A Operating current D011 ICC Write D012 ICCS Standby current D13 Note: ICCSPD Deep power-down current -- CS = VCC = 5.5V, Inputs tied to VCC or VSS This parameter is periodically sampled and not 100% tested. DS21836A-page 2 Preliminary 2003 Microchip Technology Inc. 25AA1024/25LC1024 TABLE 1-2: AC CHARACTERISTICS Param. No. Sym TA = -40C to +85C TA = -40C to +125C Industrial (I): Automotive (E): AC CHARACTERISTICS Characteristic VCC = 1.8V TO 5.5V VCC = 2.5V to 5.5V Min Max Units Conditions -- -- -- 20 10 2 MHz MHz MHz 4.5 VCC 5.5 2.5 VCC < 4.5 1.8 VCC < 2.5 1 FCLK Clock frequency 2 TCSS CS setup time 25 50 250 -- -- -- ns ns ns 4.5 VCC 5.5 2.5 VCC < 4.5 1.8 VCC < 2.5 3 TCSH CS hold time 50 100 500 -- -- -- ns ns ns 4.5 VCC 5.5 2.5 VCC < 4.5 1.8 VCC < 2.5 (Note 3) 4 TCSD CS disable time 50 -- ns 5 Tsu Data setup time 5 10 50 -- -- -- ns ns ns 4.5 VCC 5.5 2.5 VCC < 4.5 1.8 VCC < 2.5 6 THD Data hold time 10 20 100 -- -- -- ns ns ns 4.5 VCC 5.5 2.5 VCC < 4.5 1.8 VCC < 2.5 7 TR CLK rise time -- 20 ns (Note 1) 8 TF CLK fall time -- 20 ns (Note 1) 9 THI Clock high time 25 50 250 -- -- -- ns ns ns 4.5 VCC 5.5 2.5 VCC < 4.5 1.8 VCC < 2.5 10 TLO Clock low time 25 50 250 -- -- ns ns ns 4.5 VCC 5.5 2.5 VCC < 4.5 1.8 VCC < 2.5 11 TCLD Clock delay time 50 -- ns 12 TCLE Clock enable time 50 -- ns 13 TV Output valid from clock low -- -- -- 25 50 250 ns ns ns 4.5 VCC 5.5 2.8 VCC < 4.5 1.8 VCC < 2.5 14 THO Output hold time 0 -- ns (Note 1) 15 TDIS Output disable time -- -- -- 25 50 250 ns ns ns 4.5 VCC 5.5 2.5 VCC < 4.5 1.8 VCC < 2.5 (Note 1) 16 THS HOLD setup time 10 20 100 -- -- -- ns ns ns 4.5 VCC 5.5 2.5 VCC < 4.5 1.8 VCC < 2.5 17 THH HOLD hold time 10 20 100 -- -- -- ns ns ns 4.5 VCC 5.5 2.5 VCC < 4.5 1.8 VCC < 2.5 Note 1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but established by characterization and qualification. For endurance estimates in a specific application, please consult the Total EnduranceTM Model which can be obtained from our web site. 3: Includes THI time. 2003 Microchip Technology Inc. Preliminary DS21836A-page 3 25AA1024/25LC1024 TABLE 1-2: (CONTINUED) AC CHARACTERISTICS Param. No. Sym TA = -40C to +85C TA = -40C to +125C Industrial (I): Automotive (E): AC CHARACTERISTICS Characteristic Min Max Units VCC = 1.8V TO 5.5V VCC = 2.5V to 5.5V Conditions 18 Thz HOLD low to output High-Z 15 30 150 -- -- -- ns ns ns 4.5 VCC 5.5 2.5 VCC < 4.5 1.8 VCC < 2.5 (Note 1) 19 Thv HOLD high to output valid 15 30 150 -- -- -- ns ns ns 4.5 VCC 5.5 2.5 VCC < 4.5 1.8 VCC < 2.5 20 Trel CS High to Standby mode -- 1.6 s VCC = 1.8V to 5.5V 21 Tpd CS High to Deep powerdown -- 1.6 s VCC = 1.8V to 5.5V 22 Tce Chip erase cycle time -- 4 s VCC = 1.8V to 5.5V 23 Tse Sector erase cycle time -- 2 s VCC = 1.8V to 5.5V 24 Twc Internal write cycle time ms Byte or Page mode 25 -- Endurance -- 5 100K -- E/W (Note 2) Cycles Note 1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but established by characterization and qualification. For endurance estimates in a specific application, please consult the Total EnduranceTM Model which can be obtained from our web site. 3: Includes THI time. TABLE 1-3: AC TEST CONDITIONS AC Waveform: VLO = 0.2V -- VH I = VCC - 0.2V (Note 1) VH I = 4.0V (Note 2) CL = 100 pF -- Timing Measurement Reference Level Input 0.5 VCC Output 0.5 VCC Note 1: For VCC 4.0V 2: For VCC > 4.0V DS21836A-page 4 Preliminary 2003 Microchip Technology Inc. 25AA1024/25LC1024 FIGURE 1-1: HOLD TIMING CS 17 16 17 16 SCK 18 SO n+2 SI n+2 n+1 19 high-impedance n n 5 don't care n+1 n-1 n n n-1 HOLD FIGURE 1-2: SERIAL INPUT TIMING 4 CS 2 12 11 7 Mode 1,1 8 3 SCK Mode 0,0 5 SI 6 MSB in LSB in high-impedance SO FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 3 10 Mode 1,1 SCK Mode 0,0 13 SO 14 MSB out SI 2003 Microchip Technology Inc. 15 LSB out don't care Preliminary DS21836A-page 5 25AA1024/25LC1024 2.0 FUNCTIONAL DESCRIPTION 2.1 Principles of Operation 2.3 The 25XX1024 is a 131,072 byte Serial Flash designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today's popular microcontroller families, including Microchip's PICMicro(R) microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to match the SPI protocol. The 25XX1024 contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. Table 2-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses, and data are transferred MSB first, LSB last. Data (SI) is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25XX1024 in `HOLD' mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. 2.2 Prior to any attempt to write data to the 25XX1024, the write enable latch must be set by issuing the WREN instruction (Figure 2-4). This is done by setting CS low and then clocking out the proper instruction into the 25XX1024. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. Once the write enable latch is set, the user may proceed by setting the CS low, issuing a WRITE instruction, followed by the 24-bit address, with seven MSBs of the address being don't care bits, and then the data to be written. Up to 256 bytes of data can be sent to the device before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page. Note: Read Sequence The device is selected by pulling CS low. The 8-bit read instruction is transmitted to the 25XX1024 followed by the 24-bit address, with seven MSBs of the address being don't care bits. After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (1FFFFh), the address counter rolls over to address 00000h allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin (Figure 2-1). DS21836A-page 6 Write Sequence Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or `page size'), and end at addresses that are integer multiples of page size - 1. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. For the data to be actually written to the array, the CS must be brought high after the Least Significant bit (D0) of the nth data byte has been clocked in. If CS is brought high at any other time, the write operation will not be completed. Refer to Figure 2-2 and Figure 2-3 for more detailed illustrations on the byte write sequence and the page write sequence respectively. While the write is in progress, the Status Register may be read to check the status of the WPEN, WIP, WEL, BP1 and BP0 bits (Figure 2-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset. Preliminary 2003 Microchip Technology Inc. 25AA1024/25LC1024 BLOCK DIAGRAM Status Register HV Generator Memory Control Logic I/O Control Logic EEPROM Array X Dec Page Latches SI SO Y Decoder CS SCK Sense Amp. R/W Control HOLD WP VCC VSS TABLE 2-1: INSTRUCTION SET Instruction Name Instruction Format READ 0000 0011 Description Read data from memory array beginning at selected address WRITE 0000 0010 Write data to memory array beginning at selected address WREN 0000 0110 Set the write enable latch (enable write operations) WRDI 0000 0100 Reset the write enable latch (disable write operations) RDSR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register PE 0100 0010 Page Erase - erase one page in memory array SE 1101 1000 Sector Erase - erase one sector in memory array CE 1100 0111 Chip Erase - erase all sectors in memory array RDID 1010 1011 Release from Deep power-down and read electronic signature DPD 1011 1001 Deep Power-down mode FIGURE 2-1: READ SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK instruction SI 0 0 0 0 0 24 Bit Address 0 1 1 23 22 21 20 2 1 0 Data Out high-impedance 7 SO 2003 Microchip Technology Inc. Preliminary 6 5 4 3 2 1 0 DS21836A-page 7 25AA1024/25LC1024 FIGURE 2-2: BYTE WRITE SEQUENCE CS Twc 0 1 2 3 4 5 6 8 7 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK instruction SI 0 0 0 0 0 24-bit address 0 1 0 23 22 21 20 data byte 2 1 0 7 6 5 4 3 2 1 0 high-impedance SO FIGURE 2-3: PAGE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK instruction SI 0 0 0 0 0 24-bit address 0 1 0 23 22 21 20 data byte 1 2 1 0 7 6 5 4 3 2 1 0 CS 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCK data byte 2 SI 7 DS21836A-page 8 6 5 4 3 data byte 3 2 1 0 7 6 5 4 3 data byte n (256 max) 2 Preliminary 1 0 7 6 5 4 3 2 1 0 2003 Microchip Technology Inc. 25AA1024/25LC1024 2.4 Write Enable (WREN) and Write Disable (WRDI) The following is a list of conditions under which the write enable latch will be reset: * * * * The 25XX1024 contains a write enable latch. See Table 2-4 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI will reset the latch. FIGURE 2-4: Power-up WRDI instruction successfully executed WRSR instruction successfully executed WRITE instruction successfully executed WRITE ENABLE SEQUENCE (WREN) CS 0 1 2 3 4 5 6 7 SCK 0 SI 0 0 0 0 1 1 0 high-impedance SO FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 10 0 high-impedance SO 2003 Microchip Technology Inc. Preliminary DS21836A-page 9 25AA1024/25LC1024 2.5 Read Status Register Instruction (RDSR) The Write Enable Latch (WEL) bit indicates the status of the write enable latch and is read-only. When set to a `1', the latch allows writes to the array, when set to a `0', the latch prohibits writes to the array. The state of this bit can always be updated via the WREN or WRDI commands regardless of the state of write protection on the Status Register. These commands are shown in Figure 2-4 and Figure 2-5. The Read Status Register instruction (RDSR) provides access to the Status Register. The Status Register may be read at any time, even during a write cycle. The Status Register is formatted as follows: TABLE 2-2: STATUS REGISTER 7 6 5 4 3 2 1 W/R - - - W/R W/R R WPEN X X X BP1 BP0 WEL W/R = writable/readable. R = read-only. The Block Protection (BP0 and BP1) bits indicate which blocks are currently write-protected. These bits are set by the user issuing the WRSR instruction. These bits are nonvolatile, and are shown in Table 2-3. 0 R WIP See Figure 2-6 for the RDSR timing sequence. The Write-In-Process (WIP) bit indicates whether the 25XX1024 is busy with a write operation. When set to a `1', a write is in progress, when set to a `0', no write is in progress. This bit is read-only. FIGURE 2-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 SCK instruction SI 0 0 0 0 0 1 0 1 Data from Status Register high-impedance SO DS21836A-page 10 7 Preliminary 6 5 4 3 2 2003 Microchip Technology Inc. 25AA1024/25LC1024 2.6 Write Status Register Instruction (WRSR) The Write-Protect Enable (WPEN) bit is a nonvolatile bit that is available as an enable bit for the WP pin. The Write-Protect (WP) pin and the Write-Protect Enable (WPEN) bit in the Status Register control the programmable hardware write-protect feature. Hardware write protection is enabled when WP pin is low and the WPEN bit is high. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low. When the chip is hardware write-protected, only writes to nonvolatile bits in the Status Register are disabled. See Table 2-4 for a matrix of functionality on the WPEN bit. The Write Status Register instruction (WRSR) allows the user to write to the nonvolatile bits in the Status Register as shown in Table 2-2. The user is able to select one of four levels of protection for the array by writing to the appropriate bits in the Status Register. The array is divided up into four segments. The user has the ability to write-protect none, one, two or all four of the segments of the array. The partitioning is controlled as shown in Table 2-3. See Figure 2-7 for the WRSR timing sequence. TABLE 2-3: ARRAY PROTECTION BP1 BP0 Array Addresses Write-Protected Array Addresses Unprotected 0 0 none All (Sectors 0, 1, 2 & 3) (00000h - 1FFFFh) 0 1 Upper 1/4 (Sector 3) (18000h - 1FFFFh) Lower 3/4 (Sectors 0, 1 & 2) (00000h - 17FFFh) 1 0 Upper 1/2 (Sectors 2 & 3) (10000h - 1FFFFh) Lower 1/2 (Sectors 0 & 1) (00000h - 0FFFFh) 1 1 All (Sectors 0, 1, 2 & 3) (00000h - 1FFFFh) none FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 SCK instruction SI 0 0 0 0 data to Status Register 0 0 0 1 7 6 5 4 3 2 high-impedance SO 2003 Microchip Technology Inc. Preliminary DS21836A-page 11 25AA1024/25LC1024 2.7 Data Protection 2.8 The following protection has been implemented to prevent inadvertent writes to the array: * The write enable latch is reset on power-up * A write enable instruction must be issued to set the write enable latch * After a byte write, page write or Status Register write, the write enable latch is reset * CS must be set high after the proper number of clock cycles to start an internal write cycle * Access to the array during an internal write cycle is ignored and programming is continued TABLE 2-4: Power-On State The 25XX1024 powers on in the following state: * The device is in low-power Standby mode (CS = 1) * The write enable latch is reset * SO is in high-impedance state * A high-to-low-level transition on CS is required to enter active state WRITE-PROTECT FUNCTIONALITY MATRIX WEL (SR bit 1) WPEN (SR bit 7) WP (pin 3) Protected Blocks Unprotected Blocks Status Register 0 x x Protected Protected Protected 1 0 x Protected Writable Writable 1 1 0 (low) Protected Writable Protected 1 1 1 (high) Protected Writable Writable x = don't care DS21836A-page 12 Preliminary 2003 Microchip Technology Inc. 25AA1024/25LC1024 2.9 PAGE ERASE The Page Erase function will erase all bits (FFh) inside the given page. A Write Enable (WREN) instruction must be given prior to attempting a Page Erase. This is done by setting CS low and then clocking out the proper instruction into the 25XX1024. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. CS must then be driven high after the last bit if the address or the Page Erase will not execute. Once the CS is driven high the self-timed Page Erase cycle is started. The WIP bit in the Status Register can be read to determine when the Page Erase cycle is complete. If a Page Erase function is given to an address that has been protected by the Block Protect bits (BP0, BP1) then the sequence will be aborted and no erase will occur. The Page Erase function is entered by driving CS low, followed by the instruction code Figure 2-8, and three address bytes. Any address inside the page to be erased is a valid address. FIGURE 2-8: PAGE ERASE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 SCK instruction SI 0 1 0 0 0 24-bit address 0 1 0 23 22 21 20 2 1 0 high-impedance SO 2003 Microchip Technology Inc. Preliminary DS21836A-page 13 25AA1024/25LC1024 2.10 SECTOR ERASE The Sector Erase function will erase all bits (FFh) inside the given sector. A Write Enable (WREN) instruction must be given prior to attempting a Sector Erase. This is done by setting CS low and then clocking out the proper instruction into the 25XX1024. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. CS must then be driven high after the last bit if the address or the Sector Erase will not execute. Once the CS is driven high the self-timed Sector Erase cycle is started. The WIP bit in the Status Register can be read to determine when the Sector Erase cycle is complete. If a Sector Erase instruction is given to an address that has been protected by the Block Protect bits (BP0, BP1) then the sequence will be aborted and no erase will occur. The Sector Erase function is entered by driving CS low, followed by the instruction code Figure 2-9, and three address bytes. Any address inside the sector to be erased is a valid address. FIGURE 2-9: See Table 2-3 for Sector Addressing. SECTOR ERASE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 SCK instruction SI 1 1 0 1 1 24-bit address 0 0 0 23 22 21 20 2 1 0 high-impedance SO DS21836A-page 14 Preliminary 2003 Microchip Technology Inc. 25AA1024/25LC1024 2.11 CHIP ERASE The Chip Erase function will erase all bits (FFh) in the array. A Write Enable (WREN) instruction must be given prior to executing a Chip Erase. This is done by setting CS low and then clocking out the proper instruction into the 25XX1024. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. The CS pin must be driven high after the eighth bit of the instruction code has been given or the Chip Erase function will not be executed. Once the CS pin is driven high the self-timed Chip Erase function begins. While the device is executing the Chip Erase function the WIP bit in the Status Register can be read to determine when the Chip Erase function is complete. The Chip Erase function is entered by driving the CS low, followed by the instruction code (Figure 2-10) onto the SI line. The Chip Erase function is ignored if either of the Block Protect bits (BP0, BP1) are not 0, meaning 1/4, 1/2, or all of the array is protected. FIGURE 2-10: CHIP ERASE SEQUENCE CS 0 1 2 3 4 5 6 7 SCK SI 1 1 0 0 0 1 1 1 high-impedance SO 2003 Microchip Technology Inc. Preliminary DS21836A-page 15 25AA1024/25LC1024 2.12 DEEP POWER-DOWN MODE Deep Power-down Mode of the 25XX1024 is its lowest power consumption state. The device will not respond to any of the read or write commands while in Deep Power-down mode, and therefore it can be used as an additional software write protection feature. All instructions given during Deep Power-down mode are ignored except the Read Electronic Signature Command (RDID). The RDID command will release the device from Deep power-down and outputs the electronic signature on the SO pin, and then returns the device to Standby mode after delay (TREL) The Deep Power-down mode is entered by driving CS low, followed by the instruction code (Figure 2-11) onto the SI line, followed by driving CS high. Deep Power-down mode automatically releases at device power-down. Once power is restored to the device it will power-up in the Standby mode. If the CS pin is not driven high after the eighth bit of the instruction code has been given, the device will not execute Deep power-down. Once the CS line is driven high there is a delay (TDP) before the current settles to its lowest consumption. FIGURE 2-11: DEEP POWER-DOWN SEQUENCE CS 0 1 2 3 4 5 6 7 SCK SI 1 0 1 1 1 0 0 1 high-impedance SO DS21836A-page 16 Preliminary 2003 Microchip Technology Inc. 25AA1024/25LC1024 2.13 RELEASE FROM DEEP POWERDOWN AND READ ELECTRONIC SIGNATURE Release from Deep Power-down mode and Read Electronic Signature is entered by driving CS low, followed by the RDID instruction code (Figure 2-12) and then a dummy address of 24 bits (A23-A0). After the last bit of the dummy address is clock in, the 8-bit Electronic signature is clocked out on the SO pin. Once the device has entered Deep Power-down mode all instructions are ignored except the Release from Deep Power-down and Read Electronic Signature command. This command can also be used when the device is not in Deep Power-down to read the electronic signature out on the SO pin unless another command is being executed such as Erase, Program or Write Status Register. FIGURE 2-12: After the signature has been read out at least once, the sequence can be terminated by driving CS high. The device will then return to Standby mode and will wait to be selected so it can be given new instructions. If additional clock cycles are sent after the electronic signature has been read once, it will continue to output the signature on the SO line until the sequence is terminated. RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE CS 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK instruction SI 1 0 1 0 24-bit address 1 0 1 1 23 22 21 20 2 1 0 Electronic Signature Out high-impedance SO 7 6 5 4 3 2 1 0 0 0 1 0 1 0 0 1 Manufacturers ID 0x29 Driving CS high after the 8-bit RDID command but before the Electronic Signature has been transmitted will still ensure the device will be taken out of Deep Power-down mode. However, there is a delay TREL that occurs before the device returns to Standby mode (ICCS), as shown in Figure 2-13. FIGURE 2-13: RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE CS 0 1 2 3 4 5 6 0 1 7 TREL SCK instruction SI 1 0 1 0 1 1 high-impedance SO 2003 Microchip Technology Inc. Preliminary DS21836A-page 17 25AA1024/25LC1024 3.0 PIN DESCRIPTIONS The WP pin function is blocked when the WPEN bit in the Status Register is low. This allows the user to install the 25XX1024 in a system with WP pin grounded and still be able to write to the Status Register. The WP pin functions will be enabled when the WPEN bit is set high. The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE Name Pin Number CS 1 Chip Select Input SO 2 Serial Data Output WP 3 Write-Protect Pin VSS 4 Ground SI 5 Serial Data Input SCK 6 Serial Clock Input HOLD 7 Hold Input VCC 8 Supply Voltage 3.1 Function 3.4 The SI pin is used to transfer data into the device. It receives instructions, addresses and data. Data is latched on the rising edge of the serial clock. 3.5 Chip Select (CS) 3.6 Serial Output (SO) The SO pin is used to transfer data out of the 25XX1024. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock. 3.3 Serial Clock (SCK) The SCK is used to synchronize the communication between a master and the 25XX1024. Instructions, addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input. A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. However, a programming cycle which is already initiated or in progress will be completed, regardless of the CS input signal. If CS is brought high during a program cycle, the device will go into Standby mode as soon as the programming cycle is complete. When the device is deselected, SO goes to the high-impedance state, allowing multiple parts to share the same SPI bus. A low-to-high transition on CS after a valid write sequence initiates an internal write cycle. After powerup, a low level on CS is required prior to any sequence being initiated. 3.2 Serial Input (SI) Hold (HOLD) The HOLD pin is used to suspend transmission to the 25XX1024 while in the middle of a serial sequence without having to retransmit the entire sequence again. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD pin must be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high-tolow transition. The 25XX1024 must remain selected during this sequence. The SI, SCK and SO pins are in a high-impedance state during the time the device is paused and transitions on these pins will be ignored. To resume serial communication, HOLD must be brought high while the SCK pin is low, otherwise serial communication will not resume. Pulling the HOLD line low at any time will tri-state the SO line. Write-Protect (WP) This pin is used in conjunction with the WPEN bit in the Status Register to prohibit writes to the nonvolatile bits in the Status Register. When WP is low and WPEN is high, writing to the nonvolatile bits in the Status Register is disabled. All other operations function normally. When WP is high, all functions, including writes to the nonvolatile bits in the Status Register, operate normally. If the WPEN bit is set, WP low during a Status Register write sequence will disable writing to the Status Register. If an internal write cycle has already begun, WP going low will have no effect on the write. DS21836A-page 18 Preliminary 2003 Microchip Technology Inc. 25AA1024/25LC1024 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 8-Lead DFN Example: XXXXXXX T/XXXXX YYWW NNN 5LC1024 I/MF 0328 1L7 8-Lead PDIP Example: XXXXXXXX T/XXXNNN YYWW 25AA1024 I/P 1L7 0328 Example: 8-Lead SOIC 25LC1024 I/SN 0328 1L7 XXXXXXXX T/XXYYWW NNN Legend: Note: XX...X T Blank YY WW NNN Part number Temperature (I,E) Commercial Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Custom marking available. 2003 Microchip Technology Inc. Preliminary DS21836A-page 19 25AA1024/25LC1024 8-Lead Plastic Dual Flat No Lead Package (MF) 6x5 mm Body (DFN-S) E p B E1 n L R D1 1 D D2 PIN 1 ID EXPOSED METAL PADS 2 E2 TOP VIEW BOTTOM VIEW A2 A3 A A1 Number of Pins MILLIMETERS* INCHES Units Dimension Limits NOM MIN n MAX NOM MIN MAX 8 8 Pitch p Overall Height A .033 .039 0.85 1.00 Molded Package Thickness A2 .026 .031 0.65 0.80 Standoff A1 .0004 .002 0.01 0.05 Base Thickness A3 .008 REF. 0.20 REF. 4.92 BSC .000 E .194 BSC Molded Package Length E1 .184 BSC Exposed Pad Length E2 Overall Length Overall Width 1.27 BSC .050 BSC .152 D .158 0.00 4.67 BSC .163 3.85 4.00 4.15 5.99 BSC .236 BSC Molded Package Width D1 Exposed Pad Width D2 .085 .091 .097 2.16 2.31 2.46 B .014 .016 .019 0.35 0.40 0.47 Lead Length L .020 .024 .030 0.50 0.60 0.75 Tie Bar Width R Lead Width Mold Draft Angle Top 5.74 BSC .226 BSC .356 .014 12 12 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC equivalent: pending Drawing No. C04-113 DS21836A-page 20 Preliminary 2003 Microchip Technology Inc. 25AA1024/25LC1024 8-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n 1 E A2 A L c A1 B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D L c B1 B eB MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM MAX 8 .100 .155 .130 .170 .145 .313 .250 .373 .130 .012 .058 .018 .370 10 10 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 2003 Microchip Technology Inc. Preliminary DS21836A-page 21 25AA1024/25LC1024 8-Lead Plastic Small Outline (SM) - Medium, 208 mil (SOIC) E E1 p D 2 n 1 B c A2 A L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D L c B MIN .070 .069 .002 .300 .201 .202 .020 0 .008 .014 0 0 INCHES* NOM 8 .050 .075 .074 .005 .313 .208 .205 .025 4 .009 .017 12 12 A1 MAX .080 .078 .010 .325 .212 .210 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.78 1.97 1.75 1.88 0.05 0.13 7.62 7.95 5.11 5.28 5.13 5.21 0.51 0.64 0 4 0.20 0.23 0.36 0.43 0 12 0 12 MIN MAX 2.03 1.98 0.25 8.26 5.38 5.33 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. Drawing No. C04-056 DS21836A-page 22 Preliminary 2003 Microchip Technology Inc. 25AA1024/25LC1024 ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape(R) or Microsoft(R) Internet Explorer. Files are also available for FTP download from our FTP site. SYSTEMS INFORMATION AND UPGRADE HOT LINE The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive the most current upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. Connecting to the Microchip Internet Web Site 042003 The Microchip web site is available at the following URL: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events 2003 Microchip Technology Inc. Preliminary DS21836A-page 23 25AA1024/25LC1024 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y Device: 25AA1024/25LC1024 N Literature Number: DS21836A Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21836A-page 24 Preliminary 2003 Microchip Technology Inc. 25AA1024/25LC1024 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X Device Tape & Reel - X /XX X Temp Range Package Lead Finish Examples: a) b) Device 25AA1024 25LC1024 1 Mbit, 1.8V, 256-Byte Page SPI Serial Flash 1 Mbit, 2.5V, 256-Byte Page SPI Serial Flash Tape & Reel Blank T = = Standard packaging (tube) Tape & Reel Temperature Range I E = = -40C to+85C -40C to+125C Package MF P SM = = = Micro Lead Frame (6 x 5 mm body), 8-lead Plastic DIP (300 mil body), 8-lead Plastic SOIC (207 mil body), 8-lead Lead Finish Blank = G = c) d) e) f) 25AA1024-I/SMG = 1 Mbit, 1.8V Serial Flash, Industrial temp., SOIC package, Pb-free 25AA1024T-I/SM = 1 Mbit, 1.8V Serial Flash, Industrial temp., Tape & Reel, SOIC package 25AA1024T-I/MF = 1 Mbit, 1.8V Serial Flash, Industrial temp., Tape & Reel, DFN package 25LC1024-I/SMG = 1 Mbit, 2.5V Serial Flash, Industrial temp., SOIC package, Pb-free 25LC1024-I/P = 1 Mbit, 2.5V Serial Flash, Industrial temp., P-DIP package 25LC1024T-E/MF = 1 Mbit, 2.5V Serial Flash, Extended temp., Tape & Reel, DFN package Standard 63% / 37% Sn/Pb Matte Tin (Pure Sn) Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2003 Microchip Technology Inc. Preliminary DS21836A-page 25 25AA1024/25LC1024 NOTES: DS21836A-page 26 Preliminary 2003 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Application Maestro, dsPICDEM, dsPICDEM.net, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. 2003 Microchip Technology Inc. Preliminary DS21836A-page 27 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Korea Corporate Office Australia 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Atlanta Unit 915 Bei Hai Wan Tai Bldg. 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