Datasheet 1 Rev. 1.0
www.infineon.com/hitfet 2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
1 Overview
Features
• Single channel device
• 3.3V and 5V compatible logic input
• PWM switching capability 20kHz for 10-90% duty cycle
• Electrostatic discharge protection (ESD)
• Adjustable switching speed
• Digital latch feedback signal
• Very low power DMOS leakage current in OFF state
• DMOS turn on capability in inverse current situation
• Green Product (RoHS compliant)
Potential applications
• Suitable for resistive, inductive and capacitive loads
• Replaces electromechanical relays, fuses and discrete circuits
• Allows high inrush currents and active freewheeling
Product validation
Qualified for automotive applications. Product validation according to AEC-Q100/101.
Description
The BTF3050EJ is a 50 mΩ single channel Smart Low-Side Power Switch with in a PG-TDSO-8-31 package
providing embedded protective functions. The power transistor is built by an N-channel vertical power
MOSFET.
The device is monolithically integrated. The BTF3050EJ is automotive qualified and is optimized for 12V
automotive and industrial applications.
Table 1 Product Summary
Operating voltage range VOUT 3 .. 28 V
Maximum battery voltage VBAT(LD) 40 V
Operating supply voltage range VDD 3.0 .. 5.5 V
Maximum input voltage VIN 5.5 V
Maximum On-State resistance at Tj = 150°C, VDD = 5V, VIN = 5V RDS(ON) 100 mΩ
Datasheet 2 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Overview
Diagnostic Functions
• Short circuit to battery
• Over temperature shut down
• Stable latching diagnostic signal
Protection Functions
• Over temperature shutdown with auto-restart
• Active clamp over voltage protection of the output (OUT, cooling tab)
•Current limitation
• Enhanced short circuit protection
Detailed Description
The device is able to switch all kind of resistive, inductive and capacitive loads, limited by maximum clamping
energy and maximum current capabilities.
The BTF3050EJ offers dedicated ESD protection on the IN, VDD, ENABLE, STATUS and SRP pin which refers to
the GND ground pin, as well as an over voltage clamping of the OUT to Source/GND.
The over voltage protection gets activated during inductive turn off conditions or other over voltage events
(like load dump). The power MOSFET is limiting the drain-source voltage, if it rises above the VOUT(CLAMP).
The over temperature protection prevents the device from overheating due to overload and/or bad cooling
conditions.
The BTF3050EJ has an auto-restart thermal shutdown function. The device will turn on again, if input is still
high, after the measured temperature has dropped below the thermal hysteresis.
Nominal load current IL(NOM) 4A
Minimum current limitation IL(LIM) 10 A
Minimum current limitation trigger level IL(LIM)TRIGGER 29 A
Maximum OFF state load current at TJ ≤ 85°C IL(OFF) 2µA
Maximum stand-by supply current at TJ = 25°C IDD(OFF) 6µA
Type Package Marking
BTF3050EJ PG-TDSO-8-31 F3050EJ
Table 1 Product Summary (cont’d)
Datasheet 3 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3 Voltage and Current Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.1 PCB set up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3.2 Transient Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 Output On-state Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 Functional description of ENABLE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 Functional description of IN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4 Resistive Load Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5 Inductive Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.5.1 Output Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.5.2 Maximum Load Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.6 Adjustable Switching Speed / Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.7 Inverse Current Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.8 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 Over Voltage Clamping on OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2 Over Temperature Protection with Latched Fault Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.3 Overcurrent Limitation / Short Circuit Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4 Reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1 Functional Description of the STATUS pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8 Supply and Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.1 Supply Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.2 Undervoltage Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.3 Input/Enable Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.4 Functional Description of the SRP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.1 Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.2 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.3 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.4 Supply and Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table of Contents
Datasheet 4 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
10 Characterization Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10.1 Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10.2 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.3 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.4 Supply and Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.1 Design and Layout Recommendations/Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
13 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Datasheet 5 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Block Diagram
2 Block Diagram
Figure 1 Block Diagram
Datasheet 6 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Pin Assignment
3 Pin Assignment
3.1 Pin Configuration
Figure 2 Pin configuration
3.2 Pin Definitions and Functions
Pin Symbol I/O Function
1 IN Input If IN logic is high, switches ON the Power DMOS
If IN logic is low, switches OFF the Power DMOS
only if pin ENABLE is logic high
2V
DD Input Logic supply voltage, 3V to 5.5V
3 STATUS Input Reset of latches by microcontroller pull-up
Output If STATUS logic is high, device is under normal operation
If STATUS logic is low, device is in over temperature condition
4 SRP Input Slewrate control with external resistor
5 ENABLE Input If ENABLE logic is high, IN pin is enabled
If ENABLE logic is low, IN pin is disabled and leakages are minimum
6,7,8 GND I/O SOURCE of power DMOS and Logic, GND pins must be connected
together
Cooling tab OUT I/O DRAIN of power DMOS. Connected to Load.
Datasheet 8 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
General Product Characteristics
4 General Product Characteristics
4.1 Absolute Maximum Ratings
Table 2 Absolute Maximum Ratings1)
TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Voltages
Supply voltage VDD -0.3 – 5.5 V P_4.1.1
Output voltage VOUT ––40V P_4.1.2
Battery voltage for short circuit
protection
VBAT(SC) ––31V 1)l = 0 or 5m
RSC = 30 mΩ+ RCable
RCable = l * 16 mΩ/m
LSC = 5 µH + LCable
LCable = l * 1 µH/m VDD =5V;
VIN=5V; VENABLE=5V
P_4.1.3
Battery voltage for load dump
protection
(VBAT(LD) = VA + VS with VA = 13.5V)
VBAT(LD) ––40V 2)Ri = 2 Ω, RL = 4.7 Ω, td =
400 ms,
suppressed pulse
P_4.1.4
Control pins voltages
Input Voltage VIN -0.3 – 5.5 V – P_4.1.8
SRP pin Voltage VSRP -0.3 – 5.5 V VSRP ≤ VDD P_4.1.9
STATUS pin Voltage VSTATUS -0.3 – 5.5 V P_4.1.10
ENABLE pin Voltage VENABLE -0.3 – 5.5 V P_4.1.11
Power Stage
Load current |IL|––IL(LIM) TJ < 150°C P_4.1.12
Power Dissipation PTOT – – 1.60 W DC operation,TA =
85°C,TJ < 150°C, IL = INOM
P_4.1.47
Energies
Unclamped single inductive energy
single pulse
EAS ––94mJIL(0) = IL(NOM)
VBAT = 13.5 V
Tj(0) = 150°C
P_4.1.16
Unclamped repetitive inductive
energy pulse with 10k cycles
EAR(10k) ––90mJIL(0) = IL(NOM)
VBAT = 13.5 V
Tj(0) = 85 °C
P_4.1.26
Datasheet 9 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
General Product Characteristics
Note:
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation
Unclamped repetitive inductive
energy pulse with 100k cycles
EAR(100k) ––85mJIL(0) = IL(NOM)
VBAT = 13.5 V
TJ(0) = 85 °C
P_4.1.31
Temperatures
Operating temperature Tj-40 – +150 °C – P_4.1.39
Storage temperature Tstg -55 – +150 °C –
ESD robustness
ESD robustness (all pins) VESD -2 – 2 kV HBM3) P_4.1.41
ESD robustness OUT pin vs. GND VESD -4 – 4 kV HBM3) P_4.1.42
ESD robustness VESD -500 – 500 V CDM4) P_4.1.43
ESD robustness corner pins VESD -750 – 750 V CDM 5) P_4.1.44
1) Not subject to production test, specified by design.
2) VBAT(LD) is setup without the DUT connected to the generator per ISO7637-1;
Ri is the internal resistance of the load dump test pulse generator;
td is the pulse duration time for load dump pulse (pulse 5) according ISO 7637-1, -2.
3) ESD robustness, HBM according to ANSI/ESDA/JEDEC JS-001 (1.5 kΩ, 100 pF)
4) ESD robustness, Charged Device Model “CDM” ESDA STM5.3.1 or JESD22-C101
5) ESD robustness, Charged Device Model “CDM” ESDA STM5.3.1 or JESD22-C101
Table 2 Absolute Maximum Ratings1) (cont’d)
TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Datasheet 10 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
General Product Characteristics
4.2 Functional Range
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics
table.
Table 3 Functional Range
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Supply Voltage Range for
Nominal Operation
VDD(NOR) 3.0 5.0 5.5 V P_4.2.1
Supply current continuous ON
operation
IDD(ON) – 1.3 2.5 mA Supply current
continuous ON
operation is specified
forRSRP=0. It is lower
(0.7mA typ)
forRSRP=5.8k
1)
P_4.2.4
Standby supply current
(ambient)
IDD(OFF) –1.56µATJ = 25°C
1)
P_4.2.8
Maximum standby supply current
(hot)
IDD(OFF)_150 –614µAT
J = 150°C P_4.2.9
Battery Voltage Range for
Nominal Operation
VBAT(NOR) 6 13.5 18 V 1) P_4.2.10
Extended Battery Voltage Range
for Operation
VBAT(EXT) 0 – 29 V parameter deviations
possible
P_4.2.11
SRP pin resistor for adjustable
operation
RSRP(NOR) 5–70kΩrefer to graphic
Figure 16
1)
P_4.2.12
SRP pin resistor for fast operation RSRP(EXTF) 0–1.5kΩ1) P_4.2.13
SRP pin resistor for slow
operation
RSRP(EXTS) >160 – – kΩPin can be left open
1)
P_4.2.14
DIAGNOSIS
STATUS Pin voltage operation
range
VSTATUS -0.3 – 5.5 V normal and reset
mode
1)
P_4.2.15
STATUS Pin Leakage current ISTATUS –1.512µAVSTATUS ≤ 5V
1)
P_4.2.17
STATUS Pin voltage drop Fault VSTATUS(FAULT) 0.5 0.8 V ISTATUS(FAULT)=1mA P_4.2.18
STATUS Current Reset ISTATUS(RESET) 5–7mA P_4.2.19
Datasheet 11 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
General Product Characteristics
4.3 Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards.
For more information, go to www.jedec.org.
Table 4 TJ = -40°C to +150°CVDD = 3.0 V to 5.5 VVBAT = 6 V to 18 Vall voltages with respect to ground,
positive current flowing into pin (unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Junction to Case RthJC –3–K/W
1) 2)
1) Not subject to production test, specified by design
2) Specified RthJC value is simulated at natural convection on a cold plate setup (bottom of package is fixed to ambient
temperature).
TC = 85°C. Device is loaded with 1W power.
P_4.3.3
Junction to Ambient (2s2p) RthJA(2s2p) –35–K/W
1) 3)
3) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board;
The product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu,
2 x 35µm Cu). Where applicable a thermal via array under the ex posed pad contacted the first inner copper layer.
Ta = 85°C, Device is loaded with 1W power.
P_4.3.9
Junction to Ambient
(1s0p+600mm2 Cu)
RthJA(1s0p) –46–K/W
1) 4)
4) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 1s0p board;
The product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional heatspreading copper
area of 600mm2 and 70 mm thickness. Ta = 85°C, Device is loaded with 1W power.
P_4.3.14
Datasheet 12 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
General Product Characteristics
4.3.1 PCB set up
The following PCB setup was implemented to determine the transient thermal impedance. The setup is
according to JEDEC standard JESD51-2A and related.
Figure 4 Cross-section JEDEC2s2p
Figure 5 Cross-section JEDEC1s0p
Figure 6 PCB layout, top view
Datasheet 13 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
General Product Characteristics
4.3.2 Transient Thermal Impedance
Figure 7 Typical transient thermal impedance ZthJA = f(tp), Ta = 85°C
Value is according to Jedec JESD51-2,-7 at natural convection on FR4 boards; The product
(Chip+Package) was simulated with the respective PCB setups, according to the JEDEC
standard. Where applicable a thermal via array under the ex posed pad contacted the first
inner copper layer. Device is dissipating 1 W power.
Datasheet 14 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
General Product Characteristics
Figure 8 Zth(JC) vs. duty cycle
Figure 9 PCB 1sp0 - Rthja vs. cooling areas
Datasheet 15 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Power Stage
5 Power Stage
5.1 Output On-state Resistance
The on-state resistance depends on the supply voltage and on the junction temperature TJ. Figure 10 shows
this dependencies in terms of temperature and voltage for the typical on-state resistance RDS(ON). The behavior
in reverse polarity is described in chapter“Inverse Current Capability” on Page 20.
Figure 10 Trend of On-State Resistance RDS(ON) = f(TJ), VDD = 5V or 3V, VIN = high
At VIN= high the power DMOS switches ON with a dedicated slope.
To achieve a reasonable RDS(ON)and the specified switching speed a 5V supply is required.
5.2 Functional description of ENABLE pin
The physical digital input ENABLE allows power down mode when IN pin toggling is not needed.
When ENABLE is set to logic low, the DMOS is switched off (regardless of the status of the input IN) and the
device will be in Power Down mode. It allows the lowest possible leakage current through OUT and VDD pins.
The STATUS pin will not be available during this stage and the device is reset.
When the ENABLE pin is switched to logic high, the device logic and DMOS are available with full
functionalities, after a dead time defined as masking time - tENABLE(MASKING)”(Table “tENABLE(MASKING)” on
Page 36), .
Then, depending on the status of the IN pin the DMOS is switched on or off, see Chapter 5.3 and Figure 11
“VOUT in relation to VENABLE and VIN” on Page 16. The STATUS pin will also be available. For the electrical
characteristics see Table 8, Page 35.
Datasheet 16 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Power Stage
5.3 Functional description of IN pin
The IN pin is a digital input. As described in Chapter 5.2 using the physical IN pin requires the ENABLE pin to
be set to logic high.
If IN is set to logic low, the DMOS is switched off.
If IN is set to logic high, the DMOS is switched on.
In addition, an high frequency PWM signal source can be connected. At a frequency of 20kHz the duty cycle can
be selected between 10% and 90%. .
5.4 Resistive Load Output Timing
Figure 12 shows the typical timing when switching a resistive load.
Figure 11 VOUT in relation to VENABLE and VIN
Figure 12 Definition of Power Output Timing for Resistive Load
Datasheet 17 Rev. 1.0
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BTF3050EJ
Smart Low-Side Power Switch
Power Stage
5.5 Inductive Load
5.5.1 Output Clamping
When switching off inductive loads with low side switches, the drain-source voltage VOUT rises above battery
potential, because the inductance intends to continue driving the current. To prevent unwanted high voltages
the device has a voltage clamping mechanism to keep the voltage at VOUT(CLAMP). During this clamping
operation mode the device heats up as it dissipates the energy from the inductance. Therefore the maximum
allowed load inductance is limited. See Figure 13 and Figure 14 for more details.
Figure 13 Output Clamp Circuitry
Figure 14 Switching an Inductive Load
Note: Repetitive switching of inductive load by VDD instead of using the input is a not recommended
operation and may affect the device reliability and reduce the lifetime.
Datasheet 18 Rev. 1.0
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BTF3050EJ
Smart Low-Side Power Switch
Power Stage
5.5.2 Maximum Load Inductance
While demagnetization of inductive loads, energy has to be dissipated in the BTF3050EJ.
This energy can be calculated by the following equation:
(5.1)
Following equation simplifies under assumption of RL = 0
(5.2)
The figure below shows the inductance / current combination the BTF3050EJ can handle.
For maximum single avalanche energy refer to EAS value in Table 2.
Figure 15 Maximum load inductance for single pulse
L = f(IL), TJ,start = 150°C, VBAT = 13.5V
L
L
CLAMPOUTBAT
LL
L
CLAMPOUTBAT
CLAMPOUT R
L
I
VV
IR
R
VV
V×
⎥
⎥
⎦
⎤
⎢
⎢
⎣
⎡+
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
−
×
−×
−
×=
)(
)(
)( 1lnE
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
−
−×=
)(
2
1
2
1
CLAMPOUTBAT
BAT
L
VV
V
LIE
Datasheet 19 Rev. 1.0
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BTF3050EJ
Smart Low-Side Power Switch
Power Stage
5.6 Adjustable Switching Speed / Slew Rate
In order to optimize electromagnetic emission, the switching speed of the MOSFET can be adjusted by
connecting an external resistor between SRP pin and GND. This allows for balancing between electromagnetic
emissions and power dissipation. Shorting the SRP pin to GND represents the fastest switching speed. Open
pin represents the slowest switching speed.
The accuracy of the switching speed adjustment is dependent on the precision of the external resistor used
and on the parasitic capacitance on the SRP pin. It is recommended to use accurate resistors and place them
as close as possible to the SRP pin with the shortest way possible to the GND of the device.
Figure 16 shows the simplified relation between the resistor value and the switching times
Figure 16 Typical simplified relation between switching time and RSRP resistor values used on SRP pin
It is not recommended to change the slew rate resistance during switching (supplied device, VDD > VDD(UV_ON).
Undefined switching times can result.
If the SRP pin is externally pulled up above the normal SRP pin voltage VSRP (e.g. to VDD) the slowest slew rate
settings apply.
Datasheet 20 Rev. 1.0
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BTF3050EJ
Smart Low-Side Power Switch
Power Stage
5.7 Inverse Current Capability
An inverse situation means the OUT pin is pulled below GND potential via the load and current flows in the
Power DMOS intrinsic body diode.
In certain application cases (for example in use in a bridge or half-bridge configuration) the body diode is used
for freewheeling of an inductive load. In this case the device is still supplied but the inverse current is flowing
from GND to OUT(drain).
In inverse operation the body diode is dissipating power, which is defined by the driven current times the
voltage drop on the body diode -VDS.
In order to dissipate less power in inverse situation, a dedicated circuit has been implemented.
The BTF3050EJ includes an inverse current detection circuit that allows to turn ON the Power DMOS while
inverse current is present (active freewheeling) and disables all protections, e.g. current limitation,
temperature shutdown or over voltage clamping. To do active freewheeling, both ENABLE and IN pin must be
set to logic high.
The timings are set to slow mode (open SRP pin), regardless of the SRP pin configuration.
During inverse current condition the quiescent current of the circuit is the same as in normal operation if
ENABLE=high (see Chapter 9.4). If ENABLE=low and the device is still supplied, the standby supply current in
inverse increases compared to standby supply current in normal output current condition (see Table 8
“Electrical Characteristics: Supply and Input” on Page 35).
The maximum admissible inverse current is -IL(NOM).
5.8 Characteristics
See Table 9.1 “Power Stage” on Page 30 for electrical characteristics.
Datasheet 21 Rev. 1.0
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BTF3050EJ
Smart Low-Side Power Switch
Protection Functions
6 Protection Functions
The device provides embedded protection functions. Integrated protection functions are designed to prevent
IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside”
normal operation. Protection functions are not to be used for continuous or repetitive operation. Over
temperature is indicated by a low active signal on the STATUS pin.
6.1 Over Voltage Clamping on OUT
The BTF3050EJ is equipped with a voltage clamp circuitry that keeps the drain-source voltage VDS at a certain
level VOUT(CLAMP). The over voltage clamping is overruling the other protection functions. Power dissipation has
to be limited not to exceed the maximum allowed junction temperature.
This function is also used in terms of inductive clamping. See also “Output Clamping” on Page 17 for more
details.
6.2 Over Temperature Protection with Latched Fault Signal
The device is protected against over temperature due to overload and/or bad cooling conditions by an
integrated temperature sensor. The over temperature protection is available if the device is active, i.e. IN=high
and ENABLE=high.
The device incorporates an absolute (TJ(SD)) and a dynamic temperature limitation (ΔTJ(SW)). Triggering one of
them will cause the output to switch off. The dynamic temperature limitation principle is developed in a
separated Application Note for HITFET+.
The switch off will be done with the fastest possible slew rate. The BTF3050EJ has a thermal-restart function.
If IN pin is still high the device will turn on again after the junction temperature has dropped below the thermal
hysteresis (ΔTJ_HYS).
In case of detected overtemperature the fault signal will be set and the STATUS pin will be internally pulled
down to VSTATUS(FAULT).
This VSTATUS is independent from the IN signal, providing a stable fault signal (Logic “low”) to be read out by a
micro controller.
The latched fault signal needs to be reset by a pull-up signal (VSTATUS ≥ VSTATUS(RESET)) at the STATUS pin for a
minimum duration of tRESET, provided that the junction temperature has decreased at least from the thermal
hysteresis in the meantime.
The latched fault signal can also be reset by setting ENABLE=low. See Chapter 6.4 for an overview of reset
conditions.
See “Diagnostics” on Page 26 for details on the feedback and reset function.
Datasheet 22 Rev. 1.0
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BTF3050EJ
Smart Low-Side Power Switch
Protection Functions
Figure 17 Thermal protective switch OFF scenario for case of overload or short circuit
Note: For better understanding, the time scale is not linear. The real timing of this drawing is application
dependant and cannot be described.
6.3 Overcurrent Limitation / Short Circuit Behavior
BTF3050EJ provides a smart overcurrent limitation intended to protect against short circuit conditions while
allowing also load inrush currents higher than the current limitation level. It has a current limitation level IL(LIM)
which is triggered by a higher trigger level IL(LIM)TRIGGER.
If the load current IL reaches the current limitation trigger level IL(LIM)TRIGGER, the internal current limitation will
be activated and the device limits the current to a lower value IL(LIM).
The IL(LIM)TRIGGER function has a latch behaviour, it happens once and is disabled until it is reset.
Then, BTF3050EJ behaves as a normal auto-restart, current limiting device: It keeps heating up at IL(LIM) until
the thermal shutdown temperature TJ(SD) is reached, then it turns off.
Due to autorestart feature, the MOSFET turns on again after it drops in temperature below thermal hysteresis
(∆TJ_HYS). If fault situation is still present, the current will be limited to IL(LIM) as the trigger feature is now
disabled. The time to over temperature switch off strongly depends on the cooling conditions.
To reset the IL(LIM)TRIGGER level feature, two conditions are necessary. The STATUS pin needs a pull-up signal
(VSTATUS ≥ VSTATUS(RESET)) for a minimum duration of tRESET, and the IN pin must be in low state (VIN ≤ VIN(L)) at the
same time.
The IL(LIM)TRIGGER level feature can also be reset by setting ENABLE=low. See Chapter 6.4 for an overview of reset
conditions.
Figure 18 “Short circuit protection via current limitation and thermal switch off , with latched fault
signal on STATUS” on Page 23 shows this behavior.
Datasheet 23 Rev. 1.0
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BTF3050EJ
Smart Low-Side Power Switch
Protection Functions
Figure 18 Short circuit protection via current limitation and thermal switch off , with latched fault
signal on STATUS
Note: For better understanding, the time scale is not linear. The real timing of this drawing is application
dependant and cannot be described.
Datasheet 24 Rev. 1.0
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BTF3050EJ
Smart Low-Side Power Switch
Protection Functions
Behavior with overload current below current limitation trigger level
The lower current limitation level IL(LIM) is also triggered by any thermal shutdown. It can be the case when a
still current, below the overcurrent limitation trigger level (IL < IL(LIM)TRIGGER), provokes an over temperature
shutdown. Any over temperature shutdown disables the IL(LIM)TRIGGER function.
Figure 19 Example of overload behavior with thermal shutdown
Note: For better understanding, the time scale is not linear. The real timing of this drawing is application
dependant and cannot be described.
Datasheet 25 Rev. 1.0
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BTF3050EJ
Smart Low-Side Power Switch
Protection Functions
6.4 Reset conditions
The following table gives the reset conditions of the latched STATUS signal and the IL(LIM)TRIGGER function.
Additionally, both functions are reset when ENABLE=low, regardless of STATUS and IN pin states.
Figure 20 Reset conditions of latched STATUS signal and IL(LIM)TRIGGER function.
Datasheet 26 Rev. 1.0
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BTF3050EJ
Smart Low-Side Power Switch
Diagnostics
7 Diagnostics
The BTF3050EJ provides a latched digital fault feedback signal on the STATUS pin triggered by an over
temperature or dynamic temperature shutdown.
7.1 Functional Description of the STATUS pin
The BTF3xxxEJ series provides digital status information via the STATUS pin to give an alarm feedback to a
possible connected micro controller. See Figure 17 “Thermal protective switch OFF scenario for case of
overload or short circuit” on Page 22.
Normal operation mode
In normal operation (no fault is detected) the STATUS pin is logic “high”. It is pulled up via an external Resistor
with a recommended value of 4.7kΩ. Internally it is connected to an open drain MOSFET via an internal
Resistor.
Fault operation
In case of a temperature shutdown the internal MOSFET of the BTF3xxxEJ series pulls the STATUS pin down to
approx 0.5V, which a connected microcontroller would accept as logic “low” level signal for a 4.7kΩ pull-up
resistor. This mode stays active independent from the input pin state or internal auto-restarts until it is reset.
Reset Latch (external pull up)
To reset the latched STATUS signal, the STATUS pin has to be pulled-up to VDD, for a minimum time of tRESET.
The IN pin state does not matter to reset the latched STATUS signal. See Chapter 11 for an example of basic
circuitry to use this digital feedback function.
Reset IL(LIM)TRIGGER
See Chapter 6.3 for detailed explanation on the function and Chapter 6.4 for a quick overview of reset
mechanism.
7.2 Characteristics
See Table 9.3 “Diagnostics” on Page 34 for electrical characteristics.
Datasheet 27 Rev. 1.0
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BTF3050EJ
Smart Low-Side Power Switch
Supply and Input Stage
8 Supply and Input Stage
8.1 Supply Circuit
The supply pin VDD is protected against ESD pulses as shown in Figure 21.
The device supply is not internally regulated but directly taken from a external supply. Therefore a reverse
polarity protected and buffered (3.0V..5.5V) voltage supply is required. To achieve a reasonable RDS(ON) and the
specified switching speed a 5V supply is required.
Figure 21 Supply Circuit
8.2 Undervoltage Shutdown
In order to ensure a stable and defined device behavior under all allowed conditions the supply voltage VDD is
monitored.
If the supply voltage VDD drops below the switch-off threshold VDD(TH), the power DMOS switches off. In this case
ENABLE pin is pulled to low state and both latched STATUS and IL(LIM)TRIGGER level are reset (See Chapter 6.4,
Reset conditions). All device functions are only specified for supply voltages above the supply voltage
threshold VDD(TH)MAX. There is no fault feedback ensured for VDD <VDD(TH).
8.3 Input/Enable Circuit
Figure 22 shows the IN pin circuit of the BTF3050EJ. Due to an internal pull-down it is ensured that the device
switches off in case of open IN pin. A Zener structure protects the input circuit against ESD pulses.
This structure is also valid for ENABLE pin.
Datasheet 28 Rev. 1.0
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BTF3050EJ
Smart Low-Side Power Switch
Supply and Input Stage
Figure 22 Simplified IN/ENABLE pin circuitry
8.4 Functional Description of the SRP Pin
The BTF3050EJ provides the possibility to adjust slewrate with an external resistor connected to the Slew-
Rate-Preset pin (SRP). It defines the strength of the gate driver stage used to switch the power DMOS. The
greater the resistor the lesser the current driven by the slew rate logic block to the gate driver block, which will
result in a slower turn-on and turn-off. For details on this function please refer to “Adjustable Switching
Speed / Slew Rate” on Page 19.
Figure 23 Simplified functional block diagram of SRP pin
Datasheet 29 Rev. 1.0
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BTF3050EJ
Smart Low-Side Power Switch
Supply and Input Stage
8.5 Characteristics
Please see Table “INPUT” on Page 36, Table “ENABLE” on Page 36 for INPUT and ENABLE electrical
characteristics.
The timings Table shows slew rate for specific resistor values, for the SRP pin electrical characteristics please
see Table “SRP” on Page 36.
Datasheet 30 Rev. 1.0
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BTF3050EJ
Smart Low-Side Power Switch
Electrical Characteristics
9 Electrical Characteristics
Note: Characteristics show the deviation of parameter at given input voltage and junction temperature.
Typical values show the typical parameters expected from manufacturing and in typical application
condition.
All voltages and currents naming and polarity in accordance to
Figure 3 “Naming Definition of electrical parameters” on Page 7
9.1 Power Stage
See Chapter “Power Stage” on Page 15 for parameters description and further details.
Table 5 Electrical Characteristics: Power Stage
TJ = -40°C to +150°C, VDD = 3.0 V to 5.5 V, VBAT = 6 V to 18 V, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Power Stage - Static Characteristics
On-State resistance RDS(ON) –45– mΩIL = IL(NOM);
VDD = 5V;
TJ = 25°C
P_9.1.3
On-State resistance RDS(ON) – 87 100 mΩIL = IL(NOM);
VDD = 5V;
TJ = 150°C
P_9.1.8
Nominal load current IL(NOM) –4– A1)TJ < 150°C;
VDD = 5 V;
P_9.1.33
OFF state load current, Output
leakage current
IL(OFF)25 ––2 µA
2)
VBAT = 13.5 V;
VIN = 0 V;
VDD = 5 V;
TJ ≤85°C
P_9.1.38
OFF state load current, Output
leakage current
IL(OFF)150 –1.24 µAVBAT = 18 V;
VIN = 0 V;
VDD = 5 V;
TJ = 150°C
P_9.1.43
Reverse Diode
Reverse diode forward voltage -VDS –0.81.5VID = - IL(NOM);
VIN = 0 V
P_9.1.50
Power Stage - Dynamic characteristics - switching time adjustment VBAT = 13.5V, VDD = 5 V; resistive load:
RL = 4.7Ω; CSRP-GND < 100 pF;
see also Figure 12 “Definition of Power Output Timing for Resistive Load” on Page 16
Turn-on time tON(0) 0.45 1.35 2.8 µs RSRP = 0Ω
3)
P_9.1.51
Turn-off time tOFF(0) 0.8 2 4 µs RSRP = 0Ω
4)
P_9.1.55
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BTF3050EJ
Smart Low-Side Power Switch
Electrical Characteristics
Turn-on delay time tDON(0) 0.15 0.35 0.8 µs RSRP = 0ΩP_9.1.59
Turn-off delay time tDOFF(0) 0.5 1 2 µs RSRP = 0ΩP_9.1.63
Turn-on output fall time tF(0) 0.3 1 2 µs RSRP = 0ΩP_9.1.67
Turn-off output rise time tR(0) 0.3 1 2 µs RSRP = 0ΩP_9.1.71
Turn-on Slew rate 5) -(DV/Dt)ON(0) 15 27 45 V/µs RSRP = 0Ω
5)
P_9.1.75
Turn-off Slew rate (DV/Dt)OFF(0) 15 27 45 V/µs RSRP = 0Ω
5)
P_9.1.79
Turn-on time tON(5k8) 1.3 2.7 4.5 µs RSRP = 5.8kΩ
3)
P_9.1.52
Turn-off time tOFF(5k8) 246 µsRSRP = 5.8kΩ
4)
P_9.1.56
Turn-on delay time tDON(5k8) 0.3 0.75 1.5 µs RSRP = 5.8kΩP_9.1.60
Turn-off delay time tDOFF(5k8) 123 µsRSRP = 5.8kΩP_9.1.64
Turn-on output fall time tF(5k8) 123 µsRSRP = 5.8kΩP_9.1.68
Turn-off output rise time tR(5k8) 123 µsRSRP = 5.8kΩP_9.1.72
Turn-on Slew rate -(DV/Dt)ON(5k8) 71321V/µsRSRP = 5.8kΩ
5)
P_9.1.76
Turn-off Slew rate (DV/Dt)OFF(5k8) 71321V/µsRSRP = 5.8kΩ
5)
P_9.1.80
Turn-on time tON(58k) 13 26 40 µs RSRP = 58kΩ
3)
P_9.1.53
Turn-off time tOFF(58k) 23 35 70 µs RSRP = 58kΩ
4)
P_9.1.57
Turn-on delay time tDON(58k) 3610µsRSRP = 58kΩP_9.1.61
Turn-off delay time tDOFF(58k) 71535µsRSRP = 58kΩP_9.1.65
Turn-on output fall time tF(58k) 10 20 30 µs RSRP = 58kΩP_9.1.69
Turn-off output rise time tR(58k) 10 20 30 µs RSRP = 58kΩP_9.1.73
Turn-on Slew rate -(DV/Dt)ON(58k) 0.7 1.4 2.1 V/µs RSRP = 58kΩ
5)
P_9.1.77
Turn-off Slew rate (DV/Dt)OFF(58k) 0.7 1.4 2.1 V/µs RSRP = 58kΩ
5)
P_9.1.81
Turn-on time tON(open) 40 80 130 µs RSRP = 200kΩ(open)
3)
P_9.1.54
Turn-off time tOFF(open) 55 110 190 µs RSRP = 200kΩ(open)
4)
P_9.1.58
Turn-on delay time tDON(open) 10 20 40 µs RSRP = 200kΩ(open) P_9.1.62
Table 5 Electrical Characteristics: Power Stage (cont’d)
TJ = -40°C to +150°C, VDD = 3.0 V to 5.5 V, VBAT = 6 V to 18 V, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Datasheet 32 Rev. 1.0
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BTF3050EJ
Smart Low-Side Power Switch
Electrical Characteristics
9.2 Protection
See Chapter “Protection Functions” on Page 21 for parameter description and further details.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions
described in the data sheet. Fault conditions are considered as “outside” normal operating range.
Protection functions are not designed for continuous repetitive operation
Turn-off delay time tDOFF(open) 25 50 100 µs RSRP = 200kΩ(open) P_9.1.66
Turn-on output fall time tF(open) 30 60 90 µs RSRP = 200kΩ(open) P_9.1.70
Turn-off output rise time tR(open) 30 60 90 µs RSRP = 200kΩ(open) P_9.1.74
Turn-on Slew rate -(DV/Dt)ON(open) 0.25 0.5 0.7 V/µs RSRP = 200kΩ(open)
5)
P_9.1.78
Turn-off Slew rate (DV/Dt)OFF(open) 0.25 0.5 0.7 V/µs RSRP = 200kΩ(open)
5)
P_9.1.82
1) Not subject to production test, calculated by RthJA and RDS(ON).(JEDEC2S2P)
2) Not subject to production test, specified by design
3) Not subject to production test, calculated by (tDON + tF)
4) Not subject to production test, calculated by (tDOFF + tR)
5) Not subject to production test, calculated slew rate between 90% and 50%; see Figure 12 “Definition of Power
Output Timing for Resistive Load” on Page 16
Table 6 Electrical characteristics: Protection
TJ = -40°C to +150°C, VDD = 3.0 V to 5.5 V; VBAT = 6 V to 18 V, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Thermal shut down 1)
Thermal shut down
junction temperature
TJ(SD) 150 175 200 °C 1) P_9.2.1
Thermal hysteresis ΔTJ_HYS –15–K
1) P_9.2.3
Dynamic temperature limitation ΔTJ(SW) –70–K
1) P_9.2.4
Over Voltage Protection / Clamping
Drain clamp voltage VOUT(CLAMP) 40 – – V VIN = 0 V; IL= 10
mA;
P_9.2.7
Table 5 Electrical Characteristics: Power Stage (cont’d)
TJ = -40°C to +150°C, VDD = 3.0 V to 5.5 V, VBAT = 6 V to 18 V, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Datasheet 33 Rev. 1.0
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BTF3050EJ
Smart Low-Side Power Switch
Electrical Characteristics
Current limitation
Current limitation trigger level IL(LIM)TRIGGER 29 43 58 A VIN = 5V;
VDD = 5V;
VEN=5V
P_9.2.10
Current limitation level IL(LIM) 10 - 20 A VIN = 5V;
VDD = 5V;
VEN=5V
settled value
P_9.2.15
1) Not subject to production test, specified by design.
Table 6 Electrical characteristics: Protection (cont’d)
TJ = -40°C to +150°C, VDD = 3.0 V to 5.5 V; VBAT = 6 V to 18 V, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Datasheet 34 Rev. 1.0
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BTF3050EJ
Smart Low-Side Power Switch
Electrical Characteristics
9.3 Diagnostics
See Chapter “Diagnostics” on Page 26 for description and further details.
Table 7 Electrical Characteristics: Diagnostics
TJ = -40°C to +150°C, VDD = 3.0 V to 5.5 V, VBAT = 6 V to 18 V, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Feedback pin
STATUS pin voltage operation
range
VSTATUS -0.3 – 5.5 V
STATUS Pin voltage drop Fault VSTATUS(FAULT) –0.50.8VI
STATUS(FAULT)=1mA P_9.3.2
STATUS Pin reset current ISTATUS(RESET) 5–7mA– P_9.3.3
STATUS Pin reset threshold
voltage
VSTATUS(RESET) 0.9 2.0 2.5 V – P_9.3.6
STATUS Pin leakage current
(85°C)
ISTATUS(85) 1.5 6 µA VSTATUS ≤ 5.5V
TJ ≤ 85°C
1)
1) Not subject to production test, specified by design.
P_9.3.4
STATUS Pin leakage current
(150°C)
ISTATUS(150) 612µAVSTATUS ≤ 5V
TJ = 150°C
P_9.3.5
Fault feedback reset time tRESET 20 – – µs VSTATUS > VSTATUS(RESET) P_9.3.7
Datasheet 35 Rev. 1.0
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BTF3050EJ
Smart Low-Side Power Switch
Electrical Characteristics
9.4 Supply and Input Stage
See Chapter “Supply and Input Stage” on Page 27 for description and further details.
Table 8 Electrical Characteristics: Supply and Input
TJ = -40°C to +150°C, VDD = 3.0 V to 5.5 V, VBAT = 6 V to 18 V, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Supply
Nominal supply voltage VDD(NOM) 3.0 5.0 5.5 V – P_9.4.1
Supply ON/OFF threshold voltage VDD(TH) 1.3 2.4 3.0 V VIN = 5.0V; VBAT=13.5V;
VEN= 5V;
VIN= 5V;
P_9.4.2
Supply current,
continuous ON operation
IDD(ON) –1.32.5mAVDD = 5.0V;
RSRP = 0Ω;
VEN= 5V;
IOUT(0) = IOUT(NOM)
P_9.4.5
Supply current,
inverse condition on OUT to GND,
ON mode
IDD_ON(-VOUT) –0.72.5mAVOUT < -0.3V;
VDD = 5.5V;
VEN= 5V;
VIN= 5V;
IL =-IL(NOM)
P_9.4.9
Supply current,
inverse condition on OUT to GND,
OFF mode
IDD_OFF(-VOUT) – – 200 µA VOUT < -0.3V;
VDD= 5.5V;
VEN= 5V;
VIN= 0V;
IL =-IL(NOM)
P_9.4.10
Standby supply current IDD(OFF) –1.56 µA
1)VIN = 0V;
VDD = 5.0V;
RSRP = 0Ω;
VEN= 0V;
TJ ≤ 85°C
P_9.4.11
Standby supply current,
maximum at 150°C
IDD(OFF)_150 –614µAVIN = 0V;
VDD = 5.0V;
RSRP = 0Ω;
VEN= 0V;
TJ = 150°C
P_9.4.12
Datasheet 36 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Electrical Characteristics
INPUT
Input Voltage VIN -0.3 – 5.5 V –
Low level input voltage VIN(L) -0.3 – 0.8 V – P_9.4.14
High level input voltage VIN(H) 2.0 – VDD V– P_9.4.15
Input voltage hysteresis VIN(HYS) – 200 – mV – P_9.4.16
Input pull down current IIN – – 160 µA 2.7V < VIN < 5.5V
-0.3V < VDD < 5.5V
P_9.4.17
Internal Input pull down resistor RIN(GND) 25 50 100 kΩ–P_9.4.18
ENABLE
ENABLE Voltage VENABLE -0.3 – 5.5 V –
Low level ENABLE voltage VENABLE(L) -0.3 – 0.8 V – P_9.4.20
High level ENABLEvoltage VENABLE(H) 2.0 – VDD V– P_9.4.21
ENABLE voltage hysteresis VENABLE(HYS) – 200 – mV – P_9.4.22
ENABLE pull down current IENABLE – – 160 µA 2.7V < VIN < 5.5V
-0.3V < VDD < 5.5V
P_9.4.23
Internal ENABLE pull down resistor RENABLE(GND) 25 50 100 kΩ–P_9.4.24
ENABLE masking time tENABLE(MASKING) 4816µs– P_9.4.25
SRP
SRP resistor range for adjustable
operation
RSRP(NOR) 5–70KΩ1) P_9.4.26
SRP resistor range for fast
operation
RSRP(EXTF) 0–1.5KΩ1) P_9.4.27
SRP resistor range for slow
operation
RSRP(EXTS) 160 – – KΩ1) P_9.4.28
1) Not subject to production test, specified by design.
Table 8 Electrical Characteristics: Supply and Input (cont’d)
TJ = -40°C to +150°C, VDD = 3.0 V to 5.5 V, VBAT = 6 V to 18 V, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Datasheet 37 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Characterization Results
10 Characterization Results
10.1 Power Stage
Figure 24 RDS(ON) vs. VDD @ TJ=-40, 25, 85, 150°C, IL=IL(NOM); VIN= VENABLE= 5V; VDD= 3...5.5V; RSRP= 0Ω
Datasheet 38 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Characterization Results
Figure 25 IDD(ON) vs. RSRP @ TJ=-40, 25, 150°C, IL=IL(NOM); VIN = VENABLE= VDD= 5V
Figure 26 RDS(ON) vs. TJ @ VDD=3V, 5V; VIN = VENABLE = 5V; TJ= -40, 25, 85, 150°C;
Datasheet 39 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Characterization Results
Figure 27 IL(OFF) vs. TJ @ VIN = 0V; VENABLE= VDD= 5V; TJ= -40, -20, 0, 25, 50, 85, 105, 125, 150°C; VBAT =
13.5V, 18V, 31V
Figure 28 IL(OFF) vs. VBAT =0..40V @ TJ= -40, 25, 85, 150°C; VIN = 0V; VENABLE= VDD= 5V
Datasheet 40 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Characterization Results
Figure 29 EAS vs. IL @ TJ(0)=25°C, 150°C, VBAT=13.5V; VIN = VENABLE = VDD= open; IL=IL(NOM) /4, IL(NOM)/2,
IL(NOM), 2*IL(NOM)
Figure 30 EAR_10k, _100k vs. IL @ TJ(0)=25°C, 105°C, VBAT= 13.5V; VIN = VENABLE = VDD= 5V; IL =IL(NOM), 2*IL(NOM)
Datasheet 41 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Characterization Results
Figure 31 EAR vs. cycles @ TJ(0)=25°C, 105°C, VBAT = 13.5V; VIN = VENABLE = VDD= 5V; IL = IL(NOM), 2*IL(NOM)
Datasheet 42 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Characterization Results
Figure 32 tF, tR, tDON, tDOFF vs. RSRP; VIN = VENABLE= VDD= 5V; VBAT= 13.5V; RL=4.7Ω; TJ = -40, 25, 150°C
Datasheet 43 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Characterization Results
Figure 33 -(ΔV/Δt)ON, (ΔV/Δt)OFF vs. RSRP; VIN = VENABLE = VDD= 5V; VBAT = 13.5V; RL=4.7Ω; TJ= -40, 25, 150°C
Datasheet 44 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Characterization Results
Figure 34 tF, tR, tDON, tDOFFvs. VDD=3..5.5V @ VBAT=13.5V; TJ= -40, 25, 150°C; RSRP = 5.8kΩ; VIN = VENABLE =
5V; RL=4.7Ω;
Datasheet 45 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Characterization Results
Figure 35 tF, tR, tDON, tDOFF vs. VBAT=3..31V @ VDD=5V; VIN = VENABLE= VDD = 5V; RL = 4.7Ω; RSRP=5.8kΩ, open;
TJ= -40, 25, 150°C
Datasheet 46 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Characterization Results
Figure 36 Slewrates (-(ΔV/Δt)ON, (ΔV/Δt)OFF vs. VBAT @ TJ = -40, 25, 150°C; RL=4.7Ω; RSRP= 5.8kΩ; VIN =
VDD = VENABLE= 5V; VBAT = 3..31V
Datasheet 47 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Characterization Results
Figure 37 tF, tR, tDON, tDOFF vs. TJ= -40; 25; 150°C @ RSRP= 5.8kΩ; VIN= VENABLE = VDD = 5V; VBAT = 13.5V; RL=
4.7Ω
Datasheet 48 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Characterization Results
Figure 38 tF, tR, tDON, tDOFF vs. RL @ RSRP= 5.8kΩ; VIN= VENABLE= VDD= 5V; VBAT = 13.5V; TJ = -40, 25, 150°C
Datasheet 49 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Characterization Results
10.2 Protection
Figure 39 TJ(SD) vs. VDD; VIN=VENABLE= 5V; VDD= 3V...5.5V; IL= 10mA
Figure 40 VOUT(clamp) vs. TJ; VIN= 0V;VENABLE= VDD= 5V; IL= 10mA
Datasheet 50 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Characterization Results
Figure 41 IL(LIM)TRIGGER peak vs. VDD=3...5.5V@ TJ= -40, 25, 85, 150°C; VIN= PWM 5V in SOA; VENABLE= 5V;
VBAT= 13.5V; RL= 4.7Ω
Figure 42 IL(LIM) vs. VDD= 3V...5.5V @ TJ = -40, 25, 150°C; VENABLE=VIN= 5V; VBAT= 13.5V
Datasheet 51 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Characterization Results
10.3 Diagnostics
Figure 43 ISTATUS vs. VDD = 3V...5.5V@ TJ= -40, 25, 150°C; VENABLE= VIN= 5V; VBAT= 13.5V;
Figure 44 VSTATUS in fault mode vs. VDD = 3V...5V@ TJ = -40, 25, 150°C; VIN = VENABLE= 5V; VBAT= 13.5V;
Datasheet 52 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Characterization Results
10.4 Supply and Input Stage
Figure 45 VDD(TH) vs. TJ = -40, 25, 150°C; VIN=VENABLE= 5V; RL= 4.7Ω; VBAT= 13.5V; RSRP= 0Ω
Figure 46 IDD(ON) vs. VDD = 3V...5.5V@ TJ = -40, 25, 85, 150°C; VIN = VENABLE = 5V; RSRP= 0Ω; VBAT = 13.5V;
Datasheet 53 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Characterization Results
Figure 47 IDD(OFF) vs. TJ @ VDD = 3, 4, 5V; VIN = VENABLE = 0V;
Figure 48 IIN vs. VIN = -0.3V...5.5V@ TJ = -40, 25, 150°C; VDD = VENABLE= 5V;
Datasheet 54 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Characterization Results
Figure 49 VIN(L), VIN(H) vs. TJ @ VDD = 5V; VENABLE= 5V; IL= 1.4 mA; RSRP= 0Ω; VIN= 0V...5.5V; VBAT= 13.5V;
Figure 50 VEN(L), VEN(H) vs. TJ @ VDD = 5V; VBAT= 13.5V; IL= 1.4mA; RSRP= 0Ω; VEN= 0V...5.5V; VBAT= 13.5V;
Datasheet 55 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Application Information
11 Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not
be regarded as a description or warranty of a certain functionality, condition or quality of the device.
Application Diagram
An application example with the BTF3050EJ is shown below.
Figure 51 Simplified application diagram
Note: This is a very simplified example of an application circuit. The function must be verified in the real
application.
Table 9 Pin description for simplified application diagram
Reference Value Purpose
RSTATUS 4.7kΩPulls-up the STATUS pin
RSRP kΩSRP resistor
CSRP-GND < 100pF maximum permitted parasitic capacitance at the SRP pin
CVDD 100nF Filter capacitor on supply pin
Datasheet 56 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Application Information
11.1 Design and Layout Recommendations/Considerations
As consequence of the fast switching times for high currents, special care has to be taken to the PCB layout.
Stray inductances have to be minimized. The BTF3050EJ has no separate pin for power ground and logic
ground. Therefore it is recommended to assure that the offset between the ground connection of the slew rate
resistor and ground pin of the device (GND/SOURCE) is minimized. The resistor RSRP should be placed near to
the device and directly connected to the GND pin of the device to avoid any influence of GND shift to the
functionality of the SRP pin.
In order to avoid influence on SRP functionality (e.g. switching times..) the maximum capacitance on SRP pin
to GND (CSRP-GND) has to be less than 100pF. This has to be considered by a proper layout also taking into
account of parasitic capacitors.
It is recommended not to let the SRP pin floating. A maximum resistor of 200 kOhm to GND is recommended.
Datasheet 57 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Package information
12 Package information
Figure 52 PG-TDSO-8-31
1)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Further information on packages
https://www.infineon.com/packages
1) Dimension in mm
Datasheet 58 Rev. 1.0
2018-08-08
BTF3050EJ
Smart Low-Side Power Switch
Revision History
13 Revision History
Revision Date Changes
Rev. 1.0 2018-08-08 First Release
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2018-08-08
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2018 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about any
aspect of this document?
Email: erratum@infineon.com
Document reference
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characteristics ("Beschaffenheitsgarantie").
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values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
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