LTC2208-14
1
220814fb
14-Bit, 130Msps ADC
The LTC
®
2208-14 is a 130Msps, sampling 14-bit A/D
converter designed for digitizing high frequency, wide
dynamic range signals with input frequencies up to
700MHz. The input range of the ADC can be optimized
with the PGA front end.
The LTC2208-14 is perfect for demanding communications
applications, with AC performance that includes 77.1dBFS
Noise Floor and 98dB spurious free dynamic range (SFDR).
Ultralow jitter of 70fsRMS allows undersampling of high
input frequencies with excellent noise performance.
Maximum DC specs include ±1.5LSB INL, ±0.5LSB DNL
(no missing codes).
The digital output can be either differential LVDS or
single-ended CMOS. There are two format options for the
CMOS outputs: a single bus running at the full data rate or
demultiplexed buses running at half data rate. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.6V.
The ENC+ and ENC– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed with a wide range of
clock duty cycles.
n Telecommunications
n Receivers
n Cellular Base Stations
n Spectrum Analysis
n Imaging Systems
n ATE
n Sample Rate: 130Msps
n 77.1dBFS Noise Floor
n 98dB SFDR
n SFDR >81dB at 250MHz (1.5VP-P Input Range)
n PGA Front End (2.25VP-P or 1.5VP-P Input Range)
n 700MHz Full Power Bandwidth S/H
n Optional Internal Dither
n Optional Data Output Randomizer
n LVDS or CMOS Outputs
n Single 3.3V Supply
n Power Dissipation: 1.32W
n Clock Duty Cycle Stabilizer
n Pin Compatible 16-Bit Version
130Msps: LTC2208 (16-Bit)
n 64-Pin (9mm × 9mm) QFN Package
32k Point FFT, fIN = 15.11MHz,
–1dB, PGA = 0, RAND “On”,
Dither “OFF”
–
+
S/H
AMP
CORRECTION
LOGIC AND
SHIFT REGISTER
OUTPUT
DRIVERS
14-BIT
PIPELINED
ADC CORE
INTERNAL ADC
REFERENCE
GENERATOR
1.25V
COMMON MODE
BIAS VOLTAGE
CLOCK/DUTY
CYCLE
CONTROL
D13
•
•
•
D0
PGA SHDN DITH MODE LVDS RAND
VCM
ANALOG
INPUT
220814 TA01
CMOS
OR
LVDS
0.5V TO 3.6V
3.3V
3.3V
SENSE
OGND
OVDD
2.2μF 0.1μF
0.1μF
0.1μF
0.1μF
VDD
GND
ADC CONTROL INPUTS
AIN+
ENC +
AIN–
ENC –
OF
CLKOUT
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–80
–20
–10
0
20 40 50
220814 G05
–100
–110
–40
–60
–90
–30
–120
–50
–70
10 30 60
TYPICAL APPLICATION
DESCRIPTION
FEATURES
APPLICATIONS
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
LTC2208-14
2
220814fb
Supply Voltage (VDD) ................................... –0.3V to 4V
Digital Output Ground Voltage (OGND) ........ –0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V)
Digital Input Voltage .................... –0.3V to (VDD + 0.3V)
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Power Dissipation ............................................ 2000mW
Operating Temperature Range
LTC2208C-14 ........................................... 0°C to 70°C
LTC2208I-14 ........................................–40°C to 85°C
Storage Temperature Range ..................–65°C to 150°C
Digital Output Supply Voltage (OVDD) .......... –0.3V to 4V
OVDD = VDD (Notes 1 and 2)
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2208CUP-14#PBF LTC2208CUP-14#TRPBF LTC2208UP-14 64-Lead (9mm × 9mm) Plastic Plastic QFN 0°C to 70°C
LTC2208IUP-14#PBF LTC2208IUP-14#TRPBF LTC2208UP-14 64-Lead (9mm × 9mm) Plastic Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
CONVERTER CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Integral Linearity Error Differential Analog Input (Note 5) l±1±1.5 LSB
Differential Linearity Error Differential Analog Input l±0.2 ±0.5 LSB
Offset Error (Note 6) l±2±10.8 mV
Offset Drift ±10 μV/°C
Gain Error External Reference l±0.2 ±2.3 %FS
Full-Scale Drift Internal Reference
External Reference
±30
±15
ppm/°C
ppm/°C
Transition Noise External Reference 0.8 LSBRMS
TOP VIEW
65
UP PACKAGE
64-LEAD (9mm s 9mm) PLASTIC QFN
SENSE 1
GND 2
VCM 3
GND 4
VDD 5
VDD 6
GND 7
AIN+8
AIN– 9
GND 10
GND 11
ENC+ 12
ENC– 13
GND 14
VDD 15
VDD 16
48 D9+/DA4
47 D9–/DA3
46 D8+/DA2
45 D8–/DA1
44 D7+/DA0
43 D7–/DNC
42 D6+/DNC
41 D6–/CLKOUTA
40 CLKOUT+/CLKOUTB
39 CLKOUT–/OFB
38 D5+/DB13
37 D5_/DB12
36 D4+/DB11
35 D4–/DB10
34 D3+/DB9
33 D3–/DB8
64 PGA
63 RAND
62 MODE
61 LVDS
60 OF+/0FA
59 OF–/DA13
58 D13+/DA12
57 D13–/DA11
56 D12+/DA10
55 D12–/DA9
54 D11+/DA8
53 D11–/DA7
52 D10+/DA6
51 D10–/DA5
50 OGND
49 OVDD
VDD 17
GND 18
SHDN 19
DITH 20
NC 21
NC 22
DNC/DB0 23
DNC/DB1 24
D0–/DB2 25
D0+/DB3 26
D1–/DB4 27
D1+/DB5 28
D2–/DB6 29
D2+/DB7 30
OGND 31
OVDD 32
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB BOARD
TJMAX = 150°C, θJA = 20°C/W
LTC2208-14
3
220814fb
The l denotes the specifi cations which apply over the full operating temperature range, otherwise
specifi cations are at TA = 25°C. (Note 4)
ANALOG INPUT
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Analog Input Range (AIN+ – AIN–) 3.135V ≤ VDD ≤ 3.465V 1.5 to 2.25 VP-P
VIN, CM Analog Input Common Mode Differential Input (Note 7) l1 1.25 1.5 V
IIN Analog Input Leakage Current 0V ≤ AIN+, AIN– ≤ VDD l–1 1 μA
ISENSE SENSE Input Leakage Current 0V ≤ SENSE ≤ VDD l–3 3 μA
IMODE MODE Pin Pull-Down Current to GND 10 μA
ILVD S LVDS Pin Pull-Down Current to GND 10 μA
CIN Analog Input Capacitance Sample Mode ENC+ < ENC–
Hold Mode ENC+ > ENC–6.5
1.8
pF
pF
tAP Sample-and-Hold
Acquisition Delay Time
1ns
tJITTER Sample-and-Hold
Acquisition Delay Time Jitter
70 fsRMS
CMRR Analog Input
Common Mode Rejection Ratio
1V < (AIN+ = AIN–) <1.5V 80 dB
BW-3dB Full Power Bandwidth RS ≤ 25Ω700 MHz
The l denotes the specifi cations which apply over the full operating temperature range,
otherwise specifi cations are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio 5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
77.1
74.9
dBFS
dBFS
30MHz Input (2.25V Range, PGA = 0), TA = 25ºC
30MHz Input (2.25V Range, PGA = 0)
30MHz Input (1.5V Range, PGA = 1)
l
75.7
75.4
77
77
74.9
dBFS
dBFS
dBFS
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
76.9
74.8
dBFS
dBFS
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1), TA = 25ºC
140MHz Input (1.5V Range, PGA = 1) l
73.5
73.3
76.4
74.6
74.6
dBFS
dBFS
dBFS
250MHz Input (2.25V Range, PGA = 0)
250MHz Input (1.5V Range, PGA = 1)
75
73.6
dBFS
dBFS
SFDR Spurious Free
Dynamic Range
2nd or 3rd
Harmonic
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
98
98
dBc
dBc
30MHz Input (2.25V Range, PGA = 0)
30MHz Input (1.5V Range, PGA = 1)
l84 96
98
dBc
dBc
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
90
93
dBc
dBc
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1) l81.5
85
95
dBc
dBc
250MHz Input (2.25V Range, PGA = 0)
250MHz Input (1.5V Range, PGA = 1)
76
81
dBc
dBc
DYNAMIC ACCURACY
LTC2208-14
4
220814fb
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SFDR Spurious Free
Dynamic Range
4th Harmonic
or Higher
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
100
100
dBc
dBc
30MHz Input (2.25V Range, PGA = 0)
30MHz Input (1.5V Range, PGA = 1)
l87 100
100
dBc
dBc
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
100
100
dBc
dBc
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1) l85
95
95
dBc
dBc
250MHz Input (2.25V Range, PGA = 0)
250MHz Input (1.5V Range, PGA = 1)
90
90
dBc
dBc
S/(N+D) Signal-to-Noise
Plus Distortion Ratio
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
77
74.8
dBFS
dBFS
30MHz Input (2.25V Range, PGA = 0), TA = 25ºC
30MHz Input (2.25V Range, PGA = 0
30MHz Input (1.5V Range, PGA = 1)
l
75.4
75.1
76.9
76.9
74.7
dBFS
dBFS
dBFS
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
76.6
74.6
dBFS
dBFS
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1), TA = 25ºC
140MHz Input (1.5V Range, PGA = 1) l
73.4
73
76.3
74.5
74.5
dBFS
dBFS
dBFS
250MHz Input (2.25V Range, PGA = 0)
250MHz Input (1.5V Range, PGA = 1)
73.6
72.9
dBFS
dBFS
SFDR Spurious Free Dynamic Range
at –25dBFS
Dither “OFF”
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
105
105
dBFS
dBFS
30MHz Input (2.25V Range, PGA = 0)
30MHz Input (1.5V Range, PGA = 1)
105
105
dBFS
dBFS
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
105
105
dBFS
dBFS
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
100
100
dBFS
dBFS
250MHz Input (2.25V Range, PGA = 0)
250MHz Input (1.5V Range, PGA = 1)
100
100
dBFS
dBFS
SFDR Spurious Free Dynamic Range
at –25dBFS
Dither “ON”
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
115
115
dBFS
dBFS
30MHz Input (2.25V Range, PGA = 0)
30MHz Input (1.5V Range, PGA = 1)
l95 110
110
dBFS
dBFS
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
110
110
dBFS
dBFS
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
107
107
dBFS
dBFS
250MHz Input (2.25V Range, PGA = 0)
250MHz Input (1.5V Range, PGA = 1)
105
105
dBFS
dBFS
The l denotes the specifi cations which apply over the full operating temperature range,
otherwise specifi cations are at TA = 25°C. AIN = –1dBFS. (Note 4)
DYNAMIC ACCURACY
LTC2208-14
5
220814fb
The l denotes the specifi cations which apply over
the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)
COMMON MODE BIAS CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCM Output Voltage IOUT = 0 1.15 1.25 1.35 V
VCM Output Tempco IOUT = 0 40 ppm/°C
VCM Line Regulation 3.135V ≤ VDD ≤ 3.465V 1 mV/ V
VCM Output Resistance | IOUT | ≤ 1mA 2 Ω
The l denotes the specifi cations which apply over the
full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)
DIGITAL INPUTS AND DIGITAL OUTPUTS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ENCODE INPUTS (ENC+, ENC–)
VID Differential Input Voltage (Note 7) l0.2 V
VICM Common Mode Input Voltage Internally Set
Externally Set (Note 7) 1.2
1.6
3
V
RIN Input Resistance (See Figure 2) 6 kΩ
CIN Input Capacitance (Note 7) 3 pF
LOGIC INPUTS (DITH, PGA, SHDN, RAND)
VIH High Level Input Voltage VDD = 3.3V l2V
VIL Low Level Input Voltage VDD = 3.3V l0.8 V
IIN Digital Input Current VIN = 0V to VDD l±10 μA
CIN Digital Input Capacitance (Note 7) 1.5 pF
LOGIC OUTPUTS (CMOS MODE)
OVDD = 3.3V
VOH High Level Output Voltage VDD = 3.3V IO = –10μA
IO = –200μA l3.1
3.299
3.29
V
V
VOL Low Level Output Voltage VDD = 3.3V IO = 160μA
IO = 1.60mA l
0.01
0.1 0.4
V
V
ISOURCE Output Source Current VOUT = 0V –50 mA
ISINK Output Sink Current VOUT = 3.3V 50 mA
OVDD = 2.5V
VOH High Level Output Voltage VDD = 3.3V IO = –200μA 2.49 V
VOL Low Level Output Voltage VDD = 3.3V IO = 1.6mA 0.1 V
OVDD = 1.8V
VOH High Level Output Voltage VDD = 3.3V IO = –200μA 1.79 V
VOL Low Level Output Voltage VDD = 3.3V IO = 1.6mA 0.1 V
LOGIC OUTPUTS (LVDS MODE)
STANDARD LVDS
VDD Differential Output Voltage 100Ω Differential Load l247 350 454 mV
VOS Output Common Mode Voltage 100Ω Differential Load l1.125 1.2 1.375 V
LOW POWER LVDS
VDD Differential Output Voltage 100Ω Differential Load l125 175 250 mV
VOS Output Common Mode Voltage 100Ω Differential Load l1.125 1.2 1.375 V
LTC2208-14
6
220814fb
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSSampling Frequency (Note 8) l1 130 MHz
tLENC Low Time Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
l
l
3.65
2.6
3.846
3.846
1000
1000
ns
ns
tHENC High Time Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
l
l
3.65
2.6
3.846
3.846
1000
1000
ns
ns
tAP Sample-and-Hold Aperture Delay –1 ns
LVDS OUTPUT MODE (STANDARD AND LOW POWER)
tDENC to DATA Delay (Note 7) l1.3 2.5 3.8 ns
tCENC to CLKOUT Delay (Note 7) l1.3 2.5 3.8 ns
tSKEW DATA to CLKOUT Skew (tC-tD) (Note 7) l–0.6 0 0.6 ns
tRISE Output Rise Time 0.5 ns
tFALL Output Fall Time 0.5 ns
Data Latency Data Latency 7 Cycles
CMOS OUTPUT MODE
tDENC to DATA Delay (Note 7) l1.3 2.7 4 ns
tCENC to CLKOUT Delay (Note 7) l1.3 2.7 4 ns
tSKEW DATA to CLKOUT Skew (tC-tD) (Note 7) l–0.6 0 0.6 ns
Data Latency Data Latency Full Rate CMOS
Demuxed
7
7
Cycles
Cycles
TIMING CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 8) l3.135 3.3 3.465 V
PSHDN Shutdown Power SHDN = VDD 0.2 mW
STANDARD LVDS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) l3 3.3 3.6 V
IVDD Analog Supply Current l401 470 mA
IOVDD Output Supply Voltage l71 90 mA
PDIS Power Dissipation l1498 1782 mW
LOW POWER LVDS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) l3 3.3 3.6 V
IVDD Analog Supply Current l401 470 mA
IOVDD Output Supply Voltage l40 50 mA
PDIS Power Dissipation l1356 1650 mW
CMOS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) l0.5 3.6 V
IVDD Analog Supply Current l401 470 mA
PDIS Power Dissipation l1320 1551 mW
POWER REQUIREMENTS
LTC2208-14
7
220814fb
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND, with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3.3V, fSAMPLE = 130MHz, LVDS outputs, differential ENC+/
ENC– = 2VP-P sine wave with 1.6V common mode, input range = 2.25VP-P
with differential drive (PGA = 0), unless otherwise specifi ed.
Note 5: Integral nonlinearity is defi ned as the deviation of a code from a “best
fi t straight line” to the transfer curve. The deviation is measured from the
center of the quantization band.
Note 6: Offset error is the offset voltage measured from –1/2LSB when the
output code fl ickers between 00 0000 0000 0000 and 11 1111 1111 1111 in
2’s complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: Recommended operating conditions.
LVDS Output Mode Timing
All Outputs are Differential and Have LVDS Levels
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAM
tH
tD
tC
tL
N – 7 N – 6 N – 5 N – 4 N – 3
ANALOG
INPUT
ENC–
ENC+
CLKOUT–
CLKOUT+
D0-D13, OF
220814 TD01
tAP N + 1
N + 2
N + 4
N + 3
N
LTC2208-14
8
220814fb
Demultiplexed CMOS Output Mode Timing
All Outputs are Single-Ended and Have CMOS Levels
Full-Rate CMOS Output Mode Timing
All Outputs are Single-Ended and Have CMOS Levels
tAP
ANALOG
INPUT
tH
tD
tC
tL
N – 7 N – 6 N – 5 N – 4 N – 3
ENC–
ENC+
CLKOUTA
CLKOUTB
DA0-DA13, OFA
DB0-DB13, OFB
220814 TD02
HIGH IMPEDANCE
N + 1
N + 2
N + 4
N + 3
N
tH
tD
tD
tC
tL
N – 8 N – 6 N – 4
N – 7 N – 5 N – 3
ENC–
ENC+
CLKOUTA
CLKOUTB
DA0-DA13, OFA
DB0-DB13, OFB
220814 TD03
tAP
ANALOG
INPUT
N + 1
N + 2
N + 4
N + 3
N
TIMING DIAGRAM
LTC2208-14
9
220814fb
Integral Nonlinearity (INL)
vs Output Code
Differential Nonlinearity (DNL)
vs Output Code AC Grounded Input Histogram
32k Point FFT, fIN = 5.21MHz,
–1dBFS, PGA = 0, RAND = “On”,
Dither “Off”
OUTPUT CODE
0
–1.0
INL ERROR (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
4096 8192
220814 G01
–0.6
0.6
0.8
0.2
12288 16384
OUTPUT CODE
0
–0.5
DNL ERROR (LSB)
–0.4
–0.2
–0.1
0
0.5
0.2
4096 8192
220814 G02
–0.3
0.3
0.4
0.1
12288 16384
OUTPUT CODE
8176
COUNT
150000
200000
250000
8184
220814 G03
100000
50000
08178 8180 8182 8186
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–80
–20
–10
0
20 40 50
220814 G04
–100
–110
–40
–60
–90
–30
–120
–50
–70
10 30 60
32k Point FFT, fIN = 15.11MHz,
–1dBFS, PGA = 0, RAND = “On”,
Dither “Off”
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–80
–20
–10
0
20 40 50
220814 G05
–100
–110
–40
–60
–90
–30
–120
–50
–70
10 30 60
128k Point FFT, fIN = 15.11MHz,
–40dBFS, PGA = 0, RAND = “On”,
Dither “Off”
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–80
–20
–10
0
20 40 50
220814 G06
–100
–110
–40
–60
–90
–30
–120
–50
–70
10 30 60
128k Point FFT, fIN = 15.11MHz,
–40dBFS, PGA = 0, RAND = “On”,
Dither “On”
32k Point 2-Tone FFT, fIN = 20.14MHz
and 14.25MHz, –7dBFS, PGA = 0,
RAND = “On”, Dither “Off”
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–80
–20
–10
0
20 40 50
220814 G07
–100
–110
–40
–60
–90
–30
–120
–50
–70
10 30 60
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–80
–20
–10
0
20 40 50
220814 G08
–100
–110
–40
–60
–90
–30
–120
–50
–70
10 30 60
32k Point 2-Tone FFT, fIN = 20.14MHz
and 14.25MHz, –25dBFS, PGA = 0,
RAND = “On”, Dither “Off”
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–80
–20
–10
0
20 40 50
220814 G09
–100
–110
–40
–60
–90
–30
–120
–50
–70
10 30 60
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2208-14
10
220814fb
SFDR vs Input Level, fIN = 15.1MHz,
PGA = 0, RAND = “On”, Dither “Off”
INPUT LEVEL (dBFS)
–80
0
SFDR (dBc AND dBFS)
20
40
60
80
–60 –40 –20 0
220814 G10
100
120
–70 –50 –30 –10
32k Point FFT, fIN = 30.11MHz,
–1dBFS, PGA = 0, RAND = “On”,
Dither “Off”
INPUT LEVEL (dBFS)
–80
0
SFDR (dBc AND dBFS)
20
40
60
80
–60 –40 –20 0
220814 G11
100
120
–70 –50 –30 –10
SFDR vs Input Level, fIN = 15.1MHz,
PGA = 0, RAND = “On”, Dither “On”
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–80
–20
–10
0
20 40 50
220814 G12
–100
–110
–40
–60
–90
–30
–120
–50
–70
10 30 60
32k Point FFT, fIN = 30.11MHz,
–25dBFS, PGA = 0, RAND = “On”,
Dither “On”
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–80
–20
–10
0
20 40 50
220814 G13
–100
–110
–40
–60
–90
–30
–120
–50
–70
10 30 60
32k Point FFT, fIN = 70.11MHz,
–1dBFS, PGA = 0, RAND = “On”,
Dither “Off”
32k Point FFT, fIN = 70.11MHz,
–10dBFS, PGA = 0, RAND = “On”,
Dither “Off”
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–80
–20
–10
0
20 40 50
220814 G15
–100
–110
–40
–60
–90
–30
–120
–50
–70
10 30 60
128k Point FFT, fIN = 70.11MHz,
–40dBFS, PGA = 0, RAND = “On”,
Dither “Off”
128k Point FFT, fIN = 70.11MHz,
–40dBFS, PGA = 0, RAND = “On”,
Dither “On”
32k Point FFT, fIN = 70.11MHz,
–1dBFS, PGA = 1, RAND = “On”,
Dither “Off”
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–80
–20
–10
0
20 40 50
220814 G16
–100
–110
–40
–60
–90
–30
–120
–50
–70
10 30 60
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–80
–20
–10
0
20 40 50
220814 G17
–100
–110
–40
–60
–90
–30
–120
–50
–70
10 30 60
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–80
–20
–10
0
20 40 50
220814 G18
–100
–110
–40
–60
–90
–30
–120
–50
–70
10 30 60
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–80
–20
–10
0
20 40 50
220814 G14
–100
–110
–40
–60
–90
–30
–120
–50
–70
10 30 60
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2208-14
11
220814fb
SFDR vs Input Level, fIN = 70.2MHz,
PGA = 0, RAND = “On”, Dither “Off”
SFDR vs Input Level, fIN = 70.2MHz,
PGA = 0, RAND = “On”, Dither “On”
32k Point 2-Tone FFT, fIN = 67.2MHz
and 74.4MHz, –15dBFS, PGA = 0,
RAND = “On”, Dither “Off”
32k Point FFT, fIN = 140.11MHz,
–1dBFS, PGA = 0, RAND = “On”,
Dither “Off”
32k Point FFT, fIN = 140.11MHz,
–1dBFS, PGA = 1, RAND = “On”,
Dither “Off”
32k Point FFT, fIN = 170.1MHz,
–1dBFS, PGA = 1, RAND = “On”,
Dither “Off”
INPUT LEVEL (dBFS)
–80
0
SFDR (dBc AND dBFS)
20
40
60
80
–60 –40 –20 0
220814 G19
100
120
–70 –50 –30 –10
INPUT LEVEL (dBFS)
–80
0
SFDR (dBc AND dBFS)
20
40
60
80
–60 –40 –20 0
220814 G20
100
120
–70 –50 –30 –10
32k Point 2-Tone FFT, fIN = 67.2MHz
and 74.4MHz, –7dBFS, PGA = 0,
RAND = “On”, Dither “Off”
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–80
–20
–10
0
20 40 50
220814 G21
–100
–110
–40
–60
–90
–30
–120
–50
–70
10 30 60
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–80
–20
–10
0
20 40 50
220814 G22
–100
–110
–40
–60
–90
–30
–120
–50
–70
10 30 60
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–80
–20
–10
0
20 40 50
220814 G23
–100
–110
–40
–60
–90
–30
–120
–50
–70
10 30 60
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–80
–20
–10
0
20 40 50
220814 G24
–100
–110
–40
–60
–90
–30
–120
–50
–70
10 30 60
SFDR vs Input Level, fIN = 140.1MHz,
PGA = 1, RAND = “On”, Dither “Off”
INPUT LEVEL (dBFS)
–80
0
SFDR (dBc AND dBFS)
20
40
60
80
–60 –40 –20 0
220814 G25
100
120
–70 –50 –30 –10
SFDR vs Input Level, fIN = 140.1MHz,
PGA = 1, RAND = “On”, Dither “On”
INPUT LEVEL (dBFS)
–80
0
SFDR (dBc AND dBFS)
20
40
60
80
–60 –40 –20 0
220814 G26
100
120
–70 –50 –30 –10
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–80
–20
–10
0
20 40 50
220814 G27
–100
–110
–40
–60
–90
–30
–120
–50
–70
10 30 60
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2208-14
12
220814fb
32k Point FFT, fIN = 250.11MHz,
–10dBFS, PGA = 1, RAND = “On”,
Dither “Off”
32k Point FFT, fIN = 380.11MHz,
–1dBFS, PGA = 1, RAND = “On”,
Dither “Off”
32k Point FFT, fIN = 380.11MHz,
–10dBFS, PGA = 1, RAND = “On”,
Dither “Off”
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–80
–20
–10
0
20 40 50
220814 G29
–100
–110
–40
–60
–90
–30
–120
–50
–70
10 30 60
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–80
–20
–10
0
20 40 50
220814 G30
–100
–110
–40
–60
–90
–30
–120
–50
–70
10 30 60
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–80
–20
–10
0
20 40 50
220814 G31
–100
–110
–40
–60
–90
–30
–120
–50
–70
10 30 60
SFDR (HD2 and HD3)
vs Input Frequency SNR vs Input Frequency
SNR and SFDR vs Sample Rate
fIN = 5.1MHz, –1dBFS
SNR and SFDR vs Supply Voltage
(VDD), fIN = 5.1MHz, –1dBFS
IVDD vs Sample Rate,
fIN = 5.1MHz, –1dBfs
SAMPLE RATE (Msps)
0
350
IVDD (mA)
370
390
410
430
40 80 120 160
220814 G36
450
470
20 60 100 140
VDD = 3.47V
VDD = 3.13V
VDD = 3.3V
32k Point FFT, fIN = 250.11MHz,
–1dBFS, PGA = 1, RAND = “On”,
Dither “Off”
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–80
–20
–10
0
20 40 50
220814 G28
–100
–110
–40
–60
–90
–30
–120
–50
–70
10 30 60
INPUT FREQUENCY (MHz)
0
65
SFDR (dBc)
70
80
85
90
200
110
220814 G32
75
100
50 250
150 300
95
100
105
PGA = 1
PGA = 0
INPUT FREQUENCY (MHz)
0
78
77
76
75
74
73
72
71
220814 G33
100
PGA = 0
200 300
SNR (dBFS)
PGA = 1
SAMPLE RATE (Msps)
0
SNR AND SFDR (dBFS)
90
100
200
220814 G34
80
70 50 100 150
25 75 125 175
110
85
95
75
105
SFDR
SNR
SUPPLY VOLTAGE (V)
2.8
SNR AND SFDR (dBFS)
90
95
100
3.6
220814 G35
85
80
70 3.0 3.2
SFDR
SNR
3.4
75
110
105
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2208-14
13
220814fb
SNR and SFDR vs Duty Cycle
DUTY CYCLE (%)
30
SFDR AND SNR (dBFS)
80
90
70
220814 G37
70
60 40 50 60
110
100
SFDR DCS ON
SFDR DCS OFF
SNR DCS OFF
SNR DCS ON
Gain Error Drift vs Temperature,
Internal Reference, Drift from 25°C
TEMPERATURE (°C)
–50
–0.1
0
0.2
10 50
220814 G38
–0.2
–0.3
–30 –10 30 70 90
–0.4
–0.5
0.1
GAIN ERROR DRIFT (%)
Gain Error Drift vs Temperature,
External Reference, Drift from 25°C
TEMPERATURE (°C)
–50
–0.12
GAIN ERROR DRIFT (%)
–0.10
–0.06
–0.04
–0.02
0.08
0.02
–10 30 50
220814 G39
–0.08
0.04
0.06
0
–30 10 70 90
Input Offset Voltage Drift
vs Temperature, Drift from 25°C
SNR and SFDR vs Input Common
Mode Voltage
TEMPERATURE (°C)
–50
INPUT OFFSET VOLTAGE (mV)
0.15
0.20
0.24
10 50
220814 G40
0.10
0.05
–30 –10 30 70 90
0
–0.05
INPUT COMMON MODE VOLTAGE (V)
0.50
60
SNR (dBFS) AND SFDR (dBc)
70
80
90
100
0.75 1.00 1.25
SFDR
SNR
1.50
220814 G41
1.75 2.00
TYPICAL PERFORMANCE CHARACTERISTICS
Mid-Scale Settling After Wake
Up from Shutdown or Starting
Encode Clock
TIME AFTER WAKE-UP OR CLOCK START (μs)
0
FULL-SCALE ERROR (%)
0.2
0.6
1.0
400
2208 G42
–0.2
–0.6
0
0.4
0.8
–0.4
–0.8
–1.0 10050 200150 300 350 450
250 500
TIME FROM WAKE-UP OR CLOCK START (μs)
0
FULL-SCALE ERROR (%)
1
3
5
800
2208 G43
–1
–3
0
2
4
–2
–4
–5 200100 400300 600 700 900
500 1000
Full-Scale Settling After Wake
Up from Shutdown or Starting
Encode Clock
LTC2208-14
14
220814fb
For CMOS Mode. Full Rate or Demultiplexed
SENSE (Pin 1): Reference Mode Select and External
Reference Input. Tie SENSE to VDD to select the internal
2.5V bandgap reference. An external reference of 2.5V or
1.25V may be used; both reference values will set a full
scale ADC range of 2.25V (PGA = 0).
GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground.
VCM (Pin 3): 1.25V Output. Optimum voltage for input com-
mon mode. Must be bypassed to ground with a minimum
of 2.2μF. Ceramic chip capacitors are recommended.
VDD (Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin.
Bypass to GND with 0.1μF ceramic chip capacitors.
AIN+ (Pin 8): Positive Differential Analog Input.
AIN– (Pin 9): Negative Differential Analog Input.
ENC+ (Pin 12): Positive Differential Encode Input. The
sampled analog input is held on the rising edge of ENC+.
Internally biased to 1.6V through a 6.2kΩ resistor. Output
data can be latched on the rising edge of ENC+.
ENC– (Pin 13): Negative Differential Encode Input. The
sampled analog input is held on the falling edge of ENC–.
Internally biased to 1.6V through a 6.2kΩ resistor. By-
pass to ground with a 0.1μF capacitor for a single-ended
Encode signal.
SHDN (Pin 19): Power Shutdown Pin. SHDN = low results
in normal operation. SHDN = high results in powered
down analog circuitry and the digital outputs are placed
in a high impedance state.
DITH (Pin 20): Internal Dither Enable Pin. DITH = low
disables internal dither. DITH = high enables internal dither.
Refer to Internal Dither section of this data sheet for details
on dither operation.
NC (Pins 21, 22): No Connect.
DB0-DB13 (Pins 23-30 and 33-38): Digital Outputs, B Bus.
DB13 is the MSB. Active in demultiplexed mode. The B bus
is in high impedance state in full rate CMOS mode.
OGND (Pins 31 and 50): Output Driver Ground.
OVDD (Pins 32 and 49): Positive Supply for the Output
Drivers. Bypass to ground with O.1μF capacitor.
OFB (Pin 39): Overfl ow/Underfl ow Digital Output for the B
Bus. OFB is high when an over or under fl ow has occurred
on the B bus. This pin goes to high impedance state in
full rate CMOS mode.
CLKOUTB (Pin 40): Data Valid Output. CLKOUTB will toggle
at the sample rate in full rate CMOS mode or at 1/2 the
sample rate in demultiplexed mode. Latch the data on the
falling edge of CLKOUTB.
CLKOUTA (Pin 41): Inverted Data Valid Output. CLKOUTA
will toggle at the sample rate in full rate CMOS mode or
at 1/2 the sample rate in demultiplexed mode. Latch the
data on the rising edge of CLKOUTA.
DNC (Pins 42, 43): Do Not Connect in CMOS Mode.
DA0-DA13 (Pins 44-48 and 51-59): Digital Outputs, A Bus.
DA13 is the MSB. Output bus for full rate CMOS mode
and demultiplexed mode.
OFA (Pin 60): Overfl ow/Underfl ow Digital Output for the
A Bus. OFA is high when an over or under fl ow has oc-
curred on the A bus.
LVDS (Pin 61): Data Output Mode Select Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting LVDS
to 1/3VDD selects demultiplexed CMOS mode. Connecting
LVDS to 2/3VDD selects Low Power LVDS mode. Connect-
ing LVDS to VDD selects Standard LVDS mode.
MODE (Pin 62): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and disables the clock duty
cycle stabilizer. Connecting MODE to 1/3VDD selects offset
binary output format and enables the clock duty cycle sta-
bilizer. Connecting MODE to 2/3VDD selects 2’s complement
output format and enables the clock duty cycle stabilizer.
Connecting MODE to VDD selects 2’s complement output
format and disables the clock duty cycle stabilizer.
RAND (Pin 63): Digital Output Randomization Selection
Pin. RAND low results in normal operation. RAND high
selects D1-D13 to be EXCLUSIVE-ORed with D0 (the
LSB). The output can be decoded by again applying an
XOR operation between the LSB and all other bits. This
mode of operation reduces the effects of digital output
interference.
PIN FUNCTIONS
LTC2208-14
15
220814fb
PGA (Pin 64): Programmable Gain Amplifi er Control Pin.
Low selects a front-end gain of 1, input range of 2.25VP-P.
High selects a front-end gain of 1.5, input range of
1.5VP-P.
GND (Exposed Pad): ADC Power Ground. The exposed
pad on the bottom of the package must be soldered to
ground.
For LVDS Mode. Standard or Low Power
SENSE (Pin 1): Reference Mode Select and External
Reference Input. Tie SENSE to VDD to select the internal
2.5V bandgap reference. An external reference of 2.5V or
1.25V may be used; both reference values will set a full
scale ADC range of 2.25V (PGA = 0).
GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground.
VCM (Pin 3): 1.25V Output. Optimum voltage for input com-
mon mode. Must be bypassed to ground with a minimum
of 2.2μF. Ceramic chip capacitors are recommended.
VDD (Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin.
Bypass to GND with 0.1μF ceramic chip capacitors.
AIN+ (Pin 8): Positive Differential Analog Input.
AIN– (Pin 9): Negative Differential Analog Input.
ENC+ (Pin 12): Positive Differential Encode Input. The
sampled analog input is held on the rising edge of ENC+.
Internally biased to 1.6V through a 6.2kΩ resistor. Output
data can be latched on the rising edge of ENC+.
ENC– (Pin 13): Negative Differential Encode Input. The
sampled analog input is held on the falling edge of ENC–.
Internally biased to 1.6V through a 6.2kΩ resistor. By-
pass to ground with a 0.1μF capacitor for a single-ended
Encode signal.
SHDN (Pin 19): Power Shutdown Pin. SHDN = low results
in normal operation. SHDN = high results in powered
down analog circuitry and the digital outputs are set in
high impedance state.
DITH (Pin 20): Internal Dither Enable Pin. DITH = low
disables internal dither. DITH = high enables internal dither.
Refer to Internal Dither section of the data sheet for details
on dither operation.
NC (Pins 21, 22): No Connect.
NC (Pins 23, 24): Do Not Connect in LVDS Mode.
D0–/D0+ to D13–/D13+ (Pins 25-30, 33-38, 41-48 and
51-58): LVDS Digital Outputs. All LVDS outputs require
differential 100Ω termination resistors at the LVDS receiver.
D13+/D13– is the MSB.
OGND (Pins 31 and 50): Output Driver Ground.
OVDD (Pins 32 and 49): Positive Supply for the Output
Drivers. Bypass to ground with 0.1μF capacitor.
CLKOUT–/CLKOUT+ (Pins 39 and 40): LVDS Data Valid
0utput. Latch data on the rising edge of CLKOUT+, falling
edge of CLKOUT–.
OF–/OF+ (Pins 59 and 60): Overfl ow/Underfl ow Digital Out-
put OF is high when an over or under fl ow has occurred.
LVDS (Pin 61): Data Output Mode Select Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting LVDS
to 1/3VDD selects demultiplexed CMOS mode. Connecting
LVDS to 2/3VDD selects Low Power LVDS mode. Connect-
ing LVDS to VDD selects Standard LVDS mode.
MODE (Pin 62): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and disables the clock duty
cycle stabilizer. Connecting MODE to 1/3VDD selects offset
binary output format and enables the clock duty cycle sta-
bilizer. Connecting MODE to 2/3VDD selects 2’s complement
output format and enables the clock duty cycle stabilizer.
Connecting MODE to VDD selects 2’s complement output
format and disables the clock duty cycle stabilizer.
RAND (Pin 63): Digital Output Randomization Selection Pin.
RAND low results in normal operation. RAND high selects
D1-D13 to be EXCLUSIVE-ORed with D0 (the LSB). The
output can be decoded by again applying an XOR operation
between the LSB and all other bits. The mode of operation
reduces the effects of digital output interference.
PGA (Pin 64): Programmable Gain Amplifi er Control Pin. Low
selects a front-end gain of 1, input range of 2.25VP-P. High
selects a front-end gain of 1.5, input range of 1.5VP-P.
GND (Exposed Pad Pin 65): ADC Power Ground. The
exposed pad on the bottom of the package must be sol-
dered to ground.
PIN FUNCTIONS
LTC2208-14
16
220814fb
Figure 1. Functional Block Diagram
ADC CLOCKS
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
DITHER
SIGNAL
GENERATOR
FIRST PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
ENC+ENC–
CORRECTION LOGIC
AND
SHIFT REGISTER
DITHM0DE
OGND
CLKOUT+
CLKOUT–
OF+
OF–
D13+
D13–
OVDD
D0+
D0–
220814 F01
INPUT
S/H
AIN–
AIN+
THIRD PIPELINED
ADC STAGE
OUTPUT
DRIVERS
CONTROL
LOGIC
PGA RAND LVDSSHDN
•
•
•
VDD
GND
PGA
SENSE
VCM BUFFER
ADC
REFERENCE
VOLTAGE
REFERENCE
RANGE
SELECT
BLOCK DIAGRAM
LTC2208-14
17
220814fb
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function
can create distortion products at the sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 3rd order IMD terms include (2fa + fb),
(fa + 2fb), (2fa - fb) and (fa - 2fb). The 3rd order IMD is
defi ned as the ratio of the RMS value of either input tone
to the RMS value of the largest 3rd order IMD product.
Spurious Free Dynamic Range (SFDR)
The ratio of the RMS input signal amplitude to the RMS
value of the peak spurious spectral component expressed
in dBc. SFDR may also be calculated relative to full scale
and expressed in dBFS.
Full Power Bandwidth
The Full Power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is reduced
by 3dB for a full scale input signal.
Aperture Delay Time
The time from when a rising ENC+ equals the ENC– voltage
to the instant that the input signal is held by the sample-
and-hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from convertion
to conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π • fIN • tJITTER)
OPERATION
DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N+D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band lim-
ited to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
The signal-to-noise (SNR) is the ratio between the RMS
amplitude of the fundamental input frequency and the RMS
amplitude of all other frequency components, except the
fi rst fi ve harmonics.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
THD = –20Log (√(V22 + V32 + V42 + ... VN2)/V1)
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the second
through nth harmonics.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
LTC2208-14
18
220814fb
CONVERTER OPERATION
The LTC2208-14 is a CMOS pipelined multistep converter
with a front-end PGA. As shown in Figure 1, the converter
has fi ve pipelined ADC stages; a sampled analog input
will result in a digitized value seven cycles later (see the
Timing Diagram). The analog input is differential for im-
proved common mode noise immunity and to maximize
the input range. Additionally, the differential input drive
will reduce even order harmonics of the sample and hold
circuit. The encode input is also differential for improved
common mode noise immunity.
The LTC2208-14 has two phases of operation, determined
by the state of the differential ENC+/ENC– input pins. For
brevity, the text will refer to ENC+ greater than ENC– as
ENC high and ENC+ less than ENC– as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage amplifi er. In
operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplifi ed and
output by the residue amplifi er. Successive stages oper-
ate out of phase so that when odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the voltage on the
sample capacitors is held. While ENC is high, the held
input voltage is buffered by the S/H amplifi er which drives
the fi rst pipelined ADC stage. The fi rst stage acquires
the output of the S/H amplifi er during the high phase of
ENC. When ENC goes back low, the fi rst stage produces
its residue which is acquired by the second stage. At
the same time, the input S/H goes back to acquiring the
analog input. When ENC goes high, the second stage
produces its residue which is acquired by the third stage.
An identical process is repeated for the third and fourth
stages, resulting in a fourth stage residue that is sent to
the fi fth stage for fi nal evaluation.
Each ADC stage following the fi rst has additional range to
accommodate fl ash and amplifi er offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2208-14
CMOS differential sample and hold. The differential ana-
log inputs are sampled directly onto sampling capacitors
(CSAMPLE) through NMOS transitors. The capacitors shown
attached to each input (CPARASITIC) are the summation of
all other capacitance associated with each input.
During the sample phase when ENC is low, the NMOS
transistors connect the analog inputs to the sampling
capacitors and they charge to, and track the differential
input voltage. When ENC transitions from low to high, the
sampled input voltage is held on the sampling capacitors.
During the hold phase when ENC is high, the sampling
capacitors are disconnected from the input and the held
voltage is passed to the ADC core for processing. As ENC
transitions from high to low, the inputs are reconnected to
the sampling capacitors to acquire a new sample. Since
the sampling capacitors still hold the previous sample,
a charging glitch proportional to the change in voltage
between samples will be seen at this time. If the change
between the last sample and the new sample is small,
the charging glitch seen at the input will be small. If the
Figure 2. Equivalent Input Circuit
CSAMPLE
4.9pF
RPARASITIC
3Ω
RPARASITIC
3Ω
RON
20Ω
RON
20Ω
VDD
LTC2208-14
AIN+
AIN–
220814 F02
CSAMPLE
4.9pF
VDD
VDD
ENC–
ENC+
1.6V
6k
1.6V
6k
CPARASITIC
1.8pF
CPARASITIC
1.8pF
APPLICATIONS INFORMATION
LTC2208-14
19
220814fb
input change is large, such as the change seen with input
frequencies near Nyquist, then a larger charging glitch
will be seen.
Common Mode Bias
The ADC sample-and-hold circuit requires differential
drive to achieve specifi ed performance. Each input should
swing ±0.5625V for the 2.25V range (PGA = 0) or ±0.375V
for the 1.5V range (PGA = 1), around a common mode
voltage of 1.25V. The VCM output pin (Pin 3) is designed
to provide the common mode bias level. VCM can be tied
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
driver circuit. The VCM pin must be bypassed to ground
close to the ADC with 2.2μF or greater.
Input Drive Impedance
As with all high performance, high speed ADCs the dy-
namic performance of the LTC2208-14 can be infl uenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and input reactance
can infl uence SFDR. At the falling edge of ENC the
sample and hold circuit will connect the 4.9pF sampling
capacitor to the input pin and start the sampling period.
The sampling period ends when ENC rises, holding the
sampled input on the sampling capacitor. Ideally, the
input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2F encode); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
INPUT DRIVE CIRCUITS
Input Filtering
A fi rst order RC low pass fi lter at the input of the ADC can
serve two functions: limit the noise from input circuitry and
provide isolation from ADC S/H switching. The LTC2208-14
has a very broadband S/H circuit, DC to 700MHz; it can
be used in a wide range of applications; therefore, it is not
possible to provide a single recommended RC fi lter.
Figures 3, 4a and 4b show three examples of input RC
fi ltering at three ranges of input frequencies. In general
it is desirable to make the capacitors as large as can be
tolerated—this will help suppress random noise as well
as noise coupled from the digital circuitry. The LTC2208-
14 does not require any input fi lter to achieve data sheet
specifi cations; however, no fi ltering will put more stringent
noise requirements on the input drive circuitry.
Transformer Coupled Circuits
Figure 3 shows the LTC2208-14 being driven by an RF
transformer with a center-tapped secondary. The secondary
center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used; however,
as the turns ratio increases so does the impedance seen by
the ADC. Source impedance greater than 50Ω can reduce
the input bandwidth and increase high frequency distor-
tion. A disadvantage of using a transformer is the loss of
low frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
Center-tapped transformers provide a convenient means
of DC biasing the secondary; however, they often show
poor balance at high input frequencies, resulting in large
2nd order harmonics.
Figure 3. Single-Ended to Differential Conversion
Using a Transformer. Recommended for Input
Frequencies from 5MHz to 100MHz
35Ω
5Ω
35Ω
10Ω
10Ω
5Ω
5Ω
0.1μF
AIN+
AIN–
8.2pF
2.2μF
8.2pF
8.2pF
VCM
T1
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2μF
220814 F03
LTC2208-14
APPLICATIONS INFORMATION
LTC2208-14
20
220814fb
Figure 4a shows transformer coupling using a transmis-
sion line balun transformer. This type of transformer has
much better high frequency response and balance than
fl ux coupled center tap transformers. Coupling capaci-
tors are added at the ground and input primary terminals
to allow the secondary terminals to be biased at 1.25V.
Figure 4b shows the same circuit with components suit-
able for higher input frequencies.
Figure 5. DC Coupled Input with Differential Amplifi er
Figure 4a. Using a Transmission Line Balun Transformer.
Recommended for Input Frequencies from 100MHz to 250MHz
Figure 4b. Using a Transmission Line Balun Transformer.
Recommended for Input Frequencies from 250MHz to 500MHz
Reference Operation
Figure 6 shows the LTC2208-14 reference circuitry con-
sisting of a 2.5V bandgap reference, a programmable gain
amplifi er and control circuit. The LTC2208-14 has three
modes of reference operation: Internal Reference, 1.25V
external reference or 2.5V external reference. To use the
internal reference, tie the SENSE pin to VDD. To use an
external reference, simply apply either a 1.25V or 2.5V
reference voltage to the SENSE input pin. Both 1.25V
and 2.5V applied to SENSE will result in a full scale range
of 2.25VP-P (PGA = 0). A 1.25V output, VCM is provided
for a common mode bias for input drive circuitry. An
external bypass capacitor is required for the VCM output.
This provides a high frequency low impedance path to
ground for internal and external circuitry. This is also the
compensation capacitor for the reference; it will not be
stable without this capacitor. The minimum value required
for stability is 2.2μF.
Figure 6. Reference Circuit
Direct Coupled Circuits
Figure 5 demonstrates the use of a differential amplifi er to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides
low frequency input response; however, the limited gain
bandwidth of any op amp or closed-loop amplifi er will de-
grade the ADC SFDR at high input frequencies. Additionally,
wideband op amps or differential amplifi ers tend to have
high noise. As a result, the SNR will be degraded unless
the noise bandwidth is limited prior to the ADC input.
0.1μF
AIN+
AIN–
4.7pF
2.2μF
4.7pF
4.7pF
VCM
LTC2208-14
ANALOG
INPUT
0.1μF
0.1μF 5Ω10Ω
10Ω
25Ω
25Ω 5Ω
T1
1:1
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2μF
220814 F04a
0.1μF
5Ω
25Ω
25Ω 5Ω
AIN+
AIN–
2.2μF
2.2pF
2.2pF
VCM
LTC2208-14
ANALOG
INPUT
0.1μF
0.1μF
T1
1:1
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2μF
220814 F04b
––
++
AIN+
AIN–
2.2μF
12pF
12pF
25Ω
25Ω
VCM
LTC2208-14
ANALOG
INPUT
220814 F05
CM
AMPLIFIER = LTC6600-20,
LT1993, ETC.
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
PGA
1.25V
SENSE
VCM BUFFER
INTERNAL
ADC
REFERENCE
RANGE
SELECT
AND GAIN
CONTROL
2.5V
BANDGAP
REFERENCE
2.2μF
TIE TO VDD TO USE
INTERNAL 2.5V
REFERENCE
OR INPUT FOR
EXTERNAL 2.5V
REFERENCE
OR INPUT FOR
EXTERNAL 1.25V
REFERENCE
220814 F06
APPLICATIONS INFORMATION
LTC2208-14
21
220814fb
The internal programmable gain amplifi er provides the
internal reference voltage for the ADC. This amplifi er has
very stringent settling requirements and is not accessible
for external use.
The SENSE pin can be driven ±5% around the nominal 2.5V
or 1.25V external reference inputs. This adjustment range
can be used to trim the ADC gain error or other system
gain errors. When selecting the internal reference, the
SENSE pin should be tied to VDD as close to the converter
as possible. If the sense pin is driven externally it should
be bypassed to ground as close to the device as possible
with 1μF ceramic capacitor.
Figure 7. A 2.25V Range ADC with an External 2.5V Reference
In applications where jitter is critical (high input frequen-
cies), take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude possible. If using trans-
former coupling, use a higher turns ratio to increase the
amplitude.
3. If the ADC is clocked with a fi xed frequency sinusoidal
signal, fi lter the encode signal to reduce wideband
noise.
4. Balance the capacitance and series resistance at both
encode inputs such that any coupled noise will appear
at both inputs as common mode noise.
The encode inputs have a common mode range of 1.2V
to 3V. Each input may be driven from ground to VDD for
single-ended drive.
PGA Pin
The PGA pin selects between two gain settings for the ADC
front-end. PGA = 0 selects an input range of 2.25VP-P;
PGA = 1 selects an input range of 1.5VP-P. The 2.25V input
range has the best SNR; however, the distortion will be
higher for input frequencies above 100MHz. For applica-
tions with high input frequencies, the low input range
will have improved distortion; however, the SNR will be
approximately 1.8dB worse. See the Typical Performance
Characteristics section.
Driving the Encode Inputs
The noise performance of the LTC2208-14 can depend on
the encode signal quality as much as on the analog input.
The encode inputs are intended to be driven differentially,
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a
1.6V bias. The bias resistors set the DC operating point
for transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
Any noise present on the encode signal will result in ad-
ditional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
Figure 8a. Equivalent Encode Input Circuit
Figure 8b. Transformer Driven Encode
VCM
SENSE
1.25V
3.3V
2.2μF
2.2μF
1μF
220814 F07
LTC2208-14
LT1461-2.5
26
4
VDD
VDD
LTC2208-14
220814 F08a
VDD
ENC–
ENC+
1.6V
1.6V
6k
6k
TO INTERNAL
ADC CLOCK
DRIVERS
50Ω
100Ω
8.2pF
0.1μF
0.1μF
0.1μF
T1
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
50Ω
LTC2208-14
220814 F08b
ENC–
ENC+
APPLICATIONS INFORMATION
LTC2208-14
22
220814fb
The lower limit of the LTC2208-14 sample rate is determined
by droop of the sample and hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specifi ed minimum operating frequency
for the LTC2208-14 is 1Msps.
DIGITAL OUTPUTS
Digital Output Modes
The LTC2208-14 can operate in four digital output modes:
standard LVDS, low power LVDS, full rate CMOS, and
demultiplexed CMOS. The LVDS pin selects the mode of
operation. This pin has a four level logic input, centered at
0, 1/3VDD, 2/3VDD and VDD. An external resistor divider can
be used to set the 1/3VDD and 2/3VDD logic levels. Table 1
shows the logic states for the LVDS pin.
Table 1. LVDS Pin Function
LVDS DIGITAL OUTPUT MODE
0V(GND) Full-Rate CMOS
1/3VDD Demultiplexed CMOS
2/3VDD Low Power LVDS
VDD LVDS
Digital Output Buffers (CMOS Modes)
Figure 11 shows an equivalent circuit for a single output
buffer in CMOS Mode, Full-Rate or Demultiplexed. Each
buffer is powered by OVDD and OGND, isolated from the
ADC power and ground. The additional N-channel transistor
in the output driver allows operation down to low voltages.
The internal resistor in series with the output makes the
output appear as 50Ω to external circuitry and eliminates
the need for external damping resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2208-14 should drive a minimum
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as a ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF. A resistor in series with the
Figure 10. ENC Drive Using a CMOS to PECL Translator
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC2208-14 is 130Msps.
For the ADC to operate properly the encode signal should
have a 50% (±5%) duty cycle. Each half cycle must have at
least 3.65ns for the ADC internal circuitry to have enough
settling time for proper operation. Achieving a precise 50%
duty cycle is easy with differential sinusoidal drive using
a transformer or using symmetric differential logic such
as PECL or LVDS. When using a single-ended ENCODE
signal asymmetric rise and fall times can result in duty
cycles that are far from 50%.
An optional clock duty cycle stabilizer can be used if the
input clock does not have a 50% duty cycle. This circuit
uses the rising edge of ENC pin to sample the analog input.
The falling edge of ENC is ignored and an internal falling
edge is generated by a phase-locked loop. The input clock
duty cycle can vary from 30% to 70% and the clock duty
cycle stabilizer will maintain a constant 50% internal duty
cycle. If the clock is turned off for a long period of time,
the duty cycle stabilizer circuit will require one hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin must be
connected to 1/3VDD or 2/3VDD using external resistors.
Figure 9. Single-Ended ENC Drive,
Not Recommended for Low Jitter
220814 F09
ENC–
1.6V
VTHRESHOLD = 1.6V ENC+
0.1μF
LTC2208-14
220814 F10
ENC–
ENC+
3.3V
3.3V
D0
Q0
Q0
MC100LVELT22
LTC2208-14
83Ω83Ω
130Ω130Ω
APPLICATIONS INFORMATION
LTC2208-14
23
220814fb
resistor, even if the signal is not used (such as OF+/OF– or
CLKOUT+/CLKOUT–). To minimize noise the PC board
traces for each LVDS output pair should be routed close
together. To minimize clock skew, all LVDS PC board traces
should have about the same length.
In Low Power LVDS Mode 1.75mA is steered between
the differential outputs, resulting in ±175mV at the LVDS
receiver’s 100Ω termination resistor. The output com-
mon mode voltage is 1.20V, the same as standard LVDS
Mode.
Data Format
The LTC2208-14 parallel digital output can be selected
for offset binary or 2’s complement format. The format
is selected with the MODE pin. This pin has a four level
logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An
external resistor divider can be used to set the 1/3VDD
and 2/3VDD logic levels. Table 2 shows the logic states
for the MODE pin.
Table 2. MODE Pin Function
MODE OUTPUT FORMAT CLOCK DUTY CYCLE STABILIZER
0(GND) Offset Binary Off
1/3VDD Offset Binary On
2/3VDD 2’s Complement On
VDD 2’s Complement Off
Figure 11. Equivalent Circuit for a Digital Output Buffer
output may be used but is not required since the ADC has
a series resistor of 43Ω on-chip.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Digital Output Buffers (LVDS Modes)
Figure 12 shows an equivalent circuit for an LVDS output
pair. A 3.5mA current is steered from OUT+ to OUT– or
vice versa, which creates a ±350mV differential voltage
across the 100Ω termination resistor at the LVDS receiver.
A feedback loop regulates the common mode output volt-
age to 1.20V. For proper operation each LVDS output pair
must be terminated with an external 100Ω termination
Figure 12. Equivalent Output Buffer in LVDS Mode
LTC2208-14
220814 F11
OVDD
VDD VDD
0.1μF
TYPICAL
DATA
OUTPUT
OGND
43Ω
OVDD 0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
LTC2208-14
220814 F12
3.5mA
1.20V
LVDS
RECEIVER
OGND
10k 10k
VDD
VDD
0.1μF
OVDD
3.3V
PREDRIVER
LOGIC
DATA
FROM
LATCH
+
–
OVDD
OVDD
43Ω
43Ω
100Ω
APPLICATIONS INFORMATION
LTC2208-14
24
220814fb
Overfl ow Bit
An overfl ow output bit (OF) indicates when the converter is
overranged or underranged. In CMOS mode, a logic high
on the OFA pin indicates an overfl ow or underfl ow on the
A data bus, while a logic high on the OFB pin indicates
an overfl ow on the B data bus. In LVDS mode, a differen-
tial logic high on OF+/OF– pins indicates an overfl ow or
underfl ow.
Output Clock
The ADC has a delayed version of the encode input avail-
able as a digital output, CLKOUT. The CLKOUT pin can
be used to synchronize the converter data to the digital
system. This is necessary when using a sinusoidal en-
code. In both CMOS modes, A bus data will be updated
as CLKOUTA falls and CLKOUTB rises. In demultiplexed
CMOS mode the B bus data will be updated as CLKOUTA
falls and CLKOUTB rises.
In Full Rate CMOS Mode, only the A data bus is active;
data may be latched on the rising edge of CLKOUTA or
the falling edge of CLKOUTB.
In demultiplexed CMOS mode CLKOUTA and CLKOUTB
will toggle at 1/2 the frequency of the encode signal. Both
the A bus and the B bus may be latched on the rising edge
of CLKOUTA or the falling edge of CLKOUTB.
Digital Output Randomizer
Interference from the ADC digital outputs is sometimes
unavoidable. Interference from the digital outputs may be
from capacitive or inductive coupling or coupling through
the ground plane. Even a tiny coupling factor can result in
discernible unwanted tones in the ADC output spectrum.
By randomizing the digital output before it is transmitted
off chip, these unwanted tones can be randomized, trading
a slight increase in the noise fl oor for a large reduction in
unwanted tone amplitude.
The digital output is “Randomized” by applying an exclu-
sive-OR logic operation between the LSB and all other data
output bits. To decode, the reverse operation is applied;
that is, an exclusive-OR operation is applied between the
LSB and all other bits. The LSB, OF and CLKOUT outputs
are not affected. The output Randomizer function is active
when the RAND pin is high.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven.
For example, if the converter is driving a DSP powered
by a 1.8V supply, then OVDD should be tied to that same
1.8V supply. In CMOS mode OVDD can be powered with
any logic voltage up to the 3.6V. OGND can be powered
with any voltage from ground up to 1V and must be less
than OVDD. The logic outputs will swing between OGND
and OVDD. In LVDS Mode, OVDD should be connected to
a 3.3V supply and OGND should be connected to GND.
Figure 13. Functional Equivalent of Digital Output Randomizer
•
•
•
CLKOUT
OF
D13/D0
D12/D0
D2/D0
D1/D0
D0D0
D1
RAND = HIGH,
RANDOMIZER
ENABLED
D2
D12
D13
OF
CLKOUT
RAND
220814 F13
APPLICATIONS INFORMATION
LTC2208-14
25
220814fb
Figure 14. Derandomizing a Randomized Digital Output
Internal Dither
The LTC2208-14 is a 14-bit ADC with a very linear transfer
function; however, at low input levels even slight imperfec-
tions in the transfer function will result in unwanted tones.
Small errors in the transfer function are usually a result
of ADC element mismatches. An optional internal dither
mode can be enabled to randomize the input location on
the ADC transfer curve, resulting in improved SFDR for
low signal levels.
As shown in Figure 15, the output of the sample-and-hold
amplifi er is summed with the output of a dither DAC. The
dither DAC is driven by a long sequence pseudo-random
number generator; the random number fed to the dither
DAC is also subtracted from the ADC result. If the dither
DAC is precisely calibrated to the ADC, very little of the
dither signal will be seen at the output. The dither signal
that does leak through will appear as white noise. The dither
DAC is calibrated to result in less than 0.5dB elevation in
the noise fl oor of the ADC, as compared to the noise fl oor
with dither off.
Figure 15. Functional Equivalent Block Diagram of Internal Dither Circuit
•
•
•
D1
D0
D2
D12
D13
LTC2208-14
PC BOARD
FPGA
CLKOUT
OF
D13/D0
D12/D0
D2/D0
D1/D0
D0
220814 F14
+–
AIN–
AIN+
S/H
AMP
DIGITAL
SUMMATION OUTPUT
DRIVERS
MULTIBIT DEEP
PSEUDO-RANDOM
NUMBER
GENERATOR
14-BIT
PIPELINED
ADC CORE
PRECISION
DAC
CLOCK/DUTY
CYCLE
CONTROL
CLKOUT
OF
D13
•
•
•
D0
ENC
DITHER ENABLE
HIGH = DITHER ON
LOW = DITHER OFF
DITH
ENC
ANALOG
INPUT
220814 F15
LTC2208-14
APPLICATIONS INFORMATION
LTC2208-14
26
220814fb
Grounding and Bypassing
The LTC2208-14 requires a printed circuit board with a
clean unbroken ground plane; a multilayer board with an
internal ground plane is recommended. The pinout of the
LTC2208-14 has been optimized for a fl owthrough layout
so that the interaction between inputs and digital outputs
is minimized. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated
as much as possible. In particular, care should be taken
not to run any digital track alongside an analog signal
track or underneath the ADC.
High quality ceramic bypass capacitors should be used
at the VDD, VCM, and OVDD pins. Bypass capacitors must
be located as close to the pins as possible. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The LTC2208-14 differential inputs should run parallel and
close to each other. The input traces should be as short as
possible to minimize capacitance and to minimize noise
pickup.
Heat Transfer
Most of the heat generated by the LTC2208-14 is trans-
ferred from the die through the bottom-side exposed pad.
For good electrical and thermal performance, the exposed
pad must be soldered to a large grounded pad on the PC
board. It is critical that the exposed pad and all ground
pins are connected to a ground plane of suffi cient area
with as many vias as possible.
APPLICATIONS INFORMATION
LTC2208-14
27
220814fb
UP Package
64-Lead Plastic QFN (9mm × 9mm)
(Reference LTC DWG # 05-08-1705 Rev C)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
9 .00 p 0.10
(4 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
PIN 1 TOP MARK
(SEE NOTE 5)
0.40 p 0.10
6463
1
2
BOTTOM VIEW—EXPOSED PAD
7.15 p 0.10
7.15 p 0.10
7.50 REF
(4-SIDES)
0.75 p 0.05
R = 0.10
TYP
R = 0.115
TYP
0.25 p 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UP64) QFN 0406 REV C
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 p0.05
7.50 REF
(4 SIDES)
7.15 p0.05
7.15 p0.05
8.10 p0.05 9.50 p0.05
0.25 p0.05
0.50 BSC
PACKAGE OUTLINE
PIN 1
CHAMFER
C = 0.35
LTC2208-14
28
220814fb
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006
LT 0909 REV B • PRINTED IN USA
PART NUMBER DESCRIPTION COMMENTS
LTC1747 12-Bit, 80MSPS ADC 72dB SNR, 87dB SFDR, 48-Pin TSSOP Package
LTC1748 14-Bit, 80Msps ADC 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package
LTC1749 12-Bit, 80Msps Wideband ADC Up to 500MHz IF Undersampling, 87dB SFDR
LTC1750 14-Bit, 80Msps Wideband ADC Up to 500MHz IF Undersampling, 90dB SFDR
LT1993-2 High Speed Differential Op Amp 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain
LTC2202 16-Bit, 10MSPS ADC 140mW, 81.6dB SNR, 100dB SFDR
LTC2203 16-Bit, 25MSPS ADC 220mW, 81.6dB SNR, 100dB SFDR
LTC2204 16-Bit, 40Msps ADC 480mW, 79.1dB SNR, 100dB SFDR
LTC2205 16-Bit, 65Msps ADC 610mW, 79dB SNR, 100dB SFDR
LTC2206 16-Bit, 80Msps ADC 725mW, 77.9dB SNR, 100dB SFDR
LTC2207 16-Bit, 105Msps ADC 900mW, 77.9dB SNR, 100dB SFDR
LTC2208 16-Bit, 130Msps ADC 1250mW, 77.7dB SNR, 100dB SFDR
LTC2220 12-Bit, 170Msps ADC 890mW, 67.5dB SNR, 9mm × 9mm QFN Package
LTC2220-1 12-Bit, 185Msps ADC 910mW, 67.5dB SNR, 9mm × 9mm QFN Package
LTC2249 14-Bit, 65Msps ADC 230mW, 73dB SNR, 5mm × 5mm QFN Package
LTC2250 10-Bit, 105Msps ADC 320mW, 61.6dB SNR, 5mm × 5mm QFN Package
LTC2251 10-Bit, 125Msps ADC 395mW, 61.6dB SNR, 5mm × 5mm QFN Package
LTC2252 12-Bit, 105Msps ADC 320mW, 70.2dB SNR, 5mm × 5mm QFN Package
LTC2253 12-Bit, 125Msps ADC 395mW, 70.2dB SNR, 5mm × 5mm QFN Package
LTC2254 14-Bit, 105Msps ADC 320mW, 72.5dB SNR, 5mm × 5mm QFN Package
LTC2255 14-Bit, 125Msps ADC 395mW, 72.4dB SNR, 5mm × 5mm QFN Package
LTC2299 Dual 14-Bit, 80Msps ADC 445mW, 73dB SNR, 9mm × 9mm QFN Package
LT5512 DC-3GHz High Signal Level Downconverting Mixer DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
LT5514 Ultralow Distortion IF Amplifi er/ADC Driver with
Digitally Controlled Gain
450MHz 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step
LT5522 600MHz to 2.7GHz High Linearity
Downconverting Mixer
4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB,
50Ω Single-Ended RF and LO Ports
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