Data Sheet, V1.5, August 2012 TLE8102SG Smart Dual Channel Powertrain Switch coreFLEX Automotive Power TLE 8102 SG Smart Dual Channel Powertrain Switch Table of Contents Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 3.1 3.2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 4.1 4.2 Maximum Ratings and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 5.1 5.2 5.3 5.3.1 5.3.2 5.3.3 5.3.3.1 5.3.3.2 5.3.4 5.3.5 5.4 5.5 5.6 5.6.1 5.6.2 5.7 Electrical and Functional Description of Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Parallel Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Inductive Output Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Reverse Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Current Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6 SPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7 Application Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Data Sheet 2 V1.5, 2012-08-17 Smart Dual Channel Powertrain Switch coreFLEX 1 TLE8102SG Overview Features * * * * * * * * * Overload Protection DMOS Overtemperature protection Open load detection Current limitation Low quiescent current mode 3.3 V C compatible input Electrostatic discharge (ESD) protection Green Product (RoHS compliant) AEC Qualified PG-DSO-12-11 Description * * * * * * Proportional load current sense with improved Precision: +/- 6% at ID=3A and +/-3% Current Sense Temperature Deviation refering to TJ=25C Two Low-Side Channels with RON(max. @ 150C) = 360mOhm. IC Overtemperature warning 8-Bit SPI (for diagnosis and control) Short to GND detection Programmable overload behaviour Dual Current Sense Low-Side Switch in Smart Power Technology (SPT) with two open drain DMOS output stages. The TLE8102SG is protected by embedded protection functions and designed for automotive applications. The output stages can be controlled directly by parallel inputs for PWM applications (e.g. Oxygen Probe Heater) or by SPI. All output stages can provide a load current proportional sense signal. Diagnosis can be read from an 8-bit SPI or by the external fault pin. Type Package Marking TLE8102SG PG-DSO-12-11 TLE8102SG Data Sheet 3 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Overview Parameter Summary Parameter Symbol Value Unit Supply voltage VDD VDS(CL) RON(max. @ 150C) 4.5 ... 5.5 V 48 ... 60 V 0.36 Drain source voltage On resistance VDD IN1 IN2 proportional current sense input control SPI CS SCLK hardware configuration OUT2 temperature sensor reset sleep mode OUT1 control, diagnostic and protective functions short circuit detection open load detection selectable current limit SI gate control CO2 [SO / ST2] CO1 [IS1 / IS2 / ST1 / FAULT] current sense / diagnosis under current detection GND Overview.emf Figure 1 Data Sheet Block Diagram 4 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Overview 2 Overview 2.1 Terms Figure 2 shows all terms used in this Target Data Sheet. Vbat IVDD IIN1 V DD I IN2 V IN1 I CS V IN2 VCS ISCLK I SI V SCLK V SI I SO I ST2 V SO / ST2 I IS1 / IS2 / ST1 / FAULT V IS1 / IS2 / ST1 / FAULT VDD OUT1 IN1 OUT2 I D1 I D2 VDS1 VDS2 IN2 CS SCLK SI CO2 [SO / ST2] CO1 [IS1 / IS2 / ST1 / FAULT] GND I GND Figure 2 Terms In all tables of electrical characteristics is valid: Channel related symbols without channel number are valid for each channel separately (e.g. VDS specification is valid for VDS1 and VDS2). Data Sheet 5 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Pin Configuration 3 Pin Configuration 3.1 Pin Assignment P-DSO-12 IN2 1 12 GND SI 2 11 CO2 OUT2 3 10 VDD CO1 4 9 OUT1 SCLK 5 8 CS GND 6 7 IN1 P-DSO-12_TLE8102.vsd Figure 3 Pin Configuration (top view) Both GND pins and the heat sink must be connected to GND externally. 3.2 Pin Pin Definitions and Functions Symbol Function 1 IN2 Input Channel 2 2 SI SPI Signal In 3 OUT2 Power Output Channel 2 4 CO1 Current Sense 1/2/Fault/Status Ch1 5 SCLK SPI Clock 6 GND Ground 7 IN1 Input Channel 1 8 CS SPI Chip Select 9 OUT1 Power Output Channel 1 10 VDD Supply Voltage 11 CO2 SPI Signal Out/Status Ch2 12 GND Ground Data Sheet 6 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Maximum Ratings and Operating Conditions 4 Maximum Ratings and Operating Conditions 4.1 Absolute Maximum Ratings Absolute Maximum Ratings 1) Tj = -40 C to +150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol 4.1.1 Supply Voltage 4.1.2 Continuous Drain Source Voltage (OUT1 to OUT2) 4.1.3 Limit Values Unit Conditions Min. Max. VDD VDS -0.3 7 V - -0.3 48 V - Input Voltage, All Inputs and Data outputs, Sense Lines VIN -0.3 7 V - 4.1.4 Output Current per Channel2) -3 ID(lim1,2) min. A Output ON 4.1.5 Maximum Voltage for short circuit Protection (single event)3) ID VSC, single - 48 V Current Limit 2, slew rate 1 (default setting) - 32 V Current Limit 2, slew rate 2 - 18 V Current Limit 1, slew rate 1 or 2 -4000 -2000 4000 2000 V V Output Pins All other Pins VESD 4.1.6 Electrostatic Discharge Voltage (human body model) according to EIA/JESD22-A114-E 4.1.7 DIN Humidity Category, DIN 40 040 E - 4.1.8 IEC Climatic Category, DIN IEC 68-1 40/150/ 56 - 1) Not subject to production test, specified by design. 2) Output current rating as long as maximum junction temperature is not exceeded. The maximum output current in the application has to be calculated using RthJA depending onmounting conditions. 3) Device mounted on PCB (50 mm x 50 mm x 1.5 mm epoxy, FR4) with 6 cm2 copper heatsink area (one layer, 70 m thick); PCB in test chamber with blown air. Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous repetitive operation. Data Sheet 7 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Maximum Ratings and Operating Conditions 4.2 Pos. 4.2.1 Operating Conditions Parameter Symbol Output Clamping Energy (single EAS event), linearly decreasing current1) Limit Values Min. Typ. Max. - - 75 Unit Conditions mJ ID(0) = 2 A, TJ(0) = 150 C, max. 100 cycles over lifetime Thermal Resistance 4.2.2 4.2.3 RthJSP Junction to ambient (see Figure 4) RthJA Junction to case - 1.3 2 K/W Pv = 2W - 25 - K/W Pv = 2W -40 - 150 C - -55 - 150 C - Temperature Range 4.2.4 Operating Temperature Range 4.2.5 Storage Temperature Range Tj Tstg 1) Pulse shape represents inductive switch off: ID(t) = ID(0) x (1 - t / tpulse); 0 < t < tpulse Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given by the related electrical characteristics table. PCB Dimensions: 76.2 x 114.3 x 1.5 mm, FR4 Thermal Vias: diameter = 0.3 mm; plating 25 m; 14 pcs. Metallisation according JEDEC 2s2p (JESD 51-7) + (JESD 51-5) 70m modeled (traces) 1,5 mm 35m, 90% metalization 35m, 90% metalization 70m, 5% metalization Thermal_Setup.vsd Figure 4 Data Sheet Thermal Simulation - PCB set-up 8 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks 5 Electrical and Functional Description of Blocks 5.1 Power Supply The TLE8102SG is supplied by power supply line VDD, used for the digital as well as the analog functions of the device including the gate control of the power stages. A capacitor between pins VDD to GND is recommended. The TLE8102SG can be programmed via SPI to enter sleep mode. In sleep mode, all outputs are turned off and all diagnosis and biasing circuits are disabled. These actions reduce the quiescent current consumption from the power supply. However, the SPI configuration registers (except for the channel on/off register) are not reset when the TLE8102SG enters sleep mode. To exit sleep mode, a wake up command must be sent via SPI. Electrical Characteristics: Power Supply VDD = 4.5 V to 5.5 V, Tj = -40 C to +150 C, (unless otherwise specified) all voltages with respect to ground, positive current flowing into pin Pos. Parameter Symbol 5.1.1 Supply Voltage 5.1.2 Supply Current 5.1.3 Supply Current in Sleep Mode 5.1.4 Wake up Time (after sleep mode) 1) Limit Values VDD IVDD IVDD(sleep) twake Unit Conditions Min. Typ. Max. 4.5 - 5.5 V - - - 5 mA - - - 10 A - - - 100 s - 1) Not subject to production test, specified by design. 5.2 Parallel Inputs There are two input pins available on the TLE8102SG to control the output stages. Each input signal controls the output stages of its assigned channel. For example, IN1 controls OUT1 and IN2 controls OUT2. Please refer to Figure 5 for details. The input pins are active high and each have an integrated pull-down current source. A comparator with hysteresis determines the state of the signal on INn. The zener diode protects the input circuit against ESD pulses. The BOL bit can be set via SPI. This bit determines if the output is exclusively controlled by the INn signals, exclusively controlled by the corresponding data bits CHnIN or by a Boolean OR or AND operation of the two inputs. The default setting of the BOL bits programs the outputs to be controlled exclusively by the INn signals. The SLEn bit can be set via SPI. This bit sets the slew rate of its assigned channel by selecting either slew rate 1 or slew rate 2. The slew rate also changes the over load switch off delay time (only for current limit 2). channel 2 channel 1 IN OR IN1 gate control & I IN1 SPI CH1IN Figure 5 Data Sheet BOL SLE1 Input Control and Boolean Operator 9 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks Electrical Characteristics: Parallel Inputs VDD = 4.5 V to 5.5 V, Tj = -40 C to +150 C, (unless otherwise specified) all voltages with respect to ground, positive current flowing into pin Pos. Parameter Symbol 5.2.1 Input Low Voltage 5.2.2 Input High Voltage VINL VINH VINHys IIN(1 ... 2) 5.2.3 Input Voltage Hysteresis 5.2.4 Input Pull-down Current (IN1 to IN2) 1) Limit Values Unit Conditions Min. Typ. Max. - - 1.0 V - 2.0 - - V - 100 200 400 mV - 20 50 100 A - 1) Not subject to production test, specified by design. 5.3 Power Outputs 5.3.1 Timing Diagrams The power transistors are switched on and off with a dedicated slope either via the parallel inputs or by the CHnIN bits of the serial peripheral interface SPI. The switching times tON and tOFF are designed equally. The switching time of each channel can be selected via SPI by programming the SLEn bit of the desired output. See Figure 6 for details CS SPI: ON VDS SPI: OFF tON tOFF t 80% 20% t Figure 6 Switching a Resistive Load 5.3.2 Inductive Output Clamp When switching off inductive loads, the potential at pin OUT rises to VDS(CL), as the inductance continues to drive current. The inductive output clamp is necessary to prevent destruction of the device. See Figure 7 for details. The maximum allowed load inductance and current, however, are limited. V bat OUT ID L, RL VDS VDS(CL) GND Figure 7 Data Sheet Inductive Output Clamp 10 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks Maximum Load Inductance During demagnetization of inductive loads, energy has to be dissipated in the TLE8102SG. This energy can be calculated with following equation: V bat - V DS(CL) RL ID L - ln 1 - ------------------------------------ + I D -----E = V DS(CL) -----------------------------------RL RL V bat - V DS(CL) The equation simplifies under the assumption of RL = 0: V bat 2 1 - E = --- LI D 1 - -----------------------------------2 V bat - V DS(CL) The energy, which is converted into heat, is limited by the thermal design of the component. 5.3.3 Protection Functions The TLE8102SG provides embedded protective functions. Integrated protection functions are designed to prevent IC destruction under fault conditions described in this data sheet. Fault conditions are considered "outside" the normal operating range. Protection functions are not designed for continuous repetitive operation. Over load and over temperature protections are implemented in the TLE8102SG. Figure 8 gives an overview pf the protective functions. INn Input Control temperature monitor CS SCLK SI T gate control SPI SO current limitation / shutdown FAULT ST OUTn Tn CLn Status GND Figure 8 Protection Functions 5.3.3.1 Over Load Protection The TLE8102SG is protected in case of over load or short circuit of the load. If the device is programmed for current limitation (current limit 1), the current is limited to IDS(lim1). After time td(fault), the corresponding over load flag CLn is set. If using the status outputs for diagnosis, the over load flag is cleared immediately after the over load condition is no longer present. If using the SPI interface and fault pin for diagnosis, the over load flag of the affected channel is cleared by the rising edge of the CS signal after a successful SPI transmission. If the TLE8102SG is programmed for current shutdown (current limit 2), the current threshold is IDS(lim2). However, unlike in current limit 1, after time td(fault), the affected channel is turned off and the according over load flag CLn is set. To turn on the channel again, this overload latch has to be reset by turning off the affected channel with either the parallel input or SPI. In addition, the switch off delay time can be programmed by changing the slew rate setting. If using the SPI interface and fault pin for diagnosis in case of current limit 2, the over load flag of the affected channel is cleared by the rising edge of the CS signal after a successful SPI transmission when the IN pin is low. A valid SPI cycle would not lead to a reset of the OVL flag of the affected channel during the IN-Pin is high. In both cases, the channel may shut down due to over temperature. Data Sheet 11 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks For timing information, please refer to Figure 9 and Figure 10 for details. OVL NO O VL OVL Condition IN ON O FF ID (lim 1) I O UT Inom Inom t d(fault) V B at V O UT t d(fault) t d(fault) t<t d(fault) td(fault) I*R O N set ST reset reset set FA ULT SO HH (N orm al F unction) CS set reset HL (O VL) HH HL reset HH HL reset HH HL HH reset Valid S P I c ycles OL_CurrLim1.vsd Figure 9 Data Sheet Over Load Behavior - Current Limitation (current limit 1) 12 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks OVL OVL Condition IN ON OFF ILIM 2 Failure latched ID(lim 2) Inom ILIM2 Failure latched ILIM 2 Failure latched I OUT t d(off) V Bat V O UT t d(off) shutdown t d(off) shutdown shutdown I*R ON set ST reset set FAU LT SO HH (Norm al Function) CS set reset HL (O VL) HH HL HH HL HH reset V alid SP I cycles OL_CurrLim2.vsd Figure 10 Over Load Behavior - Latched Shutdown (current limit 2) 5.3.3.2 Over Temperature Protection A dedicated temperature sensor for each channel detects if the temperature of its channel exceeds the over temperature shutdown threshold. If the channel temperature exceeds the over temperature shutdown threshold, the overheated channel is switched off immediately to prevent destruction. At the same time (no delay), the over temperature flag Tn is set. If the status outputs are used for diagnosis, the over temperature flag is cleared immediately after the over temperature condition is no longer present. If using the SPI interface and fault pin for diagnosis, the over temperature flag of the affected channel is cleared by the rising edge of the CS signal after a successful SPI transmission. The restart response of the channel can be programmed via SPI. If automatic autorestart is selected, after cooling down, the channel is switched on again with thermal hysteresis Tj. If latching shutdown is selected, the channel remains switched off even after cooling down. The channel can be restarted only if first turned off with either the parallel input or SPI. In addition, the channel must first be turned off before the the over temperature flag of the affected channel can be cleared by the rising edge of the CS signal after a successful SPI transmission. For timing information, please refer to Figure 11 and Figure 12 for details. Data Sheet 13 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks O utput chann el with OT condition OT O FF IN No O T condition ON T herm al toggling Therm a l toggling T herm al to ggling IO U T V OUT set (without delay tim e) ST set rewritten FA U LT T wo B it S O D iag no stic: O T F la g : HH L H L (O V L) H (O T ) reset HH HL HL HL H H (N o rm a l Fu n ction ) L H H H L (N o O T co nditio n) reset CS V alid S P I c ycles OT_behaviour_Restart.vsd Figure 11 Data Sheet Over Temperature Behavior - Automatic Autorestart 14 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks Output channel with OT condition OT IN OFF No OT condition ON OT Failure latched IOUT Thermal shutdown V OUT set ST reset rewritten set FAULT SO Two Bit Diagnostic: HH L OT Flag: HL (OVL) H (OT) reset HH HL H L HL H reset CS HH (Normal Function) L (No OT condition) Valid SPI cycles OT_behaviour_Latch.vsd Figure 12 Over Temperature Behavior - Latched Shutdown 5.3.4 Reverse Current In the case of reverse polarity when outputs are turned on, the power stages of the TLE8102SG are able to conduct reverse current Irev, defined as current that flows from ground to the output pin. Please note that neither the over load, over temperature, nor current sense diagnostics are functional in reverse current operation. Additionally, it is possible for the supply current IVDD to be greater than 5 mA. 5.3.5 Reverse Polarity Protection In the case of reverse polarity when outputs are turned off, the intrinsic body diode of the power transistor causes power dissipation. The reverse current through the intrinsic body diode has to be limited by the connected load. The VDD supply pin must be protected against reverse polarity externally. Please note that neither the over load, over temperature, nor current sense diagnostics are functional in reverse current operation. Data Sheet 15 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks Electrical Characteristics: Power Outputs VDD = 4.5 V to 5.5 V, Tj = -40 C to +150 C, (unless otherwise specified) all voltages with respect to ground, positive current flowing into pin Pos. Parameter Symbol 5.3.1 ON Resistance RDS(ON) VDS(CL) ID(lim1) Current Limit 2: Overload switch off ID(lim2) Limit Values Unit Conditions TJ = 25 C,1) VDD = 5 V, ID = 2 A TJ = 125 C,1) VDD = 5 V, ID = 2 A TJ = 150 C, VDD = 5 V, ID = 2 A Min. Typ. Max. - 0.18 - - 0.27 - - 0.3 0.36 5.3.2 Output Clamping Voltage 48 - 60 V output OFF 5.3.3 Current Limit 1: Current limitation 5 6.5 8 A - 9 10.5 12 A 9 - 12 A 8 - 12 A VDD 5 V VDD < 5 V, TJ 125 C VDD < 5 V, TJ > 125 C1) - - 2 A - - - 5 A Sleep mode active - - 5 20 10 50 s ID = 2 A, - - 5 20 10 50 s ID = 2 A, V/s Vbat = 14 V, ID = 2 A, resistive load, UDS 5.3.4 5.3.5 Reverse Current per channel1)2) 5.3.6 Output Leakage Current 5.3.7 Turn-On Time 1 Turn-On Time 2 Irev ID(lkg) tON 5.3.8 Turn-Off Time 1 Turn-Off Time 2 tOFF 5.3.9 Turn On slew rate Slew rate 1 Slew rate 2 sON Turn Off slew rate Slew rate 1 Slew rate 2 sOFF 5.3.10 1) 5.3.11 IC Overtemperature Warning Hysteresis1) 5.3.12 Channel Overtemp. Shutdown1) Hysteresis1) Tw T(w) hys Tth(sd) T(sd)hys resistive load resistive load 1 - 5 1 20 5 1 - 5 1 20 5 155 - - 10 185 - C K - - 170 - - 10 200 - C K - - = 80% to 30% V/s Vbat = 14 V, ID = 2 A, resistive load, UDS = 30% to 80% 1) Not subject to production test, specified by design. 2) Device functions normally, but supply current IVDD can be greater than 5 mA. Data Sheet 16 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks 5.4 Diagnostic Functions The TLE8102SG provides diagnosis information about the device and about the load. The following diagnosis functions are implemented: * * * * The protective functions (flags CLn and Tn) of channel n are registered in the diagnosis flag Pn. The open load diagnosis of channel n is registered in the diagnosis flag OLn. The under current diagnosis of channel n is registered in the diagnosis flag UCn. The short to ground monitor information of channel n is registered in the diagnosis flag SGn The diagnosis information of the TLE8102SG can either be accessed by status (ST) pins or the SPI interface and/or fault pin. With the exception of over temperature, a fault is only recognized if it lasts longer than the fault delay time td(fault). If using the status pins for diagnosis, the status pins change state in normal operation to match the input signal of the corresponding channel. If a fault condition appears and the fault delay time elapses, the status pin for the channel shows the inverted input signal. This diagnosis flag is not latched. Therefore, if the fault condition is removed, the status pins will indicate normal operation. Unlike the status pins, when using the SPI interface and/or fault pin, diagnosis flags are latched in the diagnosis register of the SPI interface. In this case, diagnosis flags are cleared by the rising edge of the CS signal after a successful SPI transmission. Please see Table 1 and Figure 13 for details. Table 1 Diagnostic Information Operating Condition Control Input Power Output Filter Time Status Output Fault Output Channel Channel Diagnosis Overtemp. Bits Flag MSB, LSB Sleep Mode x off - L H -- - Normal Operation L H off on - L H H H H, H H, H L L Short to ground L H off on td(fault) td(fault) H L L L L, L L, H L L Open load, Under current.1) L H off on td(fault) td(fault) H L L L L, H L, H L L Over load (current limit 1, H current limitation)1) on td(fault) L L H, L L Over load (current limit 2, H latching shutdown)2) off td(off) L L H, L L Overtemp. (autorestart) H off3) - L L H, L H H 4) - L L H, L H Overtemp. (latching shutdown) off 1) Short to ground/open load/ under current /overload/short-to-supply - events shorter than min. time td(fault) will not be latched and not reported at the diagnosis pins. 2) Overload/short-to-supply - events shorter than min. time td(off) will not be latched and not reported at the diagnosis pins. 3) Off as long as overtemperature occurs, restart after cooling down. 4) Shutdown latch reset by falling input edge. Data Sheet 17 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks VDD VDS (S G) SPI CHn MUX 00 01 10 I DS (S G) SGn VDS (OL) IDS (P D) OLn STn / FAULT ISn OR OUTn OR gate control under current detection UCn CLn Pn OR Tn protective functions IIS n current sense diagnosis.emf GND Figure 13 Block Diagram of Diagnostic Functions Electrical Characteristics: Diagnostic Functions VDD = 4.5 V to 5.5 V, Tj = -40 C to +150 C, (unless otherwise specified) all voltages with respect to ground, positive current flowing into pin Pos. Parameter Symbol Limit Values Min. Typ. Max. Unit Conditions V - Open Load Detection Voltage (Channel OFF) VDS(OL) 0.5 x 0.6 x 0.7 x VDD VDD VDD 5.4.2 Output Pull-down Current (Channel OFF) IPD(OL) 25 50 100 A - 5.4.3 Fault Filtering Time td(fault) 50 100 200 s - 5.4.4 Overload switch off delay time (only current limit 2) Td(off) 10 10 - - 50 150 s Slew rate 1 Slew rate 2 5.4.5 Short to Ground Detection Voltage VDS(SHG) 0.3 x 0.4 x 0.5 x V - VDD VDD VDD -50 -100 -150 A - 100 170 300 mA - 5.4.1 IPU(SHG) 5.4.6 Output Pull-up Current (Channel OFF) 5.4.7 Under Current Detection Threshold ID(OL) (Channel ON) Data Sheet 18 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks Figure 14 Open load (off) and Short to GND Diagnostics OL/ UC O L("O FF")/U C ("O N ") C ondition IN ON I O UT V Bat O FF Inom ID(UC) td(fault) t d(fault) t d(fault) V OUT t d(fault) t d(fault) t d(fault) V DS(O L) reset ST t d(fault) t<t d(fault) I*R O N set reset reset reset FAU LT rewritten set SO NO O L/UC reset HH LH HH (Normal reset Function) CS rewritten LH (UC) LH (OL) HH LH LH HH LH HH LH HH Valid SP I c ycles UC_OL.vsd Figure 15 Data Sheet Diagnostic at "Open Load/Under Current" Condition 19 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks SHG/ UC SHG("O FF") /UC ("ON") Condition IN ON OFF Inom I OUT V Bat NO SHG/UC ID(UC) td(fault) td(fault) V OUT td(fault) t d(fault) t d(fault) td(fault) t<t d(fault) I*R O N V DS(SHG) set reset ST td(fault) reset reset reset set FAULT rewritten set SO rewritten reset HH LH HH (Normal reset Function) LH (UC) LL (SHG) HH LL LH HH LH HH LL HH Valid SPI cycles CS UC_S_GND.vsd Figure 16 Diagnostic at "Short to GND/Under Current" Condition 5.5 Current Sense The TLE8102SG includes an integrated current sense feature. If the device is programmed (via SPI) to use this feature, the current source IIS of the current sense pin becomes active and generates a pull-down current proportional to the load current of the selected channel. An external pull-up resistor must be connected to the current sense pin to generate a voltage signal proportional to the load current of the selected channel. To achieve the specified accuracy for current sensing, the voltage VIS at the current sense pin must always be greater than or equal to 2 V. The current source IIS can also be programmed to generate a current proportional to the sum of the load current of both channels. Data Sheet 20 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks Electrical Characteristics: Current Sense VDD = 4.5 V to 5.5 V, Tj = -40 C to +150 C, (unless otherwise specified) all voltages with respect to ground, positive current flowing into pin Pos. Parameter Symbol 5.5.1 Current Sense Precision (single channel)1) IFB/IOUT PIS Limit Values Min. 5.5.2 Current Sense Temperature Deviation1) 2) 3) at 0.50 0.80 0.90 0.93 0.94 0.95 Typ. 1.00 Unit Conditions mA/A VDD = 5 V, UCO1 2 V ID = 100 mA, ID = 200 mA, ID = 500 mA, ID = 1 A, ID = 3 A, ID = 5 A, VDD = 5 V, UCO1 2 V ID = 100 mA, ID = 200 mA, ID = 500 mA, ID = 1 A, ID = 3 A, ID = 5 A, UCO1 2 V, Rsense = 2.5 k (IDmax = 1 A) UCO1 2 V, Rsense = 500 (IDmax = 5 A) Max. 1.50 1.20 1.10 1.07 1.06 1.05 IStemp % - 25 -10 -4 -3 -3 -3 PIS(25C, ID) +25 +10 +4 +3 +3 +3 5.5.3 Current Sense Settle time2) tIS - - 4 s 5.5.4 Current Sense Settle time2) tIS - - 2 s 5.5.5 Output Tri-state Leakage Current ISOlkg -10 0 10 A VFAULTL VST - - 0.4 V - - 0.4 V 5.5.6 FAULT Output Low Voltage 5.5.7 Status Output Low Voltage CS = H, 0 VSO VDD IFAULT = 1.6 mA IST = 1.6 mA 1) If the summed current is sensed the tolerances of the single channels are added. 2) Not subject to production test, specified by design. 3) Temperature Variation of one single device. Data Sheet 21 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks 1.50 1.40 1.30 1.20 I FB /I OUT [mA/A] 1.10 1 0.90 0.80 0.70 0.60 0.60 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ID [A] Current_Sense_points.vsd Figure 17 Current Sense Precision 1.50 1.40 1.30 1.20 I FB /IO UT [mA/A] 1.10 1 0.90 0.80 0.70 0.60 0.50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Expected Distribution of Current Sense Precision. Not testet. Figure 18 Data Sheet 4.5 5.0 ID [A] Current_Sense_range.vsd Current Sense Precision - range of expected distribution. 22 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks 5.6 SPI Interface The diagnosis and control interface is based on a serial peripheral interface (SPI). The SPI is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is transferred by the lines SI and SO at the data rate given by SCLK. The falling edge of CS indicates the beginning of a data access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CS. The interface provides daisy chain capability. SO MSB 6 5 4 3 2 1 SI MSB 6 5 4 3 2 1 LSB LSB CS SCLK time Figure 19 Serial Peripheral Interface The SPI protocol is described in Section 6. All registers are reset to default values after power-on reset or if the chip is programmed via SPI to enter sleep mode. 5.6.1 SPI Signal Description CS - Chip Select: The system micro controller selects the TLE8102SG by means of the CS pin. Whenever the pin is in low state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. CS High to Low transition: * The diagnosis information is transferred into the shift register. CS Low to High transition: * * * Command decoding is only done after the falling edge of CS if the command is valid. Data from shift register is transferred into the input matrix register. The diagnosis flags are cleared. SCLK - Serial Clock: This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock. It is essential that the SCLK pin is in low state whenever chip select CS makes any transition. SI - Serial Input: Serial input data bits are shifted in at this pin, the most significant bit first. SI information is read on the falling edge of SCLK. The 8 bit input data consist of two parts (control and data). Please refer to Section 6 for further information. Data Sheet 23 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks SO - Serial Output: Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Section 6 for further information. 5.6.2 Daisy Chain Capability The SPI of TLE8102SG is daisy chain capable. In this configuration several devices are activated by the same signal CS. The SI line of one device is connected with the SO line of another device (see Figure 20), which builds a chain. The ends of the chain are connected with the output and input of the master device, SO and SI respectively. The master device provides the master clock SCLK, which is connected to the SCLK line of each device in the chain. SI device 3 SO SI SO SPI CS SPI SCLK SCLK SI CS SCLK Figure 20 SO SPI CS SI CS SO device 2 SCLK device 1 Daisy Chain Configuration In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The bit shifted out can be seen at SO. After 8 SCLK cycles, the data transfer for one device has been finished. In single chip configuration, the CS line must go high to make the device accept the transferred data. In daisy chain configuration the data shifted out at device 1 has been shifted in to device 2. When using three TLE8102SG devices in daisy chain, three times 8 bits have to be shifted through the devices. After that, the CS line must go high (see Figure 21). SI SO SO device 3 SO device 2 SO device 1 SI device 3 SI device 2 SI device 1 CS CLK time Figure 21 Data Transfer in Daisy Chain Configuration Electrical Characteristics: SPI Interface VDD = 4.5 V to 5.5 V, Tj = -40 C to +150 C, (unless otherwise specified) all voltages with respect to ground, positive current flowing into pin Pos. Parameter Symbol Limit Values Min. 5.6.1 Input Pull-down Current (SI, SCLK) IIN(SI,SCLK) 10 5.6.2 Input Pull-up Current (CS) Data Sheet IIN(CS) 10 24 Unit Conditions Typ. Max. 20 50 A - 20 50 A - V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks Electrical Characteristics: SPI Interface (cont'd) VDD = 4.5 V to 5.5 V, Tj = -40 C to +150 C, (unless otherwise specified) all voltages with respect to ground, positive current flowing into pin Pos. 5.6.3 Parameter Symbol SO High State Output Voltage VSOH Limit Values Unit Conditions Min. Typ. Max. VDD - - - V ISOH = 2 mA 0.4 VSOL fSCK - - 0.4 V ISOL = 2.5 mA DC - 5 MHz - tp(SCK) tSCKH tSCKL tlead 200 - - ns - 80 - - ns - 80 - - ns - 200 - - ns - tlag 200 - - ns - 20 - - ns - 20 - - ns - - - 150 ns - 300 - - ns - - - - - 120 150 ns CL = 50 pF1) CL = 100 pF1) 5.6.4 SO Low State Output Voltage 5.6.5 Serial Clock Frequency (depending on SO load) 5.6.6 Serial Clock Period (1/fsclk) 5.6.7 Serial Clock High Time 5.6.8 Serial Clock Low Time 5.6.9 Enable Lead Time (falling edge of CS to rising edge of SCLK) 5.6.10 Enable Lag Time (falling edge of SCLK to rising edge of CS) 5.6.11 Data Setup Time (required time SI tSU to falling of SCLK) 5.6.12 Data Hold Time (falling edge of SCLK to SI) 5.6.13 Disable Time1) 5.6.14 tH tDIS Transfer Delay Time (CS high time tdt 2) between two accesses) 5.6.15 Data Valid Time tvalid 1) Not subject to production test, specified by design. 2) This time is necessary between two write accesses. To get the correct diagnostic information, the transfer delay time has to be extended to the maximum fault delay time td(fault)max = 200 s. Data Sheet 25 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Electrical and Functional Description of Blocks 5.7 Timing Diagrams t t CS(lead) CS(lag) t CS(td) tSCLK(P) CS 0.7Vdd 0.2Vdd t SCLK(H) tSCLK(L) 0.7Vdd SCLK 0.2Vdd t SI(su) tSI(h) 0.7Vdd SI 0.2Vdd tSO(v) tSO(dis) 0.7Vdd 0.2Vdd SO spi_timing_TLE8102L.vsd Figure 22 Data Sheet Serial Interface Timing Diagram 26 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch SPI Control 6 SPI Control The SPI protocol of the TLE8102SG provides two types of registers: control and diagnosis. After power-on reset, all register bits are set to default values. Serial Input Default Value: xxxxH 7 6 5 4 3 w 1 0 w w DATA CMD w 2 w w w w Field Bits Type Description CMD 7:5 w Command 001 Diagnosis only: The requested data is shifted out at SO. The data bits are ignored. 010 Output Configure: Configures the behavior of the power outputs. 011 I/O Configure: Configures the behavior of the I/O ports. 100 Reset Registers: Resets all internal registers to their reset values. The data bits are ignored. 101 Sleep Mode: Activates the low quiescent mode. In sleep mode, only the command "wake up" will be accepted. Other commands will not be accepted. Wake up can be performed by sending the wake up command or by performing an undervoltage reset. The data bits are ignored. 110 Wake up: Deactivates the sleep mode. After time delay twake, the device becomes fully functional. The data bits are ignored. 111 Channels ON/OFF: Turns on/off the power outputs (if configured for serial control) 000 No command: Not accepted as a valid command and the data bits will be ignored. Additionally, the diagnosis register will not be reset. DATA 4:0 w Data Data written to register selected by CMD Output Configure Default Value: 00H 7 6 5 4 3 2 1 0 0 1 0 LIM2 LIM1 RES SLE2 SLE1 w w w w w w w w Field Bits Type Description LIMn n+2 w Over load current limitation channel n 0 Current limit 2 is active (IDn(lim2)) 1 Current limit 1 is active (IDn(lim1)) Data Sheet 27 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch SPI Control Field Bits Type Description RES 2 w Over temperature behavior of all channels 0 Automatic autorestart of a channel after cooling down 1 Latching shutdown at over temperature SLEn n-1 w Slew rate of channel n 0 Slew rate 1 1 Slew rate 2 I/O Configure Default Value: 00H 7 6 5 4 0 1 1 DIA w w w w 3 2 1 BOL w 0 SENS w w w Field Bits Type Description DIA 4 w Status / SPI of diagnostic information 0 Diagnosis output with one status output per channel (ST1, ST2) 1 Diagnosis output with SPI interface (SO) and fault pin / current sense BOL 3:2 w Parallel / Serial control of all channels 00 With parallel input only (IN1, IN2) 01 With logic OR operation of INn and data bits 10 With logic AND operation of INn and data bits 11 With SPI interface only SENS 1:0 w Function of fault / current sense output 00 General fault pin 01 Current sense output of channel 1 (IIS1) 10 Current sense output of channel 2 (IIS2) 11 Current sense output of channel 1+2 (IIS1+IIS2) Channels ON/OFF Default Value: 00H 7 6 5 4 3 2 1 0 1 1 1 CTRL2 CTRL1 X X X w w w w w w w w Field Bits Type Description CTRLn n+2 w SPI control of channel n (CHnIN) 0 Output off 1 Output on Data Sheet 28 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch SPI Control E Serial Output (Standard Diagnosis) Default Value: FFH 7 6 - - r r 5 4 CH2 (CH21 CH20) r r 3 2 CH1 (CH11 CH10) r r 1 0 Channel IC Over temp. Over temp. r r Field Bits Type Description CHn 2n+1: 2n r Standard Diagnosis for Channel n 00 Short circuit to ground 01 Open load / Under current 10 Over load / over temperature 11 Normal operation Channel over temp. 1 r Channel Over Temperature Flag 0 No channel has an over temperature condition 1 One or both channels has an over temperature condition IC Over temp. 0 r Device Over Temperature Flag 0 IC temperature is below IC over temperature warning threshold Tw 1 IC temperature has exceeded IC over temperature warning threshold Tw Data Sheet 29 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Application Description 7 Application Description 12V IN1 OUT1 LDO 5V VDD 10 F 10 kOhm I/O I/O PWM PWM 10 kOhm ST1 ST2 C CS SPI co ntr ol, protection and d ia gno sis IN2 OUT2 SCLK SI AppDiag_Status.vsd Figure 23 Application Circuit using Status Outputs only 12V IN1 IN2 5V VDD 10 F I/O I/O PWM PWM 500 Ohm IS1 / IS2 / IS1+2 SO CS C SPI Figure 24 Data Sheet co ntr ol, protection and d iagno sis LDO OUT1 OUT2 SCLK SI Application Circuit using SPI and Current Sense Output 30 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Application Description 12V IN1 IN2 co ntr ol, protection and d ia gno sis OUT1 LDO 5V VDD 10 F 10kOhm I/O I/O PWM PWM FAULT SO C CS SPI OUT2 SCLK SI AppDiag_SPI_Fault.vsd Figure 25 Application Circuit using SPI and Fault Flag VBatt IN1 I/O IN2 VDD 10k 10k I/O ST1 I/O ST2 CS 10F OUT1 control, protect ion and diagno sis I/O OUT2 SCLK SI Micro Controller AppDiag_noSPI.vsd Figure 26 Data Sheet Application Circuit using parallel Inputs and Status Outputs, no SPI. 31 V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Package Outlines 0.8 Index Marking1 53 35 Bottom View 7 6 6 0.25B 12 1.60.1 (Metal ) 4.20.1 (Metal ) (4.4 Mold ) 6.40.11) B (Mold) 7 B 10.30.3 7.6+0.13 -0.1 12 7.50.11) 0.70.15 7.80.1 (Heatslug) (1.8 Mold ) 0.1 +0.075 0.25-0 .0 (1.55) 0+0.1 STANDOFF 2.350.1 (Body) Package Outlines 2.6 MAX. 8 1 Heatslu 1 12x 0.4+0.13 0.25M C A B 5x 1 = 5 5.10.1 (Metal ) 1) Does not include plastic or metal protrusion of Figure 27 PG-DSO-12-11 (Plastic Dual Small Outline Package) - Green Product. Green Product To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. Data Sheet 32 Dimensions in mm V1.5, 2012-08-17 TLE 8102 SG Smart Dual Channel Powertrain Switch Revision History 9 Version Revision History Date Changes 2012-08-17: Version 1.5: Data Sheet: V1.5 2012-08-17 Figure 26 corrected. No Functional Change 08-05-08: Version 1.4: Data Sheet: V1.4 08-05-08 Table 1 corrected. Functionality not changed. V1.4 08-05-08 Figure 14 corrected. No functional change. 08-04-24: Version 1.3: Data Sheet: V1.3 Data Sheet 08-04-24 Data Sheet released 33 V1.5, 2012-08-17 Edition 2012-08-17 Published by Infineon Technologies AG 81726 Munchen, Germany (c) Infineon Technologies AG 2012. All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.