Virtex-II Pro™ X Platform FPGAs: Pinout Information
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Virtex-II Pro X Pin Definitions
This section describes the pinouts for Virtex-II Pro X
devices in the following packages:
• FF896 and FF1704: flip-chip fine-pitch BGA of
1.00 mm pitch
All of the devices supported in a particular package are
pinout compatible and are listed in the same table (one
table per package). Pins that are not av ailable for the small-
est devices are listed in right-hand columns.
Each device is split into eight I/O banks to allow f or flexibility
in the choice of I/O standards (see Virtex-II Pro X™ Plat-
form FPGAs: Functional Description (Module 2) Global
pins, including JTA G, configuration, and power/ground pins,
are listed at the end of each table. Table 3 provides defin i-
tions for all pin types.
All Virtex-II Pro X pinout tables are available on the distribu-
tion CD-ROM, or on the web (at http://www.xilinx.com).
Table 3: Virtex -II Pro X Pin Definitions
Pin Name Direction Description
User I/O Pins
IO_LXXY_# Input/Output All user I/O pins are capable of differential signalling and can implement LVDS, ULVDS,
BLVDS, or LDT pairs. Each user I/O is labeled “IO_LXXY_#”, where:
IO indicates a user I/O pin.
LXXY indicates a differential pair , with XX a unique pair in the bank and Y = P/N for
the positive and negative sides of the differential pair.
# indicates the bank number (0 through 7)
Dual-Function Pins
IO_LXX Y_# /Z ZZ The dual-function pins ar e labelle d “IO_LXXY_#/ZZZ”, where ZZZ can be on e of the
following pins:
Per Bank - VRP, VRN, or VREF
Globally - GCLKX(S/P), BUSY/DOUT, INIT_B, DIN/D0 – D7, RDWR_B, or CS_B
With /ZZZ:
DIN / D0, D1, D2,
D3, D4, D5, D6,
D7
Input/Output In SelectMAP mode, D0 through D7 are configuration data pins. These pins become
user I/Os after configuration, unless the SelectMAP port is retained.
In bit-serial modes, DIN (D0) is the single-data input. This pin becomes a user I/O after
configuration.
CS_B Input In SelectMAP mode, this is the active-low Chip Select signal. The pin becomes a user
I/O after configuration, unless the SelectMAP port is retained.
RDWR_B Input In SelectMAP mode, this is the active-low Write Enable signal. The pin becomes a user
I/O after configuration, unless the SelectMAP port is retained.
BUSY/DOUT Output In SelectMAP mode, BUSY controls the rate at which configuration data is loaded. The
pin becomes a user I/O after configuration, unless the SelectMAP port is retained.
In bit-serial modes, DOUT provides preamble and configuration data to downstream
devices in a daisy-chain. The pin becomes a user I/O after configuration.
INIT_B Bidirectional
(open-drain) When Low, this pin indicates that the configuration memory is being cleared. When held
Low, the start of configuration is delayed. During configuration, a Low on this output
indicates that a configuration data error has occurred. The pin becomes a user I/O after
configuration.
GCLKx (S/P) Input These are clock input pins that connect to Global Clock Buffers. These pins become
regular user I/Os when not needed for clocks.
VRP Input This pin is for the DCI voltage reference resistor of P transistor (per bank).
VRN Input This pin is for the DCI voltage reference resistor of N transistor (per bank).