74 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics DS714 (v2.2) January 17, 2011 Product Specification Virtex-5Q FPGA Electrical Characteristics * UG192, Virtex-5 FPGA System Monitor User Guide * UG193, Virtex-5 FPGA XtremeDSPTM Design Considerations User Guide * UG194, Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide * UG195, Virtex-5 FPGA Packaging and Pinout Specification All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. * UG196, Virtex-5 FPGA RocketIOTM GTP Transceiver User Guide * UG197, Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express(R) Designs This Virtex-5Q FPGA data sheet, part of an overall set of documentation on the Virtex-5 family of FPGAs, is available on the Xilinx website: * UG198, Virtex-5 FPGA RocketIO GTX Transceiver User Guide * UG200, Embedded Processor Block in Virtex-5 FPGAs Reference Guide UG203, Virtex-5 FPGA PCB Designer's Guide Defense-grade Virtex(R)-5Q FPGAs are available in -2I, -1I, and -1M (only FX70T and FX100T devices in -1M) speed grades, with -2I having the highest performance. Virtex-5Q FPGA DC and AC characteristics are specified for the industrial temperature range. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade. * DS174, Virtex-5Q Family Overview * UG190, Virtex-5 FPGA User Guide * * UG191, Virtex-5 FPGA Configuration Guide All specifications are subject to change without notice. Virtex-5Q FPGA DC Characteristics Table 1: Absolute Maximum Ratings(1) Symbol Description Range Units VCCINT Internal supply voltage relative to GND -0.5 to 1.1 V VCCAUX Auxiliary supply voltage relative to GND -0.5 to 3.0 V VCCO Output drivers supply voltage relative to GND -0.5 to 3.75 V VBATT Key memory battery backup supply -0.5 to 4.05 V VREF Input reference voltage -0.5 to 3.75 V -0.75 to 4.05 V 3.3V I/O input voltage relative to VIN(3) GND(2) (user and dedicated I/Os) 3.3V I/O input voltage relative to GND (restricted to maximum of 100 user VTS TSTG -0.85 to 4.3 (Industrial Temperature) 2.5V or below I/O input voltage relative to GND (user and dedicated I/Os) IIN I/Os)(4) V -0.75 to VCCO + 0.5 V Current applied to an I/O pin, powered or unpowered 100 mA Total current applied to all I/O pins, powered or unpowered 100 mA -0.75 to 4.05 V -0.75 to VCCO + 0.5 V -65 to 150 C Voltage applied to 3-state 3.3V output(2) (user and dedicated I/Os) Voltage applied to 3-state 2.5V or below output (user and dedicated I/Os) Storage temperature (ambient) (c) 2009-2011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 1 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 1: Absolute Maximum Ratings(1) (Cont'd) Symbol Description TSOL Maximum soldering Tj Maximum junction Range Units +220 C +125 C temperature(5) temperature(5) Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. For 3.3V I/O operation, refer to Virtex-5 FPGA User Guide, Chapter 6, 3.3V I/O Design Guidelines. 3.3V I/O absolute maximum limit applied to DC and AC signals. For more flexibility in specific designs, a maximum of 100 user I/Os can be stressed beyond the normal specification for no more than 20% of a data period. For soldering guidelines, refer to UG112: Device Package User Guide. For thermal considerations, refer to UG195: Virtex-5 FPGA Packaging and Pinout Specification on the Xilinx website. 2. 3. 4. 5. Table 2: Recommended Operating Conditions Symbol Description Temperature Range Min Max Units VCCINT Internal supply voltage relative to GND, Tj = -40C to +100C Industrial 0.95 1.05 V VCCAUX(1) VCCO(2)(3)(4) Auxiliary supply voltage relative to GND, Tj = -40C to +100C Industrial 2.375 2.625 V Supply voltage relative to GND, Tj = -40C to +100C Industrial 1.14 3.45 V VIN 3.3V supply voltage relative to GND, Tj = -40C to +100C Industrial GND - 0.20 3.45 V 2.5V and below supply voltage relative to GND, Tj = -40C to +100C Industrial GND - 0.20 VCCO + 0.2 V IIN Maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. Industrial 10 mA VBATT(5) Battery voltage relative to GND, Tj = -40C to +100C Industrial 3.6 V 1.0 Notes: 1. 2. 3. 4. 5. Recommended maximum voltage drop for VCCAUX is 10 mV/ms. Configuration data is retained even if VCCO drops to 0V. Includes VCCO of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V. The configuration supply voltage VCC_CONFIG is also known as VCCO_0. VBATT is required only when using bitstream encryption. If battery is not used, connect VBATT to either ground or VCCAUX. Table 3: DC Characteristics Over Recommended Operating Conditions Symbol Description Min Typ Max Units VDRINT Data retention VCCINT voltage (below which configuration data might be lost) 0.75 V VDRI Data retention VCCAUX voltage (below which configuration data might be lost) 2.0 V IREF VREF leakage current per pin 10 A IL Input or output leakage current per pin (sample-tested) 10 A Input capacitance (sample-tested) 8 pF CIN IRPU IRPD (1) (1) Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V 20 150 A Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V 10 90 A Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.8V 5 45 A Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.5V 3 30 A Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.2V 2 15 A Pad pull-down (when selected) @ VIN = 2.5V 5 110 A 150 nA IBATT(2) Battery supply current n Temperature diode ideality factor r Series resistance 1.0002 n 5.0 Notes: 1. 2. Typical values are specified at nominal voltage, 25C. Maximum value specified for worst case process at 25C. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 2 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Important Note Typical values for quiescent supply current are now specified at nominal voltage, 85C junction temperatures (Tj). Xilinx recommends analyzing static power consumption at Tj = 85C because the majority of designs operate near the high end of the commercial temperature range. Data sheets for older products (e.g., Virtex-4 devices) still specify typical quiescent supply current at Tj = 25C. Quiescent supply current is specified by speed grade for Virtex-5Q devices. Use the XPOWER Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to calculate static power consumption for conditions other than those specified in Table 4. Table 4: Typical Quiescent Supply Current Symbol ICCINTQ ICCOQ Description Quiescent VCCINT supply current Quiescent VCCO supply current DS714 (v2.2) January 17, 2011 Product Specification Device Speed and Temperature Grade Units -2 (I) -1 (I) -1 (M) XQ5VLX30T 507 317 N/A mA XQ5VLX85 1072 833 N/A mA XQ5VLX110 1391 1109 N/A mA XQ5VLX110T 1448 1154 N/A mA XQ5VLX155T 2674 2188 N/A mA XQ5VLX220T 2844 2328 N/A mA XQ5VLX330T N/A 3492 N/A mA XQ5VSX50T 1092 840 N/A mA XQ5VSX95T 1924 1475 N/A mA XQ5VSX240T N/A 3168 N/A mA XQ5VFX70T 1658 1658 1658 mA XQ5VFX100T 2875 2875 2875 mA XQ5VFX130T 3041 3041 N/A mA XQ5VFX200T N/A 3755 N/A mA XQ5VLX30T 1.5 1.5 N/A mA XQ5VLX85 3 3 N/A mA XQ5VLX110 4 4 N/A mA XQ5VLX110T 4 4 N/A mA XQ5VLX155T 8 8 N/A mA XQ5VLX220T 8 8 N/A mA XQ5VLX330T N/A 12 N/A mA XQ5VSX50T 2 2 N/A mA XQ5VSX95T 4 4 N/A mA XQ5VSX240T N/A 12 N/A mA XQ5VFX70T 6 6 6 mA XQ5VFX100T 7 7 7 mA XQ5VFX130T 8 8 N/A mA XQ5VFX200T N/A 10 N/A mA www.xilinx.com 3 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 4: Typical Quiescent Supply Current (Cont'd) Symbol ICCAUXQ Description Quiescent VCCAUX supply current Device Speed and Temperature Grade Units -2 (I) -1 (I) -1 (M) XQ5VLX30T 43 43 N/A mA XQ5VLX85 93 93 N/A mA XQ5VLX110 125 125 N/A mA XQ5VLX110T 130 130 N/A mA XQ5VLX155T 177 177 N/A mA XQ5VLX220T 236 236 N/A mA XQ5VLX330T N/A 353 N/A mA XQ5VSX50T 74 74 N/A mA XQ5VSX95T 131 131 N/A mA XQ5VSX240T N/A 300 N/A mA XQ5VFX70T 110 110 110 mA XQ5VFX100T 150 150 150 mA XQ5VFX130T 180 180 N/A mA XQ5VFX200T N/A 250 N/A mA Notes: 1. 2. 3. Typical values are specified at nominal voltage, 85C junction temperatures (Tj). Industrial (I) and Military (M) grade devices have the same typical values as commercial (C) grade devices at 85C, but higher values at 100C (I) and 125C (M). Use the XPE/XPA power tools to calculate values for conditions other than specified in this data sheet. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 4 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Power-On Power Supply Requirements Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device initialization. The actual current consumed depends on the power-on ramp rate of the power supply. The power supplies can be turned on in any sequence, though the specifications shown in Table 5 are for the recommended power-on sequence of VCCINT, VCCAUX, and VCCO. The I/O will remain 3-stated through power-on if the recommended power-on sequence is followed. Xilinx does not specify the current or I/O behavior for other power-on sequences. Table 5 shows the minimum current required by Virtex-5Q devices for proper power-on and configuration. If the current minimums shown in Table 5 are met, the device powers on properly after all three supplies have passed through their power-on reset threshold voltages. The FPGA must be configured after VCCINT is applied. Once initialized and configured, use the XPOWER tools to estimate current drain on these supplies. Table 5: Power-On Current for Virtex-5Q Devices Device ICCINTMIN ICCAUXMIN ICCOMIN Typ(1) Typ(1) Typ(1) Units XQ5VLX30T 246 86 50 mA XQ5VLX85 492 186 100 mA XQ5VLX110 623 250 100 mA XQ5VLX110T 651 260 100 mA XQ5VLX155T 728 368 100 mA XQ5VLX220T 1056 472 150 mA XQ5VLX330T 1509 706 150 mA XQ5VSX50T 472 148 50 mA XQ5VSX95T 804 262 100 mA XQ5VSX240T 1632 662 150 mA XQ5VFX70T 695 232 100 mA XQ5VFX100T 749 298 100 mA XQ5VFX130T 1111 392 150 mA XQ5VFX200T 1222 534 150 mA Notes: 1. 2. Typical values are specified at nominal voltage, 25C. The maximum startup current can be obtained using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools and adding the quiescent plus dynamic current consumption. Table 6: Power Supply Ramp Time Symbol Description Ramp Time Units VCCINT Internal supply voltage relative to GND 0.20 to 50.0 ms VCCO Output drivers supply voltage relative to GND 0.20 to 50.0 ms VCCAUX Auxiliary supply voltage relative to GND 0.20 to 50.0 ms DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 5 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics SelectIOTM DC Input and Output Levels Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested. Table 7: SelectIO DC Input and Output Levels VIL VOL VOH IOL IOH V, Min V, Max V, Min V, Max V, Max V, Min mA mA LVTTL -0.3 0.8 2.0 3.45 0.4 2.4 Note 3 Note 3 LVCMOS33, LVDCI33 -0.3 0.8 2.0 3.45 0.4 VCCO - 0.4 Note 3 Note 3 LVCMOS25, LVDCI25 -0.3 0.7 1.7 VCCO + 0.3 0.4 VCCO - 0.4 Note 3 Note 3 LVCMOS18, LVDCI18 -0.3 35% VCCO 65% VCCO VCCO + 0.3 0.45 VCCO - 0.45 Note 4 Note 4 LVCMOS15, LVDCI15 -0.3 35% VCCO 65% VCCO VCCO + 0.3 25% VCCO 75% VCCO Note 4 Note 4 LVCMOS12 -0.3 35% VCCO 65% VCCO VCCO + 0.3 25% VCCO 75% VCCO Note 6 Note 6 PCI33_3(5) -0.2 30% VCCO 50% VCCO VCCO 10% VCCO 90% VCCO Note 5 Note 5 PCI66_3(5) -0.2 30% VCCO 50% VCCO VCCO 10% VCCO 90% VCCO Note 5 Note 5 PCI-X(5) -0.2 35% VCCO 50% VCCO VCCO 10% VCCO 90% VCCO Note 5 Note 5 GTLP -0.3 VREF - 0.1 VREF + 0.1 - 0.6 - 36 - GTL -0.3 VREF - 0.05 VREF + 0.05 - 0.4 - 32 - HSTL I_12 -0.3 VREF - 0.1 VREF + 0.1 VCCO + 0.3 25% VCCO 75% VCCO 6.3 6.3 HSTL I(2) -0.3 VREF - 0.1 VREF + 0.1 VCCO + 0.3 0.4 VCCO - 0.4 8 -8 HSTL II(2) -0.3 VREF - 0.1 VREF + 0.1 VCCO + 0.3 0.4 VCCO - 0.4 16 -16 HSTL III(2) -0.3 VREF - 0.1 VREF + 0.1 VCCO + 0.3 0.4 VCCO - 0.4 24 -8 HSTL IV(2) -0.3 VREF - 0.1 VREF + 0.1 VCCO + 0.3 0.4 VCCO - 0.4 48 -8 VCCO + 0.3 - - - - VCCO + 0.3 - - - - I/O Standard DIFF HSTL I(2) -0.3 DIFF HSTL II(2) -0.3 VIH 50% VCCO - 0.1 50% VCCO + 0.1 50% VCCO - 0.1 50% VCCO + 0.1 SSTL2 I -0.3 VREF - 0.15 VREF + 0.15 VCCO + 0.3 VTT - 0.61 VTT + 0.61 8.1 -8.1 SSTL2 II -0.3 VREF - 0.15 VREF + 0.15 VCCO + 0.3 VTT - 0.81 VTT + 0.81 16.2 -16.2 DIFF SSTL2 I -0.3 50% VCCO - 0.15 50% VCCO + 0.15 VCCO + 0.3 - - - - DIFF SSTL2 II -0.3 50% VCCO - 0.15 50% VCCO + 0.15 VCCO + 0.3 - - - - SSTL18 I -0.3 VREF - 0.125 VREF + 0.125 VCCO + 0.3 VTT - 0.47 VTT + 0.47 6.7 -6.7 SSTL18 II -0.3 VREF - 0.125 VREF + 0.125 VCCO + 0.3 VTT - 0.60 VTT + 0.60 13.4 -13.4 DIFF SSTL18 I -0.3 50% VCCO - 0.125 50% VCCO + 0.125 VCCO + 0.3 - - - - DIFF SSTL18 II -0.3 50% VCCO - 0.125 50% VCCO + 0.125 VCCO + 0.3 - - - - Notes: 1. 2. 3. 4. 5. 6. Tested according to relevant specifications. Applies to both 1.5V and 1.8V HSTL. Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA. Using drive strengths of 2, 4, 6, 8, 12, or 16 mA. For more information on PCI33_3, PCI66_3, and PCI-X, refer to Virtex-5 FPGA User Guide, Chapter 6, 3.3V I/O Design Guidelines. Supported drive strengths of 2, 4, 6, or 8 mA. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 6 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics HT DC Specifications (HT_25) Table 8: HT DC Specifications Symbol DC Parameter Conditions Min Typ Max Units 2.38 2.5 2.63 V 495 600 840 mV 15 mV 715 mV 15 mV 1000 mV 15 mV 780 mV 15 mV VCCO Supply Voltage VOD Differential Output Voltage VOD Change in VOD Magnitude VOCM Output Common Mode Voltage VOCM Change in VOCM Magnitude -15 VID Input Differential Voltage 200 VID Change in VID Magnitude -15 VICM Input Common Mode Voltage 440 VICM Change in VICM Magnitude -15 RT = 100 across Q and Q signals -15 RT = 100 across Q and Q signals 495 600 600 600 LVDS DC Specifications (LVDS_25) Table 9: LVDS DC Specifications Symbol DC Parameter Conditions Min Typ Max Units 2.38 2.5 2.63 V 1.675 V VCCO Supply Voltage VOH Output High Voltage for Q and Q RT = 100 across Q and Q signals VOL Output Low Voltage for Q and Q RT = 100 across Q and Q signals 0.825 VODIFF Differential Output Voltage (Q - Q), Q = High (Q - Q), Q = High RT = 100 across Q and Q signals 247 350 600 mV VOCM Output Common-Mode Voltage RT = 100 across Q and Q signals 1.125 1.250 1.375 V VIDIFF Differential Input Voltage (Q - Q), Q = High (Q - Q), Q = High 100 350 600 mV VICM Input Common-Mode Voltage 0.3 1.2 2.2 V Min Typ Max Units 2.38 2.5 2.63 V - 1.785 V V Extended LVDS DC Specifications (LVDSEXT_25) Table 10: Extended LVDS DC Specifications Symbol DC Parameter Conditions VCCO Supply Voltage VOH Output High Voltage for Q and Q RT = 100 across Q and Q signals VOL Output Low Voltage for Q and Q RT = 100 across Q and Q signals 0.715 - - V VODIFF Differential Output Voltage (Q - Q), Q = High (Q - Q), Q = High RT = 100 across Q and Q signals 350 - 820 mV VOCM Output Common-Mode Voltage RT = 100 across Q and Q signals 1.025 1.250 1.475 V VIDIFF Differential Input Voltage (Q - Q), Q = High (Q - Q), Q = High Common-mode input voltage = 1.25V 100 - 1000 mV VICM Input Common-Mode Voltage Differential input voltage = 350 mV 0.3 1.2 2.2 V DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 7 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics LVPECL DC Specifications (LVPECL_25) These values are valid when driving a 100 differential load only, i.e., a 100 resistor between the two receiver pins. The VOH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode ranges. Table 11 summarizes the DC output specifications of LVPECL. For more information on using LVPECL, see Virtex-5 FPGA User Guide, Chapter 6, SelectIO Resources. Table 11: LVPECL DC Specifications Symbol DC Parameter Min Typ Max Units VOH Output High Voltage VCC - 1.025 1.545 VCC - 0.88 V VOL Output Low Voltage VCC - 1.81 0.795 VCC - 1.62 V VICM Input Common-Mode Voltage 0.6 2.2 V 0.100 1.5 V Differential Input VIDIFF Voltage(1)(2) Notes: 1. 2. Recommended input maximum voltage not to exceed VCCAUX + 0.2V. Recommended input minimum voltage not to go below -0.5V. PowerPC 440 Switching Characteristics Consult the Embedded Processor Block in Virtex-5 FPGAs Reference Guide for further information. Table 12: Processor Block Switching Characteristics Clock Name Description CPMC440CLK CPU clock CPMINTERCONNECTCLK Xbar clock CPMPPCS0PLBCLK CPMPPCS1PLBCLK CPMPPCMPLBCLK CPMMCCLK CPMFCMCLK Speed Grade Units -2I -1I -1M 475 400 400 MHz 316.6 266.6 266.6 MHz Slave 0 PLB clock(1) 158.3 133.3 133.3 MHz Slave 1 PLB clock(1) 158.3 133.3 133.3 MHz Master PLB clock(1) 158.3 133.3 133.3 MHz 316.6 266.6 266.6 MHz 237.5 200 200 MHz Memory interface FCM clock(1)(2) clock(1) clock(1) 158.3 133.3 133.3 MHz DMA0 LL clock(1) 250 200 200 MHz DMA1 LL clock(1) 250 200 200 MHz DMA2 LL clock(1) 250 200 200 MHz CPMDMA3LLCLK DMA3 LL clock(1) 250 200 200 MHz JTGC440TCK JTAG clock 50 50 50 MHz CPMC440TIMERCLOCK Timer clock 237.5 200 200 MHz CPMDCRCLK CPMDMA0LLCLK CPMDMA1LLCLK CPMDMA2LLCLK FPGA logic DCR Notes: 1. 2. Typical bus frequencies are provided for reference only, actual frequencies are user-design dependent. Refer to DS567, DDR2 Memory Controller for PowerPC 440 Processors, for maximum clock speed of designs using the DDR2 Memory Controller for PowerPC(R) 440 processors. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 8 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 13: Processor Block MIB Switching Characteristics Clock Name Reference Clock Speed Grade -2I -1I -1M Units Clock-to-out and setup relative to clock TCK_CONTROL CPMMCCLK 1.247 1.463 1.463 ps TCK_ADDRESS CPMMCCLK 1.136 1.38 1.38 ps TCK_DATA CPMMCCLK 1.172 1.38 1.38 ps TCONTROL_CK CPMMCCLK 0.844 0.941 0.941 ps TDATA_CK CPMMCCLK 0.95 1.058 1.058 ps Table 14: Processor Block PLBM Switching Characteristics Clock Name Reference Clock Speed Grade -2I -1I -1M Units Clock-to-out and setup relative to clock TCK_CONTROL CPMPPCMPLBCLK 1.095 1.354 1.354 ps TCK_ADDRESS CPMPPCMPLBCLK 1.372 1.673 1.673 ps TCK_DATA CPMPPCMPLBCLK 1.257 1.535 1.535 ps TCONTROL_CK CPMPPCMPLBCLK 1.79 1.86 1.86 ps TDATA_CK CPMPPCMPLBCLK 0.914 1.059 1.059 ps Table 15: Processor Block PLBS0 Switching Characteristics Clock Name Reference Clock Speed Grade -2I -1I -1M Units Clock-to-out and setup relative to clock TCK_CONTROL CPMPPCS0PLBCLK 1.196 1.462 1.462 ps TCK_DATA CPMPPCS0PLBCLK 1.189 1.461 1.461 ps TCONTROL_CK CPMPPCS0PLBCLK 1.545 1.836 1.836 ps TADDRESS_CK CPMPPCS0PLBCLK 1.492 1.787 1.787 ps TDATA_CK CPMPPCS0PLBCLK 0.971 1.124 1.124 ps Table 16: Processor Block PLBS1 Switching Characteristics Clock Name Reference Clock Speed Grade -2I -1I -1M Units Clock-to-out and setup relative to clock TCK_CONTROL CPMPPCS1PLBCLK 1.234 1.525 1.525 ps TCK_DATA CPMPPCS1PLBCLK 1.298 1.615 1.615 ps TCONTROL_CK CPMPPCS1PLBCLK 1.596 1.921 1.921 ps TADDRESS_CK CPMPPCS1PLBCLK 1.568 1.864 1.864 ps TDATA_CK CPMPPCS1PLBCLK 0.969 1.127 1.127 ps DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 9 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 17: Processor Block DMA0 Switching Characteristics Clock Name Reference Clock Speed Grade -2I -1I -1M Units Clock-to-out and setup relative to clock TCK_CONTROL CPMDMA0LLCLK 1.42 1.665 1.665 ps TCK_DATA CPMDMA0LLCLK 1.472 1.712 1.712 ps TCONTROL_CK CPMDMA0LLCLK 0.558 0.716 0.716 ps TDATA_CK CPMDMA0LLCLK -0.105 -0.104 -0.104 ps Table 18: Processor Block DMA1 Switching Characteristics Clock Name Reference Clock Speed Grade -2I -1I -1M Units Clock-to-out and setup relative to clock TCK_CONTROL CPMDMA1LLCLK 1.266 1.474 1.474 ps TCK_DATA CPMDMA1LLCLK 1.418 1.645 1.645 ps TCONTROL_CK CPMDMA1LLCLK 0.555 0.717 0.717 ps TDATA_CK CPMDMA1LLCLK 0.01 0.046 0.046 ps Table 19: Processor Block DMA2 Switching Characteristics Clock Name Reference Clock Speed Grade -2I -1I -1M Units Clock-to-out and setup relative to clock TCK_CONTROL CPMDMA2LLCLK 1.235 1.437 1.437 ps TCK_DATA CPMDMA2LLCLK 1.262 1.463 1.463 ps TCONTROL_CK CPMDMA2LLCLK 0.924 1.155 1.155 ps TDATA_CK CPMDMA2LLCLK 0.142 0.168 0.168 ps Table 20: Processor Block DMA3 Switching Characteristics Clock Name Reference Clock Speed Grade -2I -1I -1M Units Clock-to-out and setup relative to clock TCK_CONTROL CPMDMA3LLCLK 1.242 1.462 1.462 ps TCK_DATA CPMDMA3LLCLK 1.184 1.376 1.376 ps TCONTROL_CK CPMDMA3LLCLK 0.767 0.965 0.965 ps TDATA_CK CPMDMA3LLCLK 0.119 0.116 0.116 ps Table 21: Processor Block DCR Switching Characteristics Clock Name Reference Clock Speed Grade -2I -1I -1M Units Clock-to-out and setup relative to clock TCK_CONTROL CPMDCRCLK - - - TCK_ADDRESS CPMDCRCLK - - - TCK_DATA CPMDCRCLK - - - TCONTROL_CK CPMDCRCLK - - - TADDRESS_CK CPMDCRCLK - - - TDATA_CK CPMDCRCLK - - - DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 10 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 22: Processor Block FCM Switching Characteristics Clock Name Reference Clock Speed Grade -2I -1I -1M Units Clock-to-out and setup relative to clock TCK_CONTROL CPMFCMCLK 1.084 1.324 1.324 ps TCK_DATA CPMFCMCLK 1.158 1.4 1.4 ps TCK_INSTRUCTION CPMFCMCLK 0.818 1.06 1.06 ps TCONTROL_CK CPMFCMCLK 1.218 1.395 1.395 ps TDATA_CK CPMFCMCLK 0.698 0.768 0.768 ps TRESULT_CK CPMFCMCLK 0.698 0.768 0.768 ps Table 23: Processor Block MISC Switching Characteristics Clock Name Reference Clock Speed Grade -2I -1I -1M Units Clock-to-out and setup relative to clock TCK_CONTROL CLK1 - - - TCK_ADDRESS CLK2 - - - TCK_DATA CLK3 - - - TCONTROL_CK CLK4 - - - TADDRESS_CK CLK5 - - - TDATA_CK CLK6 - - - DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 11 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics GTP_DUAL Tile Specifications GTP_DUAL Tile DC Characteristics Table 24: Absolute Maximum Ratings for GTP_DUAL Tiles Symbol Description Units MGTAVCCPLL Analog supply voltage for the GTP_DUAL shared PLL relative to GND -0.5 to 1.32 V MGTAVTTTX Analog supply voltage for the GTP_DUAL transmitters relative to GND -0.5 to 1.32 V MGTAVTTRX Analog supply voltage for the GTP_DUAL receivers relative to GND -0.5 to 1.32 V MGTAVCC Analog supply voltage for the GTP_DUAL common circuits relative to GND -0.5 to 1.1 V MGTAVTTRXC Analog supply voltage for the resistor calibration circuit of the GTP_DUAL column -0.5 to 1.32 V Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. Table 25: Recommended Operating Conditions for GTP_DUAL Tiles(1)(2) Symbol MGTAVCCPLL(1) MGTAVTTTX(1) MGTAVTTRX(1) MGTAVCC(1) MGTAVTTRXC(1) Description Min Max Units Analog supply voltage for the GTP_DUAL shared PLL relative to GND 1.14 1.26 V Analog supply voltage for the GTP_DUAL transmitters relative to GND 1.14 1.26 V Analog supply voltage for the GTP_DUAL receivers relative to GND 1.14 1.26 V Analog supply voltage for the GTP_DUAL common circuits relative to GND 0.95 1.05 V Analog supply voltage for the resistor calibration circuit of the GTP_DUAL column 1.14 1.26 V Notes: 1. 2. Each voltage listed requires the filter circuit described in Virtex-5 FPGA RocketIO GTP Transceiver User Guide. Voltages are specified for the temperature range of Tj = -40C to +100C. Table 26: DC Characteristics Over Recommended Operating Conditions for GTP_DUAL Tiles(1) Symbol Description Min Typ Max Units IMGTAVTTTX GTP_DUAL tile transmitter termination supply current(2) 71 90 mA IMGTAVCCPLL GTP_DUAL tile shared PLL supply current 36 60 mA IMGTAVTTRXC GTP_DUAL tile resistor termination calibration supply current 0.1 0.5 mA IMGTAVTTRX GTP_DUAL tile receiver termination supply current(3) 0.1 0.5 mA IMGTAVCC GTP_DUAL tile internal analog supply current 56 110 mA MGTRREF Precision reference resistor for internal calibration termination 49.9 1% tolerance Notes: 1. 2. 3. Typical values are specified at nominal voltage, 25C, with a 3.2 Gb/s line rate. ICC numbers are given per GTP_DUAL tile with both GTP transceivers operating with default settings. AC coupled TX/RX link. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 12 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 27: GTP_DUAL Tile Quiescent Supply Current Symbol Description Typ(1) Max Units 8.5 18 mA 8 18 mA IAVTTTXQ Quiescent MGTAVTTTX (transmitter termination) supply current IAVCCPLLQ Quiescent MGTAVCCPLL (PLL) supply current IAVTTRXQ Quiescent MGTAVTTRX (receiver termination) supply current. Includes MGTAVTTRXCQ. 0.1 0.8 mA IAVCCQ Quiescent MGTAVCC (analog) supply current 2.5 11 mA Notes: 1. 2. 3. 4. Typical values are specified at nominal voltage, 25C. Device powered and unconfigured. Currents for conditions other than values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools. GTP_DUAL tile quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of available GTP_DUAL tiles in the target LXT or SXT device. GTP_DUAL Tile DC Input and Output Levels Table 28 summarizes the DC output specifications of the GTP_DUAL tiles in Virtex-5Q FPGAs. Figure 1, page 14 shows the single-ended output voltage swing. Figure 2, page 14 shows the peak-to-peak differential output voltage. Consult Virtex-5 FPGA RocketIO GTP Transceiver User Guide for further details. Table 28: GTP_DUAL Tile DC Specifications Symbol DVPPIN DC Parameter Differential peak-to-peak input voltage Conditions Min External AC coupled 3.2 Gb/s Typ Max Units 150 2000 mV External AC coupled 3.2 Gb/s 180 2000 mV -400 MGTAVTTRX + 400 up to 1320 mV VIN Absolute input voltage DC coupled VCMIN Common mode input voltage DC coupled MGTAVTTRX = 1.2V DVPPOUT Differential peak-to-peak output voltage(1) TXBUFDIFFCTRL = 000, TX_DIFF_BOOST = ON 1400 mV VSEOUT Single-ended output voltage swing (1) TXBUFDIFFCTRL = 000, TX_DIFF_BOOST = ON 700 mV VCMOUT Common mode output voltage Equation based MGTAVTTTX = 1.2V RIN Differential input resistance 90 100 120 ROUT Differential output resistance 90 100 120 TOSKEW Transmitter output skew 15 ps CEXT Recommended external AC coupling capacitor(2) 200 nF 800 mV 1200 - Amplitude/2 75 100 mV Notes: 1. 2. The output swing and preemphasis levels are programmable using the attributes discussed in Virtex-5 FPGA RocketIO GTP Transceiver User Guide and can result in values lower than reported in this table. Values outside of this range can be used as appropriate to conform to specific protocols and standards. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 13 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics X-Ref Target - Figure 1 +V P VSEOUT N 0 ds714_01_012109 Figure 1: Single-Ended Output Voltage Swing X-Ref Target - Figure 2 +V DVPPOUT DVPPIN 0 -V P-N ds714_02_012109 Figure 2: Peak-to-Peak Differential Output Voltage Table 29 summarizes the DC specifications of the clock input of the GTP_DUAL tile. Figure 3 shows the single-ended input voltage swing. Figure 4 shows the peak-to-peak differential clock input voltage swing. Consult Virtex-5 FPGA RocketIO GTP Transceiver User Guide for further details. Table 29: GTP_DUAL Tile Clock DC Input Specifications(1) Symbol DC Parameter Conditions Min Typ Max Units VIDIFF Differential peak-to-peak input voltage 200 800 2000 mV VISE Single-ended input voltage 100 400 1000 mV RIN Differential input resistance 80 105 130 CEXT Required external AC coupling capacitor 75 100 200 nF Notes: 1. VMIN = 0V and VMAX = 1200 mV X-Ref Target - Figure 3 +V P VISE N 0 ds714_03_012109 Figure 3: Single-Ended Clock Input Voltage Swing Peak-to-Peak X-Ref Target - Figure 4 +V P-N VIDIFF 0 -V ds714_04_012109 Figure 4: Differential Clock Input Voltage Swing Peak-to-Peak DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 14 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics GTP_DUAL Tile Switching Characteristics Consult Virtex-5 FPGA RocketIO GTP Transceiver User Guide for further information. Table 30: GTP_DUAL Tile Performance Symbol Speed Grade Description -2I -1I Units FGTPMAX Maximum GTP transceiver data rate 3.75 3.2 Gb/s FGPLLMAX Maximum PLL frequency 2.0 2.0 GHz FGPLLMIN Minimum PLL frequency 1.0 1.0 GHz Table 31: Dynamic Reconfiguration Port (DRP) in the GTP_DUAL Tile Switching Characteristics Symbol FGTPDRPCLK Speed Grade Description GTPDRPCLK maximum frequency -2I -1I 175 150 Units MHz Table 32: GTP_DUAL Tile Reference Clock Switching Characteristics Symbol Description Conditions FGCLK Reference clock frequency range(1) CLK TRCLK Reference clock rise time 20% - 80% TFCLK Reference clock fall time 80% - 20% cycle(2) All Speed Grades Min Typ 60 Max Units 350 MHz 200 400 ps 200 400 ps 50 60 % TDCREF Reference clock duty TGJTT Reference clock total jitter, peakpeak(3) CLK 40 ps TLOCK Clock recovery frequency acquisition time Initial PLL lock 1 ms TPHASE Clock recovery phase acquisition time Lock to data after PLL has locked to the reference clock 200 s CLK 40 Notes: The clock from the GTP_DUAL differential clock pin pair can be used for all serial bit rates. GREFCLK can be used for serial bit rates up to 1 Gb/s. 2. For reference clock rates above 325 MHz, a duty cycle of 45% to 55% must be maintained. 3. Measured at the package pin. GTP_DUAL jitter characteristics measured using a clock with specification TGJTT. 1. X-Ref Target - Figure 5 TRCLK 80% 20% TFCLK ds714_05_012109 Figure 5: Reference Clock Timing Parameters DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 15 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 33: GTP_DUAL Tile User Clock Switching Characteristics(1) Symbol Description Speed Grade Conditions -2I -1I Units FTXOUT TXOUTCLK maximum frequency 375 320 MHz FRXREC RXRECCLK maximum frequency 375 320 MHz TRX RXUSRCLK maximum frequency 375 320 MHz TRX2 RXUSRCLK2 maximum frequency RXDATAWIDTH = 0 350 320 MHz RXDATAWIDTH = 1 187.5 160 MHz TTX TXUSRCLK maximum frequency 375 320 MHz TTX2 TXUSRCLK2 maximum frequency TXDATAWIDTH = 0 350 320 MHz TXDATAWIDTH = 1 187.5 160 MHz Max Units FGTPMAX Gb/s Notes: 1. Clocking must be implemented as described in Virtex-5 FPGA RocketIO GTP Transceiver User Guide. Table 34: GTP_DUAL Tile Transmitter Switching Characteristics Symbol Description Min Typ FGTPTX Serial data rate range 0.1 TRTX TX Rise time 140 ps TFTX TX Fall time 120 ps TLLSKEW TX lane-to-lane skew(1) 855 ps VTXOOBVDPP Electrical idle amplitude 20 mV TTXOOBTRANS Electrical idle transition time 40 ns TJ3.75 Total Jitter(2) 0.35 UI DJ3.75 Deterministic Jitter(2) 0.19 UI TJ3.2 Total Jitter(2) 0.35 UI DJ3.2 Deterministic Jitter(2) 0.19 UI TJ2.5 Total Jitter(2) 0.30 UI DJ2.5 Deterministic Jitter(2) 0.14 UI TJ2.0 Total Jitter(2) 0.30 UI DJ2.0 Deterministic Jitter(2) 0.14 UI TJ1.25 Total Jitter(2) 0.20 UI DJ1.25 Deterministic Jitter(2) 0.10 UI TJ1.00 Total Jitter(2) 0.20 UI DJ1.00 Deterministic Jitter(2) 0.10 UI TJ500 Total Jitter(2) 0.10 UI DJ500 Deterministic Jitter(2) 0.04 UI TJ100 Total Jitter(2) 0.02 UI DJ100 Deterministic Jitter(2) 0.01 UI 3.75 Gb/s 3.20 Gb/s 2.50 Gb/s 2.00 Gb/s 1.25 Gb/s 1.00 Gb/s 500 Mb/s 100 Mb/s Notes: 1. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTP_DUAL sites. 2. Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1. 3. All jitter values are based on a Bit-Error Ratio of 1e-12. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 16 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 35: GTP_DUAL Tile Receiver Switching Characteristics Symbol Description Min Typ Max Units RX oversampler not enabled 0.5 FGTPMAX Gb/s RX oversampler enabled 0.1 0.5 Gb/s OOB detect threshold peak-to-peak OOBDETECT_THRESHOLD = 100 60 165 mV RXSST Receiver spread-spectrum tracking(1) Modulated @ 33 KHz 0 ppm RXRL Run length (CID) Internal AC capacitor bypassed 150 UI FGTPRX Serial data rate RXOOBVDPP 2nd-order RXPPMTOL Data/REFCLK PPM offset tolerance -5000 105 CDR loop disabled with PLL_RXDIVSEL_OUT = 1(2) -200 200 ppm CDR 2nd-order loop disabled with PLL_RXDIVSEL_OUT = 2(2) -200 200 ppm CDR 2nd-order loop disabled with PLL_RXDIVSEL_OUT = 4(2) -100 100 ppm CDR 2nd-order loop enabled -1000 1000 ppm SJ Jitter Tolerance JT_SJ3.75 Sinusoidal Jitter(3) 3.75 Gb/s 0.30 UI JT_SJ3.2 Sinusoidal Jitter(3) 3.20 Gb/s 0.40 UI JT_SJ2.50 Sinusoidal Jitter(3) 2.50 Gb/s 0.40 UI JT_SJ2.00 Sinusoidal Jitter(3) 2.00 Gb/s 0.40 UI JT_SJ1.00 Sinusoidal Jitter(3) 1.00 Gb/s 0.30 UI JT_SJ500 Sinusoidal Jitter(3) 500 Mb/s 0.30 UI JT_SJ500 Sinusoidal Jitter(3) 500 Mb/s OS 0.30 UI JT_SJ100 Sinusoidal Jitter(3) 100 Mb/s OS 0.30 UI SJ Jitter Tolerance with Stressed Eye JT_TJSE3.2 Total Jitter with Stressed Eye(4) 3.20 Gb/s 0.87 UI JT_SJSE3.2 Sinusoidal Jitter with Stressed Eye(4) 3.20 Gb/s 0.30 UI Notes: 1. 2. 3. 4. 5. Using PLL_RXDIVSEL_OUT = 1 only. CDR 1st-order step size set to 2. Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter. Stimulus signal includes 0.4UI of DJ and 0.17UI of RJ. RX equalizer is enabled. All jitter values are based on a Bit Error Ratio of 1e-12. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 17 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics GTX_DUAL Tile Specifications GTX_DUAL Tile DC Characteristics Table 36: Absolute Maximum Ratings for GTX_DUAL Tiles Symbol Description Units MGTAVCCPLL Analog supply voltage for the GTX_DUAL shared PLL relative to GND -0.5 to 1.1 V MGTAVTTTX Analog supply voltage for the GTX_DUAL transmitters relative to GND -0.5 to 1.32 V MGTAVTTRX Analog supply voltage for the GTX_DUAL receivers relative to GND -0.5 to 1.32 V MGTAVCC Analog supply voltage for the GTX_DUAL common circuits relative to GND -0.5 to 1.1 V MGTAVTTRXC Analog supply voltage for the resistor calibration circuit of the GTX_DUAL column -0.5 to 1.32 V Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. Table 37: Recommended Operating Conditions for GTX_DUAL Tiles(1)(2) Symbol MGTAVCCPLL(1) MGTAVTTTX(1) MGTAVTTRX(1) MGTAVCC(1) MGTAVTTRXC(1) Description Min Max Units Analog supply voltage for the GTX_DUAL shared PLL relative to GND 0.95 1.05 V Analog supply voltage for the GTX_DUAL transmitters relative to GND 1.14 1.26 V Analog supply voltage for the GTX_DUAL receivers relative to GND 1.14 1.26 V Analog supply voltage for the GTX_DUAL common circuits relative to GND 0.95 1.05 V Analog supply voltage for the resistor calibration circuit of the GTX_DUAL column 1.14 1.26 V Notes: 1. 2. Each voltage listed requires the filter circuit described in Virtex-5 FPGA RocketIO GTX Transceiver User Guide. Voltages are specified for the temperature range of Tj = -40C to +100C. Table 38: DC Characteristics Over Recommended Operating Conditions for GTX_DUAL Tiles(1) Symbol Description Min Typ Max Units IMGTAVTTTX GTX_DUAL tile transmitter termination supply current(2) 43.3 86.3 mA IMGTAVCCPLL GTX_DUAL tile shared PLL supply current 38.0 99.4 mA IMGTAVTTRXC GTX_DUAL tile resistor termination calibration supply current 0.1 0.5 mA IMGTAVTTRX GTX_DUAL tile receiver termination supply current(3) 40.3 56.5 mA IMGTAVCC GTX_DUAL tile internal analog supply current 80.5 179.5 mA MGTRREF Precision reference resistor for internal calibration termination 59.0 1% tolerance Notes: 1. 2. 3. 4. Typical values are specified at nominal voltage, 25C, with a 3.2 Gb/s line rate. ICC numbers are given per GTX_DUAL tile with both GTX transceivers operating with default settings. AC coupled TX/RX link. Values for currents other than the values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 18 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 39: GTX_DUAL Tile Quiescent Supply Current Symbol Description Typ(1) Max Units IAVTTTXQ Quiescent MGTAVTTTX (transmitter termination) supply current 8.2 21.6 mA IAVCCPLLQ Quiescent MGTAVCCPLL (PLL) supply current 0.8 4.8 mA IAVTTRXQ Quiescent MGTAVTTRX (receiver termination) supply current. Includes MGTAVTTRXCQ. 1.2 12.0 mA IAVCCQ Quiescent MGTAVCC (analog) supply current 9.0 50.4 mA Notes: Typical values are specified at nominal voltage, 25C. Device powered and unconfigured. Currents for conditions other than values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools. 4. GTX_DUAL tile quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of available GTX_DUAL tiles in the target FXT device. 1. 2. 3. GTX_DUAL Tile DC Input and Output Levels Table 40 summarizes the DC output specifications of the GTX_DUAL tiles in Virtex-5Q FPGAs. Figure 6, page 20 shows the single-ended output voltage swing. Figure 7, page 20 shows the peak-to-peak differential output voltage. Consult Virtex-5 FPGA RocketIO GTX Transceiver User Guide for further details. Table 40: GTX_DUAL Tile DC Specifications Symbol DVPPIN DC Parameter Differential peak-to-peak input voltage Conditions Min Typ Max Units External AC coupled 4.25 Gb/s 200 1800 mV External AC coupled 4.25 Gb/s 125 1800 mV -400 MGTAVTTRX +400 up to 1320 mV VIN Absolute input voltage DC coupled MGTAVTTRX = 1.2V VCMIN Common mode input voltage DC coupled MGTAVTTRX = 1.2V DVPPOUT Differential peak-to-peak output voltage(1) TXBUFDIFFCTRL = 111 1400 mV VSEOUT Single-ended output voltage swing(1) TXBUFDIFFCTRL = 111 700 mV VCMOUT Common mode output voltage Equation based MGTAVTTTX = 1.2V RIN Differential input resistance 85 100 120 ROUT Differential output resistance 85 100 120 TOSKEW Transmitter output skew 2 8 ps CEXT Recommended external AC coupling capacitor(2) 100 200 nF 800 mV 1200 - DVPPOUT/2 75 mV Notes: 1. 2. The output swing and preemphasis levels are programmable using the attributes discussed in Virtex-5 FPGA RocketIO GTX Transceiver User Guide and can result in values lower than reported in this table. Values outside of this range can be used as appropriate to conform to specific protocols and standards. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 19 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics X-Ref Target - Figure 6 +V P VSEOUT N 0 ds714_06_012109 Figure 6: Single-Ended Output Voltage Swing X-Ref Target - Figure 7 +V DVPPOUT DVPPIN 0 -V P-N ds714_07_012109 Figure 7: Peak-to-Peak Differential Output Voltage Table 41 summarizes the DC specifications of the clock input of the GTX_DUAL tile. Figure 8 shows the single-ended input voltage swing. Figure 9 shows the peak-to-peak differential clock input voltage swing. Consult Virtex-5 FPGA RocketIO GTX Transceiver User Guide for further details. Table 41: GTX_DUAL Tile Clock DC Input Level Specification(1) Symbol DC Parameter Conditions Min Typ Max Units VIDIFF Differential peak-to-peak input voltage 210 800 2000 mV VISE Single-ended input voltage 105 400 750 mV RIN Differential input resistance 90 105 130 CEXT Required external AC coupling capacitor 100 nF Notes: 1. VMIN = 0V and VMAX = 1200 mV X-Ref Target - Figure 8 +V P VISE N 0 ds714_08_012109 Figure 8: Single-Ended Clock Input Voltage Swing Peak-to-Peak X-Ref Target - Figure 9 +V P-N VIDIFF 0 -V ds714_09_012109 Figure 9: Differential Clock Input Voltage Swing Peak-to-Peak DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 20 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics GTX_DUAL Tile Switching Characteristics Consult Virtex-5 FPGA RocketIO GTX Transceiver User Guide for further information. Table 42: GTX_DUAL Tile Performance Symbol Speed Grade Description -2I -1I -1M Units FGTXMAX Maximum GTX transceiver data rate 6.5 4.25 4.25 Gb/s FGPLLMAX Maximum PLL frequency 3.25 3.25 3.25 GHz FGPLLMIN Minimum PLL frequency 1.5 1.5 1.5 GHz Table 43: Dynamic Reconfiguration Port (DRP) in the GTX_DUAL Tile Switching Characteristics Symbol FGTXDRPCLK Speed Grade Description GTXDRPCLK maximum frequency -2I -1I -1M 175 150 150 Units MHz Table 44: GTX_DUAL Tile Reference Clock Switching Characteristics Symbol Description Conditions All Speed Grades Min Typ Max Units FGCLK Reference clock frequency range(1) CLK TRCLK Reference clock rise time 20% - 80% 200 ps TFCLK Reference clock fall time 80% - 20% 200 ps TDCREF Reference clock duty cycle CLK TGJTT Reference clock total jitter(2)(3) TLOCK TPHASE 60 40 650 50 60 MHz % At 100 KHz -145 dBc/Hz At 1 MHz -150 dBc/Hz Clock recovery frequency acquisition time Initial PLL lock 0.25 Clock recovery phase acquisition time Lock to data after PLL has locked to the reference clock 1 ms 200 s Notes: 1. 2. 3. GREFCLK can be used for serial bit rates up to 1 Gb/s; however, Jitter Specifications are not guaranteed when using GREFCLK. GTX_DUAL jitter characteristics measured using a clock with specification TGJTT. A reference clock with higher phase noise can be used with link margin trade off. The selection of the reference clock is application dependent. This parameter describes the quality of the reference clock used during transceiver jitter characterization - see Table 46, page 22 and Table 47, page 23. X-Ref Target - Figure 10 TRCLK 80% 20% TFCLK ds714_10_012109 Figure 10: Reference Clock Timing Parameters DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 21 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 45: GTX_DUAL Tile User Clock Switching Characteristics Symbol Description Conditions FTXOUT TXOUTCLK maximum frequency FRXREC RXRECCLK maximum frequency TRX RXUSRCLK maximum frequency TRX2 RXUSRCLK2 maximum frequency Device Internal 20-bit datapath FXT Internal 16-bit datapath Speed Grade -2I -1I -1M 325 212.5 212.5 Units MHz FXT 406.25 265.625 265.625 MHz FXT 406.25 265.625 265.625 MHz 2 byte or 4 byte interface FXT 406.25 265.625 265.625 MHz 1 byte interface FXT 312.5 235.625 235.625 MHz 390.625 265.625 265.625 MHz 2 byte interface 203.125 132.813 132.813 MHz TTX TXUSRCLK maximum frequency 2 byte or 4 byte interface 4 byte interface FXT 406.25 265.625 265.625 MHz TTX2 TXUSRCLK2 maximum frequency 1 byte interface FXT 312.5 235.625 235.625 MHz 2 byte interface 390.625 265.625 265.625 MHz 4 byte interface 203.125 132.813 132.813 MHz Min Typ Max Units Gb/s ps ps ps mV ns UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI Table 46: GTX_DUAL Tile Transmitter Switching Characteristics Symbol FGTXTX TRTX TFTX TLLSKEW VTXOOBVDPP TTXOOBTRANSITION TJ6.5 DJ6.5 TJ5.0 DJ5.0 TJ4.25 DJ4.25 TJ3.75 DJ3.75 TJ3.2 DJ3.2 TJ3.2L DJ3.2L TJ2.5 DJ2.5 TJ1.25 DJ1.25 TJ750 DJ750 TJ150 DJ150 Description Serial data rate range TX Rise time TX Fall time TX lane-to-lane skew(1) Electrical idle amplitude Electrical idle transition time Total Jitter(2) Deterministic Jitter(2) Total Jitter(2) Deterministic Jitter(2) Total Jitter(2) Deterministic Jitter(2) Total Jitter(2) Deterministic Jitter(2) Total Jitter(2) Deterministic Jitter(2) Total Jitter(2) Deterministic Jitter(2) Total Jitter(2) Deterministic Jitter(2) Total Jitter(2) Deterministic Jitter(2) Total Jitter(2)(4) Deterministic Jitter(2)(4) Total Jitter(2)(4) Deterministic Jitter(2)(4) Condition 0.15 20%-80% 80%-20% FGTXMAX 120 120 350 15 75 6.5 Gb/s 0.33 0.17 5.0 Gb/s 0.33 0.15 4.25 Gb/s 0.35(5) 0.14 3.75 Gb/s 0.34 0.16 3.2 Gb/s 3.2 Gb/s(3) 0.20 0.10 0.36 0.16 2.5 Gb/s 0.20 0.08 1.25 Gb/s 0.15 0.06 750 Mb/s 0.10 0.03 150 Mb/s 0.02 0.01 Notes: 1. 2. 3. 4. 5. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTX_DUAL sites. Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1. These values are NOT intended for protocol specific compliance determinations. PLL frequency at 1.6 GHz and OUTDIV = 1. GREFCLK can be used for serial data rates up to 1.0 Gb/s, but performance is not guaranteed. M-temperature only (0.33 UI for I-temperature) DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 22 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 47: GTX_DUAL Tile Receiver Switching Characteristics Symbol Description Min Typ Max Units RX oversampler not enabled 0.75 FGTXMAX Gb/s RX oversampler enabled 0.15 0.75 Gb/s 75 ns 55 135 mV -5000 0 ppm 512 UI FGTXRX Serial data rate TRXELECIDLE TIme for RXELECIDLE to respond to loss or restoration of data OOBDETECT_THRESHOLD = 110 RXOOBVDPP OOB detect threshold peak-to-peak OOBDETECT_THRESHOLD = 110 RXSST Receiver spread-spectrum tracking(1) Modulated @ 33 KHz RXRL Run length (CID) Internal AC capacitor bypassed Data/REFCLK PPM offset tolerance CDR 2nd-order CDR 2nd-order JT_SJ6.5 Sinusoidal Jitter(3) 6.5 Gb/s 0.44 UI JT_SJ5.0 Sinusoidal Jitter(3) 5.0 Gb/s 0.44 UI Sinusoidal Jitter(3) 4.25 Gb/s 0.44 UI Sinusoidal Jitter(3) 3.75 Gb/s 0.44 UI Sinusoidal Jitter(3) 3.2 Gb/s 0.45 UI Sinusoidal Jitter(3) 3.2 0.45 UI Sinusoidal Jitter(3) 2.5 Gb/s 0.50 UI Sinusoidal Jitter(3) 1.25 Gb/s 0.50 UI Sinusoidal Jitter(3)(5) 750 Mb/s 0.57 UI Sinusoidal Jitter(3)(5) 150 Mb/s 0.57 UI RXPPMTOL SJ Jitter loop disabled -200 200 ppm loop enabled -2000 2000 ppm Tolerance(2) JT_SJ4.25 JT_SJ3.75 JT_SJ3.2 JT_SJ3.2L JT_SJ2.5 JT_SJ1.25 JT_SJ750 JT_SJ150 SJ Jitter Tolerance with Stressed Gb/s(4) Eye(2) JT_TJSE4.25 Total Jitter with Stressed Eye(6) 4.25 Gb/s 0.69 UI JT_SJSE4.25 Sinusoidal Jitter with Stressed Eye(6) 4.25 Gb/s 0.1 UI Notes: 1. 2. 3. 4. 5. 6. Using PLL_RXDIVSEL_OUT = 1, 2, and 4. All jitter values are based on a Bit Error Ratio of 1e-12. Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter. PLL frequency at 1.6 GHz and OUTDIV = 1. GREFCLK can be used for serial data rates up to 1.0 Gb/s, but performance is not guaranteed. Composite jitter with RX equalizer enabled. DFE disabled. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 23 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics CRC Block Switching Characteristics Table 48: CRC Block Switching Characteristics Symbol FCRC Speed Grade Description CRCCLK maximum frequency -2I -1I -1M 325 270 270 Units MHz Ethernet MAC Switching Characteristics Consult Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide for further information. Table 49: Maximum Ethernet MAC Performance Symbol FTEMACCLIENT FTEMACPHY Description Conditions Client interface maximum frequency Physical interface maximum frequency Speed Grade Units -2I -1I -1M 10 Mb/s - 8-bit width 1.25 1.25 1.25 MHz 100 Mb/s - 8-bit width 12.5 12.5 12.5 MHz 1000 Mb/s - 8-bit width 125 125 125 MHz 2000 Mb/s - 16-bit width 125 125 125 MHz 10 Mb/s - 4-bit width 2.5 2.5 2.5 MHz 100 Mb/s - 4-bit width 25 25 25 MHz 1000 Mb/s - 8-bit width 125 125 125 MHz 2000 Mb/s - 8-bit width 250 250 250 MHz Endpoint Block for PCI Express Designs Switching Characteristics Consult Virtex-5 FPGA Integrated Endpoint Block for PCI Express Designs User Guide for further information. Table 50: Maximum Performance for PCI Express Designs Symbol Description Speed Grade -2I -1I -1M Units FPCIECORE Core clock maximum frequency 250 250 250 MHz FPCIEUSER User clock maximum frequency 250 250 250 MHz DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 24 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics System Monitor Analog-to-Digital Converter Specification Table 51: Analog-to-Digital Specifications Parameter Symbol Comments/Conditions Min Typ Max Units AVDD = 2.5V 2%, VREFP = 2.5V, VREFN = 0V, ADCCLK = 5.2 MHz, TA = TMIN to TMAX, Typical values at TA=+25C DC Accuracy: All external input channels such as VP/VN and VAUXP[15:0]/VAUXN[15:0], Unipolar Mode, and Common Mode = 0V Resolution 10 Integral Nonlinearity INL Differential Nonlinearity DNL Unipolar Offset Error(1) Bipolar Offset No missing codes (TMIN to TMAX) Guaranteed Monotonic Uncalibrated Error(1) Bits 2 Uncalibrated measured in bipolar mode 2 LSBs 0.9 LSBs 30 LSBs 2 30 LSBs 0.2 2.0 % Uncalibrated, Tj = -55C to 125C 0.2 2.5 % Uncalibrated measured in bipolar mode, Tj = -40C to 100C 0.2 2.0 % Uncalibrated measured in bipolar mode, Tj = -55C to 125C 0.2 2.5 % Gain Error(1) Uncalibrated, Tj = -40C to 100C Bipolar Gain Error(1) Total Unadjusted Error (Uncalibrated) TUE Deviation from ideal transfer function. VREFP - VREFN = 2.5V 10 Total Unadjusted Error (Calibrated) TUE Deviation from ideal transfer function. VREFP - VREFN = 2.5V 1 Variation of FS code with temperature 0.01 LSB/ C 70 dB Calibrated Gain Temperature Coefficient DC Common-Mode Reject CMRRDC VN = VCM = 0.5V 0.5V, VP - VN = 100mV LSBs 2 LSBs Conversion Rate(2) Conversion Time - Continuous tCONV Number of CLK cycles Conversion Time - Event tCONV Number of CLK cycles T/H Acquisition Time tACQ Number of CLK cycles 26 32 21 4 DRP Clock Frequency DCLK DRP clock frequency 8 250 MHz ADC Clock Frequency ADCCLK Derived from DCLK, Tj = -40C to 100C 1 5.2 MHz Derived from DCLK, Tj = -55C to 125C 2.5 5.2 MHz 40 60 % 0 1 V -0.25 +0.25 0 +0.5 CLK Duty cycle Analog Inputs(3) Dedicated Analog Inputs Input Voltage Range VP - VN Unipolar Operation Differential Inputs Unipolar Common Mode Range (FS input) Differential Common Mode Range (FS input) +0.3 Bandwidth Auxiliary Analog Inputs Input Voltage Range VAUXP[0] /VAUXN[0] to VAUXP[15] /VAUXN[15] Unipolar Operation Differential Operation Unipolar Common Mode Range (FS input) Differential Common Mode Range (FS input) Bandwidth Input Leakage Current A/D not converting, ADCCLK stopped Input Capacitance On-chip Supply Monitor Error +0.7 20 MHz 0 1 -0.25 +0.25 0 +0.5 +0.3 +0.7 10 kHz 1.0 A 10 VCCINT and VCCAUX with calibration enabled Volts pF 1.0 % Reading DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 25 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 51: Analog-to-Digital Specifications (Cont'd) Parameter Symbol On-chip Temperature Monitor Error Comments/Conditions Min Typ -40C to +125C with calibration enabled Max Units 4 C External Reference Inputs(4) Positive Reference Input Voltage VREFP Range Measured Relative to VREFN 2.45 2.5 2.55 Volts Negative Reference Input Voltage Range VREFN Measured Relative to AGND -50 0 100 mV Input current IREF ADCCLK = 5.2 MHz 100 A Analog Power Supply AVDD Measured Relative to AVSS 2.55 V Analog Supply Current AIDD ADCCLK = 5.2 MHz 13 mA Power Requirements 2.45 2.5 5 Notes: 1. 2. 3. 4. Offset and gain errors are removed by enabling the System Monitor automatic gain calibration feature. See Virtex-5 FPGA System Monitor User Guide. See "System Monitor Timing" in Virtex-5 FPGA System Monitor User Guide. See "Analog Inputs" in Virtex-5 FPGA System Monitor User Guide for a detailed description. Any variation in the reference voltage from the nominal VREFP = 2.5V and VREFN = 0V will result is a deviation from the ideal transfer function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external ratiometric type applications allowing the supply voltage and reference to vary by 2% is permitted. Performance Characteristics This section provides the performance characteristics of some common functions and designs implemented in Virtex-5Q devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same guidelines as the Switching Characteristics. Table 52 shows internal (register-to-register) performance. Table 52: Register-to-Register Performance -2I Register-to-Register (with I/O Delays) Speed Grade -1I -1M 500 500 467 438 500 500 500 377 500 500 500 381 450 450 407 428 428 450 447 323 450 450 450 333 450 450 407 428 428 450 447 323 450 450 450 333 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 450 400 400 MHz 500 500 500 450 450 450 450 450 450 MHz MHz MHz Description Basic Functions 16:1 Multiplexer 32:1 Multiplexer 64:1 Multiplexer 9 x 9 Logic Multiplier with 4 pipestages 9 x 9 Logic Multiplier with 5 pipestages 16-bit Adder 32-bit Adder 64-bit Adder Register to LUT to Register 16-bit Counter 32-bit Counter 64-bit Counter Memory Cascaded block RAM (64K) Block RAM Pipelined Single-Port 512 x 36 bits Single-Port 4096 x 4 bits Dual-Port A: 4096 x 4 bits and B: 1024 x 18 bits DS714 (v2.2) January 17, 2011 Product Specification Units www.xilinx.com 26 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 52: Register-to-Register Performance (Cont'd) -2I Register-to-Register (with I/O Delays) Speed Grade -1I -1M 500 450 450 MHz 500 500 450 450 450 450 MHz MHz MHz 500 500 500 450 450 438 450 450 438 MHz MHz MHz 500 500 500 500 500 500 458 500 450 450 450 450 450 450 397 450 450 450 450 450 450 450 397 450 MHz MHz MHz MHz MHz MHz MHz MHz Description Distributed RAM Single-Port 16 x 8 Single-Port 32 x 8 Single-Port 64 x 8 Dual-Port 16 x 8 Shift Register Chain 16-bit 32-bit 64-bit Dedicated Arithmetic Logic DSP48E Quad 12-bit Adder/Subtracter DSP48E Dual 24-bit Adder/Subtracter DSP48E 48-bit Adder/Subtracter DSP48E 48-bit Counter DSP48E 48-bit Comparator DSP48E 25 x 18 bit Pipelined Multiplier DSP48E Direct 4-tap FIR Filter Pipelined DSP48E Systolic n-tap FIR Filter Pipelined Units Notes: 1. Device used is the XQ5VLX50T- FF1136. Table 53: Interface Performances Speed Grade Description -2I -1I -1M SFI-4.1 (SDR LVDS Interface)(1) 710 MHz 645 MHz 645 MHz Interface)(2) 1.25 Gb/s 1.0 Gb/s 1.0 Gb/s 200 MHz 200 MHz 200 MHz Networking Applications SPI-4.2 (DDR LVDS Memory Interfaces DDR(3) DDR2(4) QDR II 300 MHz 267 MHz 267 MHz SRAM(5) 300 MHz 250 MHz 250 MHz II(6) 300 MHz 250 MHz 250 MHz RLDRAM Notes: 1. Performance defined using design implementation described in application note XAPP856, SFI-4.1 16-Channel SDR Interface with Bus Alignment. 2. Performance defined using design implementation described in application note XAPP860, 16-Channel, DDR LVDS Interface with Real-time Window Monitoring. 3. Performance defined using design implementation described in application note XAPP851, DDR SDRAM Controller. 4. Performance defined using design implementation described in application note XAPP858, High-Performance DDR2 SDRAM Interface Data Capture. 5. Performance defined using design implementation described in application note XAPP853, QDRII SRAM Interface. 6. Performance defined using design implementation described in application note XAPP852, Synthesizable RLDRAM II Controller. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 27 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Switching Characteristics All values represented in this data sheet are based on speed specification version 1.71. Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows: Advance These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some underreporting might still occur. All specifications are always representative of worst-case supply voltage and junction temperature conditions. Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 54 correlates the current status of each Virtex-5Q device on a per speed grade basis. Table 54: Virtex-5Q Device Speed Grade Designations Device Preliminary Speed Grade Designations Advance Preliminary Production These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. XQ5VLX30T -2I, -1I XQ5VLX85 -2I, -1I XQ5VLX110 -2I, -1I XQ5VLX110T -2I, -1I XQ5VLX155T -2I, -1I Production XQ5VLX220T -2I, -1I These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. XQ5VLX330T -1I XQ5VSX50T -2I, -1I XQ5VSX95T -2I, -1I XQ5VSX240T -1I XQ5VFX70T -2I, -1I, -1M XQ5VFX100T -2I, -1I, -1M XQ5VFX130T -2I, -1I XQ5VFX200T -1I Testing of Switching Characteristics All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Virtex-5Q devices. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 28 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Production Silicon and ISE Software Status In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent speed specification releases. Table 55 lists the production released Virtex-5Q family member, speed grade, and the minimum corresponding supported speed specification version and ISE(R) software revisions. The ISE software and speed specifications listed are the minimum releases required for production. All subsequent releases of software and speed specifications are valid. Table 55: Virtex-5Q Device Production Software(1) and Speed Specification Release Device Speed Grade Designations -2I -1I -1M XQ5VLX30T ISE 11.2 v1.65 N/A XQ5VLX85 ISE 11.2 v1.65 N/A XQ5VLX110 ISE 11.2 v1.65 N/A XQ5VLX110T ISE 11.2 v1.65 N/A XQ5VLX155T ISE 11.2 v1.65 N/A XQ5VLX220T ISE 12.2 v1.71 ISE 11.2 v1.65 N/A ISE 11.2 v1.65 N/A XQ5VLX330T N/A XQ5VSX50T ISE 11.2 v1.65 N/A XQ5VSX95T ISE 12.2 v1.71 ISE 11.2 v1.65 N/A ISE 11.2 v1.65 N/A XQ5VSX240T N/A XQ5VFX70T ISE 11.2 v1.65 ISE 12.4 v1.71 XQ5VFX100T ISE 11.2 v1.65 ISE 12.4 v1.71 XQ5VFX130T ISE 11.2 v1.65 N/A XQ5VFX200T N/A ISE 11.2 v1.65 N/A Notes: 1. 2. DS714 (v2.2) January 17, 2011 Product Specification Listed software revisions are those for production-released Virtex-5Q family members. Blank entries indicate a device and/or speed grade in advance or preliminary status. www.xilinx.com 29 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics IOB Pad Input/Output/3-State Switching Characteristics Table 56 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer. TIOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer. TIOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer. Table 57, page 34 summarizes the value of TIOTPHZ. TIOTPHZ is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). Table 56: IOB Switching Characteristics I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade Units -2(I) -1(I) -1(M) -2(I) -1(I) -1(M) -2(I) -1(I) -1(M) LVDS_25 0.90 1.06 1.11 1.29 1.44 1.79 1.29 1.44 1.79 ns LVDSEXT_25 1.16 1.30 1.36 1.34 1.49 1.82 1.34 1.49 1.82 ns HT_25 0.90 1.06 1.11 1.26 1.40 1.79 1.26 1.40 1.79 ns BLVDS_25 0.90 1.06 1.12 1.38 1.58 1.91 1.38 1.58 1.91 ns RSDS_25 (point to point) 0.90 1.06 1.11 1.29 1.44 1.79 1.29 1.44 1.79 ns ULVDS_25 0.90 1.06 1.11 1.27 1.41 1.79 1.27 1.41 1.79 ns PCI33_3 0.70 0.82 1.05 2.06 2.38 2.41 2.06 2.38 2.41 ns PCI66_3 0.70 0.82 1.05 2.06 2.38 2.41 2.06 2.38 2.41 ns PCI-X 0.70 0.82 1.05 1.56 1.80 2.03 1.56 1.80 2.03 ns GTL 0.85 1.00 1.11 1.63 1.86 2.10 1.63 1.86 2.10 ns GTLP 0.85 1.00 1.05 1.68 1.93 2.14 1.68 1.93 2.14 ns HSTL_I 0.85 1.00 1.07 1.57 1.79 1.96 1.57 1.79 1.96 ns HSTL_II 0.85 1.00 1.05 1.53 1.74 1.84 1.53 1.74 1.84 ns HSTL_III 0.85 1.00 1.40 1.60 1.85 2.03 1.60 1.85 2.03 ns HSTL_IV 0.85 1.00 1.40 1.60 1.83 2.07 1.60 1.83 2.07 ns HSTL_I _18 0.85 1.00 1.26 1.55 1.77 1.91 1.55 1.77 1.91 ns HSTL_II _18 0.85 1.00 1.13 1.51 1.72 1.79 1.51 1.72 1.79 ns HSTL_III _18 0.85 1.00 1.45 1.61 1.85 1.98 1.61 1.85 1.98 ns HSTL_IV_18 0.85 1.00 1.45 1.57 1.81 1.92 1.57 1.81 1.92 ns SSTL2_I 0.85 1.00 1.11 1.64 1.78 1.94 1.64 1.78 1.94 ns SSTL2_II 0.85 1.00 1.11 1.55 1.76 1.83 1.55 1.76 1.83 ns LVTTL, Slow, 2 mA 0.70 0.82 1.02 4.47 5.01 6.05 4.47 5.01 6.05 ns LVTTL, Slow, 4 mA 0.70 0.82 1.02 3.09 3.41 4.13 3.09 3.41 4.13 ns LVTTL, Slow, 6 mA 0.70 0.82 1.02 2.91 3.29 3.91 2.91 3.29 3.91 ns LVTTL, Slow, 8 mA 0.70 0.82 1.02 2.30 2.61 2.91 2.30 2.61 2.91 ns LVTTL, Slow, 12 mA 0.70 0.82 1.02 2.15 2.46 2.56 2.15 2.46 2.56 ns LVTTL, Slow, 16 mA 0.70 0.82 1.02 2.04 2.34 2.47 2.04 2.34 2.47 ns LVTTL, Slow, 24 mA 0.70 0.82 1.02 2.07 2.38 2.48 2.07 2.38 2.48 ns DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 30 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 56: IOB Switching Characteristics (Cont'd) I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade Units -2(I) -1(I) -1(M) -2(I) -1(I) -1(M) -2(I) -1(I) -1(M) LVTTL, Fast, 2 mA 0.70 0.82 1.02 3.61 4.05 5.58 3.61 4.05 5.58 ns LVTTL, Fast, 4 mA 0.70 0.82 1.02 2.55 2.90 3.72 2.55 2.90 3.72 ns LVTTL, Fast, 6 mA 0.70 0.82 1.02 2.31 2.63 3.34 2.31 2.63 3.34 ns LVTTL, Fast, 8 mA 0.70 0.82 1.02 1.82 2.09 2.39 1.82 2.09 2.39 ns LVTTL, Fast, 12 mA 0.70 0.82 1.02 1.63 1.89 2.31 1.63 1.89 2.31 ns LVTTL, Fast, 16 mA 0.70 0.82 1.02 1.57 1.81 2.27 1.57 1.81 2.27 ns LVTTL, Fast, 24 mA 0.70 0.82 1.02 1.52 1.74 2.27 1.52 1.74 2.27 ns LVCMOS33, Slow, 2 mA 0.70 0.82 1.02 3.96 4.44 6.05 3.96 4.44 6.05 ns LVCMOS33, Slow, 4 mA 0.70 0.82 1.02 3.09 3.49 4.13 3.09 3.49 4.13 ns LVCMOS33, Slow, 6 mA 0.70 0.82 1.02 2.86 3.24 3.89 2.86 3.24 3.89 ns LVCMOS33, Slow, 8 mA 0.70 0.82 1.02 2.26 2.57 2.91 2.26 2.57 2.91 ns LVCMOS33, Slow, 12 mA 0.70 0.82 1.02 2.14 2.42 2.56 2.14 2.42 2.56 ns LVCMOS33, Slow, 16 mA 0.70 0.82 1.02 2.04 2.31 2.44 2.04 2.31 2.44 ns LVCMOS33, Slow, 24 mA 0.70 0.82 1.02 2.07 2.35 2.48 2.07 2.35 2.48 ns LVCMOS33, Fast, 2 mA 0.70 0.82 1.02 3.20 3.59 5.56 3.20 3.59 5.56 ns LVCMOS33, Fast, 4 mA 0.70 0.82 1.02 2.50 2.84 3.70 2.50 2.84 3.70 ns LVCMOS33, Fast, 6 mA 0.70 0.82 1.02 2.27 2.59 3.32 2.27 2.59 3.32 ns LVCMOS33, Fast, 8 mA 0.70 0.82 1.02 1.79 2.05 2.35 1.79 2.05 2.35 ns LVCMOS33, Fast, 12 mA 0.70 0.82 1.02 1.61 1.86 2.31 1.61 1.86 2.31 ns LVCMOS33, Fast, 16 mA 0.70 0.82 1.02 1.56 1.80 2.28 1.56 1.80 2.28 ns LVCMOS33, Fast, 24 mA 0.70 0.82 1.02 1.51 1.74 2.26 1.51 1.74 2.26 ns LVCMOS25, Slow, 2 mA 0.70 0.82 0.82 3.97 4.42 5.06 3.97 4.42 5.06 ns LVCMOS25, Slow, 4 mA 0.70 0.82 0.82 2.60 2.94 3.71 2.60 2.94 3.71 ns LVCMOS25, Slow, 6 mA 0.70 0.82 0.82 2.41 2.74 3.42 2.41 2.74 3.42 ns LVCMOS25, Slow, 8 mA 0.70 0.82 0.82 2.26 2.56 2.93 2.26 2.56 2.93 ns LVCMOS25, Slow, 12 mA 0.70 0.82 0.82 2.31 2.63 2.73 2.31 2.63 2.73 ns LVCMOS25, Slow, 16 mA 0.70 0.82 0.82 2.02 2.30 2.31 2.02 2.30 2.31 ns LVCMOS25, Slow, 24 mA 0.70 0.82 0.82 2.04 2.34 2.37 2.04 2.34 2.37 ns LVCMOS25, Fast, 2 mA 0.70 0.82 0.82 3.41 3.82 4.48 3.41 3.82 4.48 ns LVCMOS25, Fast, 4 mA 0.70 0.82 0.82 2.08 2.37 3.23 2.08 2.37 3.23 ns LVCMOS25, Fast, 6 mA 0.70 0.82 0.82 1.92 2.20 2.89 1.92 2.20 2.89 ns LVCMOS25, Fast, 8 mA 0.70 0.82 0.82 1.83 2.09 2.38 1.83 2.09 2.38 ns LVCMOS25, Fast, 12 mA 0.70 0.82 0.82 1.69 1.94 1.94 1.69 1.94 1.94 ns LVCMOS25, Fast, 16 mA 0.70 0.82 0.82 1.60 1.85 1.99 1.60 1.85 1.99 ns LVCMOS25, Fast, 24 mA 0.70 0.82 0.82 1.54 1.76 1.98 1.54 1.76 1.98 ns LVCMOS18, Slow, 2 mA 0.76 0.89 1.14 4.56 5.09 6.81 4.56 5.09 6.81 ns LVCMOS18, Slow, 4 mA 0.76 0.89 1.14 3.32 3.75 4.30 3.32 3.75 4.30 ns LVCMOS18, Slow, 6 mA 0.76 0.89 1.14 2.61 2.97 3.76 2.61 2.97 3.76 ns LVCMOS18, Slow, 8 mA 0.76 0.89 1.14 2.37 2.69 3.32 2.37 2.69 3.32 ns DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 31 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 56: IOB Switching Characteristics (Cont'd) I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade Units -2(I) -1(I) -1(M) -2(I) -1(I) -1(M) -2(I) -1(I) -1(M) LVCMOS18, Slow, 12 mA 0.76 0.89 1.14 2.16 2.47 2.59 2.16 2.47 2.59 ns LVCMOS18, Slow, 16 mA 0.76 0.89 1.14 2.14 2.45 2.53 2.14 2.45 2.53 ns LVCMOS18, Fast, 2 mA 0.76 0.89 1.14 3.71 4.16 6.23 3.71 4.16 6.23 ns LVCMOS18, Fast, 4 mA 0.76 0.89 1.14 2.61 2.98 3.80 2.61 2.98 3.80 ns LVCMOS18, Fast, 6 mA 0.76 0.89 1.14 2.06 2.35 3.30 2.06 2.35 3.30 ns LVCMOS18, Fast, 8 mA 0.76 0.89 1.14 1.87 2.13 2.66 1.87 2.13 2.66 ns LVCMOS18, Fast, 12 mA 0.76 0.89 1.14 1.68 1.93 2.07 1.68 1.93 2.07 ns LVCMOS18, Fast, 16 mA 0.76 0.89 1.14 1.61 1.86 1.97 1.61 1.86 1.97 ns LVCMOS15, Slow, 2 mA 0.83 0.98 1.23 3.84 4.34 5.08 3.84 4.34 5.08 ns LVCMOS15, Slow, 4 mA 0.83 0.98 1.23 2.40 2.74 3.48 2.40 2.74 3.48 ns LVCMOS15, Slow, 6 mA 0.83 0.98 1.23 2.20 2.52 2.55 2.20 2.52 2.55 ns LVCMOS15, Slow, 8 mA 0.83 0.98 1.23 2.12 2.43 2.46 2.12 2.43 2.46 ns LVCMOS15, Slow, 12 mA 0.83 0.98 1.23 1.95 2.25 2.28 1.95 2.25 2.28 ns LVCMOS15, Slow, 16 mA 0.83 0.98 1.23 1.91 2.20 2.23 1.91 2.20 2.23 ns LVCMOS15, Fast, 2 mA 0.83 0.98 1.23 3.07 3.48 4.99 3.07 3.48 4.99 ns LVCMOS15, Fast, 4 mA 0.83 0.98 1.23 1.95 2.23 3.39 1.95 2.23 3.39 ns LVCMOS15, Fast, 6 mA 0.83 0.98 1.23 1.80 2.06 2.41 1.80 2.06 2.41 ns LVCMOS15, Fast, 8 mA 0.83 0.98 1.23 1.74 2.00 2.26 1.74 2.00 2.26 ns LVCMOS15, Fast, 12 mA 0.83 0.98 1.23 1.60 1.86 1.99 1.60 1.86 1.99 ns LVCMOS15, Fast, 16 mA 0.83 0.98 1.23 1.53 1.77 1.92 1.53 1.77 1.92 ns LVCMOS12, Slow, 2 mA 0.96 1.14 1.61 3.98 4.58 5.58 3.98 4.58 5.58 ns LVCMOS12, Slow, 4 mA 0.96 1.14 1.61 2.33 2.66 3.13 2.33 2.66 3.13 ns LVCMOS12, Slow, 6 mA 0.96 1.14 1.61 2.18 2.45 2.54 2.18 2.45 2.54 ns LVCMOS12, Slow, 8 mA 0.96 1.14 1.61 2.14 2.48 2.51 2.14 2.48 2.51 ns LVCMOS12, Fast, 2 mA 0.96 1.14 1.61 3.38 3.87 5.54 3.38 3.87 5.54 ns LVCMOS12, Fast, 4 mA 0.96 1.14 1.61 1.91 2.20 3.01 1.91 2.20 3.01 ns LVCMOS12, Fast, 6 mA 0.96 1.14 1.61 1.78 2.08 2.44 1.78 2.08 2.44 ns LVCMOS12, Fast, 8 mA 0.96 1.14 1.61 1.70 1.97 2.28 1.70 1.97 2.28 ns LVDCI_33 0.70 0.82 1.02 1.66 1.90 2.66 1.66 1.90 2.66 ns LVDCI_25 0.70 0.82 0.82 1.71 1.93 2.65 1.71 1.93 2.65 ns LVDCI_18 0.76 0.89 1.14 1.78 1.99 2.85 1.78 1.99 2.85 ns LVDCI_15 0.83 0.98 1.23 1.75 2.02 2.74 1.75 2.02 2.74 ns LVDCI_DV2_25 0.70 0.82 0.82 1.51 1.74 2.12 1.51 1.74 2.12 ns LVDCI_DV2_18 0.76 0.89 1.14 1.60 1.85 2.16 1.60 1.85 2.16 ns LVDCI_DV2_15 0.83 0.98 1.23 1.65 1.91 2.33 1.65 1.91 2.33 ns GTL_DCI 0.85 1.00 1.11 1.47 1.65 1.79 1.47 1.65 1.79 ns GTLP_DCI 0.85 1.00 1.05 1.52 1.76 1.94 1.52 1.76 1.94 ns LVPECL_25 0.90 1.06 1.12 1.42 1.62 1.91 1.42 1.62 1.91 ns DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 32 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 56: IOB Switching Characteristics (Cont'd) I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade Units -2(I) -1(I) -1(M) -2(I) -1(I) -1(M) -2(I) -1(I) -1(M) HSTL_I_12 0.85 1.00 1.08 1.61 1.85 1.98 1.61 1.85 1.98 ns HSTL_I_DCI 0.85 1.00 1.07 1.56 1.77 1.98 1.56 1.77 1.98 ns HSTL_II_DCI 0.85 1.00 1.05 1.48 1.69 1.86 1.48 1.69 1.86 ns HSTL_II_T_DCI 0.85 1.00 1.05 1.56 1.77 1.98 1.56 1.77 1.98 ns HSTL_III_DCI 0.85 1.00 1.40 1.72 1.95 2.27 1.72 1.95 2.27 ns HSTL_IV_DCI 0.85 1.00 1.40 1.46 1.64 1.84 1.46 1.64 1.84 ns HSTL_I_DCI_18 0.85 1.00 1.26 1.50 1.70 1.95 1.50 1.70 1.95 ns HSTL_II_DCI_18 0.85 1.00 1.13 1.43 1.64 1.77 1.43 1.64 1.77 ns HSTL_II _T_DCI_18 0.85 1.00 1.13 1.50 1.70 1.95 1.50 1.70 1.95 ns HSTL_III_DCI_18 0.85 1.00 1.45 1.69 1.91 2.16 1.69 1.91 2.16 ns HSTL_IV_DCI_18 0.85 1.00 1.45 1.44 1.62 1.84 1.44 1.62 1.84 ns DIFF_HSTL_I_18 0.90 1.06 1.10 1.55 1.77 1.91 1.55 1.77 1.91 ns DIFF_HSTL_I_DCI_18 0.90 1.06 1.10 1.50 1.70 1.91 1.50 1.70 1.91 ns DIFF_HSTL_I 0.90 1.06 1.10 1.57 1.79 1.91 1.57 1.79 1.91 ns DIFF_HSTL_I_DCI 0.90 1.06 1.10 1.56 1.77 1.95 1.56 1.77 1.95 ns DIFF_HSTL_II_18 0.90 1.06 1.10 1.51 1.72 1.91 1.51 1.72 1.91 ns DIFF_HSTL_II_DCI_18 0.90 1.06 1.10 1.43 1.64 1.91 1.43 1.64 1.91 ns DIFF_HSTL_II 0.90 1.06 1.10 1.53 1.74 1.91 1.53 1.74 1.91 ns DIFF_HSTL_II_DCI 0.90 1.06 1.10 1.48 1.69 1.91 1.48 1.69 1.91 ns SSTL2_I_DCI 0.85 1.00 1.11 1.56 1.78 3.30 1.56 1.78 3.30 ns SSTL2_II_DCI 0.85 1.00 1.11 1.48 1.70 1.97 1.48 1.70 1.97 ns SSTL2_II_T_DCI 0.85 1.00 1.11 1.56 1.78 3.30 1.56 1.78 3.30 ns SSTL18_I 0.85 1.00 1.08 1.61 1.84 1.94 1.61 1.84 1.94 ns SSTL18_II 0.85 1.00 1.08 1.53 1.75 1.81 1.53 1.75 1.81 ns SSTL18_I_DCI 0.85 1.00 1.08 1.53 1.74 1.97 1.53 1.74 1.97 ns SSTL18_II_DCI 0.85 1.00 1.08 1.44 1.64 1.86 1.44 1.64 1.86 ns SSTL18_II_T_DCI 0.85 1.00 1.08 1.53 1.74 1.97 1.53 1.74 1.97 ns DIFF_SSTL2_I 0.90 1.06 1.11 1.64 1.87 1.97 1.64 1.87 1.97 ns DIFF_SSTL2_I_DCI 0.90 1.06 1.11 1.56 1.78 1.94 1.56 1.78 1.94 ns DIFF_SSTL18_I 0.90 1.06 1.10 1.61 1.84 1.94 1.61 1.84 1.94 ns DIFF_SSTL18_I_DCI 0.90 1.06 1.10 1.53 1.74 1.94 1.53 1.74 1.94 ns DIFF_SSTL2_II 0.90 1.06 1.11 1.55 1.76 1.91 1.55 1.76 1.91 ns DIFF_SSTL2_II_DCI 0.90 1.06 1.11 1.48 1.70 1.90 1.48 1.70 1.90 ns DIFF_SSTL18_II 0.90 1.06 1.10 1.53 1.75 1.91 1.53 1.75 1.91 ns DIFF_SSTL18_II_DCI 0.90 1.06 1.10 1.44 1.64 1.91 1.44 1.64 1.91 ns Notes: 1. M-temperature IOB delays are slightly larger than timing analyzer/speeds specification values. Correct values are listed in this table. It is necessary to allow for this difference in the design. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 33 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 57: IOB 3-state ON Output Switching Characteristics (TIOTPHZ) Symbol TIOTPHZ Speed Grade Description T input to Pad high-impedance -2I -1I -1M 1.01 1.12 1.12 Units ns I/O Standard Adjustment Measurement Methodology Input Delay Measurements Table 58 shows the test setup parameters used for measuring input delay. Table 58: Input Delay Measurement Methodology Description LVTTL (Low-Voltage Transistor-Transistor Logic) LVCMOS (Low-Voltage CMOS), 3.3V LVCMOS, 2.5V LVCMOS, 1.8V LVCMOS, 1.5V LVCMOS, 1.2V PCI (Peripheral Component Interconnect), 33 MHz, 3.3V PCI, 66 MHz, 3.3V PCI-X, 133 MHz, 3.3V GTL (Gunning Transceiver Logic) I/O Standard Attribute LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33_3 PCI66_3 PCIX GTL VL (1)(2) 0 0 0 0 0 0 VH(1)(2) VMEAS (1)(4)(5) 3.0 1.4 3.3 1.65 2.5 1.25 1.8 0.9 1.5 0.75 1.2 0.6 Per PCITM Specification Per PCI Specification Per PCI-XTM Specification VREF - 0.2 VREF (1)(3)(5) - - - - - - - - - GTLP HSTL_I, HSTL_II HSTL_III, HSTL_IV HSTL_I_18, HSTL_II_18 HSTL_III_18, HSTL_IV_18 VREF - 0.2 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF + 0.2 VREF + 0.2 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF - 0.5 VREF + 0.5 VREF 1.08 SSTL (Stub Terminated Transceiver Logic), Class I & II, 3.3V SSTL3_I, SSTL3_II VREF - 1.00 VREF + 1.00 VREF 1.5 SSTL, Class I & II, 2.5V SSTL, Class I & II, 1.8V AGP-2X/AGP (Accelerated Graphics Port) SSTL2_I, SSTL2_II SSTL18_I, SSTL18_II AGP 1.25 0.90 AGP Spec LVDS_25 VREF + 0.75 VREF + 0.5 VREF + (0.2 xVCCO) 1.2 + 0.125 VREF VREF LVDS (Low-Voltage Differential Signaling), 2.5V VREF - 0.75 VREF - 0.5 VREF - (0.2 xVCCO) 1.2 - 0.125 LVDSEXT (LVDS Extended Mode), 2.5V LDT (HyperTransport), 2.5V LVPECL (Low-Voltage Positive Emitter-Coupled Logic), 2.5V LVDSEXT_25 LDT_25 LVPECL_25 1.2 - 0.125 0.6 - 0.125 1.15 - 0.3 1.2 + 0.125 0.6 + 0.125 1.15 - 0.3 0(6) 0(6) 0(6) GTL Plus HSTL (High-Speed Transceiver Logic), Class I & II HSTL, Class III & IV HSTL, Class I & II, 1.8V HSTL, Class III & IV, 1.8V VREF VREF VREF VREF VREF 0.80 1.0 0.75 0.90 0.90 VREF 0(6) Notes: 1. 2. 3. 4. 5. 6. The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other DCI standards are the same for the corresponding non-DCI standards. Input waveform switches between VL and VH. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values listed are typical. Input voltage level from which measurement starts. This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 11, page 35. The value given is the differential input voltage. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 34 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Output Delay Measurements X-Ref Target - Figure 12 FPGA Output Output delays are measured using a Tektronix P6245 TDS500/600 probe (< 1 pF) across approximately 4" of FR4 microstrip trace. Standard termination was used for all testing. The propagation delay of the 4" trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in Figure 11 and Figure 12. + RREF VMEAS CREF - ds714_12_012109 X-Ref Target - Figure 11 Figure 12: Differential Test Setup VREF Measurements and test conditions are reflected in the IBIS models except where the IBIS format precludes it. Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using the following method: RREF FPGA Output VMEAS (voltage level when taking delay measurement) 1. Simulate the output driver of choice into the generalized test setup, using values from Table 59. CREF (probe capacitance) 2. Record the time to VMEAS . DS714_11_012109 3. Simulate the output driver of choice into the actual PCB trace and load, using the appropriate IBIS model or capacitance value to represent the load. Figure 11: Single Ended Test Setup 4. Record the time to VMEAS . 5. Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual propagation delay of the PCB trace. Table 59: Output Delay Measurement Methodology I/O Standard Attribute Description RREF () CREF(1) (pF) VMEAS (V) VREF (V) LVTTL (Low-Voltage Transistor-Transistor Logic) LVTTL (all) 1M 0 1.4 0 LVCMOS (Low-Voltage CMOS), 3.3V LVCMOS33 1M 0 1.65 0 LVCMOS, 2.5V LVCMOS25 1M 0 1.25 0 LVCMOS, 1.8V LVCMOS18 1M 0 0.9 0 LVCMOS, 1.5V LVCMOS15 1M 0 0.75 0 LVCMOS, 1.2V LVCMOS12 1M 0 0.6 0 PCI33_3 (rising edge) 25 10(2) 0.94 0 PCI33_3 (falling edge) 25 10(2) 2.03 3.3 PCI66_3 (rising edge) 25 10(2) 0.94 0 PCI66_3 (falling edge) 25 10(2) 2.03 3.3 PCIX (rising edge) 25 10(3) 0.94 PCIX (falling edge 25 10 (3) 2.03 3.3 GTL (Gunning Transceiver Logic) GTL 25 0 0.8 1.2 GTL Plus GTLP 25 0 1.0 1.5 HSTL (High-Speed Transceiver Logic), Class I HSTL_I 50 0 VREF 0.75 HSTL, Class II HSTL_II 25 0 VREF 0.75 HSTL, Class III HSTL_III 50 0 0.9 1.5 PCI (Peripheral Component Interface), 33 MHz, 3.3V PCI, 66 MHz, 3.3V PCI-X, 133 MHz, 3.3V DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 35 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 59: Output Delay Measurement Methodology (Cont'd) I/O Standard Attribute Description RREF () CREF(1) (pF) VMEAS (V) VREF (V) HSTL, Class IV HSTL_IV 25 0 0.9 1.5 HSTL, Class I, 1.8V HSTL_I_18 50 0 VREF 0.9 HSTL, Class II, 1.8V HSTL_II_18 25 0 VREF 0.9 HSTL, Class III, 1.8V HSTL_III_18 50 0 1.1 1.8 HSTL, Class IV, 1.8V HSTL_IV_18 25 0 1.1 1.8 SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL18_I 50 0 VREF 0.9 SSTL, Class II, 1.8V SSTL18_II 25 0 VREF 0.9 SSTL, Class I, 2.5V SSTL2_I 50 0 VREF 1.25 SSTL, Class II, 2.5V SSTL2_II 25 0 VREF 1.25 0 0(4) 1.2 0 0(4) 1.2 0 0(4) 0 0 0(4) 0.6 0 LVDS (Low-Voltage Differential Signaling), 2.5V LVDSEXT (LVDS Extended Mode), 2.5V BLVDS (Bus LVDS), 2.5V LDT (HyperTransport), 2.5V LVDS_25 LVDS_25 BLVDS_25 LDT_25 100 100 100 100 LVPECL (Low-Voltage Positive Emitter-Coupled Logic), 2.5V LVPECL_25 100 0 0(4) LVDCI/HSLVDCI (Low-Voltage Digitally Controlled Impedance), 3.3V LVDCI_33, HSLVDCI_33 1M 0 1.65 0 LVDCI/HSLVDCI, 2.5V LVDCI_25, HSLVDCI_25 1M 0 1.25 0 LVDCI/HSLVDCI, 1.8V LVDCI_18, HSLVDCI_18 1M 0 0.9 0 LVDCI/HSLVDCI, 1.5V LVDCI_15, HSLVDCI_15 1M 0 0.75 0 HSTL (High-Speed Transceiver Logic), Class I & II, with DCI HSTL_I_DCI, HSTL_II_DCI 50 0 VREF 0.75 HSTL, Class III & IV, with DCI HSTL_III_DCI, HSTL_IV_DCI 50 0 0.9 1.5 HSTL, Class I & II, 1.8V, with DCI HSTL_I_DCI_18, HSTL_II_DCI_18 50 0 VREF 0.9 HSTL, Class III & IV, 1.8V, with DCI HSTL_III_DCI_18, HSTL_IV_DCI_18 50 0 1.1 1.8 SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI SSTL18_I_DCI, SSTL18_II_DCI 50 0 VREF 0.9 SSTL, Class I & II, 2.5V, with DCI SSTL2_I_DCI, SSTL2_II_DCI 50 0 VREF 1.25 GTL (Gunning Transceiver Logic) with DCI GTL_DCI 50 0 0.8 1.2 GTL Plus with DCI GTLP_DCI 50 0 1.0 1.5 Notes: 1. 2. 3. 4. CREF is the capacitance of the probe, nominally 0 pF. Per PCI specifications. Per PCI-X specifications. The value given is the differential input voltage. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 36 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Input/Output Logic Switching Characteristics Table 60: ILOGIC Switching Characteristics Symbol Description Speed Grade -2I -1I -1M Units Setup/Hold TICE1CK/TICKCE1 CE1 pin Setup/Hold with respect to CLK 0.49 -0.24 0.59 -0.24 0.59 -0.17 ns TISRCK/TICKSR SR/REV pin Setup/Hold with respect to CLK 1.00 -0.20 1.22 -0.20 1.22 -0.22 ns TIDOCK/TIOCKD D pin Setup/Hold with respect to CLK without Delay 0.37 -0.12 0.39 -0.12 0.39 -0.12 ns TIDOCKD/TIOCKDD DDLY pin Setup/Hold with respect to CLK (using IODELAY) 0.33 -0.09 0.36 -0.08 0.36 -0.08 ns TIDI D pin to O pin propagation delay, no Delay 0.26 0.30 0.30 ns TIDID DDLY pin to O pin propagation delay (using IODELAY) 0.22 0.26 0.26 ns TIDLO D pin to Q1 pin using flip-flop as a latch without Delay 0.50 0.58 0.58 ns TIDLOD DDLY pin to Q1 pin using flip-flop as a latch (using IODELAY) 0.46 0.55 0.55 ns TICKQ CLK to Q outputs 0.52 0.60 0.60 ns TRQ SR/REV pin to OQ/TQ out 1.28 1.53 1.53 ns TGSRQ Global Set/Reset to Q outputs 7.30 10.10 10.10 ns Minimum Pulse Width, SR/REV inputs 0.95 1.20 1.20 ns, Min Combinatorial Sequential Delays Set/Reset TRPW Table 61: OLOGIC Switching Characteristics Symbol Description Speed Grade -2I -1I -1M Units Setup/Hold TODCK/TOCKD D1/D2 pins Setup/Hold with respect to CLK 0.36 -0.21 0.44 -0.21 0.44 -0.14 ns TOOCECK/TOCKOCE OCE pin Setup/Hold with respect to CLK 0.19 -0.07 0.23 -0.07 0.23 -0.04 ns TOSRCK/TOCKSR SR/REV pin Setup/Hold with respect to CLK 1.02 -0.20 1.16 -0.20 1.16 -0.20 ns TOTCK/TOCKT T1/T2 pins Setup/Hold with respect to CLK 0.34 -0.18 0.41 -0.18 0.41 -0.12 ns TOTCECK/TOCKTCE TCE pin Setup/Hold with respect to CLK 0.23 -0.06 0.29 -0.06 0.29 -0.01 ns D1 to OQ out or T1 to TQ out 0.70 0.83 0.83 ns TOCKQ CLK to OQ/TQ out 0.62 0.62 0.62 ns TRQ SR/REV pin to OQ/TQ out 1.89 2.27 2.27 ns TGSRQ Global Set/Reset to Q outputs 7.30 10.10 10.10 ns Minimum Pulse Width, SR/REV inputs 0.98 1.25 1.25 ns, Min Combinatorial TDOQ Sequential Delays Set/Reset TRPW DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 37 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Input Serializer/Deserializer Switching Characteristics Table 62: ISERDES Switching Characteristics Symbol Description Speed Grade -2I -1I -1M Units Setup/Hold for Control Lines TISCCK_BITSLIP/ TISCKC_BITSLIP BITSLIP pin Setup/Hold with respect to CLKDIV 0.11 0.00 0.12 0.00 0.12 0.00 ns TISCCK_CE / TISCKC_CE(2) CE pin Setup/Hold with respect to CLK (for CE1) 0.49 -0.24 0.59 -0.24 0.59 -0.17 ns TISCCK_CE2 / TISCKC_CE2(2) CE pin Setup/Hold with respect to CLKDIV (for CE2) 0.04 0.13 0.06 0.15 0.06 0.15 ns TISDCK_D /TISCKD_D D pin Setup/Hold with respect to CLK 0.37 -0.12 0.39 -0.12 0.39 -0.12 ns TISDCK_DDLY /TISCKD_DDLY DDLY pin Setup/Hold with respect to CLK (using IODELAY) 0.33 -0.09 0.36 -0.08 0.36 -0.08 ns TISDCK_DDR /TISCKD_DDR D pin Setup/Hold with respect to CLK at DDR mode 0.37 -0.12 0.39 -0.12 0.39 -0.12 ns TISDCK_DDLY_DDR TISCKD_DDLY_DDR D pin Setup/Hold with respect to CLK at DDR mode (using IODELAY) 0.33 -0.09 0.36 -0.08 0.36 -0.08 ns CLKDIV to out at Q pin 0.51 0.60 0.60 ns D input to DO output pin 0.22 0.26 0.26 ns Setup/Hold for Data Lines Sequential Delays TISCKO_Q Propagation Delays TISDO_DO Notes: 1. 2. Recorded at 0 tap value. TISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE/TISCKC_CE in TRACE report. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 38 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Output Serializer/Deserializer Switching Characteristics Table 63: OSERDES Switching Characteristics Symbol Description Speed Grade -2I -1I -1M Units Setup/Hold TOSDCK_D/TOSCKD_D D input Setup/Hold with respect to CLKDIV 0.24 -0.02 0.30 -0.02 0.30 -0.02 ns TOSDCK_T/TOSCKD_T(1) T input Setup/Hold with respect to CLK 0.34 -0.18 0.41 -0.18 0.41 -0.12 ns TOSDCK_T2/TOSCKD_T2(1) T input Setup/Hold with respect to CLKDIV 0.24 -0.03 0.28 -0.03 0.28 -0.03 ns TOSCCK_OCE/TOSCKC_OCE OCE input Setup/Hold with respect to CLK 0.19 -0.07 0.23 -0.07 0.23 -0.04 ns TOSCCK_S SR (Reset) input Setup with respect to CLKDIV 0.58 0.70 0.70 ns TOSCCK_TCE/TOSCKC_TCE TCE input Setup/Hold with respect to CLK 0.23 -0.06 0.29 -0.06 0.29 -0.01 ns TOSCKO_OQ Clock to out from CLK to OQ 0.60 0.61 0.61 ns TOSCKO_TQ Clock to out from CLK to TQ 0.62 0.62 0.62 ns TOSDO_TTQ T input to TQ Out 0.70 0.83 0.83 ns TOSCO_OQ Asynchronous Reset to OQ 1.82 2.19 2.19 ns TOSCO_TQ Asynchronous Reset to TQ 1.89 2.27 2.27 ns Sequential Delays Combinatorial Notes: 1. TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T/TOSCKD_T in TRACE report. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 39 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Input/Output Delay Switching Characteristics Table 64: Input/Output Delay Switching Characteristics Symbol Speed Grade Description Units -2I -1I -1M 3.00 3.00 3.00 s 200.00 200.00 200.00 MHz 10 10 10 MHz 50.00 50.00 50.00 ns IDELAYCTRL TIDELAYCTRLCO_RDY Reset to Ready for IDELAYCTRL FIDELAYCTRL_REF REFCLK frequency IDELAYCTRL_REF_PRECISION REFCLK precision TIDELAYCTRL_RPW Minimum Reset pulse width IODELAY 1/(64 x FREF x 1e6)(1) IODELAY Chain Delay Resolution TIDELAYRESOLUTION ps Pattern dependent period jitter in delay chain for clock pattern 0 0 0 Note 2 Pattern dependent period jitter in delay chain for random data pattern (PRBS 23) 5 5 5 Note 2 TIODELAY_CLK_MAX Maximum frequency of CLK input to IODELAY 250 250 250 MHz TIODCCK_CE / TIODCKC_CE CE pin Setup/Hold with respect to CK 0.34 -0.06 0.42 -0.06 0.42 -0.06 ns TIODCK_INC/ TIODCKC_INC INC pin Setup/Hold with respect to CK 0.20 0.04 0.24 0.06 0.24 0.06 ns TIODCK_RST/ TIODCKC_RST RST pin Setup/Hold with respect to CK 0.28 -0.12 0.33 -0.12 0.33 -0.12 ns TIODDO_T TSCONTROL delay to MUXE/MUXF switching and through IODELAY Note 3 Note 3 Note 3 TIODDO_IDATAIN Propagation delay through IODELAY Note 3 Note 3 Note 3 TIODDO_ODATAIN Propagation delay through IODELAY Note 3 Note 3 Note 3 TIDELAYPAT_JIT Notes: 1. Average Tap Delay at 200 MHz = 78 ps. 2. Units in ps, peak-to-peak per tap, in High Performance mode. 3. Delay depends on IODELAY tap setting. See TRACE report for actual values. CLB Switching Characteristics Table 65: CLB Switching Characteristics Symbol Speed Grade Description Units -2I -1I -1M An - Dn LUT address to A 0.09 0.10 0.10 ns, Max An - Dn LUT address to AMUX/CMUX 0.22 0.25 0.25 ns, Max An - Dn LUT address to BMUX_A 0.35 0.40 0.40 ns, Max TITO An - Dn inputs to A - D Q outputs 0.77 0.90 0.90 ns, Max TAXA AX inputs to AMUX output 0.44 0.53 0.53 ns, Max TAXB AX inputs to BMUX output 0.52 0.61 0.61 ns, Max TAXC AX inputs to CMUX output 0.36 0.42 0.42 ns, Max TAXD AX inputs to DMUX output 0.62 0.73 0.73 ns, Max TBXB BX inputs to BMUX output 0.41 0.48 0.48 ns, Max Combinatorial Delays TILO DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 40 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 65: CLB Switching Characteristics (Cont'd) Symbol Speed Grade Description -2I -1I -1M Units TBXD BX inputs to DMUX output 0.51 0.59 0.59 ns, Max TCXB CX inputs to CMUX output 0.36 0.42 0.42 ns, Max TCXD CX inputs to DMUX output 0.42 0.49 0.49 ns, Max TDXD DX inputs to DMUX output 0.42 0.49 0.49 ns, Max TOPCYA An input to COUT output 0.50 0.59 0.59 ns, Max TOPCYB Bn input to COUT output 0.44 0.51 0.51 ns, Max TOPCYC Cn input to COUT output 0.37 0.43 0.43 ns, Max TOPCYD Dn input to COUT output 0.34 0.40 0.40 ns, Max TAXCY AX input to COUT output 0.42 0.50 0.50 ns, Max TBXCY BX input to COUT output 0.30 0.37 0.37 ns, Max TCXCY CX input to COUT output 0.22 0.26 0.26 ns, Max TDXCY DX input to COUT output 0.22 0.26 0.26 ns, Max TBYP CIN input to COUT output 0.10 0.11 0.11 ns, Max TCINA CIN input to AMUX output 0.27 0.31 0.31 ns, Max TCINB CIN input to BMUX output 0.30 0.35 0.35 ns, Max TCINC CIN input to CMUX output 0.32 0.36 0.36 ns, Max TCIND CIN input to DMUX output 0.35 0.41 0.41 ns, Max Clock to AQ - DQ outputs 0.40 0.47 0.47 ns, Max Sequential Delays TCKO Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK TDICK/TCKDI AX - DX input to CLK on A - D Flip Flops 0.41 0.21 0.49 0.24 0.49 0.31 ns, Min TRCK DX input to CLK when used as REV 0.42 0.51 0.51 ns, Min TCECK/TCKCE CE input to CLK on A - D Flip Flops 0.20 -0.04 0.23 -0.04 0.23 -0.03 ns, Min TSRCK/TCKSR SR input to CLK on A - D Flip Flops 0.49 -0.19 0.59 -0.19 0.59 -0.19 ns, Min TCINCK/TCKCIN CIN input to CLK on A - D Flip Flops 0.16 0.16 0.18 0.19 0.18 0.26 ns, Min TSRMIN SR input minimum pulse width 0.90 0.90 0.90 ns, Min TRQ Delay from SR or REV input to AQ - DQ flip-flops 0.86 1.03 1.03 ns, Max TCEO Delay from CE input to AQ - DQ flip-flops 0.52 0.63 0.63 ns, Max FTOG Toggle frequency (for export control) 1265 1098 1098 MHz Set/Reset Notes: 1. 2. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. These items are of interest for Carry Chain applications. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 41 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics CLB Distributed RAM Switching Characteristics (SLICEM Only) Table 66: CLB Distributed RAM Switching Characteristics Symbol Speed Grade Description -2I -1I -1M Units Sequential Delays TSHCKO Clock to A - B outputs 1.26 1.54 1.54 ns, Max TSHCKO_1 Clock to AMUX - BMUX outputs 1.38 1.68 1.68 ns, Max Setup and Hold Times Before/After Clock CLK TDS/TDH A - D inputs to CLK 0.84 0.22 1.03 0.26 1.03 0.26 ns, Min TAS/TAH Address An inputs to clock 0.46 0.22 0.54 0.27 0.54 0.27 ns, Min TWS/TWH WE input to clock 0.39 -0.04 0.46 -0.02 0.46 -0.02 ns, Min TCECK/TCKCE CE input to CLK 0.42 -0.07 0.51 -0.06 0.51 -0.06 ns, Min TMPW Minimum pulse width 0.82 1.00 1.00 ns, Min TMCP Minimum clock period 1.64 2.00 2.00 ns, Min Clock CLK Notes: 1. 2. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. TSHCKO also represents the CLK to XMUX output. Refer to TRACE report for the CLK to XMUX path. CLB Shift Register Switching Characteristics (SLICEM Only) Table 67: CLB Shift Register Switching Characteristics Symbol Speed Grade Description -2I -1I -1M Units Sequential Delays TREG Clock to A - D outputs 1.43 1.73 1.73 ns, Max TREG_MUX Clock to AMUX - DMUX output 1.55 1.87 1.87 ns, Max TREG_M31 Clock to DMUX output via M31 output 1.15 1.38 1.38 ns, Max Setup and Hold Times Before/After Clock CLK TWS/TWH WE input 0.24 -0.04 0.29 -0.02 0.29 -0.02 ns, Min TCECK/TCKCE CE input to CLK 0.27 -0.07 0.33 -0.06 0.33 -0.06 ns, Min TDS/TDH A - D inputs to CLK 0.66 0.09 0.78 0.11 0.78 0.11 ns, Min Minimum pulse width 0.70 0.85 0.85 ns, Min Clock CLK TMPW Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 42 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Block RAM and FIFO Switching Characteristics Table 68: Block RAM and FIFO Switching Characteristics Symbol Speed Grade Description -2I -1I -1M Units Block RAM and FIFO Clock to Out Delays TRCKO_DO and TRCKO_DOR(1) Clock CLK to DOUT output (without output register)(2)(3) 1.92 2.19 2.19 ns, Max register)(4)(5) 0.69 0.82 0.82 ns, Max Clock CLK to DOUT output with ECC (without output register)(2)(3) 3.03 3.61 3.61 ns, Max Clock CLK to DOUT output with ECC (with output register)(4)(5) 0.77 0.93 0.93 ns, Max Clock CLK to DOUT output with Cascade (without output register)(2) 2.44 2.94 2.94 ns, Max Clock CLK to DOUT output with Cascade (with output register)(4) 1.07 1.30 1.30 ns, Max Clock CLK to FIFO flags outputs(6) 0.87 1.02 1.02 ns, Max 1.26 1.48 1.48 ns, Max Clock CLK to DOUT output (with output TRCKO_FLAGS outputs(7) TRCKO_POINTERS Clock CLK to FIFO pointer TRCKO_ECCR Clock CLK to BITERR (with output register) 0.77 0.93 0.93 ns, Max TRCKO_ECC Clock CLK to BITERR (without output register) 2.85 3.41 3.41 ns, Max Clock CLK to ECCPARITY in standard ECC mode 1.47 1.74 1.74 ns, Max Clock CLK to ECCPARITY in ECC encode only mode 0.89 1.05 1.05 ns, Max Setup and Hold Times Before/After Clock CLK TRCCK_ADDR/TRCKC_ADDR ADDR inputs(8) 0.40 0.32 0.48 0.36 0.48 0.36 ns, Min TRDCK_DI/TRCKD_DI DIN inputs(9) 0.30 0.28 0.35 0.29 0.35 0.29 ns, Min DIN inputs with ECC in standard mode(9) 0.37 0.33 0.42 0.36 0.42 0.47 ns, Min DIN inputs with ECC encode only(9) 0.72 0.33 0.77 0.36 0.77 0.47 ns, Min TRCCK_EN/TRCKC_EN Block RAM Enable (EN) input 0.36 0.15 0.42 0.15 0.42 0.15 ns, Min TRCCK_REGCE/TRCKC_REGCE CE input of output register 0.16 0.24 0.18 0.27 0.18 0.27 ns, Min TRCCK_SSR/TRCKC_SSR Synchronous Set/ Reset (SSR) input 0.21 0.25 0.26 0.28 0.26 0.28 ns, Min TRCCK_WE/TRCKC_WE Write Enable (WE) input 0.51 0.17 0.63 0.18 0.63 0.18 ns, Min TRCCK_WREN/TRCKC_WREN WREN/RDEN FIFO inputs(10) 0.41 0.34 0.48 0.40 0.48 0.40 ns, Min Reset RST to FIFO Flags/Pointers(11) 1.26 1.48 1.48 ns, Max TRDCK_DI_ECC/TRCKD_DI_ECC Reset Delays TRCO_FLAGS DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 43 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 68: Block RAM and FIFO Switching Characteristics (Cont'd) Symbol Description Speed Grade -2I -1I -1M Units Maximum Frequency FMAX Block RAM in all modes 500 450 450 MHz FMAX_CASCADE Block RAM in cascade configuration 450 400 400 MHz FMAX_FIFO FIFO in all modes 500 450 450 MHz FMAX_ECC Block RAM and FIFO in ECC configuration 375 325 325 MHz Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. TRACE will report all of these parameters as TRCKO_DO. TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters. These parameters also apply to synchronous FIFO with DO_REG = 0. TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1. TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR. TRCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT. The ADDR setup and hold must be met when EN is asserted even though WE is deasserted. Otherwise, block RAM data corruption is possible. TRCKO_DI includes both A and B inputs as well as the parity inputs of A and B. These parameters also apply to RDEN. TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT. DSP48E Switching Characteristics Table 69: DSP48E Switching Characteristics Symbol Description Speed Grade Units -2I -1I -1M 0.21 0.23 0.26 0.30 0.26 0.30 ns 0.16 0.31 0.20 0.37 0.20 0.50 ns 1.44 0.19 1.71 0.19 1.71 0.19 ns Setup and Hold Times of Data/Control Pins to the Input Register Clock TDSPDCK_{AA, BB, ACINA, BCINB}/ TDSPCKD_{AA, BB, ACINA, BCINB} {A, B, ACIN, BCIN} input to {A, B} register CLK TDSPDCK_CC/TDSPCKD_CC C input to C register CLK Setup and Hold Times of Data Pins to the Pipeline Register Clock TDSPDCK_{AM, BM, ACINM, BCINM}/ TDSPCKD_{AM, BM, ACINM, BCINM} {A, B, ACIN, BCIN} input to M register CLK Setup and Hold Times of Data/Control Pins to the Output Register Clock TDSPDCK_{AP, BP, ACINP, BCINP}_M/ TDSPCKD_{AP, BP, ACINP, BCINP}_M {A, B, ACIN, BCIN} input to P register CLK using multiplier 2.74 -0.30 3.25 -0.30 3.25 -0.30 ns TDSPDCK_{AP, BP, ACINP, BCINP}_NM/ TDSPCKD_{AP, BP, ACINP, BCINP}_NM {A, B, ACIN, BCIN} input to P register CLK not using multiplier 1.54 -0.10 1.83 -0.10 1.83 -0.10 ns TDSPDCK_CP/TDSPCKD_CP C input to P register CLK 1.42 -0.13 1.70 -0.13 1.70 -0.13 ns TDSPDCK_{PCINP, CRYCINP, MULTSIGNINP}/ TDSPCKD_{PCINP, CRYCINP, MULTSIGNINP} {PCIN, CARRYCASCIN, MULTSIGNIN} input to P register CLK 1.17 0.11 1.31 0.11 1.31 0.11 ns 0.28 0.25 0.33 0.31 0.33 0.31 ns Setup and Hold Times of the CE Pins {CEA1, CEA2A, CEB1B, CEB2B} input to TDSPCCK_{CEA1A, CEA2A, CEB1B, {A, B} register CLK CEB2B}/ TDSPCKC_{CEA1A, CEA2A, CEB1A, CEB2B} TDSPCCK_CECC/TDSPCKC_CECC CEC input to C register CLK 0.21 0.21 0.26 0.28 0.26 0.28 ns TDSPCCK_CEMM/TDSPCKC_CEMM CEM input to M register CLK 0.29 0.21 0.36 0.26 0.36 0.26 ns DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 44 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 69: DSP48E Switching Characteristics (Cont'd) Symbol Description Speed Grade Units -2I -1I -1M CEP input to P register CLK 0.63 0.01 0.73 0.01 0.73 0.01 ns TDSPCCK_{RSTAA, RSTBB}/ TDSPCKC_{RSTAA, RSTBB} {RSTA, RSTB} input to {A, B} register CLK 0.28 0.26 0.33 0.31 0.33 0.31 ns TDSPCCK_RSTCC/ TDSPCKC_RSTCC RSTC input to C register CLK 0.21 0.21 0.26 0.28 0.26 0.28 ns TDSPCCK_RSTMM/ TDSPCKC_RSTMM RSTM input to M register CLK 0.29 0.21 0.36 0.26 0.36 0.26 ns TDSPCCK_RSTPP/TDSPCKC_RSTPP RSTP input to P register CLK 0.63 0.01 0.73 0.01 0.73 0.01 ns 3.22 3.84 3.84 ns TDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_NM {A, B} input to {P, CARRYOUT} output not using multiplier 1.77 2.22 2.22 ns TDSPDO_{CP, CCRYOUT, CRYINP, CRYINCRYOUT} 1.67 2.08 2.08 ns TDSPCCK_CEPP/TDSPCKC_CEPP Setup and Hold Times of the RST Pins Combinatorial Delays from Input Pins to Output Pins TDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_M {A, B} input to {P, CARRYOUT} output using multiplier {C, CARRYIN} input to {P, CARRYOUT} output Combinatorial Delays from Input Pins to Cascading Output Pins TDSPDO_{AACOUT, BBCOUT} {A, B} input to {ACOUT, BCOUT} output 1.12 1.31 1.31 ns TDSPDO_{APCOUT, ACRYCOUT, AMULTSIGNOUT, BPCOUT, BCRYCOUT, BMULTSIGNOUT}_M {A, B} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output using multiplier 3.22 3.84 3.84 ns TDSPDO_{APCOUT, ACRYCOUT, AMULTSIGNOUT, BPCOUT, BCRYCOUT, BMULTSIGNOUT}_NM {A, B} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output not using multiplier 1.92 2.42 2.42 ns TDSPDO_{CPCOUT, CCRYCOUT, CMULTSIGNOUT, CRYINPCOUT, CRYINCRYCOUT, CRYINMULTSIGNOUT} {C, CARRYIN} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output 1.82 2.28 2.28 ns Combinatorial Delays from Cascading Input Pins to All Output Pins TDSPDO_{ACINP, ACINCRYOUT, BCINP, BCINCRYOUT}_M {ACIN, BCIN} input to {P, CARRYOUT} output using multiplier 3.22 3.84 3.84 ns TDSPDO_{ACINP, ACINCRYOUT, BCINP, BCINCRYOUT}_NM {ACIN, BCIN} input to {P, CARRYOUT} output not using multiplier 1.77 2.22 2.22 ns TDSPDO_{ACINACOUT, BCINBCOUT} {ACIN, BCIN} input to {ACOUT, BCOUT} output 1.12 1.31 1.31 ns TDSPDO_{ACINPCOUT, ACINCRYCOUT, ACINMULTSIGNOUT, BCINPCOUT, BCINCRYCOUT, BCINMULTSIGNOUT}_M {ACIN, BCIN} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output using multiplier 3.22 3.84 3.84 ns TDSPDO_{ACINPCOUT, ACINCRYCOUT, ACINMULTSIGNOUT, BCINPCOUT, BCINCRYCOUT, BCINMULTSIGNOUT}_NM {ACIN, BCIN} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output not using multiplier 1.92 2.42 2.42 ns TDSPDO_{PCINP, CRYCINP, MULTSIGNINP, PCINCRYOUT, CRYCINCRYOUT, MULTSIGNINCRYOUT} {PCIN, CARRYCASCIN, MULTSIGNIN} input to {P, CARRYOUT} output 1.45 1.82 1.82 ns DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 45 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 69: DSP48E Switching Characteristics (Cont'd) Symbol Description TDSPDO_{PCINPCOUT, CRYCINPCOUT, MULTSIGNINPCOUT, PCINCRYCOUT, CRYCINCRYCOUT, MULTSIGNINCRYCOUT, PCINMULTSIGNOUT, CRYCINMULTSIGNOUT, MULTSIGNINMULTSIGNOUT} {PCIN, CARRYCASCIN, MULTSIGNIN} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output Speed Grade Units -2I -1I -1M 1.60 2.02 2.02 ns Clock to Outs from Output Register Clock to Output Pins TDSPCKO_{PP, CRYOUTP} CLK (PREG) to {P, CARRYOUT} output 0.48 0.56 0.56 ns TDSPCKO_{CRYCOUTP, PCOUTP, MULTSIGNOUTP} CLK (PREG) to {CARRYCASCOUT, PCOUT, MULTSIGNOUT} output 0.53 0.62 0.62 ns Clock to Outs from Pipeline Register Clock to Output Pins TDSPCKO_{PM, CRYOUTM} CLK (MREG) to {P, CARRYOUT} output 2.10 2.47 2.47 ns TDSPCKO_{PCOUTM, CRYCOUTM, MULTSIGNOUTM} CLK (MREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output 2.13 2.66 2.66 ns Clock to Outs from Input Register Clock to Output Pins TDSPCKO_{PA, CRYOUTA, PB, CRYOUTB}_M CLK (AREG, BREG) to {P, CARRYOUT} output using multiplier 3.57 4.23 4.23 ns TDSPCKO_{PA, CRYOUTA, PB, CRYOUTB}_NM CLK (AREG, BREG) to {P, CARRYOUT} output not using multiplier 2.11 2.63 2.63 ns TDSPCKO_{PC, CRYOUTC} CLK (CREG) to {P, CARRYOUT} output 2.11 2.62 2.62 ns Clock to Outs from Input Register Clock to Cascading Output Pins TDSPCKO_{ACOUTA, BCOUTB} CLK (AREG, BREG) to {ACOUT, BCOUT} 0.68 0.79 0.79 ns TDSPCKO_{PCOUTA, CRYCOUTA, MULTSIGNOUTA, PCOUTB, CRYCOUTB, MULTSIGNOUTB}_M CLK (AREG, BREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output using multiplier 3.57 4.23 4.23 ns TDSPCKO_{PCOUTA, CRYCOUTA, MULTSIGNOUTA, PCOUTB, CRYCOUTB, MULTSIGNOUTB}_NM CLK (AREG, BREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output not using multiplier 2.27 2.82 2.82 ns TDSPCKO_{PCOUTC, CRYCOUTC, MULTSIGNOUTC} CLK (CREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output 2.26 2.82 2.82 ns FMAX With all registers used 500 450 450 MHz FMAX_PATDET With pattern detector 465 410 410 MHz FMAX_MULT_NOMREG Two register multiply without MREG 324 275 275 MHz FMAX_MULT_NOMREG_PATDET Two register multiply without MREG with pattern detect 300 254 254 MHz Maximum Frequency DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 46 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Configuration Switching Characteristics Table 70: Configuration Switching Characteristics Symbol Description Speed Grade -2I -1I -1M Units Power-up Timing Characteristics TPL Program Latency 3 3 3 ms, Max TPOR Power-on-Reset 10 50 10 50 10 50 ms, Min/Max TICCK CCLK (output) delay 400 400 400 ns, Min TPROGRAM Program Pulse Width 250 250 250 ns, Min Master/Slave Serial Mode Programming Switching(1) TDCCK/TCCKD DIN Setup/Hold, slave mode 4.0 0.0 4.0 0.0 5.0 0.0 ns, Min TDSCCK/TSCCKD DIN Setup/Hold, master mode 4.0 0.0 4.0 0.0 5.0 0.0 ns, Min TCCO DOUT 7.5 7.5 7.5 ns, Max FMCCK Maximum Frequency, master mode with respect to nominal CCLK. 100 100 100 MHz, Max FMCCKTOL Frequency Tolerance, master mode with respect to nominal CCLK. 50 50 50 % FMSCCK Slave mode external CCLK 100 100 100 MHz SelectMAP Mode Programming Switching(1) TSMDCCK/TSMCCKD SelectMAP Data Setup/Hold 3.0 0.5 3.0 0.5 3.0 0.5 ns, Min TSMCSCCK/TSMCCKCS CS_B Setup/Hold 3.0 0.5 3.0 0.5 3.0 0.5 ns, Min TSMCCKW/TSMWCCK RDWR_B Setup/Hold 8.0 0.5 8.0 0.5 8.0 0.5 ns, Min TSMCKCSO CSO_B clock to out (330 pull-up resistor required) 10 10 10 ns, Min TSMCO CCLK to DATA out in readback 9.0 9.0 9.0 ns, Max TSMCKBY CCLK to BUSY out in readback 7.5 7.5 7.5 ns, Max FSMCCK Maximum Frequency with respect to nominal CCLK 100 100 100 MHz, Max FRBCCK Maximum Readback Frequency with respect to nominal CCLK 60 60 60 MHz, Max FMCCKTOL Frequency Tolerance with respect to nominal CCLK 50 50 50 % Boundary-Scan Port Timing Specifications TTAPTCK TMS and TDI Setup time before TCK 1.0 1.0 1.0 ns, Min TTCKTAP TMS and TDI Hold time after TCK 2.0 2.0 2.0 ns, Min TTCKTDO TCK falling edge to TDO output valid 6 6 6 ns, Max FTCK Maximum configuration TCK clock frequency 66 66 66 MHz, Max FTCKB Maximum boundary-scan TCK clock frequency 66 66 66 MHz, Max DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 47 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 70: Configuration Switching Characteristics (Cont'd) Symbol Description Speed Grade Units -2I -1I -1M 10 10 10 ns BPI Master Flash Mode Programming Switching TBPICCO(4) ADDR[25:0], RS[1:0], FCS_B, FOE_B, FWE_B outputs valid after CCLK rising edge TBPIDCC/TBPICCD Setup/Hold on D[15:0] data input pins 3.0 0.5 3.0 0.5 3.0 0.5 ns TINITADDR Minimum period of initial ADDR[25:0] address cycles 3.0 3.0 3.0 CCLK cycles SPI Master Flash Mode Programming Switching TSPIDCC/TSPIDCCD DIN Setup/Hold before/after the rising CCLK edge 4.0 0.0 4.0 0.0 5.0 0.0 ns TSPICCM MOSI clock to out 10 10 10 ns TSPICCFC FCS_B clock to out 10 10 10 ns TFSINIT/TFSINITH FS[2:0] to INIT_B rising edge Setup and Hold 2 2 2 s CCLK Output (Master Modes) TMCCKL Master CCLK clock minimum Low time 3.0 3.0 3.0 ns, Min TMCCKH Master CCLK clock minimum High time 3.0 3.0 3.0 ns, Min TSCCKL Slave CCLK clock minimum Low time 2.0 2.0 2.0 ns, Min TSCCKH Slave CCLK clock minimum High time 2.0 2.0 2.0 ns, Min CCLK Input (Slave Modes) Dynamic Reconfiguration Port (DRP) for DCM and PLL Before and After DCLK FDCK Maximum frequency for DCLK 450 400 400 MHz TDMCCK_DADDR/TDMCKC_DADDR DADDR Setup/Hold 1.35 0.0 1.56 0.0 1.56 0.0 ns TDMCCK_DI/TDMCKC_DI DI Setup/Hold 1.35 0.0 1.56 0.0 1.56 0.0 ns TDMCCK_DEN/TDMCKC_DEN DEN Setup/Hold time 1.35 0.0 1.56 0.0 1.56 0.0 ns TDMCCK_DWE/TDMCKC_DWE DWE Setup/Hold time 1.35 0.0 1.56 0.0 1.56 0.0 ns TDMCKO_DO CLK to out of DO(3) 1.12 1.30 1.30 ns TDMCKO_DRDY CLK to out of DRDY 1.12 1.30 1.30 ns Notes: 1. 2. 3. 4. Maximum frequency and setup/hold timing parameters are for 3.3V and 2.5V configuration voltages. To support longer delays in configuration, use the design solutions described in the Virtex-5 FPGA User Guide. DO will hold until next DRP operation. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 48 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Clock Buffers and Networks Table 71: Global Clock Switching Characteristics (Including BUFGCTRL) Symbol Description Devices Speed Grade -2I -1I -1M Units TBCCCK_CE/TBCCKC_CE(1) CE pins Setup/Hold All 0.27 0.00 0.31 0.00 0.31 0.00 ns TBCCCK_S/TBCCKC_S(1) S pins Setup/Hold All 0.27 0.00 0.31 0.00 0.31 0.00 ns LX30T, LX85, LX110, LX110T, SX50T, FX70T, FX100T, and FX130T 0.22 0.25 0.25 ns LX155T 0.14 0.30 N/A ns LX220T, LX330T, SX95T, SX240T, and FX200T 0.22 0.25 N/A ns LX30T, LX85, LX110, LX110T, SX50T, and FX70T(I) 667 600 N/A MHz LX155T, FX70T(M), and FX100T 600 550 550 MHz FX130T 500 450 N/A MHz LX220T, LX330T, SX95T, SX240T, and FX200T 500 450 N/A MHz TBCCKO_O(2) BUFGCTRL delay from I0/I1 to O Maximum Frequency FMAX Global clock tree (BUFG) Notes: 1. 2. TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks. TBGCKO_O (BUFG delay from I0 to O) values are the same as TBCCKO_O values. Table 72: Input/Output Clock Switching Characteristics (BUFIO) Symbol TBUFIOCKO_O Description Speed Grade Units -2I -1I -1M Clock to out delay from I to O 1.16 1.29 1.29 ns I/O clock tree (BUFIO) 710 644 644 MHz Maximum Frequency FMAX DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 49 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 73: Regional Clock Switching Characteristics (BUFR) Symbol TBRCKO_O TBRCKO_O_BYP TBRDO_CLRO Description Clock to out delay from I to O Clock to out delay from I to O with Divide Bypass attribute set Devices Speed Grade Units -2I -1I -1M LX30T, LX85, LX110, LX110T, SX50T, FX100T, and FX130T 0.59 0.67 0.67 ns FX70T 0.74 0.83 0.83 ns LX155T 0.80 0.90 N/A ns LX220T, LX330T, SX95T, SX240T, and FX200T 0.59 0.67 N/A ns LX30T, LX85, LX110, LX110T, SX50T, FX70T, FX100T, and FX130T 0.24 0.26 0.26 ns LX155T 0.26 0.30 N/A ns LX220T, LX330T, SX95T, SX240T, and FX200T 0.24 0.26 N/A ns 0.70 0.82 0.82 ns 250 250 250 MHz Propagation delay from CLR to O All Maximum Frequency FMAX Regional clock tree (BUFR) DS714 (v2.2) January 17, 2011 Product Specification All www.xilinx.com 50 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics PLL Switching Characteristics Table 74: PLL Specification Symbol Description Speed Grade -2I -1I -1M Units FINMAX Maximum Input Clock Frequency 710 645 645 MHz FINMIN Minimum Input Clock Frequency 19 19 19 MHz FINJITTER Maximum Input Clock Period Jitter FINDUTY Allowable Input Duty Cycle: 19--49 MHz 25/75 % Allowable Input Duty Cycle: 50--199 MHz 30/70 % Allowable Input Duty Cycle: 200--399 MHz 35/65 % Allowable Input Duty Cycle: 400--499 MHz 40/60 % Allowable Input Duty Cycle: >500 MHz 45/55 % <20% of clock input period or 1 ns Max FVCOMIN Minimum PLL VCO Frequency 400 400 400 MHz FVCOMAX Maximum PLL VCO Frequency FBANDWIDTH TSTAPHAOFFSET TOUTJITTER TOUTDUTY 1200 1000 1000 MHz Low PLL Bandwidth at Typical(1) 1 1 1 MHz High PLL Bandwidth at Typical(1) 4 4 4 MHz 120 120 120 ps Static Phase Offset of the PLL Outputs PLL Output Jitter(2) Note 1 PLL Output Clock Duty Cycle Precision(3) Time(4) 200 200 200 ps 100 100 100 s TLOCKMAX PLL Maximum Lock FOUTMAX PLL Maximum Output Frequency for LX30T, LX85, LX110, LX110T, SX50T, and FX70T(I) devices 667 600 N/A MHz PLL Maximum Output Frequency for LX155T, FX70T(M), and FX100T devices 600 550 550 MHz PLL Maximum Output Frequency for FX130T devices 500 450 N/A MHz PLL Maximum Output Frequency for LX220T, LX330T, SX95T, SX240T, and FX200T devices 500 450 N/A MHz 3.125 3.125 3.125 MHz FOUTMIN PLL Minimum Output Frequency(5) TEXTFDVAR External Clock Feedback Variation RSTMINPULSE Minimum Reset Pulse Width FPFDMAX < 20% of clock input period or 1 ns Max 5 5 5 ns Maximum Frequency at the Phase Frequency Detector 500 450 450 MHz FPFDMIN Minimum Frequency at the Phase Frequency Detector 19 19 19 MHz TFBDELAY Maximum Delay in the Feedback Path 3 ns Max or one CLKIN cycle Notes: 1. 2. 3. 4. 5. The PLL does not filter typical spread spectrum input clocks because they are usually far below the bandwidth filter frequencies. Values for this parameter are available in the Architecture Wizard. Includes global clock buffer. The LOCK signal must be sampled after TLOCKMAX. The LOCK signal is invalid after configuration or reset until the TLOCKMAX time has expired. Calculated as FVCO/128 assuming output duty cycle is 50%. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 51 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 75: PLL in PMCD Mode Switching Characteristics Symbol Description Speed Grade -2I -1I -1M Units TPLLCCK_REL/TPLLCKC_REL REL Setup and Hold for all Outputs 0.00 0.60 0.00 0.60 0.00 0.60 ns TPLLCCKO Maximum Clock Propagation Delay 4.6 5.2 5.2 ns CLKIN_FREQ_MAX Maximum Input Frequency 710 645 645 MHz CLKIN_FREQ_MIN Minimum Input Frequency 1 1 1 MHz CLKIN_DUTY_CYCLE Allowable Input Duty Cycle: 1--49 MHz 25/75 % Allowable Input Duty Cycle: 50--199 MHz 30/70 % Allowable Input Duty Cycle: 200--399 MHz 35/65 % Allowable Input Duty Cycle: 400--499 MHz 40/60 % Allowable Input Duty Cycle: >500 MHz 45/55 % RES_REL_PULSE_MIN DS714 (v2.2) January 17, 2011 Product Specification Minimum Pulse Width for RST and REL 5 5 5 ns www.xilinx.com 52 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics DCM Switching Characteristics Table 76: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode Symbol Description Speed Grade Units -2I -1I -1M 32.00 32.00 32.00 MHz 135.00 120.00 120.00 MHz 64.00 64.00 64.00 MHz 270.00 240.00 240.00 MHz 2.0 2.0 2.0 MHz 90.00 80.00 80.00 MHz 32.00 32.00 32.00 MHz 160.00 140.00 140.00 MHz 32.00 32.00 32.00 MHz 135.00 120.00 120.00 MHz 1.00 1.00 1.00 MHz 160.00 140.00 140.00 MHz 1.00 1.00 1.00 KHz 500.00 450.00 450.00 MHz 120.00 120.00 120.00 MHz 500.00 450.00 450.00 MHz 240.00 240.00 240.00 MHz 500.00 450.00 450.00 MHz 7.5 7.5 7.5 MHz 333.34 300.00 300.00 MHz 140.00 140.00 140.00 MHz 375.00 350.00 350.00 MHz 120.00 120.00 120.00 MHz 500.00 450.00 450.00 MHz 25.00 25.00 25.00 MHz 375.00 350.00 350.00 MHz 1.00 1.00 1.00 KHz 500.00 450.00 450.00 MHz Outputs Clocks (Low Frequency Mode) F1XLFMSMIN CLK0, CLK90, CLK180, CLK270 F1XLFMSMAX F2XLFMSMIN CLK2X, CLK2X180 F2XLFMSMAX FDVLFMSMIN CLKDV(5) FDVLFMSMAX FFXLFMSMIN CLKFX, CLKFX180 FFXLFMSMAX Input Clocks (Low Frequency Mode) FDLLLFMSMIN CLKIN (using DLL outputs)(1)(3)(4) FDLLLFMSMAX FCLKINLFFXMSMIN CLKIN (using DFS outputs only)(2)(3)(4) FCLKINLFFXMSMAX FPSCLKLFMSMIN PSCLK FPSCLKLFMSMAX Outputs Clocks (High Frequency Mode) F1XHFMSMIN CLK0, CLK90, CLK180, CLK270 F1XHFMSMAX F2XHFMSMIN CLK2X, CLK2X180 F2XHFMSMAX FDVHFMSMIN CLKDV(5) FDVHFMSMAX FFXHFMSMIN CLKFX, CLKFX180(5) FFXHFMSMAX Input Clocks (High Frequency Mode) FDLLHFMSMIN CLKIN (using DLL outputs)(1)(3)(4) FDLLHFMSMAX FCLKINHFFXMSMIN CLKIN (using DFS outputs only)(2)(3)(4)(5) FCLKINHFFXMSMAX FPSCLKHFMSMIN PSCLK FPSCLKHFMSMAX Notes: 1. 2. 3. 4. 5. DLL outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. DFS outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. Other resources can limit the maximum input frequency. When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within 5% (45/55 to 55/45). Only available for I-temperature conditions. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 53 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 77: Operating Frequency Ranges for DCM in Maximum Range (MR) Mode(5) Symbol Description Speed Grade Units -2I -1I -1M 19.00 19.00 19.00 MHz 32.00 32.00 32.00 MHz 38.00 38.00 38.00 MHz 64.00 64.00 64.00 MHz 1.19 1.19 1.19 MHz 21.34 21.34 21.34 MHz 19.00 19.00 19.00 MHz 40.00 40.00 40.00 MHz 19.00 19.00 19.00 MHz 32.00 32.00 32.00 MHz 1.00 1.00 1.00 MHz 40.00 40.00 40.00 MHz 1.00 1.00 1.00 KHz 270.00 240.00 240.00 MHz Outputs Clocks (Low Frequency Mode) F1XMRMIN F1XMRMAX F2XMRMIN F2XMRMAX FDLLMRMIN FDLLMRMAX FFXMRMIN FFXMRMAX CLK0, CLK90, CLK180, CLK270 CLK2X, CLK2X180 CLKDV CLKFX, CLKFX180 Input Clocks (Low Frequency Mode) FCLKINDLLMRMIN FCLKINDLLMRMAX FCLKINFXMRMIN FCLKINFXMRMAX FPSCLKMRMIN FPSCLKMRMAX CLKIN (using DLL outputs)(1)(3)(4) CLKIN (using DFS outputs only)(2)(3)(4) PSCLK Notes: 1. 2. 3. 4. 5. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. Other resources can limit the maximum input frequency. When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within 5% (45/55 to 55/45). Maximum range is not available outside of I-temperature conditions. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 54 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 78: Input Clock Tolerances Symbol Description Frequency Range Value Units < 1 MHz 25 - 75 % 1 - 50 MHz 25 - 75 % 50 - 100 MHz 30 - 70 % 100 - 200 MHz 40 - 60 % 45 - 55 % 45 - 55 % Duty Cycle Input Tolerance (in %) TDUTYCYCRANGE_1 PSCLK only TDUTYCYCRANGE_1_50 TDUTYCYCRANGE_50_100 TDUTYCYCRANGE_100_200 PSCLK and CLKIN TDUTYCYCRANGE_200_400 200 - 400 TDUTYCYCRANGE_400 > 400 MHz Speed Grade Input Clock Cycle-Cycle Jitter (Low Frequency Mode) TCYCLFDLL TCYCLFFX MHz(4) Units -2I -1I -1M CLKIN (using DLL outputs)(1) 300.00 345.00 345.00 ps outputs)(2) 300.00 345.00 345.00 ps CLKIN (using DLL outputs)(1) 150.00 173.00 173.00 ps outputs)(2) 150.00 173.00 173.00 ps CLKIN (using DFS Input Clock Cycle-Cycle Jitter (High Frequency Mode) TCYCHFDLL TCYCHFFX CLKIN (using DFS Input Clock Period Jitter (Low Frequency Mode) TPERLFDLL CLKIN (using DLL outputs)(1) 1.00 1.15 1.15 ns TPERLFFX CLKIN (using DFS outputs)(2) 1.00 1.15 1.15 ns Input Clock Period Jitter (High Frequency Mode) TPERHFDLL CLKIN (using DLL outputs)(1) 1.00 1.15 1.15 ns TPERHFFX CLKIN (using DFS outputs)(2) 1.00 1.15 1.15 ns CLKFB off-chip feedback 1.00 1.15 1.15 ns Feedback Clock Path Delay Variation TCLKFB_DELAY_VAR Notes: 1. 2. 3. 4. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. If both DLL and DFS outputs are used, follow the more restrictive specifications. This duty cycle specification does not apply to the GTP_DUAL to DCM or GTX_DUAL to DCM connection. The GTP transceivers drive the DCMs at the following frequencies: 320 MHz for -1I speed grade devices, or 375 MHz for -2I speed grade devices. The GTX transceivers drive the DCMs at the following frequencies: 450 MHz for -1I speed grade devices or 500 MHz for -2I speed grade devices. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 55 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Output Clock Jitter Table 79: Output Clock Jitter Symbol Description Speed Grade -2I -1I -1M Units Clock Synthesis Period Jitter TPERJITT_0 CLK0 120 120 120 ps TPERJITT_90 CLK90 120 120 120 ps TPERJITT_180 CLK180 120 120 120 ps TPERJITT_270 CLK270 120 120 120 ps TPERJITT_2X CLK2X, CLK2X180 200 230 230 ps TPERJITT_DV1 CLKDV (integer division) 150 180 180 ps TPERJITT_DV2 CLKDV (non-integer division) 300 345 345 ps TPERJITT_FX CLKFX, CLKFX180 Note 1 Note 1 Note 1 ps Notes: 1. Values for this parameter are available in the Architecture Wizard. Output Clock Phase Alignment Table 80: Output Clock Phase Alignment Symbol Description Speed Grade Units -2I -1I -1M 50 60 60 ps Phase Offset Between CLKIN and CLKFB TIN_FB_OFFSET CLKIN/CLKFB Phase Offset Between Any DCM Outputs(1) TOUT_OFFSET_1X CLK0, CLK90, CLK180, CLK270 140 160 160 ps TOUT_OFFSET_2X CLK2X, CLK2X180, CLKDV 150 200 200 ps TOUT_OFFSET_FX CLKFX, CLKFX180 160 220 220 ps DLL outputs(3) 150 180 180 ps outputs(4) 150 180 180 ps Duty Cycle Precision(2) TDUTY_CYC_DLL TDUTY_CYC_FX DFS Notes: 1. 2. 3. 4. All phase offsets are with respect to group CLK1X. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if DUTY_CYCLE_CORRECTION = TRUE. The duty cycle distortion includes the global clock tree (BUFG). DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 56 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 81: Miscellaneous Timing Parameters Symbol Speed Grade Description Units -2I -1I -1M 80.00 80.00 80.00 s 250.00 250.00 250.00 s Time Required to Achieve LOCK DLL output - Frequency range > 240 MHz(1) TDLL_240 TDLL_120_240 DLL output - Frequency range 120 - 240 TDLL_60_120 DLL output - Frequency range 60 - 120 MHz(1) MHz(1) 900.00 900.00 900.00 s DLL output - Frequency range 50 - 60 MHz(1) 1300.00 1300.00 1300.00 s DLL output - Frequency range 40 - 50 MHz(1) 2000.00 2000.00 2000.00 s DLL output - Frequency range 30 - 40 MHz(1) 3600.00 3600.00 3600.00 s DLL output - Frequency range 24 - 30 MHz(1) 5000.00 5000.00 5000.00 s 5000.00 5000.00 5000.00 s 10.00 10.00 10.00 ms 10.00 10.00 10.00 ms Multiplication factor for DLL lock time with Fine Shift 2.00 2.00 2.00 Absolute shifting range in maximum speed mode 7.00 7.00 7.00 ns Absolute shifting range in maximum range mode 10.00 10.00 10.00 ns TTAP_MS_MIN Tap delay resolution (Min) in maximum speed mode 7.00 7.00 7.00 ps TTAP_MS_MAX Tap delay resolution (Max) in maximum speed mode 30.00 30.00 30.00 ps TTAP_MR_MIN(3) Tap delay resolution (Min) in maximum range mode 10.00 10.00 10.00 ps TTAP_MR_MAX(3) Tap delay resolution (Max) in maximum range mode 40.00 40.00 40.00 ps TDLL_50_60 TDLL_40_50 TDLL_30_40 TDLL_24_30 TDLL_30 DLL output - Frequency range < 30 TFX_MIN MHz(1) DFS outputs(2) TFX_MAX TDLL_FINE_SHIFT Fine Phase Shifting TRANGE_MS TRANGE_MR (3) Delay Lines Notes: 1. 2. 3. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. Maximum range is not available outside of I-temperature conditions. Table 82: Frequency Synthesis Attribute Min Max CLKFX_MULTIPLY 2 33 CLKFX_DIVIDE 1 32 Table 83: DCM Switching Characteristics Symbol Description Speed Grade -2I -1I -1M Units TDMCCK_PSEN/ TDMCKC_PSEN PSEN Setup/Hold 1.35 0.00 1.56 0.00 1.56 0.00 ns TDMCCK_PSINCDEC/ TDMCKC_PSINCDEC PSINCDEC Setup/Hold 1.35 0.00 1.56 0.00 1.56 0.00 ns TDMCKO_PSDONE Clock to out of PSDONE 1.12 1.30 1.30 ns DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 57 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Virtex-5Q Device Pin-to-Pin Output Parameter Guidelines All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are listed in Table 84. Values are expressed in nanoseconds unless otherwise noted. Table 84: Global Clock Input to Output Delay Without DCM or PLL Symbol Description Device Speed Grade -2I -1I -1M Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without DCM or PLL TICKOF Global Clock and OUTFF without DCM or PLL XQ5VLX30T 6.04 6.73 N/A ns XQ5VLX85 6.28 6.99 N/A ns XQ5VLX110 6.35 7.06 N/A ns XQ5VLX110T 6.35 7.06 N/A ns XQ5VLX155T 6.68 7.52 N/A ns XQ5VLX220T 6.99 7.71 N/A ns XQ5VLX330T N/A 7.91 N/A ns XQ5VSX50T 6.27 6.97 N/A ns XQ5VSX95T 6.59 7.30 N/A ns XQ5VSX240T N/A 7.98 N/A ns XQ5VFX70T 6.33 7.04 7.04 ns XQ5VFX100T 6.73 7.44 7.44 ns XQ5VFX130T 6.80 7.52 N/A ns XQ5VFX200T N/A 7.91 N/A ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 58 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 85: Global Clock Input to Output Delay With DCM in System-Synchronous Mode Symbol Description Device Speed Grade -2I -1I -1M Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in System-Synchronous Mode TICKOFDCM Global Clock and OUTFF with DCM XQ5VLX30T 2.56 2.93 N/A ns XQ5VLX85 2.63 3.00 N/A ns XQ5VLX110 2.69 3.06 N/A ns XQ5VLX110T 2.69 3.06 N/A ns XQ5VLX155T 2.74 3.10 N/A ns XQ5VLX220T 2.83 3.18 N/A ns XQ5VLX330T N/A 3.37 N/A ns XQ5VSX50T 2.69 3.05 N/A ns XQ5VSX95T 2.64 3.00 N/A ns XQ5VSX240T N/A 3.36 N/A ns XQ5VFX70T 2.74 3.12 3.12 ns XQ5VFX100T 2.59 3.00 3.00 ns XQ5VFX130T 2.67 3.07 N/A ns XQ5VFX200T N/A 3.27 N/A ns Notes: 1. 2. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. DCM output jitter is already included in the timing calculation. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 59 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 86: Global Clock Input to Output Delay With DCM in Source-Synchronous Mode Symbol Description Device Speed Grade -2I -1I -1M Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in Source-Synchronous Mode TICKOFDCM_0 Global Clock and OUTFF with DCM XQ5VLX30T 3.71 4.15 N/A ns XQ5VLX85 3.86 4.29 N/A ns XQ5VLX110 3.92 4.36 N/A ns XQ5VLX110T 3.92 4.36 N/A ns XQ5VLX155T 4.18 4.62 N/A ns XQ5VLX220T 4.41 4.85 N/A ns XQ5VLX330T N/A 5.04 N/A ns XQ5VSX50T 3.91 4.35 N/A ns XQ5VSX95T 4.16 4.59 N/A ns XQ5VSX240T N/A 5.11 N/A ns XQ5VFX70T 3.96 4.41 4.41 ns XQ5VFX100T 4.10 4.53 4.53 ns XQ5VFX130T 4.29 4.74 N/A ns XQ5VFX200T N/A 5.03 N/A ns Notes: 1. 2. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. DCM output jitter is already included in the timing calculation. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 60 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 87: Global Clock Input to Output Delay With PLL in System-Synchronous Mode Symbol Description Device Speed Grade -2I -1I -1M Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL in System-Synchronous Mode TICKOFPLL Global Clock and OUTFF with PLL XQ5VLX30T 2.30 2.70 N/A ns XQ5VLX85 2.49 2.88 N/A ns XQ5VLX110 2.53 2.92 N/A ns XQ5VLX110T 2.53 2.92 N/A ns XQ5VLX155T 2.60 3.01 N/A ns XQ5VLX220T 2.74 3.12 N/A ns XQ5VLX330T N/A 3.27 N/A ns XQ5VSX50T 2.36 2.76 N/A ns XQ5VSX95T 2.29 2.69 N/A ns XQ5VSX240T N/A 3.34 N/A ns XQ5VFX70T 2.71 3.10 3.10 ns XQ5VFX100T 2.70 3.10 3.10 ns XQ5VFX130T 2.75 3.17 N/A ns XQ5VFX200T N/A 3.35 N/A ns Notes: 1. 2. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. PLL output jitter is included in the timing calculation. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 61 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 88: Global Clock Input to Output Delay With PLL in Source-Synchronous Mode Symbol Description Device Speed Grade -2I -1I -1M Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL in Source-Synchronous Mode TICKOFPLL_0 Global Clock and OUTFF with PLL XQ5VLX30T 4.32 4.82 N/A ns XQ5VLX85 4.40 4.88 N/A ns XQ5VLX110 4.44 4.92 N/A ns XQ5VLX110T 4.44 4.92 N/A ns XQ5VLX155T 4.66 5.16 N/A ns XQ5VLX220T 4.85 5.29 N/A ns XQ5VLX330T N/A 5.44 N/A ns XQ5VSX50T 4.54 5.02 N/A ns XQ5VSX95T 4.68 5.14 N/A ns XQ5VSX240T N/A 5.51 N/A ns XQ5VFX70T 4.54 5.02 5.02 ns XQ5VFX100T 4.70 5.19 5.19 ns XQ5VFX130T 4.86 5.40 N/A ns XQ5VFX200T N/A 5.55 N/A ns Notes: 1. 2. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. PLL output jitter is included in the timing calculation. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 62 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 89: Global Clock Input to Output Delay With DCM and PLL in System-Synchronous Mode Symbol Description Device Speed Grade -2I -1I -1M Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM and PLL in System-Synchronous Mode TICKOFDCM_PLL Global Clock and OUTFF with DCM and PLL XQ5VLX30T 2.48 2.84 N/A ns XQ5VLX85 2.55 2.91 N/A ns XQ5VLX110 2.61 2.97 N/A ns XQ5VLX110T 2.61 2.97 N/A ns XQ5VLX155T 2.66 3.01 N/A ns XQ5VLX220T 2.75 3.09 N/A ns XQ5VLX330T N/A 3.28 N/A ns XQ5VSX50T 2.61 2.96 N/A ns XQ5VSX95T 2.56 2.91 N/A ns XQ5VSX240T N/A 3.27 N/A ns XQ5VFX70T 2.66 3.03 3.03 ns XQ5VFX100T 2.51 2.91 2.91 ns XQ5VFX130T 2.59 2.98 N/A ns XQ5VFX200T N/A 3.18 N/A ns Notes: 1. 2. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. DCM and PLL output jitter are already included in the timing calculation. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 63 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 90: Global Clock Input to Output Delay With DCM and PLL in Source-Synchronous Mode Symbol Description Device Speed Grade -2I -1I -1M Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM and PLL in Source-Synchronous Mode TICKOFDCM0_PLL Global Clock and OUTFF with DCM and PLL XQ5VLX30T 3.63 4.06 N/A ns XQ5VLX85 3.78 4.20 N/A ns XQ5VLX110 3.84 4.27 N/A ns XQ5VLX110T 3.84 4.27 N/A ns XQ5VLX155T 4.10 4.53 N/A ns XQ5VLX220T 4.33 4.76 N/A ns XQ5VLX330T N/A 4.95 N/A ns XQ5VSX50T 3.83 4.26 N/A ns XQ5VSX95T 4.08 4.50 N/A ns XQ5VSX240T N/A 5.02 N/A ns XQ5VFX70T 3.88 4.32 4.32 ns XQ5VFX100T 4.02 4.44 4.44 ns XQ5VFX130T 4.21 4.65 N/A ns XQ5VFX200T N/A 4.94 N/A ns Notes: 1. 2. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. DCM and PLL output jitter are already included in the timing calculation. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 64 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Virtex-5Q Device Pin-to-Pin Input Parameter Guidelines All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are listed in Table 91. Values are expressed in nanoseconds unless otherwise noted. Table 91: Global Clock Setup and Hold without DCM or PLL Symbol Description Device Speed Grade -2I -1I -1M Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard(1) TPSFD/ TPHFD Full Delay (Legacy Delay or Default Delay) Global Clock and IFF(2) without DCM or PLL XQ5VLX30T 1.60 -0.35 1.76 -0.35 N/A ns XQ5VLX85 1.89 -0.49 2.09 -0.49 N/A ns XQ5VLX110 1.88 -0.43 2.09 -0.43 N/A ns XQ5VLX110T 1.88 -0.43 2.09 -0.43 N/A ns XQ5VLX155T 2.36 -0.50 2.78 -0.49 N/A ns XQ5VLX220T 2.57 -0.74 2.86 -0.74 N/A ns XQ5VLX330T N/A 2.86 -0.56 N/A ns XQ5VSX50T 1.74 -0.31 1.93 -0.31 N/A ns XQ5VSX95T 2.10 -0.44 2.32 -0.44 N/A ns XQ5VSX240T N/A 2.28 0.18 N/A ns XQ5VFX70T 2.06 -0.30 2.35 -0.30 2.35 -0.30 ns XQ5VFX100T 2.38 -0.42 2.66 -0.42 2.66 -0.42 ns XQ5VFX130T 2.59 -0.54 2.95 -0.54 N/A ns XQ5VFX200T N/A 2.81 -0.43 N/A ns Notes: 1. 2. 3. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. IFF = Input Flip-Flop or Latch A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 65 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 92: Global Clock Setup and Hold with DCM in System-Synchronous Mode Symbol Description Device Speed Grade -2I -1I -1M Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard(1) TPSDCM/ TPHDCM No Delay Global Clock and IFF(2) with DCM in System-Synchronous Mode XQ5VLX30T 1.70 -0.50 1.88 -0.50 N/A ns XQ5VLX85 1.76 -0.43 1.95 -0.43 N/A ns XQ5VLX110 1.76 -0.37 1.95 -0.37 N/A ns XQ5VLX110T 1.76 -0.37 1.95 -0.37 N/A ns XQ5VLX155T 2.16 -0.32 2.38 -0.32 N/A ns XQ5VLX220T 2.17 -0.27 2.44 -0.27 N/A ns XQ5VLX330T N/A 2.44 -0.10 N/A ns XQ5VSX50T 1.76 -0.37 1.95 -0.37 N/A ns XQ5VSX95T 2.34 -0.41 2.35 -0.41 N/A ns XQ5VSX240T N/A 2.54 -0.10 N/A ns XQ5VFX70T 1.86 -0.36 1.98 -0.36 1.98 -0.36 ns XQ5VFX100T 2.35 -0.51 2.49 -0.49 2.49 -0.49 ns XQ5VFX130T 2.48 -0.43 2.72 -0.42 N/A ns XQ5VFX200T N/A 2.43 -0.21 N/A ns Notes: 1. 2. 3. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include DCM CLK0 jitter. IFF = Input Flip-Flop or Latch Use IBIS to determine any duty-cycle distortion incurred using various standards. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 66 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 93: Global Clock Setup and Hold with DCM in Source-Synchronous Mode Symbol Description Device Speed Grade -2I -1I -1M Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard(1) TPSDCM0/ TPHDCM0 No Delay Global Clock and IFF(2) with DCM in Source-Synchronous Mode XQ5VLX30T 0.27 0.62 0.27 0.66 N/A ns XQ5VLX85 0.24 0.76 0.24 0.80 N/A ns XQ5VLX110 0.24 0.82 0.24 0.87 N/A ns XQ5VLX110T 0.24 0.82 0.24 0.87 N/A ns XQ5VLX155T 0.14 1.08 0.16 1.13 N/A ns XQ5VLX220T 0.21 1.31 0.22 1.36 N/A ns XQ5VLX330T N/A 0.22 1.55 N/A ns XQ5VSX50T 0.25 0.82 0.25 0.86 N/A ns XQ5VSX95T 0.24 1.06 0.24 1.11 N/A ns XQ5VSX240T N/A 0.21 1.62 N/A ns XQ5VFX70T 0.14 0.86 0.14 0.92 0.14 0.92 ns XQ5VFX100T 0.21 1.00 0.21 1.05 0.21 1.05 ns XQ5VFX130T 0.21 1.19 0.24 1.25 N/A ns XQ5VFX200T N/A 0.16 1.55 N/A ns Notes: 1. 2. 3. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include DCM CLK0 jitter. IFF = Input Flip-Flop or Latch Use IBIS to determine any duty-cycle distortion incurred using various standards. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 67 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 94: Global Clock Setup and Hold with PLL in System-Synchronous Mode Symbol Description Device Speed Grade -2I -1I -1M Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard(1) TPSPLL/ TPHPLL No Delay Global Clock and IFF(2) with PLL in System-Synchronous Mode XQ5VLX30T 1.68 -0.80 1.90 -0.79 N/A ns XQ5VLX85 1.95 -0.62 2.09 -0.61 N/A ns XQ5VLX110 1.96 -0.57 2.10 -0.57 N/A ns XQ5VLX110T 1.96 -0.57 2.10 -0.57 N/A ns XQ5VLX155T 2.09 -0.49 2.37 -0.47 N/A ns XQ5VLX220T 1.93 -0.36 2.09 -0.36 N/A ns XQ5VLX330T N/A 2.34 -0.21 N/A ns XQ5VSX50T 2.07 -0.72 2.20 -0.72 N/A ns XQ5VSX95T 2.17 -0.80 2.35 -0.79 N/A ns XQ5VSX240T N/A 2.33 -0.14 N/A ns XQ5VFX70T 1.90 -0.30 2.07 -0.30 2.07 -0.30 ns XQ5VFX100T 1.91 -0.40 2.09 -0.38 2.09 -0.38 ns XQ5VFX130T 1.95 -0.28 2.14 -0.24 N/A ns XQ5VFX200T N/A 2.29 -0.14 N/A ns Notes: 1. 2. 3. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter. IFF = Input Flip-Flop or Latch Use IBIS to determine any duty-cycle distortion incurred using various standards. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 68 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 95: Global Clock Setup and Hold with PLL in Source-Synchronous Mode Symbol Description Device Speed Grade -2I -1I -1M Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard(1) TPSPLL0/ TPHPLL0 No Delay Global Clock and IFF(2) with PLL in Source-Synchronous Mode XQ5VLX30T -0.33 1.22 -0.33 1.34 N/A ns XQ5VLX85 -0.23 1.30 -0.22 1.39 N/A ns XQ5VLX110 -0.24 1.34 -0.23 1.43 N/A ns XQ5VLX110T -0.25 1.34 -0.23 1.43 N/A ns XQ5VLX155T -0.12 1.56 -0.10 1.67 N/A ns XQ5VLX220T -0.34 1.75 -0.30 1.80 N/A ns XQ5VLX330T N/A -0.30 1.95 N/A ns XQ5VSX50T -0.26 1.44 -0.25 1.53 N/A ns XQ5VSX95T -0.26 1.58 -0.24 1.65 N/A ns XQ5VSX240T N/A -0.31 2.02 N/A ns XQ5VFX70T -0.10 1.44 -0.09 1.53 -0.09 1.53 ns XQ5VFX100T -0.18 1.60 -0.18 1.71 -0.18 1.71 ns XQ5VFX130T -0.11 1.76 -0.09 1.92 N/A ns XQ5VFX200T N/A -0.10 2.06 N/A ns Notes: 1. 2. 3. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter. IFF = Input Flip-Flop or Latch Use IBIS to determine any duty-cycle distortion incurred using various standards. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 69 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 96: Global Clock Setup and Hold with DCM and PLL in System-Synchronous Mode Symbol Description Device Speed Grade -2I -1I -1M Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard(1) TPSDCMPLL/ TPHDCMPLL No Delay Global Clock and IFF(2) with DCM and PLL in System-Synchronous Mode XQ5VLX30T 1.89 -0.58 2.06 -0.58 N/A ns XQ5VLX85 1.93 -0.51 2.13 -0.51 N/A ns XQ5VLX110 1.93 -0.45 2.13 -0.45 N/A ns XQ5VLX110T 1.93 -0.45 2.13 -0.45 N/A ns XQ5VLX155T 2.31 -0.40 2.55 -0.40 N/A ns XQ5VLX220T 2.32 -0.35 2.61 -0.35 N/A ns XQ5VLX330T N/A 2.61 -0.18 N/A ns XQ5VSX50T 1.94 -0.45 2.14 -0.45 N/A ns XQ5VSX95T 2.51 -0.49 2.53 -0.49 N/A ns XQ5VSX240T N/A 2.70 -0.18 N/A ns XQ5VFX70T 2.03 -0.44 2.16 -0.44 2.16 -0.44 ns XQ5VFX100T 2.51 -0.59 2.66 -0.58 2.66 -0.58 ns XQ5VFX130T 2.64 -0.51 2.89 -0.51 N/A ns XQ5VFX200T N/A 2.59 -0.30 N/A ns Notes: 1. 2. 3. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include CMT jitter; DCM CLK0 driving PLL, PLL CLKOUT0 driving BUFG. IFF = Input Flip-Flop or Latch Use IBIS to determine any duty-cycle distortion incurred using various standards. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 70 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 97: Global Clock Setup and Hold with DCM and PLL in Source-Synchronous Mode Symbol Description Device Speed Grade -2I -1I -1M Units Example Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin,(1) using DCM, PLL, and Global Clock Buffer. For situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the values shown in IOB Switching Characteristics. TPSDCMPLL_0/ TPHDCMPLL_0 No Delay Global Clock and IFF(2) with DCM and PLL in Source-Synchronous Mode XQ5VLX30T 0.46 0.54 0.46 0.57 N/A ns XQ5VLX85 0.42 0.68 0.42 0.71 N/A ns XQ5VLX110 0.41 0.74 0.41 0.78 N/A ns XQ5VLX110T 0.41 0.74 0.41 0.78 N/A ns XQ5VLX155T 0.29 1.00 0.33 1.04 N/A ns XQ5VLX220T 0.36 1.23 0.38 1.27 N/A ns XQ5VLX330T N/A 0.38 1.46 N/A ns XQ5VSX50T 0.43 0.74 0.43 0.77 N/A ns XQ5VSX95T 0.41 0.98 0.41 1.02 N/A ns XQ5VSX240T N/A 0.38 1.53 N/A ns XQ5VFX70T 0.32 0.78 0.32 0.83 0.32 0.83 ns XQ5VFX100T 0.35 0.92 0.35 0.96 0.35 0.96 ns XQ5VFX130T 0.37 1.11 0.41 1.16 N/A ns XQ5VFX200T N/A 0.33 1.46 N/A ns Notes: 1. 2. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. The timing values were measured using the fine-phase adjustment feature of the DCM. These measurements include CMT jitter; DCM CLK0 driving PLL, PLL CLKOUT0 driving BUFG. Package skew is not included in these measurements. IFF = Input Flip-Flop DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 71 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Source-Synchronous Switching Characteristics The parameters in this section provide the necessary values for calculating timing budgets for Virtex-5Q FPGA sourcesynchronous transmitter and receiver data-valid windows. Table 98: Duty Cycle Distortion and Clock-Tree Skew Symbol TDCD_CLK TCKSKEW Description Device Global Clock Tree Duty Cycle Distortion(1) Global Clock Tree Skew(2) Speed Grade Units -2I -1I -1M All 0.12 0.12 0.12 ns XQ5VLX30T 0.22 0.22 N/A ns XQ5VLX85 0.43 0.45 N/A ns XQ5VLX110 0.50 0.51 N/A ns XQ5VLX110T 0.50 0.51 N/A ns XQ5VLX155T 0.85 0.88 N/A ns XQ5VLX220T 1.07 1.10 N/A ns XQ5VLX330T N/A 1.29 N/A ns XQ5VSX50T 0.44 0.45 N/A ns XQ5VSX95T 0.72 0.74 N/A ns XQ5VSX240T N/A 1.36 N/A ns XQ5VFX70T 0.42 0.43 0.43 ns XQ5VFX100T 0.84 0.86 0.86 ns XQ5VFX130T 0.84 0.86 N/A ns XQ5VFX200T N/A 1.29 N/A ns TDCD_BUFIO I/O clock tree duty cycle distortion All 0.10 0.10 0.10 ns TBUFIOSKEW I/O clock tree skew across one clock region All 0.07 0.08 0.08 ns TDCD_BUFR Regional clock tree duty cycle distortion All 0.25 0.25 0.25 ns Notes: 1. 2. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor and Timing Analyzer tools to evaluate clock skew specific to your application. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 72 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 99: Package Skew(1) Symbol TPKGSKEW Description Device Package Skew(2) Package Value Units XQ5VLX30T(3) FF323 127 ps XQ5VLX85 EF676 142 ps XQ5VLX110 EF676 142 ps XQ5VLX110 EF1153 173 ps XQ5VLX110T EF1136 163 ps XQ5VLX155T EF1136 147 ps XQ5VLX220T EF1738 156 ps XQ5VLX330T EF1738 155 ps XQ5VSX50T EF665 103 ps XQ5VSX95T EF1136 176 ps XQ5VSX240T(3) FF1738 161 ps XQ5VFX70T EF665 102 ps XQ5VFX70T EF1136 153 ps XQ5VFX100T EF1136 144 ps XQ5VFX100T EF1738 172 ps XQ5VFX130T EF1738 181 ps XQ5VFX200T(3) FF1738 164 ps Notes: 1. 2. 3. Package trace length information is available for these device/package combinations. This information can be used to deskew the package. These values represent the worst-case skew between any two SelectIO resources in the package: shortest flight time to longest flight time from Pad to Ball (7.0 ps per mm). The EF package is not available for these devices. Table 100: Sample Window Symbol TSAMP TSAMP_BUFIO Description Device Sampling Error at Receiver Pins(1) Sampling Error at Receiver Pins using BUFIO(2) Speed Grade Units -2I -1I -1M All 500 550 550 ps All 400 450 450 ps Notes: 1. 2. This parameter indicates the total sampling error of Virtex-5Q FPGA DDR input registers across voltage, temperature, and process. The characterization methodology uses the DCM to capture the DDR input registers' edges of operation. These measurements include: - CLK0 DCM jitter - DCM accuracy (phase offset) - DCM phase shift resolution These measurements do not include package or clock tree skew. This parameter indicates the total sampling error of Virtex-5Q FPGA DDR input registers across voltage, temperature, and process. The characterization methodology uses the BUFIO clock network and IODELAY to capture the DDR input registers' edges of operation. These measurements do not include package or clock tree skew. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 73 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 101: Source-Synchronous Pin-to-Pin Setup/Hold and Clock-to-Out Symbol Speed Grade Description Units -2I -1I -1M -0.54 1.72 -0.54 1.91 -0.54 1.91 ns 4.82 5.40 5.40 ns Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO TPSCS/TPHCS Setup/Hold of I/O clock Pin-to-Pin Clock-to-Out Using BUFIO TICKOFCS Clock-to-Out of I/O clock Revision History The following table shows the revision history for this document. Date Version Description of Revisions 05/05/09 1.0 Initial Xilinx release. 12/17/09 2.0 Changed the document classification from Preliminary Product Specification to Product Specification. Updated XQ5VSX240T, XQ5VFX70T, and XQ5VFX200T to production devices in Table 54 and Table 55. Updated package information for XQ5VFX200T and XQ5VSX240T in Table 99. 07/23/10 2.1 Production release of XQ5VFX70T and XQ5VFX100T in the -1M speed grade. This includes changes to Table 54 and Table 55. Added a -1M column to any table with speed grades. Also updated the -2I speed grade software in Table 55 for the XQ5VLX220T and XQ5VSX95T device. Added -1(M) column to Table 4 including values for XQ5VFX70T and XQ5VFX100T. Revised maximum VOD in Table 8. Updated both minimum and maximum VOCM in Table 10. Updated minimum DVPPIN in Table 40. In Table 46, updated TJ4.25 and added note 5. In Table 51, added I-grade and Mgrade delineation for gain error, bipolar gain error, and ADCCLK revised AIDD maximum specification. Added note 1 to Table 57. In Table 71, added the FX70T (M) specification for the global clock tree (BUFG) FMAX. Added the FX70T (M) specification for the FOUTMAX to Table 74. Added note 5 to Table 76. Added note 5 to Table 77. Added note 3 to Table 81. 01/17/11 2.2 Revised production release of the XQ5VFX70T and XQ5VFX100T in the -1M speed grade to software version ISE 12.4 using the v1.71 speed specification (see Table 55). Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). 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CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL APPLICATIONS. DS714 (v2.2) January 17, 2011 Product Specification www.xilinx.com 74