EVALUATION KIT AVAILABLE MAX2112 Complete, Direct-Conversion Tuner for DVB-S2 Applications LE AVAILAB General Description Features The MAX2112 low-cost, direct-conversion tuner IC is designed for satellite set-top and VSAT applications. The IC is intended for 8PSK and Digital Video Broadcast (DVB-S2) applications. The MAX2112 directly converts the satellite signals from the LNB to baseband using a broadband I/Q downconverter. The operating frequency range extends from 925MHz to 2175MHz. The device includes an LNA and an RF variable-gain amplifier, I and Q downconverting mixers, and baseband lowpass filters with programmable cutoff frequency control and digitally controlled baseband variable-gain amplifiers. Together, the RF and baseband variable-gain amplifiers provide more than 80dB of gain control range. The IC is compatible with virtually all DVB-S2 demodulators. The MAX2112 includes fully monolithic VCOs, as well as a complete fractional-N frequency synthesizer. Additionally, an on-chip crystal oscillator is provided along with a buffered output for driving additional tuners and demodulators. Synthesizer programming and device configuration are accomplished with a 2-wire serial interface. The IC features a VCO autoselect (VAS) function that automatically selects the proper VCO. For multituner applications, the device can be configured to have one of two 2-wire interface addresses. A low-power standby mode is available whereupon the signal path is shut down while leaving the reference oscillator, digital interface, and buffer circuits active, providing a method to reduce power in single and multituner applications. Functional Diagrams The MAX2112 is the most advanced DBS tuner available today. The low noise figure eliminates the need for an external LNA. A small number of passive components are needed to form a complete DVB-S2 RF frontend solution. The tuner is available in a very small 28-pin thin QFN package. o 925MHz to 2175MHz Frequency Range o Monolithic VCO Low Phase Noise: -97dBc/Hz at 10kHz No Calibration Required o High Dynamic Range: -75dBm to 0dBm o Integrated Variable BW LP Filters: 4MHz to 40MHz o Single +3.3V 5% Supply o Low-Power Standby Mode o Address Pin for Multituner Applications o Differential I/Q Interface o I2C 2-Wire Serial Interface o Very Small 28-Pin TQFN Package Applications DirecTV and Dish Network DBS Ordering Information TEMP RANGE PIN-PACKAGE MAX2112CTI+ PART 0C to +70C 28 Thin QFN-EP* MAX2112ETI+ -40C to +85C 28 Thin QFN-EP* *EP = Exposed paddle. +Denotes a lead(Pb)-free/RoHS-compliant package. VCC_RF2 SCL SDA VCC_BB QDC- QDC+ IDC- + ADDR Pin Configuration/ Functional Diagram 28 27 26 25 24 23 22 1 DC OFFSET CORRECTION MAX2112 INTERFACE LOGIC AND CONTROL LPF BW CONTROL 21 IDC+ 20 IOUT- VCC_RF1 2 GND 3 19 IOUT+ RFIN 4 18 QOUT- GC1 5 17 QOUT+ 16 VCC_DIG 15 REFOUT DVB-S2 FREQUENCY SYNTHESIZER DIV2/DIV4 8 9 10 11 12 13 GNDSYN CPOUT VCC_SYN 7 GNDTUNE VCC_VCO EP VTUNE 6 VCOBYP Pin Configurations appear at end of data sheet. Functional Diagrams continued at end of data sheet. UCSP is a trademark of Maxim Integrated Products, Inc. VCC_LO For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maximintegrated.com. 14 XTAL VSATs 19-0869; Rev 2; 5/10 MAX2112 Complete, Direct-Conversion Tuner for DVB-S2 Applications ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.3V to +3.9V All Other Pins to GND.................................-0.3V to (VCC + 0.3V) RF Input Power: RFIN .....................................................+10dBm VCOBYP, CPOUT, XTAL, REFOUT, IOUT_, QOUT_ , IDC_, QDC_ to GND Short-Circuit Protection...............................10s Continuous Power Dissipation (TA = +70C) 28-Pin Thin QFN (derated 34.5mW/C above +70C) ...2.75W Operating Temperature Range (MAX2112CTI+) ......0C to +70C Operating Temperature Range (MAX2112ETI+) ...-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10s) .................................+300C Soldering Temperature (reflow) .......................................+260C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION! ESD SENSITIVE DEVICE DC ELECTRICAL CHARACTERISTICS (MAX2112 Evaluation Kit: VCC = +3.13V to +3.47V, TA = 0C to +70C (MAX2112CTI+), TA = -40C to +85C (MAX2112ETI+), VGC1 = +0.5V (max gain), default register settings except BBG[3:0] = 1011. No input signals at RF, baseband I/Os are open circuited. Typical values measured at VCC = +3.3V, TA = +25C.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS V SUPPLY Supply Voltage Supply Current 3.3 3.47 Receive mode, bit STBY = 0 3.13 100 160 Standby mode, bit STBY = 1 3 mA ADDRESS SELECT INPUT (ADDR) Digital Input Voltage High, VIH 2.4 V Digital Input Voltage Low, VIL 0.5 V Digital Input Current High, IIH 50 A Digital Input Current Low, IIL -50 A ANALOG GAIN-CONTROL INPUT (GC1) Input Voltage Range Maximum gain = 0.5V Input Bias Current 0.5 2.7 V -50 +50 A 0.4 2.3 V 400 kHz VCO TUNING VOLTAGE INPUT (VTUNE) Input Voltage Range 2-WIRE SERIAL INPUTS (SCL, SDA) Clock Frequency 0.7 x VCC Input Logic-Level High V Input Logic-Level Low Input Leakage Current Digital inputs = GND or VCC 0.1 0.3 x VCC V 1 A 0.4 V 2-WIRE SERIAL OUTPUT (SDA) Output Logic-Level Low 2 ISINK = 1mA Maxim Integrated MAX2112 Complete, Direct-Conversion Tuner for DVB-S2 Applications AC ELECTRICAL CHARACTERISTICS (MAX2112 Evaluation Kit: VCC = +3.13V to +3.47V, TA = 0C to +70C (MAX2112CTI+), TA = -40C to +85C (MAX2112ETI+), default register settings except BBG[3:0] = 1011. Typical values measured at VCC = +3.3V, TA = +25C.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS 2175 MHz MAIN SIGNAL PATH PERFORMANCE Input Frequency Range (Note 2) 925 RF Gain-Control Range (GC1) 0.5V < VGC1 < 2.7V 65 73 Baseband Gain-Control Range Bits GC2 = 1111 to 0000 13 15 dB In-Band Input IP3 (Note 3) +2 dBm Out-of-Band Input IP3 (Note 4) +15 dBm Input IP2 (Note 5) +40 dBm Adjacent Channel Protection (Note 6) 25 dB 8 Noise Figure VGC1 is set to 0.5V (maximum RF gain) and BBG[3:0] is adjusted to give a 1VP-P baseband output level for a -75dBm CW input tone at 1500MHz Starting with the same BBG[3:0] setting as above, VGC1 is adjusted to back off RF gain by 10dB (Note 7) 9 925MHz < fRF < 2175MHz, in 75 system 12 dB 1 VP-P Minimum RF Input Return Loss dB dB 12 BASEBAND OUTPUT CHARACTERISTICS Nominal Output Voltage Swing RLOAD = 2k//10pF 0.5 I/Q Amplitude Imbalance Measured at 500kHz; filter set to 22.27MHz 1 dB I/Q Quadrature Phase Imbalance Measured at 500kHz; filter set to 22.27MHz 3.5 Degrees Single-Ended I/Q Output Impedance Real ZO, from 1MHz to 40MHz 30 Output 1dB Compression Voltage Differential 3 VP-P Baseband Highpass -3dB Frequency Corner 47nF capacitors at IDC_, QDC_ 400 Hz BASEBAND LOWPASS FILTERS Filter Bandwidth Range 4 40 MHz Rejection Ratio At 2 x f-3dB 39 dB Group Delay Up to 1dB bandwidth 37 ns Ratio of In-Filter-Band to Out-ofFilter-Band Noise fINBAND = 100Hz to 22.5MHz, fOUTBAND = 87.5MHz to 112.5MHz 25 dB FREQUENCY SYNTHESIZER RF-Divider Frequency Range 925 2175 RF-Divider Range (N) 19 251 MHz Reference-Divider Frequency Range 12 30 Reference-Divider Range (R) 1 1 Phase-Detector Comparison Frequency 12 30 MHz 2175 MHz MHz VOLTAGE-CONTROLLED OSCILLATOR AND LO GENERATION Guaranteed LO Frequency Range LO Phase Noise Maxim Integrated 925 fOFFSET = 10kHz -97 fOFFSET = 100kHz -100 fOFFSET = 1MHz -122 dBc/Hz 3 MAX2112 Complete, Direct-Conversion Tuner for DVB-S2 Applications AC ELECTRICAL CHARACTERISTICS (continued) (MAX2112 Evaluation Kit: VCC = +3.13V to +3.47V, TA = 0C to +70C (MAX2112CTI+), TA = -40C to +85C (MAX2112ETI+), default register settings except BBG[3:0] = 1011. Typical values measured at VCC = +3.3V, TA = +25C.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS 30 MHz 1 2.0 VP-P 1.5 2 XTAL/REFERENCE OSCILLATOR INPUT AND OUTPUT BUFFER XTAL Oscillator Frequency Range Parallel-resonance-mode crystal (Note 8) 12 Input Overdrive level AC-coupled sine-wave input 0.5 XTAL Output-Buffer Divider Range XTAL Output Voltage Swing XTAL Output Duty Cycle 1 4MHz to 30MHz, CLOAD = 10pF 1 8 50 VP-P % Note 1: MAX2112CTI+: Min/max values are production tested at TA = +70C. Min/max limits at TA = 0C and TA = +25C are guaranteed by design and characterization. MAX2112ETI+: Min/max values are production tested at TA = +85C. Min/max limits at TA = -40C and TA = +25C are guaranteed by design and characterization. Note 2: Input gain range specifications met over this band. Note 3: In-band IIP3 test conditions: GC1 set to provide the nominal baseband output drive when mixing down a -23dBm tone at 2175MHz to 5MHz baseband (fLO = 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at -26dBm each are applied at 2174MHz and 2175MHz. The IM3 tone at 3MHz is measured at baseband, but is referred to the RF input. Note 4: Out-of-band IIP3 test conditions: GC1 set to provide nominal baseband output drive when mixing down a -23dBm tone at 2175MHz to 5MHz baseband (fLO = 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at -20dBm each are applied at 2070MHz and 1975MHz. The IM3 tone at 5MHz is measured at baseband, but is referred to the RF input. Note 5: Input IP2 test conditions: GC1 set to provide nominal baseband output drive when mixing down a -23dBm tone at 2175MHz to 5MHz baseband (fLO = 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at -20dBm each are applied at 925MHz and 1250MHz. The IM2 tone at 5MHz is measured at baseband, but is referred to the RF input. Note 6: Adjacent channel protection test conditions: GC1 is set to provide the nominal baseband output drive with a 2110MHz 27.5Mbaud signal at -55dBm. GC2 set for mid-scale. The test signal shall be set for PR = 7/8 and SNR of -8.5dB. An adjacent channel at 40MHz is added at -25dBm. DVB-S BER performance of 2E-4 shall be maintained for the desired signal. GC2 may be adjusted for best performance. Note 7: Guaranteed by design and characterization at TA = +25C. Note 8: See Table 16 for crystal ESR requirements. 4 Maxim Integrated MAX2112 Complete, Direct-Conversion Tuner for DVB-S2 Applications Typical Operating Characteristics (MAX2112 Evaluation Kit: VCC = +3.3V, TA = +25C, baseband output frequency = 5MHz; VGC1 = +1.2V, default register settings except BBG[3:0] = 1011.) STANDBY MODE SUPPLY CURRENT vs. SUPPLY VOLTAGE 94 93 92 TA = -40C 2.8 2.7 TA = +25C 2.6 2.5 90 88 3.3 3.4 3.5 SUPPLY VOLTAGE (V) HD3 vs. VOUT QUADRATURE PHASE vs. LO FREQUENCY 3.0 -25 -30 -35 -40 -45 3.5 MAX2112 toc05a TA = +25C 91.5 TA = +85C 90.5 89.5 TA = -40C 88.5 4 -50 87.5 2.0 2.5 3.0 1200 VOUT (VP-P) QUADRATURE PHASE vs. BASEBAND FREQUENCY 92.5 TA = +85C 91.5 90.5 TA = +25C 89.5 1500 1800 2100 LO FREQUENCY (MHz) TA = -40C 88.5 87.5 86.5 1.0 QUADRATURE MAGNITUDE MATCHING (dB) fLO = 925MHz 4 8 12 16 BASEBAND FREQUENCY (MHz) Maxim Integrated 0.6 20 28 32 36 40 TA = +25C 0.4 0.2 0 -0.2 TA = -40C -0.4 TA = +85C -0.6 -0.8 900 2400 fLO = 925MHz 0.8 0.6 0.4 0.2 0 -0.2 TA = +25C -0.6 1500 1800 2100 2400 BASEBAND FILTER FREQUENCY RESPONSE TA = +85C -0.4 1200 LO FREQUENCY (MHz) TA = -40C 0 -10 -20 -30 -40 -50 -60 -70 -0.8 -1.0 0 24 fBASEBAND = 10MHz 0.8 QUADRATURE MAGNITUDE MATCHING vs. BASEBAND FREQUENCY MAX2112 toc06a 93.5 20 -1.0 900 3.5 16 1.0 BASEBAND OUTPUT LEVEL (dB) 1.5 MAX2112 toc06b 1.0 12 QUADRATURE MAGNITUDE MATCHING vs. LO FREQUENCY 86.5 -60 8 BASEBAND FILTER CUTOFF FREQUENCY (MHz) 92.5 -55 90 3.6 fBASEBAND = 10MHz QUADRATURE PHASE () -20 3.1 93.5 MAX2112 toc04 -15 92 84 3.2 3.3 3.4 SUPPLY VOLTAGE (V) -10 BASEBAND 3RD-ORDER HARMONIC (dBc) 3.6 94 MAX2112 toc07 3.2 96 86 QUADRATURE MAGNITUDE MATCHING (dB) 3.1 98 88 2.3 3.0 QUADRATURE PHASE () 100 TA = -40C 2.4 89 102 MAX2112 toc05b TA = +25C 91 TA = +85C SUPPLY CURRENT (mA) 95 2.9 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 96 104 MAX2112 toc02 TA = +85C 97 3.0 MAX2112 toc01 98 SUPPLY CURRENT vs. BASEBAND FILTER CUTOFF FREQUENCY MAX2112 toc03 SUPPLY CURRENT vs. SUPPLY VOLTAGE -80 0 4 8 12 16 BASEBAND FREQUENCY (MHz) 20 0 20 40 60 80 BASEBAND FREQUENCY (MHz) 5 MAX2112 Complete, Direct-Conversion Tuner for DVB-S2 Applications Typical Operating Characteristics (continued) (MAX2112 Evaluation Kit: VCC = +3.3V, TA = +25C, baseband output frequency = 5MHz; VGC1 = +1.2V, default register settings except BBG[3:0] = 1011.) -8 -10 25 20 15 10 -12 5 -14 0 5 INPUT POWER vs. VGC1 MAX2112 toc11 TA = +25C -30 -40 TA = +85C TA = -40C 10 15 20 25 30 35 40 -50 -40 TA = +85C 9.5 9.0 TA = +70C 8.5 60 -80 3.0 40 30 -80 1100 1300 1500 1700 1900 2100 2300 FREQUENCY (MHz) -70 -10 -40 -30 -20 -10 0 60 10 SEE NOTE 5 ON PAGE 4 FOR CONDITIONS 50 40 0 IIP2 (dBm) 0 -50 INPUT POWER (dBm) MAX2112 toc15 SEE NOTE 3 ON PAGE 4 FOR CONDITIONS 20 IN-BAND IIP3 (dBm) 10 -60 IIP2 vs. INPUT POWER 30 MAX2112 toc14 20 OUT-OF-BAND IIP3 (dBm) 50 ADJUST BBG[3:0] FOR 1VP-P BASEBAND OUTPUT WITH PIN = -75dBm AND VGC1 = 0.5V. fLO = 1500MHz IN-BAND IIP3 vs. INPUT POWER SEE NOTE 4 ON PAGE 4 FOR CONDITIONS 80 0 900 OUT-OF-BAND IIP3 vs. INPUT POWER 30 60 10 7.5 2.5 0 20 40 TEMPERATURE (C) 20 TA = +25C 8.0 1.5 2.0 VGC1 (V) -20 70 -70 1.0 -0.6 NOISE FIGURE vs. INPUT POWER ADJUST BBG[3:0] FOR 1VP-P BASEBAND OUTPUT WITH PIN = -75dBm AND VGC1 = 0.5V 10.0 -60 0.5 -0.4 45 10.5 NOISE FIGURE (dB) INPUT POWER (dBm) ADJUST BBG[3:0] FOR 1VP-P BASEBAND OUTPUT WITH PIN = -75dBm AND VGC1 = 0.5V -20 0 -0.2 NOISE FIGURE vs. FREQUENCY 10 -10 0.2 PROGRAMMED f-3dB FREQUENCY (MHz) BASEBAND FREQUENCY (MHz) 0 0.4 -1.0 0 10,000 0.6 -0.8 NOISE FIGURE (dB) 1000 MAX2112 toc09 30 NORMALIZED TO TA = +25C 0.8 MAX2112 toc13 -6 35 1.0 MAX2112 toc16 -4 LPF[7:0] = 12 + (f-3dB - 4MHz)/290kHz 40 BASEBAND GAIN ERROR AT f-3dB (dB) -2 45 MAX2112 toc12 BASEBAND OUTPUT LEVEL (dB) 0 MEASURED f-3dB FREQUENCY (MHz) MAX2112 toc08 2 100 BASEBAND FILTER 3dB FREQUENCY vs. TEMPERATURE PROGRAMMED f-3dB FREQUENCY vs. MEASURED f-3dB FREQUENCY MAX2112 toc10 BASEBAND FILTER HIGHPASS FREQUENCY RESPONSE -10 -20 -30 30 20 10 -40 -20 0 -50 -80 -70 -60 -50 -40 -30 INPUT POWER (dBm) 6 -10 -60 -30 -20 -10 0 -80 -70 -60 -50 -40 -30 INPUT POWER (dBm) -20 -10 0 -80 -70 -60 -50 -40 -30 -20 -10 0 INPUT POWER (dBm) Maxim Integrated MAX2112 Complete, Direct-Conversion Tuner for DVB-S2 Applications Typical Operating Characteristics (continued) (MAX2112 Evaluation Kit: VCC = +3.3V, TA = +25C, baseband output frequency = 5MHz; VGC1 = +1.2V, default register settings except BBG[3:0] = 1011.) PHASE NOISE AT 10kHz OFFSET vs. CHANNEL FREQUENCY INPUT RETURN LOSS vs. FREQUENCY MAX2112 toc17 VGC1 = 0.5V -10 -15 -20 VGC1 = 2.7V -25 900 1125 1350 1575 1800 2025 2250 MAX2112 toc18 -90 -95 -100 -105 925 FREQUENCY (MHz) LO LEAKAGE vs. LO FREQUENCY PHASE NOISE vs. OFFSET FREQUENCY MAX2112 toc19 -70 MEASURED AT RF INPUT -75 -100 LO LEAKAGE (dBm) PHASE NOISE (dBc/Hz) -90 1115 1305 1495 1685 1875 2065 2255 CHANNEL FREQUENCY (MHz) MAX2112 toc20 -5 PHASE NOISE AT 10kHz OFFSET (dBc/Hz) INPUT RETURN LOSS (dB) 0 -110 -80 -85 -120 fLO = 1800MHz -130 1.0E+03 -90 1.0E+04 925 1.0E+06 1.0E+05 1175 OFFSET FREQUENCY (Hz) 1425 1675 1925 LO FREQUENCY (MHz) 2175 VCO: KV vs. VTUNE MAX2112 toc21 450 400 350 SUB-BAND 23 KV (MHz/V) 300 250 200 SUB-BAND 12 150 100 50 SUB-BAND 0 0 0 Maxim Integrated 0.5 1.0 1.5 2.0 VTUNE (V) 2.5 3.0 7 MAX2112 Complete, Direct-Conversion Tuner for DVB-S2 Applications Pin Description 8 PIN NAME FUNCTION 1 VCC_RF2 DC Power Supply for LNA. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections. 2 VCC_RF1 DC Power Supply for LNA. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections. 3 GND Ground. Connect to board's ground plane for proper operation. 4 RFIN Wideband 75 RF Input. Connect to an RF source through a DC-blocking capacitor. 5 GC1 RF Gain-Control Input. High-impedance analog input with a 0.5V to 2.7V operating range. VGC1 = 0.5V corresponds to the maximum gain setting. 6 VCC_LO 7 VCC_VCO DC Power Supply for VCO Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections. 8 VCOBYP Internal VCO Bias Bypass. Bypass to GND with a 100nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections. 9 VTUNE 10 GNDTUNE 11 GNDSYN 12 CPOUT C h ar g e - P ump O u tp u t . Co n n e c t t h is o u t p u t t o t he P L L lo o p filt e r in p u t w it h th e sh or t e st c o n n e ct io n p o ssib le . 13 VCC_SYN DC Power Supply for Synthesizer Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections. 14 XTAL Crystal-Oscillator Interface. Use with an external parallel-resonance-mode crystal through a series 1nF capacitor. See the Typical Application Circuit. 15 REFOUT Crystal-Oscillator Buffer Output. A DC-blocking capacitor must be used when driving external circuitry. 16 VCC_DIG DC Power Supply for Digital Logic Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections. 17 QOUT+ 18 QOUT- 19 IOUT+ 20 IOUT- 21 IDC+ 22 IDC- 23 QDC+ 24 QDC- 25 VCC_BB DC Power Supply for LO Generation Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections. High-Impedance VCO Tune Input. Connect the PLL loop filter output directly to this pin with as short of a connection as possible. Ground for VTUNE. Connect to the PCB ground plane. Ground for Synthesizer. Connect to the PCB ground plane. Quadrature Baseband Differential Output. AC-couple with 47nF capacitors to the demodulator input. In-Phase Baseband Differential Output. AC-couple with 47nF capacitors to the demodulator input. I-Channel Baseband DC Offset Correction. Connect a 47nF ceramic chip capacitor from IDC- to IDC+. Q-Channel Baseband DC Offset Correction. Connect a 47nF ceramic chip capacitor from QDC- to QDC+. DC Power Supply for Baseband Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections. Maxim Integrated MAX2112 Complete, Direct-Conversion Tuner for DVB-S2 Applications Pin Description (continued) PIN NAME FUNCTION 26 SDA 2-Wire Serial-Data Interface. Requires 1k pullup resistor to VCC. 27 SCL 2-Wire Serial-Clock Interface. Requires 1k pullup resistor to VCC. 28 ADDR -- EP Address. Must be connected to either ground (logic 0) or supply (logic 1). Exposed Paddle. Solder evenly to the board's ground plane for proper operation. Detailed Description Register Description The MAX2112 includes 12 user-programmable registers and 2 read-only registers. See Table 1 for register configurations. The register configuration of Table 1 shows each bit name and the bit usage information for all registers. Note that all registers must be written after and no earlier than 100s after the device is powered up. Table 1. Register Configuration MSB LSB REG REGISTER READ/ REG NUMBER NAME WRITE ADDRESS DATA BYTE D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 1 N-Divider MSB Write 0x00 FRAC 1 N[14] N[13] N[12] N[11] N[10] N[9] N[8] 2 N-Divider LSB Write 0x01 N[7] N[6] N[5] N[4] N[3] N[2] N[1] N[0] 3 Charge Pump Write 0x02 CPMP[1] 0 CPMP[0] 0 CPLIN[1] 0 CPLIN[0] 1 F[19] F[18] F[17] F[16] 4 F-Divider MSB Write 0x03 F[15] F[14] F[13] F[12] F[11] F[10] F[9] F[8] 5 F-Divider LSB Write 0x04 F[7] F[6] F[5] F[4] F[3] F[2] F[1] F[0] 6 XTAL Divider R-Divider Write 0x05 XD[2] XD[1] XD[0] R[4] R[3] R[2] R[1] R[0] 7 PLL Write 0x06 D24 CPS ICP X X X X X 8 VCO Write 0x07 VCO[4] VCO[3] VCO[2] VCO[1] VCO[0] VAS ADL ADE 9 LPF Write 0x08 LPF[7] LPF[6] LPF[5] LPF[4] LPF[3] LPF[2] LPF[1] LPF[0] X BBG[3] BBG[2] BBG[1] BBG[0] 10 Control Write 0x09 STBY X PWDN 0 11 Shutdown Write 0x0A X PLL 0 DIV 0 VCO 0 BB 0 12 Test Write 0x0B CPTST[2] 0 CPTST[1] 0 CPTST[0] 0 X TURBO 1 13 Status Byte-1 Read 0x0C POR VASA VASE LD X 14 Status Byte-2 Read 0x0D X = Don't care. Maxim Integrated RFMIX RFVGA 0 0 FE 0 LD LD LD MUX[2] MUX[1] MUX[0] 0 0 0 X X X VCOSBR[4] VCOSBR[3] VCOSBR[2] VCOSBR[1] VCOSBR[0] ADC[2] ADC[1] ADC[0] 0 = Set to 0 for factory-tested operation. 1 = Set to 1 for factory-tested operation. 9 MAX2112 Complete, Direct-Conversion Tuner for DVB-S2 Applications Table 2. N-Divider MSB Register BIT NAME BIT LOCATION (0 = LSB) DEFAULT FRAC 7 1 N[14:8] 6-0 0000000 FUNCTION Users must program to 1 upon powering up the device. Sets the most significant bits of the PLL integer-divide number (N). N can range from 19 to 251. Table 3. N-Divider LSB Register BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION N[7:0] 7-0 00100011 Sets the least significant bits of the PLL integer-divide number. N can range from 19 to 251. Table 4. Charge-Pump Register BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION CPMP[1:0] 7-6 00 Charge-pump minimum pulse width. Users must program to 00 upon powering up the device. CPLIN[1:0] 5-4 00 Controls charge-pump linearity. Users must program to 01 upon powering up the device. F[19:16] 3-0 0010 Sets the 4 most significant bits of the PLL fractional divide number. Default value is F = 194,180 decimal. Table 5. F-Divider MSB Register BIT NAME F[15:8] BIT LOCATION (0 = LSB) DEFAULT 7-0 11110110 FUNCTION Sets the most significant bits of the PLL fractional-divide number (F). Default value is F = 194,180 decimal. Table 6. F-Divider LSB Register BIT NAME F[7:0] BIT LOCATION (0 = LSB) DEFAULT 7-0 10000100 FUNCTION Sets the least significant bits of the PLL fractional-divide number (F). Default value is F = 194,180 decimal. Table 7. XTAL Buffer and Reference Divider Register BIT NAME BIT LOCATION (0 = LSB) DEFAULT XD[2:0] 7-5 000 R[4:0] 4-0 00001 10 FUNCTION Sets the crystal-divider setting. 000 = Divide by 1. 001 = Divide by 2. 011 = Divide by 3. 100 = Divide by 4. 101 through 110 = All divide values from 5 (101) to 7 (110). 111 = Divide by 8. Sets the PLL reference-divider (R) number. Users must program to 00001 upon powering up the device. 00001 = Divide by 1; other values are not tested. Maxim Integrated MAX2112 Complete, Direct-Conversion Tuner for DVB-S2 Applications Table 8. PLL Register BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION D24 7 1 VCO divider setting. 0 = Divide by 2. Use for LO frequencies 1125MHz. 1 = Divide by 4. Use for LO frequencies < 1125MHz. CPS 6 1 Charge-pump current mode. 0 = Charge-pump current controlled by ICP bit. 1 = Charge-pump current controlled by VCO autoselect (VAS). ICP 5 0 Charge-pump current. 0 = 600A typical. 1 = 1200A typical. X 4-0 X Don't care. Table 9. VCO Register BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION Controls which VCO is activated when using manual VCO programming mode. This also serves as the starting point for the VCO autoselection (VAS) mode. VCO[4:0] 7-3 11001 VAS 2 1 VCO autoselection (VAS) circuit. 0 = Disable VCO selection must be programmed through I2C. 1 = Enable VCO selection controlled by autoselection circuit. 0 Enables or disables the VCO tuning voltage ADC latch when the VCO autoselect mode (VAS) is disabled. 0 = Disables the ADC latch. 1 = Latches the ADC value. 0 Enables or disables VCO tuning voltage ADC read when the VCO autoselect mode (VAS) is disabled. 0 = Disables ADC read. 1 = Enables ADC read. ADL 1 ADE 0 Table 10. Lowpass Filter Register BIT NAME BIT LOCATION (0 = LSB) DEFAULT LPF[7:0] Maxim Integrated 7-0 FUNCTION Sets the baseband lowpass filter 3dB corner frequency. 01001011 f-3dB = 4MHz + (LPF[7:0]dec - 12) x 290kHz. Default value equates to f-3dB = 22.27MHz typical. 11 MAX2112 Complete, Direct-Conversion Tuner for DVB-S2 Applications Table 11. Control Register BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION STBY 7 0 Software standby control. 0 = Normal operation. 1 = Disables the signal path and frequency synthesizer leaving only the 2-wire bus, crystal oscillator, XTALOUT buffer, and XTALOUT buffer divider active. X 6 X Don't care. PWDN 5 0 Factory use only. 0 = Normal operation; other value is not tested. X 4 X Don't care. BBG[3:0] 3-0 0000 Baseband gain setting (1dB typical per step). 0000 = Minimum gain (0dB, default). ... 1111 = Maximum gain (15dB typical). Table 12. Shutdown Register BIT NAME X 12 BIT LOCATION (0 = LSB) DEFAULT 7 FUNCTION X Don't care. PLL 6 0 PLL enable. 0 = Normal operation. 1 = Shuts down the PLL. Value not tested. DIV 5 0 Divider enable. 0 = Normal operation. 1 = Shuts down the divider. Value not tested. VCO 4 0 VCO enable. 0 = Normal operation. 1 = Shuts down the VCO. Value not tested. BB 3 0 Baseband enable. 0 = Normal operation. 1 = Shuts down the baseband. Value not tested. RFMIX 2 0 RF mixer enable. 0 = Normal operation. 1 = Shuts down the RF mixer. Value not tested. RFVGA 1 0 RF VGA enable. 0 = Normal operation. 1 = Shuts down the RF VGA. Value not tested. FE 0 0 Front-end enable. 0 = Normal operation. 1 = Shuts down the front-end. Value not tested. Maxim Integrated MAX2112 Complete, Direct-Conversion Tuner for DVB-S2 Applications Table 13. Test Register BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION CPTST[2:0] 7-5 000 X 4 X Don't care. TURBO 3 0 Charge-pump fast lock. Users must program to 1 after powering up the device. LDMUX[2:0] 2-0 000 Charge-pump test modes. 000 = Normal operation (default). REFOUT output. 000 = Normal operation. Other values are not tested. Table 14. Status Byte-1 Register BIT NAME BIT LOCATION (0 = LSB) FUNCTION POR 7 Power-on reset status. 0 = Chip status register has been read with a stop condition since last power-on. 1 = Power-on reset (power cycle) has occurred. Default values have been loaded in registers. VASA 6 Indicates whether VCO autoselection was successful. 0 = Indicates the autoselect function is disabled or unsuccessful VCO selection. 1 = Indicates successful VCO autoselection. VASE 5 Status indicator for the autoselect function. 0 = Indicates the autoselect function is active. 1 = Indicates the autoselect process is inactive. LD 4 PLL lock detector. TURBO bit must be programmed to 1 for valid LD reading. 0 = Unlocked. 1 = Locked. X 3:0 Don't care. Table 15. Status Byte-2 Register BIT NAME BIT LOCATION (0 = LSB) VCOSBR[4:0] 7-3 VCO band readback. 2-0 VAS ADC output readback. 000 = Out of lock. 001 = Locked. 010 = VAS locked. 101 = VAS locked. 110 = Locked. 111 = Out of lock. ADC[2:0] Maxim Integrated FUNCTION 13 MAX2112 Complete, Direct-Conversion Tuner for DVB-S2 Applications 2-Wire Serial Interface The MAX2112 uses a 2-wire I2C-compatible serial interface consisting of a serial-data line (SDA) and a serialclock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX2112 and the master at clock frequencies up to 400kHz. The master initiates a data transfer on the bus and generates the SCL signal to permit data transfer. The MAX2112 behaves as a slave device that transfers and receives data to and from the master. SDA and SCL must be pulled high with external pullup resistors (1k or greater) for proper bus operation. Pullup resistors should be referenced to the MAX2112's VCC. One bit is transferred during each SCL clock cycle. A minimum of nine clock cycles is required to transfer a byte in or out of the MAX2112 (8 bits and an ACK/NACK). The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high and stable are considered control signals (see the START and STOP Conditions section). Both SDA and SCL remain high when the bus is not busy. START and STOP Conditions The master initiates a transmission with a START condition (S), which is a high-to-low transition on SDA while SCL is high. The master terminates a transmission with a STOP condition (P), which is a low-to-high transition on SDA while SCL is high. Acknowledge and Not-Acknowledge Conditions Data transfers are framed with an acknowledge bit (ACK) or a not-acknowledge bit (NACK). Both the master and the MAX2112 (slave) generate acknowledge bits. To generate an acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse. To generate a not-acknowledge condition, the receiver allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse, and leaves SDA high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master must reattempt communication at a later time. WRITE DEVICE START ADDRESS 1100000 R/W ACK 0 -- WRITE REGISTER ADDRESS 0x00 ACK -- Slave Address The MAX2112 has a 7-bit slave address that must be sent to the device following a START condition to initiate communication. The slave address is internally programmed to 1100000. The eighth bit (R/W) following the 7-bit address determines whether a read or write operation occurs. The MAX2112 continuously awaits a START condition followed by its slave address. When the device recognizes its slave address, it acknowledges by pulling the SDA line low for one clock period; it is ready to accept or send data depending on the R/W bit (Figure 1). The write/read address is C0/C1 if ADDR pin is connected to ground. The write/read address is C2/C3 if ADDR pin is connected to VCC. SLAVE ADDRESS 1 S 1 0 0 0 0 0 SDA SCL 1 2 3 4 5 6 R/W ACK 8 9 7 Figure 1. MAX2112 Slave Address Byte with ADDR Pin Connected to Ground Write Cycle When addressed with a write command, the MAX2112 allows the master to write to a single register or to multiple successive registers. A write cycle begins with the bus master issuing a START condition followed by the seven slave address bits and a write bit (R/W = 0). The MAX2112 issues an ACK if the slave address byte is successfully received. The bus master must then send to the slave the address of the first register it wishes to write to (see Table 1 for register addresses). If the slave acknowledges the address, the master can then write one byte to the register at the specified address. Data is written beginning with the most significant bit. The MAX2112 again issues an ACK if the data is successfully written to the register. The master can continue to write data to the successive internal registers with the MAX2112 acknowledging each successful transfer, or it can terminate transmission by issuing a STOP condition. The write cycle does not terminate until the master issues a STOP condition. WRITE DATA TO REGISTER 0x00 0x0E ACK WRITE DATA TO REGISTER 0x01 -- 0xD8 ACK -- WRITE DATA TO REGISTER 0x02 0xE1 ACK STOP -- Figure 2. Example: Write Registers 0 through 2 with 0x0E, 0xD8, and 0xE1, respectively. 14 Maxim Integrated MAX2112 Complete, Direct-Conversion Tuner for DVB-S2 Applications S T A R T DEVICE ADDRESS R/W 1100000 0 A C K REGISTER ADDRESS 00000000 S T A R T A C K DEVICE ADDRESS R/W 1100000 1 A C K REG 00 DATA xxxxxxxx A C K REG 01 DATA xxxxxxxx A C K REG 02 DATA xxxxxxxx N A C K S T O P Figure 3. Example: Receive Data from Read Registers Read Cycle When addressed with a read command, the MAX2112 allows the master to read back a single register, or multiple successive registers. A read cycle begins with the bus master issuing a START condition followed by the 7 slave address bits and a write bit (R/W = 0). The MAX2112 issues an ACK if the slave address byte is successfully received. The bus master must then send the address of the first register it wishes to read (see Table 1 for register addresses). The slave acknowledges the address. Then, a START condition is issued by the master, followed by the 7 slave address bits and a read bit (R/W = 1). The MAX2112 issues an ACK if the slave address byte is successfully received. The MAX2112 starts sending data MSB first with each SCL clock cycle. At the 9th clock cycle, the master can issue an ACK and continue to read successive registers, or the master can terminate the transmission by issuing a NACK. The read cycle does not terminate until the master issues a STOP condition. Figure 3 illustrates an example in which registers 0 through 2 are read back. Application Information The MAX2112 downconverts RF signals in the 925MHz to 2175MHz range directly to the baseband I/Q signals. The devices are targeted for digital DBS tuner applications. RF Input The RF input of the MAX2112 is internally matched to 75. Only a DC-blocking capacitor is needed. See the Typical Application Circuit. RF Gain Control The MAX2112 features a variable-gain low-noise amplifier providing 73dB of RF gain range. The voltage control (VGC) range is 0.5V (minimum attenuation) to 2.7V (maximum attenuation). Baseband Variable-Gain Amplifier The receiver baseband variable-gain amplifiers provide 15dB of gain control range programmable in 1dB steps. The VGA gain can be serially programmed through the SPI interface by setting bits BBG[3:0] in the Control register. Maxim Integrated Table 16. Maximum Crystal ESR Requirement ESRMAX () XTAL FREQUENCY (MHz) 80 12 < fXTAL 14 60 14 < fXTAL 30 Baseband Lowpass Filter The MAX2112 includes a programmable on-chip 7th-order Butterworth filter. The filter -3dB corner frequency can be adjusted from approximately 4MHz to 40MHz by programming the LPF[7:0] register using the following equation: LPF[7:0]dec = (f-3dB - 4MHz)/0.29MHz + 12, where f-3dB is in units of MHz. Total device supply current depends on the filter BW setting. See Supply Current vs. Baseband Filter Cutoff Frequency in the Typical Operating Characteristics for more information. DC Offset Cancellation The DC offset cancellation is required to maintain the I/Q output dynamic range. Connecting an external capacitor between IDC+ and IDC- forms a highpass filter for the I channel and an external capacitor between QDC+ and QDC- forms a highpass filter for the Q channel. Keep the value of the external capacitor less than 47nF to form a typical highpass corner of 250Hz. XTAL Oscillator The MAX2112 contains an internal reference oscillator, reference output divider, and output buffer. All that is required is to connect a crystal through a series 1nF capacitor. To minimize parasitics, place the crystal and series capacitor as close as possible to pin 14 (XTAL pin). See Table 16 for crystal (XTAL) ESR (equivalent series resistance) requirements. VCO Autoselect (VAS) The MAX2112 includes 24 VCOs. The local oscillator frequency can be manually selected by programming the VCO[4:0] bits in the VCO register. The selected VCO is reported in the Status Byte-2 register (see Table 15). 15 MAX2112 Complete, Direct-Conversion Tuner for DVB-S2 Applications Alternatively, the MAX2112 can be set to autonomously choose a VCO by setting the VAS bit in the VCO register to logic-high. The VAS routine is initiated once the F-Divider LSB register word (REG 5) is loaded. In the event that only the N-divider register or F-divider MSB word is changed, the F-divider LSB word must also be loaded last to initiate the VCO autoselect function. The VCO value programmed in the VCO[4:0] register serves as the starting point for the automatic VCO selection process. During the selection process, the VASE bit in the Status Byte-1 register is cleared to indicate the autoselection function is active. Upon successful completion, bits VASE and VASA are set and the VCO selected is reported in the Status Byte-2 register (see Table 15). If the search is unsuccessful, VASA is cleared and VASE is set. This indicates that searching has ended but no good VCO has been found, and occurs when trying to tune to a frequency outside the VCO's specified frequency range. Refer to the MAX2112/MAX2120 VCO Autoselect (VAS) Application Note for more information. 3-Bit ADC The MAX2112 has an internal 3-bit ADC connected to the VCO tune pin (VTUNE). This ADC can be used for checking the lock status of the VCOs. Table 17 summarizes the ADC output bits and the VCO lock indication. The VCO autoselect routine only selects Table 17. ADC Trip Points and Lock Status 16 ADC[2:0] LOCK STATUS 000 Out of lock 001 Locked 010 VAS locked 101 VAS locked 110 Locked 111 Out of lock a VCO in the "VAS locked" range. This allows room for a VCO to drift over temperature and remain in a valid "locked" range. The ADC must first be enabled by setting the ADE bit in the VCO register. The ADC reading is latched by a subsequent programming of the ADC latch bit (ADL = 1). The ADC value is reported in the Status Byte-2 register (see Table 15). Standby Mode The MAX2112 features normal operating mode and standby mode using the I2C interface. Setting a logichigh to the STBY bit in the Control register puts the device into standby mode, during which only the 2wire-compatible bus, the crystal oscillator, the XTAL buffer, and the XTAL buffer divider are active. In all cases, register settings loaded prior to entering shutdown are saved upon transition back to active mode. Default register values are provided for the user's convenience only. It is the user's responsibility to load all the registers no sooner than 100s after the device is powered up. Layout Considerations The MAX2112 EV kit serves as a guide for PCB layout. Keep RF signal lines as short as possible to minimize losses and radiation. Use controlled impedance on all high-frequency traces. For proper operation, the exposed paddle must be soldered evenly to the board's ground plane. Use abundant vias beneath the exposed paddle for maximum heat dissipation. Use abundant ground vias between RF traces to minimize undesired coupling. Bypass each VCC pin to ground with a 1nF capacitor placed as close as possible to the pin. Maxim Integrated MAX2112 Complete, Direct-Conversion Tuner for DVB-S2 Applications Typical Application Circuit SERIAL-DATA INPUT/OUTPUT VCC + VCC_RF2 VCC 28 27 26 1 25 IDC- QDC+ QDC24 23 22 IOUT- LPF BW CONTROL 2 IDC+ 21 DC OFFSET CORRECTION MAX2112 INTERFACE LOGIC AND CONTROL VCC_RF1 VCC_BB VCC SDA SCL ADDR SERIAL-CLOCK INPUT 20 IOUT+ GND 19 3 QOUT- RF INPUT RFIN VGC GC1 18 4 QOUT+ 5 17 VCC FREQUENCY SYNTHESIZER DIV2 /DIV4 VCC_LO VCC 6 16 VCC VCC_DIG EP REFOUT VCC_VCO 15 7 VCC 14 XTAL 13 VCC_SYN 12 CPOUT 11 GNDSYN 10 GNDTUNE 9 VTUNE VCOBYP 8 Maxim Integrated BASEBAND OUTPUTS 17 MAX2112 Complete, Direct-Conversion Tuner for DVB-S2 Applications Package Information Chip Information PROCESS: BiCMOS 18 For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 28 TQFN-EP T2855+3 21-0140 90-0023 Maxim Integrated MAX2112 Complete, Direct-Conversion Tuner for DVB-S2 Applications Revision History REVISION NUMBER REVISION DATE DESCRIPTION 0 8/07 Initial release 1 12/07 Corrected errors in data sheet 2 5/10 Corrected errors in FUNCTION cells of Tables 8 and 10, corrected formula in Baseband Lowpass Filter section PAGES CHANGED -- 1-7, 9-16 11, 15 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 (c) Maxim Integrated 19 The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc. Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Maxim Integrated: MAX2112CTI+ MAX2112CTI+T MAX2112ETI+ MAX2112ETI+T