2001 Microchip Technology Inc. DS21172E-page 1
93C46B
FEATURES
• Single supply 5.0V operation
• Low power CMOS technology
- 1 mA active curr ent (typical)
- 1 µA standby current (maximum)
• 64 x 16 bit organization
• Self-timed ERASE and WRITE cycles (including
auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial interface
• Device status signal during ERASE/WRITE
cycles
• Seque nti al REA D functi on
• 1,000,000 E/W cycles ensured
• Data retention > 200 years
• 8-pin PDIP/SOIC and 8-pin TSSOP packages
• Available for the following temperature ranges:
BLOCK DIAGRAM
DESCRIPTION
The Microchip Technology Inc. 93C46B is a 1 Kbit,
low-voltage serial Electrically Erasable PROM. The
device memory is conf igured as 64 x 16 bits. Ad vanced
CMOS technology makes this device ideal for
low-power, nonvolatile memory applications. The
93C46B is available in standard 8-pin DIP, surface
mount SOIC, and TSSOP packages. The 93C46BX are
only offered in a 150 mil SOIC package.
PACKAGE TYPE
- Commercial (C): 0°C to +70°C
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
VCC
VSS
DI
CS
CLK
DO
MEMORY
ARRAY ADDRESS
DECODER
ADDRESS
COUNTER
DATA
REGISTER OUTPUT
BUFFER
MEMORY
DECODE
LOGIC
CLOCK
GENERATOR
93C46B
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
NC
VSS
CS
CLK
DI
DO
VCC
NC
NC
VSS
93C46B
NC
VCC
CS
CLK
NC
VSS
DO
DI
93C46BX
93C46B
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
NC
VSS
TSSOP
SOICSOIC
1
2
3
4
DIP
8
7
6
5
1
2
3
4
8
7
6
5
1K 5.0V Microwire® Serial EEPROM
Microwire is a registered trademark of National Semiconductor Incorporated.
93C46B
DS21172E-page 2 2001 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
1.1 Maximum Ratings*
VCC...................................................................................7.0V
All inputs and outputs w.r.t. VSS .......... .. .. -0. 6 V to VCC +1.0V
Storage temperature..................................... -65°C to +1 5 0 °C
Ambient temp. with power applied................ - 65°C to +125 °C
Soldering temperature of leads (10 seconds).............+300°C
ESD protec tio n o n all pin s................. ......................... ......4 kV
*Notice: Stresses above those listed under “Maximum ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above tho s e in dicated in th e o per ati o nal l ist i ngs of t hi s sp ecifi ca tion i s
not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
TABLE 1-1 PIN FUNCTION TABLE
Name Function
CS Chip Select
CLK S erial Data Clock
DI Serial Data Input
DO Serial Data Output
VSS Ground
NC No Connect
VCC Power Supply
TABLE 1-2 DC AND AC ELECTRICAL CHARACTERISTICS
All parameters apply over
the specified operating
ranges unless otherwise
noted
Commercial (C) VCC = +4.5V to +5.5V TAMB = 0°C to +70°C
Industrial (I) VCC = +4.5V to +5.5V TAMB = -40°C to +85°C
Automotive (E) VCC = +4.5V to +5.5V TAMB = -40°C to +125°C
Parameter Symbol Min. Max. Units Conditions
High level input voltage VIH 2.0 VCC +1 V (Note 2)
Low level input voltage VIL -0.3 0.8 V —
Low level output voltage VOL —0.4 V IOL = 2.1 mA; VCC = 4.5V
High level output voltage VOH 2.4 —VIOH = -400 µA; VCC = 4.5V
Input leakage current ILI -10 10 µA VIN = VSS to VCC
Output leakage current ILO -10 10 µA VOUT = VSS to VCC
Pin capacita nce
(all inputs/outputs) CIN, COUT —7pF
VIN/VOUT = 0 V (Notes 1 & 2)
TAMB = +25°C, FCLK = 1 MHz
Operating current ICC read —1 mA —
ICC write —1.5 mA —
Standby current ICCS —1µACS = VSS; DI = VSS
Clock frequency FCLK —2MHzVCC = 4.5V
Clock high time TCKH 250 —ns —
Clock low time TCKL 250 —ns —
Chip select setup time TCSS 50 —ns Relative to CLK
Chip select hold time TCSH 0—ns Relative to CLK
Chip select low time TCSL 250 —ns —
Data input setup time TDIS 100 —ns Relative to CLK
Data input hold time TDIH 100 —ns Relative to CLK
Data output del ay time TPD —400 ns CL = 100 pF
Data output disab le tim e TCZ —100 ns CL = 100 pF (Note 2)
Status valid time TSV —500 ns CL = 100 pF
Program cycl e time TWC —2msERASE/WRITE mode
TEC —6 ms ERAL mode
TWL —15 ms WRAL mode
Endurance —1M —cycles 25°C, VCC = 5.0V, Block Mode (Note 3)
Note 1: This parameter is tested at TAMB = 25°C and FCLK = 1 MHz.
2: This par ameter is peri odically sampled and not 100% tested.
3: This applic ati on is not tested but ensu red by chara cte riz ati on. For endurance estimates in a specifi c app lic a-
tion, please consult the Total Endurance Model which may be obtained on our website:
www.microchip.com
93C46B
2001 Microchip Technology Inc. DS21172E-page 3
2.0 PIN DESCRIPTION
2.1 Chip Select (CS)
A high level selects the device; a low level deselects
the dev ice a nd forc es it into s tandb y mod e. How ever, a
progra mmin g c yc le which is already i n pro gres s wi ll b e
completed, regardless of the Chip Select (CS) input
signal . I f C S is brou gh t low duri ng a p r ogra m c yc le, th e
device will go into standby mode as soon as the pro-
gramming cycle is completed.
CS must be low for 250 ns minimum (TCSL) between
consecutive instructions. If CS is low, the internal con-
trol logic is held in a RESET status.
2.2 Serial Clock (CLK)
The Serial Clock (CLK) is used to synchronize the com-
munication between a master device and the 93C46B.
Opcodes, addresses, and data bits are clocked in on
the pos itive edge o f CLK. Data bits are also c locked out
on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (TCKH) and
clock low time (TCKL). This gives the controlling master
freedom in preparing the opcode, address, and data.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but START condition has not been
dete cted, an y numbe r of cloc k cycles can be rec eived
by the device, without changing its status (i.e., waiting
for a START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detecting a START condition, the specified num-
ber of clock cycles (respectively low to high transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcodes, addresses,
and data bits before an instruction is executed
(Table 2-1). CLK a nd DI then become don' t c are in put s
waiting for a new START condition to be detected.
2.3 Data In (DI)
Data In (DI) is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
2.4 Data Out (DO )
Data Out (DO) is used in the READ mode to output
data synchronously with the CLK input (TPD after the
positive edge of CLK).
This pin also provides READY/BUSY status informa-
tion during ERASE and WRITE cycles. READY/BUSY
status information is available on the DO pin if CS is
brought high after being low for minimum chip select
low time (TCSL) and an ERASE or WRITE operation
has been initi ated.
The status signal is not available on DO, if CS is held
low during the entire ERASE or WRITE cycle. In this
case, DO is in the HIGH-Z mode. If status is checked
after the ERASE/ WRITE cycle, the data line will be high
to indicate the device is ready.
Note: CS must go low between consecutive
instructions.
TABLE 2-1 INSTRUCTION SET FOR 93C46B
Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
ERASE 111 A5 A4 A3 A2 A1 A0 —(RDY/BSY)9
ERAL 100 10XXXX —(RDY/BSY)9
EWDS 100 00XXXX —HIGH-Z 9
EWEN 100 11XXXX —HIGH-Z 9
READ 110 A5 A4 A3 A2 A1 A0 —D15 - D0 25
WRITE 101 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY)25
WRAL 100 0 1 X X X X D15 - D0 (RDY/BSY)25
93C46B
DS21172E-page 4 2001 Microchip Technology Inc.
3.0 FUNCTIONAL DESCRIPTION
Instr uct ion s, add res se s a nd w ri te d ata are clocked into
the DI pin on the rising edge of the clock (CLK). The DO
pin is normally held in a HIGH-Z state except when
reading data from the device, or when checking the
READY/BUSY status during a programming operation.
The READY/BUSY status can be verified during an
ERASE/WRITE operation by polling the DO pin; DO
low indicates that programming is still in progress,
while DO high indicates the device is ready . Th e DO will
enter the HIGH-Z state on the falling edge of the CS.
3.1 START Condition
The START bit is detected by the device if CS and DI
are both high with respect to the positive edge of CLK
for the first time.
Before a ST AR T condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
STAR T condi tion), withou t resultin g in any d evice oper-
ation (ERASE, ERAL, EWDS, EWEN, READ, WRITE,
and WRAL). As soon as CS is high, the device is no
longer in the standby mode.
An instruction following a START condition will only be
executed if the required amount of opcodes,
address es, and data bits for any parti cular instructio n is
clocked in.
Afte r ex ecut ion of an i nstr ucti on ( i.e ., clo ck in or ou t of
the last required address or data bit) CLK and DI
bec ome do n’t care bits until a new START condition is
detected.
3.2 Data In (DI) and Data Out (DO)
It is possible to connect the Data In (DI)and Data Out
(DO) pins together. However, with this configuration, if
A0 is a l ogi c-high level, it is possible for a “bus conflict”
to occur during the “dummy zero” that precedes the
READ operation. Under such a condition, the voltage
level seen a t DO is undefined and wi ll depen d upon th e
relative impedances of DO and the signal source driv-
ing A0. The higher the current sourcing capability of A0,
the higher the voltage at the DO pin.
3.3 Data Pro tec ti on
During power-up, all programming modes of operation
are in hib ite d un til Vc c has reac he d a l ev el g reate r tha n
3.8V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
Vcc has fa llen below 3.8V a t nominal condi tions.
The ERASE/SRITE Disable (EWDS) and ERASE/
WRITE Enable (EWEN) commands give additional
protection against accidental programming during nor-
mal operati on.
After power-up, the device is automatically in the
EWDS mod e. Therefore, an EWEN instruc tion must b e
performed before any ERASE or WRITE instruction
can be execu ted .
FIGURE 3-1: SYNCHRONOUS DATA TIMING
CS VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VOH
VOL
CLK
DI
DO
(READ)
DO
(PROGRAM)
TCSS
TDIS
TCKH TCKL
TDIH
TPD
TCSH
TPD
TCZ
STATUS VALID
TSV
TCZ
Note: AC test conditions: VIL = 0.4V, VIH = 2.4V
93C46B
2001 Microchip Technology Inc. DS21172E-page 5
3.4 ERASE
The ERASE instruction forces all data bits of the spec-
ified address to the logical “1” state. This cycle begins
on the rising clock edge of the last address bit.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical “0” indicates that program-
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
3.5 Erase All (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical “1” state. The ERAL cycle
is iden tical to the ERASE cycle, except f or th e d ifferent
opcode. The ERAL cycle is completely self-timed and
comme nces at the ri sing cloc k edge of the l ast add ress
bit. Clocking of the CLK pin is not necessary after the
device has entered the ERAL cycle.
The DO pin indicates the READY/BUSY status of the
device , if CS is brough t high a fter a mi nimum of 250 n s
low (TCSL) and before the entire ERAL cycle is
complete.
FIGURE 3-2: ERASE TIM ING
FIGURE 3-3: ERAL TIM ING
CS
CLK
DI
DO
TCSL
CHECK STATUS
111A
NAN-1 AN-2 ••• A0
TSV TCZ
BUSY READY HIGH-Z
TWC
HIGH-Z
CS
CLK
DI
DO
TCSL
CHECK STATUS
10010X
••• X
TSV TCZ
BUSY READY HIGH-Z
TEC
HIGH-Z
93C46B
DS21172E-page 6 2001 Microchip Technology Inc.
3.6 ERASE/WRITE Disable and Enable
(EWDS/EWEN)
The device powers up in the ERASE/WRITE Disable
(EWDS) state. All programming modes must be pre-
ceded by an Erase/Write Enable (EWEN) instruction.
Once the EWEN instruction is executed, programming
remains enab led until an EWDS instruc tion is execute d
or Vcc is removed from the device. To protect against
accide nta l d ata di stu r ban ce , th e EWDS instruction ca n
be used to disable all ERASE/WRITE functions and
should foll ow a ll p rogrammin g ope rations . Exe cutio n of
a READ instruction is independent of both the EWDS
and EWEN instructions.
3.7 READ
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16-bit output string. The output
data bits will toggle on the rising edge of the CLK and
are sta ble after the specifie d time delay (TPD). Se quen-
tial read is po ssible w hen CS is held hi gh. The memor y
data will automatically cycle to the next register and
output sequentially.
FIGURE 3-4: EWDS TIM ING
FIGURE 3-5: EWEN TIM ING
FIGURE 3-6: READ TIM ING
CS
CLK
DI 10
000X ••• X
TCSL
1X
CS
CLK
DI 00 1 1X
TCSL
•••
CS
CLK
DI
DO
110An ••• A0
HIGH-Z 0Dx
••• D0 Dx ••• D0 •••
Dx D0
93C46B
2001 Microchip Technology Inc. DS21172E-page 7
3.8 WRITE
The WRITE instruction is followed by 16 bits of data,
which are written into the specified address. After the
last data bit is clocked into the DI pin, the self-timed
auto- eras e and prog ram ming cy cl e begins.
The DO pin indicates the READY/BUSY status of the
device , if CS i s broug ht high a fter a mi nimum of 250 n s
low (TCSL) and be fore the enti re write c ycle is co mplete.
DO at logical “0” indicates that programming is still in
progress. DO at logical “1” indicates that the register at
the specified address has been written with the data
specified and the device is ready for another instruc-
tion.
3.9 Write All (WRAL)
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
The WRAL cycle is completely self-timed and com-
mences at the rising clock edge of the last data bit.
Clocking of the CLK pin is not necessary after the
device has entered the WRAL cycle. The WRAL com-
mand does include an automatic ERAL cycle for the
device. Therefore, the WRAL instruction does not
require an ERAL inst ruction, but the chi p must be in the
EWEN status.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low ( TCSL).
FIGURE 3-7: WRITE TIMING
FIGURE 3-8: WRAL TIM ING
CS
CLK
DI
DO
101An
••• A0 Dx ••• D0
BUSY READY HIGH-Z
HIGH-Z
Twc
TCSL
TCZ
TSV
CS
CLK
DI
DO HIGH-Z
10001X
••• XDx ••• D0
HIGH-Z BUSY READY
TWL
TCSL
TSV TCZ
93C46B
DS21172E-page 8 2001 Microchip Technology Inc.
93C46B PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
Package:
P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
SM = Plastic SOIC (208 mil Body), 8-lead
ST = TSSOP, 8-lead
Temperature
Range:
Blank = 0°C to +70°C
I=-40°C to +85°C
E=-40°C to +125°C
Device:
93C46B = 1K Microwire Serial EEPROM
93C46BT = 1K Microwire Serial EEPROM Tape and Reel
93C46BX = 1K Microwire Serial EEPROM in alternate pinout
(SN only)
93C46BXT = 1K Microwire Serial EEPROM in alternate pinout,
Tape and Reel (SN only)
93C46B — /P
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microc hip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Web Site (www.microchip.com)
93C46B
2001 Microchip Technology Inc. DS21172E-page 9
NOTES:
93C46B
DS21172E-page 10 2001 Microchip Technology Inc.
NOTES:
93C46B
2001 Microchip Technology Inc. DS21172E-page 11
“All rights reserved. Copyright © 2001, Microchip
Technology Incorporated, USA. Information contained
in this publication regarding device ap plications an d the
like is intended through suggestion only and may be
superse ded by updates . No repr esent ati on or warrant y
is given and no liabil ity is assume d by Microchip
Technology Incorporated with respect to the accuracy
or use of such information, or infringement of patents or
other intellectual property rights arising from such use
or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized
except with express written approval by Microchip. No
licenses are conveyed, implicitly or otherwise, under
any int ell ectual pro per ty righ ts. The Mi croch ip log o and
name are registered trademarks of Microchip
Technology Inc. in the U.S.A. and other countries. All
rights reserved. All ot her trademarks menti one d herein
are the property of their respective companies. No
licenses are conveyed, implicitly or otherwise, under
any intellectual property rights.”
Trademarks
The Microchip name, logo, PIC, PICmicro,
PICMASTER, PICSTART, PRO MATE, KEELOQ,
SEEVAL, MPLAB and The Emb edded Control
Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and
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Total Endurance, ICSP, In-Circuit Serial Programming,
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SelectMode and microPort are trademarks of
Microchip Technology Incorporated in the U.S.A.
Serializ ed Q ui ck Term Programming (SQTP) is a
service mark of Microchip Technology Incorporated in
the U.S.A.
All other trademarks mentioned herein are property of
their respec tiv e com p a ni es.
© 2001, M icr oc hip Technology Inco rpo rated, Printed in
the U.S.A., All Rights Reserved.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and T empe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8- bi t MC Us , KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
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Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by
update s. It i s your respo nsibilit y to en sure t hat you r app licatio n mee ts with y our sp ecifica tions. N o re presen tation or warra nty is given and n o liability is
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DS21172E-page 12 2001 Microchip Technology Inc.
All rights reserved. © 2001 Microchip Technology Incorporated. Printed in the USA. 3/01 Printed on recycled paper.
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91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30 -90-79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann Ring 125
D-81739 Munich, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Germany
Analog Product Sales
Lochhamer Strasse 13
D-82152 Martinsried, Germany
Tel: 49-89-895650-0 Fax: 49-89-895650-22
Italy
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berksh ire, E ngla nd RG 41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
01/30/01
WORLDWIDE SALES AND SERVICE
