HN62W4416NFB-15 - Hitachi Semiconductor

Preliminary: This document contains information on a product. Specifications and information contained

herein are subject to change without notice.

HN62W4416N Series

1048576-word × 16-bit/2097152-word × 8-bit CMOS Mask

Programmable ROM

ADE-203-468 (Z)

Preliminary

Rev. 0.0

Nov. 20, 1995

Description

The HN62W4416N is a 16-Mbit CMOS mask-Programmable ROM organized either as 1048576 words

by 16 bits or 2097152 words by 8 bits. Realizing low power consumption, this memory is allowed for

battery operation. And a high speed access of 150 ns (max) is the most suitable to the system using a

high speed micro-computer by 16 bits.

Feature

• Low voltage operation Mask ROM

Single 3.3 V supply

• High speed

Normal access time: 150 ns (max)

Page access time: 50 ns (max)

• Low power

Active: 252 mW (max)

Standby: 108 µW (max)

• Byte-wide or word-wide data organization (Switched by BHE terminal)

• 4 word page access on word-wide mode

• 8 byte page access on byte-wide mode

• Three-state data output for or-tying

• Directly LVTTL compatible

All inputs and outputs

Ordering Information

Type No. Access time Package

HN62W4416NP-15 150 ns 600 mil 42-pin plastic DIP (DP-42)

HN62W4416NFB-15 150 ns 600 mil 44-pin plastic SOP (FP-44D)

HN62W4416NTT-15 150 ns 400 mil 44-pin plastic TSOP II (TTP-44D)

HN62W4416N Series

Pin Arrangement

HN62W4416NP Series HN62W4416NFB Series

HN62W4416NTT Series

A18 A19

A17 A8

A7 A9

A6 A10

A5 A11

A4 A12

A3 A13

A2 A14

A1 A15

A0 A16

CE BHE

VSS VSS

OE D15/A-1

D0 D7

D8 D14

D1 D6

D9 D13

D2 D5

D10 D12

D3 D4

D11 VDD

(Top View) (Top View)

A18 A19

A17 A8

A7 A9

A6 A10

A5 A11

A4 A12

A3 A13

A2 A14

A1 A15

A0 A16

CE BHE

VSS VSS

OE D15/A-1

D0 D7

D8 D14

D1 D6

D9 D13

D2 D5

D10 D12

D3 D4

D11 VDD

NC NC

Pin Description

Pin name Function

A2 to A19 Address inputs

D0 to D15 Data outputs

BHE 8/16 bit (byte/word) mode switch

A-1, A0 , A1 Page address inputs

BHE 8/16 bit (byte/word) mode switch

CE Chip enable

OE Output enable

NC No connection

VDD Power supply

VSS Ground

HN62W4416N Series

Block Diagram

Address

Buffer

X Decoder

Y Decoder

Memory Array

Y Gates

Hex/Byte

3-state output

buffer

A19

(A-1)*1

BHE

D0 D15/(D7)

BHE = VIH : 16-bit (D15 to D0)

BHE = VIL : 8-bit (D7 to D0)

Note : 1. A-1 is least significant address.

When BHE is 'low', D14 to D8 goes the high impedance state, and D15 should be A-1.

Page Decoder

Mode Selection

Data output Address input

Mode CE OE BHE D15/A-1 D0-D7 D8-D15 LSB MSB

Standby H ×*1 ××High-Z*2 High-Z — —

Output disable L H ××High-Z High-Z — —

Read (16-bit) L L H Dout D0 to D7 D8 to D15 A0 A19

Read (8-bit) L L L L D0 to D7 High-Z A-1 A19

Read (8-bit) L L L H D8 to D15 High-Z A-1 A19

Notes: 1. ×: Don’t care.

2. High-Z: High impedance

HN62W4416N Series

Absolute Maximum Ratings

Parameter Symbol Value Unit

Supply voltage*1 VDD –0.3 to +5.5 V

All input and output voltage*1 Vin, Vout –0.3 to VDD + 0.3 V

Operating temperature range Topr 0 to +70 °C

Storage temperature range Tstg –55 to +125 °C

Temperature under bias Tbias –20 to +85 °C

Note: 1. With respect to VSS.

Recommended DC Operating Conditions (Ta = 0 to + 70°C)

Parameter Symbol Min Typ Max Unit

Supply voltage VDD 3.0 3.3 3.6 V

VSS 000V

Input voltage VIH 2.2 — VDD + 0.3 V

VIL –0.3 — 0.8 V

DC Characteristics (VDD = 3.3 V ± 0.3 V, VSS = 0 V, Ta = 0 to + 70°C)

Parameter Symbol Min Max Unit Test conditions

Supply current Active IDD —70mAV

DD = 3.6 V, IDOUT = 0 mA, tRC = 150 ns

Standby ISB1 —30µAV

DD = 3.6 V, CE ≥ VDD – 0.2 V

Standby ISB2 — 3 mA VDD = 3.6 V, CE ≥ 2.2 V

Input leakage current |IIL|—10µA Vin = 0 to VDD

Output leakage current |IOL|—10µACE = 2.2 V, Vout = 0 to VDD

Output voltage VOH 2.4 — V IOH = –2.0 mA

VOL — 0.4 V IOL = 2.0 mA

Capacitance (VDD = 3.3 V ± 0.3 V, VSS = 0 V, Ta = 25°C, Vin = 0 V, f = 1MHz)

Parameter Symbol Min Max Unit

Input capacitance*1 Cin — 10 pF

Output capacitance*1 Cout — 15 pF

Note: 1. This parameter is sampled and not 100% tested. D15/A-1 pin is output.

HN62W4416N Series

AC Characteristics (VDD = 3.3 V ± 0.3 V, VSS = 0 V, Ta = 0 to + 70°C)

• Output load: 1TTL + CL = 100 pF (including jig)

• Input pulse level: 0.4 to 2.4 V

• Input and output timing reference level: 1.4 V

• Input rise and fall time: 5 ns

HN62W4416N-15

Parameter Symbol Min Max Unit Note

Read cycle time tRC 150 — ns

Page read cycle time tPC 50 — ns

Address access time tAA — 150 ns

Page address access time tPA —50ns

CE access time tACE — 150 ns

OE access time tOE —50ns

BHE access time tBHE — 150 ns

Output hold time from address change tDHA 5—ns

Output hold time from CE tDHC 0—ns

Output hold time from OE tDHO 0—ns

Output hold time from BHE tDHB 0—ns

CE to output in high-Z tCHZ —50ns1

OE to output in high-Z tOHZ —50ns1

BHE to output in high-Z tBHZ —30ns1

CE to output in low-Z tCLZ 5—ns

OE to output in low-Z tOLZ 5—ns

BHE to output in low-Z tBLZ 5—ns

Note: 1. tCHZ, tOHZ and tBHZ are defined as the time at which the output achieves the open circuit

conditions and are not referred to output voltage levels.

HN62W4416N Series

Timing Waveforms

Word Mode (BHE = ‘VIH’) or Byte Mode (BHE = ‘VIL’)

Address

Dout

Notes : 1. tDHA, tDHC, tDHO : Determined by faster.

2. tAA, tACE, tOE : Determined by slower.

3. tCLZ, tOLZ : Determined by slower.

High-Z High-Z

Valid data

tOLZ

tOE

tCLZ

tACE

tAA

tRC

tDHA

tCHZ

tDHC

tDHO

tOHZ

Word Mode, Byte Mode Switch

A-1

BHE

D7 to D0

D15 to D8

Notes : 1.

High-Z

Valid data

tAA

High-Z High-Z

tDHA

tBHE

tBLZ

tDHB

tBHZ

Valid data

CE and OE are enable, A19 to A0 are valid.

D15/A-1 pin is in the output state when BHE is high, CE and OE are enable.

Therefore, the input signals of opposite phase to the output must not be applied to them.

HN62W4416N Series

Page mode

A2 to A19

A0, A1,

(A-1)

Dout

Notes : 1. Page address is determined as below.

Word mode (BHE = 'High') : A0, A1.

Byte mode (BHE = 'Low') : A-1, A0, A1

2. CE and OE are eneble.

Valid data

tAA

Valid

data Valid

data

tDHA tDHA tDHA tDHA

tPA tPA tPA

tRC tPC

tPC tPC

Power Up Sequence

VCC

Dout

Note : 1. This device is used ATD (Address Transition Detecter). Therefore, transfer either

CE or address (A19 to A2) after power up to 3.0 V.

Valid data

tAA

0 V

3.0 V

Address Valid data

tACE

tP > 0 µs

HN62W4416N Series

Package Dimensions

HN62W4416P Series (DP-42) Unit: mm

2.54 Min 5.06 Max

0.25 + 0.26

– 0.05

2.54 ± 0.25 0.48 ± 0.10 0° – 15°

15.24

0.51 Min

52.80

53.80 Max

13.40

15.0 Max

1.20

121

1.3 Max

HN62W4416FB Series (FP-44D) Unit: mm

0.12 M

1.27

28.50

28.70 Max

44 23

221 16.04 ± 0.30

1.72

0 – 10°

0.80 ± 0.20

3.00 Max

0.19 ± 0.10 12.60

0.40 ± 0.10

0.17 ± 0.05

1.02 Max

0.10

HN62W4416N Series

Package Dimensions (cont)

HN62W4416TT Series (TTP-44D) Unit: mm

0.13 M

0.80

44 23

122

18.41

18.81 Max

0.30 ± 0.10

1.20 Max

10.16

0.17 ± 0.05

11.76 ± 0.20

0 – 5°

1.105 Max

0.50 ± 0.10

0.80

0.10

0.13 +0.03

–0.05