1. General description
The 74LVC162245A; 74LVCH162245A are 16-bit transceivers with non-inverting 3-state
bus compatible outputs in both send and receive directions. Two send/receive (nDIR)
inputs control direction, and two output enable (nOE) inputs make cascading easy. The
nOE inputs control the outputs so that the buses are effectively isolated. This device can
be used as two 8-bit transceivers or one 16-bit transceiver.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V and 5 V applications.
The 74LVCH162245A bus hold on data inputs eliminates the need for external pull-up
resistors to hold unused inputs.
Both HIGH and LOW ou tp ut stages includ e 30 series termination resistors to reduce
line noise.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum noise an d ground
bounce
Direct interface with TTL levels
Integrated 30 termination resistors
High-impedance when VCC =0V
All data inputs have bus hold (74LVCH162245A only)
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 Cto+85C and from 40 Cto+125C
74LVC162245A; 74LVCH162245A
16-bit transceiver with direction pin, 30 series termination
resistors; 5 V tolerant input/output; 3-state
Rev. 6 — 23 November 2011 Product data sheet
74LVC_LVCH162245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 23 November 2011 2 of 16
NXP Semiconductors 74LVC162245A; 74LVCH162245A
16-bit transceiver with direction pin; 30 resistors; 3-state
3. Ordering information
4. Functional diagram
Tabl e 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC162245ADL 40 Cto+125C SSOP48 plastic shrink small outline package; 48 leads;
body width 7.5 mm SOT370-1
74LVCH162245ADL
74LVC162245ADGG 40 Cto+125C TSSOP48 plastic thin shrink small outline package;
48 leads; body width 6.1 mm SOT362-1
74LVCH162245ADGG
Fig 1. Logic symbol
47
1
1DIR
2
48
1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
46
3
44
5
43
6
41
8
40
9
38
11
37
1A0
1A1
1A2
1A3
1A4
1A5
1A6
1A7 12
1OE 36
24
2DIR
13
25
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
35
14
33
16
32
17
30
19
29
20
27
22
26
2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7 23
2OE
mna708
74LVC_LVCH162245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 23 November 2011 3 of 16
NXP Semiconductors 74LVC162245A; 74LVCH162245A
16-bit transceiver with direction pin; 30 resistors; 3-state
Fig 2. IEC logic symbol
G3
G6
3EN1[BA]
6EN4[BA]
3EN2[AB]
6EN5[AB]
47
36
46
35
44
33
43
32
41
30
40
29
38
27
37
26
2
13
3
14
5
16
6
17
8
19
9
20
11
22
12
23
1A0
2A1
2A0
2A2
2A3
2A4
2A5
2A6
2A7
2B1
2B2
2B3
2B4
2B5
2B6
2B7
1OE
1DIR
mna709
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1B0
2B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
5
4
2
1
25
24
48
1
2OE
2DIR
Fig 3. Bus hold circuit
to internal circuit
mna705
VCC
data input
74LVC_LVCH162245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 23 November 2011 4 of 16
NXP Semiconductors 74LVC162245A; 74LVCH162245A
16-bit transceiver with direction pin; 30 resistors; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 4. Pin configuration SSOP48 and TSSOP48
74LVC162245A
74LVCH162245A
001aaa156
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1B0
1B1
GND
1A0
1A1
GND
1DIR 1OE
1B2
1B3
V
CC
1B4
1B5
GND
1B6
1B7
2B0
2B1
GND
2B2
2B3
V
CC
2B4
2B5
GND
2B6
2B7
2DIR
1A2
1A3
V
CC
1A4
1A5
GND
1A6
1A7
2A0
2A1
GND
2A2
2A3
V
CC
2A4
2A5
GND
2A6
2A7
2OE
Table 2. Pin description
Name Pin Description
1DIR 1 direction control input
2DIR 24 direction control input
GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0 V)
VCC 7, 18, 31, 42 supply voltage
1OE 48 output enable input (active LOW)
2OE 25 output enable input (active LOW)
1A[0:7] 47, 46, 44, 43, 41, 40, 38, 37 data input/output
2A[0:7] 36, 35, 33, 32, 30, 29, 27, 26 data input/output
1B[0:7] 2, 3, 5, 6, 8, 9, 11, 12 data input/output
2B[0:7] 13, 14, 16, 17, 19, 20, 22, 23 data input/output
74LVC_LVCH162245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 23 November 2011 5 of 16
NXP Semiconductors 74LVC162245A; 74LVCH162245A
16-bit transceiver with direction pin; 30 resistors; 3-state
6. Functional description
[1] H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high-impedance OFF-state
7. Limiting values
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] Above 60 C the value of Ptot derates linearly with 5.5 mW/K.
Table 3. Function table[1]
Input Output
nOE nDIR nAn nBn
L L A = B inputs
L H inputs B = A
HXZZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI<0V 50 - mA
VIinput voltage [1] 0.5 +6.5 V
IOK output clamping current VO>V
CC or VO<0V - 50 mA
VOoutput voltage output HIGH or LOW state [2] 0.5 VCC +0.5 V
output 3-state [2] 0.5 +6.5 V
IOoutput current VO=0V toV
CC -50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb =40 C to +125 C[3] -500mW
74LVC_LVCH162245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 23 November 2011 6 of 16
NXP Semiconductors 74LVC162245A; 74LVCH162245A
16-bit transceiver with direction pin; 30 resistors; 3-state
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 1.65 - 3.6 V
functional 1.2 - - V
VIinput voltage 0 - 5.5 V
VOoutput voltage output HIGH or LOW state 0 - VCC V
output 3-state 0 - 5.5 V
Tamb ambient temperature in free air 40 - +125 C
t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V
VCC = 2.7 V to 3.6 V 0 - 10 ns/V
Table 6. Static characteristics
At recommended operating conditions. V oltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
VIH HIGH-level
input
voltage
VCC = 1.2 V 1.08 - - 1.08 - V
VCC = 1.65 V to 1.95 V 0.65 VCC --0.65 VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level
input
voltage
VCC = 1.2 V - - 0.12 - 0.12 V
VCC = 1.65 V to 1.95 V - - 0.35 VCC - 0.35 VCC V
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VOH HIGH-level
output
voltage
VI=V
IH or VIL
IO=100 A;
VCC =1.65Vto3.6V VCC 0.2 VCC -V
CC 0.3 - V
IO=2mA; V
CC = 1.65 V 1.2 - - 1.05 - V
IO=4mA; V
CC = 2.3 V 1.8 - - 1.65 - V
IO=6mA; V
CC = 2.7 V 2.2 - - 2.05 - V
IO=12 mA; VCC = 3.0 V 2.2 - - 2.0 - V
VOL LOW-level
output
voltage
VI=V
IH or VIL
IO=100A;
VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V
IO=2mA; V
CC = 1.65 V - - 0.45 - 0.65 V
IO=4mA; V
CC = 2.3 V - - 0.6 - 0.8 V
IO=6mA; V
CC = 2.7 V - - 0.4 - 0.6 V
IO=12mA; V
CC = 3.0 V - - 0.55 - 0.8 V
IIinput
leakage
current
VCC = 3.6 V;
VI=5.5VorGND [2] -0.1 5-20 A
74LVC_LVCH162245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 23 November 2011 7 of 16
NXP Semiconductors 74LVC162245A; 74LVCH162245A
16-bit transceiver with direction pin; 30 resistors; 3-state
[1] All typical values are measured at VCC = 3.3 V and Tamb =25C.
[2] The bus hold circuit is switched off when VI>V
CC allowing 5.5 V on the input terminal.
[3] For I/O ports the parameter IOZ includes the input leakage current.
[4] Valid for data inputs only. Control inputs do not have a bus hold circuit.
[5] The specified sustaining current at the data input holds the input below the specified VI level.
[6] The specified overdrive current at the data input forces the data input to the opposite logic input state.
IOZ OFF-state
output
current
VI=V
IH or VIL; VCC = 3.6 V;
VO= 5.5 V or GND; [2][3] -0.1 5-20 A
IOFF power-off
leakage
current
VCC = 0 V; VIor VO= 5.5 V - 0.1 10 - 20 A
ICC supply
current VCC = 3.6 V;
VI=V
CC or GND; IO=0A -0.120 - 80A
ICC additional
supply
current
per input pin;
VCC = 2.7 V to 3.6 V ;
VI=V
CC 0.6 V; IO=0A
-5500 -5000A
CIinput
capacitance VCC = 0 V to 3.6 V;
VI=GNDtoV
CC
-5.0- - -pF
CI/O input/output
capacitance VCC = 0 V to 3.6 V;
VI=GNDtoV
CC
- 10.0 - - - pF
IBHL bus hold
LOW
current
VCC = 1.65 V; VI = 0.58 V [4][5] 10 - - 10 - A
VCC = 2.3 V; VI = 0.7 V 30 - - 25 - A
VCC = 3.0 V; VI = 0.8 V 75 - - 60 - A
IBHH bus hold
HIGH
current
VCC = 1.65 V; VI = 1.07 V [4][5] 10 - - 10 - A
VCC = 2.3 V; VI = 1.7 V 30 - - 25 - A
VCC = 3.0 V; VI = 2.0 V 75 - - 60 - A
IBHLO bus hold
LOW
overdrive
current
VCC = 1.95 V [4][6] 200 - - 200 - A
VCC = 2.7 V 300 - - 300 - A
VCC = 3.6 V 500 - - 500 - A
IBHHO bus hold
HIGH
overdrive
current
VCC = 1.95 V [4][6] 200 - - 200 - A
VCC = 2.7 V 300 - - 300 - A
VCC = 3.6 V 500 - - 500 - A
Table 6. Static characteristics …continued
At recommended operating conditions. V oltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
74LVC_LVCH162245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 23 November 2011 8 of 16
NXP Semiconductors 74LVC162245A; 74LVCH162245A
16-bit transceiver with direction pin; 30 resistors; 3-state
10. Dynamic characteristics
[1] Typical values are measured at Tamb =25C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3] CPD is used to determine the dynamic power dissipation (PDin W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz; fo= output frequency in MHz
CL= output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CLVCC2fo) = sum of the outputs
Table 7. Dynamic characteristics
Vo ltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.
Symbol Parameter Conditions Tamb =40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
tpd propagation
delay nAn to nBn; nBn to nAn; see Figure 5 [2]
VCC = 1.2 V - 12 - - - ns
VCC = 1.65 V to 1.95 V 1.5 6.6 16.0 1.5 18.4 ns
VCC = 2.3 V to 2.7 V 1.0 3.5 7.8 1.0 9.1 ns
VCC = 2.7 V 1.0 3.5 6.7 1.0 9.5 ns
VCC = 3.0 V to 3.6 V 1.0 2.9 5.7 1.0 8.5 ns
ten enable time nOE to nAn, nBn; see Figure 6 [2]
VCC = 1.2 V - 18 - - - ns
VCC = 1.65 V to 1.95 V 2.0 7.7 17.2 2.0 19.8 ns
VCC = 2.3 V to 2.7 V 1.5 4.3 9.4 1.5 10.9 ns
VCC = 2.7 V 1.5 4.6 8.5 1.5 9.5 ns
VCC = 3.0 V to 3.6 V 1.0 3.5 7.5 1.0 7.5 ns
tdis disable time nOE to nAn, nBn; see Figure 6 [2]
VCC = 1.2 V - 10 - - - ns
VCC = 1.65 V to 1.95 V 2.8 4.6 11.0 2.8 12.7 ns
VCC = 2.3 V to 2.7 V 1.0 2.6 6.3 1.0 7.3 ns
VCC = 2.7 V 1.5 3.4 7.5 1.5 11.0 ns
VCC = 3.0 V to 3.6 V 1.5 3.2 6.5 1.5 8.5 ns
CPD power
dissipation
capacitance
per input; VI=GNDtoV
CC [3]
VCC = 1.65 V to 1.95 V - 10.4 - - - pF
VCC = 2.3 V to 2.7 V - 14.0 - - - pF
VCC = 3.0 V to 3.6 V - 17.2 - - - pF
74LVC_LVCH162245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 23 November 2011 9 of 16
NXP Semiconductors 74LVC162245A; 74LVCH162245A
16-bit transceiver with direction pin; 30 resistors; 3-state
11. Waveforms
VM= 1.5 V at VCC 2.7 V.
VM=0.5 VCC at VCC <2.7V.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5. The input (nAn, nBn) to outputs (nBn, nAn) propagation delays
mna477
nAn, nBn
input
nBn, nAn
output
tPHL tPLH
GND
VI
VM
VM
VOH
VOL
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. 3-state enable and disable times
mna362
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
nOE input
VI
VOL
VOH
VCC
VM
GND
GND
tPZL
tPZH
VM
VM
Table 8. Measurement points
Supply voltage VMInput
VCC VItr=t
fVXVY
1.2 V 0.5 VCC VCC 2.5 ns VOL + 0.15 V VOH 0.15 V
1.65 V to 1.95 V 0.5 VCC VCC 2.5 ns VOL + 0.15 V VOH 0.15 V
2.3 V to 2.7 V 0.5 VCC VCC 2.5 ns VOL + 0.15 V VOH 0.15 V
2.7V 1.5V 2.7V 2.5 ns VOL + 0.3 V VOH 0.3 V
3.0V to 3.6V 1.5V 2.7V 2.5 ns VOL + 0.3 V VOH 0.3 V
74LVC_LVCH162245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 23 November 2011 10 of 16
NXP Semiconductors 74LVC162245A; 74LVCH162245A
16-bit transceiver with direction pin; 30 resistors; 3-state
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 7. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aae331
V
EXT
V
CC
V
I
V
O
DUT
CL
RT
RL
RL
G
Table 9. Test data
Supply voltage Input Load VEXT
VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH
1.2 V VCC 2 ns 30 pF 1 kopen 2 VCC GND
1.65 V to 1.95 V VCC 2 ns 30 pF 1 kopen 2 VCC GND
2.3 V to 2.7 V VCC 2 ns 30 pF 500 open 2 VCC GND
2.7V 2.7V 2.5 ns 50 pF 500 open 2 VCC GND
3.0Vto3.6V 2.7V 2.5 ns 50 pF 500 open 2 VCC GND
74LVC_LVCH162245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 23 November 2011 11 of 16
NXP Semiconductors 74LVC162245A; 74LVCH162245A
16-bit transceiver with direction pin; 30 resistors; 3-state
12. Package outline
Fig 8. Package outline SOT370-1 (SSOP48)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.4
0.2 2.35
2.20 0.25 0.3
0.2 0.22
0.13 16.00
15.75 7.6
7.4 0.635 1.4 0.25
10.4
10.1 1.0
0.6 1.2
1.0 0.85
0.40 8
0
o
o
0.18 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT370-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
48 25
MO-118
24
1
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
pin 1 index
0 5 10 mm
scale
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1
A
max.
2.8
74LVC_LVCH162245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 23 November 2011 12 of 16
NXP Semiconductors 74LVC162245A; 74LVCH162245A
16-bit transceiver with direction pin; 30 resistors; 3-state
Fig 9. Package outline SOT362-1 (TSSOP48)
UNIT A1A2A3bpcD
(1) E(2) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.2
0.1 8
0
o
o
0.1
DIMENSIONS (mm are the original dimensions).
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
SOT362-1 99-12-27
03-02-19
wM
θ
A
A1
A2
D
Lp
Q
detail X
E
Z
e
c
L
X
(A )
3
0.25
124
48 25
y
pin 1 index
b
H
1.05
0.85 0.28
0.17 0.2
0.1 12.6
12.4 6.2
6.0 0.5 1 0.25
8.3
7.9 0.50
0.35 0.8
0.4
0.08
0.8
0.4
p
EvMA
A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1
A
max.
1.2
0
2.5
5 mm
scale
MO-153
74LVC_LVCH162245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 23 November 2011 13 of 16
NXP Semiconductors 74LVC162245A; 74LVCH162245A
16-bit transceiver with direction pin; 30 resistors; 3-state
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CDM Charged Device Mo del
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change
notice Supersedes
74LVCH1 62245A v.6 20111123 Product data sheet - 74LVC_LVCH162245A v.5
Modifications: •The format of thi s doc ument has been redesigned to com pl y wi th the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Table 5, Table 6, Table 7 and Table 9: values added for lower voltage ranges.
74LVC_ LVCH162245 A v.5 20031208 Product specification - 74LVC_H162245A v. 4
74LVC_ H162245A v.4 19980217 Product speci fication - 74LVC162 245A_74LVC H162245A v. 3
74LVC162245A_
74LVCH1 62245A v.3 19980217 Product specifica tion - 74LVC162245 A v.2
74LVC1 62245A v.2 19970801 Product specification - 74LVC162245A v.1
74LVC162245A v.1 - - - -
74LVC_LVCH162245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 23 November 2011 14 of 16
NXP Semiconductors 74LVC162245A; 74LVCH162245A
16-bit transceiver with direction pin; 30 resistors; 3-state
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device (s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short dat a sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specificatio n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyon d those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect , incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulati ve liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descripti ons, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suit able for use in life support, life-crit ical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for il lustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associate d with t heir
applications and products.
NXP Semiconductors does not accept any liabil ity related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress rating s only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Not hing in this document may be interpret ed or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyri ghts, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from competent authorities.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contain s data from the objective specification for product develop ment.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74LVC_LVCH162245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 23 November 2011 15 of 16
NXP Semiconductors 74LVC162245A; 74LVCH162245A
16-bit transceiver with direction pin; 30 resistors; 3-state
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors prod uct is automotive qualified,
the product is not suitable for automotive use. It i s neit her qualif ied nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever cust omer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
15.4 Trademarks
Notice: All refe renced brands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74LVC162245A; 74LVCH162245A
16-bit transceiver with direction pin; 30 resistors; 3-state
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 23 November 2011
Document identifier: 74LVC_LVCH162245A
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 5
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16 Contact information. . . . . . . . . . . . . . . . . . . . . 15
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
