LMH0394
LMH0394 3G HD/SD SDI Low Power Extended Reach Adaptive Cable Equalizer
Literature Number: SNLS312J
LMH0394
August 9, 2011
3G HD/SD SDI Low Power Extended Reach Adaptive Cable
Equalizer
General Description
The LMH0394 3 Gbps HD/SD SDI Low Power Extended
Reach Adaptive Cable Equalizer is designed to equalize data
transmitted over cable (or any media with similar dispersive
loss characteristics). The equalizer operates over a wide
range of data rates from 125 Mbps to 2.97 Gbps and supports
SMPTE 424M, SMPTE 292M, SMPTE 344M, SMPTE 259M,
and DVB-ASI standards.
The LMH0394 provides extended cable reach with improved
immunity to crosstalk and ultra low power consumption. The
equalizer includes active sensing circuitry that ensures robust
performance and enhanced immunity to variations in the input
signal launch amplitude. The output driver offers pro-
grammable de-emphasis for up to 40” of FR4 trace losses.
The LMH0394 includes power management to further reduce
power consumption when no input signal is present.
The LMH0394 supports two modes of operation. In pin mode,
the LMH0394 operates with control pins to set its operating
state, and is footprint compatible with the LMH0384,
LMH0344, and legacy SDI equalizers. In SPI mode, an op-
tional SPI serial interface can be used to access and configure
multiple LMH0394 devices in a daisy-chain configuration.
This allows programming the output common mode voltage
and swing, output de-emphasis level, input launch amplitude,
and power management settings, as well as access to a cable
length indicator and all pin mode features.
Features
■SMPTE 424M, SMPTE 292M, SMPTE 344M, SMPTE
259M, and DVB-ASI compliant
■Equalized cable lengths (Belden 1694A): 200m at 2.97
Gbps, 220m at 1.485 Gbps, and 400m at 270 Mbps
■Ultra low power consumption: 115 mW (normal operation)
■Power save mode with auto sleep control (17 mW typical
power consumption in power save mode)
■Designed for crosstalk immunity
■Output de-emphasis to compensate for FR4 board trace
losses
■Digital and analog programmable MUTEREF threshold
■Optional SPI register access
■Input data rates: 125 Mbps to 2.97 Gbps
■Internally terminated 100Ω LVDS outputs with
programmable output common mode voltage and swing
■Programmable launch amplitude optimization
■Cable length indicator
■Single 2.5V supply operation
■16-pin LLP package
■Industrial temperature range: −40°C to +85°C
■Footprint compatible with the LMH0384 and also the
LMH0344, LMH0044, and LMH0074 in pin mode.
Applications
■SMPTE 424M, SMPTE 292M, SMPTE 344M, and SMPTE
259M serial digital interfaces
■Broadcast Video routers, switchers, and distribution
amplifiers
Typical Application (Pin Mode)
30101501
© 2011 National Semiconductor Corporation 301015 www.national.com
LMH0394 3G HD/SD SDI Low Power Extended Reach Adaptive Cable Equalizer
Connection Diagrams
Pin Mode (non-SPI) / SPI_EN = GND / LMH0344 Compatible
30101503
SPI Mode / SPI_EN = VCC
30101507
The exposed die attach pad is a negative electrical terminal for this device. It should be connected to the negative power supply voltage.
16-Pin LLP
Order Number LMH0394SQ
NS Package Number SQB16A
Ordering Information
Part Number Package Quantity
LMH0394SQ 16-Pin LLP, 4.0 x 4.0 x 0.8 mm, 0.65 mm pitch Reel of 1000
LMH0394SQE 16-Pin LLP, 4.0 x 4.0 x 0.8 mm, 0.65 mm pitch Reel of 250
LMH0394SQX 16-Pin LLP, 4.0 x 4.0 x 0.8 mm, 0.65 mm pitch Reel of 4500
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LMH0394
Pin Descriptions – Pin Mode (non-SPI) / SPI_EN = GND / LMH0344 Compatible
Pin Name I/O, Type Description
1 VEE Ground Negative power supply (ground).
2 SDI I, SDI Serial data true input.
3 SDI I, SDI Serial data complement input.
4 SPI_EN I, LVCMOS SPI register access enable. This pin has an internal pulldown.
H = SPI register access mode.
L = Pin mode.
5 AEC+ I/O, Analog AEC loop filter external capacitor (1µF) positive connection (capacitor is optional).
6 AEC- I/O, Analog AEC loop filter external capacitor (1µF) negative connection (capacitor is optional).
7 BYPASS I, LVCMOS Equalization bypass. This pin has an internal pulldown.
H = Equalization is bypassed (no equalization occurs).
L = Normal operation.
8 MUTEREF I, Analog Mute reference input. Sets the threshold for CD and (with CD tied to MUTE)
determines the maximum cable to be equalized before muting. MUTEREF may be
either unconnected or connected to ground for normal CD operation.
9 VEE I, LVCMOS Connect this pin to ground or drive it logic low.
10 SDO O, LVDS Serial data complement output.
11 SDO O, LVDS Serial data true output.
12 AUTO SLEEP I, LVCMOS Auto Sleep. AUTO SLEEP has precedence over MUTE and BYPASS. This pin has
an internal pullup.
H = Device will power down when no input is detected.
L = Normal operation (device will not enter auto power down).
13 VCC Power Positive power supply (+2.5V).
14 MUTE I, LVCMOS Output mute. CD may be tied to this pin to inhibit the output when no input signal is
present. MUTE has precedence over BYPASS. This pin has an internal pulldown.
H = Outputs forced to a muted state.
L = Outputs enabled.
15 CD O, LVCMOS Carrier detect.
H = No input signal detected.
L = Input signal detected.
16 VCC Power Positive power supply (+2.5V).
DAP VEE Ground Connect exposed DAP to negative power supply (ground).
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LMH0394
Pin Descriptions – SPI Mode / SPI_EN = VCC
Pin Name I/O, Type Description
1 VEE Ground Negative power supply (ground).
2 SDI I, SDI Serial data true input.
3 SDI I, SDI Serial data complement input.
4 SPI_EN I, LVCMOS SPI register access enable. This pin has an internal pulldown.
H = SPI register access mode.
L = Pin mode.
5 AEC+ I/O, Analog AEC loop filter external capacitor (1µF) positive connection (capacitor is optional).
6 AEC- I/O, Analog AEC loop filter external capacitor (1µF) negative connection (capacitor is optional).
7 CD O, LVCMOS Carrier detect.
H = No input signal detected.
L = Input signal detected.
8 MUTEREF I, Analog Mute reference input. Sets the threshold for CD and (with CD tied to MUTE)
determines the maximum cable to be equalized before muting. MUTEREF may be
either unconnected or connected to ground for normal CD operation.
9 SS (SPI) I, LVCMOS SPI slave select. This pin has an internal pullup.
10 SDO O, LVDS Serial data complement output.
11 SDO O, LVDS Serial data true output.
12 MISO (SPI) O, LVCMOS SPI Master Input / Slave Output. LMH0394 control data transmit.
13 VCC Power Positive power supply (+2.5V).
14 SCK (SPI) I, LVCMOS SPI serial clock input.
15 MOSI (SPI) I, LVCMOS SPI Master Output / Slave Input. LMH0394 control data receive. This pin has an
internal pulldown.
16 VCC Power Positive power supply (+2.5V).
DAP VEE Ground Connect exposed DAP to negative power supply (ground).
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LMH0394
Absolute Maximum Ratings (Note 1)
Supply Voltage 3.1V
Input Voltage (all inputs) −0.3V to VCC+0.3V
Storage Temperature Range −65°C to +150°C
Junction Temperature +125°C
Package Thermal Resistance
θJA 16-pin LLP
θJC 16-pin LLP
+40°C/W
+6°C/W
ESD Rating (HBM) ≥±6 kV
ESD Rating (MM) ≥±300V
ESD Rating (CDM) ≥±2 kV
Recommended Operating
Conditions
Supply Voltage (VCC – VEE) 2.5V ±5%
Input Coupling Capacitance 1.0 µF
Operating Free Air Temperature (TA) −40°C to +85°C
DC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 2, Note 3).
Symbol Parameter Conditions Reference Min Typ Max Units
VIH Input Voltage High Level Logic Inputs 1.7 VCC V
VIL Input Voltage Low Level VEE 0.7 V
VSDI Input Voltage Swing 0m cable length, (Note 5) SDI, SDI 720 800 880 mVP−P
VCMIN Input Common Mode Voltage 1.65 V
VSSP-P Differential Output Voltage, P-P 100Ω load, default register
settings (Note 6), Figure 1
SDO, SDO 500 700 900 mVP-P
VOD Differential Output Voltage 250 350 450 mV
ΔVOD Change in Magnitude of VOD for
Complimentary Output States 50 mV
VOS Offset Voltage 1.1 1.2 1.35 V
ΔVOS Change in Magnitude of VOS for
Complimentary Output States 50 mV
IOS Output Short Circuit Current 30 mA
MUTEREF DC Voltage (floating) MUTEREF 1.3 V
MUTEREF Range 0.8 V
VOH Output Voltage High Level IOH = -2 mA CD, MISO 2.0 V
VOL Output Voltage Low Level IOL = +2 mA 0.2 V
ICC Supply Current Normal operation, (Note 7) 45 65 mA
Power save mode 7 10 mA
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LMH0394
AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).
Symbol Parameter Conditions Reference Min Typ Max Units
BRMIN Minimum Input Data Rate SDI, SDI 125 Mbps
BRMAX Maximum Input Data Rate 2970 Mbps
Jitter for Various Cable Lengths 2.97 Gbps, Belden 1694A,
0-100 meters (Note 8)
0.2 UI
2.97 Gbps, Belden 1694A,
100-140 meters (Note 8) 0.3 UI
2.97 Gbps, Belden 1694A,
140-180 meters (Note 8) 0.5 UI
2.97 Gbps, Belden 1694A,
180-200 meters 0.55 UI
1.485 Gbps, Belden 1694A,
0-200 meters (Note 8) 0.2 UI
1.485 Gbps, Belden 1694A,
200-220 meters 0.3 UI
270 Mbps, Belden 1694A,
0-400 meters (Note 8) 0.3 UI
tr, tfOutput Rise Time, Fall Time 20% – 80%, 100Ω load,
(Note 4), Figure 1
SDO, SDO 90 130 ps
Mismatch in Rise/Fall Time (Note 4) 2 15 ps
tOS Output Overshoot (Note 4) 1 5 %
RLIN Input Return Loss 5 MHz - 1.5 GHz, (Note 9) SDI, SDI 15 dB
1.5 GHz - 3.0 GHz, (Note 9) 10 dB
RIN Input Resistance single-ended 1.5 kΩ
CIN Input Capacitance single-ended 0.7 pF
SPI Interface AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).
Symbol Parameter Conditions Reference Min Typ Max Units
Recommended Input Timing Requirements
fSCK SCK Frequency SCK 20 MHz
tPH SCK Pulse Width High Figure 2, Figure 3 40 % SCK
period
tPL SCK Pulse Width Low 40 % SCK
period
tSU MOSI Setup Time Figure 2, Figure 3 MOSI 4 ns
tHMOSI Hold Time 4 ns
tSSSU SS Setup Time Figure 2, Figure 3 SS 14 ns
tSSH SS Hold Time 4 ns
tSSOF SS Off Time 1 SCK
period
Switching Characteristics
tODZ MISO Driven-to-TRI-STATE Time Figure 3 MISO 20 ns
tOZD MISO TRI-STATE-to-Driven Time 10 ns
tOD MISO Output Delay Time 15 ns
Note 1: "Absolute Maximum Ratings" are those parameter values beyond which the life and operation of the device cannot be guaranteed. The stating herein of
these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of "Electrical Characteristics"
specifies acceptable device operating conditions.
Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated referenced to
VEE = 0 Volts.
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LMH0394
Note 3: Typical values are stated for VCC = +2.5V and TA = +25°C.
Note 4: Specification is guaranteed by characterization.
Note 5: The LMH0394 can be optimized for different launch amplitudes via the SPI.
Note 6: The differential output voltage and offset voltage are adjustable via the SPI.
Note 7: Typical ICC is measured with a 2.97 Gbps input signal.
Note 8: Based on design and characterization data over the full range of recommended operating conditions of the device. Jitter is measured in accordance with
SMPTE RP 184, SMPTE RP 192, and the applicable serial data transmission standard: SMPTE 424M, SMPTE 292M, or SMPTE 259M.
Note 9: Input return loss is dependent on board design. The LMH0394 exceeds this specification on the SD394 evaluation board with a return loss network
consisting of a 5.6 nH inductor in parallel with a 75Ω series resistor on the input.
Timing Diagrams
30101508
FIGURE 1. LVDS Output Voltage, Offset, and Timing Parameters
30101509
FIGURE 2. SPI Write
30101510
FIGURE 3. SPI Read
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LMH0394
Block Diagram (Pin Mode)
30101502
Device Operation
BLOCK DESCRIPTION
The Equalizer Filter block is a multi-stage adaptive filter. If
Bypass is high, the equalizer filter is disabled.
The DC Restoration / Level Control block receives the dif-
ferential signals from the equalizer filter block. This block
incorporates a self-biasing DC restoration circuit to fully DC
restore the signals. If Bypass is high, this function is disabled.
The signals before and after the DC Restoration / Level Con-
trol block are used to generate the Automatic Equalization
Control (AEC) signal. This control signal sets the gain and
bandwidth of the equalizer filter.
The Carrier Detect block generates the carrier detect signal
based on the SDI input and an adjustment from the Mute
Reference block.
The SPI Control block uses the MOSI, MISO, SCK, and SS
signals in SPI mode to control the SPI registers. SPI_EN se-
lects between SPI mode and pin mode. In pin mode, SPI_EN
is driven logic low.
The Output Driver produces SDO and SDO.
MUTE REFERENCE (MUTEREF)
The mute reference sets the threshold for CD and (with CD
tied to MUTE) determines the amount of cable to equalize
before automatically muting the outputs. This is set by apply-
ing a voltage inversely proportional to the length of cable to
equalize. The applied voltage must be greater than the
MUTEREF floating voltage (typically 1.3V) in order to change
the CD threshold. As the applied MUTEREF voltage is in-
creased, the amount of cable that can be equalized before
carrier detect is de-asserted and the outputs are muted is de-
creased. MUTEREF may be left unconnected or connected to
ground for normal CD operation. Optionally, the LMH0394 al-
lows the mute reference to be set digitally via SPI register 03h.
Figure 4 shows the minimum MUTEREF input voltage required
to force carrier detect to inactive vs. Belden 1694A cable
length. The results shown are valid for Belden 1694A cable
lengths of 0-200m at 2.97 Gbps, 0-220m at 1.485 Gbps, and
0-400m at 270 Mbps.
0 50 100 150 200 250 300 350 400
1.2
1.4
1.6
1.8
2.0
2.2
MUTEREF (V)
BELDEN 1694A CABLE LENGTH (m)
30101512
FIGURE 4. MUTEREF vs. Belden 1694A Cable Length
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LMH0394
CARRIER DETECT (CD) AND MUTE
Carrier detect CD indicates if a valid signal is present at the
LMH0394 input. This signal is logical OR operation of the in-
ternal energy detector and MUTEREF setting (if used). The
internal energy detector detects energy across different data
rates. If MUTEREF is used, the carrier detect threshold will be
altered accordingly. CD provides a high voltage when no sig-
nal is present at the LMH0394 input. CD is low when a valid
input signal is detected.
MUTE can be used to manually mute or enable SDO and
SDO. Applying a high input to MUTE will mute the LMH0394
outputs by forcing the output to a logic 1. Applying a low input
will force the outputs to be active.
In pin mode, CD and MUTE may be tied together to automat-
ically mute the output when no input signal is present.
AUTO SLEEP
The auto sleep mode allows the LMH0394 to power down
when no input signal is detected. If the AUTO SLEEP pin is
set high, the LMH0394 goes into a deep power save mode
when no signal is detected. The device powers on again once
an input signal is detected. The auto sleep functionality can
be turned off by setting AUTO SLEEP low or tying this pin to
ground. An additional auto sleep setting available in SPI mode
can be used to force the equalizer to power down regardless
of whether there is an input signal or not. Auto sleep has
precedence over mute and bypass modes.
In auto sleep mode, the time to power down the equalizer
when the input signal is removed is less than 200 µs and
should not have any impact on the system timing require-
ments. The device will wake up automatically once an input
signal is detected, and the delay between signal detection and
full functionality of the equalizer is negligible (about 5 ms). The
overall system will be limited only by the settling time constant
of the equalizer adaptation loop.
INPUT INTERFACING
The LMH0394 accepts either differential or single-ended in-
put. The input must be AC coupled. The Typical Application
(Pin Mode) diagram on the front page shows the typical con-
figuration for a single-ended input. The unused input must be
properly terminated as shown.
The LMH0394 can be optimized for different launch ampli-
tudes via the SPI (see LAUNCH AMPLITUDE OPTIMIZA-
TION in the SPI Register Access section).
The LMH0394 correctly handles equalizer pathological sig-
nals for standard definition and high definition serial digital
video, as described in SMPTE RP 178 and RP 198, respec-
tively.
OUTPUT INTERFACING
SDO and SDO together are internally terminated 100Ω LVDS
outputs. These outputs can be DC coupled to most common
differential receivers.
The default output common mode voltage (VOS) is 1.2V. The
output common mode voltage may be adjusted via the SPI in
200 mV increments, from 0.8V to 1.2V (see OUTPUT DRIV-
ER ADJUSTMENTS AND DE-EMPHASIS SETTING in the
SPI Register Access section). When the output common
mode is supply referenced, the common mode voltage is
about 1.35V (for 700 mVP-P differential swing). This adjustable
output common mode voltage offers flexibility for interfacing
to many types of receivers.
The default differential output swing (VSSP-P) is 700 mVP-P.
The differential output swing may be adjusted via the SPI.
Valid options are 400, 600, 700, or 800 mVP-P (see OUTPUT
DRIVER ADJUSTMENTS AND DE-EMPHASIS SETTING in
the SPI Register Access section).
The LMH0394 output should be DC coupled to the input of
the receiving device as long as the common mode ranges of
both devices are compatible. 100Ω differential transmission
lines should be used to connect between the LMH0394 out-
puts and the input of the receiving device where possible.
Figure 5 shows an example of a DC-coupled interface be-
tween the LMH0394 and LMH0346 SDI reclocker. All that is
required is the 100Ω differential termination as shown. The
resistor should be placed as close as possible to the
LMH0346 input. If desired, this network may be terminated
with two 50Ω resistors and a center tap capacitor to ground
in place of the signal 100Ω resistor.
Figure 6 shows an example of a DC-coupled interface be-
tween the LMH0394 and LMH0356 SDI reclocker. The
LMH0356 inputs have 50Ω internal terminations (100Ω dif-
ferential) to terminate the transmission line, so no additional
components are required.
The LMH0394 may be AC coupled to the receiving device
when necessary. For example, the LMH0394 outputs are not
strictly compatible with 2.5V CML and thus should not be
connected via 50Ω resistors to 2.5V. If the input common
mode range of the receiving device is not compatible with the
output common mode range of the LMH0394, then AC cou-
pling is required. Following the AC coupling capacitors, the
signal may have to be biased at the input of the receiving de-
vice.
The LMH0394 output driver is equipped with programmable
output de-emphasis to minimize inter-symbol interference
caused by the loss dispersion from driving signals across
PCB traces (see OUTPUT DRIVER ADJUSTMENTS AND
DE-EMPHASIS SETTING in the SPI Register Access sec-
tion). De-emphasis works with all combinations of output
common mode voltage and output voltage swing settings to
support DC coupling to the receiving device.
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LMH0394
30101518
FIGURE 5. DC Output Interface to LMH0346 Reclocker
30101516
FIGURE 6. DC Output Interface to LMH0356 Reclocker
SPI Register Access
Setting SPI_EN high enables the optional SPI register access
mode. In SPI mode, the LMH0394 provides register access
to all of its features along with a cable length indicator, pro-
grammable output de-emphasis, programmable output com-
mon mode voltage and swing, digital MUTEREF, and launch
amplitude optimization. There are eight supported 8-bit reg-
isters in the device (see Table 1). The LMH0394 supports SPI
daisy-chaining among an unlimited number of LMH0394 de-
vices. With SPI_EN set low, the device operates in pin mode
and is footprint compatible with the LMH0384, LMH0344,
LMH0044, and LMH0074.
SPI Transaction Overview
Each SPI transaction to a single device is 16-bits long. The
transaction is initiated by driving SS low, and completed by
returning SS high. The 16-bit MOSI payload consists of the
read/write command (“1” for reads and “0” for writes), the
seven address bits of the device register (MSB first), and the
eight data bits (MSB first). The LMH0394 MOSI input data is
latched on the rising edge of SCK, and the MISO output data
is sourced on the falling edge of SCK.
In order to facilitate daisy-chaining, the prior SPI command,
address, and data are shifted out on the MISO output as the
current command, address, and data are shifted in on the
MOSI input. For SPI writes, the MISO output is typically ig-
nored as “Don't Care” data. For SPI reads, the MISO output
provides the requested read data (after 16 periods of SCK).
The MISO output is active when SS low, and tri-stated when
SS is high.
SPI Write
The SPI write is shown in Figure 2. The SPI write is 16 bits
long. The 16-bit MOSI payload consists of a “0” (write com-
mand), seven address bits, and eight data bits. The SS signal
is driven low, and the 16 bits are sent to the LMH0394's MOSI
input. After the SPI write, SS must return high. The prior SPI
command, address, and data shifted out on the MISO output
during the SPI write is shown as “Don't Care” on the MISO
output in Figure 2.
SPI Read
The SPI read is shown in Figure 3. The SPI read is 32 bits
long, consisting of a 16-bit read transaction followed by a 16-
bit dummy read transaction to shift out the read data on the
MISO output. The first 16-bit MOSI payload consists of a
“1” (read command), seven address bits, and eight “1”s which
are ignored. The second 16-bit MOSI payload consists of 16
“1”s which are ignored but necessary in order to shift out the
requested read data on the MISO output. The SS signal is
driven low, and the first 16 bits are sent to the LMH0394's
MOSI input. The prior SPI command, address, and data are
shifted out on the MISO output during the first 16-bit transac-
tion, and are typically ignored (this is shown as “Don't Care”
on the MISO output in Figure 3. SS must return high and then
is driven low again before the second 16 bits (all “1”s) are sent
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LMH0394
to the LMH0394's MOSI input. Once again, the prior SPI com-
mand, address, and data are shifted out on the MISO output,
but this data now includes the requested read data. The read
data is available on the MISO output during the second 8 bits
of the 16-bit dummy read transaction, as shown by D7-D0 in
Figure 3.
SPI Daisy-Chain Operation
The LMH0394 SPI controller supports daisy-chaining the se-
rial data between an unlimited number of LMH0394 devices.
Each LMH0394 device is directly connected to the SCK and
SS pins on the host. However, only the first LMH0394 device
in the chain is connected to the host’s MOSI pin, and only the
last device in the chain is connected to the host’s MISO pin.
The MISO pin of each intermediate LMH0394 device in the
chain is connected to the MOSI pin of the next LMH0394 de-
vice, creating a serial shift register. This daisy-chain architec-
ture is shown in Figure 7.
30101520
FIGURE 7. SPI Daisy Chain System Architecture
In a daisy-chain configuration of N LMH0394 devices, the host
conceptually sees a shift register of length 16xN. Therefore
the length of SPI transactions (as previously described) is
16xN bits, and SS must be asserted for 16xN clock cycles for
each SPI transaction.
SPI Daisy-Chain Write
Figure 8 shows the SPI daisy-chain write for a daisy-chain of
N devices. The SS signal is driven low and SCK is toggled for
16xN clocks. The 16xN bit MOSI payload (sent to Device 1 in
the daisy-chain) consists of the 16-bit SPI write data for De-
vice N (the last device in the chain), followed by the write data
for Device N-1, Device N-2, etc., ending with the write data
for Device 1 (the first device in the chain). The 16-bit SPI write
data for each device consists of a “0” (write command), seven
address bits, and eight data bits. After the SPI daisy-chain
write, SS must return high and then the write occurs for all
devices in the daisy-chain.
30101525
FIGURE 8. SPI Daisy-Chain Write
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LMH0394
SPI Daisy-Chain Read
Figure 9 shows the SPI daisy-chain read for a daisy-chain of
N devices. The SPI daisy-chain read is 32xN bits long, con-
sisting of 16xN bits for the read transaction followed by 16xN
bits for the dummy read transaction (all “1”s) to shift out the
read data on the MISO output. The SS signal is driven low
and SCK is toggled for 16xN clocks. The first 16xN bit MOSI
payload (sent to Device 1 in the daisy-chain) consists of the
16-bit SPI read data for Device N (the last device in the chain),
followed by the read data for Device N-1, Device N-2, etc.,
ending with the read data for Device 1 (the first device in the
chain). The 16-bit SPI read data for each device consists of
a “1” (read command), seven address bits, and eight “1”s
(which are ignored). After the first 16xN bit transaction, SS
must return high (to latch the data) and then is driven low
again before the second 16xN bit transaction of all “1”s is sent
to the MOSI input. The requested read data is shifted out on
MISO starting with the data for Device N and ending with the
data for Device 1. After this transaction, SS must return high.
30101526
FIGURE 9. SPI Daisy-Chain Read
SPI Daisy-Chain Read and Write Example
The following example further clarifies LMH0394 SPI daisy-
chain operation. Assume a daisy-chain of three LMH0394
devices (Device 1, Device 2, and Device 3), with Device 1 as
the first device in the chain and Device 3 as the last device in
the chain, as shown by the first three devices in Figure 7.
Since there are three devices in the daisy-chain, each SPI
transaction is 48-bits long.
This example shows an SPI operation combining SPI reads
and writes in order to accomplish the following three tasks:
1. Write 0x22 to register 0x01 of Device 1 in order to set the
output swing to 400 mVP-P.
2. Read the contents of register 0x00 of Device 2.
3. Write 0x10 to register 0x00 of Device 3 in order to force
the sleep mode.
Figure 10 shows the two 48-bit SPI transactions required to
complete these tasks (the bits are shifted in left to right).
30101528
FIGURE 10. SPI Daisy-Chain Read and Write Example
The following occurs at the end of the first transaction:
1. Write 0x22 to register 0x01 of Device 1.
2. Latch the data from register 0x00 of Device 2.
3. Write 0x10 to register 0x00 of Device 3.
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LMH0394
In the second transaction, three dummy reads (each consist-
ing of 16 “1”s) are shifted in, and the read data from Device 2
(with value 0x88) appears on MISO in the 25th through 32nd
clock cycles.
SPI Daisy-Chain Length Detection
A useful operation for the host may be to detect the length of
the daisy-chain. This is a simple matter of shifting in a series
of dummy reads with a known data value (such as 0x5A). For
an SPI daisy-chain of N LMH0394 devices, the known data
value will appear on the host's MISO pin after N+1 writes.
Assuming a daisy-chain of three LMH0394 devices, the result
of this operation is shown in Figure 11.
30101529
FIGURE 11. SPI Daisy-Chain Length Detection
OUTPUT DRIVER ADJUSTMENTS AND DE-EMPHASIS
SETTING
The output driver swing (amplitude), offset voltage (common
mode voltage), and de-emphasis level are adjustable via SPI
register 01h.
The output swing is adjustable via bits [7:6] of SPI register
01h. The default value for these register bits is “10” for a peak
to peak differential output voltage of 700 mVP-P. The output
swing can be set for 400 mVP-P, 600 mVP-P , 700 mVP-P, or
800 mVP-P.
The offset voltage is adjustable via bits [5:4] of SPI register
01h. The default value for these register bits is “10” for an
output offset of 1.2V. The output common mode voltage may
be adjusted in 200 mV increments, from 0.8V to 1.2V. It can
be set to “11” for the maximum offset voltage. At this maxi-
mum offset voltage setting, the outputs are referenced to the
positive supply and the offset voltage is around 1.35V.
The output de-emphasis is turned on or off by bit 3 of SPI
register 01h, and the de-emphasis level is set by bits [2:1] of
SPI register 01h. The output de-emphasis level may be set
for 0 dB (for driving up to 10” FR4), 3 dB (for driving 10-20”
FR4), 5 dB (for driving 20-30” FR4), or 7 dB (for driving 30-40”
FR4).
LAUNCH AMPLITUDE OPTIMIZATION
The LMH0394 can compensate for attenuation of the input
signal prior to the equalizer. This compensation is useful for
applications with a passive splitter at the equalizer input or a
non-ideal input termination network, and is controlled by SPI
register 02h.
Bit 7 of SPI register 02h is used for the launch amplitude set-
ting. At the default setting of “0”, the LMH0394 operates
normally and expects a launch amplitude of 800 mVP-P. Bit 7
may be set to “1” to optimize the LMH0394 for input signals
with 6 dB of attenuation (400 mVP-P).
CABLE LENGTH INDICATOR (CLI)
The cable length indicator (CLI) provides an indication of the
length of the cable attached to input. CLI is accessible via bits
[7:0] of SPI register 06h. The 8-bit setting ranges in decimal
value from 0 to 247 (“00000000” to “11110111” binary), cor-
responding to 0 to 400m of Belden 1694A cable. For 3G and
HD input, CLI is 1.25m per step. For SD input, CLI is 1.25m
per step, less 20m, from 0 to 191 decimal, and 3.5m per step
from 192 to 247 decimal.
To calculate the Belden 1694A cable length (in meters) from
the CLI decimal value for 3G or HD input:
To calculate the Belden 1694A cable length (in meters) from
the CLI decimal value for SD input:
Figure 12 shows typical CLI values vs. Belden 1694A cable
length. CLI is valid for Belden 1694A cable lengths of 0-200m
at 2.97 Gbps, 0-220m at 1.485 Gbps, and 0-400m at 270
Mbps. Note: Given the continuous adaptive nature of the
equalizer, this setting changes by some steps constantly.
0 50 100 150 200 250 300 350 400
0
25
50
75
100
125
150
175
200
225
250
CLI (decimal value)
BELDEN 1694A CABLE LENGTH (m)
3G/HD
SD
30101513
FIGURE 12. CLI vs. Belden 1694A Cable Length
13 www.national.com
LMH0394
Application Information
APPLICATION CIRCUIT (SPI MODE)
Figure 13 shows the application circuit for the LMH0394 in
SPI mode. (Note: The application circuit shows an external
capacitor connected between the AEC+ and AEC- pins as
commonly configured in legacy equalizers. This capacitor is
optional and not necessary for the LMH0394; the AEC+ and
AEC- pins may be left unconnected with no change in perfor-
mance.)
30101517
FIGURE 13. Application Circuit (SPI Mode)
INTERFACING TO 3.3V SPI
The LMH0394 may be controlled via optional SPI register ac-
cess. The LMH0394 SPI pins support 2.5V LVCMOS logic
levels and are compliant with JEDEC JESD8-5 (see DC Elec-
trical Characteristics). Care must be taken when interfacing
the SPI pins to other voltage levels.
The 2.5V LMH0394 SPI pins may be interfaced to a 3.3V
compliant SPI host by using a voltage divider or level trans-
lator. One implementation is a simple resistive voltage divider
as shown in Figure 14.
30101530
FIGURE 14. 3.3V SPI Interfacing
www.national.com 14
LMH0394
CROSSTALK IMMUNITY
Single-ended SDI signals are susceptible to crosstalk and
good design practices should be employed to minimize its ef-
fects. Most crosstalk originates through capacitive coupling
from adjacent signals routed closely together via traces and
connectors. To reduce capacitive coupling, SDI signals
should be appropriately spaced apart or insulated from one
another. This can be accomplished by physically isolating
signal traces in the layout and by providing additional ground
pins between signal traces in connectors as necessary.
These techniques help to reduce crosstalk but do not elimi-
nate it.
The LMH0394 was designed specifically with crosstalk in
mind and incorporates advanced circuit design techniques
that help to isolate and minimize the effects of cross-coupling
in high-density system designs. Lab evaluations and cus-
tomer testimonials have shown other adaptive cable equaliz-
ers are much more susceptible to crosstalk, resulting in
significant cable reach degradation. The LMH0394’s en-
hanced design results in minimal degradation in cable reach
in the presence of crosstalk and overall superior immunity
against cross-coupling from neighboring channels.
PCB LAYOUT RECOMMENDATIONS
For information on layout and soldering of the LLP package,
pease refer to the following application note: AN-1187,
“Leadless Leadframe Package (LLP).”
The SMPTE 424M, 292M, and 259M standards have strin-
gent requirements for the input return loss of receivers, which
essentially specify how closely the input must resemble a
75Ω network. Any non-idealities in the network between the
BNC and the equalizer will degrade the input return loss. Care
must be taken to minimize impedance discontinuities be-
tween the BNC and the equalizer to ensure that the charac-
teristic impedance of this trace is 75Ω. Please consider the
following PCB recommendations:
•Use surface mount components, and use the smallest
components available. In addition, use the smallest size
component pads.
•Select trace widths that minimize the impedance
mismatch between the BNC and the equalizer.
•Select a board stack up that supports both 75Ω single-
ended traces and 100Ω loosely-coupled differential
traces.
•Place return loss components closest to the equalizer
input pins.
•Maintain symmetry on the complimentary signals.
•Route 100Ω traces uniformly (keep trace widths and trace
spacing uniform along the trace).
•Avoid sharp bends in the signal path; use 45° or radial
bends.
•Place bypass capacitors close to each power pin, and use
the shortest path to connect equalizer power and ground
pins to the respective power or ground planes.
•Remove ground plane under input/output components to
minimize parasitic capacitance.
15 www.national.com
LMH0394
SPI Registers
TABLE 1. SPI Registers
Address R/W Name Bits Field Default Description
00h R/W General Control 7 Carrier Detect Read only.
0: No carrier detected.
1: Carrier detected.
6 Mute 0 Mute has precedence over Bypass.
0: Normal operation.
1: Outputs muted.
5 Bypass 0 0: Normal operation.
1: Equalizer bypassed.
4:3 Sleep Mode 01 Sleep mode control. Sleep has precedence over Mute and
Bypass.
00: Disable sleep mode (force equalizer to stay enabled).
01: Sleep mode active when no input signal detected.
10: Force equalizer into sleep mode (powered down)
regardless of whether there is an input signal or not.
11: Reserved.
2 Reserved 0 Reserved as 0. Always write 0 to this bit.
1 Master Reset 0 Reset registers and state machine. (This bit is self-clearing.)
0: Normal operation.
1: Reset registers and state machine.
0 Acquisition Reset 0 Reset state machine. (This bit is self-clearing.)
0: Normal operation.
1: Reset state machine.
01h R/W Output Driver 7:6 Output Swing 10 Output driver swing (VSSP-P).
00: VSSP-P = 400 mVP-P.
01: VSSP-P = 600 mVP-P.
10: VSSP-P = 700 mVP-P.
11: VSSP-P = 800 mVP-P.
5:4 Offset Voltage 10 Output driver offset voltage (common mode voltage).
00: VOS = 0.8V.
01: VOS = 1.0V.
10: VOS = 1.2V.
11: VOS Referenced to positive supply.
3 De-Emphasis 0 Output driver de-emphasis control.
0: De-emphasis disabled.
1: De-emphasis enabled.
2:1 De-Emphasis
Amplitude Level
01 Output drive de-emphasis level.
00: 0 dB (no de-emphasis).
01: 3 dB de-emphasis.
10: 5 dB de-emphasis.
11: 7 dB de-emphasis.
0 Reserved 0 Reserved (read only).
02h R/W Launch
Amplitude
Control
7 Launch Amplitude
Control
0 Launch amplitude optimization setting.
0: Normal optimization with no external attenuation (800
mVP-P launch amplitude).
1: Optimized for 6 dB external attenuation (400 mVP-P launch
amplitude).
6:0 Reserved 1101000 Reserved as 1101000. Always write 1101000 to these bits.
www.national.com 16
LMH0394
Address R/W Name Bits Field Default Description
03h R/W MUTEREF 7:6 Reserved 00 Reserved as 00. Always write 00 to these bits.
5 MUTEREF Mode 0 0: Use MUTEREF pin.
1: Use digital MUTEREF.
4:0 Digital MUTEREF
Setting
11111 Digital MUTEREF (10m per step).
00000: Mute when cable (EQ boost) ≥ 10m.
......
01111: Mute when cable (EQ boost) ≥ 160m.
......
11111: Never mute.
04h R Device ID 7:6 Reserved 00 Reserved.
5:4 EQ ID 01 00: LMH0384 device.
01: LMH0394 device.
10: LMH0395 device.
11: Reserved.
3:0 Die Revision 0011 Die revision.
05h R Rate Indicator 7:6 Reserved 00 Reserved.
5 Rate Indicator 0: SD.
1: 3G/HD.
4:0 Reserved 11000 Reserved.
06h R Cable Length
Indicator
7:0 Cable Length
Indicator
Cable Length Indicator (CLI), with 10% accuracy.
00000000: Short cable.
......
11110111: Maximum cable.
11111000: Reserved.
......
11111111: Reserved.
07h R Launch
Amplitude
Indication
7:2 Launch Amplitude
Indication
Indication of launch amplitude: 1% or 0.08 dB per step with
5% accuracy.
000000: Nominal -32%.
......
011111: Nominal -1%.
100000: Nominal.
100001: Nominal +1%.
......
111111: Nominal +31%.
1:0 Reserved Reserved.
17 www.national.com
LMH0394
Physical Dimensions inches (millimeters) unless otherwise noted
16-Pin LLP
Order Number LMH0394SQ
NS Package Number SQB16A
www.national.com 18
LMH0394
Notes
19 www.national.com
LMH0394
Notes
LMH0394 3G HD/SD SDI Low Power Extended Reach Adaptive Cable Equalizer
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