PIC18F2682/2685/4682/4685 Data Sheet 28/40/44-Pin Enhanced Flash Microcontrollers with ECANTM Technology, 10-Bit A/D and nanoWatt Technology (c) 2007 Microchip Technology Inc. Preliminary DS39761B Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39761B-page ii Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 28/40/44-Pin Enhanced Flash Microcontrollers with ECANTM Technology, 10-Bit A/D and nanoWatt Technology Power-Managed Modes: Peripheral Highlights: * * * * * * * * * * * * Run: CPU on, peripherals on Idle: CPU off, peripherals on Sleep: CPU off, peripherals off Idle mode currents down to 5.8 A typical Sleep mode currents down to 0.1 A typical Timer1 Oscillator: 1.1 A, 32 kHz, 2V Watchdog Timer: 2.1 A Two-Speed Oscillator Start-up Flexible Oscillator Structure: * * Four Crystal modes, up to 40 MHz * 4x Phase Lock Loop (PLL) - available for crystal and internal oscillators * Two External RC modes, up to 4 MHz * Two External Clock modes, up to 40 MHz * Internal Oscillator Block: - 8 user-selectable frequencies, from 31 kHz to 8 MHz - Provides a complete range of clock speeds, from 31 kHz to 32 MHz when used with PLL - User-tunable to compensate for frequency drift * Secondary Oscillator using Timer1 @ 32 kHz * Fail-Safe Clock Monitor - Allows for safe shutdown if peripheral clock stops * * * Special Microcontroller Features: High-Current Sink/source 25 mA/25 mA Three External Interrupts One Capture/Compare/PWM (CCP1) module Enhanced Capture/Compare/PWM (ECCP1) module (40/44-pin devices only): - One, two or four PWM outputs - Selectable polarity - Programmable dead time - Auto-shutdown and auto-restart Master Synchronous Serial Port (MSSP) module supporting 3-Wire SPI (all 4 modes) and I2CTM Master and Slave modes Enhanced Addressable USART module: - Supports RS-485, RS-232 and LIN 1.3 - RS-232 operation using internal oscillator block (no external crystal required) - Auto-wake-up on Start bit - Auto-Baud Detect 10-Bit, up to 11-Channel Analog-to-Digital Converter module (A/D), up to 100 ksps: - Auto-acquisition capability - Conversion available during Sleep Dual Analog Comparators with Input Multiplexing ECAN Module Features: * C compiler Optimized Architecture with optional Extended Instruction Set * 100,000 Erase/Write Cycle Enhanced Flash Program Memory typical * 1,000,000 Erase/Write Cycle Data EEPROM Memory typical * Flash/Data EEPROM Retention: > 40 years * Self-Programmable under Software Control * Priority Levels for Interrupts * 8 x 8 Single-Cycle Hardware Multiplier * Extended Watchdog Timer (WDT): - Programmable period from 41 ms to 131s * Single-Supply 5V In-Circuit Serial ProgrammingTM (ICSPTM) via two pins * In-Circuit Debug (ICD) via two pins * Wide operating voltage range: 2.0V to 5.5V EUSART * Message bit rates up to 1 Mbps * Conforms to CAN 2.0B ACTIVE Specification * Fully Backward Compatible with PIC18XXX8 CAN modules * Three Modes of Operation: - Legacy, Enhanced Legacy, FIFO * Three Dedicated Transmit Buffers with Prioritization * Two Dedicated Receive Buffers * Six Programmable Receive/Transmit Buffers * Three Full, 29-Bit Acceptance Masks * 16 Full, 29-Bit Acceptance Filters w/Dynamic Association * DeviceNetTM Data Byte Filter Support * Automatic Remote Frame Handling * Advanced Error Management Features Comp. PIC18F2682 80K 40960 3328 1024 28 8 1/0 Y Y 1 0 PIC18F2685 96K 49152 3328 1024 28 8 1/0 Y Y 1 0 1/3 PIC18F4682 80K 40960 3328 1024 40/44 11 1/1 Y Y 1 2 1/3 PIC18F4685 96K 49152 3328 1024 40/44 11 1/1 Y Y 1 2 1/3 Program Memory Device Data Memory Flash # Single-Word SRAM EEPROM (bytes) Instructions (bytes) (bytes) (c) 2007 Microchip Technology Inc. I/O CCP1/ 10-Bit ECCP1 A/D (ch) (PWM) Preliminary MSSP SPI Master I2CTM Timers 8/16-bit 1/3 DS39761B-page 1 PIC18F2682/2685/4682/4685 Pin Diagrams 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PIC18F2685 MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/HLVDIN VSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL PIC18F2682 28-Pin PDIP, SOIC RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN9 RB3/CANRX RB2/INT2/CANTX RB1/INT1/AN8 RB0/INT0/AN10 VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA MCLR/VPP/RE3 RA0/AN0/CVREF RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/HLVDIN RE0/RD/AN5 RE1/WR/AN6/C1OUT RE2/CS/AN7/C2OUT VDD VSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RD0/PSP0/C1IN+ RD1/PSP1/C1IN- Note: DS39761B-page 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIC18F4682 PIC18F4685 40-Pin PDIP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN9 RB3/CANRX RB2/INT2/CANTX RB1/INT1/AN8 RB0/INT0/FLT0/AN10 VDD VSS RD7/PSP7/P1D RD6/PSP6/P1C RD5/PSP5/P1B RD4/PSP4/ECCP1/P1A RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3/C2INRD2/PSP2/C2IN+ Pinouts are subject to change. Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3/C2INRD2/PSP2/C2IN+ RD1/PSP1/C1INRD0/PSP0/C1IN+ RC3/SCK/SCL RC2/CCP1 RC1/T1OSI NC Pin Diagrams (Continued) 44 43 42 41 40 39 38 37 36 35 34 44-Pin TQFP 33 32 31 30 29 28 27 26 25 24 23 PIC18F4682 PIC18F4685 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 NC RC0/T1OSO/T13CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7 VSS VDD RE2/CS/AN7/C2OUT RE1/WR/AN6/C1OUT RE0/RD/AN5 RA5/AN4/SS/HLVDIN RA4/T0CKI RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3/C2INRD2/PSP2/C2IN+ RD1/PSP1/C1INRD0/PSP0/C1IN+ RC3/SCK/SCL RC2/CCP1 RC1/T1OSI RC0/T1OSO/T13CKI NC NC RB4/KBI0/AN9 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD MCLR/VPP/RE3 RA0/AN0/CVREF RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RC7/RX/DT RD4/PSP4/ECCP1/P1A RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D VSS VDD RB0/INT0/FLT0/AN10 RB1/INT1/AN8 RB2/INT2/CANTX RB3/CANRX 44 43 42 41 40 39 38 37 36 35 34 44-Pin QFN PIC18F4682 PIC18F4685 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 OSC2/CLKO/RA6 OSC1/CLKI/RA7 VSS AVSS VDD AVDD RE2/CS/AN7/C2OUT RE1/WR/AN6/C1OUT RE0/RD/AN5 RA5/AN4/SS/HLVDIN RA4/T0CKI RB3/CANRX NC RB4/KBI0/AN9 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD MCLR/VPP/RE3 RA0/AN0/CVREF RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RC7/RX/DT RD4/PSP4/ECCP1/P1A RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D VSS AVDD VDD RB0/INT0/FLT0/AN10 RB1/INT1/AN8 RB2/INT2/CANTX Note: Pinouts are subject to change. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 3 PIC18F2682/2685/4682/4685 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Oscillator Configurations ............................................................................................................................................................ 23 3.0 Power-Managed Modes ............................................................................................................................................................. 33 4.0 Reset .......................................................................................................................................................................................... 41 5.0 Memory Organization ................................................................................................................................................................. 61 6.0 Flash Program Memory .............................................................................................................................................................. 95 7.0 Data EEPROM Memory ........................................................................................................................................................... 105 8.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 111 9.0 Interrupts .................................................................................................................................................................................. 113 10.0 I/O Ports ................................................................................................................................................................................... 129 11.0 Timer0 Module ......................................................................................................................................................................... 147 12.0 Timer1 Module ......................................................................................................................................................................... 151 13.0 Timer2 Module ......................................................................................................................................................................... 157 14.0 Timer3 Module ......................................................................................................................................................................... 159 15.0 Capture/Compare/PWM (CCP1) Modules ............................................................................................................................... 163 16.0 Enhanced Capture/Compare/PWM (ECCP1) Module.............................................................................................................. 173 17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 187 18.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART) ....................................................................................... 227 19.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 247 20.0 Comparator Module.................................................................................................................................................................. 257 21.0 Comparator Voltage Reference Module ................................................................................................................................... 263 22.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 267 23.0 ECANTM Technology ................................................................................................................................................................ 273 24.0 Special Features of the CPU .................................................................................................................................................... 343 25.0 Instruction Set Summary .......................................................................................................................................................... 363 26.0 Development Support............................................................................................................................................................... 413 27.0 Electrical Characteristics .......................................................................................................................................................... 417 28.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 453 29.0 Packaging Information.............................................................................................................................................................. 455 Appendix A: Revision History............................................................................................................................................................. 463 Appendix B: Device Differences......................................................................................................................................................... 463 Appendix C: Conversion Considerations ........................................................................................................................................... 464 Appendix D: Migration From Baseline to Enhanced Devices............................................................................................................. 464 Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 465 Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 465 Index .................................................................................................................................................................................................. 467 The Microchip Web Site ..................................................................................................................................................................... 479 Customer Change Notification Service .............................................................................................................................................. 479 Customer Support .............................................................................................................................................................................. 479 Reader Response .............................................................................................................................................................................. 480 PIC18F2682/2685/4682/4685 Product Identification System ............................................................................................................ 481 DS39761B-page 4 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 5 PIC18F2682/2685/4682/4685 NOTES: DS39761B-page 6 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 1.0 DEVICE OVERVIEW 1.1.2 This document contains device-specific information for the following devices: * * * * PIC18F2682 PIC18F2685 PIC18F4682 PIC18F4685 This family of devices offers the advantages of all PIC18 microcontrollers - namely, high computational performance at an economical price - with the addition of high-endurance, Enhanced Flash program memory. In addition to these features, the PIC18F2682/2685/ 4682/4685 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive applications. 1.1 1.1.1 New Core Features nanoWatt TECHNOLOGY All of the devices in the PIC18F2682/2685/4682/4685 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: * Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. * Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. * On-the-Fly Mode Switching: The powermanaged modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application's software design. * Lower Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer have been reduced by up to 80%, with typical values of 1.1 and 2.1 A, respectively. * Extended Instruction Set: In addition to the standard 75 instructions of the PIC18 instruction set, PIC18F2682/2685/4682/4685 devices also provide an optional extension to the core CPU functionality. The added features include eight additional instructions that augment indirect and indexed addressing operations and the implementation of Indexed Literal Offset Addressing mode for many of the standard PIC18 instructions. (c) 2007 Microchip Technology Inc. MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F2682/2685/4682/4685 family offer ten different oscillator options, allowing users a wide range of choices in developing application hardware. These options include: * Four Crystal modes, using crystals or ceramic resonators * Two External Clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general I/O) * Two External RC Oscillator modes with the same pin options as the External Clock modes * An internal oscillator block which provides an 8 MHz clock (2% accuracy) and an INTRC source (approximately 31 kHz, stable over temperature and VDD), as well as a range of 6 user selectable clock frequencies, between 125 kHz to 4 MHz, for a total of 8 clock frequencies. This option frees the two oscillator pins for use as additional general purpose I/O. * A Phase Lock Loop (PLL) frequency multiplier, available to both the High-Speed Crystal and Internal Oscillator modes, which allows clock speeds of up to 40 MHz. Used with the internal oscillator, the PLL gives users a complete selection of clock speeds, from 31 kHz to 32 MHz - all without using an external crystal or clock circuit. Besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: * Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued low-speed operation or a safe application shutdown. * Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available. Preliminary DS39761B-page 7 PIC18F2682/2685/4682/4685 1.2 Other Special Features 1.3 * Memory Endurance: The Enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles - up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. * Self-Programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field. * Extended Instruction Set: The PIC18F2682/ 2685/4682/4685 family introduces an optional extension to the PIC18 instruction set, which adds 8 new instructions and an Indexed Addressing mode. This extension, enabled as a device configuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as C. * Enhanced CCP1 Module: In PWM mode, this module provides 1, 2 or 4 modulated outputs for controlling half-bridge and full-bridge drivers. Other features include auto-shutdown, for disabling PWM outputs on interrupt or other select conditions, and auto-restart to reactivate outputs once the condition has cleared. * Enhanced Addressable USART: This serial communication module is capable of standard RS-232 operation and provides support for the LIN bus protocol. Other enhancements include Auto-Baud Rate Detection and a 16-bit Baud Rate Generator for improved resolution. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement). * 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead. * Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing a time-out range from 4 ms to over 131 seconds, that is stable across operating voltage and temperature. DS39761B-page 8 Details on Individual Family Members Devices in the PIC18F2682/2685/4682/4685 family are available in 28-pin (PIC18F2682/2685) and 40/44-pin (PIC18F4682/4685) packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in six ways: 1. 2. 3. 4. 5. 6. Flash program memory (80 Kbytes for PIC18F2682/4682 devices, 96 Kbytes for PIC18F2685/4685 devices). A/D channels (8 for PIC18F2682/2685 devices, 11 for PIC18F4682/4685 devices). I/O ports (3 bidirectional ports and 1 input only port on PIC18F2682/2685 devices, 5 bidirectional ports on PIC18F4682/4685 devices). CCP1 and Enhanced CCP1 implementation (PIC18F2682/2685 devices have 1 standard CCP1 module, PIC18F4682/4685 devices have one standard CCP1 module and one ECCP1 module). Parallel Slave Port (present only on PIC18F4682/4685 devices). PIC18F4682/4685 devices provide two comparators. All other features for devices in this family are identical. These are summarized in Table 1-1. The pinouts for all devices are listed in Table 1-2 and Table 1-3. Like all Microchip PIC18 devices, members of the PIC18F2682/2685/4682/4685 family are available as both standard and low-voltage devices. Standard devices with Enhanced Flash memory, designated with an "F" in the part number (such as PIC18F2685), accommodate an operating VDD range of 4.2V to 5.5V. Low-voltage parts, designated by "LF" (such as PIC18LF2685), function over an extended VDD range of 2.0V to 5.5V. Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 1-1: DEVICE FEATURES Features PIC18F2682 PIC18F2685 PIC18F4682 PIC18F4685 Operating Frequency DC - 40 MHz DC - 40 MHz DC - 40 MHz DC - 40 MHz 80K 96K 80K 96K Program Memory (Instructions) 40960 49152 40960 49152 Data Memory (Bytes) 3328 3328 3328 3328 Data EEPROM Memory (Bytes) 1024 1024 1024 1024 19 19 20 20 Ports A, B, C, (E) Ports A, B, C, (E) 4 4 Program Memory (Bytes) Interrupt Sources I/O Ports Timers Ports A, B, C, D, E Ports A, B, C, D, E 4 4 Capture/Compare/PWM Modules 1 1 1 1 Enhanced Capture/ Compare/PWM Modules 0 0 1 1 ECAN Module 1 1 1 1 Serial Communications MSSP, Enhanced USART MSSP, Enhanced USART MSSP, Enhanced USART MSSP, Enhanced USART Parallel Slave Port Communications (PSP) No No Yes Yes 8 Input Channels 8 Input Channels 11 Input Channels 11 Input Channels 10-bit Analog-to-Digital Module Comparators 0 0 2 2 POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT Programmable High/Low-Voltage Detect Yes Yes Yes Yes Programmable Brown-out Reset Yes Yes Yes Yes 75 Instructions; 83 with Extended Instruction Set Enabled 75 Instructions; 83 with Extended Instruction Set Enabled 75 Instructions; 83 with Extended Instruction Set Enabled 75 Instructions; 83 with Extended Instruction Set Enabled 28-pin PDIP 28-pin SOIC 28-pin PDIP 28-pin SOIC 40-pin PDIP 44-pin QFN 44-pin TQFP 40-pin PDIP 44-pin QFN 44-pin TQFP Resets (and Delays) Instruction Set Packages (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 9 PIC18F2682/2685/4682/4685 FIGURE 1-1: PIC18F2682/2685 (28-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/HLVDIN OSC2/CLKO/RA6 OSC1/CLKI/RA7 Data Memory (3.3 Kbytes) PCLATU PCLATH 21 PORTA Data Latch 8 8 inc/dec logic Address Latch 20 PCU PCH PCL Program Counter 12 Data Address<12> 31 Level Stack 4 BSR Address Latch STKPTR Program Memory (80/96 Kbytes) Data Latch 4 Access Bank 12 FSR0 FSR1 FSR2 12 PORTB RB0/INT0/AN10 RB1/INT1/AN8 RB2/INT2/CANTX RB3/CANRX RB4/KBI0/AN9 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD inc/dec logic 8 Table Latch Address Decode ROM Latch Instruction Bus <16> IR 8 Instruction Decode & Control State Machine Control Signals PRODH PRODL PORTC 3 8 BITOP 8 Internal Oscillator Block Power-up Timer T1OSI INTRC Oscillator T1OSO 8 MHz Oscillator Oscillator Start-up Timer Power-on Reset OSC1(2) (2) OSC2 Single-Supply Programming In-Circuit Debugger MCLR(1) VDD, VSS BOR HLVD Note RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT 8 x 8 Multiply W 8 8 8 8 ALU<8> 8 Watchdog Timer Brown-out Reset Fail-Safe Clock Monitor Band Gap Reference PORTE MCLR/VPP/RE3(1) Data EEPROM Timer0 Timer1 Timer2 Timer3 CCP1 ECCP1 MSSP EUSART ADC 10-bit ECANTM 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 "Oscillator Configurations" for additional information. DS39761B-page 10 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 FIGURE 1-2: PIC18F4682/4685 (40/44-PIN) BLOCK DIAGRAM Data Bus<8> PORTA Table Pointer<21> 8 8 inc/dec logic Data Memory (3.3 Kbytes) PCLATU PCLATH 21 RA0/AN0/CVREF RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/HLVDIN OSC2/CLKO/RA6 OSC1/CLKI/RA7 Data Latch Address Latch 20 PCU PCH PCL Program Counter 12 Data Address<12> PORTB 31 Level Stack 4 BSR Address Latch STKPTR Program Memory (80/96 Kbytes) Data Latch 12 FSR0 FSR1 FSR2 RB0/INT0/FLT0/AN10 RB1/INT1/AN8 RB2/INT2/CANTX RB3/CANRX RB4/KBI0/AN9 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD 4 Access Bank 12 inc/dec logic 8 Table Latch PORTC Address Decode ROM Latch Instruction Bus <16> RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT IR 8 Instruction Decode & Control State Machine Control Signals PRODH PRODL PORTD 3 8 x 8 Multiply BITOP 8 Internal Oscillator Block Power-up Timer T1OSI INTRC Oscillator T1OSO 8 MHz Oscillator Oscillator Start-up Timer Power-on Reset OSC1(2) (2) OSC2 MCLR(1) Single-Supply Programming VDD, VSS In-Circuit Debugger W 8 8 8 8 ALU<8> 8 Watchdog Timer Brown-out Reset Fail-Safe Clock Monitor PORTE RE0/RD/AN5 RE1/WR/AN6/C1OUT RE2/CS/AN7/C2OUT MCLR/VPP/RE3(1) Band Gap Reference BOR HLVD Data EEPROM Timer0 Timer1 Timer2 Timer3 Comparator CCP1 ECCP1 MSSP EUSART ADC 10-bit Note RD0/PSP0/C1IN+ RD1/PSP1/C1INRD2/PSP2/C2IN+ RD3/PSP3/C2INRD4/PSP4/ECCP1/P1A RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D 8 ECANTM 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 "Oscillator Configurations" for additional information. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 11 PIC18F2682/2685/4682/4685 TABLE 1-2: PIC18F2682/2685 PINOUT I/O DESCRIPTIONS Pin Name MCLR/VPP/RE3 MCLR Pin Number PDIP, SOIC I ST P I ST 9 I CLKI I RA7 OSC2/CLKO/RA6 OSC2 Buffer Type 1 VPP RE3 OSC1/CLKI/RA7 OSC1 Pin Type I/O Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. CMOS External clock source input. Always associated with pin function OSC1. (See related OSC2/CLKO pin.) TTL General purpose I/O pin. ST 10 O -- CLKO O -- RA6 I/O TTL Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output DS39761B-page 12 CMOS = CMOS compatible input or output I = Input P = Power Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 1-2: PIC18F2682/2685 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP, SOIC Pin Type Buffer Type Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 2 RA1/AN1 RA1 AN1 3 RA2/AN2/VREFRA2 AN2 VREF- 4 RA3/AN3/VREF+ RA3 AN3 VREF+ 5 RA4/T0CKI RA4 T0CKI 6 RA5/AN4/SS/HLVDIN RA5 AN4 SS HLVDIN 7 I/O I TTL Analog Digital I/O. Analog input 0. I/O I TTL Analog Digital I/O. Analog input 1. I/O I I TTL Analog Analog Digital I/O. Analog input 2. A/D reference voltage (low) input. I/O I I TTL Analog Analog Digital I/O. Analog input 3. A/D reference voltage (high) input. I/O I TTL ST I/O I I I TTL Analog TTL Analog Digital I/O. Timer0 external clock input. Digital I/O. Analog input 4. SPI slave select input. High/Low-Voltage Detect input. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output (c) 2007 Microchip Technology Inc. CMOS = CMOS compatible input or output I = Input P = Power Preliminary DS39761B-page 13 PIC18F2682/2685/4682/4685 TABLE 1-2: PIC18F2682/2685 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP, SOIC Pin Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/AN10 RB0 INT0 AN10 21 RB1/INT1/AN8 RB1 INT1 AN8 22 RB2/INT2/CANTX RB2 INT2 CANTX 23 RB3/CANRX RB3 CANRX 24 RB4/KBI0/AN9 RB4 KBI0 AN9 25 RB5/KBI1/PGM RB5 KBI1 PGM 26 RB6/KBI2/PGC RB6 KBI2 PGC 27 RB7/KBI3/PGD RB7 KBI3 PGD 28 I/O I I TTL ST Analog Digital I/O. External interrupt 0. Analog input 10. I/O I I TTL ST Analog Digital I/O. External interrupt 1. Analog input 8. I/O I O TTL ST TTL Digital I/O. External interrupt 2. CAN bus TX. I/O I TTL TTL Digital I/O. CAN bus RX. I/O I I TTL TTL Analog I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. Low-Voltage ICSPTM Programming enable pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. Digital I/O. Interrupt-on-change pin. Analog input 9. Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output DS39761B-page 14 CMOS = CMOS compatible input or output I = Input P = Power Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 1-2: PIC18F2682/2685 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP, SOIC Pin Type Buffer Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 11 RC1/T1OSI RC1 T1OSI 12 RC2/CCP1 RC2 CCP1 13 RC3/SCK/SCL RC3 SCK SCL 14 RC4/SDI/SDA RC4 SDI SDA 15 RC5/SDO RC5 SDO 16 RC6/TX/CK RC6 TX CK 17 RC7/RX/DT RC7 RX DT 18 I/O O I ST -- ST Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. I/O I ST CMOS I/O I/O ST ST Digital I/O. Capture1 input/Compare1 output/PWM1 output. I/O I/O I/O ST ST ST Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2CTM mode. I/O I I/O ST ST ST Digital I/O. SPI data in. I2C data I/O. I/O O ST -- Digital I/O. SPI data out. I/O O I/O ST -- ST Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX/DT). I/O I I/O ST ST ST Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX/CK). Digital I/O. Timer1 oscillator input. RE3 -- -- -- See MCLR/VPP/RE3 pin. VSS 8, 19 P -- Ground reference for logic and I/O pins. VDD 20 P -- Positive supply for logic and I/O pins. Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output (c) 2007 Microchip Technology Inc. CMOS = CMOS compatible input or output I = Input P = Power Preliminary DS39761B-page 15 PIC18F2682/2685/4682/4685 TABLE 1-3: PIC18F4682/4685 PINOUT I/O DESCRIPTIONS Pin Name MCLR/VPP/RE3 MCLR Pin Number PDIP QFN 1 18 Pin Buffer TQFP Type Type 18 VPP RE3 OSC1/CLKI/RA7 OSC1 13 32 I ST P I ST 30 I CLKI I RA7 I/O OSC2/CLKO/RA6 OSC2 14 33 Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. CMOS External clock source input. Always associated with pin function OSC1. (See related OSC2/CLKO pin.) TTL General purpose I/O pin. ST 31 O -- CLKO O -- RA6 I/O TTL Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output DS39761B-page 16 Description Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. CMOS = CMOS compatible input or output I = Input P = Power Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 1-3: PIC18F4682/4685 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP QFN RA0/AN0/CVREF RA0 AN0 CVREF 2 19 RA1/AN1 RA1 AN1 3 RA2/AN2/VREFRA2 AN2 VREF- 4 RA3/AN3/VREF+ RA3 AN3 VREF+ 5 RA4/T0CKI RA4 T0CKI 6 RA5/AN4/SS/HLVDIN RA5 AN4 SS HLVDIN 7 Pin Buffer TQFP Type Type Description PORTA is a bidirectional I/O port. 20 21 22 23 24 19 I/O I O TTL Analog Analog Digital I/O. Analog input 0. Analog comparator reference output. I/O I TTL Analog Digital I/O. Analog input 1. I/O I I TTL Analog Analog Digital I/O. Analog input 2. A/D reference voltage (low) input. I/O I I TTL Analog Analog Digital I/O. Analog input 3. A/D reference voltage (high) input. I/O I TTL ST I/O I I I TTL Analog TTL Analog 20 21 22 23 24 RA6 Digital I/O. Analog input 4. SPI slave select input. High/Low-Voltage Detect input. See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output (c) 2007 Microchip Technology Inc. Digital I/O. Timer0 external clock input. CMOS = CMOS compatible input or output I = Input P = Power Preliminary DS39761B-page 17 PIC18F2682/2685/4682/4685 TABLE 1-3: PIC18F4682/4685 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP QFN Pin Buffer TQFP Type Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0/AN10 RB0 INT0 FLT0 AN10 33 RB1/INT1/AN8 RB1 INT1 AN8 34 RB2/INT2/CANTX RB2 INT2 CANTX 35 RB3/CANRX RB3 CANRX 36 RB4/KBI0/AN9 RB4 KBI0 AN9 37 RB5/KBI1/PGM RB5 KBI1 PGM 38 RB6/KBI2/PGC RB6 KBI2 PGC 39 RB7/KBI3/PGD RB7 KBI3 PGD 40 9 10 11 12 14 15 16 17 8 I/O I I I TTL ST ST Analog Digital I/O. External interrupt 0. Enhanced PWM Fault input (ECCP1 module). Analog input 10. I/O I I TTL ST Analog Digital I/O. External interrupt 1. Analog input 8. I/O I O TTL ST TTL Digital I/O. External interrupt 2. CAN bus TX. I/O I TTL TTL Digital I/O. CAN bus RX. I/O I I TTL TTL Analog I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. Low-Voltage ICSPTM Programming enable pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. 9 10 11 14 15 16 17 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output DS39761B-page 18 Digital I/O. Interrupt-on-change pin. Analog input 9. CMOS = CMOS compatible input or output I = Input P = Power Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 1-3: PIC18F4682/4685 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP QFN RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 15 34 RC1/T1OSI RC1 T1OSI 16 RC2/CCP1 RC2 CCP1 17 RC3/SCK/SCL RC3 SCK 18 Pin Buffer TQFP Type Type Description PORTC is a bidirectional I/O port. 35 36 37 32 23 RC5/SDO RC5 SDO 24 RC6/TX/CK RC6 TX CK 25 RC7/RX/DT RC7 RX DT 26 42 43 44 1 ST -- ST I/O I ST CMOS I/O I/O ST ST Digital I/O. Capture1 input/Compare1 output/PWM1 output. I/O I/O ST ST I/O ST Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2CTM mode. I/O I I/O ST ST ST Digital I/O. SPI data in. I2C data I/O. I/O O ST -- Digital I/O. SPI data out. I/O O I/O ST -- ST Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX/DT pin). I/O I I/O ST ST ST Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX/CK pin). Digital I/O. Timer1 oscillator input. 36 37 42 43 44 1 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output (c) 2007 Microchip Technology Inc. Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. 35 SCL RC4/SDI/SDA RC4 SDI SDA I/O O I CMOS = CMOS compatible input or output I = Input P = Power Preliminary DS39761B-page 19 PIC18F2682/2685/4682/4685 TABLE 1-3: PIC18F4682/4685 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP QFN Pin Buffer TQFP Type Type Description PORTD is a bidirectional I/O port or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when PSP module is enabled. RD0/PSP0/C1IN+ RD0 PSP0 C1IN+ 19 RD1/PSP1/C1INRD1 PSP1 C1IN- 20 RD2/PSP2/C2IN+ RD2 PSP2 C2IN+ 21 RD3/PSP3/C2INRD3 PSP3 C2IN- 22 RD4/PSP4/ECCP1/ P1A RD4 PSP4 ECCP1 P1A 27 RD5/PSP5/P1B RD5 PSP5 P1B 28 RD6/PSP6/P1C RD6 PSP6 P1C 29 RD7/PSP7/P1D RD7 PSP7 P1D 30 38 39 40 41 2 3 4 5 38 I/O I/O I ST TTL Analog Digital I/O. Parallel Slave Port data. Comparator 1 input (+). I/O I/O I ST TTL Analog Digital I/O. Parallel Slave Port data. Comparator 1 input (-) I/O I/O I ST TTL Analog Digital I/O. Parallel Slave Port data. Comparator 2 input (+). I/O I/O I ST TTL Analog Digital I/O. Parallel Slave Port data. Comparator 2 input (-). I/O I/O I/O O ST TTL ST TTL Digital I/O. Parallel Slave Port data. Capture2 input/Compare2 output/PWM2 output. ECCP1 PWM output A. I/O I/O O ST TTL TTL Digital I/O. Parallel Slave Port data. ECCP1 PWM output B. I/O I/O O ST TTL TTL Digital I/O. Parallel Slave Port data. ECCP1 PWM output C. I/O I/O O ST TTL TTL Digital I/O. Parallel Slave Port data. ECCP1 PWM output D. 39 40 41 2 3 4 5 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output DS39761B-page 20 CMOS = CMOS compatible input or output I = Input P = Power Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 1-3: PIC18F4682/4685 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP QFN Pin Buffer TQFP Type Type Description PORTE is a bidirectional I/O port. RE0/RD/AN5 RE0 RD 8 25 25 AN5 RE1/WR/AN6/C1OUT RE1 WR 9 26 10 27 ST TTL I Analog I/O I ST TTL I O Analog TTL I/O I ST TTL I O Analog TTL Digital I/O. Read control for Parallel Slave Port (see also WR and CS pins). Analog input 5. 26 AN6 C1OUT RE2/CS/AN7/C2OUT RE2 CS I/O I Digital I/O. Write control for Parallel Slave Port (see CS and RD pins). Analog input 6. Comparator 1 output. 27 AN7 C2OUT Digital I/O. Chip select control for Parallel Slave Port (see related RD and WR pins). Analog input 7. Comparator 2 output. RE3 -- -- -- -- -- See MCLR/VPP/RE3 pin. VSS 12, 31 6, 30, 31 6, 29 P -- Ground reference for logic and I/O pins. VDD 11, 32 7, 8, 28, 29 7, 28 P -- Positive supply for logic and I/O pins. NC -- 13 12, 13, 33, 34 -- -- No connect. Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output (c) 2007 Microchip Technology Inc. CMOS = CMOS compatible input or output I = Input P = Power Preliminary DS39761B-page 21 PIC18F2682/2685/4682/4685 NOTES: DS39761B-page 22 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 2.0 OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types FIGURE 2-1: C1(1) PIC18F2682/2685/4682/4685 devices can be operated in ten different oscillator modes. The user can program the Configuration bits, FOSC3:FOSC0, in Configuration Register 1H to select one of these ten modes: 1. 2. 3. 4. LP XT HS HSPLL Low-Power Crystal Crystal/Resonator High-Speed Crystal/Resonator High-Speed Crystal/Resonator with PLL enabled 5. RC External Resistor/Capacitor with FOSC/4 output on RA6 6. RCIO External Resistor/Capacitor with I/O on RA6 7. INTIO1 Internal Oscillator with FOSC/4 output on RA6 and I/O on RA7 8. INTIO2 Internal Oscillator with I/O on RA6 and RA7 9. EC External Clock with FOSC/4 output 10. ECIO External Clock with I/O on RA6 2.2 OSC1 XTAL To Internal Logic RF(3) Sleep RS(2) C2(1) PIC18FXXXX OSC2 Note 1:See Table 2-1 and Table 2-2 for initial values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the oscillator mode chosen. TABLE 2-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS Typical Capacitor Values Used: Mode Freq OSC1 OSC2 XT 455 kHz 2.0 MHz 4.0 MHz 56 pF 47 pF 33 pF 56 pF 47 pF 33 pF HS 8.0 MHz 16.0 MHz 27 pF 22 pF 27 pF 22 pF Crystal Oscillator/Ceramic Resonators In XT, LP, HS or HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-1 shows the pin connections. The oscillator design requires the use of a parallel cut crystal. Note: CRYSTAL/CERAMIC RESONATOR OPERATION (XT, LP, HS OR HSPLL CONFIGURATION) Use of a series cut crystal may give a frequency out of the crystal manufacturer's specifications. Capacitor values are for design guidance only. These capacitors were tested with the resonators listed below for basic start-up and operation. These values are not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes on page 24 for additional information. Resonators Used: 455 kHz 4.0 MHz 2.0 MHz 8.0 MHz 16.0 MHz Note: (c) 2007 Microchip Technology Inc. Preliminary When using resonators with frequencies above 3.5 MHz, the use of HS mode, rather than XT mode, is recommended. HS mode may be used at any VDD for which the controller is rated. If HS is selected, it is possible that the gain of the oscillator will overdrive the resonator. Therefore, a series resistor should be placed between the OSC2 pin and the resonator. As a good starting point, the recommended value of RS is 330. DS39761B-page 23 PIC18F2682/2685/4682/4685 TABLE 2-2: Osc Type LP XT HS CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq Typical Capacitor Values Tested: C1 C2 32 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF 1 MHz 33 pF 33 pF 4 MHz 27 pF 27 pF 4 MHz 27 pF 27 pF 8 MHz 22 pF 22 pF 20 MHz 15 pF 15 pF FIGURE 2-2: EXTERNAL CLOCK INPUT OPERATION (HS OSCILLATOR CONFIGURATION) OSC1 Clock from Ext. System PIC18FXXXX Open 2.3 Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following this table for additional information. Crystals Used: 32 kHz An external clock source may also be connected to the OSC1 pin in the HS mode, as shown in Figure 2-2. External Clock Input The EC and ECIO Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-3 shows the pin connections for the EC Oscillator mode. FIGURE 2-3: EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) 4 MHz 200 kHz 8 MHz 1 MHz 20 MHz OSC1/CLKI Clock from Ext. System Note 1: Higher capacitance increases the stability of the oscillator but also increases the start-up time. 2: When operating below 3V VDD, or when using certain ceramic resonators at any voltage, it may be necessary to use the HS mode or switch to a crystal oscillator. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Rs may be required to avoid overdriving crystals with low drive level specifications. 5: Always verify oscillator performance over the VDD and temperature range that is expected for the application. DS39761B-page 24 (HS Mode) OSC2 PIC18FXXXX FOSC/4 OSC2/CLKO The ECIO Oscillator mode functions like the EC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). Figure 2-4 shows the pin connections for the ECIO Oscillator mode. FIGURE 2-4: EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1/CLKI Clock from Ext. System Preliminary PIC18FXXXX RA6 I/O (OSC2) (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 2.4 RC Oscillator 2.5 For timing insensitive applications, the "RC" and "RCIO" device options offer additional cost savings. The actual oscillator frequency is a function of several factors: * supply voltage * values of the external resistor (REXT) and capacitor (CEXT) * operating temperature A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals or users who require higher clock speeds from an internal oscillator. 2.5.1 Given the same device, operating voltage and temperature and component values, there will also be unit-to-unit frequency variations. These are due to factors such as: * normal manufacturing variation * difference in lead frame capacitance between package types (especially for low CEXT values) * variations within the tolerance of limits of REXT and CEXT The HSPLL mode makes use of the HS mode oscillator for frequencies up to 10 MHz. A PLL then multiplies the oscillator output frequency by 4 to produce an internal clock frequency up to 40 MHz. FIGURE 2-7: PLL BLOCK DIAGRAM (HS MODE) HS Osc Enable PLL Enable (from Configuration Register 1H) RC OSCILLATOR MODE OSC2 VDD HS Mode OSC1 Crystal Osc REXT OSC1 HSPLL OSCILLATOR MODE The PLL is only available to the crystal oscillator when the FOSC3:FOSC0 Configuration bits are programmed for HSPLL mode (= 0110). In the RC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-5 shows how the R/C combination is connected. FIGURE 2-5: PLL Frequency Multiplier Internal Clock FIN Phase Comparator FOUT Loop Filter CEXT PIC18FXXXX VSS OSC2/CLKO /4 VCO MUX FOSC/4 Recommended values: 3 k REXT 100 k CEXT > 20 pF The RCIO Oscillator mode (Figure 2-6) functions like the RC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). FIGURE 2-6: RCIO OSCILLATOR MODE VDD REXT OSC1 2.5.2 SYSCLK PLL AND INTOSC The PLL is also available to the internal oscillator block in selected oscillator modes. In this configuration, the PLL is enabled in software and generates a clock output of up to 32 MHz. The operation of INTOSC with the PLL is described in Section 2.6.4 "PLL in INTOSC Modes". Internal Clock CEXT PIC18FXXXX VSS RA6 I/O (OSC2) Recommended values: 3 k REXT 100 k CEXT > 20 pF (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 25 PIC18F2682/2685/4682/4685 2.6 Internal Oscillator Block The PIC18F2682/2685/4682/4685 devices include an internal oscillator block which generates two different clock signals; either can be used as the microcontroller's clock source. This may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC) is an 8 MHz clock source, which can be used to directly drive the device clock. It also drives a postscaler, which can provide a range of clock frequencies from 31 kHz to 4 MHz. The INTOSC output is enabled when a clock frequency from 125 kHz to 8 MHz is selected. The other clock source is the internal RC oscillator (INTRC), which provides a nominal 31 kHz output. INTRC is enabled if it is selected as the device clock source; it is also enabled automatically when any of the following are enabled: * * * * Power-up Timer Fail-Safe Clock Monitor Watchdog Timer Two-Speed Start-up These features are discussed in greater detail in Section 24.0 "Special Features of the CPU". The clock source frequency (INTOSC direct, INTRC direct or INTOSC postscaler) is selected by configuring the IRCF bits of the OSCCON register (Register 2-2). 2.6.1 INTIO MODES Using the internal oscillator as the clock source eliminates the need for up to two external oscillator pins, which can then be used for digital I/O. Two distinct configurations are available: * In INTIO1 mode, the OSC2 pin outputs FOSC/4, while OSC1 functions as RA7 for digital input and output. * In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output. 2.6.2 INTOSC OUTPUT FREQUENCY The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of 8.0 MHz. The INTRC oscillator operates independently of the INTOSC source. Any changes in INTOSC across voltage and temperature are not necessarily reflected by changes in INTRC and vice versa. 2.6.3 OSCTUNE REGISTER The internal oscillator's output has been calibrated at the factory but can be adjusted in the user's application. This is done by writing to the OSCTUNE register (Register 2-1). The tuning sensitivity is constant throughout the tuning range. DS39761B-page 26 When the OSCTUNE register is modified, the INTOSC and INTRC frequencies will begin shifting to the new frequency. The INTRC clock will reach the new frequency within 8 clock cycles (approximately 8 * 32 s = 256 s). The INTOSC clock will stabilize within 1 ms. Code execution continues during this shift. There is no indication that the shift has occurred. The OSCTUNE register also implements the INTSRC and PLLEN bits, which control certain features of the internal oscillator block. The INTSRC bit allows users to select which internal oscillator provides the clock source when the 31 kHz frequency option is selected. This is covered in greater detail in Section 2.7.1 "Oscillator Control Register". The PLLEN bit controls the operation of the frequency multiplier, PLL, in internal oscillator modes. 2.6.4 PLL IN INTOSC MODES The 4x frequency multiplier can be used with the internal oscillator block to produce faster device clock speeds than are normally possible with an internal oscillator. When enabled, the PLL produces a clock speed of up to 32 MHz. Unlike HSPLL mode, the PLL is controlled through software. The control bit, PLLEN (OSCTUNE<6>), is used to enable or disable its operation. The PLL is available when the device is configured to use the internal oscillator block as its primary clock source (FOSC3:FOSC0 = 1001 or 1000). Additionally, the PLL will only function when the selected output frequency is either 4 MHz or 8 MHz (OSCCON<6:4> = 111 or 110). If both of these conditions are not met, the PLL is disabled. The PLLEN control bit is only functional in those internal oscillator modes where the PLL is available. In all other modes, it is forced to `0' and is effectively unavailable. 2.6.5 INTOSC FREQUENCY DRIFT The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz. However, this frequency may drift as VDD or temperature changes, which can affect the controller operation in a variety of ways. It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register. This has no effect on the INTRC clock source frequency. Tuning the INTOSC source requires knowing when to make the adjustment, in which direction it should be made and in some cases, how large a change is needed. Three compensation techniques are discussed in Section 2.6.5.1 "Compensating with the EUSART", Section 2.6.5.2 "Compensating with the Timers" and Section 2.6.5.3 "Compensating with the CCP1 Module in Capture Mode", but other techniques may be used. Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0(1) R/W-0 INTSRC PLLEN (1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled) 0 = 31 kHz device clock derived directly from INTRC internal oscillator bit 6 PLLEN: Frequency Multiplier PLL for INTOSC Enable bit(1) 1 = PLL enabled for INTOSC (4 MHz and 8 MHz only) 0 = PLL disabled bit 5 Unimplemented: Read as `0 bit 4-0 TUN4:TUN0: Frequency Tuning bits 01111 = Maximum frequency * * * * 00001 00000 = Center frequency. Oscillator module is running at the calibrated frequency. 11111 * * * * 10000 = Minimum frequency Note 1: 2.6.5.1 Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as `0'. See text for details. Compensating with the EUSART 2.6.5.3 An adjustment may be required when the EUSART begins to generate framing errors or receives data with errors while in Asynchronous mode. Framing errors indicate that the device clock frequency is too high. To adjust for this, decrement the value in OSCTUNE to reduce the clock frequency. On the other hand, errors in data may suggest that the clock speed is too low. To compensate, increment OSCTUNE to increase the clock frequency. 2.6.5.2 Compensating with the Timers This technique compares device clock speed to some reference clock. Two timers may be used; one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the Timer1 oscillator. Both timers are cleared, but the timer clocked by the reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. (c) 2007 Microchip Technology Inc. Compensating with the CCP1 Module in Capture Mode The CCP1 module can use free running Timer1 (or Timer3), clocked by the internal oscillator block and an external event with a known period (i.e., AC power frequency). The time of the first event is captured in the CCPRxH:CCPRxL registers and is recorded for use later. When the second event causes a capture, the time of the first event is subtracted from the time of the second event. Since the period of the external event is known, the time difference between events can be calculated. If the measured time is much greater than the calculated time, the internal oscillator block is running too fast. To compensate, decrement the OSCTUNE register. If the measured time is much less than the calculated time, the internal oscillator block is running too slow. To compensate, increment the OSCTUNE register. Preliminary DS39761B-page 27 PIC18F2682/2685/4682/4685 2.7 Clock Sources and Oscillator Switching Like previous PIC18 devices, the PIC18F2682/2685/ 4682/4685 family includes a feature that allows the device clock source to be switched from the main oscillator to an alternate low-frequency clock source. PIC18F2682/2685/4682/4685 devices offer two alternate clock sources. When an alternate clock source is enabled, the various power-managed operating modes are available. Essentially, there are three clock sources for these devices: PIC18F2682/2685/4682/4685 devices offer the Timer1 oscillator as a secondary oscillator. In all powermanaged modes, this oscillator is often the time base for functions such as a Real-Time Clock. Most often, a 32.768 kHz watch crystal is connected between the RC0/T1OSO/T13CKI and RC1/T1OSI pins. Like the LP mode oscillator circuit, loading capacitors are also connected from each pin to ground. The Timer1 oscillator is discussed in greater detail in Section 12.3 "Timer1 Oscillator". * Primary oscillators * Secondary oscillators * Internal oscillator block The primary oscillators include the External Crystal and Resonator modes, the External RC modes, the External Clock modes and the internal oscillator block. The particular mode is defined by the FOSC3:FOSC0 Configuration bits. The details of these modes are covered earlier in this chapter. FIGURE 2-8: The secondary oscillators are those external sources not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power-managed mode. In addition to being a primary clock source, the internal oscillator block is available as a power-managed mode clock source. The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F2682/2685/4682/4685 devices are shown in Figure 2-8. See Section 24.0 "Special Features of the CPU" for Configuration register details. PIC18F2682/2685/4682/4685 CLOCK DIAGRAM PIC18F2682/2685/4682/4685 Primary Oscillator LP, XT, HS, RC, EC OSC2 Sleep 4 x PLL OSC1 OSCTUNE<6> Secondary Oscillator T1OSCEN Enable Oscillator OSCCON<6:4> 2 MHz 8 MHz (INTOSC) 31 kHz (INTRC) Postscaler INTRC Source 4 MHz 1 MHz 500 kHz 250 kHz 125 kHz Internal Oscillator CPU 111 110 IDLEN 101 100 011 MUX 8 MHz OSCCON<6:4> Internal Oscillator Block 8 MHz Source Peripherals MUX T1OSC T1OSO T1OSI HSPLL, INTOSC/PLL 010 001 1 31 kHz 000 0 Clock Control FOSC3:FOSC0 OSCCON<1:0> Clock Source Option for other Modules OSCTUNE<7> WDT, PWRT, FSCM and Two-Speed Startup DS39761B-page 28 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 2.7.1 OSCILLATOR CONTROL REGISTER The OSCCON register (Register 2-2) controls several aspects of the device clock's operation, both in full power operation and in power-managed modes. The System Clock Select bits, SCS1:SCS0, select the clock source. The available clock sources are the primary clock (defined by the FOSC3:FOSC0 Configuration bits), the secondary clock (Timer1 oscillator) and the internal oscillator block. The clock source changes immediately after one or more of the bits is written to, following a brief clock transition interval. The SCS bits are cleared on all forms of Reset. The Internal Oscillator Frequency Select bits, IRCF2:IRCF0, select the frequency output of the internal oscillator block to drive the device clock. The choices are the INTRC source, the INTOSC source (8 MHz) or one of the frequencies derived from the INTOSC postscaler (31 kHz to 4 MHz). If the internal oscillator block is supplying the device clock, changing the states of these bits will have an immediate change on the internal oscillator's output. On device Resets, the default output frequency of the internal oscillator block is set at 1 MHz. When an output frequency of 31 kHz is selected (IRCF2:IRCF0 = 000), users may choose which internal oscillator acts as the source. This is done with the INTSRC bit in the OSCTUNE register (OSCTUNE<7>). Setting this bit selects INTOSC as a 31.25 kHz clock source by enabling the divide-by-256 output of the INTOSC postscaler. Clearing INTSRC selects INTRC (nominally 31 kHz) as the clock source. The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed. The use of the flag and control bits in the OSCCON register is discussed in more detail in Section 3.0 "Power-Managed Modes". Note 1: The Timer1 oscillator must be enabled to select the secondary clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON<3>). If the Timer1 oscillator is not enabled, then any attempt to select a secondary clock source when executing a SLEEP instruction will be ignored. 2: It is recommended that the Timer1 oscillator be operating and stable before executing the SLEEP instruction, or a very long delay may occur while the Timer1 oscillator starts. 2.7.2 OSCILLATOR TRANSITIONS PIC18F2682/2685/4682/4685 devices contain circuitry to prevent clock "glitches" when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Clock transitions are discussed in greater detail in Section 3.1.2 "Entering Power-Managed Modes". This option allows users to select the tunable and more precise INTOSC as a clock source, while maintaining power savings with a very low clock speed. Regardless of the setting of INTSRC, INTRC always remains the clock source for features such as the Watchdog Timer and the Fail-Safe Clock Monitor. The OSTS, IOFS and T1RUN bits indicate which clock source is currently providing the device clock. The OSTS bit indicates that the Oscillator Start-up Timer has timed out and the primary clock is providing the device clock in primary clock modes. The IOFS bit indicates when the internal oscillator block has stabilized and is providing the device clock in RC Clock modes. The T1RUN bit (T1CON<6>) indicates when the Timer1 oscillator is providing the device clock in secondary clock modes. In power-managed modes, only one of these three bits will be set at any time. If none of these bits are set, the INTRC is providing the clock or the internal oscillator block has just started and is not yet stable. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 29 PIC18F2682/2685/4682/4685 REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits 111 = 8 MHz (INTOSC drives clock directly) 110 = 4 MHz 101 = 2 MHz 100 = 1 MHz(3) 011 = 500 kHz 010 = 250 kHz 001 = 125 kHz 000 = 31 kHz (from either INTOSC/256 or INTRC directly)(2) bit 3 OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready bit 2 IOFS: INTOSC Frequency Stable bit 1 = INTOSC frequency is stable and the frequency is provided by one of the RC modes 0 = INTOSC frequency is not stable bit 1-0 SCS1:SCS0: System Clock Select bits 1x = Internal oscillator block 01 = Timer1 oscillator 00 = Primary oscillator Note 1: 2: 3: Depends on state of the IESO Configuration bit. Source selected by the INTSRC bit (OSCTUNE<7>), see text. Default output frequency of INTOSC on Reset. DS39761B-page 30 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 2.8 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin, if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the device clock. The Timer1 oscillator may also run in all power-managed modes if required to clock Timer1 or Timer3. In internal oscillator modes (RC_RUN and RC_IDLE), the internal oscillator block provides the device clock source. The 31 kHz INTRC output can be used directly to provide the clock and may be enabled to support various special features, regardless of the powermanaged mode (see Section 24.2 "Watchdog Timer (WDT)", Section 24.3 "Two-Speed Start-up" and Section 24.4 "Fail-Safe Clock Monitor" for more information on WDT, Two-Speed Start-up and Fail-Safe Clock Monitor). The INTOSC output at 8 MHz may be used directly to clock the device or may be divided down by the postscaler. The INTOSC output is disabled if the clock is provided directly from the INTRC output. If the Sleep mode is selected, all clock sources are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The INTRC is required to support WDT operation. The Timer1 oscillator may be operating to support TABLE 2-3: a Real-Time Clock. Other features may be operating that do not require a device clock source (i.e., MSSP slave, PSP, INTx pins and others). Peripherals that may add significant current consumption are listed in Section 27.2 "DC Characteristics: Power-Down and Supply Current". 2.9 Power-up Delays Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply is stable under normal circumstances and the primary clock is operating and stable. For additional information on power-up delays, see Section 4.5 "Device Reset Timers". The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up (parameter 33, Table 27-10). It is enabled by clearing (= 0) the PWRTEN Configuration bit. The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (LP, XT and HS modes). The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. When the HSPLL Oscillator mode is selected, the device is kept in Reset for an additional 2 ms, following the HS mode OST delay, so the PLL can lock to the incoming clock frequency. There is a delay of interval TCSD (parameter 38, Table 27-10), following POR, while the controller becomes ready to execute instructions. This delay runs concurrently with any other delays. This may be the only delay that occurs when any of the EC, RC or INTIO modes are used as the primary clock source. OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode OSC1 Pin OSC2 Pin RC, INTIO1 Floating, external resistor should pull high At logic low (clock/4 output) RCIO, INTIO2 Floating, external resistor should pull high Configured as PORTA, bit 6 ECIO Floating, pulled by external clock Configured as PORTA, bit 6 EC Floating, pulled by external clock At logic low (clock/4 output) LP, XT and HS Feedback inverter disabled at quiescent voltage level Feedback inverter disabled at quiescent voltage level Note: See Table 4-2 in Section 4.0 "Reset" for time-outs due to Sleep and MCLR Reset. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 31 PIC18F2682/2685/4682/4685 NOTES: DS39761B-page 32 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 3.0 POWER-MANAGED MODES 3.1.1 PIC18F2682/2685/4682/4685 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: * The primary clock as defined by the FOSC3:FOSC0 Configuration bits * The secondary clock (the Timer1 oscillator) * The internal oscillator block (for RC modes) There are three categories of power-managed modes: 3.1.2 * Run modes * Idle modes * Sleep mode These categories define which portions of the device are clocked and sometimes, what speed. The Run and Idle modes may use any of the three available clock sources (primary, secondary or internal oscillator block); the Sleep mode does not use a clock source. The power-managed modes include several power saving features offered on previous PIC(R) devices. One is the clock switching feature, offered in other PIC18 devices, allowing the controller to use the Timer1 oscillator in place of the primary oscillator. Also included is the Sleep mode, offered by all PIC devices, where all device clocks are stopped. 3.1 Selecting Power-Managed Modes Selecting a power-managed mode requires two decisions: if the CPU is to be clocked or not and the selection of a clock source. The IDLEN bit (OSCCON<7>) controls CPU clocking, while the SCS1:SCS0 bits (OSCCON<1:0>) select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 3-1. TABLE 3-1: IDLEN<7>(1) SCS1:SCS0<1:0> Sleep Switching from one power-managed mode to another begins by loading the OSCCON register. The SCS1:SCS0 bits select the clock source and determine which Run or Idle mode is to be used. Changing these bits causes an immediate switch to the new clock source, assuming that it is running. The switch may also be subject to clock transition delays. These are discussed in Section 3.1.3 "Clock Transitions And Status Indicators" and subsequent sections. Entry to the power-managed Idle or Sleep modes is triggered by the execution of a SLEEP instruction. The actual mode that results depends on the status of the IDLEN bit. Depending on the current mode and the mode being switched to, a change to a power-managed mode does not always require setting all of these bits. Many transitions may be done by changing the oscillator select bits, or changing the IDLEN bit, prior to issuing a SLEEP instruction. If the IDLEN bit is already configured correctly, it may only be necessary to perform a SLEEP instruction to switch to the desired mode. POWER-MANAGED MODES OSCCON Bits Mode ENTERING POWER-MANAGED MODES Module Clocking Available Clock and Oscillator Source CPU Peripherals 0 N/A Off Off PRI_RUN N/A 00 Clocked Clocked SEC_RUN N/A 01 Clocked Clocked Secondary - Timer1 Oscillator RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block(2) PRI_IDLE 1 00 Off Clocked Primary - LP, XT, HS, HSPLL, RC, EC SEC_IDLE 1 01 Off Clocked Secondary - Timer1 Oscillator RC_IDLE 1 1x Off Clocked Internal Oscillator Block(2) Note 1: 2: None - all clocks are disabled Primary - LP, XT, HS, HSPLL, RC, EC, INTRC: this is the normal full power execution mode(2) IDLEN reflects its value when the SLEEP instruction is executed. Includes INTOSC and INTOSC postscaler, as well as the INTRC source. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 33 PIC18F2682/2685/4682/4685 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: * OSTS (OSCCON<3>) * IOFS (OSCCON<2>) * T1RUN (T1CON<6>) In general, only one of these bits will be set while in a given power-managed mode. When the OSTS bit is set, the primary clock is providing the device clock. When the IOFS bit is set, the INTOSC output is providing a stable 8 MHz clock source to a divider that actually drives the device clock. When the T1RUN bit is set, the Timer1 oscillator is providing the clock. If none of these bits are set, then either the INTRC clock source is clocking the device, or the INTOSC source is not yet stable. If the internal oscillator block is configured as the primary clock source by the FOSC3:FOSC0 Configuration bits, then both the OSTS and IOFS bits may be set when in PRI_RUN or PRI_IDLE modes. This indicates that the primary clock (INTOSC output) is generating a stable 8 MHz output. Entering another power-managed RC mode at the same frequency would clear the OSTS bit. 3.2 In the Run modes, clocks to both the core and peripherals are active. The difference between these modes is the clock source. 3.2.1 3.1.4 MULTIPLE SLEEP COMMANDS The power-managed mode that is invoked with the SLEEP instruction is determined by the setting of the IDLEN bit at the time the instruction is executed. If another SLEEP instruction is executed, the device will enter the power-managed mode specified by IDLEN at that time. If IDLEN has changed, the device will enter the new power-managed mode specified by the new setting. DS39761B-page 34 PRI_RUN MODE The PRI_RUN mode is the normal, full power execution mode of the microcontroller. This is also the default mode upon a device Reset, unless Two-Speed Start-up is enabled (see Section 24.3 "Two-Speed Start-up" for details). In this mode, the OSTS bit is set. The IOFS bit may be set if the internal oscillator block is the primary clock source (see Section 2.7.1 "Oscillator Control Register"). 3.2.2 SEC_RUN MODE The SEC_RUN mode is the compatible mode to the "clock switching" feature offered in other PIC18 devices. In this mode, the CPU and peripherals are clocked from the Timer1 oscillator. This gives users the option of lower power consumption while still using a high accuracy clock source. SEC_RUN mode is entered by setting the SCS1:SCS0 bits to `01'. The device clock source is switched to the Timer1 oscillator (see Figure 3-1), the primary oscillator is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared. Note: Note 1: Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated. 2: Executing a SLEEP instruction does not necessarily place the device into Sleep mode. It acts as the trigger to place the controller into either the Sleep mode or one of the Idle modes, depending on the setting of the IDLEN bit. Run Modes The Timer1 oscillator should already be running prior to entering SEC_RUN mode. If the T1OSCEN bit is not set when the SCS1:SCS0 bits are set to `01', entry to SEC_RUN mode will not occur. If the Timer1 oscillator is enabled but not yet running, device clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. On transitions from SEC_RUN to PRI_RUN mode, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 T1OSI Q2 1 2 n-1 3 Q3 Q4 Q1 Q2 Q3 n Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC FIGURE 3-2: PC + 2 PC + 4 TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI OSC1 TOST(1) TPLL(1) 1 PLL Clock Output 2 n-1 n Clock Transition CPU Clock Peripheral Clock Program Counter SCS1:SCS0 bits Changed PC PC + 2 PC + 4 OSTS bit Set Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 3.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer; the primary clock is shut down. When using the INTRC source, this mode provides the best power conservation of all the Run modes, while still executing code. It works well for user applications which are not highly timing sensitive or do not require high-speed clocks at all times. If the primary clock source is the internal oscillator block (either INTRC or INTOSC), there are no distinguishable differences between PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. This mode is entered by setting SCS1 to `1'. Although it is ignored, it is recommended that SCS0 also be cleared; this is to maintain software compatibility with future devices. When the clock source is switched to (c) 2007 Microchip Technology Inc. the INTOSC multiplexer (see Figure 3-3), the primary oscillator is shut down and the OSTS bit is cleared. The IRCF bits may be modified at any time to immediately change the clock speed. Note: Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated. If the IRCF bits and the INTSRC bit are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the device clocks. If the IRCF bits are changed from all clear (thus, enabling the INTOSC output) or if INTSRC is set, the IOFS bit becomes set after the INTOSC output becomes stable. Clocks to the device continue while the INTOSC source stabilizes after an interval of TIOBST. Preliminary DS39761B-page 35 PIC18F2682/2685/4682/4685 If the IRCF bits were previously at a non-zero value or if INTSRC was set before setting SCS1 and the INTOSC source was already stable, the IOFS bit will remain set. primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 3-4). When the clock switch is complete, the IOFS bit is cleared, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 1 INTRC 2 3 n-1 Q3 Q4 Q1 Q2 Q3 n Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC FIGURE 3-4: PC + 2 PC + 4 TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q2 Q3 Q4 Q1 Q2 Q3 Q1 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 PLL Clock Output 2 n-1 n Clock Transition CPU Clock Peripheral Clock Program Counter SCS1:SCS0 bits Changed PC PC + 2 PC + 4 OSTS bit Set Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. DS39761B-page 36 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 3.3 Sleep Mode 3.4 The power-managed Sleep mode in the PIC18F2682/ 2685/4682/4685 devices is identical to the legacy Sleep mode offered in all other PIC devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 3-5). All clock source status bits are cleared. Entering the Sleep mode from any other mode does not require a clock switch. This is because no clocks are needed once the controller has entered Sleep. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS1:SCS0 bits becomes ready (see Figure 3-6), or it will be clocked from the internal oscillator block if either the Two-Speed Start-up or the Fail-Safe Clock Monitor are enabled (see Section 24.0 "Special Features of the CPU"). In either case, the OSTS bit is set when the primary clock is providing the device clocks. The IDLEN and SCS bits are not affected by the wake-up. Idle Modes The Idle modes allow the controller's CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a `1' when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS1:SCS0 bits; however, the CPU will not be clocked. The clock source status bits are not affected. Setting IDLEN and executing a SLEEP instruction provides a quick method of switching from a given Run mode to its corresponding Idle mode. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. Since the CPU is not executing instructions, the only exits from any of the Idle modes are by interrupt, WDT time-out or a Reset. When a wake event occurs, CPU execution is delayed by an interval of TCSD (parameter 38, Table 27-10) while it becomes ready to execute code. When the CPU begins executing code, it resumes with the same clock source for the current Idle mode. For example, when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or the Sleep mode, a WDT timeout will result in a WDT wake-up to the Run mode currently specified by the SCS1:SCS0 bits. FIGURE 3-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC FIGURE 3-6: PC + 2 TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 OSC1 TOST(1) PLL Clock Output TPLL(1) CPU Clock Peripheral Clock Program Counter PC Wake Event PC + 2 PC + 4 PC + 6 OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 37 PIC18F2682/2685/4682/4685 3.4.1 PRI_IDLE MODE 3.4.2 This mode is unique among the three low-power Idle modes in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to "warm up" or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then clear the SCS bits and execute SLEEP. Although the CPU is disabled, the peripherals continue to be clocked from the primary clock source specified by the FOSC3:FOSC0 Configuration bits. The OSTS bit remains set (see Figure 3-7). When a wake event occurs, the CPU is clocked from the primary clock source. A delay of interval TCSD is required between the wake event and when code execution starts. This is required to allow the CPU to become ready to execute instructions. After the wakeup, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure 3-8). FIGURE 3-7: SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered from SEC_RUN by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set the IDLEN bit first, then set the SCS1:SCS0 bits to `01' and execute SLEEP. When the clock source is switched to the Timer1 oscillator, the primary oscillator is shut down, the OSTS bit is cleared and the T1RUN bit is set. When a wake event occurs, the peripherals continue to be clocked from the Timer1 oscillator. After an interval of TCSD following the wake event, the CPU begins executing code being clocked by the Timer1 oscillator. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run (see Figure 3-8). Note: The Timer1 oscillator should already be running prior to entering SEC_IDLE mode. If the T1OSCEN bit is not set when the SLEEP instruction is executed, the SLEEP instruction will be ignored and entry to SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 Q3 Q2 Q4 Q1 OSC1 CPU Clock Peripheral Clock Program Counter PC FIGURE 3-8: PC + 2 TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 TCSD CPU Clock Peripheral Clock Program Counter PC Wake Event DS39761B-page 38 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 3.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then set the SCS1 bit and execute SLEEP. Although its value is ignored, it is recommended that SCS0 also be cleared; this is to maintain software compatibility with future devices. The INTOSC multiplexer may be used to select a higher clock frequency, by modifying the IRCF bits, before executing the SLEEP instruction. When the clock source is switched to the INTOSC multiplexer, the primary oscillator is shut down and the OSTS bit is cleared. If the IRCF bits are set to any non-zero value or the INTSRC bit is set, the INTOSC output is enabled. The IOFS bit becomes set, after the INTOSC output becomes stable, after an interval of TIOBST (parameter 39, Table 27-10). Clocks to the peripherals continue while the INTOSC source stabilizes. If the IRCF bits were previously at a non-zero value, or INTSRC was set before the SLEEP instruction was executed and the INTOSC source was already stable, the IOFS bit will remain set. If the IRCF bits and INTSRC are all clear, the INTOSC output will not be enabled, the IOFS bit will remain clear and there will be no indication of the current clock source. When a wake event occurs, the peripherals continue to be clocked from the INTOSC multiplexer. After a delay of TCSD following the wake event, the CPU begins executing code being clocked by the INTOSC multiplexer. The IDLEN and SCS bits are not affected by the wake-up. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. 3.5 Exiting Idle and Sleep Modes An exit from Sleep mode or any of the Idle modes is triggered by an interrupt, a Reset or a WDT time-out. This section discusses the triggers that cause exits from power-managed modes. The clocking subsystem actions are discussed in each of the power-managed modes (see Section 3.2 "Run Modes", Section 3.3 "Sleep Mode" and Section 3.4 "Idle Modes"). 3.5.1 EXIT BY INTERRUPT Any of the available interrupt sources can cause the device to exit from an Idle mode or the Sleep mode to a Run mode. To enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. (c) 2007 Microchip Technology Inc. On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 9.0 "Interrupts"). A fixed delay of interval TCSD following the wake event is required when leaving the Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. 3.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs. If the device is not executing code (all Idle modes and Sleep mode), the time-out will result in an exit from the power-managed mode (see Section 3.2 "Run Modes" and Section 3.3 "Sleep Mode"). If the device is executing code (all Run modes), the time-out will result in a WDT Reset (see Section 24.2 "Watchdog Timer (WDT)"). The WDT timer and postscaler are cleared by executing a SLEEP or CLRWDT instruction, the loss of a currently selected clock source (if the Fail-Safe Clock Monitor is enabled) and modifying the IRCF bits in the OSCCON register if the internal oscillator block is the device clock source. 3.5.3 EXIT BY RESET Normally, the device is held in Reset by the Oscillator Start-up Timer (OST) until the primary clock becomes ready. At that time, the OSTS bit is set and the device begins executing code. If the internal oscillator block is the new clock source, the IOFS bit is set instead. The exit delay time from Reset to the start of code execution depends on both the clock sources before and after the wake-up and the type of oscillator if the new clock source is the primary clock. Exit delays are summarized in Table 3-2. Code execution can begin before the primary clock becomes ready. If either the Two-Speed Start-up (see Section 24.3 "Two-Speed Start-up") or Fail-Safe Clock Monitor (see Section 24.4 "Fail-Safe Clock Monitor") is enabled, the device may begin execution as soon as the Reset source has cleared. Execution is clocked by the INTOSC multiplexer driven by the internal oscillator block. Execution is clocked by the internal oscillator block until either the primary clock becomes ready or a power-managed mode is entered before the primary clock becomes ready; the primary clock is then shut down. Preliminary DS39761B-page 39 PIC18F2682/2685/4682/4685 3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. There are two cases: * PRI_IDLE mode where the primary clock source is not stopped * The primary clock source is not any of the LP, XT, HS or HSPLL modes TABLE 3-2: In these instances, the primary clock source either does not require an oscillator start-up delay, since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (RC, EC and INTIO Oscillator modes). However, a fixed delay of interval TCSD following the wake event is still required when leaving the Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Clock Source Before Wake-up Clock Source After Wake-up Exit Delay Clock Ready Status Bit (OSCCON) LP, XT, HS HSPLL Primary Device Clock (PRI_IDLE mode) EC, RC OSTS TCSD(2) INTRC(1) -- INTOSC(3) (1) T1OSC or INTRC TOST(4) HSPLL TOST + trc(4) EC, RC INTRC(1) (3) INTOSC TIOBST(5) LP, XT, HS TOST(4) HSPLL TOST + trc(4) EC, RC INTOSC (3) 3: 4: 5: TCSD(2) None LP, XT, HS TOST(4) HSPLL TOST + trc(4) EC, RC INTRC(1) INTOSC(3) Note 1: 2: TCSD(2) INTOSC(3) INTRC(1) None (Sleep mode) IOFS LP, XT, HS TCSD(2) TIOBST(5) OSTS -- IOFS OSTS -- IOFS OSTS -- IOFS In this instance, refers specifically to the 31 kHz INTRC clock source. TCSD (parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently with any other required delays (see Section 3.4 "Idle Modes"). Includes both the INTOSC 8 MHz source and postscaler derived frequencies. TOST is the Oscillator Start-up Timer (parameter 32). trc is the PLL Lock-out Timer (parameter F12); it is also designated as TPLL. Execution continues during TIOBST (parameter 39), the INTOSC stabilization period. DS39761B-page 40 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 4.0 RESET A simplified block diagram of the on-chip Reset circuit is shown in Figure 4-1. The PIC18F2682/2685/4682/4685 devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during power-managed modes Watchdog Timer (WDT) Reset during execution Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset This section discusses Resets generated by MCLR, POR and BOR and covers the operation of the various start-up timers. Stack Reset events are covered in Section 5.1.2.4 "Stack Full and Underflow Resets". WDT Resets are covered in Section 24.2 "Watchdog Timer (WDT)". FIGURE 4-1: 4.1 RCON Register Device Reset events are tracked through the RCON register (Register 4-1). The lower five bits of the register indicate that a specific Reset event has occurred. In most cases, these bits can only be cleared by the event and must be set by the application after the event. The state of these flag bits, taken together, can be read to indicate the type of Reset that just occurred. This is described in more detail in Section 4.6 "Reset State of Registers". The RCON register also has control bits for setting interrupt priority (IPEN) and software control of the BOR (SBOREN). Interrupt priority is discussed in Section 9.0 "Interrupts". BOR is covered in Section 4.4 "Brown-out Reset (BOR)". SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Stack Full/Underflow Reset Stack Pointer External Reset MCLR MCLRE ( )_IDLE Sleep WDT Time-out VDD Rise Detect POR Pulse VDD Brown-out Reset S BOREN OST/PWRT OST 1024 Cycles 10-Bit Ripple Counter R OSC1 32 s INTRC(1) PWRT Q Chip_Reset 65.5 ms 11-Bit Ripple Counter Enable PWRT Enable OST(2) Note 1: 2: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. See Table 4-2 for time-out situations. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 41 PIC18F2682/2685/4682/4685 REGISTER 4-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0 IPEN SBOREN -- RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit(1) If BOREN1:BOREN0 = 01: 1 = BOR is enabled 0 = BOR is disabled If BOREN1:BOREN0 = 00, 10 or 11: Bit is disabled and read as `0'. bit 5 Unimplemented: Read as `0' bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-Down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: 2: If SBOREN is enabled, its Reset state is `1'; otherwise, it is `0'. The actual Reset value of POR is determined by the type of device Reset. See the notes following this register and Section 4.6 "Reset State of Registers" for additional information. Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected. 2: Brown-out Reset is said to have occurred when BOR is `0' and POR is `1' (assuming that POR was set to `1' by software immediately after a Power-on Reset). DS39761B-page 42 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 4.2 Master Clear Reset (MCLR) The MCLR pin provides a method for triggering an external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. The MCLR pin is not driven low by any internal Resets, including the WDT. POR events are captured by the POR bit (RCON<1>). The state of the bit is set to `0' whenever a Power-on Reset occurs; it does not change for any other Reset event. POR is not reset to `1' by any hardware event. To capture multiple events, the user manually resets the bit to `1' in software following any Power-on Reset. FIGURE 4-2: In PIC18F2682/2685/4682/4685 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 10.5 "PORTE, TRISE and LATE Registers" for more information. 4.3 EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) VDD VDD D R R1 Power-on Reset (POR) MCLR A Power-on Reset pulse is generated on-chip whenever VDD rises above a certain threshold. This allows the device to start in the initialized state when VDD is adequate for operation. To take advantage of the POR circuitry, tie the MCLR pin through a resistor (1 k to 10 k) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (parameter D004). For a slow rise time, see Figure 4-2. C Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that the voltage drop across R does not violate the device's electrical specification. 3: R1 1 k will limit any current flowing into MCLR from external capacitor C, in the event of MCLR/VPP pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. (c) 2007 Microchip Technology Inc. PIC18FXXXX Preliminary DS39761B-page 43 PIC18F2682/2685/4682/4685 4.4 Brown-out Reset (BOR) PIC18F2682/2685/4682/4685 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV1:BORV0 and BOREN1:BOREN0 Configuration bits. There are a total of four BOR configurations which are summarized in Table 4-1. The BOR threshold is set by the BORV1:BORV0 bits. If BOR is enabled (any value of BOREN1:BOREN0, except `00'), any drop of VDD below VBOR (parameter D005) for greater than TBOR (parameter 35) will reset the device. A Reset may or may not occur if VDD falls below VBOR for less than TBOR. The chip will remain in Brown-out Reset until VDD rises above VBOR. If the Power-up Timer is enabled, it will be invoked after VDD rises above VBOR; it then will keep the chip in Reset for an additional time delay, TPWRT (parameter 33). If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above VBOR, the Power-up Timer will execute the additional time delay. BOR and the Power-on Timer (PWRT) are independently configured. Enabling Brown-out Reset does not automatically enable the PWRT. 4.4.1 SOFTWARE ENABLED BOR When BOREN1:BOREN0 = 01, the BOR can be enabled or disabled by the user in software. This is done with the control bit, SBOREN (RCON<6>). Setting SBOREN enables the BOR to function as previously described. Clearing SBOREN disables the BOR entirely. The SBOREN bit operates only in this mode; otherwise it is read as `0'. TABLE 4-1: Placing the BOR under software control gives the user the additional flexibility of tailoring the application to its environment without having to reprogram the device to change BOR configuration. It also allows the user to tailor device power consumption in software by eliminating the incremental current that the BOR consumes. While the BOR current is typically very small, it may have some impact in low-power applications. Note: 4.4.2 Even when BOR is under software control, the Brown-out Reset voltage level is still set by the BORV1:BORV0 Configuration bits. It cannot be changed in software. DETECTING BOR When BOR is enabled, the BOR bit always resets to `0' on any Brown-out Reset or Power-on Reset event. This makes it difficult to determine if a Brown-out Reset event has occurred just by reading the state of BOR alone. A more reliable method is to simultaneously check the state of both POR and BOR. This assumes that the POR bit is reset to `1' in software immediately after any Power-on Reset event. IF BOR is `0' while POR is `1', it can be reliably assumed that a Brown-out Reset event has occurred. 4.4.3 DISABLING BOR IN SLEEP MODE When BOREN1:BOREN0 = 10, the BOR remains under hardware control and operates as previously described. Whenever the device enters Sleep mode, however, the BOR is automatically disabled. When the device returns to any other operating mode, BOR is automatically re-enabled. This mode allows for applications to recover from brown-out situations, while actively executing code, when the device requires BOR protection the most. At the same time, it saves additional power in Sleep mode by eliminating the small incremental BOR current. BOR CONFIGURATIONS BOR Configuration BOREN1 BOREN0 Status of SBOREN (RCON<6>) 0 0 Unavailable 0 1 Available 1 0 Unavailable BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. 1 1 Unavailable BOR enabled in hardware; must be disabled by reprogramming the Configuration bits. DS39761B-page 44 BOR Operation BOR disabled; must be enabled by reprogramming the Configuration bits. BOR enabled in software; operation controlled by SBOREN. Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 4.5 4.5.3 Device Reset Timers PIC18F2682/2685/4682/4685 devices incorporate three separate on-chip timers that help regulate the Power-on Reset process. Their main function is to ensure that the device clock is stable before code is executed. These timers are: * Power-up Timer (PWRT) * Oscillator Start-up Timer (OST) * PLL Lock Time-out 4.5.1 With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly different from other oscillator modes. A separate timer is used to provide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the oscillator start-up time-out. 4.5.4 TIME-OUT SEQUENCE On power-up, the time-out sequence is as follows: POWER-UP TIMER (PWRT) The Power-up Timer (PWRT) of PIC18F2682/2685/ 4682/4685 devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 s = 65.6 ms. While the PWRT is counting, the device is held in Reset. The power-up time delay depends on the INTRC clock and will vary from chip-to-chip due to temperature and process variation. See DC parameter 33 for details. The PWRT is enabled by clearing the PWRTEN Configuration bit. 4.5.2 PLL LOCK TIME-OUT OSCILLATOR START-UP TIMER (OST) The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over (parameter 33). This ensures that the crystal oscillator or resonator has started and stabilized. 1. 2. After the POR pulse has cleared, PWRT time-out is invoked (if enabled). Then, the OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. Figure 4-3, Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all depict time-out sequences on power-up, with the Power-up Timer enabled and the device operating in HS Oscillator mode. Figures 4-3 through 4-6 also apply to devices operating in XT or LP modes. For devices in RC mode and with the PWRT disabled, on the other hand, there will be no time-out at all. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, all time-outs will expire. Bringing MCLR high will begin execution immediately (Figure 4-5). This is useful for testing purposes or to synchronize more than one PIC18FXXXX device operating in parallel. The OST time-out is invoked only for XT, LP, HS and HSPLL modes and only on Power-on Reset or on exit from most power-managed modes. TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) and Brown-out PWRTEN = 0 PWRTEN = 1 Exit From Power-Managed Mode 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) Oscillator Configuration HSPLL HS, XT, LP 66 ms(1) 1024 TOSC 1024 TOSC EC, ECIO 66 ms (1) -- -- RC, RCIO 66 ms(1) -- -- ms(1) -- -- INTIO1, INTIO2 Note 1: 2: + 1024 TOSC 66 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2 ms is the nominal time required for the PLL to lock. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 45 PIC18F2682/2685/4682/4685 FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 4-5: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS39761B-page 46 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 1V 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO VDD) FIGURE 4-7: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL 2 ms max. First three stages of the Power-up Timer. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 47 PIC18F2682/2685/4682/4685 4.6 Reset State of Registers PD, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table 4-3. These bits are used in software to determine the nature of the Reset. Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a "Reset state" depending on the type of Reset that occurred. Table 4-4 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Condition Program Counter RCON Register SBOREN RI TO PD STKPTR Register POR BOR STKFUL STKUNF Power-on Reset 0000h 1 1 1 1 0 0 0 0 RESET instruction 0000h u(2) 0 u u u u u u Brown-out Reset 0000h u(2) 1 1 1 u 0 u u MCLR during power-managed Run modes 0000h u(2) u 1 u u u u u MCLR during power-managed Idle modes and Sleep mode 0000h u(2) u 1 0 u u u u WDT time-out during full power or power-managed Run modes 0000h u(2) u 0 u u u u u MCLR during full power execution 0000h u(2) u u u u u u u Stack Full Reset (STVREN = 1) 0000h u(2) u u u u u 1 u Stack Underflow Reset (STVREN = 1) 0000h u (2) u u u u u u 1 Stack Underflow Error (not an actual Reset, STVREN = 0) 0000h u(2) u u u u u u 1 WDT time-out during power-managed Idle or Sleep modes PC + 2 u(2) u 0 0 u u u u PC + 2(1) u(2) u u 0 u u u u Interrupt exit from power-managed modes Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the interrupt vector (008h or 0018h). 2: Reset state is `1' for POR and unchanged for all other Resets when software BOR is enabled (BOREN1:BOREN0 Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is `0'. DS39761B-page 48 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt TOSU 2682 2685 4682 4685 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu(3) TOSL 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 2682 2685 4682 4685 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU 2682 2685 4682 4685 ---0 0000 ---0 0000 ---u uuuu PCLATH 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu PCL 2682 2685 4682 4685 0000 0000 0000 0000 PC + 2(2) TBLPTRU 2682 2685 4682 4685 --00 0000 --00 0000 --uu uuuu TBLPTRH 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu TBLPTRL 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu TABLAT 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu PRODH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu PRODL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu INTCON 2682 2685 4682 4685 0000 000x 0000 000u uuuu uuuu(1) INTCON2 2682 2685 4682 4685 1111 -1-1 1111 -1-1 uuuu -u-u(1) INTCON3 2682 2685 4682 4685 11-0 0-00 11-0 0-00 uu-u u-uu(1) INDF0 2682 2685 4682 4685 N/A N/A N/A POSTINC0 2682 2685 4682 4685 N/A N/A N/A POSTDEC0 2682 2685 4682 4685 N/A N/A N/A PREINC0 2682 2685 4682 4685 N/A N/A N/A Register PLUSW0 2682 2685 4682 4685 N/A N/A FSR0H 2682 2685 4682 4685 ---- 0000 ---- 0000 ---- uuuu N/A FSR0L 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu WREG 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 2682 2685 4682 4685 N/A N/A N/A POSTINC1 2682 2685 4682 4685 N/A N/A N/A POSTDEC1 2682 2685 4682 4685 N/A N/A N/A PREINC1 2682 2685 4682 4685 N/A N/A N/A PLUSW1 2682 2685 4682 4685 N/A N/A FSR1H 2682 2685 4682 4685 ---- 0000 ---- 0000 ---- uuuu N/A FSR1L 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 49 PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt BSR 2682 2685 4682 4685 ---- 0000 ---- 0000 ---- uuuu INDF2 2682 2685 4682 4685 N/A N/A N/A Register POSTINC2 2682 2685 4682 4685 N/A N/A N/A POSTDEC2 2682 2685 4682 4685 N/A N/A N/A PREINC2 2682 2685 4682 4685 N/A N/A N/A PLUSW2 2682 2685 4682 4685 N/A N/A N/A FSR2H 2682 2685 4682 4685 ---- 0000 ---- 0000 ---- uuuu FSR2L 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu STATUS 2682 2685 4682 4685 ---x xxxx ---u uuuu ---u uuuu TMR0H 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu TMR0L 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu T0CON 2682 2685 4682 4685 1111 1111 1111 1111 uuuu uuuu OSCCON 2682 2685 4682 4685 0100 q000 0100 00q0 uuuu uuqu HLVDCON 2682 2685 4682 4685 0-00 0101 0-00 0101 0-uu uuuu WDTCON 2682 2685 4682 4685 ---- ---0 ---- ---0 ---- ---u RCON(4) 2682 2685 4682 4685 0q-1 11q0 0q-q qquu uq-u qquu TMR1H 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 2682 2685 4682 4685 0000 0000 u0uu uuuu uuuu uuuu TMR2 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu PR2 2682 2685 4682 4685 1111 1111 1111 1111 1111 1111 T2CON 2682 2685 4682 4685 -000 0000 -000 0000 -uuu uuuu SSPBUF 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu SSPADD 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu SSPSTAT 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu SSPCON1 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu SSPCON2 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu ADRESH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 2682 2685 4682 4685 --00 0000 --00 0000 --uu uuuu ADCON1 2682 2685 4682 4685 --00 0qqq --00 0qqq --uu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. DS39761B-page 50 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets ADCON2 2682 2685 4682 4685 0-00 0000 0-00 0000 CCPR1H 2682 2685 4682 4685 xxxx xxxx uuuu uuuu CCPR1L 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 2682 2685 4682 4685 --00 0000 --00 0000 --uu uuuu ECCPR1H 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu ECCPR1L 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu ECCP1CON 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu BAUDCON 2682 2685 4682 4685 01-0 0-00 01-0 0-00 --uu uuuu ECCP1DEL 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu ECCP1AS 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu CVRCON 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu CMCON 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu TMR3H 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TMR3L 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu T3CON 2682 2685 4682 4685 0000 0000 uuuu uuuu uuuu uuuu SPBRGH 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu SPBRG 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu RCREG 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu TXREG 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu TXSTA 2682 2685 4682 4685 0000 0010 0000 0010 uuuu uuuu RCSTA 2682 2685 4682 4685 0000 000x 0000 000x uuuu uuuu EEADRH 2682 2685 4682 4685 ---- --00 ---- --00 ---- --uu EEADR 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu EEDATA 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu EECON2 2682 2685 4682 4685 0000 0000 0000 0000 0000 0000 EECON1 2682 2685 4682 4685 xx-0 x000 uu-0 u000 uu-0 u000 IPR3 2682 2685 4682 4685 1111 1111 1111 1111 uuuu uuuu PIR3 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu PIE3 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu IPR2 2682 2685 4682 4685 11-1 1111 11-1 1111 uu-u uuuu 2682 2685 4682 4685 1--1 111- 1--1 111- u--u uuu- Register Wake-up via WDT or Interrupt u-uu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 51 PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register PIR2 PIE2 IPR1 PIR1 PIE1 Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt 2682 2685 4682 4685 00-0 0000 00-0 0000 uu-u uuuu(1) 2682 2685 4682 4685 0--0 000- 0--0 000- u--u uuu-(1) 2682 2685 4682 4685 00-0 0000 00-0 0000 uu-u uuuu 2682 2685 4682 4685 0--0 000- 0--0 000- u--u uuu- 2682 2685 4682 4685 1111 1111 1111 1111 uuuu uuuu 2682 2685 4682 4685 -111 1111 -111 1111 -uuu uuuu 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu(1) 2682 2685 4682 4685 -000 0000 -000 0000 -uuu uuuu 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu 2682 2685 4682 4685 -000 0000 -000 0000 -uuu uuuu OSCTUNE 2682 2685 4682 4685 0q-0 0000 0q-0 0000 uu-u uuuu TRISE 2682 2685 4682 4685 0000 -111 0000 -111 uuuu -uuu TRISD 2682 2685 4682 4685 1111 1111 1111 1111 uuuu uuuu TRISC 2682 2685 4682 4685 1111 1111 1111 1111 uuuu uuuu TRISB 2682 2685 4682 4685 1111 1111 1111 1111 uuuu uuuu TRISA(5) 2682 2685 4682 4685 1111 1111(5) 1111 1111(5) uuuu uuuu(5) LATE 2682 2685 4682 4685 ---- -xxx ---- -uuu ---- -uuu LATD 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu LATC 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu LATB 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (5) xxxx(5) LATA 2682 2685 4682 4685 xxxx PORTE 2682 2685 4682 4685 ---- x000 ---- x000 ---- uuuu PORTD 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu PORTC 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu(5) uuuu uuuu(5) PORTB 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu PORTA(5) 2682 2685 4682 4685 xx0x 0000(5) uu0u 0000(5) uuuu uuuu(5) ECANCON 2682 2685 4682 4685 0001 0000 0001 0000 uuuu uuuu TXERRCNT 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu RXERRCNT 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu COMSTAT 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu CIOCON 2682 2685 4682 4685 --00 ---- --00 ---- --uu ---- Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. DS39761B-page 52 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt BRGCON3 2682 2685 4682 4685 00-- -000 00-- -000 uu-- -uuu BRGCON2 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu BRGCON1 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu CANCON 2682 2685 4682 4685 1000 000- 1000 000- uuuu uuu- CANSTAT 2682 2685 4682 4685 100- 000- 100- 000- uuu- uuu- RXB0D7 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D6 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D5 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D4 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D3 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D2 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D1 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D0 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB0DLC 2682 2685 4682 4685 -xxx xxxx -uuu uuuu -uuu uuuu RXB0EIDL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB0EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB0SIDL 2682 2685 4682 4685 xxxx x-xx uuuu u-uu uuuu u-uu RXB0SIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB0CON 2682 2685 4682 4685 000- 0000 000- 0000 uuu- uuuu RXB1D7 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D6 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D5 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D4 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D3 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D2 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D1 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D0 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB1DLC 2682 2685 4682 4685 -xxx xxxx -uuu uuuu -uuu uuuu RXB1EIDL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB1EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB1SIDL 2682 2685 4682 4685 xxxx x-xx uuuu u-uu uuuu u-uu Register Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 53 PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt RXB1SIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB1CON 2682 2685 4682 4685 000- 0000 000- 0000 uuu- uuuu TXB0D7 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D6 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D5 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D4 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D3 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D2 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D1 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D0 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB0DLC 2682 2685 4682 4685 -x-- xxxx -u-- uuuu -u-- uuuu TXB0EIDL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB0EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB0SIDL 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu TXB0SIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB0CON 2682 2685 4682 4685 0000 0-00 0000 0-00 uuuu u-uu TXB1D7 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D6 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D5 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D4 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D3 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D2 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D1 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D0 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB1DLC 2682 2685 4682 4685 -x-- xxxx -u-- uuuu -u-- uuuu TXB1EIDL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB1EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB1SIDL 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- uu-u TXB1SIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB1CON 2682 2685 4682 4685 0000 0-00 0000 0-00 uuuu u-uu TXB2D7 2682 2685 4682 4685 xxxx xxxx uuuu uuuu 0uuu uuuu Register Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. DS39761B-page 54 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt TXB2D6 2682 2685 4682 4685 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D5 2682 2685 4682 4685 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D4 2682 2685 4682 4685 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D3 2682 2685 4682 4685 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D2 2682 2685 4682 4685 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D1 2682 2685 4682 4685 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D0 2682 2685 4682 4685 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2DLC 2682 2685 4682 4685 -x-- xxxx -u-- uuuu -u-- uuuu TXB2EIDL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB2EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB2SIDL 2682 2685 4682 4685 xxxx x-xx uuuu u-uu uuuu u-uu TXB2SIDH 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu TXB2CON 2682 2685 4682 4685 0000 0-00 0000 0-00 uuuu u-uu RXM1EIDL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXM1EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXM1SIDL 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu RXM1SIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXM0EIDL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXM0EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXM0SIDL 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu RXM0SIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF5EIDL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF5EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF5SIDL 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu RXF5SIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF4EIDL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF4EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF4SIDL 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu RXF4SIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF3EIDL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF3EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu Register Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 55 PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt RXF3SIDL 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu RXF3SIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF2EIDL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF2EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF2SIDL 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu RXF2SIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF1EIDL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF1EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF1SIDL 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu RXF1SIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF0EIDL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF0EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF0SIDL 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu RXF0SIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B5D6(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B5D5(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B5D4(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B5D2(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B5D1(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B5D0(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B5DLC(6) 2682 2685 4682 4685 -xxx xxxx -uuu uuuu -uuu uuuu B5EIDL(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) B5EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B5SIDL(6) 2682 2685 4682 4685 xxxx x-xx uuuu u-uu uuuu u-uu (6) B5SIDH 2682 2685 4682 4685 xxxx x-xx uuuu u-uu uuuu u-uu B5CON(6) 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu B4D7(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B4D6(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu Register B5D7 B5D3 B4D5 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. DS39761B-page 56 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt B4D4(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B4D3(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B4D1(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) Register B4D2 B4D0 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B4DLC(6) 2682 2685 4682 4685 -xxx xxxx -uuu uuuu -uuu uuuu B4EIDL(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B4EIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B4SIDL(6) 2682 2685 4682 4685 xxxx x-xx uuuu u-uu uuuu u-uu B4SIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B4CON(6) 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu B3D7(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B3D5(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B3D4(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B3D3(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B3D2(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B3D1(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) B3D6 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B3DLC(6) 2682 2685 4682 4685 -xxx xxxx -uuu uuuu -uuu uuuu B3EIDL(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B3EIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B3SIDL(6) 2682 2685 4682 4685 xxxx x-xx uuuu u-uu uuuu u-uu B3SIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) B3CON 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu B2D7(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B2D5(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B2D4(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B2D3(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B3D0 B2D6 B2D2 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 57 PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt B2D1(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B2D0(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) 2682 2685 4682 4685 -xxx xxxx -uuu uuuu -uuu uuuu B2EIDL(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) B2EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B2SIDL(6) 2682 2685 4682 4685 xxxx x-xx uuuu u-uu uuuu u-uu B2SIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B2CON(6) 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu B1D7(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B1D6(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B1D5(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B1D4(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B1D2(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B1D1(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B1D0(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B1DLC(6) 2682 2685 4682 4685 -xxx xxxx -uuu uuuu -uuu uuuu B1EIDL(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) B1EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B1SIDL(6) 2682 2685 4682 4685 xxxx x-xx uuuu u-uu uuuu u-uu B1SIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B1CON(6) 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu B0D7(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B0D6(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B0D4(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B0D2(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B0D1(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B0D0(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu 2682 2685 4682 4685 -xxx xxxx -uuu uuuu -uuu uuuu Register B2DLC B1D3 B0D5 B0D3 (6) B0DLC Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. DS39761B-page 58 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt B0EIDL(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B0EIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) 2682 2685 4682 4685 xxxx x-xx uuuu u-uu uuuu u-uu B0SIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) B0CON 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu TXBIE(6) 2682 2685 4682 4685 ---0 00-- ---u uu-- ---u uu-- BIE0(6) 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu BSEL0(6) 2682 2685 4682 4685 0000 00-- 0000 00-- uuuu uu-- MSEL3(6) 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu MSEL2(6) 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu MSEL1(6) 2682 2685 4682 4685 0000 0101 0000 0101 uuuu uuuu MSEL0(6) 2682 2685 4682 4685 0101 0000 0101 0000 uuuu uuuu (6) SDFLC 2682 2685 4682 4685 ---0 0000 ---0 0000 ---u uuuu RXFCON1(6) 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu RXFCON0(6) Register B0SIDL 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu RXFBCON7(6) 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu RXFBCON6(6) 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu RXFBCON5(6) 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu (6) 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu RXFBCON3(6) 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu RXFBCON2(6) RXFBCON4 2682 2685 4682 4685 0001 0001 0001 0001 uuuu uuuu RXFBCON1(6) 2682 2685 4682 4685 0001 0001 0001 0001 uuuu uuuu RXFBCON0(6) 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu RXF15EIDL(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF15SIDL(6) 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu (6) RXF15EIDH (6) RXF15SIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF14EIDL(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF14EIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF14SIDL(6) 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu xxxx xxxx uuuu uuuu uuuu uuuu (6) RXF14SIDH 2682 2685 4682 4685 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 59 PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt RXF13EIDL(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF13EIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu Register Applicable Devices (6) RXF13SIDL 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu RXF13SIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) RXF12EIDL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF12EIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF12SIDL(6) 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu RXF12SIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF11EIDL(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF11EIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF11SIDL(6) 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu RXF11SIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF10EIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF10SIDL(6) RXF10EIDL 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu RXF10SIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF9EIDL(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF9EIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu RXF9SIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF8EIDL(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF8EIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF8SIDL(6) 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu RXF8SIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF7EIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu RXF7SIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF6EIDL(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF6EIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu RXF6SIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF9SIDL RXF7EIDL RXF7SIDL RXF6SIDL Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 6: This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. DS39761B-page 60 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 5.0 MEMORY ORGANIZATION 5.1 There are three types of memory in PIC18 Enhanced microcontroller devices: * Program Memory * Data RAM * Data EEPROM As Harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. The data EEPROM, for practical purposes, can be regarded as a peripheral device, since it is addressed and accessed through a set of control registers. Additional detailed information on the operation of the Flash program memory is provided in Section 6.0 "Flash Program Memory". Data EEPROM is discussed separately in Section 7.0 "Data EEPROM Memory". FIGURE 5-1: Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all `0's (a NOP instruction). The PIC18F2682 and PIC18F4682 each have 80 Kbytes of Flash memory and can store up to 40,960 single-word instructions. The PIC18F2685 and PIC18F4685 each have 96 Kbytes of Flash memory and can store up to 49,152 single-word instructions. PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. The program memory maps for PIC18F2682/4682 and PIC18F2685/4685 devices are shown in Figure 5-1. PROGRAM MEMORY MAP AND STACK FOR PIC18F2682/2685/4682/4685 DEVICES PIC18F2682/4682 PIC18F2685/4685 PC<20:0> PC<20:0> 21 CALL, RCALL, RETURN RETFIE, RETLW 21 CALL, RCALL, RETURN RETFIE, RETLW Stack Level 1 Stack Level 1 * * * * * * Stack Level 31 Stack Level 31 Reset Vector 0000h Reset Vector 0000h High Priority Interrupt Vector 00008h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h Low Priority Interrupt Vector 0018h On-Chip Program Memory On-Chip Program Memory Read `0' 17FFFh 18000h User Memory Space User Memory Space 13FFFh 14000h Read `0' 1FFFFFh 200000h 1FFFFFh 200000h (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 61 PIC18F2682/2685/4682/4685 5.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits; it is also not directly readable or writable. Updates to the PCU register are performed through the PCLATU register. The contents of PCLATH and PCLATU are transferred to the program counter by any operation that writes to the PCL. Similarly, the upper two bytes of the program counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 5.1.4.1 "Computed GOTO"). The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to a value of `0'. The PC increments by 2 to address sequential instructions in the program memory. The CALL, RCALL and GOTO program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. 5.1.2 RETURN ADDRESS STACK The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC is pushed onto the stack when a CALL, or RCALL instruction is executed, or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. FIGURE 5-2: The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-ofStack Special Function Registers. Data can also be pushed to, or popped from the stack, using these registers. A CALL type instruction causes a push onto the stack. The Stack Pointer is first incremented and the location pointed to by the Stack Pointer is written with the contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes a pop from the stack. The contents of the location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer is decremented. The Stack Pointer is initialized to `00000' after all Resets. There is no RAM associated with the location corresponding to a Stack Pointer value of `00000'; this is only a Reset value. Status bits indicate if the stack is full, has overflowed or has underflowed. 5.1.2.1 Top-of-Stack Access Only the top of the return address stack (TOS) is readable and writable. A set of three registers, TOSU:TOSH:TOSL, holds the contents of the stack location pointed to by the STKPTR register (Figure 5-2). This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU:TOSH:TOSL registers. These values can be placed on a user defined software stack. At return time, the software can return these values to TOSU:TOSH:TOSL and do a return. The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack <20:0> 11111 11110 11101 Top-of-Stack Registers TOSU 00h TOSH 1Ah STKPTR<4:0> 00010 TOSL 34h Top-of-Stack DS39761B-page 62 Stack Pointer 001A34h 000D58h Preliminary 00011 00010 00001 00000 (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 5.1.2.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next pop returns a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs. The STKPTR register (Register 5-1) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bit. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. On Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value. This feature can be used by a Real-Time Operating System (RTOS) for return stack maintenance. Note: After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a POR. 5.1.2.3 PUSH and POP Instructions Since the Top-of-Stack is readable and writable, the ability to push values onto the stack and pull values off the stack without disturbing normal program execution is a desirable feature. The PIC18 instruction set includes two instructions, PUSH and POP, that permit the TOS to be manipulated under software control. TOSU, TOSH and TOSL can be modified to place data or a return address on the stack. The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) Configuration bit. (Refer to Section 24.1 "Configuration Bits" for a description of the device Configuration bits.) If STVREN is set (default), the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit and reset the device. The STKFUL bit will remain set and the Stack Pointer will be set to zero. The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads the current PC value onto the stack. If STVREN is cleared, the STKFUL bit will be set on the 31st push and the Stack Pointer will increment to 31. Any additional pushes will not overwrite the 31st push and STKPTR will remain at 31. REGISTER 5-1: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset, as the contents of the SFRs are not affected. The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. STKPTR: STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL(1) STKUNF(1) -- SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as `0' bit 4-0 SP4:SP0: Stack Pointer Location bits Note 1: x = Bit is unknown Bit 7 and bit 6 are cleared by user software or by a POR. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 63 PIC18F2682/2685/4682/4685 5.1.2.4 Stack Full and Underflow Resets 5.1.4 Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device Reset. The STKFUL or STKUNF bit is cleared by user software or a Power-on Reset. 5.1.3 FAST REGISTER STACK A Fast Register Stack is provided for the STATUS, WREG and BSR registers to provide a "fast return" option for interrupts. Each stack is only one level deep and is neither readable nor writable. It is loaded with the current value of the corresponding register when the processor vectors for an interrupt. All interrupt sources will push values into the stack registers. The values in the registers are then loaded back into their associated registers, if the RETFIE, FAST instruction is used to return from the interrupt. LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: * Computed GOTO * Table Reads 5.1.4.1 Computed GOTO A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in Example 5-2. A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions. The W register is loaded with an offset into the table before executing a CALL to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW nn instructions, that returns the value `nn' to the calling function. If both low and high priority interrupts are enabled, the stack registers cannot be used reliably to return from low priority interrupts. If a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. In these cases, users must save the key registers in software during a low priority interrupt. The offset value (in WREG) specifies the number of bytes that the program counter should advance and should be multiples of 2 (LSb = 0). If interrupt priority is not used, all interrupts may use the Fast Register Stack for returns from interrupt. If no interrupts are used, the Fast Register Stack can be used to restore the STATUS, WREG and BSR registers at the end of a subroutine call. To use the Fast Register Stack for a subroutine call, a CALL label, FAST instruction must be executed to save the STATUS, WREG and BSR registers to the Fast Register Stack. A RETURN, FAST instruction is then executed to restore these registers from the Fast Register Stack. EXAMPLE 5-2: Example 5-1 shows a source code example that uses the Fast Register Stack during a subroutine call and return. EXAMPLE 5-1: CALL SUB1, FAST FAST REGISTER STACK CODE EXAMPLE ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK * * SUB1 * * RETURN, FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK DS39761B-page 64 In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. ORG TABLE 5.1.4.2 MOVF CALL nn00h ADDWF RETLW RETLW RETLW . . . COMPUTED GOTO USING AN OFFSET VALUE OFFSET, W TABLE PCL nnh nnh nnh Table Reads and Table Writes A better method of storing data in program memory allows two bytes of data to be stored in each instruction location. Look-up table data may be stored two bytes per program word by using table reads and writes. The Table Pointer (TBLPTR) register specifies the byte address and the Table Latch (TABLAT) register contains the data that is read from or written to program memory. Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 6.1 "Table Reads and Table Writes". Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 5.2 5.2.2 PIC18 Instruction Cycle 5.2.1 An "Instruction Cycle" consists of four Q cycles: Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 5-3). CLOCKING SCHEME The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the Program Counter (PC) is incremented on every Q1; the instruction is fetched from the program memory and latched into the Instruction Register (IR) during Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 5-3. FIGURE 5-3: INSTRUCTION FLOW/PIPELINING A fetch cycle begins with the program counter incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 OSC1 Q1 Q2 Internal Phase Clock Q3 Q4 PC OSC2/CLKO (RC mode) PC PC + 2 Execute INST (PC - 2) Fetch INST (PC) EXAMPLE 5-3: Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 2) Fetch INST (PC + 4) INSTRUCTION PIPELINE FLOW 1. MOVLW 55h TCY0 TCY1 Fetch 1 Execute 1 2. MOVWF PORTB 3. BRA SUB_1 4. BSF PORTA, BIT3 (Forced NOP) Fetch 2 TCY2 TCY3 TCY4 TCY5 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush (NOP) Fetch SUB_1 Execute SUB_1 5. Instruction @ address SUB_1 Note: PC + 4 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 65 PIC18F2682/2685/4682/4685 5.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read `0' (see Section 5.1.1 "Program Counter"). Figure 5-4 shows an example of how instruction words are stored in the program memory. FIGURE 5-4: The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1>, which accesses the desired byte address in program memory. Instruction #2 in Figure 5-4 shows how the instruction GOTO 0006h is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be offset by. Section 25.0 "Instruction Set Summary" provides further details of the instruction set. INSTRUCTIONS IN PROGRAM MEMORY LSB = 1 LSB = 0 0Fh EFh F0h C1h F4h 55h 03h 00h 23h 56h Program Memory Byte Locations 5.2.4 Instruction 1: Instruction 2: MOVLW GOTO 055h 0006h Instruction 3: MOVFF 123h, 456h TWO-WORD INSTRUCTIONS The standard PIC18 instruction set has four two-word instructions: CALL, MOVFF, GOTO and LSFR. In all cases, the second word of the instructions always has `1111' as its four Most Significant bits; the other 12 bits are literal data, usually a data memory address. The use of `1111' in the 4 MSbs of an instruction specifies a special form of NOP. If the instruction is executed in proper sequence - immediately after the first word - the data in the second word is accessed EXAMPLE 5-4: Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h and used by the instruction sequence. If the first word is skipped for some reason and the second word is executed by itself, a NOP is executed instead. This is necessary for cases when the two-word instruction is preceded by a conditional instruction that changes the PC. Example 5-4 shows how this works. Note: See Section 5.5 "Program Memory and the Extended Instruction Set" for information on two-word instructions in the extended instruction set. TWO-WORD INSTRUCTIONS CASE 1: Object Code 0110 1100 1111 0010 0110 0001 0100 0100 Source Code 0000 0010 0101 0000 0000 0011 0110 0000 0000 0010 0101 0000 0000 0011 0110 0000 TSTFSZ MOVFF ADDWF REG1 ; is RAM location 0? REG1, REG2 ; No, skip this word ; Execute this word as a NOP REG3 ; continue code CASE 2: Object Code 0110 1100 1111 0010 0110 0001 0100 0100 Source Code DS39761B-page 66 TSTFSZ MOVFF ADDWF REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 5.3 Note: 5.3.1 Data Memory Organization The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 5.6 "Data Memory and the Extended Instruction Set" for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each; PIC18F2682/ 2685/4682/4685 devices implement all 16 banks. Figure 5-5 shows the data memory organization for the PIC18F2682/2685/4682/4685 devices. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user's application. Any read of an unimplemented location will read as `0's. The instruction set and architecture allow operations across all banks. The entire data memory may be accessed by Direct, Indirect or Indexed Addressing modes. Addressing modes are discussed later in this subsection. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, PIC18 devices implement an Access Bank. This is a 256-byte memory space that provides fast access to SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 5.3.2 "Access Bank" provides a detailed description of the Access RAM. BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. Ideally, this means that an entire address does not need to be provided for each read or write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the memory space into 16 contiguous banks of 256 bytes. Depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit low-order address and a 4-bit Bank Pointer. Most instructions in the PIC18 instruction set make use of the Bank Pointer, known as the Bank Select Register (BSR). This SFR holds the 4 Most Significant bits of a location's address; the instruction itself includes the 8 Least Significant bits. Only the four lower bits of the BSR are implemented (BSR3:BSR0). The upper four bits are unused; they will always read `0' and cannot be written to. The BSR can be loaded directly by using the MOVLB instruction. The value of the BSR indicates the bank in data memory. The 8 bits in the instruction show the location in the bank and can be thought of as an offset from the bank's lower boundary. The relationship between the BSR's value and the bank division in data memory is shown in Figure 5-6. Since up to 16 registers may share the same low-order address, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. For example, writing what should be program data to an 8-bit address of F9h while the BSR is 0Fh, will end up resetting the program counter. While any bank can be selected, only those banks that are actually implemented can be read or written to. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return `0's. Even so, the STATUS register will still be affected as if the operation was successful. The data memory map in Figure 5-5 indicates which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 67 PIC18F2682/2685/4682/4685 FIGURE 5-5: DATA MEMORY MAP FOR PIC18F2682/2685/4682/4685 DEVICES BSR<3:0> = 0000 00h Access RAM FFh 00h GPR Bank 0 = 0001 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 DS39761B-page 68 1FFh 200h FFh 00h Bank 2 Bank 3 Bank 4 Bank 5 GPR FFh 00h 2FFh 300h GPR Bank 12 When a = 1: The BSR specifies the Bank used by the instruction. GPR 5FFh 600h GPR Bank 7 Bank 11 The second 128 bytes are Special Function Registers (from Bank 15). 4FFh 500h FFh 00h Bank 10 The first 128 bytes are general purpose RAM (from Bank 0). GPR FFh 00h Bank 6 Bank 9 The BSR is ignored and the Access Bank is used. 3FFh 400h FFh 00h FFh 00h Bank 8 000h 05Fh 060h 0FFh 100h GPR Bank 1 = 0010 When a = 0: Data Memory Map 6FFh 700h Access RAM Low GPR 7FFh 800h FFh 00h Access Bank GPR 00h 5Fh Access RAM High 60h (SFRs) FFh 8FFh 900h FFh 00h GPR 9FFh A00h FFh 00h GPR AFFh B00h FFh 00h GPR FFh 00h FFh Bank 13 00h BFFh C00h GPR CFFh D00h CAN SFRs DFFh E00h FFh 00h Bank 14 CAN SFRs FFh 00h CAN SFRs FFh SFR Bank 15 EFFh F00h F5Fh F60h FFFh Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 FIGURE 5-6: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) 0 Data Memory BSR(1) 7 0 0 0 0 0 0 1 000h Bank 0 1 100h Bank Select(2) Bank 1 00h 7 FFh 00h 1 From Opcode(2) 1 1 1 1 1 0 1 1 FFh 00h 200h Bank 2 FFh 00h 300h Bank 3 through Bank 13 FFh 00h E00h Bank 14 FFh 00h F00h FFFh Note 1: 2: 5.3.2 Bank 15 FFh The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. The MOVFF instruction embeds the entire 12-bit address in the instruction. ACCESS BANK While the use of the BSR with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. Otherwise, data may be read from or written to the wrong location. This can be disastrous if a GPR is the intended target of an operation, but an SFR is written to instead. Verifying and/or changing the BSR for each read or write to data memory can become very inefficient. To streamline access for the most commonly used data memory locations, the data memory is configured with an Access Bank, which allows users to access a mapped block of memory without specifying a BSR. The Access Bank consists of the first 128 bytes of memory (00h-7Fh) in Bank 0 and the last 128 bytes of memory (80h-FFh) in Block 15. The lower half is known as the "Access RAM" and is composed of GPRs. The upper half is where the device's SFRs are mapped. These two areas are mapped contiguously in the Access Bank and can be addressed in a linear fashion by an 8-bit address (Figure 5-5). The Access Bank is used by core PIC18 instructions that include the Access RAM bit (the `a' parameter in the instruction). When `a' is equal to `1', the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When `a' is `0' (c) 2007 Microchip Technology Inc. however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. Using this "forced" addressing allows the instruction to operate on a data address in a single cycle, without updating the BSR first. For 8-bit addresses of 80h and above, this means that users can evaluate and operate on SFRs more efficiently. The Access RAM below 80h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. Access RAM also allows for faster and more code efficient context saving and switching of variables. The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST Configuration bit = 1). This is discussed in more detail in Section 5.6.3 "Mapping the Access Bank in Indexed Literal Offset Mode". 5.3.3 GENERAL PURPOSE REGISTER FILE PIC18 devices may have banked memory in the GPR area. This is data RAM, which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. Preliminary DS39761B-page 69 PIC18F2682/2685/4682/4685 5.3.4 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy the top half of Bank 15 (F80h to FFFh). A list of these registers is given in Table 5-1 and Table 5-2. The SFRs can be classified into two sets: those associated with the "core" device functionality (ALU, Resets and interrupts) and those related to the TABLE 5-1: peripheral functions. The reset and interrupt registers are described in their respective chapters, while the ALU's STATUS register is described later in this section. Registers related to the operation of a peripheral feature are described in the chapter for that peripheral. The SFRs are typically distributed among the peripherals whose functions they control. Unused SFR locations are unimplemented and read as `0's. SPECIAL FUNCTION REGISTER MAP FOR PIC18F2682/2685/4682/4685 DEVICES Address Name Address Name Address Name Address Name FFFh TOSU FDFh INDF2(3) FBFh CCPR1H F9Fh IPR1 FFEh TOSH FDEh POSTINC2(3) FBEh CCPR1L F9Eh PIR1 FFDh TOSL FDDh POSTDEC2(3) FBDh CCP1CON F9Dh PIE1 FFCh STKPTR FDCh PREINC2(3) FBCh ECCPR1H(1) F9Ch -- FFBh PCLATU FDBh PLUSW2(3) FBBh ECCPR1L(1) F9Bh OSCTUNE FFAh PCLATH FDAh FSR2H FBAh ECCP1CON(1) F9Ah -- FF9h PCL FD9h FSR2L FB9h -- F99h -- FF8h TBLPTRU FD8h STATUS FB8h BAUDCON F98h -- FF7h TBLPTRH FD7h TMR0H FB7h ECCP1DEL F97h -- FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS(1) F96h TRISE(1) FF5h TABLAT FD5h T0CON FB5h CVRCON(1) F95h TRISD(1) TRISC FF4h PRODH FD4h -- FB4h CMCON F94h FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB FF2h INTCON FD2h HLVDCON FB2h TMR3L F92h TRISA FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h -- FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h -- FEFh INDF0(3) FCFh TMR1H FAFh SPBRG F8Fh -- FEEh POSTINC0(3) FCEh TMR1L FAEh RCREG F8Eh -- FEDh POSTDEC0(3) FCDh T1CON FADh TXREG F8Dh LATE(1) FECh PREINC0(3) FCCh TMR2 FACh TXSTA F8Ch LATD(1) FEBh PLUSW0 (3) FCBh PR2 FABh RCSTA F8Bh LATC FEAh FSR0H FCAh T2CON FAAh EEADRH F8Ah LATB FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA FE8h WREG FC8h SSPADD FA8h EEDATA F88h -- FE7h INDF1(3) FC7h SSPSTAT FA7h EECON2(3) F87h -- FE6h POSTINC1(3) FC6h SSPCON1 FA6h EECON1 F86h -- FE5h POSTDEC1(3) FC5h SSPCON2 FA5h IPR3 F85h -- (3) FC4h ADRESH FA4h PIR3 F84h PORTE(1) (3) FC3h ADRESL FA3h PIE3 F83h PORTD(1) FE4h PREINC1 FE3h PLUSW1 FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA Note 1: 2: 3: Registers available only on PIC18F4X8X devices; otherwise, the registers read as `0'. When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties. This is not a physical register. DS39761B-page 70 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 5-1: Address SPECIAL FUNCTION REGISTER MAP FOR PIC18F2682/2685/4682/4685 DEVICES (CONTINUED) Name F7Fh -- Address F5Fh Name CANCON_RO0 Address Name F3Fh CANCON_RO2 Address Name F1Fh RXM1EIDL RXM1EIDH F7Eh -- F5Eh CANSTAT_RO0 F3Eh CANSTAT_RO2 F1Eh F7Dh -- F5Dh RXB1D7 F3Dh TXB1D7 F1Dh RXM1SIDL F7Ch -- F5Ch RXB1D6 F3Ch TXB1D6 F1Ch RXM1SIDH F7Bh -- F5Bh RXB1D5 F3Bh TXB1D5 F1Bh RXM0EIDL F7Ah -- F5Ah RXB1D4 F3Ah TXB1D4 F1Ah RXM0EIDH F79h -- F59h RXB1D3 F39h TXB1D3 F19h RXM0SIDL F78h -- F58h RXB1D2 F38h TXB1D2 F18h RXM0SIDH F77h ECANCON F57h RXB1D1 F37h TXB1D1 F17h RXF5EIDL RXF5EIDH F76h TXERRCNT F56h RXB1D0 F36h TXB1D0 F16h F75h RXERRCNT F55h RXB1DLC F35h TXB1DLC F15h RXF5SIDL F74h COMSTAT F54h RXB1EIDL F34h TXB1EIDL F14h RXF5SIDH F73h CIOCON F53h RXB1EIDH F33h TXB1EIDH F13h RXF4EIDL F72h BRGCON3 F52h RXB1SIDL F32h TXB1SIDL F12h RXF4EIDH F71h BRGCON2 F51h RXB1SIDH F31h TXB1SIDH F11h RXF4SIDL F70h BRGCON1 F50h RXB1CON F30h TXB1CON F10h RXF4SIDH F6Fh CANCON F4Fh CANCON_RO1 F2Fh CANCON_RO3 F0Fh RXF3EIDL RXF3EIDH F6Eh CANSTAT F4Eh CANSTAT_RO1 F2Eh CANSTAT_RO3 F0Eh F6Dh RXB0D7 F4DH TXB0D7 F2Dh TXB2D7 F0Dh RXF3SIDL F6Ch RXB0D6 F4Ch TXB0D6 F2Ch TXB2D6 F0Ch RXF3SIDH F6Bh RXB0D5 F4Bh TXB0D5 F2Bh TXB2D5 F0Bh RXF2EIDL F6Ah RXB0D4 F4Ah TXB0D4 F2Ah TXB2D4 F0Ah RXF2EIDH F69h RXB0D3 F49h TXB0D3 F29h TXB2D3 F09h RXF2SIDL F68h RXB0D2 F48h TXB0D2 F28h TXB2D2 F08h RXF2SIDH F67h RXB0D1 F47h TXB0D1 F27h TXB2D1 F07h RXF1EIDL RXF1EIDH F66h RXB0D0 F46h TXB0D0 F26h TXB2D0 F06h F65h RXB0DLC F45h TXB0DLC F25h TXB2DLC F05h RXF1SIDL F64h RXB0EIDL F44h TXB0EIDL F24h TXB2EIDL F04h RXF1SIDH F63h RXB0EIDH F43h TXB0EIDH F23h TXB2EIDH F03h RXF0EIDL RXF0EIDH F62h RXB0SIDL F42h TXB0SIDL F22h TXB2SIDL F02h F61h RXB0SIDH F41h TXB0SIDH F21h TXB2SIDH F01h RXF0SIDL F60h RXB0CON F40h TXB0CON F20h TXB2CON F00h RXF0SIDH Note 1: 2: 3: Registers available only on PIC18F4X8X devices; otherwise, the registers read as `0'. When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties. This is not a physical register. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 71 PIC18F2682/2685/4682/4685 TABLE 5-1: Address SPECIAL FUNCTION REGISTER MAP FOR PIC18F2682/2685/4682/4685 DEVICES (CONTINUED) Name EFFh -- Address Name EDFh -- Address Name EBFh -- Address Name E9Fh -- EFEh -- EDEh -- EBEh -- E9Eh -- EFDh -- EDDh -- EBDh -- E9Dh -- EFCh -- EDCh -- EBCh -- E9Ch -- EFBh -- EDBh -- EBBh -- E9Bh -- EFAh -- EDAh -- EBAh -- E9Ah -- EF9h -- ED9h -- EB9h -- E99h -- EF8h -- ED8h -- EB8h -- E98h -- EF7h -- ED7h -- EB7h -- E97h -- EF6h -- ED6h -- EB6h -- E96h -- EF5h -- ED5h -- EB5h -- E95h -- EF4h -- ED4h -- EB4h -- E94h -- EF3h -- ED3h -- EB3h -- E93h -- EF2h -- ED2h -- EB2h -- E92h -- EF1h -- ED1h -- EB1h -- E91h -- EF0h -- ED0h -- EB0h -- E90h -- EEFh -- ECFh -- EAFh -- E8Fh -- EEEh -- ECEh -- EAEh -- E8Eh -- EEDh -- ECDh -- EADh -- E8Dh -- EECh -- ECCh -- EACh -- E8Ch -- EEBh -- ECBh -- EABh -- E8Bh -- EEAh -- ECAh -- EAAh -- E8Ah -- EE9h -- EC9h -- EA9h -- E89h -- EE8h -- EC8h -- EA8h -- E88h -- EE7h -- EC7h -- EA7h -- E87h -- EE6h -- EC6h -- EA6h -- E86h -- EE5h -- EC5h -- EA5h -- E85h -- EE4h -- EC4h -- EA4h -- E84h -- EE3h -- EC3h -- EA3h -- E83h -- EE2h -- EC2h -- EA2h -- E82h -- EE1h -- EC1h -- EA1h -- E81h -- EE0h -- EC0h -- EA0h -- E80h -- Note 1: 2: 3: Registers available only on PIC18F4X8X devices; otherwise, the registers read as `0'. When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties. This is not a physical register. DS39761B-page 72 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 5-1: Address SPECIAL FUNCTION REGISTER MAP FOR PIC18F2682/2685/4682/4685 DEVICES (CONTINUED) Name Address E7Fh CANCON_RO4 E7Eh CANSTAT_RO4 E7Dh B5D7(2) E6Fh Name CANCON_RO5 E6Eh CANSTAT_RO5 CANCON_RO6 Address Name E4Fh CANCON_RO7 E5Eh CANSTAT_RO6 B3D7(2) E4Dh B2D7(2) E6Ch B4D6 (2) E5Ch B3D6 (2) E4Ch B2D6(2) E6Bh B4D5(2) E5Bh B3D5(2) E4Bh B2D5(2) E6Ah B4D4(2) E5Ah B3D4(2) E4Ah B2D4(2) E69h B4D3 (2) E59h B3D3 (2) E49h B2D3(2) E68h B4D2 (2) E58h B3D2 (2) E48h B2D2(2) E67h B4D1(2) E57h B3D1(2) E47h B2D1(2) E66h (2) E56h (2) B4D7(2) E7Ch B5D6 (2) E7Bh B5D5(2) E7Ah B5D4(2) E79h B5D3 (2) E78h B5D2 (2) E77h B5D1(2) E76h (2) B4D0 B3D0 E46h B2D0(2) (2) B5DLC E65h B4DLC E55h B3DLC E45h B2DLC(2) E74h B5EIDL(2) E64h B4EIDL(2) E54h B3EIDL(2) E44h B2EIDL(2) E73h B5EIDH(2) E63h B4EIDH(2) E53h B3EIDH(2) E43h B2EIDH(2) E72h (2) B5SIDL E62h B4SIDL (2) E52h (2) B3SIDL E42h B2SIDL(2) E71h B5SIDH(2) E61h B4SIDH(2) E51h B3SIDH(2) E41h B2SIDH(2) E70h (2) E60h (2) E50h (2) E40h B2CON(2) E0Fh -- E3Fh CANCON_RO8 E2Fh (2) E4Eh CANSTAT_RO7 E75h B5CON (2) Name E5Fh E5Dh E6Dh B5D0 Address B4CON CANCON_RO9 B3CON E1Fh -- E3Eh CANSTAT_RO8 E1Eh -- E0Eh -- E3Dh B1D7(2) E2Dh B0D7(2) E1Dh -- E0Dh -- E3Ch B1D6(2) E2Ch B0D6(2) E1Ch -- E0Ch -- E3Bh B1D5(2) E2Bh B0D5(2) E1Bh -- E0Bh -- E3Ah B1D4 (2) E2Ah B0D4 (2) E1Ah -- E0Ah -- E39h B1D3(2) E29h B0D3(2) E19h -- E09h -- E38h B1D2(2) E28h B0D2(2) E18h -- E08h -- E37h B1D1(2) E27h B0D1(2) E17h -- E07h -- E36h (2) E26h (2 E2Eh CANSTAT_RO9 E16h -- E06h -- E35h B1DLC(2) E25h B0DLC(2) E15h -- E05h -- E34h B1EIDL(2) E24h B0EIDL(2) E14h -- E04h -- E33h B1EIDH(2) E23h B0EIDH(2) E13h -- E03h -- E32h B1SIDL(2) E22h B0SIDL(2) E12h -- E02h -- E31h B1SIDH(2) E21h B0SIDH(2) E11h -- E01h -- E30h B1CON(2) E20h B0CON(2) E10h -- E00h -- Note 1: 2: 3: B1D0 B0D0 Registers available only on PIC18F4X8X devices; otherwise, the registers read as `0'. When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties. This is not a physical register. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 73 PIC18F2682/2685/4682/4685 TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2682/2685/4682/4685 DEVICES (CONTINUED) Address Name DFFh -- Address Name DDFh -- Address Name DBFh -- Address Name D9Fh -- DFEh -- DDEh -- DBEh -- D9Eh -- DFDh -- DDDh -- DBDh -- D9Dh -- DFCh TXBIE DDCh -- DBCh -- D9Ch -- DFBh -- DDBh -- DBBh -- D9Bh -- DFAh BIE0 DDAh -- DBAh -- D9Ah -- DF9h -- DD9h -- DB9h -- D99h -- DF8h BSEL0 DD8h SDFLC DB8h -- D98h -- DF7h -- DD7h -- DB7h -- D97h -- DF6h -- DD6h -- DB6h -- D96h -- DF5h -- DD5h RXFCON1 DB5h -- D95h -- DF4h -- DD4h RXFCON0 DB4h -- D94h -- DF3h MSEL3 DD3h -- DB3h -- D93h RXF15EIDL DF2h MSEL2 DD2h -- DB2h -- D92h RXF15EIDH DF1h MSEL1 DD1h -- DB1h -- D91h RXF15SIDL DF0h MSEL0 DD0h -- DB0h -- D90h RXF15SIDH DEFh -- DCFh -- DAFh -- D8Fh -- DEEh -- DCEh -- DAEh -- D8Eh -- DEDh -- DCDh -- DADh -- D8Dh -- DECh -- DCCh -- DACh -- D8Ch -- DEBh -- DCBh -- DABh -- D8Bh RXF14EIDL DEAh -- DCAh -- DAAh -- D8Ah RXF14EIDH DE9h -- DC9h -- DA9h -- D89h RXF14SIDL DE8h -- DC8h -- DA8h -- D88h RXF14SIDH DE7h RXFBCON7 DC7h -- DA7h -- D87h RXF13EIDL DE6h RXFBCON6 DC6h -- DA6h -- D86h RXF13EIDH DE5h RXFBCON5 DC5h -- DA5h -- D85h RXF13SIDL DE4h RXFBCON4 DC4h -- DA4h -- D84h RXF13SIDH DE3h RXFBCON3 DC3h -- DA3h -- D83h RXF12EIDL DE2h RXFBCON2 DC2h -- DA2h -- D82h RXF12EIDH DE1h RXFBCON1 DC1h -- DA1h -- D81h RXF12SIDL DE0h RXFBCON0 DC0h -- DA0h -- D80h RXF12SIDH Note 1: 2: 3: Registers available only on PIC18F4X8X devices; otherwise, the registers read as `0'. When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties. This is not a physical register. DS39761B-page 74 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2682/2685/4682/4685 DEVICES (CONTINUED) Address Name D7Fh -- D7Eh -- D7Dh -- D7Ch -- D7Bh RXF11EIDL D7Ah RXF11EIDH D79h RXF11SIDL D78h RXF11SIDH D77h RXF10EIDL D76h RXF10EIDH D75h RXF10SIDL D74h RXF10SIDH D73h RXF9EIDL D72h RXF9EIDH D71h RXF9SIDL D70h RXF9SIDH D6Fh -- D6Eh -- D6Dh -- D6Ch -- D6Bh RXF8EIDL D6Ah RXF8EIDH D69h RXF8SIDL D68h RXF8SIDH D67h RXF7EIDL D66h RXF7EIDH D65h RXF7SIDL D64h RXF7SIDH D63h RXF6EIDL D62h RXF6EIDH D61h RXF6SIDL D60h RXF6SIDH Note 1: 2: 3: Registers available only on PIC18F4X8X devices; otherwise, the registers read as `0'. When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties. This is not a physical register. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 75 PIC18F2682/2685/4682/4685 TABLE 5-2: File Name TOSU REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) Bit 7 Bit 6 Bit 5 -- -- -- Bit 4 Top-of-Stack Register High Byte (TOS<15:8>) TOSL Top-of-Stack Register Low Byte (TOS<7:0>) STKFUL STKUNF -- PCLATU -- -- bit 21(1) Bit 2 Bit 1 Bit 0 Top-of-Stack Register Upper Byte (TOS<20:16>) TOSH STKPTR Bit 3 SP4 SP3 SP2 SP1 SP0 Holding Register for PC<20:16> Value on Details POR, BOR on page: ---0 0000 49, 62 0000 0000 49, 62 0000 0000 49, 62 00-0 0000 49, 63 ---0 0000 49, 62 PCLATH Holding Register for PC<15:8> 0000 0000 49, 62 PCL PC Low Byte (PC<7:0>) 0000 0000 49, 62 TBLPTRU -- -- bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 49, 103 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 49, 103 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 49, 103 TABLAT Program Memory Table Latch 0000 0000 49, 103 PRODH Product Register High Byte xxxx xxxx 49, 111 PRODL Product Register Low Byte xxxx xxxx 49, 111 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INTCON2 RBPU INTEDG0 INTEDG1 INTCON3 INT2IP INT1IP -- INT0IF RBIF 0000 000x 49, 115 INTEDG2 -- TMR0IP -- RBIP 1111 -1-1 49, 116 INT2IE INT1IE -- INT2IF INT1IF 11-0 0-00 49, 117 INDF0 Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) N/A 49, 89 POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) N/A 49, 90 POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register) N/A 49, 90 PREINC0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) N/A 49, 90 PLUSW0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register), value of FSR0 offset by W N/A 49, 90 FSR0H ---- xxxx 49, 89 FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 49, 89 WREG Working Register xxxx xxxx 49 INDF1 Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) N/A 49, 89 POSTINC1 Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) N/A 49, 90 POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register) N/A 49, 90 PREINC1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) N/A 49, 90 PLUSW1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register), value of FSR1 offset by W N/A 49, 90 FSR1H FSR1L BSR -- -- -- -- -- -- -- -- Indirect Data Memory Address Pointer 0 High Indirect Data Memory Address Pointer 1 High Indirect Data Memory Address Pointer 1 Low Byte -- -- -- -- Bank Select Register ---- xxxx 49, 89 xxxx xxxx 49, 89 ---- 0000 50, 67 INDF2 Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) N/A 50, 89 POSTINC2 Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) N/A 50, 90 POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) N/A 50, 90 PREINC2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) N/A 50, 90 PLUSW2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register), value of FSR2 offset by W N/A 50, 90 ---- xxxx 50, 89 xxxx xxxx 50, 89 FSR2H FSR2L -- -- -- -- Indirect Data Memory Address Pointer 2 High Indirect Data Memory Address Pointer 2 Low Byte Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as `0'. Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as `0'. See Section 4.4 "Brown-out Reset (BOR)". 3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as `0'. Reset values are shown for PIC18F4682/4685 devices; individual unimplemented bits should be interpreted as `--'. 4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as `0'. See Section 2.6.4 "PLL in INTOSC Modes". 5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as `0'. This bit is read-only. 6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. 7: CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. 9: These registers and/or bits are available on PIC18F4682/4685 devices only. DS39761B-page 76 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 5-2: File Name STATUS REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -- -- -- N OV Z DC C TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte T0CON Value on Details POR, BOR on page: ---x xxxx 50, 87 0000 0000 50, 149 xxxx xxxx 50, 149 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 50, 149 OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 HLVDCON VDIRMAG -- IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 WDTCON -- -- -- -- -- -- -- SWDTEN -- RI TO PD POR BOR RCON IPEN (2) SBOREN TMR1H Timer1 Register High Byte TMR1L Timer1 Register Low Byte T1CON RD16 T1RUN 30, 50 0-00 0101 50, 267 --- ---0 50, 354 0q-1 11q0 50, 127 xxxx xxxx 50, 155 0000 0000 50, 155 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 50, 151 TMR2 Timer2 Register 1111 1111 50, 158 PR2 Timer2 Period Register -000 0000 50, 155 T2CON -- T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 SSPBUF MSSP Receive Buffer/Transmit Register SSPADD MSSP Address Register in I2CTM Slave mode, MSSP Baud Rate Reload Register in I2C Master mode T2CKPS0 -000 0000 50, 157 xxxx xxxx 50, 195 0000 0000 50, 195 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 50, 197 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 50, 198 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN SSPCON2 ADRESH A/D Result Register High Byte ADRESL A/D Result Register Low Byte ADCON0 0000 0000 50, 199 xxxx xxxx 50, 256 xxxx xxxx 50, 256 -- -- CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 50, 247 ADCON1 -- -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0qqq 50, 248 ADCON2 ADFM -- ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 51, 249 CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 51, 168 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 51, 168 CCP1CON -- -- DC1B1 DC1B0 CCP1M3 ECCPR1H(9) Enhanced Capture/Compare/PWM Register 1 High Byte ECCPR1L(9) Enhanced Capture/Compare/PWM Register 1 Low Byte ECCP1CON(9) EPWM1M1 EPWM1M0 BAUDCON EDC1B1 EDC1B0 CCP1M2 CCP1M1 CCP1M0 --00 0000 51, 163 xxxx xxxx 51, 167 xxxx xxxx 51, 167 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 0000 0000 51, 168 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 01-0 0-00 51, 230 ECCP1DEL(9) PRSEN PDC6(3) PDC5(3) PDC4(3) PDC3(3) PDC2(3) PDC1(3) PDC0(3) 0000 0000 51, 182 ECCP1AS(9) ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(3) PSSBD0(3) 0000 0000 51, 183 CVRCON(9) CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 51, 263 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 CMCON(9) TMR3H Timer3 Register High Byte TMR3L Timer3 Register Low Byte T3CON RD16 (9) T3ECCP1 0000 0000 51, 257 xxxx xxxx 51, 161 xxxx xxxx 51, 161 T3CKPS1 T3CKPS0 (9) T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 51, 161 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as `0'. Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as `0'. See Section 4.4 "Brown-out Reset (BOR)". 3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as `0'. Reset values are shown for PIC18F4682/4685 devices; individual unimplemented bits should be interpreted as `--'. 4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as `0'. See Section 2.6.4 "PLL in INTOSC Modes". 5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as `0'. This bit is read-only. 6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. 7: CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. 9: These registers and/or bits are available on PIC18F4682/4685 devices only. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 77 PIC18F2682/2685/4682/4685 TABLE 5-2: File Name REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details POR, BOR on page: SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 51, 231 SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000 51, 231 RCREG EUSART Receive Register 0000 0000 51, 238 TXREG EUSART Transmit Register 0000 0000 51, 236 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 51, 237 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 51, 237 -- -- -- -- -- -- EEADRH EEPROM Addr Register High Byte ---- --00 51, 108 EEADR EEPROM Address Register Low Byte 0000 0000 51, 105 EEDATA EEPROM Data Register 0000 0000 51, 105 EECON2 EEPROM Control Register 2 (not a physical register) EECON1 0000 0000 51, 105 EEPGD CFGS -- FREE WRERR WREN WR RD xx-0 x000 51, 105 IPR3 Mode 0 IRXIP WAKIP ERRIP TXB2IP TXB1IP TXB0IP RXB1IP RXB0IP 1111 1111 51, 126 IPR3 Mode 1, 2 IRXIP WAKIP ERRIP TXBnIP TXB1IP(8) TXB0IP(8) RXBnIP FIFOWMIP 1111 1111 51, 126 PIR3 Mode 0 IRXIF WAKIF ERRIF TXB2IF TXB1IF TXB0IF RXB1IF RXB0IF 0000 0000 51, 120 PIR3 Mode 1, 2 IRXIF WAKIF ERRIF TXBnIF TXB1IF(8) TXB0IF(8) RXBnIF FIFOWMIF 0000 0000 51, 120 PIE3 Mode 0 IRXIE WAKIE ERRIE TXB2IE TXB1IE TXB0IE RXB1IE RXB0IE 0000 0000 51, 123 PIE3 Mode 1, 2 IRXIE WAKIE ERRIE TXBnIE TXB1IE(8) TXB0IE(8) RXBnIE FIFOMWIE 0000 0000 51, 123 IPR2 OSCFIP CMIP(9) -- EEIP BCLIP HLVDIP TMR3IP ECCP1IP(9) 11-1 1111 51, 125 PIR2 OSCFIF CMIF(9) -- EEIF BCLIF HLVDIF TMR3IF ECCP1IF(9) 00-0 0000 52, 119 PIE2 OSCFIE CMIE(9) -- EEIE BCLIE HLVDIE TMR3IE ECCP1IE(9) 00-0 0000 52, 122 IPR1 PSPIP(3) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 52, 124 PIR1 PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 52, 118 PIE1 PSPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 52, 121 OSCTUNE INTSRC PLLEN(4) -- TUN4 TUN3 TUN2 TUN1 TUN0 IBF OBF IBOV PSPMODE -- TRISE2 TRISE1 TRISE0 TRISE(3) 0q-0 0000 27, 52 0000 -111 52, 141 TRISD(3) PORTD Data Direction Register TRISC PORTC Data Direction Register 1111 1111 52, 135 TRISB PORTB Data Direction Register 1111 1111 52, 132 TRISA TRISA7(6) TRISA6(6) LATE(3) -- -- 1111 1111 52, 138 PORTA Data Direction Register -- -- 1111 1111 52, 129 -- LATE Data Output Register ---- -xxx 52, 141 LATD(3) LATD Data Output Register LATC LATC Data Output Register xxxx xxxx 52, 135 LATB LATB Data Output Register xxxx xxxx 52, 132 xxxx xxxx 52, 138 LATA7(6) LATA6(6) PORTE(3) -- -- -- -- RE3(5) RE2(3) RE1(3) RE0(3) PORTD(3) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 52, 138 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 52, 135 LATA LATA Data Output Register xxxx xxxx 52, 129 ---- xxxx 52, 145 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as `0'. Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as `0'. See Section 4.4 "Brown-out Reset (BOR)". 3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as `0'. Reset values are shown for PIC18F4682/4685 devices; individual unimplemented bits should be interpreted as `--'. 4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as `0'. See Section 2.6.4 "PLL in INTOSC Modes". 5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as `0'. This bit is read-only. 6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. 7: CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. 9: These registers and/or bits are available on PIC18F4682/4685 devices only. DS39761B-page 78 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 5-2: File Name REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details POR, BOR on page: PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 52, 132 PORTA RA7(6) RA6(6) RA5 RA4 RA3 RA2 RA1 RA0 xx00 0000 52, 129 ECANCON MDSEL1 MDSEL0 FIFOWM EWIN4 EWIN3 EWIN2 EWIN1 EWIN0 TXERRCNT TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 REC7 REC6 RXERRCNT COMSTAT Mode 0 COMSTAT Mode 1 COMSTAT Mode 2 CIOCON 0001 000 52, 280 0000 0000 52, 285 REC5 REC4 REC3 REC2 REC1 REC0 0000 0000 52, 294 TXBO TXBP RXBP TXWARN RXWARN EWARN 0000 0000 52, 281 RXBnOVFL TXBO TXBP RXBP TXWARN RXWARN EWARN -000 0000 52, 281 FIFOEMPT RXBnOVFL Y TXBO TXBP RXBP TXWARN RXWARN EWARN 0000 0000 52, 281 --00 ---- 52, 315 RXB0OVFL RXB1OVFL -- -- -- ENDRHI CANCAP -- -- -- -- BRGCON3 WAKDIS WAKFIL -- -- -- SEG2PH2 SEG2PH1 SEG2PH0 00-- -000 53, 314 BRGCON2 SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0 0000 0000 53, 313 BRGCON1 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 0000 0000 53, 312 CANCON Mode 0 REQOP2 REQOP1 REQOP0 ABAT WIN2(7) WIN1(7) WIN0(7) --(7) 1000 000- 53, 276 CANCON Mode 1 REQOP2 REQOP1 REQOP0 ABAT --(7) --(7) --(7) --(7) 1000 ---- 53, 276 CANCON Mode 2 REQOP2 REQOP1 REQOP0 ABAT FP3(7) FP2(7) FP1(7) FP0(7) 1000 0000 53, 276 CANSTAT Mode 0 OPMODE2 OPMODE1 OPMODE0 --(7) ICODE3(7) ICODE2(7) ICODE1(7) --(7) 100- 000- 53, 277 CANSTAT Modes 1, 2 OPMODE2 OPMODE1 OPMODE0 EICODE4(7) EICODE3(7) EICODE2(7) EICODE1(7) EICODE0(7) 1000 0000 53, 277 RXB0D7 RXB0D77 RXB0D76 RXB0D75 RXB0D74 RXB0D73 RXB0D72 RXB0D71 RXB0D70 xxxx xxxx 53, 293 RXB0D6 RXB0D67 RXB0D66 RXB0D65 RXB0D64 RXB0D63 RXB0D62 RXB0D61 RXB0D60 xxxx xxxx 53, 293 xxxx xxxx 53, 293 RXB0D5 RXB0D57 RXB0D56 RXB0D55 RXB0D54 RXB0D53 RXB0D52 RXB0D51 RXB0D50 RXB0D4 RXB0D47 RXB0D46 RXB0D45 RXB0D44 RXB0D43 RXB0D42 RXB0D41 RXB0D40 xxxx xxxx 53, 293 RXB0D3 RXB0D37 RXB0D36 RXB0D35 RXB0D34 RXB0D33 RXB0D32 RXB0D31 RXB0D30 xxxx xxxx 53, 293 RXB0D2 RXB0D27 RXB0D26 RXB0D25 RXB0D24 RXB0D23 RXB0D22 RXB0D21 RXB0D20 xxxx xxxx 53, 293 RXB0D1 RXB0D17 RXB0D16 RXB0D15 RXB0D14 RXB0D13 RXB0D12 RXB0D11 RXB0D10 xxxx xxxx 53, 293 RXB0D0 RXB0D07 RXB0D06 RXB0D05 RXB0D04 RXB0D03 RXB0D02 RXB0D01 RXB0D00 xxxx xxxx 53, 293 -- RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 53, 293 RXB0DLC RXB0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 53, 292 RXB0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 53, 292 RXB0SIDL SID2 SID1 SID0 SRR EXID -- EID17 EID16 xxxx x-xx 53, 292 RXB0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 53, 291 RXB0CON Mode 0 RXFUL RXM1 RXM0(7) --(7) JTOFF(7) FILHIT0(7) 000- 0000 53, 288 RXB0CON Mode 1, 2 RXFUL RXM1 RTRRO FILHIT4 FILHIT1 FILHIT0 0000 0000 53, 288 RXRTRRO(7) RXBODBEN(7) FILHIT3 FILHIT2 RXB1D7 RXB1D77 RXB1D76 RXB1D75 RXB1D74 RXB1D73 RXB1D72 RXB1D71 RXB1D70 xxxx xxxx 53, 293 RXB1D6 RXB1D67 RXB1D66 RXB1D65 RXB1D64 RXB1D63 RXB1D62 RXB1D61 RXB1D60 xxxx xxxx 53, 293 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as `0'. Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as `0'. See Section 4.4 "Brown-out Reset (BOR)". 3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as `0'. Reset values are shown for PIC18F4682/4685 devices; individual unimplemented bits should be interpreted as `--'. 4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as `0'. See Section 2.6.4 "PLL in INTOSC Modes". 5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as `0'. This bit is read-only. 6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. 7: CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. 9: These registers and/or bits are available on PIC18F4682/4685 devices only. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 79 PIC18F2682/2685/4682/4685 TABLE 5-2: File Name REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details POR, BOR on page: RXB1D5 RXB1D57 RXB1D56 RXB1D55 RXB1D54 RXB1D53 RXB1D52 RXB1D51 RXB1D50 xxxx xxxx 53, 293 RXB1D4 RXB1D47 RXB1D46 RXB1D45 RXB1D44 RXB1D43 RXB1D42 RXB1D41 RXB1D40 xxxx xxxx 53, 293 RXB1D3 RXB1D37 RXB1D36 RXB1D35 RXB1D34 RXB1D33 RXB1D32 RXB1D31 RXB1D30 xxxx xxxx 53, 293 RXB1D2 RXB1D27 RXB1D26 RXB1D25 RXB1D24 RXB1D23 RXB1D22 RXB1D21 RXB1D20 xxxx xxxx 53, 293 RXB1D1 RXB1D17 RXB1D16 RXB1D15 RXB1D14 RXB1D13 RXB1D12 RXB1D11 RXB1D10 xxxx xxxx 53, 293 RXB1D0 RXB1D07 RXB1D06 RXB1D05 RXB1D04 RXB1D03 RXB1D02 RXB1D01 RXB1D00 xxxx xxxx 53, 293 RXB1DLC -- RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 53, 293 RXB1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 53, 292 xxxx xxxx 53, 292 RXB1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 RXB1SIDL SID2 SID1 SID0 SRR EXID -- EID17 EID16 xxxx xxxx 53, 292 RXB1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 54, 291 RXB1CON Mode 0 RXFUL RXM1 RXM0(7) --(7) RXRTRRO(7) FILHIT2(7) FILHIT1(7) FILHIT0(7) 000- 0000 54, 290 RXB1CON Mode 1, 2 RXFUL RXM1 RTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 0000 0000 54, 290 TXB0D7 TXB0D77 TXB0D76 TXB0D75 TXB0D74 TXB0D73 TXB0D72 TXB0D71 TXB0D70 xxxx xxxx 54, 284 TXB0D6 TXB0D67 TXB0D66 TXB0D65 TXB0D64 TXB0D63 TXB0D62 TXB0D61 TXB0D60 xxxx xxxx 54, 284 TXB0D5 TXB0D57 TXB0D56 TXB0D55 TXB0D54 TXB0D53 TXB0D52 TXB0D51 TXB0D50 xxxx xxxx 54, 284 TXB0D4 TXB0D47 TXB0D46 TXB0D45 TXB0D44 TXB0D43 TXB0D42 TXB0D41 TXB0D40 xxxx xxxx 54, 284 TXB0D3 TXB0D37 TXB0D36 TXB0D35 TXB0D34 TXB0D33 TXB0D32 TXB0D31 TXB0D30 xxxx xxxx 54, 284 TXB0D2 TXB0D27 TXB0D26 TXB0D25 TXB0D24 TXB0D23 TXB0D22 TXB0D21 TXB0D20 xxxx xxxx 54, 284 TXB0D1 TXB0D17 TXB0D16 TXB0D15 TXB0D14 TXB0D13 TXB0D12 TXB0D11 TXB0D10 xxxx xxxx 54, 284 TXB0D0 TXB0D07 TXB0D06 TXB0D05 TXB0D04 TXB0D03 TXB0D02 TXB0D01 TXB0D00 xxxx xxxx 54, 284 TXB0DLC -- TXRTR -- -- DLC3 DLC2 DLC1 DLC0 -x-- xxxx 54, 285 TXB0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 54, 284 xxxx xxxx 54, 283 TXB0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 TXB0SIDL SID2 SID1 SID0 -- EXIDE -- EID17 EID16 xxx- x-xx 54, 283 TXB0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 54, 283 TXB0CON TXB1D7 TXBIF TXABT TXLARB TXERR TXREQ -- TXPRI1 TXPRI0 0000 0-00 54, 282 TXB1D77 TXB1D76 TXB1D75 TXB1D74 TXB1D73 TXB1D72 TXB1D71 TXB1D70 xxxx xxxx 54, 284 xxxx xxxx 54, 284 TXB1D6 TXB1D67 TXB1D66 TXB1D65 TXB1D64 TXB1D63 TXB1D62 TXB1D61 TXB1D60 TXB1D5 TXB1D57 TXB1D56 TXB1D55 TXB1D54 TXB1D53 TXB1D52 TXB1D51 TXB1D50 xxxx xxxx 54, 284 TXB1D4 TXB1D47 TXB1D46 TXB1D45 TXB1D44 TXB1D43 TXB1D42 TXB1D41 TXB1D40 xxxx xxxx 54, 284 TXB1D3 TXB1D37 TXB1D36 TXB1D35 TXB1D34 TXB1D33 TXB1D32 TXB1D31 TXB1D30 xxxx xxxx 54, 284 TXB1D2 TXB1D27 TXB1D26 TXB1D25 TXB1D24 TXB1D23 TXB1D22 TXB1D21 TXB1D20 xxxx xxxx 54, 284 TXB1D1 TXB1D17 TXB1D16 TXB1D15 TXB1D14 TXB1D13 TXB1D12 TXB1D11 TXB1D10 xxxx xxxx 54, 284 TXB1D0 TXB1D07 TXB1D06 TXB1D05 TXB1D04 TXB1D03 TXB1D02 TXB1D01 TXB1D00 xxxx xxxx 54, 284 TXB1DLC -- TXRTR -- -- DLC3 DLC2 DLC1 DLC0 -x-- xxxx 54, 285 TXB1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 54, 284 xxxx xxxx 54, 283 TXB1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 TXB1SIDL SID2 SID1 SID0 -- EXIDE -- EID17 EID16 xxx- x-xx 54, 283 TXB1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 54, 283 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as `0'. Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as `0'. See Section 4.4 "Brown-out Reset (BOR)". 3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as `0'. Reset values are shown for PIC18F4682/4685 devices; individual unimplemented bits should be interpreted as `--'. 4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as `0'. See Section 2.6.4 "PLL in INTOSC Modes". 5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as `0'. This bit is read-only. 6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. 7: CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. 9: These registers and/or bits are available on PIC18F4682/4685 devices only. DS39761B-page 80 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 5-2: File Name TXB1CON TXB2D7 REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details POR, BOR on page: TXBIF TXABT TXLARB TXERR TXREQ -- TXPRI1 TXPRI0 0000 0-00 54, 282 TXB2D77 TXB2D76 TXB2D75 TXB2D74 TXB2D73 TXB2D72 TXB2D71 TXB2D70 xxxx xxxx 54, 284 xxxx xxxx 55, 284 TXB2D6 TXB2D67 TXB2D66 TXB2D65 TXB2D64 TXB2D63 TXB2D62 TXB2D61 TXB2D60 TXB2D5 TXB2D57 TXB2D56 TXB2D55 TXB2D54 TXB2D53 TXB2D52 TXB2D51 TXB2D50 xxxx xxxx 55, 284 TXB2D4 TXB2D47 TXB2D46 TXB2D45 TXB2D44 TXB2D43 TXB2D42 TXB2D41 TXB2D40 xxxx xxxx 55, 284 TXB2D3 TXB2D37 TXB2D36 TXB2D35 TXB2D34 TXB2D33 TXB2D32 TXB2D31 TXB2D30 xxxx xxxx 55, 284 TXB2D2 TXB2D27 TXB2D26 TXB2D25 TXB2D24 TXB2D23 TXB2D22 TXB2D21 TXB2D20 xxxx xxxx 55, 284 TXB2D1 TXB2D17 TXB2D16 TXB2D15 TXB2D14 TXB2D13 TXB2D12 TXB2D11 TXB2D10 xxxx xxxx 55, 284 TXB2D0 TXB2D07 TXB2D06 TXB2D05 TXB2D04 TXB2D03 TXB2D02 TXB2D01 TXB2D00 xxxx xxxx 55, 284 TXB2DLC -- TXRTR -- -- DLC3 DLC2 DLC1 DLC0 -x-- xxxx 55, 285 TXB2EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 55, 284 xxxx xxxx 55, 283 TXB2EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 TXB2SIDL SID2 SID1 SID0 -- EXIDE -- EID17 EID16 xxxx x-xx 55, 283 TXB2SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxx- x-xx 55, 283 TXB2CON TXBIF TXABT TXLARB TXERR TXREQ -- TXPRI1 TXPRI0 0000 0-00 55, 282 RXM1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 55, 305 xxxx xxxx 55, 305 RXM1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 RXM1SIDL SID2 SID1 SID0 -- EXIDEN -- EID17 EID16 xxx- x-xx 55, 305 RXM1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 55, 304 RXM0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 55, 305 RXM0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 55, 305 RXM0SIDL SID2 SID1 SID0 -- EXIDEN -- EID17 EID16 xxx- x-xx 55, 305 RXM0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 55, 304 RXF5EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 55, 304 RXF5EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 55, 304 RXF5SIDL SID2 SID1 SID0 -- EXIDEN -- EID17 EID16 xxx- x-xx 55, 303 RXF5SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 55, 304 RXF4EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 55, 304 RXF4EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 55, 304 RXF4SIDL SID2 SID1 SID0 -- EXIDEN -- EID17 EID16 xxx- x-xx 55, 303 RXF4SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 55, 304 RXF3EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 55, 304 RXF3EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 55, 304 RXF3SIDL SID2 SID1 SID0 -- EXIDEN -- EID17 EID16 xxx- x-xx 56, 303 RXF3SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 56, 304 RXF2EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 56, 304 RXF2EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 56, 304 RXF2SIDL SID2 SID1 SID0 -- EXIDEN -- EID17 EID16 xxx- x-xx 56, 303 RXF2SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 56, 304 RXF1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 56, 304 RXF1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 56, 304 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as `0'. Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as `0'. See Section 4.4 "Brown-out Reset (BOR)". 3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as `0'. Reset values are shown for PIC18F4682/4685 devices; individual unimplemented bits should be interpreted as `--'. 4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as `0'. See Section 2.6.4 "PLL in INTOSC Modes". 5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as `0'. This bit is read-only. 6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. 7: CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. 9: These registers and/or bits are available on PIC18F4682/4685 devices only. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 81 PIC18F2682/2685/4682/4685 TABLE 5-2: File Name REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 RXF1SIDL SID2 SID1 RXF1SIDH SID10 SID9 SID0 -- SID8 SID7 Value on Details POR, BOR on page: Bit 2 Bit 1 Bit 0 EXIDEN -- EID17 EID16 xxx- x-xx 56, 303 SID6 SID5 SID4 SID3 xxxx xxxx 56, 304 RXF0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 56, 304 RXF0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 56, 304 RXF0SIDL SID2 SID1 SID0 -- EXIDEN -- EID17 EID16 xxx- x-xx 56, 303 RXF0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 56, 304 B5D7(8) B5D77 B5D76 B5D75 B5D74 B5D73 B5D72 B5D71 B5D70 xxxx xxxx 56, 300 B5D6(8) B5D67 B5D66 B5D65 B5D64 B5D63 B5D62 B5D61 B5D60 xxxx xxxx 56, 300 B5D5(8) B5D57 B5D56 B5D55 B5D54 B5D53 B5D52 B5D51 B5D50 xxxx xxxx 56, 300 B5D4(8) B5D47 B5D46 B5D45 B5D44 B5D43 B5D42 B5D41 B5D40 xxxx xxxx 56, 300 B5D3(8) B5D37 B5D36 B5D35 B5D34 B5D33 B5D32 B5D31 B5D30 xxxx xxxx 56, 300 B5D2(8) B5D27 B5D26 B5D25 B5D24 B5D23 B5D22 B5D21 B5D20 xxxx xxxx 56, 300 B5D1(8) B5D17 B5D16 B5D15 B5D14 B5D13 B5D12 B5D11 B5D10 xxxx xxxx 56, 300 B5D0(8) B5D07 B5D06 B5D05 B5D04 B5D03 B5D02 B5D01 B5D00 xxxx xxxx 56, 300 B5DLC(8) Receive mode -- RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 56, 301 B5DLC(8) Transmit mode -- TXRTR -- -- DLC3 DLC2 DLC1 DLC0 -x-- xxxx 56, 302 xxxx xxxx 56, 299 B5EIDL(8) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 B5EIDH(8) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 56, 299 B5SIDL(8) Receive mode SID2 SID1 SID0 SRR EXID -- EID17 EID16 xxxx x-xx 56, 298 B5SIDL(8) Transmit mode SID2 SID1 SID0 -- EXIDE -- EID17 EID16 xxx- x-xx 56, 298 B5SIDH(8) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx x-xx 56, 297 B5CON(8) Receive mode RXFUL RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 0000 0000 56, 296 B5CON(8) Transmit mode TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 0000 0000 56, 296 B4D7(8) B4D77 B4D76 B4D75 B4D74 B4D73 B4D72 B4D71 B4D70 xxxx xxxx 56, 300 B4D6(8) B4D67 B4D66 B4D65 B4D64 B4D63 B4D62 B4D61 B4D60 xxxx xxxx 56, 300 B4D5(8) B4D57 B4D56 B4D55 B4D54 B4D53 B4D52 B4D51 B4D50 xxxx xxxx 56, 300 B4D4(8) B4D47 B4D46 B4D45 B4D44 B4D43 B4D42 B4D41 B4D40 xxxx xxxx 57, 300 B4D3(8) B4D37 B4D36 B4D35 B4D34 B4D33 B4D32 B4D31 B4D30 xxxx xxxx 57, 300 B4D2(8) B4D27 B4D26 B4D25 B4D24 B4D23 B4D22 B4D21 B4D20 xxxx xxxx 57, 300 B4D1(8) B4D17 B4D16 B4D15 B4D14 B4D13 B4D12 B4D11 B4D10 xxxx xxxx 57, 300 B4D0(8) B4D07 B4D06 B4D05 B4D04 B4D03 B4D02 B4D01 B4D00 xxxx xxxx 56, 300 B4DLC(8) Receive mode -- RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 56, 301 B4DLC(8) Transmit mode -- TXRTR -- -- DLC3 DLC2 DLC1 DLC0 -x-- xxxx 56, 302 B4EIDL(8) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 57, 299 B4EIDH(8) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 57, 299 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as `0'. Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as `0'. See Section 4.4 "Brown-out Reset (BOR)". 3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as `0'. Reset values are shown for PIC18F4682/4685 devices; individual unimplemented bits should be interpreted as `--'. 4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as `0'. See Section 2.6.4 "PLL in INTOSC Modes". 5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as `0'. This bit is read-only. 6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. 7: CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. 9: These registers and/or bits are available on PIC18F4682/4685 devices only. DS39761B-page 82 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details POR, BOR on page: B4SIDL(8) Receive mode SID2 SID1 SID0 SRR EXID -- EID17 EID16 xxxx x-xx 56, 298 B4SIDL(8) Transmit mode SID2 SID1 SID0 -- EXIDE -- EID17 EID16 xxx- x-xx 56, 298 B4SIDH(8) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 57, 297 B4CON(8) Receive mode RXFUL RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 0000 0000 57, 296 B4CON(8) Transmit mode TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 0000 0000 57, 296 B3D7(8) B3D77 B3D76 B3D75 B3D74 B3D73 B3D72 B3D71 B3D70 xxxx xxxx 57, 300 B3D6(8) B3D67 B3D66 B3D65 B3D64 B3D63 B3D62 B3D61 B3D60 xxxx xxxx 57, 300 B3D5(8) B3D57 B3D56 B3D55 B3D54 B3D53 B3D52 B3D51 B3D50 xxxx xxxx 57, 300 B3D4(8) B3D47 B3D46 B3D45 B3D44 B3D43 B3D42 B3D41 B3D40 xxxx xxxx 57, 300 B3D3(8) B3D37 B3D36 B3D35 B3D34 B3D33 B3D32 B3D31 B3D30 xxxx xxxx 57, 300 B3D2(8) B3D27 B3D26 B3D25 B3D24 B3D23 B3D22 B3D21 B3D20 xxxx xxxx 57, 300 B3D1(8) B3D17 B3D16 B3D15 B3D14 B3D13 B3D12 B3D11 B3D10 xxxx xxxx 57, 300 B3D0(8) B3D07 B3D06 B3D05 B3D04 B3D03 B3D02 B3D01 B3D00 xxxx xxxx 57, 300 B3DLC(8) Receive mode -- RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 56, 301 B3DLC(8) Transmit mode -- TXRTR -- -- DLC3 DLC2 DLC1 DLC0 -x-- xxxx 56, 302 xxxx xxxx 57, 299 B3EIDL(8) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 B3EIDH(8) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 57, 299 B3SIDL(8) Receive mode SID2 SID1 SID0 SRR EXID -- EID17 EID16 xxxx x-xx 56, 298 B3SIDL(8) Transmit mode SID2 SID1 SID0 -- EXIDE -- EID17 EID16 xxx- x-xx 56, 298 B3SIDH(8) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 57, 297 B3CON(8) Receive mode RXFUL RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 0000 0000 57, 296 B3CON(8) Transmit mode TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 0000 0000 57, 296 B2D7(8) B2D77 B2D76 B2D75 B2D74 B2D73 B2D72 B2D71 B2D70 xxxx xxxx 57, 300 B2D6(8) B2D67 B2D66 B2D65 B2D64 B2D63 B2D62 B2D61 B2D60 xxxx xxxx 57, 300 B2D5(8) B2D57 B2D56 B2D55 B2D54 B2D53 B2D52 B2D51 B2D50 xxxx xxxx 57, 300 B2D4(8) B2D47 B2D46 B2D45 B2D44 B2D43 B2D42 B2D41 B2D40 xxxx xxxx 57, 300 B2D3(8) B2D37 B2D36 B2D35 B2D34 B2D33 B2D32 B2D31 B2D30 xxxx xxxx 57, 300 B2D2(8) B2D27 B2D26 B2D25 B2D24 B2D23 B2D22 B2D21 B2D20 xxxx xxxx 57, 300 B2D1(8) B2D17 B2D16 B2D15 B2D14 B2D13 B2D12 B2D11 B2D10 xxxx xxxx 58, 300 B2D0(8) B2D07 B2D06 B2D05 B2D04 B2D03 B2D02 B2D01 B2D00 xxxx xxxx 58, 300 B2DLC(8) Receive mode -- RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 56, 301 B2DLC(8) Transmit mode -- TXRTR -- -- DLC3 DLC2 DLC1 DLC0 -x-- xxxx 56, 302 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as `0'. Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as `0'. See Section 4.4 "Brown-out Reset (BOR)". 3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as `0'. Reset values are shown for PIC18F4682/4685 devices; individual unimplemented bits should be interpreted as `--'. 4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as `0'. See Section 2.6.4 "PLL in INTOSC Modes". 5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as `0'. This bit is read-only. 6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. 7: CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. 9: These registers and/or bits are available on PIC18F4682/4685 devices only. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 83 PIC18F2682/2685/4682/4685 TABLE 5-2: File Name REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details POR, BOR on page: xxxx xxxx 58, 299 B2EIDL(8) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 B2EIDH(8) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 58, 299 B2SIDL(8) Receive mode SID2 SID1 SID0 SRR EXID -- EID17 EID16 xxxx x-xx 56, 298 B2SIDL(8) Transmit mode SID2 SID1 SID0 -- EXIDE -- EID17 EID16 xxx- x-xx 56, 298 B2SIDH(8) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 58, 297 B2CON(8) Receive mode RXFUL RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 0000 0000 58, 296 B2CON(8) Transmit mode TXBIF RXM1 TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 0000 0000 58, 296 B1D7(8) B1D77 B1D76 B1D75 B1D74 B1D73 B1D72 B1D71 B1D70 xxxx xxxx 58, 300 B1D6(8) B1D67 B1D66 B1D65 B1D64 B1D63 B1D62 B1D61 B1D60 xxxx xxxx 58, 300 B1D5(8) B1D57 B1D56 B1D55 B1D54 B1D53 B1D52 B1D51 B1D50 xxxx xxxx 58, 300 B1D4(8) B1D47 B1D46 B1D45 B1D44 B1D43 B1D42 B1D41 B1D40 xxxx xxxx 58, 300 B1D3(8) B1D37 B1D36 B1D35 B1D34 B1D33 B1D32 B1D31 B1D30 xxxx xxxx 58, 300 B1D2(8) B1D27 B1D26 B1D25 B1D24 B1D23 B1D22 B1D21 B1D20 xxxx xxxx 58, 300 B1D1(8) B1D17 B1D16 B1D15 B1D14 B1D13 B1D12 B1D11 B1D10 xxxx xxxx 58, 300 B1D0(8) B1D07 B1D06 B1D05 B1D04 B1D03 B1D02 B1D01 B1D00 xxxx xxxx 58, 300 B1DLC(8) Receive mode -- RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 56, 301 B1DLC(8) Transmit mode -- TXRTR -- -- DLC3 DLC2 DLC1 DLC0 -x-- xxxx 56, 302 xxxx xxxx 58, 299 B1EIDL(8) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 B1EIDH(8) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 58, 299 B1SIDL(8) Receive mode SID2 SID1 SID0 SRR EXID -- EID17 EID16 xxxx x-xx 56, 298 B1SIDL(8) Transmit mode SID2 SID1 SID0 -- EXIDE -- EID17 EID16 xxx- x-xx 56, 298 B1SIDH(8) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 58, 297 B1CON(8) Receive mode RXFUL RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 0000 0000 58, 296 B1CON(8) Transmit mode TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 0000 0000 58, 296 B0D7(8) B0D77 B0D76 B0D75 B0D74 B0D73 B0D72 B0D71 B0D70 xxxx xxxx 58, 300 B0D6(8) B0D67 B0D66 B0D65 B0D64 B0D63 B0D62 B0D61 B0D60 xxxx xxxx 58, 300 B0D5(8) B0D57 B0D56 B0D55 B0D54 B0D53 B0D52 B0D51 B0D50 xxxx xxxx 58, 300 B0D4(8) B0D47 B0D46 B0D45 B0D44 B0D43 B0D42 B0D41 B0D40 xxxx xxxx 58, 300 B0D3(8) B0D37 B0D36 B0D35 B0D34 B0D33 B0D32 B0D31 B0D30 xxxx xxxx 58, 300 B0D2(8) B0D27 B0D26 B0D25 B0D24 B0D23 B0D22 B0D21 B0D20 xxxx xxxx 58, 300 B0D1(8) B0D17 B0D16 B0D15 B0D14 B0D13 B0D12 B0D11 B0D10 xxxx xxxx 58, 300 B0D0(8) B0D07 B0D06 B0D05 B0D04 B0D03 B0D02 B0D01 B0D00 xxxx xxxx 58, 300 -- RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 56, 301 B0DLC(8) Receive mode Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as `0'. Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as `0'. See Section 4.4 "Brown-out Reset (BOR)". 3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as `0'. Reset values are shown for PIC18F4682/4685 devices; individual unimplemented bits should be interpreted as `--'. 4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as `0'. See Section 2.6.4 "PLL in INTOSC Modes". 5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as `0'. This bit is read-only. 6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. 7: CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. 9: These registers and/or bits are available on PIC18F4682/4685 devices only. DS39761B-page 84 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details POR, BOR on page: B0DLC(8) Transmit mode -- TXRTR -- -- DLC3 DLC2 DLC1 DLC0 -x-- xxxx 56, 302 xxxx xxxx 59, 299 B0EIDL(8) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 B0EIDH(8) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 59, 299 B0SIDL(8) Receive mode SID2 SID1 SID0 SRR EXID -- EID17 EID16 xxxx x-xx 56, 298 B0SIDL(8) Transmit mode SID2 SID1 SID0 -- EXIDE -- EID17 EID16 xxx- x-xx 56, 298 B0SIDH(8) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 59, 297 B0CON(8) Receive mode RXFUL RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 0000 0000 58, 296 B0CON(8) Transmit mode TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 0000 0000 58, 296 TXBIE -- -- -- TXB2IE TXB1IE TXB0IE -- -- ---0 00-- 59, 319 B5IE B4IE B3IE B2IE B1IE B0IE RXB1IE RXB0IE 0000 0000 59, 319 BSEL0 B5TXEN B4TXEN B3TXEN B2TXEN B1TXEN B0TXEN -- -- MSEL3 FIL15_1 FIL15_0 FIL14_1 FIL14_0 FIL13_1 FIL13_0 FIL12_1 FIL12_0 0000 0000 MSEL2 FIL11_1 FIL11_0 FIL10_1 FIL10_0 FIL9_1 FIL9_0 FIL8_1 FIL8_0 0000 0000 59, 310 BIE0 0000 00-- 59, 302 59, 311 MSEL1 FIL7_1 FIL7_0 FIL6_1 FIL6_0 FIL5_1 FIL5_0 FIL4_1 FIL4_0 0000 0101 59, 309 MSEL0 FIL3_1 FIL3_0 FIL2_1 FIL2_0 FIL1_1 FIL1_0 FIL0_1 FIL0_0 0101 0000 59, 308 RXFBCON7 F15BP_3 F15BP_2 F15BP_1 F15BP_0 F14BP_3 F14BP_2 F14BP_1 F14BP_0 0000 0000 59, 307 RXFBCON6 F13BP_3 F13BP_2 F13BP_1 F13BP_0 F12BP_3 F12BP_2 F12BP_1 F12BP_0 0000 0000 59, 307 RXFBCON5 F11BP_3 F11BP_2 F11BP_1 F11BP_0 F10BP_3 F10BP_2 F10BP_1 F10BP_0 0000 0000 59, 307 RXFBCON4 F9BP_3 F9BP_2 F9BP_1 F9BP_0 F8BP_3 F8BP_2 F8BP_1 F8BP_0 0000 0000 59, 307 RXFBCON3 F7BP_3 F7BP_2 F7BP_1 F7BP_0 F6BP_3 F6BP_2 F6BP_1 F6BP_0 0000 0000 59, 307 RXFBCON2 F5BP_3 F5BP_2 F5BP_1 F5BP_0 F4BP_3 F4BP_2 F4BP_1 F4BP_0 0001 0001 59, 307 RXFBCON1 F3BP_3 F3BP_2 F3BP_1 F3BP_0 F2BP_3 F2BP_2 F2BP_1 F2BP_0 0001 0001 59, 307 RXFBCON0 F1BP_3 F1BP_2 F1BP_1 F1BP_0 F0BP_3 F0BP_2 F0BP_1 F0BP_0 0000 0000 59, 307 SDFLC -- -- -- FLC4 FLC3 FLC2 FLC1 FLC0 ---0 0000 59, 306 RXFCON1 RXF15EN RXF14EN RXF13EN RXF12EN RXF11EN RXF10EN RXF9EN RXF8EN 0000 0000 59, 306 0000 0000 59, 306 RXFCON0 RXF7EN RXF6EN RXF5EN RXF4EN RXF3EN RXF2EN RXF1EN RXF0EN RXF15EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 59, 304 RXF15EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 59, 304 RXF15SIDL SID2 SID1 SID0 -- EXIDEN -- EID17 EID16 xxx- x-xx 59, 303 RXF15SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 59, 303 RXF14EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 59, 304 RXF14EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 59, 304 RXF14SIDL SID2 SID1 SID0 -- EXIDEN -- EID17 EID16 xxx- x-xx 59, 303 RXF14SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 59, 303 RXF13EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 60, 304 RXF13EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 60, 304 RXF13SIDL SID2 SID1 SID0 -- EXIDEN -- EID17 EID16 xxx- x-xx 60, 303 RXF13SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 60, 303 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as `0'. Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as `0'. See Section 4.4 "Brown-out Reset (BOR)". 3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as `0'. Reset values are shown for PIC18F4682/4685 devices; individual unimplemented bits should be interpreted as `--'. 4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as `0'. See Section 2.6.4 "PLL in INTOSC Modes". 5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as `0'. This bit is read-only. 6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. 7: CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. 9: These registers and/or bits are available on PIC18F4682/4685 devices only. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 85 PIC18F2682/2685/4682/4685 TABLE 5-2: File Name REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details POR, BOR on page: RXF12EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 60, 304 RXF12EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 60, 304 RXF12SIDL SID2 SID1 SID0 -- EXIDEN -- EID17 EID16 xxx- x-xx 60, 303 RXF12SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 60, 303 RXF11EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 60, 304 RXF11EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 60, 304 RXF11SIDL SID2 SID1 SID0 -- EXIDEN -- EID17 EID16 xxx- x-xx 60, 303 RXF11SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 60, 303 RXF10EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 60, 304 RXF10EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 60, 304 RXF10SIDL SID2 SID1 SID0 -- EXIDEN -- EID17 EID16 xxx- x-xx 60, 303 RXF10SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 60, 303 RXF9EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 60, 304 RXF9EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 60, 304 RXF9SIDL SID2 SID1 SID0 -- EXIDEN -- EID17 EID16 xxx- x-xx 60, 303 RXF9SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 60, 303 RXF8EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 60, 304 RXF8EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 60, 304 RXF8SIDL SID2 SID1 SID0 -- EXIDEN -- EID17 EID16 xxx- x-xx 60, 303 RXF8SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 60, 303 RXF7EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 60, 304 RXF7EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 60, 304 RXF7SIDL SID2 SID1 SID0 -- EXIDEN -- EID17 EID16 xxx- x-xx 60, 303 RXF7SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 60, 303 RXF6EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 60, 304 RXF6EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 60, 304 RXF6SIDL SID2 SID1 SID0 -- EXIDEN -- EID17 EID16 xxx- x-xx 60, 303 RXF6SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 60, 303 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as `0'. Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as `0'. See Section 4.4 "Brown-out Reset (BOR)". 3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as `0'. Reset values are shown for PIC18F4682/4685 devices; individual unimplemented bits should be interpreted as `--'. 4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as `0'. See Section 2.6.4 "PLL in INTOSC Modes". 5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as `0'. This bit is read-only. 6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. 7: CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all `0's until the ECANTM technology is set up in Mode 1 or Mode 2. 9: These registers and/or bits are available on PIC18F4682/4685 devices only. DS39761B-page 86 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 5.3.5 STATUS REGISTER The STATUS register, shown in Register 5-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the status is updated according to the instruction performed. Therefore, the result of an instruction with the STATUS register as its destination may be different than intended. As an example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (`000u u1uu'). REGISTER 5-2: It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C, DC, OV or N bits in the STATUS register. For other instructions that do not affect Status bits, see the instruction set summaries in Table 25-2 and Table 25-3. Note: The C and DC bits operate as the borrow and digit borrow bits respectively in subtraction. STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x -- -- -- N OV Z DC(1) C(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as `0' bit 4 N: Negative bit This bit is used for signed arithmetic (2's complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2's complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7 of the result) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit(1) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(2) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: 2: For Borrow, the polarity is reversed. A subtraction is executed by adding the 2's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. For Borrow, the polarity is reversed. A subtraction is executed by adding the 2's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 87 PIC18F2682/2685/4682/4685 5.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 5.6 "Data Memory and the Extended Instruction Set" for more information. While the program memory can be addressed in only one way - through the program counter - information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed. Other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled. The addressing modes are: * * * * Inherent Literal Direct Indirect An additional addressing mode, Indexed Literal Offset, is available when the extended instruction set is enabled (XINST Configuration bit = 1). Its operation is discussed in greater detail in Section 5.6.1 "Indexed Addressing with Literal Offset". 5.4.1 INHERENT AND LITERAL ADDRESSING Many PIC18 control instructions do not need any argument at all. They either perform an operation that globally affects the device or they operate implicitly on one register. This addressing mode is known as Inherent Addressing. Examples include SLEEP, RESET and DAW. Other instructions work in a similar way but require an additional explicit argument in the opcode. This is known as Literal Addressing mode because they require some literal value as an argument. Examples include ADDLW and MOVLW which, respectively, add or move a literal value to the W register. Other examples include CALL and GOTO, which include a 20-bit program memory address. 5.4.2 Purpose Register File") or a location in the Access Bank (Section 5.3.2 "Access Bank") as the data source for the instruction. The Access RAM bit `a' determines how the address is interpreted. When `a' is `1', the contents of the BSR (Section 5.3.1 "Bank Select Register (BSR)") are used with the address to determine the complete 12-bit address of the register. When `a' is `0', the address is interpreted as being a register in the Access Bank. Addressing that uses the Access RAM is sometimes also known as Direct Forced Addressing mode. A few instructions, such as MOVFF, include the entire 12-bit address (either source or destination) in their opcodes. In those cases, the BSR is ignored entirely. The destination of the operation's results is determined by the destination bit `d'. When `d' is `1', the results are stored back in the source register, overwriting its original contents. When `d' is `0', the results are stored in the W register. Instructions without the `d' argument have a destination that is implicit in the instruction. Their destination is either the target register being operated on or the W register. 5.4.3 Indirect Addressing allows the user to access a location in data memory without giving a fixed address in the instruction. This is done by using File Select Registers (FSRs) as pointers to the locations to be read or written to. Since the FSRs are themselves located in RAM as Special Function Registers, they can also be directly manipulated under program control. This makes FSRs very useful in implementing data structures, such as tables and arrays in data memory. The registers for Indirect Addressing are also implemented with Indirect File Operands (INDFs) that permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. This allows for efficient code, using loops, such as the example of clearing an entire RAM bank in Example 5-5. EXAMPLE 5-5: DIRECT ADDRESSING Direct Addressing mode specifies all or part of the source and/or destination address of the operation within the opcode itself. The options are specified by the arguments accompanying the instruction. In the core PIC18 instruction set, bit-oriented and byteoriented instructions use some version of Direct Addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section 5.3.3 "General DS39761B-page 88 INDIRECT ADDRESSING NEXT LFSR CLRF HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING FSR0, 100h POSTINC0 BTFSS FSR0H, 1 BRA CONTINUE Preliminary NEXT ; ; ; ; ; ; ; ; Clear INDF register then inc pointer All done with Bank1? NO, clear next YES, continue (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 5.4.3.1 FSR Registers and the INDF Operand mapped in the SFR space, but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction's target. The INDF operand is just a convenient way of using the pointer. At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers: FSRnH and FSRnL. The four upper bits of the FSRnH register are not used, so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations. Because Indirect Addressing uses a full 12-bit address, data RAM banking is not necessary. Thus, the current contents of the BSR and Access RAM bit have no effect on determining the target address. Indirect Addressing is accomplished with a set of Indirect File Operands: INDF0 through INDF2. These can be thought of as "virtual" registers: they are FIGURE 5-7: INDIRECT ADDRESSING 000h Using an instruction with one of the Indirect Addressing registers as the operand.... Bank 0 ADDWF, INDF1, 1 100h Bank 1 200h Bank 2 ...uses the 12-bit address stored in the FSR pair associated with that register.... 300h FSR1H:FSR1L 7 0 x x x x 1 1 1 0 7 0 1 1 0 0 1 1 0 0 Bank 3 through Bank 13 ...to determine the data memory location to be used in that operation. E00h In this case, the FSR1 pair contains ECCh. This means the contents of location ECCh will be added to that of the W register and stored back in ECCh. Bank 14 F00h FFFh Bank 15 Data Memory (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 89 PIC18F2682/2685/4682/4685 5.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are "virtual" registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value. They are: * POSTDEC: accesses the FSR value, then automatically decrements it by 1 afterwards * POSTINC: accesses the FSR value, then automatically increments it by 1 afterwards * PREINC: increments the FSR value by 1, then uses it in the operation * PLUSW: adds the signed value of the W register (range of -127 to 128) to that of the FSR and uses the new value in the operation. In this context, accessing an INDF register uses the value in the FSR registers without changing them. Similarly, accessing a PLUSW register gives the FSR value offset by that in the W register; neither value is actually changed in the operation. Accessing the other virtual registers changes the value of the FSR registers. Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair; that is, rollovers of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). 5.4.3.3 Operations by FSRs on FSRs Indirect Addressing operations that target other FSRs or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers will not result in successful operations. As a specific case, assume that the FSR0H:FSR0L pair contains FE7h, the address of INDF1. Attempts to read the value of the INDF1 using INDF0 as an operand will return 00h. Attempts to write to INDF1 using INDF0 as the operand will result in a NOP. On the other hand, using the virtual registers to write to an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any incrementing or decrementing. Thus, writing to INDF2 or POSTDEC2 will write the same value to the FSR2H:FSR2L pair. Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct operations. Users should proceed cautiously when working on these registers, particularly if their code uses Indirect Addressing. Similarly, operations by Indirect Addressing are generally permitted on all other SFRs. Users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device. The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. DS39761B-page 90 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 5.5 Program Memory and the Extended Instruction Set When using the extended instruction set, this addressing mode requires the following: The operation of program memory is unaffected by the use of the extended instruction set. Enabling the extended instruction set adds eight additional two-word commands to the existing PIC18 instruction set: ADDFSR, ADDULNK, CALLW, MOVSF, MOVSS, PUSHL, SUBFSR and SUBULNK. These instructions are executed as described in Section 5.2.4 "Two-Word Instructions". 5.6 Data Memory and the Extended Instruction Set Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core PIC18 instructions is different. This is due to the introduction of a new addressing mode for the data memory space. This mode also alters the behavior of Indirect Addressing using FSR2 and its associated operands. What does not change is just as important. The size of the data memory space is unchanged, as well as its linear addressing. The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect Addressing with FSR0 and FSR1 also remains unchanged. 5.6.1 INDEXED ADDRESSING WITH LITERAL OFFSET Enabling the PIC18 extended instruction set changes the behavior of Indirect Addressing using the FSR2 register pair and its associated file operands. Under the proper conditions, instructions that use the Access Bank - that is, most bit-oriented and byte-oriented - instructions - can invoke a form of Indexed Addressing using an offset specified in the instruction. This special addressing mode is known as Indexed Addressing with Literal Offset or Indexed Literal Offset mode. (c) 2007 Microchip Technology Inc. * The use of the Access Bank is forced (`a' = 0); and * The file address argument is less than or equal to 5Fh. Under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used with the BSR in Direct Addressing), or as an 8-bit address in the Access Bank. Instead, the value is interpreted as an offset value to an Address Pointer, specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation. 5.6.2 INSTRUCTIONS AFFECTED BY INDEXED LITERAL OFFSET MODE Any of the core PIC18 instructions that can use Direct Addressing are potentially affected by the Indexed Literal Offset Addressing mode. This includes all byteoriented and bit-oriented instructions, or almost one-half of the standard PIC18 instruction set. Instructions that only use Inherent or Literal Addressing modes are unaffected. Additionally, byte-oriented and bit-oriented instructions are not affected if they use the Access Bank (Access RAM bit is `1'), or include a file address of 60h or above. Instructions meeting these criteria will continue to execute as before. A comparison of the different possible addressing modes when the extended instruction set is enabled in shown in Figure 5-8. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 25.2.1 "Extended Instruction Syntax". Preliminary DS39761B-page 91 PIC18F2682/2685/4682/4685 FIGURE 5-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When a = 0 and f 60h: The instruction executes in Direct Forced mode. `f' is interpreted as a location in the Access RAM between 060h and 0FFh. This is the same as the SFRs, or locations F60h to 0FFh (Bank 15) of data memory. 000h Locations below 60h are not available in this addressing mode. F00h 060h 080h Bank 0 100h 00h Bank 1 through Bank 14 60h Valid Range for `f' FFh Access RAM Bank 15 F60h SFRs FFFh Data Memory When a = 0 and f 5Fh: The instruction executes in Indexed Literal Offset mode. `f' is interpreted as an offset to the address value in FSR2. The two are added together to obtain the address of the target register for the instruction. The address can be anywhere in the data memory space. Note that in this mode, the correct syntax is now: ADDWF [k], d where `k' is the same as `f'. 000h Bank 0 080h 100h 001001da ffffffff Bank 1 through Bank 14 FSR2H FSR2L F00h Bank 15 F60h SFRs FFFh Data Memory When a = 1 (all values of f): The instruction executes in Direct mode (also known as Direct Long mode). `f' is interpreted as a location in one of the 16 banks of the data memory space. The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. BSR 00000000 000h Bank 0 080h 100h 001001da ffffffff Bank 1 through Bank 14 F00h Bank 15 F60h SFRs FFFh Data Memory DS39761B-page 92 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 5.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower half of Access RAM (00h to 7Fh) is mapped. Rather than containing just the contents of the bottom half of Bank 0, this mode maps the contents from Bank 0 and a user defined "window" that can be located anywhere in the data memory space. The value of FSR2 establishes the lower boundary of the addresses mapped into the window, while the upper boundary is defined by FSR2 plus 95 (5Fh). Addresses in the Access RAM above 5Fh are mapped as previously described (see Section 5.3.2 "Access Bank"). An example of Access Bank remapping in this addressing mode is shown in Figure 5-9. FIGURE 5-9: Remapping of the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is `1') will continue to use Direct Addressing as before. Any indirect or indexed operation that explicitly uses any of the indirect file operands (including FSR2) will continue to operate as standard Indirect Addressing. Any instruction that uses the Access Bank, but includes a register address of greater than 05Fh, will use Direct Addressing and the normal Access Bank map. 5.6.4 BSR IN INDEXED LITERAL OFFSET MODE Although the Access Bank is remapped when the extended instruction set is enabled, the operation of the BSR remains unchanged. Direct Addressing using the BSR to select the data memory bank operates in the same manner as previously described. REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING Example Situation: ADDWF f, d, a 000h FSR2H:FSR2L = 120h Locations in the region from the FSR2 Pointer (120h) to the pointer plus 05Fh (17Fh) are mapped to the bottom of the Access RAM (000h-05Fh). Bank 0 100h 120h 17Fh 200h 00h Bank 1 Bank 1 "Window" 5Fh 60h Special Function Registers at F60h through FFFh are mapped to 60h through FFh, as usual. Bank 0 addresses below 5Fh are not available in this mode. They can still be addressed by using the BSR. Window Bank 2 through Bank 14 SFRs FFh Access Bank F00h Bank 15 F60h SFRs FFFh Data Memory (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 93 PIC18F2682/2685/4682/4685 NOTES: DS39761B-page 94 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 6.0 FLASH PROGRAM MEMORY 6.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 64 bytes at a time. Program memory is erased in blocks of 64 bytes at a time. A Bulk Erase operation may not be issued from user code. * Table Read (TBLRD) * Table Write (TBLWT) Writing or erasing program memory will cease instruction fetches until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases. A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP. The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT). Table read operations retrieve data from program memory and place it into the data RAM space. Figure 6-1 shows the operation of a table read with program memory and data RAM. Table write operations store data from the data memory space into holding registers in program memory. The procedure to write the contents of the holding registers into program memory is detailed in Section 6.5 "Writing to Flash Program Memory". Figure 6-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word-aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word-aligned. FIGURE 6-1: TABLE READ OPERATION Instruction: TBLRD* Program Memory Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 95 PIC18F2682/2685/4682/4685 FIGURE 6-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 "Writing to Flash Program Memory". 6.2 Control Registers Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include the: * * * * EECON1 register EECON2 register TABLAT register TBLPTR registers 6.2.1 The FREE bit, when set, will allow a program memory erase operation. When FREE is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set in hardware when the WREN bit is set, and cleared when the internal programming timer expires and the write operation is complete. EECON1 AND EECON2 REGISTERS Note: The EECON1 register (Register 6-1) is the control register for memory accesses. The EECON2 register is not a physical register; it is used exclusively in the memory write and erase sequences. Reading EECON2 will read all `0's. The EEPGD control bit determines if the access will be a program or data EEPROM memory access. When clear, any subsequent operations will operate on the data EEPROM memory. When set, any subsequent operations will operate on the program memory. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software; it is cleared in hardware at the completion of the write operation. Note: The CFGS control bit determines if the access will be to the Configuration/Calibration registers or to program memory/data EEPROM memory. When set, subsequent operations will operate on Configuration registers regardless of EEPGD (see Section 24.0 "Special Features of the CPU"). When clear, memory selection access is determined by EEPGD. DS39761B-page 96 During normal operation, the WRERR is read as `1'. This can indicate that a write operation was prematurely terminated by a Reset or a write operation was attempted improperly. Preliminary The EEIF Interrupt flag bit (PIR2<4>) is set when the write is complete. It must be cleared in software. (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 6-1: R/W-x EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x EEPGD CFGS U-0 -- R/W-0 FREE R/W-x (1) WRERR R/W-0 R/S-0 R/S-0 WREN WR RD bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as `0' bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 97 PIC18F2682/2685/4682/4685 6.2.2 TABLAT - TABLE LATCH REGISTER 6.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT. TBLPTR - TABLE POINTER REGISTER When a TBLWT is executed, the six LSbs of the Table Pointer register (TBLPTR<5:0>) determine which of the 64 program memory holding registers is written to. When the timed write to program memory begins (via the WR bit), the 16 MSbs of the TBLPTR (TBLPTR<21:6>) determine which program memory block of 64 bytes is written to. For more detail, see Section 6.5 "Writing to Flash Program Memory". The Table Pointer (TBLPTR) register addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order 21 bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to the Device ID, the user ID and the Configuration bits. When an erase of program memory is executed, the 16 MSbs of the Table Pointer register (TBLPTR<21:6>) point to the 64-byte block that will be erased. The Least Significant bits (TBLPTR<5:0>) are ignored. The Table Pointer, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table operation. These operations are shown in Table 6-1. These operations on the TBLPTR only affect the low-order 21 bits. TABLE 6-1: TABLE POINTER BOUNDARIES Figure 6-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations. TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLWT* TBLPTR is not modified TBLRD*+ TBLWT*+ TBLPTR is incremented after the read/write TBLRD*TBLWT*- TBLPTR is decremented after the read/write TBLRD+* TBLWT+* TBLPTR is incremented before the read/write FIGURE 6-3: 21 TABLE POINTER BOUNDARIES BASED ON OPERATION TBLPTRU 16 15 TBLPTRH 8 Table Erase/Write TBLPTR<21:6> 7 TBLPTRL 0 Table Write TBLPTR<5:0> Table Read - TBLPTR<21:0> DS39761B-page 98 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 6.3 Reading the Flash Program Memory The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT. The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 Instruction Register (IR) EXAMPLE 6-1: TBLRD FETCH TBLPTR = xxxxx0 TABLAT Read Register READING A FLASH PROGRAM MEMORY WORD MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the word READ_WORD TBLRD*+ MOVF MOVWF TBLRD*+ MOVF MOVF TABLAT, W WORD_EVEN TABLAT, W WORD_ODD (c) 2007 Microchip Technology Inc. ; read into TABLAT and increment ; get data ; read into TABLAT and increment ; get data Preliminary DS39761B-page 99 PIC18F2682/2685/4682/4685 6.4 6.4.1 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be Bulk Erased. Word Erase in the Flash array is not supported. The sequence of events for erasing a block of internal program memory location is: 1. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased. TBLPTR<5:0> are ignored. 2. The EECON1 register commands the erase operation. The EEPGD bit must be set to point to the Flash program memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation. 3. 4. 5. 6. For protection, the write initiate sequence for EECON2 must be used. 7. A long write is necessary for erasing the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. EXAMPLE 6-2: FLASH PROGRAM MEMORY ERASE SEQUENCE 8. Load Table Pointer register with address of row being erased. Set the EECON1 register for the erase operation: * set EEPGD bit to point to program memory; * clear the CFGS bit to access program memory; * set WREN bit to enable writes; * set FREE bit to enable the erase. Disable interrupts. Write 55h to EECON2. Write 0AAh to EECON2. Set the WR bit. This will begin the Row Erase cycle. The CPU will stall for duration of the erase (about 2 ms using internal timer). Re-enable interrupts. ERASING A FLASH PROGRAM MEMORY ROW MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; load TBLPTR with the base ; address of the memory block BSF BCF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF EECON1, EECON1, EECON1, EECON1, INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, ; ; ; ; ; ERASE_ROW Required Sequence DS39761B-page 100 EEPGD CFGS WREN FREE GIE point to Flash program memory access Flash program memory enable write to memory enable Row Erase operation disable interrupts ; write 55h WR GIE ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 6.5 Writing to Flash Program Memory The minimum programming block is 32 words or 64 bytes. Word or byte programming is not supported. The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 64 holding registers used by the table writes for programming. The EEPROM on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction may need to be executed 64 times for each programming operation. All of the table write operations will essentially be short writes because only the holding registers are written. At the end of updating the 64 holding registers, the EECON1 register must be written to in order to start the programming operation with a long write. FIGURE 6-5: Note: The default value of the holding registers on device Resets and after write operations is FFh. A write of FFh to a holding register does not modify that byte. This means that individual bytes of program memory may be modified, provided that the change does not attempt to change any bit from a `0' to a `1'. When modifying individual bytes, it is not necessary to load all 64 holding registers before executing a write operation. TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 TBLPTR = xxxxx0 8 TBLPTR = xxxxx1 Holding Register TBLPTR = xxxxx2 Holding Register 8 TBLPTR = xxxx3F Holding Register Holding Register Program Memory 6.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE The sequence of events for programming an internal program memory location should be: 1. 2. 3. 4. 5. 6. 7. Read 64 bytes into RAM. Update data values in RAM as necessary. Load Table Pointer register with address being erased. Execute the Row Erase procedure. Load Table Pointer register with address of first byte being written. Write the 64 bytes into the holding registers with auto-increment. Set the EECON1 register for the write operation: * set EEPGD bit to point to program memory; * clear the CFGS bit to access program memory; * set WREN to enable byte writes. (c) 2007 Microchip Technology Inc. 8. 9. 10. 11. 12. Disable interrupts. Write 55h to EECON2. Write 0AAh to EECON2. Set the WR bit. This will begin the write cycle. The CPU will stall for duration of the write (about 2 ms using internal timer). 13. Re-enable interrupts. 14. Verify the memory (table read). This procedure will require about 18 ms to update one row of 64 bytes of memory. An example of the required code is given in Example 6-3. Note: Preliminary Before setting the WR bit, the Table Pointer address needs to be within the intended address range of the 64 bytes in the holding register. DS39761B-page 101 PIC18F2682/2685/4682/4685 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'64 COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL TBLRD*+ MOVF MOVWF DECFSZ BRA TABLAT, W POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; number of bytes in erase block ; point to buffer ; Load TBLPTR with the base ; address of the memory block READ_BLOCK ; ; ; ; ; read into TABLAT, and inc get data store data done? repeat MODIFY_WORD ; point to buffer ; update buffer word ERASE_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BSF BCF BSF BSF BCF MOVLW Required MOVWF Sequence MOVLW MOVWF BSF BSF TBLRD*MOVLW MOVWF MOVLW MOVWF WRITE_BUFFER_BACK MOVLW MOVWF WRITE_BYTE_TO_HREGS MOVF MOVWF TBLWT+* CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL EECON1, EEPGD EECON1, CFGS EECON1, WREN EECON1, FREE INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR INTCON, GIE ; load TBLPTR with the base ; address of the memory block ; ; ; ; ; ; write 55h ; ; ; ; ; BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L write 0AAh start erase (CPU stall) re-enable interrupts dummy read decrement point to buffer D'64 COUNTER ; number of bytes in holding register POSTINC0, W TABLAT ; ; ; ; ; DECFSZ COUNTER BRA WRITE_BYTE_TO_HREGS DS39761B-page 102 point to Flash program memory access Flash program memory enable write to memory enable Row Erase operation disable interrupts get low byte of buffer data present data to table latch write data, perform a short write to internal TBLWT holding register. loop until buffers are full Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BSF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF Required Sequence 6.5.2 EECON1, EECON1, EECON1, INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, EECON1, EEPGD CFGS WREN GIE ; ; ; ; ; write 55h ; ; ; ; WR GIE WREN UNEXPECTED TERMINATION OF WRITE OPERATION If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed should be verified and reprogrammed if needed. If the write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal operation, the user can check the WRERR bit and rewrite the location(s) as needed. TABLE 6-2: write 0AAh start program (CPU stall) re-enable interrupts disable write to memory 6.5.4 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 6.5.3 point to Flash program memory access Flash program memory enable write to memory disable interrupts PROTECTION AGAINST SPURIOUS WRITES To protect against spurious writes to Flash program memory, the write initiate sequence must also be followed. See Section 24.0 "Special Features of the CPU" for more detail. 6.6 Flash Program Operation During Code Protection See Section 24.5 "Program Verification and Code Protection" for details on code protection of Flash program memory. REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Name Bit 7 Bit 6 Bit 5 TBLPTRU -- -- bit 21 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 49 TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 49 TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>) 49 TABLAT Program Memory Table Latch 49 INTCON GIE/GIEH PEIE/GIEL TMR0IE EECON2 EEPROM Control Register 2 (not a physical register) INT0IE RBIE TMR0IF INT0IF RBIF 49 51 EECON1 EEPGD CFGS -- FREE WRERR WREN WR RD 51 IPR2 OSCFIP CMIP(1) -- EEIP BCLIP HLVDIP TMR3IP ECCP1IP(1) 51 PIR2 OSCFIF CMIF(1) -- EEIF BCLIF HLVDIF TMR3IF ECCP1IF(1) 52 OSCFIE CMIE(1) -- EEIE BCLIE HLVDIE TMR3IE ECCP1IE(1) 52 PIE2 Legend: -- = unimplemented, read as `0'. Shaded cells are not used during Flash/EEPROM access. Note 1: These bits are available in PIC18F4682/4685 devices and reserved in PIC18F2682/2685 devices. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 103 PIC18F2682/2685/4682/4685 NOTES: DS39761B-page 104 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 7.0 DATA EEPROM MEMORY The data EEPROM is a nonvolatile memory array, separate from the data RAM and program memory, that is used for long-term storage of program data. It is not directly mapped in either the register file or program memory space but is indirectly addressed through the Special Function Registers (SFRs). The EEPROM is readable and writable during normal operation over the entire VDD range. Five SFRs are used to read and write to the data EEPROM as well as the program memory. They are: * * * * * EECON1 EECON2 EEDATA EEADR EEADRH The EEPROM data memory is rated for high erase/write cycle endurance. A byte write automatically erases the location and writes the new data (erase-before-write). The write time is controlled by an on-chip timer; it will vary with voltage and temperature, as well as from chip to chip. Please refer to parameter D122 (Table 27-1 in Section 27.0 "Electrical Characteristics") for exact limits. EEADR and EEADRH Registers The EEADRH:EEADR register pair is used to address the data EEPROM for read and write operations. EEADRH holds the two Most Significant bits of the address; the upper 6 bits are ignored. The 10-bit range of the pair can address a memory range of 1024 bytes (00h to 3FFh). 7.2 Control bit CFGS determines if the access will be to the Configuration registers or to program memory/data EEPROM memory. When set, subsequent operations access Configuration registers. When CFGS is clear, the EEPGD bit selects either program Flash or data EEPROM memory. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set in hardware when the WREN bit is set and cleared when the internal programming timer expires and the write operation is complete. The data EEPROM allows byte read and write. When interfacing to the data memory block, EEDATA holds the 8-bit data for read/write and the EEADRH:EEADR register pair holds the address of the EEPROM location being accessed. 7.1 The EECON1 register (Register 7-1) is the control register for data and program memory access. Control bit EEPGD determines if the access will be to program or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed. EECON1 and EECON2 Registers Note: During normal operation, the WRERR is read as `1'. This can indicate that a write operation was prematurely terminated by a Reset, or a write operation was attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software; it is cleared in hardware at the completion of the write operation. Note: The EEIF interrupt flag bit (PIR2<4>) is set when the write is complete. It must be cleared in software. Control bits, RD and WR, start read and erase/write operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section 6.1 "Table Reads and Table Writes" regarding table reads. The EECON2 register is not a physical register. It is used exclusively in the memory write and erase sequences. Reading EECON2 will read all `0's. Access to the data EEPROM is controlled by two registers: EECON1 and EECON2. These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 105 PIC18F2682/2685/4682/4685 REGISTER 7-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS -- FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as `0' bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS39761B-page 106 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 7.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADRH:EEADR register pair, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD (EECON1<0>). The data is available on the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation). The basic process is shown in Example 7-1. 7.4 Writing to the Data EEPROM Memory To write an EEPROM data location, the address must first be written to the EEADRH:EEADR register pair and the data written to the EEDATA register. The sequence in Example 7-2 must be followed to initiate the write cycle. The write will not begin if this sequence is not exactly followed (write 55h to EECON2, write 0AAh to EECON2, then set WR bit) for each byte. It is strongly recommended that interrupts be disabled during this code segment. EXAMPLE 7-1: MOVLW MOVWF MOVLW MOVWF BCF BCF BSF MOVF After a write sequence has been initiated, EECON1, EEADRH:EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruction. Both WR and WREN cannot be set with the same instruction. At the completion of the write cycle, the WR bit is cleared in hardware and the EEPROM Interrupt Flag bit (EEIF) is set. The user may either enable this interrupt, or poll this bit. EEIF must be cleared by software. 7.5 Write Verify Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. DATA EEPROM READ DATA_EE_ADDRH EEADRH DATA_EE_ADDR EEADR EECON1, EEPGD EECON1, CFGS EECON1, RD EEDATA, W EXAMPLE 7-2: Required Sequence Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware. ; ; ; ; ; ; ; ; Upper bits of Data Memory Address to read Lower bits of Data Memory Address to read Point to DATA memory Access EEPROM EEPROM Read W = EEDATA DATA EEPROM WRITE MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BCF BCF BSF DATA_EE_ADDRH EEADRH DATA_EE_ADDR EEADR DATA_EE_DATA EEDATA EECON1, EPGD EECON1, CFGS EECON1, WREN ; ; ; ; ; ; ; ; ; BCF MOVLW MOVWF MOVLW MOVWF BSF BSF INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR INTCON, GIE ; ; ; ; ; ; ; BCF EECON1, WREN ; User code execution ; Disable writes on write complete (EEIF set) (c) 2007 Microchip Technology Inc. Upper bits of Data Memory Address to write Lower bits of Data Memory Address to write Data Memory Value to write Point to DATA memory Access EEPROM Enable writes Disable Interrupts Write 55h Write 0AAh Set WR bit to begin write Enable Interrupts Preliminary DS39761B-page 107 PIC18F2682/2685/4682/4685 7.6 Operation During Code-Protect 7.8 Data EEPROM memory has its own code-protect bits in Configuration Words. External read and write operations are disabled if code protection is enabled. The microcontroller itself can both read and write to the internal Data EEPROM, regardless of the state of the code-protect Configuration bit. Refer to Section 24.0 "Special Features of the CPU" for additional information. 7.7 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been implemented. On power-up, the WREN bit is cleared. In addition, writes to the EEPROM are blocked during the Power-up Timer period (TPWRT, parameter 33). Using the Data EEPROM The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). Frequently changing values will typically be updated more often than specification D124. If this is not the case, an array refresh must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory. A simple data EEPROM refresh routine is shown in Example 7-3. Note: If data EEPROM is only used to store constants and/or data that changes rarely, an array refresh is likely not required. See specification D124. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch or software malfunction. EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE CLRF CLRF BCF BCF BCF BSF EEADR EEADRH EECON1, EECON1, INTCON, EECON1, BSF MOVLW MOVWF MOVLW MOVWF BSF BTFSC BRA INCFSZ BRA INCFSZ BRA EECON1, RD 55h EECON2 0AAh EECON2 EECON1, WR EECON1, WR $-2 EEADR, F LOOP EEADRH, F LOOP BCF BSF EECON1, WREN INTCON, GIE CFGS EEPGD GIE WREN Loop DS39761B-page 108 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Start at address 0 Set for memory Set for Data EEPROM Disable interrupts Enable writes Loop to refresh array Read current address Write 55h Write 0AAh Set WR bit to begin write Wait for write to complete Increment Not zero, Increment Not zero, address do it again the high address do it again ; Disable writes ; Enable interrupts Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 7-1: Name INTCON EEADRH REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Bit 7 Bit 6 GIE/GIEH PEIE/GIEL -- -- Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INT0IE RBIE TMR0IF -- -- -- -- Bit 1 Bit 0 INT0IF RBIF Reset Values on page EEPROM Address Register High Byte 49 51 EEADR EEPROM Address Register Low Byte 51 EEDATA EEPROM Data Register 51 EECON2 EEPROM Control Register 2 (not a physical register) 51 EECON1 EEPGD CFGS -- FREE WRERR WREN WR RD 51 IPR2 OSCFIP CMIP(1) -- EEIP BCLIP HLVDIP TMR3IP ECCP1IP(1) 51 OSCFIF CMIF(1) -- EEIF BCLIF HLVDIF TMR3IF ECCP1IF(1) 52 OSCFIE CMIE(1) TMR3IE ECCP1IE(1) 52 PIR2 PIE2 -- EEIE BCLIE HLVDIE Legend: -- = unimplemented, read as `0'. Shaded cells are not used during Flash/EEPROM access. Note 1: These bits are available in PIC18F4682/4685 devices and reserved in PIC18F2682/2685 devices. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 109 PIC18F2682/2685/4682/4685 NOTES: DS39761B-page 110 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 8.0 8 x 8 HARDWARE MULTIPLIER 8.1 Introduction EXAMPLE 8-1: MOVF MULWF All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier's operation does not affect any flags in the STATUS register. ARG1, W ARG2 ; ; ARG1 * ARG2 -> ; PRODH:PRODL EXAMPLE 8-2: Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the advantages of higher computational throughput and reduced code size for multiplication algorithms and allows the PIC18 devices to be used in many applications previously reserved for digital signal processors. A comparison of various hardware and software multiply operations, along with the savings in memory and execution time, is shown in Table 8-1. 8.2 8 x 8 UNSIGNED MULTIPLY ROUTINE 8 x 8 SIGNED MULTIPLY ROUTINE MOVF MULWF ARG1, W ARG2 BTFSC SUBWF ARG2, SB PRODH, F MOVF BTFSC SUBWF ARG2, W ARG1, SB PRODH, F ; ; ; ; ; ARG1 * ARG2 -> PRODH:PRODL Test Sign Bit PRODH = PRODH - ARG1 ; Test Sign Bit ; PRODH = PRODH ; - ARG2 Operation Example 8-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example 8-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the signed bits of the arguments, each argument's Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 8-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Routine 8 x 8 unsigned 8 x 8 signed 16 x 16 unsigned 16 x 16 signed Multiply Method Without hardware multiply Program Memory (Words) Cycles (Max) @ 40 MHz @ 10 MHz @ 4 MHz 13 69 6.9 s 27.6 s 69 s Time Hardware multiply 1 1 100 ns 400 ns 1 s Without hardware multiply 33 91 9.1 s 36.4 s 91 s Hardware multiply 6 6 600 ns 2.4 s 6 s Without hardware multiply 21 242 24.2 s 96.8 s 242 s Hardware multiply 28 28 2.8 s 11.2 s 28 s Without hardware multiply 52 254 25.4 s 102.6 s 254 s Hardware multiply 35 40 4.0 s 16.0 s 40 s (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 111 PIC18F2682/2685/4682/4685 Example 8-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 8-1: RES3:RES0 = = EXAMPLE 8-3: 16 x 16 UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L * ARG2H:ARG2L (ARG1H * ARG2H * 216) + (ARG1H * ARG2L * 28) + (ARG1L * ARG2H * 28) + (ARG1L * ARG2L) EQUATION 8-2: RES3:RES0= ARG1H:ARG1L * ARG2H:ARG2L = (ARG1H * ARG2H * 216) + (ARG1H * ARG2L * 28) + (ARG1L * ARG2H * 28) + (ARG1L * ARG2L) + (-1 * ARG2H<7> * ARG1H:ARG1L * 216) + (-1 * ARG1H<7> * ARG2H:ARG2L * 216) EXAMPLE 8-4: 16 x 16 UNSIGNED MULTIPLY ROUTINE MOVF MULWF ARG1L, W ARG2L MOVFF MOVFF PRODH, RES1 PRODL, RES0 MOVF MULWF ARG1H, W ARG2H MOVFF MOVFF PRODH, RES3 PRODL, RES2 MOVF MULWF ARG1L, W ARG2H MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F MOVF MULWF ARG1H, W ARG2L MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ; ARG1L * ARG2L-> ; PRODH:PRODL ; ; ARG1L * ARG2H-> PRODH:PRODL Add cross products ARG1H * ARG2L-> PRODH:PRODL Add cross products MOVFF MOVFF PRODH, RES1 PRODL, RES0 MOVF MULWF ARG1H, W ARG2H MOVFF MOVFF PRODH, RES3 PRODL, RES2 MOVF MULWF ARG1L,W ARG2H MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F MOVF MULWF ARG1H, W ARG2L MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F BTFSS BRA MOVF SUBWF MOVF SUBWFB ARG2H, 7 SIGN_ARG1 ARG1L, W RES2 ARG1H, W RES3 ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ARG1H, 7 CONT_CODE ARG2L, W RES2 ARG2H, W RES3 ; ARG1H:ARG1L neg? ; no, done ; ; ; ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; ; ; ; ; ; ; ; ; ARG1L * ARG2H -> PRODH:PRODL Add cross products ; ; ; ; ; ; ; ; ; ARG1H * ARG2L -> PRODH:PRODL Add cross products ; Example 8-4 shows the sequence to do a 16 x 16 signed multiply. Equation 8-2 shows the algorithm used. The 32-bit result is stored in four registers (RES3:RES0). To account for the signed bits of the arguments, the MSb for each argument pair is tested and the appropriate subtractions are done. DS39761B-page 112 ARG1L, W ARG2L ; ; ; ; ; ; ; ; ; ; ; MOVF MULWF ; ; ; ; ; ; ; ; ; ; 16 x 16 SIGNED MULTIPLY ROUTINE ; ; ; ARG1H * ARG2H-> ; PRODH:PRODL ; ; 16 x 16 SIGNED MULTIPLICATION ALGORITHM ; SIGN_ARG1 BTFSS BRA MOVF SUBWF MOVF SUBWFB ; CONT_CODE : Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 9.0 INTERRUPTS The PIC18F2682/2685/4682/4685 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. High priority interrupt events will interrupt any low priority interrupts that may be in progress. There are ten registers which are used to control interrupt operation. These registers are: * * * * * * * RCON INTCON INTCON2 INTCON3 PIR1, PIR2, PIR3 PIE1, PIE2, PIE3 IPR1, IPR2, IPR3 It is recommended that the Microchip header files supplied with MPLAB(R) IDE be used for the symbolic bit names in these registers. This allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. Each interrupt source has three bits to control its operation. The functions of these bits are: When an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. High priority interrupt sources can interrupt a low priority interrupt. Low priority interrupts are not processed while high priority interrupts are in progress. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (000008h or 000018h). Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. The "return from interrupt" instruction, RETFIE, exits the interrupt routine and sets the GIE bit (GIEH or GIEL if priority levels are used), which re-enables interrupts. For external interrupt events, such as the INT pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bit or the GIE bit. * Flag bit to indicate that an interrupt event occurred * Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set * Priority bit to select high priority or low priority The interrupt priority feature is enabled by setting the IPEN bit (RCON<7>). When interrupt priority is enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits. (c) 2007 Microchip Technology Inc. When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PIC(R) mid-range devices. In Compatibility mode, the interrupt priority bits for each source have no effect. INTCON<6> is the PEIE bit, which enables/disables all peripheral interrupt sources. INTCON<7> is the GIE bit, which enables/disables all interrupt sources. All interrupts branch to address 000008h in Compatibility mode. Note: Preliminary Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior. DS39761B-page 113 PIC18F2682/2685/4682/4685 FIGURE 9-1: INTERRUPT LOGIC TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP Wake-up if in Sleep Mode INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit Interrupt to CPU Vector to Location 0008h GIE/GIEH TMR1IF TMR1IE TMR1IP IPEN XXXXIF XXXXIE XXXXIP IPEN PEIE/GIEL IPEN Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit Interrupt to CPU Vector to Location 0018h TMR0IF TMR0IE TMR0IP TMR1IF TMR1IE TMR1IP RBIF RBIE RBIP XXXXIF XXXXIE XXXXIP Additional Peripheral Interrupts PEIE/GIEL GIE/GEIH INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP DS39761B-page 114 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 9.1 INTCON Registers Note: The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits. REGISTER 9-1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high priority interrupts 0 = Disables all high priority interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low priority peripheral interrupts 0 = Disables all low priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit(1) 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 115 PIC18F2682/2685/4682/4685 REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 -- TMR0IP -- RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 Unimplemented: Read as `0' bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 Unimplemented: Read as `0' bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Note: x = Bit is unknown Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39761B-page 116 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 9-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP -- INT2IE INT1IE -- INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as `0' bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 Unimplemented: Read as `0' bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Note: x = Bit is unknown Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 117 PIC18F2682/2685/4682/4685 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Request (Flag) registers (PIR1, PIR2). REGISTER 9-4: Note 1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit, GIE (INTCON<7>). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1) 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RCIF: EUSART Receive Interrupt Flag bit 1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The EUSART receive buffer is empty bit 4 TXIF: EUSART Transmit Interrupt Flag bit 1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The EUSART transmit buffer is full bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note 1: This bit is reserved on PIC18F2682/2685 devices; always maintain this bit clear. DS39761B-page 118 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF CMIF(1) -- EEIF BCLIF HLVDIF TMR3IF ECCP1IF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = Device clock operating bit 6 CMIF: Comparator Interrupt Flag bit(1) 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed bit 5 Unimplemented: Read as `0' bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared in software) 0 = The write operation is not complete or has not been started bit 3 BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred bit 2 HLVDIF: High/Low-Voltage Detect Interrupt Flag bit 1 = A high/low-voltage condition occurred (must be cleared in software) 0 = The device voltage is above the High/Low-Voltage Detect trip point bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow bit 0 ECCP1IF: ECCP1 Interrupt Flag bit(1) Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. Note 1: These bits are available in PIC18F4682/4685 and reserved in PIC18F2682/2685 devices. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 119 PIC18F2682/2685/4682/4685 REGISTER 9-6: Mode 0 Mode 1,2 R/W-0 PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 IRXIF WAKIF ERRIF TXB2IF TXB1IF(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIF WAKIF ERRIF TXBnIF (1) TXB1IF R/W-0 TXB0IF (1) R/W-0 TXB0IF (1) R/W-0 R/W-0 RXB1IF RXB0IF R/W-0 R/W-0 RXBnIF FIFOWMIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 IRXIF: CAN Invalid Received Message Interrupt Flag bit 1 = An invalid message has occurred on the CAN bus 0 = No invalid message on CAN bus bit 6 WAKIF: CAN bus Activity Wake-up Interrupt Flag bit 1 = Activity on CAN bus has occurred 0 = No activity on CAN bus bit 5 ERRIF: CAN bus Error Interrupt Flag bit 1 = An error has occurred in the CAN module (multiple sources) 0 = No CAN module errors bit 4 When CAN is in Mode 0: TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit 1 = Transmit Buffer 2 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 2 has not completed transmission of a message When CAN is in Mode 1 or 2: TXBnIF: Any Transmit Buffer Interrupt Flag bit 1 = One or more transmit buffers have completed transmission of a message and may be reloaded 0 = No transmit buffer is ready for reload bit 3 TXB1IF: CAN Transmit Buffer 1 Interrupt Flag bit(1) 1 = Transmit Buffer 1 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 1 has not completed transmission of a message bit 2 TXB0IF: CAN Transmit Buffer 0 Interrupt Flag bit(1) 1 = Transmit Buffer 0 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 0 has not completed transmission of a message bit 1 When CAN is in Mode 0: RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit 1 = Receive Buffer 1 has received a new message 0 = Receive Buffer 1 has not received a new message When CAN is in Mode 1 or 2: RXBnIF: Any Receive Buffer Interrupt Flag bit 1 = One or more receive buffers has received a new message 0 = No receive buffer has received a new message bit 0 When CAN is in Mode 0: RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit 1 = Receive Buffer 0 has received a new message 0 = Receive Buffer 0 has not received a new message When CAN is in Mode 1: Unimplemented: Read as `0' When CAN is in Mode 2: FIFOWMIF: FIFO Watermark Interrupt Flag bit 1 = FIFO high watermark is reached 0 = FIFO high watermark is not reached Note 1: In CAN Mode 1 and 2, these bits are forced to `0'. DS39761B-page 120 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1, PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 9-7: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1) 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RCIE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt bit 4 TXIE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: x = Bit is unknown This bit is reserved on PIC18F2682/2685 devices; always maintain this bit clear. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 121 PIC18F2682/2685/4682/4685 REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE CMIE(1) -- EEIE BCLIE HLVDIE TMR3IE ECCP1IE(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit(1) 1 = Enabled 0 = Disabled bit 5 Unimplemented: Read as `0' bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 ECCP1IE: ECCP1 Interrupt Enable bit(1) 1 = Enabled 0 = Disabled Note 1: x = Bit is unknown These bits are available on PIC18F4682/4685 devices only. DS39761B-page 122 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 9-9: Mode 0 Mode 1 PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIE WAKIE ERRIE TXB2IE TXB1IE(1) TXB0IE(1) RXB1IE RXB0IE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIE WAKIE ERRIE TXBnIE TXB1IE(1) TXB0IE(1) RXBnIE FIFOWMIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 IRXIE: CAN Invalid Received Message Interrupt Enable bit 1 = Enable invalid message received interrupt 0 = Disable invalid message received interrupt bit 6 WAKIE: CAN bus Activity Wake-up Interrupt Enable bit 1 = Enable bus activity wake-up interrupt 0 = Disable bus activity wake-up interrupt bit 5 ERRIE: CAN bus Error Interrupt Enable bit 1 = Enable CAN bus error interrupt 0 = Disable CAN bus error interrupt bit 4 When CAN is in Mode 0: TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit 1 = Enable Transmit Buffer 2 interrupt 0 = Disable Transmit Buffer 2 interrupt When CAN is in Mode 1 or 2: TXBnIE: CAN Transmit Buffer Interrupts Enable bit 1 = Enable transmit buffer interrupt; individual interrupt is enabled by TXBIE and BIE0 0 = Disable all transmit buffer interrupts bit 3 TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit(1) 1 = Enable Transmit Buffer 1 interrupt 0 = Disable Transmit Buffer 1 interrupt bit 2 TXB0IE: CAN Transmit Buffer 0 Interrupt Enable bit(1) 1 = Enable Transmit Buffer 0 interrupt 0 = Disable Transmit Buffer 0 interrupt bit 1 When CAN is in Mode 0: RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit 1 = Enable Receive Buffer 1 interrupt 0 = Disable Receive Buffer 1 interrupt When CAN is in Mode 1 or 2: RXBnIE: CAN Receive Buffer Interrupts Enable bit 1 = Enable receive buffer interrupt; individual interrupt is enabled by BIE0 0 = Disable all receive buffer interrupts bit 0 When CAN is in Mode 0: RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit 1 = Enable Receive Buffer 0 interrupt 0 = Disable Receive Buffer 0 interrupt When CAN is in Mode 1: Unimplemented: Read as `0' When CAN is in Mode 2: FIFOWMIE: FIFO Watermark Interrupt Enable bit 1 = Enable FIFO watermark interrupt 0 = Disable FIFO watermark interrupt Note 1: In CAN Mode 1 and 2, these bits are forced to `0'. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 123 PIC18F2682/2685/4682/4685 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1, IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 9-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RCIP: EUSART Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TXIP: EUSART Transmit Interrupt Priority bit x = Bit is unknown 1 = High priority 0 = Low priority bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: This bit is reserved on PIC18F2682/2685 devices; always maintain this bit clear. DS39761B-page 124 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 9-11: R/W-1 IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 (1) OSCFIP CMIP U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- EEIP BCLIP HLVDIP TMR3IP ECCP1IP(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as `0' bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 HLVDIP: High/Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 ECCP1IP: ECCP1 Interrupt Priority bit(1) 1 = High priority 0 = Low priority Note 1: x = Bit is unknown These bits are available on PIC18F4682/4685 devices only. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 125 PIC18F2682/2685/4682/4685 REGISTER 9-12: Mode 0 Mode 1,2 R/W-1 IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 R/W-1 IRXIP WAKIP ERRIP TXB2IP R/W-1 R/W-1 R/W-1 R/W-1 IRXIP WAKIP ERRIP R/W-1 (1) (1) TXB1IP TXB0IP R/W-1 R/W-1 (1) TXBnIP R/W-1 TXB1IP (1) TXB0IP R/W-1 R/W-1 RXB1IP RXB0IP R/W-1 R/W-1 RXBnIP FIFOWMIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 IRXIP: CAN Invalid Received Message Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 WAKIP: CAN bus Activity Wake-up Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 ERRIP: CAN bus Error Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 When CAN is in Mode 0: TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 1 or 2: TXBnIP: CAN Transmit Buffer Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 2 TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 1 When CAN is in Mode 0: RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 1 or 2: RXBnIP: CAN Receive Buffer Interrupts Priority bit 1 = High priority 0 = Low priority bit 0 When CAN is in Mode 0: RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 1: Unimplemented: Read as `0' When CAN is in Mode 2: FIFOWMIP: FIFO Watermark Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: x = Bit is unknown In CAN Mode 1 and 2, these bits are forced to `0'. DS39761B-page 126 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 9.5 RCON Register The RCON register contains flag bits which are used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the IPEN bit which enables interrupt priorities. REGISTER 9-13: RCON: RESET CONTROL REGISTER R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0 IPEN SBOREN -- RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit(1) For details of bit operation, see Register 4-1. bit 5 Unimplemented: Read as `0' bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register 4-1. bit 3 TO: Watchdog Time-out Flag bit For details of bit operation, see Register 4-1. bit 2 PD: Power-Down Detection Flag bit For details of bit operation, see Register 4-1. bit 1 POR: Power-on Reset Status bit(2) For details of bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-1. Note 1: 2: x = Bit is unknown If SBOREN is enabled, its Reset state is `1'; otherwise, it is `0'. The actual Reset value of POR is determined by the type of device Reset. See Register 4-1 for additional information. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 127 PIC18F2682/2685/4682/4685 9.6 INTx Pin Interrupts 9.7 External interrupts on the RB0/INT0, RB1/INT1 and RB2/INT2 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set. This interrupt can be disabled by clearing the corresponding enable bit INTxIE. Flag bit, INTxIF, must be cleared in software in the Interrupt Service Routine before re-enabling the interrupt. All external interrupts (INT0, INT1 and INT2) can wake-up the processor from the power-managed modes if bit INTxIE was set prior to going into the power-managed modes. If the Global Interrupt Enable bit, GIE, is set, the processor will branch to the interrupt vector following wake-up. Interrupt priority for INT1 and INT2 is determined by the value contained in the interrupt priority bits, INT1IP (INTCON3<6>) and INT2IP (INTCON3<7>). There is no priority bit associated with INT0. It is always a high priority interrupt source. TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh 00h) will set flag bit TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit TMR0IE (INTCON<5>). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP (INTCON2<2>). See Section 11.0 "Timer0 Module" for further details on the Timer0 module. 9.8 PORTB Interrupt-on-Change An input change on PORTB<7:4> sets flag bit, RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON<3>). Interrupt priority for PORTB interrupt-on-change is determined by the value contained in the interrupt priority bit, RBIP (INTCON2<0>). 9.9 Context Saving During Interrupts During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (See Section 5.3 "Data Memory Organization"), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user's application, other registers may also need to be saved. Example 9-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 9-1: MOVWF MOVFF MOVFF ; ; USER ; MOVFF MOVF MOVFF SAVING STATUS, WREG AND BSR REGISTERS IN RAM W_TEMP STATUS, STATUS_TEMP BSR, BSR_TEMP ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ISR CODE BSR_TEMP, BSR W_TEMP, W STATUS_TEMP, STATUS DS39761B-page 128 ; Restore BSR ; Restore WREG ; Restore STATUS Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 10.0 I/O PORTS 10.1 Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation. These registers are: * TRIS register (data direction register) * PORT register (reads the levels on the pins of the device) * LAT register (output latch) The Data Latch register (LAT) is useful for read-modifywrite operations on the value that the I/O pins are driving. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 10-1. FIGURE 10-1: GENERIC I/O PORT OPERATION RD LAT Data Bus WR LAT or PORT D Q I/O pin(1) CK PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. The Data Latch register (LATA) is also memory mapped. Read-modify-write operations on the LATA register read and write the latched output value for PORTA. The RA4 pin is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. Pins RA6 and RA7 are multiplexed with the main oscillator pins. They are enabled as oscillator or I/O pins by the selection of the main oscillator in Configuration Register 1H (see Section 24.1 "Configuration Bits" for details). When they are not used as port pins, RA6 and RA7 and their associated TRIS and LAT bits are read as `0'. The other PORTA pins are multiplexed with analog inputs, the analog VREF+ and VREF- inputs and the comparator voltage reference output. The operation of RA5 and RA3:RA0 pins as A/D converter inputs is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register 1). Note: Data Latch D WR TRIS Q On a Power-on Reset, RA5 and RA3:RA0 are configured as analog inputs and read as `0'. RA4 is configured as a digital input. All other PORTA pins have TTL input levels and full CMOS output drivers. CK TRIS Latch Input Buffer RD TRIS Q D ENEN The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. EXAMPLE 10-1: CLRF RD PORT CLRF Note 1: PORTA, TRISA and LATA Registers I/O pins have diode protection to VDD and VSS. MOVLW MOVWF MOVWF MOVWF MOVLW MOVWF (c) 2007 Microchip Technology Inc. Preliminary PORTA ; ; ; LATA ; ; ; 0Fh ; ADCON1 ; 07h ; CMCON ; 0CFh ; ; ; TRISA ; ; INITIALIZING PORTA Initialize PORTA by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Configure comparators for digital input Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs DS39761B-page 129 PIC18F2682/2685/4682/4685 TABLE 10-1: PORTA I/O SUMMARY Pin Name RA0/AN0/CVREF Function I/O TRIS Buffer OUT 0 DIG LATA<0> data output. IN 1 TTL PORTA<0> data input. IN 1 ANA A/D input channel 0. Enabled on POR, this analog input overrides the digital input (read as clear - low level). CVREF(1) OUT x ANA Comparator voltage reference analog output. Enabling this analog output overrides the digital I/O (read as clear - low level). RA1 OUT 0 DIG LATA<1> data output. IN 1 TTL PORTA<1> data input. AN1 IN 1 ANA A/D input channel 1. Enabled on POR, this analog input overrides the digital input (read as clear - low level). RA2 OUT 0 DIG LATA<2> data output. IN 1 TTL PORTA<2> data input. IN 1 ANA A/D input channel 2. Enabled on POR, this analog input overrides the digital input (read as clear - low level). RA0 AN0 RA1/AN1 RA2/AN2/VREF- AN2 VREFRA3/AN3/VREF+ RA3 AN3 VREF+ RA4/T0CKI RA4 T0CKI RA5/AN4/SS/HLVDIN RA5 OSC2/CLKO/RA6 OSC1/CLKI/RA7 Legend: Note 1: Description IN 1 ANA A/D and comparator negative voltage analog input. OUT 0 DIG LATA<3> data output. IN 1 TTL PORTA<3> data input. IN 1 ANA A/D input channel 3. Enabled on POR, this analog input overrides the digital input (read as clear - low level). IN 1 ANA A/D and comparator positive voltage analog input. OUT 0 DIG LATA<4> data output. IN 1 TTL PORTA<4> data input. IN 1 ST Timer0 clock input. OUT 0 DIG LATA<5> data output. IN 1 TTL PORTA<5> data input. AN4 IN 1 ANA A/D input channel 4. Enabled on POR, this analog input overrides the digital input (read as clear - low level). SS IN 1 TTL Slave select input for MSSP. HLVDIN IN 1 ANA High/Low-Voltage Detect external trip point input. OSC2 OUT x ANA Output connection, selected by FOSC3:FOSC0 Configuration bits. Enabling OSC2 overrides digital I/O. CLKO OUT x DIG Output connection, selected by FOSC3:FOSC0 Configuration bits. Enabling CLKO overrides digital I/O (FOSC/4). RA6 OUT 0 DIG LATA<6> data output. IN 1 TTL PORTA<6> data input. OSC1 IN x ANA Main oscillator input connection, determined by FOSC3:FOSC0 Configuration bits. Enabling OSC1 overrides digital I/O. CLKI IN x ANA Main clock input connection, determined by FOSC3:FOSC0 Configuration bits. Enabling CLKI overrides digital I/O. RA7 OUT 0 DIG LATA<7> data output. IN 1 TTL PORTA<7> data input. OUT = Output; IN = Input; ANA = Analog Signal; DIG = Digital Output; ST = Schmitt Buffer Input; TTL = TTL Buffer Input This bit is unimplemented on PIC18F2682/2685 devices. DS39761B-page 130 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 10-2: Name PORTA SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 (1) LATA6(1) LATA Data Output Register LATA LATA7 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Register Reset Values on page 52 52 52 ADCON1 -- -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 50 CMCON(2) C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 51 CVRCON(2) CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 51 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as `0'. 2: These registers are unimplemented on PIC18F2682/2685 devices. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 131 PIC18F2682/2685/4682/4685 10.2 PORTB, TRISB and LATB Registers Note: PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped. Read-modify-write operations on the LATB register read and write the latched output value for PORTB. Pins RB2 through RB3 are multiplexed with the ECAN peripheral. Refer to Section 23.0 "ECANTM Technology" for proper settings of TRISB when CAN is enabled. EXAMPLE 10-2: CLRF CLRF MOVLW MOVWF MOVLW MOVWF PORTB ; ; ; LATB ; ; ; 0Eh ; ADCON1 ; ; ; 0CFh ; ; ; TRISB ; ; ; INITIALIZING PORTB On a Power-on Reset, RB4:RB0 are configured as analog inputs by default and read as `0'; RB7:RB5 are configured as digital inputs. By programming the Configuration bit, PBADEN (CONFIG3H<1>), RB4:RB0 will alternatively be configured as digital inputs on POR. Four of the PORTB pins (RB7:RB4) have an interrupt-on-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupt-on-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are ORed together to generate the RB Port Change Interrupt with Flag bit, RBIF (INTCON<0>). This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: Initialize PORTB by clearing output data latches Alternate method to clear output data latches Set RB<4:0> as digital I/O pins (required if config bit PBADEN is set) Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs a) b) Any read or write of PORTB (except with the MOVFF (ANY), PORTB instruction). This will end the mismatch condition. Clear flag bit, RBIF. A mismatch condition will continue to set flag bit, RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on all device Resets. DS39761B-page 132 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 10-3: Pin Name PORTB I/O SUMMARY Function RB0/INT0/FLT0/AN10 RB0 RB1/INT1/AN8 RB2/INT2/CANTX RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD Legend: Note 1: Buffer Description 0 DIG LATB<0> data output. IN 1 TTL PORTB<0> data input. Weak pull-up available only in this mode. INT0 IN 1 ST External interrupt 0 input. FLT0(1) IN 1 ST Enhanced PWM Fault input. AN10 IN 1 ANA A/D input channel 10. Enabled on POR, this analog input overrides the digital input (read as clear - low level). RB1 OUT 0 DIG LATB<1> data output. IN 1 TTL PORTB<1> data input. Weak pull-up available only in this mode. INT1 IN 1 ST External interrupt 1 input. AN8 IN 1 ANA A/D input channel 8. Enabled on POR, this analog input overrides the digital input (read as clear - low level). RB2 OUT x DIG LATB<2> data output. IN 1 TTL PORTB<2> data input. Weak pull-up available only in this mode. IN 1 ST External interrupt 2 input. CANTX OUT 1 DIG CAN transmit signal output. The CAN interface overrides the TRIS<2> control when enabled. RB3 OUT 0 DIG LATB<3> data output. IN 1 TTL PORTB<3> data input. Weak pull-up available only in this mode. IN 1 ST CAN receive signal input. Pin must be configured as a digital input by setting TRISB<3>. CANRX RB4/KBI0/AN9 TRIS OUT INT2 RB3/CANRX I/O RB4 OUT 0 DIG LATB<4> data output. IN 1 TTL PORTB<4> data input. Weak pull-up available only in this mode. KBI0 IN 1 TTL Interrupt-on-pin change. AN9 IN 1 ANA A/D input channel 9. Enabled on POR, this analog input overrides the digital input (read as clear - low level). RB5 OUT 0 DIG LATB<5> data output. IN 1 TTL PORTB<5> data input. Weak pull-up available only in this mode. KBI1 IN 1 TTL Interrupt-on-pin change. PGM IN x ST Low-Voltage Programming mode entry (ICSPTM). Enabling this function overrides digital output. RB6 OUT 0 DIG LATB<6> data output. IN 1 TTL PORTB<6> data input. Weak pull-up available only in this mode. Interrupt-on-pin change. KBI2 IN 1 TTL PGC IN x ST Low-Voltage Programming mode entry (ICSP) clock input. RB7 OUT 0 DIG LATB<7> data output. IN 1 TTL PORTB<7> data input. Weak pull-up available only in this mode. KBI3 IN 1 TTL Interrupt-on-pin change. PGD OUT x DIG Low-Voltage Programming mode entry (ICSP) clock output. IN x ST Low-Voltage Programming mode entry (ICSP) clock input. OUT = Output; IN = Input; ANA = Analog Signal; DIG = Digital Output; ST = Schmitt Buffer Input; TTL - TTL Buffer Input This bit is unimplemented on PIC18F2682/2685 devices. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 133 PIC18F2682/2685/4682/4685 TABLE 10-4: Name PORTB SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 52 LATB LATB Data Output Register 52 TRISB PORTB Data Direction Register 52 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE INTEDG0 INTEDG1 INTEDG2 RBIE TMR0IF INT0IF RBIF 49 -- TMR0IP -- RBIP 49 INTCON2 RBPU INTCON3 INT2IP INT1IP -- INT2IE INT1IE -- INT2IF INT1IF 49 ADCON1 -- -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 50 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTB. DS39761B-page 134 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 10.3 PORTC, TRISC and LATC Registers Note: PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATC) is also memory mapped. Read-modify-write operations on the LATC register read and write the latched output value for PORTC. PORTC is multiplexed with several peripheral functions (Table 10-5). The pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. (c) 2007 Microchip Technology Inc. On a Power-on Reset, these pins are configured as digital inputs. The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins. EXAMPLE 10-3: CLRF PORTC CLRF LATC MOVLW 0CFh MOVWF TRISC Preliminary INITIALIZING PORTC ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTC by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RC<3:0> as inputs RC<5:4> as outputs RC<7:6> as inputs DS39761B-page 135 PIC18F2682/2685/4682/4685 TABLE 10-5: Pin Name RC0/T1OSO/ T13CKI RC1/T1OSI PORTC I/O SUMMARY Function I/O TRIS Buffer OUT 0 DIG LATC<0> data output. IN 1 ST PORTC<0> data input. T1OSO OUT x ANA T13CKI IN 1 ST Timer1/Timer3 clock input. OUT 0 DIG LATC<1> data output. IN 1 ST PORTC<1> data input. RC0 RC1 T1OSI RC2/CCP1 Description Timer1 oscillator output - overrides the TRIS<0> control when enabled. IN x ANA Timer1 oscillator input - overrides the TRIS<1> control when enabled. RC2 OUT 0 DIG LATC<2> data output. IN 1 ST PORTC<2> data input. CCP1 OUT 0 DIG CCP1 compare output. IN 1 ST CCP1 capture input. RC3/SCK/SCL RC3 OUT 0 DIG LATC<3> data output. IN 1 ST PORTC<3> data input. SCK OUT 0 DIG SPI clock output (MSSP module) - must have TRIS set to `1' to allow the MSSP module to control the bidirectional communication. IN 1 ST SPI clock input (MSSP module). SCL OUT 0 DIG I2CTM/SMBus clock output (MSSP module) - must have TRIS set to `1' to allow the MSSP module to control the bidirectional communication. IN 1 OUT 0 DIG RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT Legend: RC4 I2C/SMB I2C/SMBus clock input. LATC<4> data output. IN 1 ST PORTC<4> data input. SDI IN 1 ST SPI data input (MSSP module). SDA OUT 1 DIG I2C/SMBus data output (MSSP module) - must have TRIS set to `1' to allow the MSSP module to control the bidirectional communication. IN 1 RC5 I2C/SMB I2C/SMBus data input (MSSP module) - must have TRIS set to `1' to allow the MSSP module to control the bidirectional communication. OUT 0 DIG IN 1 ST LATC<5> data output. PORTC<5> data input. SDO OUT 0 DIG SPI data output (MSSP module). RC6 OUT 0 DIG LATC<6> data output. IN 1 ST PORTC<6> data input. TX OUT 0 DIG EUSART data output. CK OUT 1 DIG EUSART synchronous clock output - must have TRIS set to `1' to enable EUSART to control the bidirectional communication. IN 1 ST EUSART synchronous clock input. RC7 OUT 0 DIG LATC<7> data output. IN 1 ST PORTC<7> data input. RX IN 1 ST EUSART asynchronous data input. DT OUT 1 DIG EUSART synchronous data output - must have TRIS set to `1' to enable EUSART to control the bidirectional communication. IN 1 ST EUSART synchronous data input. OUT = Output; IN = Input; ANA = Analog Signal; DIG = Digital Output; ST = Schmitt Buffer Input; TTL = TTL Buffer Input; I2C = Inter-Integrated Circuit; SMBus = System Management Bus DS39761B-page 136 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 10-6: Name PORTC SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 52 LATC LATC Data Output Register 52 TRISC PORTC Data Direction Register 52 (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 137 PIC18F2682/2685/4682/4685 10.4 Note: PORTD, TRISD and LATD Registers PORTD is only available on PIC18F4682/ 4685 devices. PORTD is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATD) is also memory mapped. Read-modify-write operations on the LATD register read and write the latched output value for PORTD. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Three of the PORTD pins are multiplexed with outputs P1A, P1B, P1C and P1D of the Enhanced CCP1 (ECCP1) module. The operation of these additional PWM output pins is covered in greater detail in Section 16.0 "Enhanced Capture/Compare/PWM (ECCP1) Module". Note: PORTD can also be configured as an 8-bit wide microprocessor port (Parallel Slave Port) by setting control bit, PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. See Section 10.6 "Parallel Slave Port" for additional information on the Parallel Slave Port (PSP). Note: When the Enhanced PWM mode is used with either dual or quad outputs, the PSP functions of PORTD are automatically disabled. EXAMPLE 10-4: CLRF PORTD CLRF LATD MOVLW 0CFh MOVWF TRISD INITIALIZING PORTD ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTD by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RD<3:0> as inputs RD<5:4> as outputs RD<7:6> as inputs On a Power-on Reset, these pins are configured as digital inputs. DS39761B-page 138 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 10-7: Pin Name RD0/PSP0/ C1IN+ PORTD I/O SUMMARY Function RD0 0 DIG LATD<0> data output. 1 ST PORTD<0> data input. OUT x DIG Parallel Slave Port (PSP) data output (overrides the TRIS<0> control when enabled). IN x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<0> control when enabled). IN 1 ANA Comparator 1 positive input B. Default on POR. This analog input overrides the digital input (read as clear - low level). OUT 0 DIG LATD<1> data output. IN 1 ST PORTD<1> data input. OUT x DIG Parallel Slave Port (PSP) data output (overrides the TRIS<1> control when enabled). IN x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<1> control when enabled). IN 1 ANA Comparator 1 negative input. Default on POR. This analog input overrides the digital input (read as clear - low level). OUT 0 DIG LATD<2> data output. IN 1 ST PORTD<2> data input. OUT x DIG Parallel Slave Port (PSP) data output (overrides the TRIS<2> control when enabled). IN x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<2> control when enabled). IN 1 ANA Comparator 2 positive input. Default on POR. This analog input overrides the digital input (read as clear - low level). RD3 OUT 0 DIG LATD<3> data output. IN 1 ST PORTD<3> data input. PSP3 OUT x DIG Parallel Slave Port (PSP) data output (overrides the TRIS<3> control when enabled). RD1 PSP1 C1INRD2 PSP2 C2IN+ RD3/PSP3/ C2IN- C2INRD4/PSP4/ RD4 ECCP1/P1A PSP4 ECCP1 RD5/PSP5/ P1B RD6/PSP6/ P1C Legend: IN x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<3> control when enabled). IN 1 ANA Comparator 2 negative input. Default input on POR. This analog input overrides the digital input (read as clear - low level). OUT 0 DIG LATD<4> data output. IN 1 ST PORTD<4> data input. OUT x DIG Parallel Slave Port (PSP) data output (overrides the TRIS<4> control when enabled). IN x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<4> control when enabled). OUT 0 DIG ECCP1 compare output. IN 1 ST ECCP1 capture input. P1A OUT 0 DIG ECCP1 Enhanced PWM output, channel A. RD5 OUT 0 DIG LATD<5> data output. IN 1 ST PORTD<5> data input. PSP5 OUT X DIG Parallel Slave Port (PSP) data output (overrides the TRIS<5> control when enabled). IN x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<5> control when enabled). P1B OUT 0 DIG ECCP1 Enhanced PWM output, channel B. RD6 OUT 0 DIG LATD<6> data output. IN 1 ST PORTD<6> data input. OUT x DIG Parallel Slave Port (PSP) data output (overrides the TRIS<6> control when enabled). IN x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<6> control when enabled). P1C OUT 0 DIG ECCP1 Enhanced PWM output, channel C. RD7 OUT 0 DIG LATD<7> data output. IN 1 ST PORTD<7> data input. PSP7 OUT x DIG Parallel Slave Port (PSP) data output (overrides the TRIS<7> control when enabled). IN x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<7> control when enabled). P1D OUT 0 DIG ECCP1 Enhanced PWM output, channel D. PSP6 RD7/PSP7/ P1D Description IN C1IN+ RD2/PSP2/ C2IN+ TRIS Buffer OUT PSP0 RD1/PSP1/ C1IN- I/O OUT = Output; IN = Input; ANA = Analog Signal; DIG = Digital Output; ST = Schmitt Buffer Input; TTL = TTL Buffer Input (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 139 PIC18F2682/2685/4682/4685 TABLE 10-8: Name PORTD(1) SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 Reset Values on page 52 LATD(1) LATD Data Output Register 52 TRISD(1) PORTD Data Direction Register 52 (1) IBF TRISE OBF ECCP1CON(1) EPWM1M1 EPWM1M0 Legend: Note 1: IBOV PSPMODE EDC1B1 EDC1B0 -- TRISE2 TRISE1 TRISE0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 52 51 -- = unimplemented, read as `0'. Shaded cells are not used by PORTD. These registers are available on PIC18F4682/4685 devices only. DS39761B-page 140 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 10.5 PORTE, TRISE and LATE Registers Depending on the particular PIC18F2682/2685/4682/ 4685 device selected, PORTE is implemented in two different ways. For PIC18F4682/4685 devices, PORTE is a 4-bit wide port. Three pins (RE0/RD/AN5, RE1/WR/AN6/C1OUT and RE2/CS/AN7/C2OUT) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as an analog input, these pins will read as `0's. The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin). TRISE controls the direction of the RE pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. Note: On a Power-on Reset, RE2:RE0 are configured as analog inputs. The upper four bits of the TRISE register also control the operation of the Parallel Slave Port. Their operation is explained in Register 10-1. The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register, read and write the latched output value for PORTE. (c) 2007 Microchip Technology Inc. The fourth pin of PORTE (MCLR/VPP/RE3) is an input only pin. Its operation is controlled by the MCLRE Configuration bit. When selected as a port pin (MCLRE = 0), it functions as a digital input only pin. As such, it does not have TRIS or LAT bits associated with its operation. Otherwise, it functions as the device's Master Clear input. In either configuration, RE3 also functions as the programming voltage input during programming. Note: On a Power-on Reset, RE3 is enabled as a digital input only if Master Clear functionality is disabled. EXAMPLE 10-5: CLRF PORTE CLRF LATE MOVLW MOVWF MOVLW 0Ah ADCON1 03h MOVLW MOVWF MOVWF 07h CMCON TRISC 10.5.1 INITIALIZING PORTE ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTE by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Value used to initialize data direction Turn off comparators Set RE<0> as inputs RE<1> as outputs RE<2> as inputs PORTE IN 28-PIN DEVICES For PIC18F2682/2685 devices, PORTE is only available when Master Clear functionality is disabled (MCLRE = 0). In these cases, PORTE is a single bit, input only port comprised of RE3 only. The pin operates as previously described. Preliminary DS39761B-page 141 PIC18F2682/2685/4682/4685 REGISTER 10-1: TRISE REGISTER (PIC18F4682/4685 DEVICES ONLY) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE -- TRISE2 TRISE1 TRISE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General purpose I/O mode bit 3 Unimplemented: Read as `0' bit 2 TRISE2: RE2 Direction Control bit 1 = Input 0 = Output bit 1 TRISE1: RE1 Direction Control bit 1 = Input 0 = Output bit 0 TRISE0: RE0 Direction Control bit 1 = Input 0 = Output DS39761B-page 142 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 10-9: PORTE I/O SUMMARY Pin Name Function RE0/RD/AN5 RE0 MCLR/VPP/RE3 Legend: TRIS Buffer OUT 0 DIG Description LATE<0> data output. IN 1 ST PORTE<0> data input. RD IN 1 TTL PSP read enable input. AN5 IN 1 ANA A/D input channel 5. Enabled on POR, this analog input overrides the digital input (read as clear - low level). OUT 0 DIG LATE<1> data output. RE1/WR/AN6/C1OUT RE1 RE2/CS/AN7/C2OUT I/O IN 1 ST PORTE<1> data input. WR IN 1 TTL PSP write enable input. AN6 IN 1 ANA A/D input channel 6. Enabled on POR, this analog input overrides the digital input (read as clear - low level). C1OUT OUT 0 DIG Comparator 1 output. RE2 OUT 0 DIG LATE<2> data output. IN 1 ST PORTE<2> data input. CS IN 1 TTL PSP chip select input. AN7 IN 1 ANA A/D input channel 7. Enabled on POR, this analog input overrides the digital input (read as clear - low level). C2OUT OUT 0 DIG Comparator 2 output. MCLR IN x ST VPP IN x ANA RE3 IN 1 ST External Reset input. Disabled when MCLRE Configuration bit is `1'. High-voltage detection; used by ICSPTM operation. PORTE<3> data input. Disabled when MCLRE Configuration bit is `0'. OUT = Output; IN = Input; ANA = Analog Signal; DIG = Digital Output; ST = Schmitt Buffer Input; TTL = TTL Buffer Input TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Name PORTE(3) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page -- -- -- -- RE3(1,2) RE2 RE1 RE0 52 LATE(3) -- -- -- -- -- TRISE(3) IBF OBF IBOV PSPMODE -- TRISE2 TRISE1 TRISE0 52 LATE Data Output Register 52 ADCON1 -- -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 50 CMCON(3) C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 51 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTE. Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0). 2: RE3 is the only PORTE bit implemented on both PIC18F2682/2685 and PIC18F4682/4685 devices. All other bits are implemented only when PORTE is implemented (i.e., PIC18F4682/4685 devices). 3: These registers are unimplemented on PIC18F2682/2685 devices. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 143 PIC18F2682/2685/4682/4685 10.6 Note: Parallel Slave Port The Parallel Slave Port is only available on PIC18F4682/4685 devices. In addition to its function as a general I/O port, PORTD can also operate as an 8-bit wide Parallel Slave Port (PSP) or microprocessor port. PSP operation is controlled by the 4 upper bits of the TRISE register (Register 10-1). Setting control bit, PSPMODE (TRISE<4>), enables PSP operation, as long as the Enhanced CCP1 (ECCP1) module is not operating in dual output or quad output PWM mode. In Slave mode, the port is asynchronously readable and writable by the external world. The timing for the control signals in Write and Read modes is shown in Figure 10-3 and Figure 10-4, respectively. FIGURE 10-2: One bit of PORTD Data Bus Q RDx pin CK Data Latch Q RD PORTD TTL D ENEN RD LATD Set Interrupt Flag PSPIF (PIR1<7>) A write to the PSP occurs when both the CS and WR lines are first detected low and ends when either are detected high. The PSPIF and IBF flag bits are both set when the write ends. PORTE Pins Read TTL RD TTL CS TTL WR Chip Select A read from the PSP occurs when both the CS and RD lines are first detected low. The data in PORTD is read out and the OBF bit is set. If the user writes new data to PORTD to set OBF, the data is immediately read out; however, the OBF bit is not set. DS39761B-page 144 D WR LATD or WR PORTD The PSP can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting the control bit, PSPMODE, enables the PORTE I/O pins to become control inputs for the microprocessor port. When set, port pin RE0 is the RD input, RE1 is the WR input and RE2 is the CS (Chip Select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (set). The A/D port configuration bits, PFCG3:PFCG0 (ADCON1<3:0>), must also be set to `1010'. When either the CS or RD line is detected high, the PORTD pins return to the input state and the PSPIF bit is set. User applications should wait for PSPIF to be set before servicing the PSP. When this happens, the IBF and OBF bits can be polled and the appropriate action taken. PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) Write Note: Preliminary I/O pins have diode protection to VDD and VSS. (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 FIGURE 10-3: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 10-4: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 10-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 52 LATD (1) TRISD(1) (1) LATD Data Output Register 52 PORTD Data Direction Register 52 -- -- -- -- RE3 LATE(1) -- -- -- -- -- TRISE(1) IBF OBF IBOV PSPMODE -- TRISE2 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF PIR1 PSPIF(2) ADIF RCIF TXIF SSPIF CCP1IF PIE1 PSPIE(2) ADIE RCIE TXIE SSPIE CCP1IE IPR1 (2) PORTE CMCON (1) Legend: Note 1: 2: RE1 RE0 52 TRISE0 52 INT0IF RBIF 49 TMR2IF TMR1IF 52 TMR2IE TMR1IE 52 TRISE1 52 ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 -- -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 50 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 51 PSPIP ADCON1 RE2 LATE Data Output Register -- = unimplemented, read as `0'. Shaded cells are not used by the Parallel Slave Port. These registers are available on PIC18F4682/4685 devices only. These bits are unimplemented on PIC18F2682/2685 devices and read as `0'. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 145 PIC18F2682/2685/4682/4685 NOTES: DS39761B-page 146 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 11.0 TIMER0 MODULE The T0CON register (Register 11-1) controls all aspects of the module's operation, including the prescale selection. It is both readable and writable. The Timer0 module incorporates the following features: * Software selectable operation as a timer or counter in both 8-bit or 16-bit modes * Readable and writable registers * Dedicated 8-bit, software programmable prescaler * Selectable clock source (internal or external) * Edge select for external clock * Interrupt-on-overflow REGISTER 11-1: A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1. Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-Bit/16-Bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 147 PIC18F2682/2685/4682/4685 11.1 Timer0 Operation Timer0 can operate as either a timer or a counter; the mode is selected by clearing the T0CS bit (T0CON<5>). In Timer mode, the module increments on every clock by default unless a different prescaler value is selected (see Section 11.3 "Prescaler"). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. The Counter mode is selected by setting the T0CS bit (= 1). In Counter mode, Timer0 increments either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE (T0CON<4>). Clearing this bit selects the rising edge. Restrictions on the external clock input are discussed below. An external clock source can be used to drive Timer0; however, it must meet certain requirements to ensure that the external clock can be synchronized with the FIGURE 11-1: internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the timer/counter. 11.2 Timer0 Reads and Writes in 16-Bit Mode TMR0H is not the actual high byte of Timer0 in 16-bit mode; it is actually a buffered version of the real high byte of Timer0, which is not directly readable nor writable (refer to Figure 11-2). TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0 without having to verify that the read of the high and low byte were valid, due to a rollover between successive reads of the high and low byte. Similarly, a write to the high byte of Timer0 must also take place through the TMR0H Buffer register. The high byte is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once. TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 1 1 Programmable Prescaler T0CKI pin T0SE T0CS 0 Sync with Internal Clocks Set TMR0IF on Overflow TMR0L (2 TCY Delay) 8 3 T0PS2:T0PS0 8 PSA Note: Internal Data Bus Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. FIGURE 11-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) FOSC/4 0 1 1 T0CKI pin T0SE T0CS Programmable Prescaler 0 Sync with Internal Clocks TMR0 High Byte TMR0L 8 Set TMR0IF on Overflow (2 TCY Delay) 3 Read TMR0L T0PS2:T0PS0 Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS39761B-page 148 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 11.3 11.3.1 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable; its value is set by the PSA and T0PS2:T0PS0 bits (T0CON<3:0>) which determine the prescaler assignment and prescale ratio. Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values from 1:2 through 1:256 in power-of-2 increments are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF TMR0, MOVWF TMR0, BSF TMR0, etc.) clear the prescaler count. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count but will not change the prescaler assignment. TABLE 11-1: Name The prescaler assignment is fully under software control and can be changed "on-the-fly" during program execution. 11.4 Since Timer0 is shut down in Sleep mode, the TMR0 interrupt cannot awaken the processor from Sleep. REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Timer0 Register Low Byte TMR0H Timer0 Register High Byte INTCON GIE/GIEH PEIE/GIEL TMR0IE T0CON TMR0ON T08BIT T0CS T0SE PSA TRISA7(1) TRISA6(1) PORTA Data Direction Register Legend: Note 1: Timer0 Interrupt The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or from FFFFh to 0000h in 16-bit mode. This overflow sets the TMR0IF flag bit. The interrupt can be masked by clearing the TMR0IE bit (INTCON<5>). Before reenabling the interrupt, the TMR0IF bit must be cleared in software by the Interrupt Service Routine. TMR0L TRISA SWITCHING PRESCALER ASSIGNMENT Bit 2 Bit 1 Bit 0 Reset Values on page 50 50 INT0IE RBIE TMR0IF INT0IF RBIF T0PS2 T0PS1 T0PS0 49 50 52 x = unknown, u = unchanged, -- = unimplemented locations, read as `0'. Shaded cells are not used by Timer0. RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as `0'. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 149 PIC18F2682/2685/4682/4685 NOTES: DS39761B-page 150 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 12.0 TIMER1 MODULE The Timer1 timer/counter module incorporates these features: * Software selectable operation as a 16-bit timer or counter * Readable and writable 8-bit registers (TMR3H and TMR3L) * Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options * Interrupt on overflow * Module Reset on CCP1 Special Event Trigger * Device clock status flag (T1RUN) REGISTER 12-1: A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module's operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option. The Timer1 oscillator can also be used as a low-power clock source for the microcontroller in power-managed operation. Timer1 can also be used to provide Real-Time Clock (RTC) functionality to applications with only a minimal addition of external components and code overhead. Timer1 is controlled through the T1CON Control register (Register 12-1). It also contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>). T1CON: TIMER1 CONTROL REGISTER R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 6 T1RUN: Timer1 System Clock Status bit 1 = Device clock is derived from Timer1 oscillator 0 = Device clock is derived from another source bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 oscillator is enabled 0 = Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 151 PIC18F2682/2685/4682/4685 12.1 Timer1 Operation cycle (Fosc/4). When the bit is set, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer1 can operate in one of these modes: * Timer * Synchronous Counter * Asynchronous Counter When Timer1 is enabled, the RC1/T1OSI and RC0/ T1OSO/T13CKI pins become inputs. This means the values of TRISC<1:0> are ignored and the pins are read as `0'. The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared (= 0), Timer3 increments on every internal instruction FIGURE 12-1: TIMER1 BLOCK DIAGRAM Timer1 Oscillator On/Off 1 1 T1OSO/T13CKI FOSC/4 Internal Clock Synchronize Detect Prescaler 1, 2, 4, 8 T1OSI 2 T1OSCEN(1) 0 0 Sleep Input TMR1CS Timer1 On/Off T1CKPS1:T1CKPS0 T1SYNC TMR1ON Clear TMR1 (CCP1 Special Event Trigger) TMR1L Set TMR1IF on Overflow TMR1 High Byte Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 12-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator 1 T1OSO/T13CKI 1 FOSC/4 Internal Clock T1OSI Prescaler 1, 2, 4, 8 Synchronize Detect 0 0 2 (1) T1OSCEN T1CKPS1:T1CKPS0 T1SYNC TMR1ON Sleep Input TMR1CS Timer1 On/Off Clear TMR1 (CCP1 Special Event Trigger) TMR1 High Byte TMR1L 8 Set TMR1IF on Overflow Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39761B-page 152 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 12.2 TABLE 12-1: Timer1 16-Bit Read/Write Mode Timer1 can be configured for 16-bit reads and writes (see Figure 12-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 High Byte Buffer register. This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. Osc Type Freq C1 C2 LP 32.768 kHz 27 pF 27 pF Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit. 2: Higher capacitance increases the stability of the oscillator but also increases the start-up time. A write to the high byte of Timer1 must also take place through the TMR1H Buffer register. The Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. This allows a user to write all 16 bits to both the high and low bytes of Timer1 at once. The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L. 12.3 Timer1 Oscillator An on-chip crystal oscillator circuit is incorporated between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting the Timer1 Oscillator Enable bit, T1OSCEN (T1CON<3>). The oscillator is a low-power circuit rated for 32 kHz crystals. It will continue to run during all power-managed modes. The circuit for a typical LP oscillator is shown in Figure 12-3. Table 12-1 shows the capacitor selection for the Timer1 oscillator. The user must provide a software time delay to ensure proper start-up of the Timer1 oscillator. FIGURE 12-3: EXTERNAL COMPONENTS FOR THE TIMER1 LP OSCILLATOR C1 27 pF PIC18FXXXX T1OSI XTAL 32.768 kHz T1OSO C2 27 pF Note: See the Notes with Table 12-1 for additional information about capacitor selection. (c) 2007 Microchip Technology Inc. CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR(1,2,3,4) 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Capacitor values are for design guidance only. 12.3.1 USING TIMER1 AS A CLOCK SOURCE The Timer1 oscillator is also available as a clock source in power-managed modes. By setting the Clock Select bits, SCS1:SCS0 (OSCCON<1:0>), to `01', the device switches to SEC_RUN mode; both the CPU and peripherals are clocked from the Timer1 oscillator. If the IDLEN bit (OSCCON<7>) is cleared and a SLEEP instruction is executed, the device enters SEC_IDLE mode. Additional details are available in Section 3.0 "Power-Managed Modes". Whenever the Timer1 oscillator is providing the clock source, the Timer1 system clock status flag, T1RUN (T1CON<6>), is set. This can be used to determine the controller's current clocking mode. It can also indicate the clock source being currently used by the Fail-Safe Clock Monitor. If the Clock Monitor is enabled and the Timer1 oscillator fails while providing the clock, polling the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source. 12.3.2 LOW-POWER TIMER1 OPTION The Timer1 oscillator can operate at two distinct levels of power consumption based on device configuration. When the LPT1OSC Configuration bit is set, the Timer1 oscillator operates in a low-power mode. When LPT1OSC is not set, Timer1 operates at a higher power level. Power consumption for a particular mode is relatively constant, regardless of the device's operating mode. The default Timer1 configuration is the higher power mode. As the low-power Timer1 mode tends to be more sensitive to interference, high noise environments may cause some oscillator instability. The low-power option is, therefore, best suited for low noise applications where power conservation is an important design consideration. Preliminary DS39761B-page 153 PIC18F2682/2685/4682/4685 12.3.3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS 12.5 The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 12-3, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD. If a high-speed circuit must be located near the oscillator (such as the CCP1 pin in Output Compare or PWM mode, or the primary oscillator using the OSC2 pin), a grounded guard ring around the oscillator circuit, as shown in Figure 12-4, may be helpful when used on a single-sided PCB or in addition to a ground plane. FIGURE 12-4: OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING If either of the CCP1 modules is configured in Compare mode to generate a Special Event Trigger (CCP1M3:CCP1M0 or CCP2M3:CCP2M0 = 1011), this signal will reset Timer1. The trigger from ECCP1 will also start an A/D conversion if the A/D module is enabled (see Section 15.3.4 "Special Event Trigger" for more information.). The module must be configured as either a timer or a synchronous counter to take advantage of this feature. When used this way, the CCPR1H:CCPR1L register pair effectively becomes a period register for Timer1. If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work. In the event that a write to Timer1 coincides with a Special Event Trigger, the write operation will take precedence. Note: VDD VSS 12.6 OSC1 OSC2 The Special Event Triggers from the ECCP1 module will not set the TMR1IF interrupt flag bit (PIR1<0>). Using Timer1 as a Real-Time Clock Adding an external LP oscillator to Timer1 (such as the one described in Section 12.3 "Timer1 Oscillator") gives users the option to include RTC functionality to their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time. When operating in Sleep mode and using a battery or supercapacitor as a power source, it can completely eliminate the need for a separate RTC device and battery backup. RC0 RC1 RC2 Note: Not drawn to scale. 12.4 Resetting Timer1 Using the CCP1 Special Event Trigger Timer1 Interrupt The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled or disabled by setting or clearing the Timer1 Interrupt Enable bit, TMR1IE (PIE1<0>). The application code routine, RTCisr, shown in Example 12-1, demonstrates a simple method to increment a counter at one-second intervals using an Interrupt Service Routine. Incrementing the TMR1 register pair to overflow triggers the interrupt and calls the routine, which increments the seconds counter by one; additional counters for minutes and hours are incremented as the previous counter overflow. Since the register pair is 16 bits wide, counting up to overflow the register directly from a 32.768 kHz clock would take 2 seconds. To force the overflow at the required one-second intervals, it is necessary to preload it. The simplest method is to set the MSb of TMR1H with a BSF instruction. Note that the TMR1L register is never preloaded or altered; doing so may introduce cumulative error over many cycles. For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1) as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. DS39761B-page 154 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN 80h TMR1H TMR1L b'00001111' T1OSC secs mins .12 hours PIE1, TMR1IE ; Preload TMR1 register pair ; for 1 second overflow BSF BCF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN MOVLW MOVWF RETURN TMR1H, 7 PIR1, TMR1IF secs, F .59 secs ; ; ; ; Preload for 1 sec overflow Clear interrupt flag Increment seconds 60 seconds elapsed? ; ; ; ; No, done Clear seconds Increment minutes 60 minutes elapsed? ; ; ; ; No, done clear minutes Increment hours 24 hours elapsed? ; Configure for external clock, ; Asynchronous operation, external oscillator ; Initialize timekeeping registers ; ; Enable Timer1 interrupt RTCisr TABLE 12-2: Name INTCON secs mins, F .59 mins mins hours, F .23 hours ; No, done ; Reset hours to 1 .01 hours ; Done REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 Bit 6 GIE/GIEH PEIE/GIEL PIR1 PSPIF (1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 TMR1L Timer1 Register Low Byte TMR1H TImer1 Register High Byte T1CON RD16 T1RUN 50 50 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 50 Legend: x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used by the Timer1 module. Note 1: These bits are unimplemented on PIC18F2682/2685 devices; always maintain these bits clear. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 155 PIC18F2682/2685/4682/4685 NOTES: DS39761B-page 156 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 13.0 TIMER2 MODULE 13.1 Timer2 Operation * 8-bit timer and period registers (TMR2 and PR2, respectively) * Readable and writable (both registers) * Software programmable prescaler (1:1, 1:4 and 1:16) * Software programmable postscaler (1:1 through 1:16) * Interrupt on TMR2 to PR2 match * Optional use as the shift clock for the MSSP module In normal operation, TMR2 is incremented from 00h on each clock (FOSC/4). A 2-bit counter/prescaler on the clock input gives direct input, divide-by-4 and divideby-16 prescale options. These options are selected by the prescaler control bits, T2CKPS1:T2CKPS0 (T2CON<1:0>). The value of TMR2 is compared to that of the period register, PR2, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMR2 to 00h on the next cycle and drives the output counter/postscaler (see Section 13.2 "Timer2 Interrupt"). The module is controlled through the T2CON register (Register 13-1), which enables or disables the timer and configures the prescaler and postscaler. Timer2 can be shut off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption. The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, while the PR2 register initializes at FFh. Both the prescaler and postscaler counters are cleared on the following events: A simplified block diagram of the module is shown in Figure 13-1. * a write to the TMR2 register * a write to the T2CON register * any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) The Timer2 module incorporates the following features: TMR2 is not cleared when T2CON is written. REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6-3 T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale * * * 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 (c) 2007 Microchip Technology Inc. Preliminary x = Bit is unknown DS39761B-page 157 PIC18F2682/2685/4682/4685 13.2 Timer2 Interrupt 13.3 Timer2 also can generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/ postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>). TMR2 Output The unscaled output of TMR2 is available primarily to the CCP1 modules, where it is used as a time base for operations in PWM mode. Timer2 can be optionally used as the shift clock source for the MSSP module operating in SPI mode. Additional information is provided in Section 17.0 "Master Synchronous Serial Port (MSSP) Module". A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>). FIGURE 13-1: TIMER2 BLOCK DIAGRAM 4 1:1 to 1:16 Postscaler T2OUTPS3:T2OUTPS0 Set TMR2IF 2 T2CKPS1:T2CKPS0 TMR2 Output (to PWM or MSSP) TMR2/PR2 Match Reset 1:1, 1:4, 1:16 Prescaler FOSC/4 TMR2 Comparator 8 PR2 8 8 Internal Data Bus TABLE 13-1: Name REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 TMR2 T2CON PR2 Timer2 Register -- 50 T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 Timer2 Period Register 50 50 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Timer2 module. Note 1: These bits are unimplemented on PIC18F2682/2685 devices; always maintain these bits clear. DS39761B-page 158 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 14.0 TIMER3 MODULE The Timer3 timer/counter module incorporates these features: * Software selectable operation as a 16-bit timer or counter * Readable and writable 8-bit registers (TMR3H and TMR3L) * Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options * Interrupt on overflow * Module Reset on CCP1 Special Event Trigger REGISTER 14-1: A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module's operation in Read/Write mode is shown in Figure 14-2. The Timer3 module is controlled through the T3CON register (Register 14-1). It also selects the clock source options for the ECCP1/CCP1 modules (see Section 15.1.1 "CCP1 Modules and Timer Resources" for more information). T3CON: TIMER3 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T3ECCP1(1) T3CKPS1 T3CKPS0 T3CCP1(1) T3SYNC TMR3CS TMR3ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations bit 6,3 T3ECCP1:T3CCP1: Timer3 and Timer1 to ECCP1/CCP1 Enable bits(1) 1x = Timer3 is the capture/compare clock source for both CCP1 and ECCP1 modules 01 = Timer3 is the capture/compare clock source for ECCP1; Timer1 is the capture/compare clock source for CCP1 00 = Timer1 is the capture/compare clock source for both CCP1 and ECCP1 modules bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the device clock comes from Timer1/Timer3.) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. bit 1 TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Note 1: Thess bits and the ECCP1 module are available on PIC18F4682/4685 devices only. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 159 PIC18F2682/2685/4682/4685 14.1 Timer3 Operation cycle (FOSC/4). When the bit is set, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator if enabled. Timer3 can operate in one of three modes: * Timer * Synchronous Counter * Asynchronous Counter As with Timer1, the RC1/T1OSI and RC0/T1OSO/ T13CKI pins become inputs when the Timer1 oscillator is enabled. This means the values of TRISC<1:0> are ignored and the pins are read as `0'. The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared (= 0), Timer3 increments on every internal instruction FIGURE 14-1: TIMER3 BLOCK DIAGRAM Timer1 Oscillator 1 T1OSO/T13CKI 1 FOSC/4 Internal Clock T1OSI Synchronize Detect Prescaler 1, 2, 4, 8 2 Sleep Input TMR3CS T1OSCEN(1) 0 0 Timer3 On/Off T3CKPS1:T3CKPS0 T3SYNC TMR3ON Clear TMR3 CCP1/ECCP1 Special Event Trigger TCCPx TMR3L Set TMR3IF on Overflow TMR3 High Byte Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 14-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator Timer1 clock input 1 T1OSO/T13CKI 1 FOSC/4 Internal Clock T1OSI Synchronize Detect Prescaler 1, 2, 4, 8 0 0 2 Sleep Input T1OSCEN(1) TMR3CS Timer3 On/Off T3CKPS1:T3CKPS0 T3SYNC TMR3ON CCP1/ECCP1 Special Event Trigger Clear TMR3 TCCPx Set TMR3IF on Overflow TMR3 High Byte TMR3L 8 Read TMR1L Write TMR1L 8 8 TMR3H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39761B-page 160 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 14.2 Timer3 16-Bit Read/Write Mode 14.4 Timer3 Interrupt Timer3 can be configured for 16-bit reads and writes (see Figure 14-2). When the RD16 control bit (T3CON<7>) is set, the address for TMR3H is mapped to a buffer register for the high byte of Timer3. A read from TMR3L will load the contents of the high byte of Timer3 into the Timer3 High Byte Buffer register. This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in the interrupt flag bit, TMR3IF (PIR2<1>). This interrupt can be enabled or disabled by setting or clearing the Timer3 Interrupt Enable bit, TMR3IE (PIE2<1>). A write to the high byte of Timer3 must also take place through the TMR3H Buffer register. The Timer3 high byte is updated with the contents of TMR3H when a write occurs to TMR3L. This allows a user to write all 16 bits to both the high and low bytes of Timer3 at once. If the ECCP1 module is configured to generate a Special Event Trigger in Compare mode (ECCP1M3:ECCP1M0 = 1011), this signal will reset Timer3. It will also start an A/D conversion if the A/D module is enabled (see Section 15.3.4 "Special Event Trigger" for more information.). The high byte of Timer3 is not directly readable or writable in this mode. All reads and writes must take place through the Timer3 High Byte Buffer register. Writes to TMR3H do not clear the Timer3 prescaler. The prescaler is only cleared on writes to TMR3L. 14.3 Using the Timer1 Oscillator as the Timer3 Clock Source The Timer1 internal oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting the T1OSCEN (T1CON<3>) bit. To use it as the Timer3 clock source, the TMR3CS bit must also be set. As previously noted, this also configures Timer3 to increment on every rising edge of the oscillator source. 14.5 Resetting Timer3 Using the ECCP1 Special Event Trigger The module must be configured as either a timer or synchronous counter to take advantage of this feature. When used this way, the ECCPR1H:ECCPR1L register pair effectively becomes a period register for Timer3. If Timer3 is running in Asynchronous Counter mode, the Reset operation may not work. In the event that a write to Timer3 coincides with a Special Event Trigger from a CCP1 module, the write will take precedence. Note: The Special Event Triggers from the ECCP1 module will not set the TMR3IF interrupt flag bit (PIR2<1>). The Timer1 oscillator is described in Section 12.0 "Timer1 Module". TABLE 14-1: Name INTCON REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 52 Bit 6 GIE/GIEH PEIE/GIEL PIR2 OSCFIF CMIF(1) -- EEIF BCLIF HLVDIF TMR3IF ECCP1IF(1) PIE2 OSCFIE CMIE(1) -- EEIE BCLIE HLVDIE TMR3IE ECCP1IE(1) 52 IPR2 OSCFIP CMIP(1) -- EEIP BCLIP HLVDIP TMR3IP ECCP1IP(1) 51 TMR3L Timer3 Register, Low Byte TMR3H Timer3 Register, High Byte T1CON T3CON RD16 RD16 T1RUN 51 51 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC (1) T3ECCP1 (1) T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR1CS TMR1ON 50 TMR3CS TMR3ON 51 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Timer3 module. Note 1: These bits are unimplemented on PIC18F2682/2685 devices; always maintain these bits clear. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 161 PIC18F2682/2685/4682/4685 NOTES: DS39761B-page 162 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 15.0 CAPTURE/COMPARE/PWM (CCP1) MODULES PIC18F2682/2685 devices have one CCP1 module. PIC18F4682/4685 devices have two CCP1 (Capture/ Compare/PWM) modules. CCP1, discussed in this chapter, implements standard Capture, Compare and Pulse-Width Modulation (PWM) modes. ECCP1 implements an Enhanced PWM mode. The ECCP1 implementation is discussed in Section 16.0 "Enhanced Capture/Compare/PWM (ECCP1) Module". REGISTER 15-1: The CCP1 module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. For the sake of clarity, all CCP1 module operation in the following sections is described with respect to CCP1, but is equally applicable to ECCP1. Capture/ and Compare operations described in this chapter apply to all standard and Enhanced CCP1 modules. The operations of PWM mode, described in Section 15.4 "PWM Mode", apply to CCP1 only. CCP1CON: CAPTURE/COMPARE/PWM CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as `0' bit 5-4 DC1B1:DC1B0: CCP1 Module PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs (DC1B9:DC1B2) of the duty cycle are found in CCPR1L. bit 3-0 CCP1M3:CCP1M0: CCP1 Module Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCP1 module) 0001 = Reserved 0010 = Compare mode; toggle output on match (CCP1IF bit is set) 0011 = Reserved 0100 = Capture mode; every falling edge or CAN message received (time-stamp)(1) 0101 = Capture mode; every rising edge or CAN message received (time-stamp)(1) 0110 = Capture mode; every 4th rising edge or every 4th CAN message received (time-stamp)(1) 0111 = Capture mode; every 16th rising edge or every 16th CAN message received (time-stamp)(1) 1000 = Compare mode; initialize CCP1 pin low; on compare match, force CCP1 pin high (CCPIF bit is set) 1001 = Compare mode; initialize CCP pin high; on compare match, force CCP1 pin low (CCPIF bit is set) 1010 = Compare mode; generate software interrupt on compare match (CCP1IF bit is set, CCP1 pin reflects I/O state) 1011 = Compare mode; trigger special event; reset timer (TMR1 or TMR3, CCP1IF bit is set) 11xx = PWM mode Note 1: Selected by CANCAP (CIOCON<4>) bit; overrides the CCP1 input pin source. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 163 PIC18F2682/2685/4682/4685 15.1 TABLE 15-1: CCP1 Module Configuration Each Capture/Compare/PWM module is associated with a control register (CCP1CON or ECCP1CON) and a data register (CCPR1 or ECCPR1). The data register, in turn, is comprised of two 8-bit registers: CCPR1L or ECCPR1L (low byte) and CCPR1H or ECCPR1H (high byte). All registers are both readable and writable. 15.1.1 CCP1 MODULES AND TIMER RESOURCES The CCP1 modules utilize Timers 1, 2 or 3, depending on the mode selected. Timer1 and Timer3 are available to modules in Capture or Compare modes, while Timer2 is available for modules in PWM mode. TABLE 15-2: CCP1 MODE - TIMER RESOURCE CCP1/ECCP1 Mode Timer Resource Capture Compare PWM Timer1 or Timer3 Timer1 or Timer3 Timer2 The assignment of a particular timer to a module is determined by the Timer to CCP1/ECCP1 enable bits in the T3CON register (Register 14-1). Both modules may be active at any given time and may share the same timer resource if they are configured to operate in the same mode (Capture/Compare or PWM) at the same time. The interactions between the two modules are summarized in Figure 15-1 and Figure 15-2. INTERACTIONS BETWEEN CCP1 AND ECCP1 FOR TIMER RESOURCES CCP1 Mode ECCP1 Mode Interaction Capture Capture Each module can use TMR1 or TMR3 as the time base. Time base can be different for each CCP1. Capture Compare CCP1 can be configured for the Special Event Trigger to reset TMR1 or TMR3 (depending upon which time base is used). Automatic A/D conversions on trigger event can also be done. Operation of CCP1 could be affected if it is using the same timer as a time base. Compare Capture CCP1 can be configured for the Special Event Trigger to reset TMR1 or TMR3 (depending upon which time base is used). Operation of CCP1 could be affected if it is using the same timer as a time base. Compare Compare Either module can be configured for the Special Event Trigger to reset the time base. Automatic A/D conversions on ECCP1 trigger event can be done. Conflicts may occur if both modules are using the same time base. Capture PWM* None Compare PWM* None PWM* Capture None PWM* Compare None PWM* * PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt). Includes standard and Enhanced PWM operation. DS39761B-page 164 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 15.2 15.2.4 Capture Mode In Capture mode, the CCPR1H:CCPR1L (or ECCPR1H:ECCPR1L) register pair captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on the CCP1/ECCP1 pin (RC2 for 28/40/44-pin devices and RD4 for 40/44-pin devices). An event is defined as one of the following: * * * * every falling edge every rising edge every 4th rising edge every 16th rising edge The event is selected by the mode select bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit, CCP1IF (PIR1<2>), is set; it must be cleared in software. If another capture occurs before the value in the CCPR1 register pair is read, the old captured value is overwritten by the new captured value. 15.2.1 CCP1 PIN CONFIGURATION In Capture mode, the appropriate CCP1/ECCP1 pin should be configured as an input by setting the corresponding TRIS direction bit. Note: 15.2.2 If RC2/CCP1 or RD4/PSP4/ECCP1/P1A is configured as an output, a write to the port can cause a capture condition. TIMER1/TIMER3 MODE SELECTION The timers that are to be used with the capture feature (Timer1 and/or Timer3) must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation may not work. The timer to be used with each CCP1 module is selected in the T3CON register (see Section 15.1.1 "CCP1 Modules and Timer Resources"). 15.2.3 CCP1 PRESCALER There are four prescaler settings in Capture mode; they are specified as part of the operating mode selected by the mode select bits (CCP1M3:CCP1M0). Whenever the CCP1 module is turned off or the CCP1 module is not in Capture mode, the prescaler counter is cleared. This means that any Reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. Example 15-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt. 15.2.5 CAN MESSAGE TIME-STAMP The CAN capture event occurs when a message is received in any of the receive buffers. When configured, the CAN module provides the trigger to the CCP1 module to cause a capture event. This feature is provided to "time-stamp" the received CAN messages. This feature is enabled by setting the CANCAP bit of the CAN I/O Control register (CIOCON<4>). The message receive signal from the CAN module then takes the place of the events on the RC2/CCP1 pin. If this feature is selected, then four different capture options for CCP1M<3:0> are available: * 0100 - every time a CAN message is received * 0101 - every time a CAN message is received * 0110 - every 4th time a CAN message is received * 0111 - Capture mode, every 16th time a CAN message is received EXAMPLE 15-1: SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCP1IE or ECCP1IE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCP1IF or ECCP1IF, should also be cleared following any such change in operating mode. (c) 2007 Microchip Technology Inc. CLRF MOVLW CCP1CON NEW_CAPT_PS MOVWF CCP1CON Preliminary CHANGING BETWEEN CAPTURE PRESCALERS ; ; ; ; ; ; Turn CCP1 module off Load WREG with the new prescaler mode value and CCP1 ON Load CCP1CON with this value DS39761B-page 165 PIC18F2682/2685/4682/4685 FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM TMR3H TMR3L Set CCP1IF T3ECCP1 CCP1 pin Prescaler / 1, 4, 16 and Edge Detect CCPR1H T3ECCP1 4 CCP1CON<3:0> Q1:Q4 ECCP1CON<3:0> 4 TMR3 Enable CCPR1L TMR1 Enable TMR1H TMR1L TMR3H TMR3L Set ECCP1IF 4 T3CCP1 T3ECCP1 TMR3 Enable ECCP1 pin Prescaler / 1, 4, 16 and Edge Detect ECCPR1H ECCPR1L TMR1 Enable T3ECCP1 T3CCP1 DS39761B-page 166 Preliminary TMR1H TMR1L (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 15.3 15.3.2 Compare Mode TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPR1 register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCP1 pin can be: Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode if the CCP1 module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. * * * * 15.3.3 driven high driven low toggled (high-to-low or low-to-high) remain unchanged (that is, reflects the state of the I/O latch) When the Generate Software Interrupt mode is chosen (CCP1M3:CCP1M0 = 1010), the CCP1 pin is not affected. Only a CCP1 interrupt is generated, if enabled and the CCP1IE bit is set. The action on the pin is based on the value of the mode select bits (CCP1M3:CCP1M0). At the same time, the interrupt flag bit, CCP1IF, is set. 15.3.1 CCP1 PIN CONFIGURATION The user must configure the CCP1 (ECCP1) pin as an output by clearing the appropriate TRIS bit. Note: Clearing the CCP1CON register will force the RC2 compare output latch to the default low level. This is not the PORTC I/O data latch. FIGURE 15-2: SOFTWARE INTERRUPT MODE 15.3.4 SPECIAL EVENT TRIGGER Both CCP1 modules are equipped with a Special Event Trigger. This is an internal hardware signal generated in Compare mode to trigger actions by other modules. The Special Event Trigger is enabled by selecting the Compare Special Event Trigger mode (CCP1M3:CCP1M0 = 1011). For either the CCP1/ECCP1 module, the Special Event Trigger resets the timer register pair for whichever timer resource is currently assigned as the module's time base. This allows the CCPR1 (ECCPR1) registers to serve as a programmable period register for either timer. COMPARE MODE OPERATION BLOCK DIAGRAM CCPR1H Special Event Trigger (Timer1 Reset) Set CCP1IF CCPR1L CCP1 pin Comparator Compare Match Output Logic S Q R TRIS Output Enable 4 CCP1CON<3:0> 0 TMR1H TMR1L 0 1 TMR3H TMR3L 1 Special Event Trigger (Timer1/Timer3 Reset, A/D Trigger) T3CCP1 T3ECCP1 Set CCP1IF Comparator ECCPR1H ECCP1 pin Compare Match Output Logic 4 ECCPR1L S Q R TRIS Output Enable ECCP1CON<3:0> (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 167 PIC18F2682/2685/4682/4685 TABLE 15-3: Name REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Bit 7 Reset Values on page Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 IPEN SBOREN(2) -- RI TO PD POR BOR 50 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 INTCON RCON (1) -- EEIP BCLIP HLVDIP -- EEIF BCLIF HLVDIF IPR2 OSCFIP CMIP PIR2 OSCFIF CMIF(1) OSCFIE CMIE(1) PIE2 -- EEIE BCLIE HLVDIE TMR3IP ECCP1IP (1) 52 TMR3IF ECCP1IF(1) 52 TMR3IE ECCP1IE(1) 51 TRISB PORTB Data Direction Register TRISC PORTC Data Direction Register 52 TMR1L Timer1 Register Low Byte 50 TMR1H Timer1 Register High Byte 50 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN TMR3H Timer3 Register High Byte TMR3L Timer3 Register Low Byte T3CON RD16 52 Capture/Compare/PWM Register 1 Low Byte Capture/Compare/PWM Register 1 High Byte -- TMR1ON 50 51 T3ECCP1(1) T3CKPS1 T3CKPS0 T3CCP1(1) CCPR1H -- TMR1CS 51 CCPR1L CCP1CON T1SYNC DC1B1 DC1B0 T3SYNC TMR3CS TMR3ON 51 51 51 CCP1M3 CCP1M2 CCP1M1 CCP1M0 51 ECCPR1L(1) Enhanced Capture/Compare/PWM Register 1 Low Byte 51 ECCPR1H(1) Enhanced Capture/Compare/PWM Register 1 High Byte 51 ECCP1CON(1) EPWM1M1 EPWM1M0 Legend: Note 1: 2: EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 51 -- = unimplemented, read as `0'. Shaded cells are not used by Capture and Compare, Timer1 or Timer3. These bits or registers are available on PIC18F4682/4685 devices only. The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as `0'. DS39761B-page 168 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 15.4 FIGURE 15-4: PWM Mode PWM OUTPUT Period In Pulse-Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with a PORTB or PORTC data latch, the appropriate TRIS bit must be cleared to make the CCP1 pin an output. Duty Cycle TMR2 = PR2 Note: Clearing the CCP1CON register will force the RC2 output latch to the default low level. This is not the PORTC I/O data latch. Figure 15-3 shows a simplified block diagram of the CCP1 module in PWM mode. For a step-by-step procedure on how to set up the CCP1 module for PWM operation, see Section 15.4.4 "Setup for PWM Operation". FIGURE 15-3: The PWM period is specified by writing to the PR2 (PR4) register. The PWM period can be calculated using the following formula. EQUATION 15-1: PWM Period = [(PR2) + 1] * 4 * TOSC * (TMR2 Prescale Value) When TMR1 (TMR3) is equal to PR2 (PR4), the following three events occur on the next increment cycle: CCPR1H (Slave) Comparator R (Note 1) Q RC2/CCP1 PORTC<2> S * TMR2 is cleared * The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set) * The PWM duty cycle is latched from CCPR1L into CCPR1H Note: TRISC<2> Comparator Note 1: PWM PERIOD PWM frequency is defined as 1/[PWM period]. CCP1CON<5:4> CCPR1L PR2 15.4.1 SIMPLIFIED PWM BLOCK DIAGRAM Duty Cycle Registers TMR2 TMR2 = Duty Cycle TMR2 = PR2 Clear Timer, CCP1 pin and latch D.C. 15.4.2 The 8-bit TMR2 value is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. A PWM output (Figure 15-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/ period). The Timer2 postscaler (see Section 13.0 "Timer2 Module") is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time. EQUATION 15-2: PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) * TOSC * (TMR2 Prescale Value) CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 169 PIC18F2682/2685/4682/4685 The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. EQUATION 15-3: PWM Resolution (max) = log FOSC FPWM log(2) When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. Note: The maximum PWM resolution (bits) for a given PWM frequency is given by the equation. TABLE 15-4: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) 15.4.3 bits 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz 16 4 1 1 1 1 FFh FFh FFh 3Fh 1Fh 17h 14 12 10 8 7 6.58 PWM AUTO-SHUTDOWN (ECCP1 ONLY) 15.4.4 The PWM auto-shutdown features of the Enhanced CCP1 module are available to ECCP1 in PIC18F4682/ 4685 (40/44-pin) devices. The operation of this feature is discussed in detail in Section 16.4.7 "Enhanced PWM Auto-Shutdown". Auto-shutdown features are not available for CCP1. The following steps should be taken when configuring the CCP1 module for PWM operation: 1. 2. 3. 4. 5. DS39761B-page 170 SETUP FOR PWM OPERATION Preliminary Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the appropriate TRIS bit. Set the TMR2 prescale value, then enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation. (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 15-5: Name REGISTERS ASSOCIATED WITH PWM AND TIMER2 Bit 7 INTCON RCON Reset Values on page Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 IPEN SBOREN(2) -- RI TO PD POR BOR 50 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 TRISB PORTB Data Direction Register TRISC PORTC Data Direction Register 52 TMR2 Timer2 Register 50 PR2 Timer2 Period Register -- T2CON 52 50 T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON CCPR1L Capture/Compare/PWM Register 1 Low Byte CCPR1H Capture/Compare/PWM Register 1 High Byte -- CCP1CON -- DC1B1 DC1B0 T2CKPS1 T2CKPS0 50 51 51 CCP1M3 CCP1M2 CCP1M1 CCP1M0 51 ECCPR1L(1) Enhanced Capture/Compare/PWM Register 1 Low Byte 51 ECCPR1H(1) Enhanced Capture/Compare/PWM Register 1 High Byte 51 ECCP1CON(1) EPWM1M1 EPWM1M0 Legend: Note 1: 2: EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 51 -- = unimplemented, read as `0'. Shaded cells are not used by PWM or Timer2. These bits or registers are available on PIC18F4682/4685 devices only. The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as `0'. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 171 PIC18F2682/2685/4682/4685 NOTES: DS39761B-page 172 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 16.0 ENHANCED CAPTURE/ COMPARE/PWM (ECCP1) MODULE Note: The ECCP1 module is implemented only in PIC18F4682/4685 (40/44-pin) devices. In PIC18F4682/4685 devices, ECCP1 is implemented as a standard CCP1 module with Enhanced PWM capabilities. These include the provision for 2 or 4 output channels, user-selectable polarity, dead-band control and automatic shutdown and restart. The REGISTER 16-1: enhanced features are discussed in detail in Section 16.4 "Enhanced PWM Mode". Capture, Compare and single output PWM functions of the ECCP1 module are the same as described for the standard CCP1 module. The control register for the Enhanced CCP1 module is shown in Register 16-1. It differs from the CCP1CON register in the PIC18F2682/2685 devices in that the two Most Significant bits are implemented to control PWM functionality. ECCP1CON: ENHANCED CAPTURE/COMPARE/PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-6 EPWM1M1:EPWM1M0: Enhanced PWM Output Configuration bits If ECCP1M3:ECCP1M2 = 00, 01, 10: xx = P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins If ECCP1M3:ECCP1M2 = 11: 00 = Single output: P1A modulated; P1B, P1C, P1D assigned as port pins 01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive 10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive bit 5-4 EDC1B1:EDC1B0: ECCP1 Module PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in ECCPR1L. bit 3-0 ECCP1M3:ECCP1M0: Enhanced CCP1 Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCP1 module) 0001 = Reserved 0010 = Compare mode; toggle output on match 0011 = Reserved 0100 = Capture mode; every falling edge 0101 = Capture mode; every rising edge 0110 = Capture mode; every 4th rising edge 0111 = Capture mode; every 16th rising edge 1000 = Compare mode; initialize ECCP1 pin low; set output on compare match (set ECCP1IF) 1001 = Compare mode; initialize ECCP1 pin high; clear output on compare match (set ECCP1IF) 1010 = Compare mode; generate software interrupt only; ECCP1 pin reverts to I/O state 1011 = Compare mode; trigger special event (ECCP1 resets TMR1 or TMR3, sets ECCP1IF bit and starts the A/D conversion on ECCP1 match) 1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high 1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 173 PIC18F2682/2685/4682/4685 In addition to the expanded range of modes available through the ECCP1CON register, the ECCP1 module has two additional registers associated with Enhanced PWM operation and auto-shutdown features. They are: * ECCP1DEL (Dead-Band Delay) * ECCP1AS (Auto-Shutdown Configuration) 16.1 ECCP1 Outputs and Configuration The Enhanced CCP1 module may have up to four PWM outputs, depending on the selected operating mode. These outputs, designated P1A through P1D, are multiplexed with I/O pins on PORTD. The outputs that are active depend on the ECCP1 operating mode selected. The pin assignments are summarized in Table 16-1. To configure the I/O pins as PWM outputs, the proper PWM mode must be selected by setting the EPWM1M1:EPWM1M0 and ECCP1M3:ECCP1M0 bits. The appropriate TRISD direction bits for the port pins must also be set as outputs. 16.1.1 ECCP1 MODULES AND TIMER RESOURCES Like the standard CCP1 modules, the ECCP1 module can utilize Timers 1, 2 or 3, depending on the mode selected. Timer1 and Timer3 are available for modules in Capture or Compare modes, while Timer2 is available for modules in PWM mode. Interactions between the standard and Enhanced CCP1 modules are identical to those described for standard CCP1 modules. Additional details on timer resources are provided in Section 15.1.1 "CCP1 Modules and Timer Resources". TABLE 16-1: 16.2 Capture and Compare Modes Except for the operation of the Special Event Trigger discussed below, the Capture and Compare modes of the ECCP1 module are identical in operation to that of CCP1. These are discussed in detail in Section 15.2 "Capture Mode" and Section 15.3 "Compare Mode". 16.2.1 SPECIAL EVENT TRIGGER The Special Event Trigger output of ECCP1 resets the TMR1 or TMR3 register pair, depending on which timer resource is currently selected. This allows the ECCP1 register to effectively be a 16-bit programmable period register for Timer1 or Timer3. The Special Event Trigger for ECCP1 can also start an A/D conversion. In order to start the conversion, the A/D converter must be previously enabled. 16.3 Standard PWM Mode When configured in Single Output mode, the ECCP1 module functions identically to the standard CCP1 module in PWM mode, as described in Section 15.4 "PWM Mode". This is also sometimes referred to as "Compatible CCP1" mode, as in Table 16-1. Note: When setting up single output PWM operations, users are free to use either of the processes described in Section 15.4.4 "Setup for PWM Operation" or Section 16.4.9 "Setup for PWM Operation". The latter is more generic but will work for either single or multi-output PWM. PIN ASSIGNMENTS FOR VARIOUS ECCP1 MODES ECCP1 Mode CCP1CON Configuration RD4 RD5 RD6 RD7 All PIC18F4682/4685 Devices: Compatible CCP1 00xx 11xx ECCP1 RD5/PSP5 RD6/PSP6 RD7/PSP7 Dual PWM 10xx 11xx P1A P1B RD6/PSP6 RD7/PSP7 Quad PWM x1xx 11xx P1A P1B P1C P1D Legend: x = Don't care. Shaded cells indicate pin assignments not used by ECCP1 in a given mode. DS39761B-page 174 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 16.4 16.4.1 Enhanced PWM Mode PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following equation. The Enhanced PWM mode provides additional PWM output options for a broader range of control applications. The module is a backward compatible version of the standard CCP1 module and offers up to four outputs, designated P1A through P1D. Users are also able to select the polarity of the signal (either active-high or active-low). The module's output mode and polarity are configured by setting the EPWM1M1:EPWM1M0 and ECCP1M3:ECCP1M0 bits of the ECCP1CON register. EQUATION 16-1: PWM Period = PWM frequency is defined as 1/[PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: Figure 16-1 shows a simplified block diagram of PWM operation. All control registers are double-buffered and are loaded at the beginning of a new PWM cycle (the period boundary when Timer2 resets) in order to prevent glitches on any of the outputs. The exception is the PWM Dead-Band Delay register, ECCP1DEL, which is loaded at either the duty cycle boundary or the boundary period (whichever comes first). Because of the buffering, the module waits until the assigned timer resets instead of starting immediately. This means that Enhanced PWM waveforms do not exactly match the standard PWM waveforms, but are instead offset by one full instruction cycle (4 TOSC). * TMR2 is cleared * The ECCP1 pin is set (if PWM duty cycle = 0%, the ECCP1 pin will not be set) * The PWM duty cycle is copied from ECCPR1L into ECCPR1H Note: As before, the user must manually configure the appropriate TRIS bits for output. FIGURE 16-1: [(PR2) + 1] * 4 * TOSC * (TMR2 Prescale Value) The Timer2 postscaler (see Section 13.0 "Timer2 Module") is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE ECCP1CON<5:4> Duty Cycle Registers EPWM1M<1:0> 2 ECCP1M<3:0> 4 ECCPR1L ECCP1/P1A ECCP1/P1A TRISD<4> ECCPR1H (Slave) P1B P1B Comparator R Q Output Controller TRISD<5> P1C TMR2 (Note 1) S P1D Comparator PR2 P1C TRISD<6> Clear Timer, set ECCP1 pin and latch D.C. P1D TRISD<7> ECCP1DEL Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 175 PIC18F2682/2685/4682/4685 16.4.2 PWM DUTY CYCLE EQUATION 16-3: The PWM duty cycle is specified by writing to the ECCPR1L register and to the ECCP1CON<5:4> bits. Up to 10-bit resolution is available. The ECCPR1L contains the eight MSbs and the ECCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by ECCPR1L:ECCP1CON<5:4>. The PWM duty cycle is calculated by the following equation. log FOSC FPWM PWM Resolution (max) = log(2) ( Note: EQUATION 16-2: 16.4.3 PWM Duty Cycle = (ECCPR1L:ECCP1CON<5:4> * TOSC * (TMR2 Prescale Value) ECCPR1L and ECCP1CON<5:4> can be written to at any time, but the duty cycle value is not copied into ECCPR1H until a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, ECCPR1H is a read-only register. The ECCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the ECCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or two bits of the TMR2 prescaler, the ECCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the following equation. TABLE 16-2: ) bits If the PWM duty cycle value is longer than the PWM period, the ECCP1 pin will not be cleared. PWM OUTPUT CONFIGURATIONS The EPWM1M1:EPWM1M0 bits in the ECCP1CON register allow one of four configurations: * * * * Single Output Half-Bridge Output Full-Bridge Output, Forward mode Full-Bridge Output, Reverse mode The Single Output mode is the standard PWM mode discussed in Section 16.4 "Enhanced PWM Mode". The Half-Bridge and Full-Bridge Output modes are covered in detail in the sections that follow. The general relationship of the outputs in all configurations is summarized in Figure 16-2. EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) DS39761B-page 176 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz 16 4 1 1 1 1 FFh FFh FFh 3Fh 1Fh 17h 10 10 10 8 7 6.58 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 FIGURE 16-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) 0 ECCP1CON <7:6> 00 (Single Output) PR2 + 1 Duty Cycle SIGNAL Period P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive FIGURE 16-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) 0 ECCP1CON <7:6> 00 (Single Output) PR2 + 1 Duty Cycle SIGNAL Period P1A Modulated P1A Modulated 10 (Half-Bridge) Delay(1) Delay(1) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: * Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) * Duty Cycle = TOSC * (ECCPR1L<7:0>:ECCP1CON<5:4>) * (TMR2 Prescale Value) * Delay = 4 * TOSC * (ECCP1DEL<6:0>) Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 16.4.6 "Programmable Dead-Band Delay"). (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 177 PIC18F2682/2685/4682/4685 16.4.4 HALF-BRIDGE MODE FIGURE 16-4: In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complementary PWM output signal is output on the P1B pin (Figure 16-4). This mode can be used for half-bridge applications, as shown in Figure 16-5, or for full-bridge applications where four power switches are being modulated with two PWM signals. HALF-BRIDGE PWM OUTPUT Period Period Duty Cycle P1A(2) td td P1B(2) In Half-Bridge Output mode, the programmable deadband delay can be used to prevent shoot-through current in half-bridge power devices. The value of bits, PDC6:PDC0, sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section 16.4.6 "Programmable Dead-Band Delay" for more details of the dead-band delay operations. (1) (1) (1) td = Dead-Band Delay Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. Since the P1A and P1B outputs are multiplexed with the PORTD<4> and PORTD<5> data latches, the TRISD<4> and TRISD<5> bits must be cleared to configure P1A and P1B as outputs. FIGURE 16-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS V+ Standard Half-Bridge Circuit ("Push-Pull") PIC18F268X/468X FET Driver + V - P1A Load FET Driver + V - P1B VHalf-Bridge Output Driving a Full-Bridge Circuit V+ PIC18F268X/468X FET Driver FET Driver P1A FET Driver Load FET Driver P1B V- DS39761B-page 178 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 16.4.5 FULL-BRIDGE MODE In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin P1A is continuously active and pin P1D is modulated. In the Reverse mode, pin P1C is continuously active and pin P1B is modulated. These are illustrated in Figure 16-6. FIGURE 16-6: P1A, P1B, P1C and P1D outputs are multiplexed with the PORTD<4>, PORTD<5>, PORTD<6> and PORTD<7> data latches. The TRISD<4>, TRISD<5>, TRISD<6> and TRISD<7> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs. FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A(2) Duty Cycle P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Duty Cycle P1A(2) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 179 PIC18F2682/2685/4682/4685 FIGURE 16-7: EXAMPLE OF FULL-BRIDGE APPLICATION V+ PIC18F268X/468X FET Driver QA QC FET Driver P1A Load P1B FET Driver P1C FET Driver QB QD VP1D 16.4.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the EPWM1M1 bit in the ECCP1CON register allows the user to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle. Just before the end of the current PWM period, the modulated outputs (P1B and P1D) are placed in their inactive state, while the unmodulated outputs (P1A and P1C) are switched to drive in the opposite direction. This occurs in a time interval of (4 TOSC * (Timer2 Prescale Value)) before the next PWM period begins. The Timer2 prescaler will either be 1, 4 or 16, depending on the value of the T2CKPS bits (T2CON<1:0>). During the interval from the switch of the unmodulated outputs to the beginning of the next period, the modulated outputs (P1B and P1D) remain inactive. This relationship is shown in Figure 16-8. Note that in the Full-Bridge Output mode, the ECCP1 module does not provide any dead-band delay. In general, since only one output is modulated at all times, dead-band delay is not required. However, there is a situation where a dead-band delay might be required. This situation occurs when both of the following conditions are true: 1. 2. Figure 16-9 shows an example where the PWM direction changes from forward to reverse at a near 100% duty cycle. At time t1, the outputs P1A and P1D become inactive, while output P1C becomes active. In this example, since the turn-off time of the power devices is longer than the turn-on time, a shoot-through current may flow through power devices, QC and QD (see Figure 16-7), for the duration of `t'. The same phenomenon will occur to power devices, QA and QB, for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, one of the following requirements must be met: 1. 2. Reduce PWM for a PWM period before changing directions. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. DS39761B-page 180 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 FIGURE 16-8: PWM DIRECTION CHANGE Period(1) SIGNAL Period P1A (Active-High) P1B (Active-High) DC P1C (Active-High) (Note 2) P1D (Active-High) DC Note 1: 2: The direction bit in the ECCP1 Control register (ECCP1CON<7>) is written any time during the PWM cycle. When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals are inactive at this time. FIGURE 16-9: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A(1) P1B(1) DC P1C(1) P1D(1) DC tON(2) External Switch C(1) tOFF(3) External Switch D(1) Potential Shoot-Through Current(1) Note 1: 2: 3: t = tOFF - tON(2,3) All signals are shown as active-high. tON is the turn-on delay of power switch QC and its driver. tOFF is the turn-off delay of power switch QD and its driver. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 181 PIC18F2682/2685/4682/4685 16.4.6 Note: PROGRAMMABLE DEAD-BAND DELAY Programmable dead-band delay is not implemented in PIC18F2682/2685 devices with standard CCP1 modules. In half-bridge applications where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period of time until one switch completely turns off. During this brief interval, a very high current (shoot-through current) may flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shootthrough current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. In the Half-Bridge Output mode, a digitally programmable dead-band delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure 16-4 for illustration. Bits PDC6:PDC0 of the ECCP1DEL register (Register 16-2) set the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). These bits are not available on PIC18F2682/2685 devices, as the standard CCP1 module does not support half-bridge operation. 16.4.7 ENHANCED PWM AUTO-SHUTDOWN When the ECCP1 is programmed for any of the Enhanced PWM modes, the active output pins may be configured for auto-shutdown. Auto-shutdown immediately places the Enhanced PWM output pins into a defined shutdown state when a shutdown event occurs. REGISTER 16-2: A shutdown event can be caused by either of the comparator modules, a low level on the RB0/INT0/ FLT0/AN10 pin, or any combination of these three sources. The comparators may be used to monitor a voltage input proportional to a current being monitored in the bridge circuit. If the voltage exceeds a threshold, the comparator switches state and triggers a shutdown. Alternatively, a digital signal on the INT0 pin can also trigger a shutdown. The auto-shutdown feature can be disabled by not selecting any auto-shutdown sources. The auto-shutdown sources to be used are selected using the ECCPAS2:ECCPAS0 bits (bits<6:4> of the ECCP1AS register). When a shutdown occurs, the output pins are asynchronously placed in their shutdown states, specified by the PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits (ECCP1AS3:ECCP1AS0). Each pin pair (P1A/P1C and P1B/P1D) may be set to drive high, drive low or be tri-stated (not driving). The ECCPASE bit (ECCP1AS<7>) is also set to hold the Enhanced PWM outputs in their shutdown states. The ECCPASE bit is set by hardware when a shutdown event occurs. If automatic restarts are not enabled, the ECCPASE bit is cleared by firmware when the cause of the shutdown clears. If automatic restarts are enabled, the ECCPASE bit is automatically cleared when the cause of the auto-shutdown has cleared. If the ECCPASE bit is set when a PWM period begins, the PWM outputs remain in their shutdown state for that entire PWM period. When the ECCPASE bit is cleared, the PWM outputs will return to normal operation at the beginning of the next PWM period. Note: Writing to the ECCPASE bit is disabled while a shutdown condition is active. ECCP1DEL: PWM DEAD-BAND DELAY REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM bit 6-0 PDC6:PDC0: PWM Delay Count bits Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for a PWM signal to transition to active. Note 1: This register is available on PIC18F4682/4685 devices only. DS39761B-page 182 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 16-3: ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONFIGURATION REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 ECCPASE: ECCP1 Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP1 outputs are in shutdown state 0 = ECCP1 outputs are operating bit 6-4 ECCPAS2:ECCPAS0: ECCP1 Auto-Shutdown Source Select bits 111 = RB00 or Comparator 1 or Comparator 2 110 = RB0 or Comparator 2 101 = RB0 or Comparator 1 100 = RB0 011 = Either Comparator 1 or 2 010 = Comparator 2 output 001 = Comparator 1 output 000 = Auto-shutdown is disabled bit 3-2 PSSAC1:PSSAC0: Pins A and C Shutdown State Control bits 1x = Pins A and C tri-state (PIC18F4682/4685 devices) 01 = Drive Pins A and C to `1' 00 = Drive Pins A and C to `0' bit 1-0 PSSBD1:PSSBD0: Pins B and D Shutdown State Control bits 1x = Pins B and D tri-state 01 = Drive Pins B and D to `1' 00 = Drive Pins B and D to `0' Note 1: This register is available on PIC18F4682/4685 devices only. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 183 PIC18F2682/2685/4682/4685 16.4.7.1 Auto-Shutdown and Auto-Restart 16.4.8 The auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the PRSEN bit of the ECCP1DEL register (ECCP1DEL<7>). In Shutdown mode with PRSEN = 1 (Figure 16-10), the ECCPASE bit will remain set for as long as the cause of the shutdown continues. When the shutdown condition clears, the ECCPASE bit is cleared. If PRSEN = 0 (Figure 16-11), once a shutdown condition occurs, the ECCPASE bit will remain set until it is cleared by firmware. Once ECCPASE is cleared, the Enhanced PWM will resume at the beginning of the next PWM period. Note: Writing to the ECCPASE bit is disabled while a shutdown condition is active. Independent of the PRSEN bit setting, if the autoshutdown source is one of the comparators, the shutdown condition is a level. The ECCPASE bit cannot be cleared as long as the cause of the shutdown persists. The Auto-Shutdown mode can be forced by writing a `1' to the ECCPASE bit. FIGURE 16-10: START-UP CONSIDERATIONS When the ECCP1 module is used in the PWM mode, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. When the microcontroller is released from Reset, all of the I/O pins are in the high-impedance state. The external circuits must keep the power switch devices in the OFF state until the microcontroller drives the I/O pins with the proper signal levels, or activates the PWM output(s). The ECCP1M1:ECCP1M0 bits (ECCP1CON<1:0>) allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (P1A/P1C and P1B/P1D). The PWM output polarities must be selected before the PWM pins are configured as outputs. Changing the polarity configuration while the PWM pins are configured as outputs is not recommended, since it may result in damage to the application circuits. The P1A, P1B, P1C and P1D output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pins for output at the same time as the ECCP1 module may cause damage to the application circuit. The ECCP1 module must be enabled in the proper output mode and complete a full PWM cycle before configuring the PWM pins as outputs. The completion of a full PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED) PWM Period Shutdown Event ECCPASE bit PWM Activity Normal PWM Start of PWM Period FIGURE 16-11: Shutdown Event Occurs Shutdown Event Clears PWM Resumes PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED) PWM Period Shutdown Event ECCPASE bit PWM Activity Normal PWM Start of PWM Period DS39761B-page 184 Shutdown Event Occurs Preliminary ECCPASE Cleared by Shutdown Firmware PWM Event Clears Resumes (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 16.4.9 SETUP FOR PWM OPERATION 16.4.10 The following steps should be taken when configuring the ECCP1 module for PWM operation: 1. 2. 3. 4. 5. 6. 7. 8. 9. Configure the PWM pins, P1A and P1B (and P1C and P1D, if used), as inputs by setting the corresponding TRIS bits. Set the PWM period by loading the PR2 register. Configure the ECCP1 module for the desired PWM mode and configuration by loading the ECCP1CON register with the appropriate values: * Select one of the available output configurations and direction with the EPWM1M1:EPWM1M0 bits. * Select the polarities of the PWM output signals with the ECCP1M3:ECCP1M0 bits. Set the PWM duty cycle by loading the ECCPR1L register and ECCP1CON<5:4> bits. For Half-Bridge Output mode, set the deadband delay by loading ECCP1DEL<6:0> with the appropriate value. If auto-shutdown operation is required, load the ECCP1AS register: * Select the auto-shutdown sources using the ECCPAS2:ECCPAS0 bits. * Select the shutdown states of the PWM output pins using PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits. * Set the ECCPASE bit (ECCP1AS<7>). * Configure the comparators using the CMCON register. * Configure the comparator inputs as analog inputs. If auto-restart operation is required, set the PRSEN bit (ECCP1DEL<7>). Configure and start TMR2: * Clear the TMR2 interrupt flag bit by clearing the TMR2IF bit (PIR1<1>). * Set the TMR2 prescale value by loading the T2CKPS bits (T2CON<1:0>). * Enable Timer2 by setting the TMR2ON bit (T2CON<2>). Enable PWM outputs after a new PWM cycle has started: * Wait until TMRx overflows (TMRxIF bit is set). * Enable the ECCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. * Clear the ECCPASE bit (ECCP1AS<7>). (c) 2007 Microchip Technology Inc. EFFECTS OF A RESET Both Power-on Reset and subsequent Resets will force all ports to Input mode and the ECCP1 registers to their Reset states. This forces the Enhanced CCP1 module to reset to a state compatible with the standard CCP1 module. Preliminary DS39761B-page 185 PIC18F2682/2685/4682/4685 TABLE 16-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 IPEN SBOREN(3) -- RI TO PD POR BOR 50 IPR1 PSPIP (2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 PIR1 PSPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR2 OSCFIP CMIP(2) -- EEIP BCLIP HLVDIP TMR3IP ECCP1IP(2) 51 PIR2 OSCFIF CMIF (2) -- EEIF BCLIF HLVDIF TMR3IF ECCP1IF(2) 52 PIE2 OSCFIE CMIE(2) -- EEIE BCLIE HLVDIE TMR3IE ECCP1IE(2) 52 Name Bit 7 INTCON RCON TRISB PORTB Data Direction Register 52 TRISC PORTC Data Direction Register 52 (1) TRISD PORTD Data Direction Register 52 TMR1L Timer1 Register Low Byte 50 TMR1H Timer1 Register High Byte 50 T1CON RD16 TMR2 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON Timer2 Register -- T2CON 50 50 T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 50 PR2 Timer2 Period Register 50 TMR3L Timer3 Register Low Byte 51 TMR3H Timer3 Register High Byte RD16 T3CON 51 T3ECCP1(2) T3CKPS1 T3CKPS0 T3CCP1(2) T3SYNC TMR3CS TMR3ON 51 ECCPR1L(1) Enhanced Capture/Compare/PWM Register 1 Low Byte 51 ECCPR1H(1) Enhanced Capture/Compare/PWM Register 1 High Byte 51 ECCP1CON(1) EPWM1M1 EPWM1M0 ECCP1AS(1) ECCPASE ECCPAS2 ECCP1DEL(1) PRSEN PDC6 Legend: Note 1: 2: 3: EDC1B1 EDC1B0 ECCPAS1 ECCPAS0 PDC5 PDC4 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 51 PSSAC1 PSSAC0 PSSBD1 PSSBD0 51 PDC3 PDC2 PDC1 PDC0 51 -- = unimplemented, read as `0'. Shaded cells are not used during ECCP1 operation. These registers are available on PIC18F4682/4685 devices only. These bits are available on PIC18F4682/4685 and reserved on PIC18F2682/2685 devices. The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as `0'. DS39761B-page 186 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 17.0 17.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE 17.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of SPI are supported. To accomplish communication, typically three pins are used: Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2C) - Full Master mode - Slave mode (with general address call) * Serial Data Out (SDO) - RC5/SDO * Serial Data In (SDI) - RC4/SDI/SDA * Serial Clock (SCK) - RC3/SCK/SCL Additionally, a fourth pin may be used when in a Slave mode of operation: * Slave Select (SS) - RA5/AN4/SS/HLVDIN Figure 17-1 shows the block diagram of the MSSP module when operating in SPI mode. FIGURE 17-1: MSSP BLOCK DIAGRAM (SPI MODE) The I2C interface supports the following modes in hardware: Internal Data Bus * Master mode * Multi-Master mode * Slave mode 17.2 Read Write SSPBUF reg Control Registers SSPSR reg The MSSP module has three associated registers. These include a status register (SSPSTAT) and two control registers (SSPCON1 and SSPCON2). The use of these registers and their individual Configuration bits differ significantly depending on whether the MSSP module is operating in SPI or I2C mode. RC4/SDI/SDA bit 0 Shift Clock RC5/SDO Additional details are provided under the individual sections. SS Control Enable RA5/AN4/SS/HLVDIN Edge Select 2 Clock Select SSPM3:SSPM0 SMP:CKE 4 TMR2 Output 2 2 Edge Select Prescaler TOSC 4, 16, 64 ( RC3/SCK/SCL ) Data to TX/RX in SSPSR TRIS bit (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 187 PIC18F2682/2685/4682/4685 17.3.1 REGISTERS SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. The MSSP module has four registers for SPI mode operation. These are: In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. * MSSP Control Register 1 (SSPCON1) * MSSP Status Register (SSPSTAT) * Serial Receive/Transmit Buffer Register (SSPBUF) * MSSP Shift Register (SSPSR) - Not directly accessible During transmission, the SSPBUF is not doublebuffered. A write to SSPBUF will write to both SSPBUF and SSPSR. SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation. The SSPCON1 register is readable and writable. The lower 6 bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write. REGISTER 17-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Select bit 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state Polarity of clock state is set by the CKP bit (SSPCON1<4>). bit 5 D/A: Data/Address bit Used in I2C mode only. bit 4 P: Stop bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write Information bit Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty DS39761B-page 188 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 WCOL SSPOV(1) R/W-0 (2) SSPEN R/W-0 CKP R/W-0 SSPM3 (3) R/W-0 SSPM2 (3) R/W-0 SSPM1 (3) R/W-0 SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) SPI Slave mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow bit 5 SSPEN: Master Synchronous Serial Port Enable bit(2) 1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins(2) bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits(3) 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note 1: 2: 3: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. When enabled, these pins must be properly configured as input or output. Bit combinations not specifically listed here are either reserved or implemented in I2CTM mode only. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 189 PIC18F2682/2685/4682/4685 17.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: * * * * Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Data Input Sample Phase (middle or end of data output time) * Clock Edge (output data on rising/falling edge of SCK) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only) The MSSP module consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSPBUF register. Then, the Buffer Full detect bit, BF (SSPSTAT<0>) and the interrupt flag bit, SSPIF, are set. This double-buffering of the received data (SSPBUF) allows the next byte to start reception before EXAMPLE 17-1: LOOP reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data will be ignored and the write collision detect bit, WCOL (SSPCON1<7>), will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. The Buffer Full bit, BF (SSPSTAT<0>), indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 17-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP Status register (SSPSTAT) indicates the various status conditions. LOADING THE SSPBUF (SSPSR) REGISTER BTFSS BRA MOVF SSPSTAT, BF LOOP SSPBUF, W ;Has data been received (transmit complete)? ;No ;WREG reg = contents of SSPBUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF MOVWF TXDATA, W SSPBUF ;W reg = contents of TXDATA ;New data to xmit DS39761B-page 190 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 17.3.3 ENABLING SPI I/O 17.3.4 To enable the serial port, MSSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: * SDI is automatically controlled by the SPI module * SDO must have TRISC<5> bit cleared * SCK (Master mode) must have TRISC<3> bit cleared * SCK (Slave mode) must have TRISC<3> bit set * SS must have TRISF<7> bit set TYPICAL CONNECTION Figure 17-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock. Both processors should be programmed to the same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission: * Master sends data - Slave sends dummy data * Master sends data - Slave sends data * Master sends dummy data - Slave sends data Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. FIGURE 17-2: SPI MASTER/SLAVE CONNECTION SPI Slave SSPM3:SSPM0 = 010xb SPI Master SSPM3:SSPM0 = 00xxb SDI SDO Serial Input Buffer (SSPBUF) Serial Input Buffer (SSPBUF) SDI Shift Register (SSPSR) MSb SDO MSb LSb SCK Serial Clock LSb SCK PROCESSOR 2 PROCESSOR 1 (c) 2007 Microchip Technology Inc. Shift Register (SSPSR) Preliminary DS39761B-page 191 PIC18F2682/2685/4682/4685 17.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 17-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal received byte (interrupts and status bits appropriately set). This could be useful in receiver applications as a "Line Activity Monitor" mode. FIGURE 17-3: The clock polarity is selected by appropriately programming the CKP bit (SSPCON1<4>). This then, would give waveforms for SPI communication as shown in Figure 17-3, Figure 17-5 and Figure 17-6, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user-programmable to be one of the following: * * * * FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 This allows a maximum data rate (at 40 MHz) of 10.00 Mbps. Figure 17-3 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown. SPI MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDO (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPIF Next Q4 Cycle after Q2 SSPSR to SSPBUF DS39761B-page 192 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 17.3.6 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit (SSPCON1<4>). While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. When a byte is received, the device will wake-up from Sleep. 17.3.7 SLAVE SELECT SYNCHRONIZATION The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSPCON1<3:0> = 04h). The pin must not be driven low for the SS pin to function as an input. The data latch FIGURE 17-4: must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. 2: If the SPI is used in Slave mode with CKE set, then the SS pin control must be enabled. When the SPI module resets, the bit counter is forced to `0'. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. To emulate two-wire communication, the SDO pin can be connected to the SDI pin. When the SPI needs to operate as a receiver, the SDO pin can be configured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function) since it cannot create a bus conflict. SLAVE SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 6 bit 7 bit 0 bit 0 bit 7 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2 SSPSR to SSPBUF (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 193 PIC18F2682/2685/4682/4685 FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2 SSPSR to SSPBUF FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2 SSPSR to SSPBUF DS39761B-page 194 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 17.3.8 OPERATION IN POWER-MANAGED MODES 17.3.9 In SPI Master mode, module clocks may be operating at a different speed than when in full power mode. In the case of Sleep mode, all clocks are halted. In most power-managed modes, a clock is provided to the peripherals. That clock should be from the primary clock source, the secondary clock (Timer1 oscillator at 32.768 kHz) or the INTOSC source. See Section 2.7 "Clock Sources and Oscillator Switching" for additional information. In most cases, the speed that the master clocks SPI data is not important; however, this should be evaluated for each system. If MSSP interrupts are enabled, they can wake the controller from Sleep mode, or one of the Idle modes, when the master completes sending data. If an exit from Sleep or Idle mode is not desired, MSSP interrupts should be disabled. If the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the devices wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 17.3.10 BUS MODE COMPATIBILITY Table 17-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits. TABLE 17-1: SPI BUS MODES Control Bits State Standard SPI Mode Terminology CKP CKE 0, 0 0 1 0, 1 0 0 1, 0 1 1 1, 1 1 0 There is also an SMP bit which controls when the data is sampled. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in any power-managed mode and data to be shifted into the SPI Transmit/ Receive Shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. TABLE 17-2: Name REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 TRISA PORTA Data Direction Register 52 TRISC PORTC Data Direction Register 52 SSPBUF MSSP Receive Buffer/Transmit Register 50 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 50 SSPSTAT SMP CKE D/A P S R/W UA BF 50 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the MSSP in SPI mode. Note 1: These bits are unimplemented in PIC18F2682/2685 devices; always maintain these bits clear. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 195 PIC18F2682/2685/4682/4685 17.4 I2C Mode 17.4.1 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer: * Serial clock (SCL) - RC3/SCK/SCL * Serial data (SDA) - RC4/SDI/SDA The user must configure these pins as inputs or outputs through the TRISC<4:3> bits. FIGURE 17-7: MSSP BLOCK DIAGRAM (I2CTM MODE) Write Shift Clock MSb LSb Match Detect Addr Match DS39761B-page 196 SSPCON1, SSPCON2 and SSPSTAT are the control and status registers in I2C mode operation. The SSPCON1 and SSPCON2 registers are readable and writable. The lower 6 bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write. During transmission, the SSPBUF is not doublebuffered. A write to SSPBUF will write to both SSPBUF and SSPSR. SSPADD reg Start and Stop bit Detect MSSP Control Register 1 (SSPCON1) MSSP Control Register 2 (SSPCON2) MSSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer Register (SSPBUF) * MSSP Shift Register (SSPSR) - Not directly accessible * MSSP Address Register (SSPADD) In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. SSPSR reg RC4/SDI/SDA * * * * SSPADD register holds the slave device address when the MSSP is configured in I2C Slave mode. When the MSSP is configured in Master mode, the lower seven bits of SSPADD act as the Baud Rate Generator reload value. SSPBUF reg RC3/SCK/SCL The MSSP module has six registers for I2C operation. These are: SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. Internal Data Bus Read REGISTERS Set, Reset S, P bits (SSPSTAT reg) Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 17-3: R/W-0 SSPSTAT: MSSP STATUS REGISTER (I2CTM MODE) R/W-0 SMP CKE R-0 R-0 R-0 D/A (1) (1) P S R-0 R/W (2,3) R-0 R-0 UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit(1) 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last bit 3 S: Start bit(1) 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last bit 2 R/W: Read/Write Information bit (I2C mode only)(2,3) In Slave mode: 1 = Read 0 = Write In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress bit 1 UA: Update Address bit (10-Bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Receive mode: 1 = Receive complete, SSPBUF is full 0 = Receive is not complete, SSPBUF is empty In Transmit mode: 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty Note 1: 2: 3: This bit is cleared on Reset and when SSPEN is cleared. This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 197 PIC18F2682/2685/4682/4685 REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2CTM MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN(1) CKP SSPM3(2) SSPM2(2) SSPM1(2) SSPM0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a "don't care" bit. bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a "don't care" bit in Transmit mode. bit 5 SSPEN: Master Synchronous Serial Port Enable bit(1) 1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: SCK Release Control bit In Slave mode: 1 = Release clock 0 = Holds clock low (clock stretch), used to ensure data setup time In Master mode: Unused in this mode. bit 3-0 SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits(2) 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (slave Idle) 1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address Note 1: 2: When enabled, the SDA and SCL pins must be properly configured as input or output. Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. DS39761B-page 198 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2CTM MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(1) 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)(2) 1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle bit 3 RCEN: Receive Enable bit (Master mode only)(2) 1 = Enables Receive mode for I2C 0 = Receive Idle bit 2 PEN: Stop Condition Enable bit (Master mode only)(2) 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit (Master mode only(2) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable/Stretch Enable bit(2) In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: 2: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, these bits may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 199 PIC18F2682/2685/4682/4685 17.4.2 OPERATION 17.4.3.1 The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON<5>). The SSPCON1 register allows control of the I 2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2C modes to be selected: I2C Master mode, clock = (FOSC/4) x (SSPADD + 1) I 2C Slave mode (7-bit address) I 2C Slave mode (10-bit address) I 2C Slave mode (7-bit address) with Start and Stop bit interrupts enabled * I 2C Slave mode (10-bit address) with Start and Stop bit interrupts enabled * I 2C Firmware Controlled Master mode, slave is Idle * * * * Selection of any I 2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open-drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits. To ensure proper operation of the module, pull-up resistors must be provided externally to the SCL and SDA pins. 17.4.3 SLAVE MODE In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The MSSP module will override the input state with the output data when required (slave-transmitter). The I 2C Slave mode hardware will always generate an interrupt on an address match. Through the mode select bits, the user can also choose to interrupt on Start and Stop bits When an address is matched, or the data transfer after an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse and load the SSPBUF register with the received value currently in the SSPSR register. Any combination of the following conditions will cause the MSSP module not to give this ACK pulse: * The Buffer Full bit, BF (SSPSTAT<0>), was set before the transfer was received. * The overflow bit, SSPOV (SSPCON<6>), was set before the transfer was received. In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The BF bit is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. Addressing Once the MSSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match and the BF and SSPOV bits are clear, the following events occur: 1. 2. 3. 4. The SSPSR register value is loaded into the SSPBUF register. The Buffer Full bit, BF, is set. An ACK pulse is generated. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is set (interrupt is generated, if enabled) on the falling edge of the ninth SCL pulse. In 10-Bit Address mode, two address bytes need to be received by the slave. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal `11110 A9 A8 0', where `A9' and `A8' are the two MSbs of the address. The sequence of events for 10-bit address is as follows, with steps 7 through 9 for the slave-transmitter: 1. 2. 3. 4. 5. 6. 7. 8. 9. Receive first (high) byte of address (bits SSPIF, BF and UA (SSPSTAT<1>) are set). Update the SSPADD register with second (low) byte of address (clears bit UA and releases the SCL line). Read the SSPBUF register (clears bit BF) and clear flag bit, SSPIF. Receive second (low) byte of address (bits SSPIF, BF and UA are set). Update the SSPADD register with the first (high) byte of address. If match releases SCL line, this will clear bit UA. Read the SSPBUF register (clears bit BF) and clear flag bit, SSPIF. Receive Repeated Start condition. Receive first (high) byte of address (bits SSPIF and BF are set). Read the SSPBUF register (clears bit BF) and clear flag bit, SSPIF. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101. DS39761B-page 200 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 17.4.3.2 Reception 17.4.3.3 When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set, or bit SSPOV (SSPCON1<6>) is set. An MSSP interrupt is generated for each data transfer byte. Flag bit, SSPIF (PIR1<3>), must be cleared in software. The SSPSTAT register is used to determine the status of the byte. If SEN is enabled (SSPCON2<0> = 1), RC3/SCK/SCL will be held low (clock stretch) following each data transfer. The clock must be released by setting bit CKP (SSPCON<4>). See Section 17.4.4 "Clock Stretching" for more detail. Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit and pin RC3/SCK/SCL is held low regardless of SEN (see Section 17.4.4 "Clock Stretching" for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. The transmit data must be loaded into the SSPBUF register which also loads the SSPSR register. Then pin RC3/ SCK/SCL should be enabled by setting bit, CKP (SSPCON1<4>). The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 17-9). The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line is high (not ACK), then the data transfer is complete. In this case, when the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT register) and the slave monitors for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPBUF register. Again, pin RC3/SCK/SCL must be enabled by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 201 DS39761B-page 202 Preliminary CKP 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 (CKP does not reset to `0' when SEN = 0) SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 7 A1 8 9 ACK R/W = 0 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPBUF is still full. ACK is not sent. 9 ACK FIGURE 17-8: SDA PIC18F2682/2685/4682/4685 I2CTM SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) (c) 2007 Microchip Technology Inc. (c) 2007 Microchip Technology Inc. 1 Preliminary CKP 2 A6 Data in sampled BF (SSPSTAT<0>) SSPIF (PIR1<3>) S A7 3 A5 4 A4 5 A3 6 A2 Receiving Address 7 A1 8 R/W = 1 9 ACK SCL held low while CPU responds to SSPIF 1 D7 3 D5 4 D4 5 D3 6 D2 CKP is set in software SSPBUF is written in software Cleared in software 2 D6 Transmitting Data 7 8 D0 9 ACK From SSPIF ISR D1 1 D7 4 D4 5 D3 6 D2 CKP is set in software 7 8 D0 9 ACK From SSPIF ISR D1 Transmitting Data Cleared in software 3 D5 SSPBUF is written in software 2 D6 P FIGURE 17-9: SCL SDA PIC18F2682/2685/4682/4685 I2CTM SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) DS39761B-page 203 DS39761B-page 204 Preliminary 4 1 5 0 7 A8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 6 A9 8 9 (CKP does not reset to `0' when SEN = 0) UA (SSPSTAT<1>) CKP 3 1 Cleared in software 2 1 SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 ACK R/W = 0 A7 2 4 5 A4 A3 6 8 9 A0 ACK UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address 7 A2 A1 Cleared in software 3 A5 Dummy read of SSPBUF to clear BF flag 1 A6 Receive Second Byte of Address 1 D7 4 5 6 Cleared in software 3 7 8 9 1 2 4 5 6 Cleared in software 3 D3 D2 Receive Data Byte D1 D0 ACK D7 D6 D5 D4 Cleared by hardware when SSPADD is updated with high byte of address 2 D3 D2 Receive Data Byte D6 D5 D4 Clock is held low until update of SSPADD has taken place 7 8 D1 D0 9 P Bus master terminates transfer SSPOV is set because SSPBUF is still full. ACK is not sent. ACK FIGURE 17-10: SDA Receive First Byte of Address Clock is held low until update of SSPADD has taken place PIC18F2682/2685/4682/4685 I2CTM SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) (c) 2007 Microchip Technology Inc. (c) 2007 Microchip Technology Inc. Preliminary 2 CKP (SSPCON1<4>) UA (SSPSTAT<1>) BF (SSPSTAT<0>) SSPIF (PIR1<3>) 1 S SCL 1 4 1 5 0 6 7 A9 A8 8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 3 1 Receive First Byte of Address 1 9 ACK 1 3 4 5 Cleared in software 2 7 UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address 6 A6 A5 A4 A3 A2 A1 8 A0 Receive Second Byte of Address Dummy read of SSPBUF to clear BF flag A7 9 ACK 2 3 1 4 1 Cleared in software 1 1 5 0 6 8 9 ACK R/W=1 1 2 4 5 6 CKP is set in software 9 P Completion of data transmission clears BF flag 8 ACK Bus master terminates transfer CKP is automatically cleared in hardware, holding SCL low 7 D4 D3 D2 D1 D0 Cleared in software 3 D7 D6 D5 Transmitting Data Byte Clock is held low until CKP is set to `1' Write of SSPBUF BF flag is clear initiates transmit at the end of the third address sequence 7 A9 A8 Cleared by hardware when SSPADD is updated with high byte of address. Dummy read of SSPBUF to clear BF flag Sr 1 Receive First Byte of Address Clock is held low until update of SSPADD has taken place FIGURE 17-11: SDA R/W = 0 Clock is held low until update of SSPADD has taken place PIC18F2682/2685/4682/4685 I2CTM SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) DS39761B-page 205 PIC18F2682/2685/4682/4685 17.4.4 CLOCK STRETCHING 17.4.4.3 Both 7 and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence. 17.4.4.1 Clock Stretching for 7-Bit Slave Receive Mode (SEN = 1) In 7-Bit Slave Receive mode, on the falling edge of the ninth clock at the end of the ACK sequence if the BF bit is set, the CKP bit in the SSPCON1 register is automatically cleared, forcing the SCL output to be held low. The CKP being cleared to `0' will assert the SCL line low. The CKP bit must be set in the user's ISR before reception is allowed to continue. By holding the SCL line low, the user has time to service the ISR and read the contents of the SSPBUF before the master device can initiate another receive sequence. This will prevent buffer overruns from occurring (see Figure 17-13). Note 1: If the user reads the contents of the SSPBUF before the falling edge of the ninth clock, thus clearing the BF bit, the CKP bit will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software regardless of the state of the BF bit. The user should be careful to clear the BF bit in the ISR before the next receive sequence in order to prevent an overflow condition. 17.4.4.2 Clock Stretching for 7-Bit Slave Transmit Mode 7-Bit Slave Transmit mode implements clock stretching by clearing the CKP bit after the falling edge of the ninth clock if the BF bit is clear. This occurs regardless of the state of the SEN bit. The user's ISR must set the CKP bit before transmission is allowed to continue. By holding the SCL line low, the user has time to service the ISR and load the contents of the SSPBUF before the master device can initiate another transmit sequence (see Figure 17-9). Note 1: If the user loads the contents of SSPBUF, setting the BF bit before the falling edge of the ninth clock, the CKP bit will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software regardless of the state of the BF bit. 17.4.4.4 Clock Stretching for 10-Bit Slave Transmit Mode In 10-Bit Slave Transmit mode, clock stretching is controlled during the first two address sequences by the state of the UA bit, just as it is in 10-Bit Slave Receive mode. The first two addresses are followed by a third address sequence which contains the highorder bits of the 10-bit address and the R/W bit set to `1'. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-Bit Slave Transmit mode (see Figure 17-11). Clock Stretching for 10-Bit Slave Receive Mode (SEN = 1) In 10-Bit Slave Receive mode during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to `0'. The release of the clock line occurs upon updating SSPADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPADD register before the falling edge of the ninth clock occurs and if the user hasn't cleared the BF bit by reading the SSPBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. DS39761B-page 206 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 17.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCL output is forced to `0'. However, setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has FIGURE 17-12: already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 17-12). CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX - 1 SCL CKP Master device asserts clock Master device deasserts clock WR SSPCON (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 207 DS39761B-page 208 Preliminary CKP SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 7 A1 8 9 ACK R/W = 0 3 4 D4 5 D3 Receiving Data D5 Cleared in software 2 D6 If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to `0' and no clock stretching will occur SSPBUF is read 1 D7 6 D2 7 D1 9 ACK 1 D7 BF is set after falling edge of the 9th clock, CKP is reset to `0' and clock stretching occurs 8 D0 CKP written to `1' in software 2 D6 Clock is held low until CKP is set to `1' 3 4 D4 5 D3 Receiving Data D5 D1 7 D2 6 8 D0 Bus master terminates transfer P SSPOV is set because SSPBUF is still full. ACK is not sent. 9 ACK Clock is not held low because ACK = 1 FIGURE 17-13: SDA Clock is not held low because buffer full bit is clear prior to falling edge of 9th clock PIC18F2682/2685/4682/4685 I2CTM SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) (c) 2007 Microchip Technology Inc. (c) 2007 Microchip Technology Inc. 2 1 Preliminary UA (SSPSTAT<1>) SSPOV (SSPCON1<6>) CKP 3 1 4 1 5 0 6 7 A9 A8 8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR Cleared in software BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 9 ACK R/W = 0 A7 2 4 A4 5 A3 6 8 A0 Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set. UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address after falling edge of ninth clock 7 A2 A1 Cleared in software 3 A5 Dummy read of SSPBUF to clear BF flag 1 A6 Receive Second Byte of Address 9 ACK 2 4 5 6 Cleared in software 3 D3 D2 7 9 Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set. 8 ACK 1 4 5 6 Cleared in software 3 D3 D2 CKP written to `1' in software 2 D4 Receive Data Byte D7 D6 D5 Clock is held low until CKP is set to `1' D1 D0 Cleared by hardware when SSPADD is updated with high byte of address after falling edge of ninth clock Dummy read of SSPBUF to clear BF flag 1 D7 D6 D5 D4 Receive Data Byte Clock is held low until update of SSPADD has taken place 7 8 9 Bus master terminates transfer P SSPOV is set because SSPBUF is still full. ACK is not sent. D1 D0 ACK Clock is not held low because ACK = 1 FIGURE 17-14: SDA Receive First Byte of Address Clock is held low until update of SSPADD has taken place PIC18F2682/2685/4682/4685 I2CTM SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS) DS39761B-page 209 PIC18F2682/2685/4682/4685 17.4.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledge. When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the SSPBUF. The value can be used to determine if the address was device specific or a general call address. In 10-Bit Address mode, the SSPADD is required to be updated for the second half of the address to match and the UA bit is set (SSPSTAT<1>). If the general call address is sampled when the GCEN bit is set, while the slave is configured in 10-Bit Address mode, then the second half of the address is not necessary, the UA bit will not be set and the slave will begin receiving data after the Acknowledge (Figure 17-15). The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It consists of all `0's with R/W = 0. The general call address is recognized when the General Call Enable bit, GCEN, is enabled (SSPCON2<7> set). Following a Start bit detect, 8 bits are shifted into the SSPSR and the address is compared against the SSPADD. It is also compared to the general call address and fixed in hardware. FIGURE 17-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS MODE) Address is compared to General Call Address after ACK, set interrupt Receiving Data R/W = 0 General Call Address SDA SCL S 1 2 3 4 5 ACK D7 6 7 8 9 1 ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 SSPIF BF (SSPSTAT<0>) Cleared in software SSPBUF is read SSPOV (SSPCON1<6>) `0' GCEN (SSPCON2<7>) `1' DS39761B-page 210 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set or the bus is Idle, with both the S and P bits clear. The following events will cause the MSSP Interrupt Flag bit, SSPIF, to be set (MSSP interrupt, if enabled): In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on Start and Stop bit conditions. * * * * * Once Master mode is enabled, the user has six options. 1. 2. 3. 4. 5. 6. Assert a Start condition on SDA and SCL. Assert a Repeated Start condition on SDA and SCL. Write to the SSPBUF register initiating transmission of data/address. Configure the I2C port to receive data. Generate an Acknowledge condition at the end of a received byte of data. Generate a Stop condition on SDA and SCL. FIGURE 17-16: The MSSP module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPBUF register to initiate transmission before the Start condition is complete. In this case, the SSPBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPBUF did not occur. Start Condition Stop Condition Data Transfer Byte Transmitted/Received Acknowledge Transmit Repeated Start MSSP BLOCK DIAGRAM (I2CTM MASTER MODE) Internal Data Bus Read SSPM3:SSPM0 SSPADD<6:0> Write SSPBUF Baud Rate Generator SDA Shift Clock SDA In SCL In Bus Collision (c) 2007 Microchip Technology Inc. LSb Start bit, Stop bit, Acknowledge Generate Start bit Detect Stop bit Detect Write Collision Detect Clock Arbitration State Counter for end of XMIT/RCV Preliminary Clock Cntl SCL Receive Enable SSPSR MSb Clock Arbitrate/WCOL Detect (hold off clock source) 17.4.6 Set/Reset, S, P, WCOL (SSPSTAT) Set SSPIF, BCLIF Reset ACKSTAT, PEN (SSPCON2) DS39761B-page 211 PIC18F2682/2685/4682/4685 17.4.6.1 I2C Master Mode Operation A typical transmit sequence would go as follows: The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic `0'. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic `1' Thus, the first byte transmitted is a 7-bit slave address followed by a `1' to indicate the receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. The Baud Rate Generator used for the SPI mode operation is used to set the SCL clock frequency for either 100 kHz, 400 kHz or 1 MHz I2C operation. See Section 17.4.7 "Baud Rate" for more detail. DS39761B-page 212 1. The user generates a Start condition by setting the Start Enable bit, SEN (SSPCON2<0>). 2. SSPIF is set. The MSSP module will wait the required start time before any other operation takes place. 3. The user loads the SSPBUF with the slave address to transmit. 4. Address is shifted out on the SDA pin until all 8 bits are transmitted. 5. The MSSP Module shifts in the ACK bit from the slave device and writes its value into the SSPCON2 register (SSPCON2<6>). 6. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 7. The user loads the SSPBUF with eight bits of data. 8. Data is shifted out on the SDA pin until all 8 bits are transmitted. 9. The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPCON2 register (SSPCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a Stop condition by setting the Stop Enable bit, PEN (SSPCON2<2>). 12. Interrupt is generated once the Stop condition is complete. Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 17.4.7 BAUD RATE 2 In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Figure 17-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to 0 and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically. FIGURE 17-17: SSPM3:SSPM0 SCL Reload Control CLKO Note 1: Table 17-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPADD. BAUD RATE GENERATOR BLOCK DIAGRAM SSPM3:SSPM0 TABLE 17-3: Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state. SSPADD<6:0> Reload BRG Down Counter FOSC/4 I2CTM CLOCK RATE w/BRG FCY FCY*2 BRG Value FSCL (2 Rollovers of BRG) 10 MHz 20 MHz 19h 400 kHz(1) 10 MHz 20 MHz 20h 312.5 kHz 10 MHz 20 MHz 64h 100 kHz 4 MHz 8 MHz 0Ah 400 kHz(1) 4 MHz 8 MHz 0Dh 308 kHz 4 MHz 8 MHz 28h 100 kHz 1 MHz 2 MHz 03h 333 kHz(1) 1 MHz 2 MHz 0Ah 100 kHz 1 MHz 2 MHz 00h 1 MHz(1) The I2CTM interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 213 PIC18F2682/2685/4682/4685 17.4.7.1 Clock Arbitration SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 17-18). Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the FIGURE 17-18: SDA BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION DX DX - 1 SCL deasserted but slave holds SCL low (clock arbitration) SCL allowed to transition high SCL BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place and BRG starts its count BRG Reload DS39761B-page 214 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 17.4.8 I2C MASTER MODE START CONDITION TIMING Note: To initiate a Start condition, the user sets the Start Enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is high is the Start condition and causes the S bit (SSPSTAT<3>) to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit (SSPCON2<0>) will be automatically cleared by hardware, the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. FIGURE 17-19: 17.4.8.1 If at the beginning of the Start condition, the SDA and SCL pins are already sampled low, or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. WCOL Status Flag If the user writes the SSPBUF when a Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPCON2 is disabled until the Start condition is complete. FIRST START BIT TIMING Write to SEN bit occurs here SDA = 1, SCL = 1 TBRG Set S bit (SSPSTAT<3>) At completion of Start bit, hardware clears SEN bit and sets SSPIF bit TBRG Write to SSPBUF occurs here 1st bit SDA 2nd bit TBRG SCL TBRG S (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 215 PIC18F2682/2685/4682/4685 17.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPADD<5:0> and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG while SCL is high. Following this, the RSEN bit (SSPCON2<1>) will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit (SSPSTAT<3>) will be set. The SSPIF bit will not be set until the Baud Rate Generator has timed out. 2: A bus collision during the Repeated Start condition occurs if: * SDA is sampled low when SCL goes from low-to-high. * SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data `1'. Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). 17.4.9.1 If the user writes the SSPBUF when a Repeated Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Note: FIGURE 17-20: WCOL Status Flag Because queueing of events is not allowed, writing of the lower 5 bits of SSPCON2 is disabled until the Repeated Start condition is complete. REPEATED START CONDITION WAVEFORM Write to SSPCON2 occurs here. SDA = 1, SCL (no change). Set S (SSPSTAT<3>) SDA = 1, SCL = 1 TBRG TBRG At completion of Start bit, hardware clears RSEN bit and sets SSPIF TBRG 1st bit SDA Write to SSPBUF occurs here Falling edge of ninth clock, end of Xmit TBRG SCL TBRG Sr = Repeated Start DS39761B-page 216 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 17.4.10 I2C MASTER MODE TRANSMISSION 17.4.10.3 Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter 106). SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCL is released high (see data setup time specification parameter 107). When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKDT bit on the falling edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSPIF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPBUF, leaving SCL low and SDA unchanged (Figure 17-21). After the write to the SSPBUF, each bit of address will be shifted out on the falling edge of SCL until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will deassert the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT status bit (SSPCON2<6>). Following the falling edge of the ninth clock transmission of the address, the SSPIF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPBUF takes place, holding SCL low and allowing SDA to float. 17.4.10.1 BF Status Flag ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 17.4.11 I2C MASTER MODE RECEPTION Master mode reception is enabled by programming the Receive Enable bit, RCEN (SSPCON2<3>). Note: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/ low-to-high) and data is shifted into the SSPSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPSR are loaded into the SSPBUF, the BF flag bit is set, the SSPIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCL low. The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge sequence enable bit, ACKEN (SSPCON2<4>). 17.4.11.1 BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPBUF from SSPSR. It is cleared when the SSPBUF register is read. 17.4.11.2 SSPOV Status Flag In receive operation, the SSPOV bit is set when 8 bits are received into the SSPSR and the BF flag bit is already set from a previous reception. 17.4.11.3 WCOL Status Flag If the user writes the SSPBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur). In Transmit mode, the BF bit (SSPSTAT<0>) is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out. 17.4.10.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). WCOL must be cleared in software. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 217 DS39761B-page 218 S Preliminary R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPBUF written 1 D7 1 SCL held low while CPU responds to SSPIF ACK = 0 R/W = 0 SSPBUF written with 7-bit address and R/W, start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPBUF is written in software Cleared in software service routine from MSSP interrupt 2 D6 Transmitting Data or Second Half of 10-bit Address From slave, clear ACKSTAT bit SSPCON2<6> P Cleared in software 9 ACK ACKSTAT in SSPCON2 = 1 FIGURE 17-21: SEN = 0 Write SSPCON2<0> SEN = 1, start condition begins PIC18F2682/2685/4682/4685 I 2CTM MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) (c) 2007 Microchip Technology Inc. (c) 2007 Microchip Technology Inc. S Preliminary ACKEN SSPOV BF (SSPSTAT<0>) SDA = 0, SCL = 1 while CPU responds to SSPIF SSPIF SCL SDA 1 A7 2 4 5 Cleared in software 3 6 A6 A5 A4 A3 A2 Transmit Address to Slave 7 A1 8 9 R/W = 1 ACK ACK from Slave 2 3 5 6 7 8 D0 9 ACK 2 3 4 5 6 7 Cleared in software Set SSPIF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK 1 D7 D6 D5 D4 D3 D2 D1 Cleared in software Set SSPIF at end of receive 9 ACK is not sent ACK P Set SSPIF interrupt at end of Acknowledge sequence Bus master terminates transfer Set P bit (SSPSTAT<4>) and SSPIF PEN bit = 1 written here SSPOV is set because SSPBUF is still full 8 D0 RCEN cleared automatically Set ACKEN, start Acknowledge sequence SDA = ACKDT = 1 Receiving Data from Slave RCEN = 1, start next receive ACK from Master SDA = ACKDT = 0 Last bit is shifted into SSPSR and contents are unloaded into SSPBUF Cleared in software Set SSPIF interrupt at end of receive 4 Cleared in software 1 D7 D6 D5 D4 D3 D2 D1 Receiving Data from Slave RCEN cleared automatically Master configured as a receiver by programming SSPCON2<3> (RCEN = 1) FIGURE 17-22: SEN = 0 Write to SSPBUF occurs here, start XMIT Write to SSPCON2<0> (SEN = 1), begin Start condition Write to SSPCON2<4> to start Acknowledge sequence SDA = ACKDT (SSPCON2<5>) = 0 PIC18F2682/2685/4682/4685 I 2CTM MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) DS39761B-page 219 PIC18F2682/2685/4682/4685 17.4.12 ACKNOWLEDGE SEQUENCE TIMING 17.4.13 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPCON2<2>). At the end of a receive/ transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to 0. When the Baud Rate Generator times out, the SCL pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDA pin will be deasserted. When the SDA pin is sampled high while SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG later, the PEN bit is cleared and the SSPIF bit is set (Figure 17-24). An Acknowledge sequence is enabled by setting the Acknowledge sequence enable bit, ACKEN (SSPCON2<4>). When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCL pin is deasserted (pulled high). When the SCL pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP module then goes into Idle mode (Figure 17-23). 17.4.12.1 17.4.13.1 WCOL Status Flag If the user writes the SSPBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur). WCOL Status Flag If the user writes the SSPBUF when an Acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). FIGURE 17-23: STOP CONDITION TIMING ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, write to SSPCON2 ACKEN = 1, ACKDT = 0 SDA ACKEN automatically cleared TBRG SCL TBRG ACK D0 8 9 SSPIF Set SSPIF at the end of receive Cleared in software Cleared in software Set SSPIF at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 17-24: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2, set PEN SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPSTAT<4>) is set. Falling edge of 9th clock PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. DS39761B-page 220 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 17.4.14 SLEEP OPERATION 17.4.17 2 While in Sleep mode, the I C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 17.4.15 Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a `1' on SDA, by letting SDA float high and another master asserts a `0'. When the SCL pin floats high, data should be stable. If the expected data on SDA is a `1' and the data sampled on the SDA pin = 0, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF and reset the I2C port to its Idle state (Figure 17-25). EFFECT OF A RESET A Reset disables the MSSP module and terminates the current transfer. 17.4.16 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit (SSPSTAT<4>) is set, or the bus is Idle, with both the S and P bits clear. When the bus is busy, enabling the MSSP interrupt will generate the interrupt when the Stop condition occurs. If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are deasserted and the SSPBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed in hardware with the result placed in the BCLIF bit. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSPCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The states where arbitration can be lost are: * * * * * MULTI-MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition The master will continue to monitor the SDA and SCL pins. If a Stop condition occurs, the SSPIF bit will be set. A write to the SSPBUF will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 17-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high, data doesn't match what is driven by the master. Bus collision has occurred. SDA SCL Set bus collision interrupt (BCLIF) BCLIF (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 221 PIC18F2682/2685/4682/4685 17.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 17-26). SCL is sampled low before SDA is asserted low (Figure 17-27). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 17-28). If, however, a `1' is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to 0 and during this time, if the SCL pins are sampled as `0', a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Note: If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: * the Start condition is aborted, * the BCLIF flag is set; and * the MSSP module is reset to its Idle state (Figure 17-26). The Start condition begins with the SDA and SCL pins deasserted. When the SDA pin is sampled high, the Baud Rate Generator is loaded from SSPADD<6:0> and counts down to 0. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data `1' during the Start condition. FIGURE 17-26: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start condition if SDA = 1, SCL = 1 SEN cleared automatically because of bus collision. MSSP module reset into Idle state. SEN BCLIF SDA sampled low before Start condition. Set BCLIF. S bit and SSPIF set because SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software S SSPIF SSPIF and BCLIF are cleared in software DS39761B-page 222 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 FIGURE 17-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF Interrupt cleared in software S `0' `0' SSPIF `0' `0' FIGURE 17-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG SDA Set SSPIF TBRG SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time-out SEN Set SEN, enable START sequence if SDA = 1, SCL = 1 `0' BCLIF S SSPIF SDA = 0, SCL = 1, set SSPIF (c) 2007 Microchip Technology Inc. Preliminary Interrupts cleared in software DS39761B-page 223 PIC18F2682/2685/4682/4685 17.4.17.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data `0', Figure 17-29). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDA when SCL goes from low level to high level. SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data `1'. If SCL goes from high to low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data `1' during the Repeated Start condition, see Figure 17-30. When the user deasserts SDA and the pin is allowed to float high, the BRG is loaded with SSPADD<6:0> and counts down to 0. The SCL pin is then deasserted and when sampled high, the SDA pin is sampled. FIGURE 17-29: If, at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared in software S `0' SSPIF `0' FIGURE 17-30: BUS COLLISION DURING A REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL BCLIF SCL goes low before SDA, set BCLIF. Release SDA and SCL. Interrupt cleared in software RSEN `0' S SSPIF DS39761B-page 224 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 17.4.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data `0' (Figure 17-31). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data `0' (Figure 17-32). Bus collision occurs during a Stop condition if: a) b) After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed out. After the SCL pin is deasserted, SCL is sampled low before SDA goes high. FIGURE 17-31: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCLIF SDA SDA asserted low SCL PEN BCLIF P `0' SSPIF `0' FIGURE 17-32: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, set BCLIF Assert SDA SCL PEN BCLIF P `0' SSPIF `0' (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 225 PIC18F2682/2685/4682/4685 NOTES: DS39761B-page 226 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 18.0 ENHANCED UNIVERSAL SYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The pins of the Enhanced USART are multiplexed with PORTC. In order to configure RC6/TX/CK and RC7/RX/DT as an EUSART: The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.) The EUSART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers. It can also be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs and so on. The EUSART module implements additional features, including Auto-Baud Rate Detection and calibration, automatic wake-up on Sync Break reception and 12-bit Break character transmit. These features make it ideally suited for use in Local Interconnect Network bus (LIN bus) systems. * bit SPEN (RCSTA<7>) must be set (= 1) * bit TRISC<7> must be set (= 1) * bit TRISC<6> must be cleared (= 0) for Asynchronous and Synchronous Master modes, or set (= 1) for Synchronous Slave mode Note: The EUSART control will automatically reconfigure the pin from input to output as needed. The operation of the Enhanced USART module is controlled through three registers: * Transmit Status and Control (TXSTA) * Receive Status and Control (RCSTA) * Baud Rate Control (BAUDCON) These are detailed on the following pages in Register 18-1, Register 18-2 and Register 18-3, respectively. The EUSART can be configured in the following modes: * Asynchronous (full duplex) with: - Auto-Wake-up on Character Reception - Auto-Baud Calibration - 12-Bit Break Character Transmission * Synchronous - Master (half duplex) with Selectable Clock Polarity * Synchronous - Slave (half duplex) with Selectable Clock Polarity (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 227 PIC18F2682/2685/4682/4685 REGISTER 18-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don't care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-Bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don't care. bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS39761B-page 228 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don't care. Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave: Don't care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 9-bit (RX9 = 0): Don't care. bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receiving next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data This can be an address/data bit or a parity bit and must be calculated by user firmware. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 229 PIC18F2682/2685/4682/4685 REGISTER 18-3: BAUDCON: BAUD RATE CONTROL REGISTER R/W-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollover has occurred bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is active bit 5 Unimplemented: Read as `0' bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: Unused in this mode. Synchronous mode: 1 = Idle state for clock (CK) is a high level 0 = Idle state for clock (CK) is a low level bit 3 BRG16: 16-Bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator - SPBRGH and SPBRG 0 = 8-bit Baud Rate Generator - SPBRG only (Compatible mode), SPBRGH value ignored bit 2 Unimplemented: Read as `0' bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSART will continue to sample the RX pin - interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RX pin not monitored or rising edge detected Synchronous mode: Unused in this mode. bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h); cleared in hardware upon completion. 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. DS39761B-page 230 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 18.1 Baud Rate Generator (BRG) The BRG is a dedicated 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCON<3>) selects 16-bit mode. The SPBRGH:SPBRG register pair controls the period of a free-running timer. In Asynchronous mode, bits BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>) also control the baud rate. In Synchronous mode, BRGH is ignored. Table 18-1 shows the formula for computation of the baud rate for different EUSART modes which only apply in Master mode (internally generated clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRGH:SPBRG registers can be calculated using the formulas in Table 18-1. From this, the error in baud rate can be determined. An example calculation is shown in Example 18-1. Typical baud rates and error values for the various Asynchronous modes are shown in Table 18-2. It may be advantageous to use TABLE 18-1: the high baud rate (BRGH = 1) or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. Writing a new value to the SPBRGH:SPBRG registers causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. 18.1.1 OPERATION IN POWER-MANAGED MODES The device clock is used to generate the desired baud rate. When one of the power-managed modes is entered, the new clock source may be operating at a different frequency. This may require an adjustment to the value in the SPBRG register pair. 18.1.2 SAMPLING The data on the RX pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin. BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula 8-bit/Asynchronous FOSC/[64 (n + 1)] SYNC BRG16 BRGH 0 0 0 0 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 1 x 16-bit/Synchronous FOSC/[16 (n + 1)] FOSC/[4 (n + 1)] Legend: x = Don't care, n = value of SPBRGH:SPBRG register pair EXAMPLE 18-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1) Solving for SPBRGH:SPBRG: X = ((FOSC/Desired Baud Rate)/64) - 1 = ((16000000/9600)/64) - 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate - Desired Baud Rate)/Desired Baud Rate = (9615 - 9600)/9600 = 0.16% TABLE 18-2: Name TXSTA RCSTA BAUDCON REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 51 SPBRGH EUSART Baud Rate Generator Register High Byte 51 SPBRG EUSART Baud Rate Generator Register Low Byte 51 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the BRG. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 231 PIC18F2682/2685/4682/4685 TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error -- -- -- -- -- 1.221 2.441 1.73 255 9.615 0.16 64 Actual Rate (K) % Error 0.3 1.2 -- -- 2.4 9.6 SPBRG value FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error -- 1.73 -- 255 -- 1.202 2.404 0.16 129 9.766 1.73 31 SPBRG value FOSC = 8.000 MHz (decimal) Actual Rate (K) % Error -- 0.16 -- 129 -- 1.201 -- -0.16 -- 103 2.404 0.16 64 2.403 -0.16 51 9.766 1.73 15 9.615 -0.16 12 -- SPBRG value SPBRG value (decimal) 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 -- -- 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 -- -- -- 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 -- -- -- SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 4.000 MHz FOSC = 2.000 MHz (decimal) Actual Rate (K) % Error 0.16 207 0.300 0.16 51 1.201 2.404 0.16 25 Actual Rate (K) % Error 0.3 0.300 1.2 1.202 2.4 SPBRG value FOSC = 1.000 MHz (decimal) Actual Rate (K) % Error -0.16 103 0.300 -0.16 51 -0.16 25 1.201 -0.16 12 2.403 -0.16 12 -- -- -- SPBRG value SPBRG value (decimal) 9.6 8.929 -6.99 6 -- -- -- -- -- -- 19.2 20.833 8.51 2 -- -- -- -- -- -- 57.6 62.500 8.51 0 -- -- -- -- -- -- 115.2 62.500 -45.75 0 -- -- -- -- -- -- SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error -- -- -- -- -- -- -- -- -- Actual Rate (K) % Error 0.3 -- -- 1.2 -- 2.4 SPBRG value FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error -- -- -- -- -- -- -- -- -- SPBRG value FOSC = 8.000 MHz (decimal) Actual Rate (K) % Error -- -- -- -- -- -- -- -- 2.441 1.73 255 2.403 -0.16 207 SPBRG value SPBRG value (decimal) -- 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 -- -- -- SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE (K) FOSC = 4.000 MHz FOSC = 2.000 MHz (decimal) Actual Rate (K) % Error -- -- -- 0.16 207 1.201 2.404 0.16 103 9.615 0.16 25 19.2 19.231 0.16 57.6 62.500 115.2 125.000 (decimal) % Error -- 0.300 -0.16 207 -0.16 103 1.201 -0.16 51 2.403 -0.16 51 2.403 -0.16 25 9.615 -0.16 12 -- -- -- 12 -- -- -- -- -- -- 8.51 3 -- -- -- -- -- -- 8.51 1 -- -- -- -- -- -- % Error 0.3 -- -- 1.2 1.202 2.4 9.6 DS39761B-page 232 FOSC = 1.000 MHz Actual Rate (K) Actual Rate (K) SPBRG value SPBRG value Preliminary SPBRG value (decimal) (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) % Error FOSC = 20.000 MHz SPBRG value (decimal) Actual Rate (K) % Error FOSC = 10.000 MHz (decimal) Actual Rate (K) SPBRG value % Error FOSC = 8.000 MHz (decimal) Actual Rate (K) % Error SPBRG value SPBRG value (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1.201 -0.16 1665 415 2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2.403 -0.16 207 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 25 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 -- -- -- SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 4.000 MHz Actual Rate (K) % Error FOSC = 2.000 MHz SPBRG value (decimal) Actual Rate (K) % Error FOSC = 1.000 MHz SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) 0.3 0.300 0.04 832 0.300 -0.16 415 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 -- -- -- 19.2 19.231 0.16 12 -- -- -- -- -- -- 57.6 62.500 8.51 3 -- -- -- -- -- -- 115.2 125.000 8.51 1 -- -- -- -- -- -- SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error 0.00 33332 0.300 0.00 8332 1.200 0.02 4165 Actual Rate (K) % Error 0.3 0.300 1.2 1.200 2.4 2.400 SPBRG value FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error 0.00 16665 0.300 0.02 4165 1.200 2.400 0.02 2082 2.402 SPBRG value FOSC = 8.000 MHz (decimal) Actual Rate (K) % Error 0.00 8332 0.300 -0.01 6665 0.02 2082 1.200 -0.04 1665 0.06 1040 2.400 -0.04 832 SPBRG value SPBRG value (decimal) 9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9.615 -0.16 207 19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19.230 -0.16 103 57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57.142 0.79 34 115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117.647 -2.12 16 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz (decimal) Actual Rate (K) % Error 3332 832 0.300 1.201 -0.04 -0.16 2.403 -0.16 207 9.615 -0.16 51 19.230 -0.16 25 16 55.555 3.55 8 -- -- Actual Rate (K) % Error 0.3 1.2 0.300 1.200 0.01 0.04 2.4 2.404 0.16 415 9.6 9.615 0.16 103 19.2 19.231 0.16 51 57.6 58.824 2.12 115.2 111.111 -3.55 SPBRG value (c) 2007 Microchip Technology Inc. (decimal) Actual Rate (K) % Error 1665 415 0.300 1.201 -0.04 -0.16 832 207 2.403 -0.16 103 9.615 -0.16 25 19.230 -0.16 12 8 -- -- -- -- -- -- -- SPBRG value Preliminary SPBRG value (decimal) DS39761B-page 233 PIC18F2682/2685/4682/4685 18.1.3 AUTO-BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. The automatic baud rate measurement sequence (Figure 18-1) begins whenever a Start bit is received and the ABDEN bit is set. The calculation is self-averaging. While the ABD sequence takes place, the EUSART state machine is held in Idle. The RCIF interrupt is set once the fifth rising edge on RX is detected. The value in the RCREG needs to be read to clear the RCIF interrupt. The contents of RCREG should be discarded. Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible due to bit error rates. Overall system timing and communication baud rates must be taken into consideration when using the Auto-Baud Rate Detection feature. In the Auto-Baud Rate Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. In ABD mode, the internal Baud Rate Generator is used as a counter to time the bit period of the incoming serial byte stream. Once the ABDEN bit is set, the state machine will clear the BRG and look for a Start bit. The Auto-Baud Rate Detection must receive a byte with the value 55h (ASCII "U", which is also the LIN bus Sync character) in order to calculate the proper bit rate. The measurement is taken over both a low and high bit time in order to minimize any effects caused by asymmetry of the incoming signal. After a Start bit, the SPBRG begins counting up, using the preselected clock source on the first rising edge of RX. After eight bits on the RX pin or the fifth rising edge, an accumulated value totalling the proper BRG period is left in the SPBRGH:SPBRG register pair. Once the 5th edge is seen (this should correspond to the Stop bit), the ABDEN bit is automatically cleared. If a rollover of the BRG occurs (an overflow from FFFFh to 0000h), the event is trapped by the ABDOVF status bit (BAUDCON<7>). It is set in hardware by BRG rollovers and can be set or cleared by the user in software. ABD mode remains active after rollover events and the ABDEN bit remains set (Figure 18-2). While calibrating the baud rate period, the BRG registers are clocked at 1/8th the preconfigured clock rate. Note that the BRG clock will be configured by the BRG16 and BRGH bits. Independent of the BRG16 bit setting, both the SPBRG and SPBRGH will be used as a 16-bit counter. This allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the SPBRGH register. Refer to Table 18-4 for counter clock rates to the BRG. DS39761B-page 234 TABLE 18-4: BRG COUNTER CLOCK RATES BRG16 BRGH BRG Counter Clock 0 0 FOSC/512 0 1 FOSC/128 1 0 FOSC/128 1 1 FOSC/32 Note: During the ABD sequence, SPBRG and SPBRGH are both used as a 16-bit counter, independent of the BRG16 setting. 18.1.3.1 ABD and EUSART Transmission Since the BRG clock is reversed during ABD acquisition, the EUSART transmitter cannot be used during ABD. This means that whenever the ABDEN bit is set, TXREG cannot be written to. Users should also ensure that ABDEN does not become set during a transmit sequence. Failing to do this may result in unpredictable EUSART operation. Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 FIGURE 18-1: BRG Value AUTOMATIC BAUD RATE CALCULATION XXXXh RX pin 0000h 001Ch Start Edge #1 bit 1 bit 0 Edge #2 bit 3 bit 2 Edge #3 bit 5 bit 4 Edge #4 bit 7 bit 6 Edge #5 Stop bit BRG Clock Auto-Cleared Set by User ABDEN bit RCIF bit (Interrupt) Read RCREG SPBRG XXXXh 1Ch SPBRGH XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0. FIGURE 18-2: BRG OVERFLOW SEQUENCE BRG Clock ABDEN bit RX pin Start bit 0 ABDOVF bit FFFFh BRG Value XXXXh (c) 2007 Microchip Technology Inc. 0000h 0000h Preliminary DS39761B-page 235 PIC18F2682/2685/4682/4685 18.2 EUSART Asynchronous Mode Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and the TXIF flag bit (PIR1<4>) is set. This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXIE (PIE1<4>). TXIF will be set regardless of the state of TXIE; it cannot be cleared in software. TXIF is also not cleared immediately upon loading TXREG, but becomes valid in the second instruction cycle following the load instruction. Polling TXIF immediately following a load of TXREG will return invalid results. The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTA<4>). In this mode, the EUSART uses standard Non-Return-to-Zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8 bits. An on-chip, dedicated 8-bit/16-bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator. The EUSART transmits and receives the LSb first. The EUSART's transmitter and receiver are functionally independent but use the same data format and baud rate. The Baud Rate Generator produces a clock, either x16 or x64 of the bit shift rate depending on the BRGH and BRG16 bits (TXSTA<2> and BAUDCON<3>). Parity is not supported by the hardware, but can be implemented in software and stored as the 9th data bit. While TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. TRMT is a read-only bit which is set when the TSR register is empty. No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty. Note 1: The TSR register is not mapped in data memory so it is not available to the user. When operating in Asynchronous mode, the EUSART module consists of the following important elements: * * * * * * * 2: Flag bit, TXIF, is set when enable bit, TXEN, is set. Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver Auto-Wake-up on Sync Break Character 12-Bit Break Character Transmit Auto-Baud Rate Detection 18.2.1 To set up an Asynchronous Transmission: 1. 2. EUSART ASYNCHRONOUS TRANSMITTER 3. 4. The EUSART transmitter block diagram is shown in Figure 18-3. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The Shift register obtains its data from the Read/Write Transmit Buffer register, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). FIGURE 18-3: 5. 6. 7. 8. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit. Enable the transmission by setting bit TXEN which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission). If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXREG Register TXIF TXIE 8 MSb (8) LSb * * * Pin Buffer and Control 0 TSR Register TX pin Interrupt TXEN Baud Rate CLK TRMT BRG16 SPBRGH SPBRG Baud Rate Generator DS39761B-page 236 SPEN TX9 TX9D Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 FIGURE 18-4: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer Reg. Empty Flag) 1 TCY Word 1 Transmit Shift Reg TRMT bit (Transmit Shift Reg. Empty Flag) FIGURE 18-5: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG Word 2 Word 1 BRG Output (Shift Clock) TX (pin) TXIF bit (Interrupt Reg. Flag) Start bit bit 0 bit 1 1 TCY bit 7/8 Stop bit Start bit bit 0 Word 2 Word 1 1 TCY TRMT bit (Transmit Shift Reg. Empty Flag) Note: Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. This timing diagram shows two consecutive transmissions. TABLE 18-5: Name REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D RCSTA TXREG TXSTA BAUDCON EUSART Transmit Register 51 51 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 51 SPBRGH EUSART Baud Rate Generator Register High Byte 51 SPBRG EUSART Baud Rate Generator Register Low Byte 51 Legend: -- = unimplemented locations read as `0'. Shaded cells are not used for asynchronous transmission. Note 1: Reserved in PIC18F2682/2685 devices; always maintain these bits clear. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 237 PIC18F2682/2685/4682/4685 18.2.2 EUSART ASYNCHRONOUS RECEIVER 18.2.3 The receiver block diagram is shown in Figure 18-6. The data is received on the RX pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. 3. If interrupts are required, set the RCEN bit and select the desired priority level with the RCIP bit. 4. Set the RX9 bit to enable 9-bit reception. 5. Set the ADDEN bit to enable address detect. 6. Enable reception by setting the CREN bit. 7. The RCIF bit will be set when reception is complete. The interrupt will be Acknowledged if the RCIE and GIE bits are set. 8. Read the RCSTA register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. Read RCREG to determine if the device is being addressed. 10. If any error occurred, clear the CREN bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU. To set up an Asynchronous Reception: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 3. If interrupts are desired, set enable bit, RCIE. 4. If 9-bit reception is desired, set bit RX9. 5. Enable the reception by setting bit CREN. 6. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. 7. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing enable bit CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 18-6: SETTING UP 9-BIT MODE WITH ADDRESS DETECT EUSART RECEIVE BLOCK DIAGRAM CREN OERR FERR x64 Baud Rate CLK BRG16 SPBRGH SPBRG Baud Rate Generator / 64 or / 16 or /4 RSR Register MSb Stop (8) 7 * * * LSb 1 0 Start RX9 Pin Buffer and Control Data Recovery RX9D RX RCREG Register FIFO SPEN 8 Interrupt RCIF Data Bus RCIE DS39761B-page 238 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 FIGURE 18-7: ASYNCHRONOUS RECEPTION Start bit RX (pin) bit 0 bit 7/8 Stop bit bit 1 Start bit bit 0 Rcv Shift Reg Rcv Buffer Reg Stop bit Start bit bit 7/8 Stop bit Word 2 RCREG Word 1 RCREG Read Rcv Buffer Reg RCREG bit 7/8 RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word causing the OERR (Overrun) bit to be set. TABLE 18-6: Name REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INT0IE RBIE TMR0IF INT0IF RBIF 49 INTCON GIE/GIEH PEIE/GIEL TMR0IE PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51 RCSTA RCREG TXSTA EUSART Receive Register 51 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51 RCIDL -- SCKP BRG16 -- WUE ABDEN 51 BAUDCON ABDOVF SPBRGH EUSART Baud Rate Generator Register High Byte 51 SPBRG EUSART Baud Rate Generator Register Low Byte 51 Legend: -- = unimplemented locations read as `0'. Shaded cells are not used for asynchronous reception. Note 1: Reserved in PIC18F2682/2685 devices; always maintain these bits clear. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 239 PIC18F2682/2685/4682/4685 18.2.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake-up due to activity on the RX/DT line while the EUSART is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCON<1>). Once set, the typical receive sequence on RX/DT is disabled and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a Wake-up Signal character for the LIN protocol.) Following a wake-up event, the module generates an RCIF interrupt. The interrupt is generated synchronously to the Q clocks in normal operating modes (Figure 18-8) and asynchronously, if the device is in Sleep mode (Figure 18-9). The interrupt condition is cleared by reading the RCREG register. The WUE bit is automatically cleared once a low-to-high transition is observed on the RX line following the wakeup event. At this point, the EUSART module is in Idle mode and returns to normal operation. This signals to the user that the Sync Break event is over. 18.2.4.1 Special Considerations Using Auto-Wake-up Since auto-wake-up functions by sensing rising edge transitions on RX/DT, information with any state changes before the Stop bit may signal a false End-of- FIGURE 18-8: Character and cause data or framing errors. To work properly, therefore, the initial character in the transmission must be all `0's. This can be 00h (8 bytes) for standard RS-232 devices or 000h (12 bits) for LIN bus. Oscillator start-up time must also be considered, especially in applications using oscillators with longer start-up intervals (i.e., XT or HS mode). The Sync Break (or Wake-up Signal) character must be of sufficient length and be followed by a sufficient interval to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. 18.2.4.2 Special Considerations Using the WUE Bit The timing of WUE and RCIF events may cause some confusion when it comes to determining the validity of received data. As noted, setting the WUE bit places the EUSART in an Idle mode. The wake-up event causes a receive interrupt by setting the RCIF bit. The WUE bit is cleared after this when a rising edge is seen on RX/ DT. The interrupt condition is then cleared by reading the RCREG register. Ordinarily, the data in RCREG will be dummy data and should be discarded. The fact that the WUE bit has been cleared (or is still set), and the RCIF flag is set, should not be used as an indicator of the integrity of the data in RCREG. Users should consider implementing a parallel method in firmware to verify received data integrity. To assure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Bit set by user Auto-Cleared WUE bit(1) RX/DT Line RCIF Cleared due to user read of RCREG Note 1: The EUSART remains in Idle while the WUE bit is set. FIGURE 18-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Bit set by user Auto-Cleared WUE bit(2) RX/DT Line Note 1 RCIF Sleep Ends SLEEP Command Executed Note 1: 2: Cleared due to user read of RCREG If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set. DS39761B-page 240 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 18.2.5 BREAK CHARACTER SEQUENCE The Enhanced EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. The Break character transmit consists of a Start bit, followed by twelve `0' bits and a Stop bit. The frame Break character is sent whenever the SENDB and TXEN bits (TXSTA<3> and TXSTA<5>) are set while the Transmit Shift register is loaded with data. Note that the value of data written to TXREG will be ignored and all `0's will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). Note that the data value written to the TXREG for the Break character is ignored. The write simply serves the purpose of initiating the proper sequence. The TRMT bit indicates when the transmit operation is active or Idle, just as it does during normal transmission. See Figure 18-10 for the timing of the Break character sequence. 18.2.5.1 Break and Sync Transmit Sequence The following sequence will send a message frame header made up of a Break, followed by an Auto-Baud Sync byte. This sequence is typical of a LIN bus master. FIGURE 18-10: Write to TXREG 1. 2. 3. 4. 5. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to set up the Break character. Load the TXREG with a dummy character to initiate transmission (the value is ignored). Write `55h' to TXREG to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware. The Sync character now transmits in the preconfigured mode. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. 18.2.6 RECEIVING A BREAK CHARACTER The Enhanced USART module can receive a Break character in two ways. The first method forces configuration of the baud rate at a frequency of 9/13 the typical speed. This allows for the Stop bit transition to be at the correct sampling location (13 bits for Break versus Start bit and 8 data bits for typical data). The second method uses the auto-wake-up feature described in Section 18.2.4 "Auto-Wake-up on Sync Break Character". By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RCIF interrupt and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABD bit once the TXIF interrupt is observed. SEND BREAK CHARACTER SEQUENCE Dummy Write BRG Output (Shift Clock) TX (pin) Start Bit Bit 0 Bit 1 Bit 11 Stop Bit Break TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB sampled here Auto-Cleared SENDB (Transmit Shift Reg. Empty Flag) (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 241 PIC18F2682/2685/4682/4685 18.3 EUSART Synchronous Master Mode Once the TXREG register transfers the data to the TSR register (occurs in one TCYCLE), the TXREG is empty and the TXIF flag bit (PIR1<4>) is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXIE (PIE1<4>). TXIF is set regardless of the state of enable bit TXIE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. The Synchronous Master mode is entered by setting the CSRC bit (TXSTA<7>). In this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit, SPEN (RCSTA<7>), is set in order to configure the TX and RX pins to CK (clock) and DT (data) lines, respectively. While flag bit TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. TRMT is a read-only bit which is set when the TSR is empty. No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory so it is not available to the user. The Master mode indicates that the processor transmits the master clock on the CK line. Clock polarity is selected with the SCKP bit (BAUDCON<4>); setting SCKP sets the Idle state on CK as high, while clearing the bit sets the Idle state as low. This option is provided to support Microwire devices with this module. 18.3.1 To set up a Synchronous Master Transmission: 1. EUSART SYNCHRONOUS MASTER TRANSMISSION 2. The EUSART transmitter block diagram is shown in Figure 18-3. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The Shift register obtains its data from the Read/Write Transmit Buffer register, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). 3. 4. 5. 6. 7. 8. FIGURE 18-11: Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits SYNC SPEN and CSRC. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. SYNCHRONOUS TRANSMISSION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT pin bit 0 bit 1 bit 2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 bit 7 RC6/TX/CK pin (SCKP = 0) bit 0 bit 1 bit 7 Word 2 Word 1 RC6/TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit Note: `1' `1' Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words. DS39761B-page 242 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 FIGURE 18-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 18-7: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51 RCSTA TXREG TXSTA BAUDCON EUSART Transmit Register 51 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 51 SPBRGH EUSART Baud Rate Generator Register High Byte 51 SPBRG EUSART Baud Rate Generator Register Low Byte 51 Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous master transmission. Note 1: Reserved in PIC18F2682/2685 devices; always maintain these bits clear. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 243 PIC18F2682/2685/4682/4685 18.3.2 EUSART SYNCHRONOUS MASTER RECEPTION 3. 4. 5. 6. Ensure bits CREN and SREN are clear. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if the enable bit RCIE was set. 8. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTA<5>), or the Continuous Receive Enable bit, CREN (RCSTA<4>). Data is sampled on the RX pin on the falling edge of the clock. If enable bit SREN is set, only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence. To set up a Synchronous Master Reception: 1. 2. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. FIGURE 18-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RC7/TX/CK pin (SCKP = 0) RC7/TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit `0' `0' RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 18-8: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 INTCON GIE/GIEH PEIE/GIEL TMR0IE PIR1 PSPIF(1) ADIF RCIF PIE1 PSPIE(1) ADIE IPR1 PSPIP(1) SPEN RCSTA RCREG TXSTA BAUDCON Bit 0 Reset Values on page INT0IF RBIF 49 TMR2IF TMR1IF 52 TMR2IE TMR1IE 52 CCP1IP TMR2IP TMR1IP 52 FERR OERR RX9D Bit 3 Bit 2 INT0IE RBIE TMR0IF TXIF SSPIF CCP1IF RCIE TXIE SSPIE CCP1IE ADIP RCIP TXIP SSPIP RX9 SREN CREN ADDEN Bit 1 EUSART Receive Register 51 51 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 51 SPBRGH EUSART Baud Rate Generator Register High Byte 51 SPBRG EUSART Baud Rate Generator Register Low Byte 51 Legend: Note 1: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous master reception. Reserved in PIC18F2682/2685 devices; always maintain these bits clear. DS39761B-page 244 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 18.4 EUSART Synchronous Slave Mode To set up a Synchronous Slave Transmission: 1. Synchronous Slave mode is entered by clearing bit, CSRC (TXSTA<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 18.4.1 EUSART SYNCHRONOUS SLAVE TRANSMIT 2. 3. 4. 5. 6. The operation of the Synchronous Master and Slave modes are identical, except in the case of the Sleep mode. 7. 8. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: a) b) c) d) e) Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. Clear bits CREN and SREN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting enable bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREGx register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. The first word will immediately transfer to the TSR register and transmit. The second word will remain in the TXREG register. Flag bit TXIF will not be set. When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set. If enable bit TXIE is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. TABLE 18-9: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 INTCON GIE/GIEH PEIE/GIEL PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51 RCSTA TXREG EUSART Transmit Register 51 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN SPBRGH EUSART Baud Rate Generator Register High Byte 51 SPBRG EUSART Baud Rate Generator Register Low Byte 51 TXSTA 51 51 Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous slave transmission. Note 1: Reserved in PIC18F2682/2685 devices; always maintain these bits clear. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 245 PIC18F2682/2685/4682/4685 18.4.2 EUSART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep or any Idle mode, and bit SREN, which is a "don't care" in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode. Once the word is received, the RSR register will transfer the data to the RCREG register; if the RCIE enable bit is set, the interrupt generated will wake the chip from the low-power mode. If the global interrupt is enabled, the program will branch to the interrupt vector. 2. 3. 4. 5. 6. 7. 8. 9. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. To enable reception, set enable bit CREN. Flag bit RCIF will be set when reception is complete. An interrupt will be generated if enable bit RCIE was set. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing bit CREN. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51 RCSTA RCREG TXSTA EUSART Receive Register 51 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51 BAUDCON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 51 SPBRGH EUSART Baud Rate Generator Register High Byte 51 SPBRG EUSART Baud Rate Generator Register Low Byte 51 Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous slave reception. Note 1: Reserved in PIC18F2682/2685 devices; always maintain these bits clear. DS39761B-page 246 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 19.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The module has five registers: The Analog-to-Digital (A/D) converter module has 8 inputs for the PIC18F2682/2685 devices and 11 for the PIC18F4682/4685 devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number. REGISTER 19-1: * * * * * A/D Result High Register (ADRESH) A/D Result Low Register (ADRESL) A/D Control Register 0 (ADCON0) A/D Control Register 1 (ADCON1) A/D Control Register 2 (ADCON2) The ADCON0 register, shown in Register 19-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 19-2, configures the functions of the port pins. The ADCON2 register, shown in Register 19-3, configures the A/D clock source, programmed acquisition time and justification. ADCON0: A/D CONTROL REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-2 CHS3:CHS0: Analog Channel Select bits 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5)(1,2) 0110 = Channel 6 (AN6)(1,2) 0111 = Channel 7 (AN7)(1,2) 1000 = Channel 8 (AN8) 1001 = Channel 9 (AN9) 1010 = Channel 10 (AN10) 1011 = Unused 1100 = Unused 1101 = Unused 1110 = Unused 1111 = Unused bit 1 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress 0 = A/D Idle bit 0 ADON: A/D On bit 1 = A/D converter module is enabled 0 = A/D converter module is disabled Note 1: 2: x = Bit is unknown These channels are not implemented on PIC18F2682/2685 devices. Performing a conversion on unimplemented channels will return full-scale measurements. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 247 PIC18F2682/2685/4682/4685 REGISTER 19-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0(1) R/W-q(1) R/W-q(1) R/W-q(1) -- -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared PCFG3: PCFG0 AN4 AN3 AN2 AN1 AN0 PCFG3:PCFG0: A/D Port Configuration Control bits: AN5(2) bit 3-0 AN6(2) VCFG0: Voltage Reference Configuration bit (VREF+ source) 1 = VREF+ (AN3) 0 = AVDD AN7(2) bit 4 AN8 VCFG1: Voltage Reference Configuration bit (VREF- source) 1 = VREF- (AN2) 0 = AVSS AN9 Unimplemented: Read as `0' bit 5 AN10 bit 7-6 0000(1) A A A A A A A A A A A 0001 A A A A A A A A A A A 0010 A A A A A A A A A A A 0011 A A A A A A A A A A A 0100 A A A A A A A A A A A 0101 D A A A A A A A A A A 0110 D D A A A A A A A A A 0111(1) D D D A A A A A A A A 1000 D D D D A A A A A A A 1001 D D D D D A A A A A A 1010 D D D D D D A A A A A 1011 D D D D D D D A A A A 1100 D D D D D D D D A A A 1101 D D D D D D D D D A A 1110 D D D D D D D D D D A 1111 D D D D D D D D D D D A = Analog input Note 1: 2: x = Bit is unknown D = Digital I/O The POR value of the PCFG bits depends on the value of the PBADEN bit in Configuration Register 3H. When PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111. AN5 through AN7 are available only on PIC18F4682/4685 devices. DS39761B-page 248 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 19-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM -- ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as `0' bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD(1) bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Select bits 111 = FRC (clock derived from A/D RC oscillator)(1) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 Note 1: x = Bit is unknown If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 249 PIC18F2682/2685/4682/4685 The analog reference voltage is software selectable to either the device's positive and negative supply voltage (AVDD and AVSS), or the voltage level on the RA3/AN3/ VREF+ and RA2/AN2/VREF-/CVREF pins. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. Each port pin associated with the A/D converter can be configured as an analog input, or as a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH/ ADRESL registers, the GO/DONE bit (ADCON0 register) is cleared and A/D Interrupt Flag bit, ADIF, is set. The block diagram of the A/D module is shown in Figure 19-1. The A/D converter has a unique feature of being able to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived from the A/D converter's internal RC oscillator. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. FIGURE 19-1: A/D BLOCK DIAGRAM CHS3:CHS0 1010 1001 1000 0110 AN6(1) 0101 AN5(1) 0011 0010 0001 VCFG1:VCFG0 AVDD(2) Reference Voltage VREF+ X0 X1 1X VREF- 0X AN8 AN7(1) 0100 (Input Voltage) AN9 0111 VAIN 10-Bit A/D Converter AN10 0000 AN4 AN3 AN2 AN1 AN0 AVSS(2) Note 1: 2: Channels AN5 through AN7 are not available on PIC18F2682/2685 devices. I/O pins have diode protection to VDD and VSS. DS39761B-page 250 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 The value in the ADRESH/ADRESL registers is not modified for a Power-on Reset. The ADRESH/ADRESL registers will contain unknown data after a Power-on Reset. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as inputs. To determine acquisition time, see Section 19.1 "A/D Acquisition Requirements". After this acquisition time has elapsed, the A/D conversion can be started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual start of the conversion. The following steps should be followed to perform an A/D conversion: 1. Configure the A/D module: * Configure analog pins, voltage reference and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D acquisition time (ADCON2) * Select A/D conversion clock (ADCON2) * Turn on A/D module (ADCON0) Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit Wait the required acquisition time (if required). Start conversion: * Set GO/DONE bit (ADCON0 register) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared 2. 3. 4. 5. OR * Waiting for the A/D interrupt Read A/D Result registers (ADRESH:ADRESL); clear bit, ADIF, if required. For next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before next acquisition starts. 6. 7. FIGURE 19-2: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V Rs VAIN RIC 1k ANx CPIN 5 pF VT = 0.6V SS RSS ILEAKAGE 500 nA CHOLD = 120 pF VSS Legend: CPIN VT ILEAKAGE RIC SS CHOLD RSS (c) 2007 Microchip Technology Inc. = Input Capacitance = Threshold Voltage = Leakage Current at the pin due to various junctions = Interconnect Resistance = Sampling Switch = Sample/Hold Capacitance (from DAC) = Sampling Switch Resistance Preliminary VDD 6V 5V 4V 3V 2V 5 6 7 8 9 10 11 Sampling Switch (k) DS39761B-page 251 PIC18F2682/2685/4682/4685 19.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 19-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 2.5 k. After the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. Note: Example 19-3 shows the calculation of the minimum required acquisition time TACQ. This calculation is based on the following application system assumptions: CHOLD Rs Conversion Error VDD Temperature VHOLD = = = = = 120 pF 2.5 k 1/2 LSb 5V Rss = 7 k 50C (system max.) 0V @ time = 0 When the conversion is started, the holding capacitor is disconnected from the input pin. EQUATION 19-1: TACQ To calculate the minimum acquisition time, Equation 19-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. A/D ACQUISITION TIME = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 19-2: VHOLD = or TC = A/D MINIMUM CHARGING TIME (VREF - (VREF/2048)) * (1 - e(-Tc/CHOLD(RIC + RSS + RS))) -(CHOLD)(RIC + RSS + RS) ln(1/2048) EQUATION 19-3: CALCULATING THE MINIMUM REQUIRED A/D ACQUISITION TIME TACQ = TAMP + TC + TCOFF TAMP = 5 s TCOFF = (Temp - 25C)(0.05 s/C) (50C - 25C)(0.05 s/C) 1.25 s Temperature coefficient is only required for temperatures > 25C. Below 25C, TCOFF = 0 ms. TC = -(CHOLD)(RIC + RSS + RS) ln(1/2047) s -(120 pF) (1 k + 7 k + 2.5 k) ln(0.0004883) s 9.61 s TACQ = 5 s + 1.25 s + 9.61 s 12.86 s DS39761B-page 252 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 19.2 Selecting and Configuring Automatic Acquisition Time 19.3 The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit. This occurs when the ACQT2:ACQT0 bits (ADCON2<5:3>) remain in their Reset state (`000') and is compatible with devices that do not offer programmable acquisition times. If desired, the ACQT bits can be set to select a programmable acquisition time for the A/D module. When the GO/DONE bit is set, the A/D module continues to sample the input for the selected acquisition time, then automatically begins a conversion. Since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the GO/DONE bit. Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as TAD. The A/D conversion requires 11 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable. There are seven possible options for TAD: * * * * * * * 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC Internal RC Oscillator For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible, but greater than the minimum TAD (approximately 2 s, see parameter 130 for more information). Table 19-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. TABLE 19-1: TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Maximum Device Frequency PIC18F2682/2685/4682/4685 PIC18LF2682/2685/4682/4685(4) Operation ADCS2:ADCS0 2 TOSC 000 4 TOSC 100 5.71 MHz 2.86 MHz 8 TOSC 001 11.43 MHz 5.72 MHz 16 TOSC 101 22.86 MHz 11.43 MHz 32 TOSC 010 40.0 MHz 22.86 MHz 64 TOSC 110 40.0 MHz 22.86 MHz RC(3) Note 1: 2: 3: 4: x11 2.86 MHz 1.00 MHz(1) 1.43 kHz 1.00 MHz(2) The RC source has a typical TAD time of 1.2 s. The RC source has a typical TAD time of 2.5 s. For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D accuracy may be out of specification. Low-power (PIC18LFXXXX) devices only. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 253 PIC18F2682/2685/4682/4685 19.4 Operation in Power-Managed Modes 19.5 The selection of the automatic acquisition time and A/D conversion clock is determined in part, by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device is in a power-managed mode, the ACQT2:ACQT0 and ADCS2:ADCS0 bits in ADCON2 should be updated in accordance with the clock source to be used in that mode. After entering the mode, an A/D acquisition or conversion may be started. Once started, the device should continue to be clocked by the same clock source until the conversion has been completed. If desired, the device may be placed into the corresponding Idle mode during the conversion. If the device clock frequency is less than 1 MHz, the A/D RC clock source should be selected. The ADCON1, TRISA, TRISB and TRISE registers all configure the A/D port pins. The port pins needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS3:CHS0 bits and the TRIS bits. Note 1: When reading the PORT register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally configured input will be accurately converted. Operation in the Sleep mode requires the A/D FRC clock to be selected. If the ACQT2:ACQT0 bits are set to `000' and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the SLEEP instruction and entry to Sleep mode. The IDLEN bit (OSCCON<7>) must have already been cleared prior to starting the conversion. DS39761B-page 254 Configuring Analog Port Pins Preliminary 2: Analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the device's specification limits. 3: The PBADEN bit in Configuration Register 3H configures PORTB pins to reset as analog or digital pins by controlling how the PCFG0 bits in ADCON1 are reset. (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 19.6 A/D Conversions Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample. This means the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). Figure 19-3 shows the operation of the A/D converter after the GO/DONE bit has been set and the ACQT2:ACQT0 bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins. Figure 19-4 shows the operation of the A/D converter after the GO/DONE bit has been set, the ACQT2:ACQT0 bits are set to `010' and a 4 TAD acquisition time is selected before the conversion starts. After the A/D conversion is completed or aborted, a 2 TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. Note: FIGURE 19-3: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b4 b1 b0 b6 b7 b2 b9 b8 b3 b5 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit On the following cycle: ADRESH:ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) FIGURE 19-4: TAD Cycles TACQT Cycles 1 2 3 4 Automatic Acquisition Time 1 3 4 5 6 7 8 9 10 11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts (Holding capacitor is disconnected) Set GO/DONE bit (Holding capacitor continues acquiring input) (c) 2007 Microchip Technology Inc. 2 On the following cycle: ADRESH:ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. Preliminary DS39761B-page 255 PIC18F2682/2685/4682/4685 19.7 Use of the ECCP1 Trigger An A/D conversion can be started by the "Special Event Trigger" of the ECCP1 module. This requires that the ECCP1M3:ECCP1M0 bits (ECCP1CON<3:0>) be programmed as `1011' and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion and the Timer1 (or Timer3) counter will be reset to zero. Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal TABLE 19-2: Name software overhead (moving ADRESH/ADRESL to the desired location). The appropriate analog input channel must be selected and the minimum acquisition period is either timed by the user, or an appropriate TACQ time selected before the "Special Event Trigger" sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), the "Special Event Trigger" will be ignored by the A/D module, but will still reset the Timer1 (or Timer3) counter. REGISTERS ASSOCIATED WITH A/D OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INT0IE RBIE TMR0IF INT0IF RBIF 49 INTCON GIE/GIEH PEIE/GIEL TMR0IE IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR2 OSCFIP CMIP(1) -- EEIP BCLIP HLVDIP TMR3IP ECCP1IP(1) 51 PIR2 OSCFIF CMIF(1) -- EEIF BCLIF HLVDIF TMR3IF ECCP1IF(1) 52 OSCFIE CMIE(1) TMR3IE ECCP1IE(1) 52 PIE2 -- EEIE BCLIE HLVDIE ADRESH A/D Result Register High Byte 50 ADRESL 50 A/D Result Register Low Byte ADCON0 -- -- CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 50 ADCON1 -- -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 50 ADCON2 ADFM -- ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 51 PORTA RA7(2) RA6(2) RA5 RA4 RA3 RA2 RA1 RA0 52 RB2 RB1 RB0 52 TRISA PORTB TRISA7(2) TRISA6(2) PORTA Data Direction Register RB7 RB6 RB5 RB4 RB3 52 TRISB PORTB Data Direction Register 52 LATB LATB Data Output Register 52 PORTE(4) (4) TRISE LATE(4) Legend: Note 1: 2: 3: 4: -- -- -- -- RE3(3) RE2(1) RE1(1) RE0(1) 52 IBF OBF IBOV PSPMODE -- TRISE2 TRISE1 TRISE0 52 -- -- -- -- -- LATE Data Output Register 52 -- = unimplemented, read as `0'. Shaded cells are not used for A/D conversion. These bits are unimplemented on PIC18F2682/2685 devices; always maintain these bits clear. These pins may be configured as port pins depending on the oscillator mode selected. RE3 port bit is available only as an input pin when the MCLRE Configuration bit is `0'. These registers are not implemented on PIC18F2682/2685 devices. DS39761B-page 256 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 20.0 COMPARATOR MODULE Note: Comparators are only available in 40/44-pin devices (PIC18F4682/4685). The CMCON register (Register 20-1) selects the comparator input and output configuration. Block diagrams of the various comparator configurations are shown in Figure 20-1. The analog comparator module contains two comparators that can be configured in a variety of ways. The inputs can be selected from the analog inputs multiplexed with pins RA0 through RA5, as well as the on-chip voltage reference (see Section 21.0 "Comparator Voltage Reference Module"). The digital outputs (normal or inverted) are available at the pin level and can also be read through the control register. REGISTER 20-1: CMCON: COMPARATOR CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1: 1 = C2 VIN+ < C2 VIN0 = C2 VIN+ > C2 VIN- bit 6 C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1: 1 = C1 VIN+ < C1 VIN0 = C1 VIN+ > C1 VIN- bit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted bit 4 C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted bit 3 CIS: Comparator Input Switch bit When CM2:CM0 = 110: 1 = C1 VIN- connects to RD0/PSP0/C1IN+ C2 VIN- connects to RD2/PSP2/C2IN+ 0 = C1 VIN- connects to RD1/PSP1/C1INC2 VIN- connects to RD3/PSP3/C2IN- bit 2-0 CM2:CM0: Comparator Mode bits Figure 20-1 shows the Comparator modes and the CM2:CM0 bit settings. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 257 PIC18F2682/2685/4682/4685 20.1 Comparator Configuration There are eight modes of operation for the comparators, shown in Figure 20-1. Bits CM2:CM0 of the CMCON register are used to select these modes. The TRISA register controls the data direction of the comparator pins for each mode. If the Comparator mode is FIGURE 20-1: RD1/PSP1/C1IN- A VIN- RD0/PSP0/C1IN+ A VIN+ A VIN- RD2/PSP2/C2IN+ Note: Comparator interrupts should be disabled during a Comparator mode change; otherwise, a false interrupt may occur. COMPARATOR I/O OPERATING MODES Comparators Reset (POR Default Value) CM2:CM0 = 000 RD3/PSP3/C2IN- changed, the comparator output level may not be valid for the specified mode change delay shown in Section 27.0 "Electrical Characteristics". A VIN+ Comparators Off CM2:CM0 = 111 C1 Off (Read as `0') C2 Off (Read as `0') A VIN- RD0/PSP0/C1IN+ A VIN+ A VIN- A VIN+ D VIN- RD0/PSP0/C1IN+ D VIN+ RD3/PSP3/C2IN- D VIN- D VIN+ RD2/PSP2/C2IN+ C1 Off (Read as `0') C2 Off (Read as `0') Two Independent Comparators with Outputs CM2:CM0 = 011 Two Independent Comparators CM2:CM0 = 010 RD1/PSP1/C1IN- RD1/PSP1/C1IN- C1 C1OUT RD1/PSP1/C1IN- A VIN- RD0/PSP0/C1IN+ A VIN+ C1 C1OUT C2 C2OUT RE1/WR/AN6/C1OUT* RD3/PSP3/C2INRD2/PSP2/C2IN+ C2 C2OUT RD3/PSP3/C2INRD2/PSP2/C2IN+ A VIN- A VIN+ RE2/CS/AN7/C2OUT* Two Common Reference Comparators CM2:CM0 = 100 RD1/PSP1/C1INRD0/PSP0/C1IN+ A VIN- A VIN+ A VIN- D VIN+ Two Common Reference Comparators with Outputs CM2:CM0 = 101 RD1/PSP1/C1IN- C1 C1OUT RD0/PSP0/C1IN+ A VIN- A VIN+ C1 C1OUT C2 C2OUT RE1/WR/AN6/C1OUT* RD3/PSP3/C2INRD2/PSP2/C2IN+ C2 C2OUT RD3/PSP3/C2INRD2/PSP2/C2IN+ A VIN- D VIN+ RE2/CS/AN7/C2OUT* Four Inputs Multiplexed to Two Comparators CM2:CM0 = 110 One Independent Comparator with Output CM2:CM0 = 001 RD1/PSP1/C1IN- A VIN- RD0/PSP0/C1IN+ A VIN+ C1 C1OUT RE1/WR/AN6/C1OUT* D VIN- RD2/PSP2/C2IN+ D VIN+ RD3/PSP3/C2IN- C2 RD1/PSP1/ A C1INRD0/PSP0/ A C1IN+ CIS = 0 CIS = 1 RD3/PSP3/ A C2INRD2/PSP2/ A C2IN+ CIS = 0 CIS = 1 Off (Read as `0') VINVIN+ C1 C1OUT C2 C2OUT VINVIN+ CVREF From VREF Module A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch * Setting the TRISA<5:4> bits will disable the comparator outputs by configuring the pins as inputs. DS39761B-page 258 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 20.2 20.3.2 Comparator Operation A single comparator is shown in Figure 20-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure 20-2 represent the uncertainty, due to input offsets and response time. 20.3 Comparator Reference Depending on the comparator operating mode, either an external or internal voltage reference may be used. The analog signal present at VIN- is compared to the signal at VIN+ and the digital output of the comparator is adjusted accordingly (Figure 20-2). FIGURE 20-2: SINGLE COMPARATOR VIN+ + VIN- - The internal reference is only available in the mode where four inputs are multiplexed to two comparators (CM2:CM0 = 110). In this mode, the internal voltage reference is applied to the VIN+ pin of both comparators. 20.4 Comparator Response Time Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. Otherwise, the maximum delay of the comparators should be used (see Section 27.0 "Electrical Characteristics"). Comparator Outputs The comparator outputs are read through the CMCON register. These bits are read-only. The comparator outputs may also be directly output to the RE1 and RE2 I/O pins. When enabled, multiplexors in the output path of the RE1 and RE2 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. Figure 20-3 shows the comparator output block diagram. VINVIN+ Output 20.3.1 The comparator module also allows the selection of an internally generated voltage reference from the comparator voltage reference module. This module is described in more detail in Section 21.0 "Comparator Voltage Reference Module". 20.5 Output INTERNAL REFERENCE SIGNAL The TRISE bits will still function as an output enable/ disable for the RE1 and RE2 pins while in this mode. EXTERNAL REFERENCE SIGNAL When external voltage references are used, the comparator module can be configured to have the comparators operate from the same or different reference sources. However, threshold detector applications may require the same reference. The reference signal must be between VSS and VDD and can be applied to either pin of the comparator(s). (c) 2007 Microchip Technology Inc. The polarity of the comparator outputs can be changed using the C2INV and C1INV bits (CMCON<5:4>). Note 1: When reading the PORT register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert an analog input according to the Schmitt Trigger input specification. Preliminary 2: Analog levels on any pin defined as a digital input may cause the input buffer to consume more current than is specified. DS39761B-page 259 PIC18F2682/2685/4682/4685 + To RE1 or RE2 pin - Port pins COMPARATOR OUTPUT BLOCK DIAGRAM MULTIPLEX FIGURE 20-3: D Q Bus Data CxINV EN Read CMCON D Q EN CL From other Comparator Reset 20.6 Comparator Interrupts 20.7 The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred. The CMIF bit (PIR2<6>) is the Comparator Interrupt Flag. The CMIF bit must be reset by clearing it. Since it is also possible to write a `1' to this register, a simulated interrupt may be initiated. Both the CMIE bit (PIE2<6>) and the PEIE bit (INTCON<6>) must be set to enable the interrupt. In addition, the GIE bit (INTCON<7>) must also be set. If any of these bits are clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt condition occurs. Note: If a change in the CMCON register (C1OUT or C2OUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF (PIR registers) interrupt flag may not get set. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Set CMIF bit Comparator Operation During Sleep When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional if enabled. This interrupt will wake-up the device from Sleep mode, when enabled. While the comparator is powered up, higher Sleep currents than shown in the power-down current specification will occur. Each operational comparator will consume additional current, as shown in the comparator specifications. To minimize power consumption while in Sleep mode, turn off the comparators (CM2:CM0 = 111) before entering Sleep. If the device wakes up from Sleep, the contents of the CMCON register are not affected. 20.8 Effects of a Reset A device Reset forces the CMCON register to its Reset state, causing the comparator module to be in the Comparator Reset mode (CM2:CM0 = 000). This ensures that all potential inputs are analog inputs. Device current is minimized when analog inputs are present at Reset time. The comparators are powered down during the Reset interval. Any read or write of CMCON will end the mismatch condition. Clear flag bit CMIF. A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared. DS39761B-page 260 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 20.9 Analog Input Connection Considerations range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. A simplified circuit for an analog input is shown in Figure 20-4. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this FIGURE 20-4: COMPARATOR ANALOG INPUT MODEL VDD VT = 0.6V RS < 10k RIC Comparator Input AIN CPIN 5 pF VA VT = 0.6V ILEAKAGE 500 nA VSS Legend: TABLE 20-1: Name CMCON(3) (3) CVRCON INTCON CPIN VT ILEAKAGE RIC RS VA = = = = = = Input Capacitance Threshold Voltage Leakage Current at the pin due to various junctions Interconnect Resistance Source Impedance Analog Voltage REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 51 CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 51 INT0IE RBIE TMR0IF INT0IF RBIF GIE/GIEH PEIE/GIEL TMR0IE (2) 52 (2) IPR2 OSCFIP CMIP -- EEIP BCLIP HLVDIP TMR3IP ECCP1IP 51 PIR2 OSCFIF CMIF(2) -- EEIF BCLIF HLVDIF TMR3IF ECCP1IF(2) 52 OSCFIE CMIE(2) -- EEIE BCLIE HLVDIE TMR3IE ECCP1IE(2) 52 RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 52 PIE2 PORTA (1) LATA6 (1) LATA Data Output Register LATA LATA7 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Register Legend: Note 1: 2: 3: 52 52 -- = unimplemented, read as `0'. Shaded cells are unused by the comparator module. PORTA pins are enabled based on oscillator configuration. These bits are available in PIC18F4682/4685 devices and reserved in PIC18F2682/2685 devices. These registers are unimplemented on PIC18F2682/2685 devices. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 261 PIC18F2682/2685/4682/4685 NOTES: DS39761B-page 262 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 21.0 COMPARATOR VOLTAGE REFERENCE MODULE Note: Comparators are only available in 40/44-pin devices (PIC18F4682/4685). The comparator voltage reference is a 16-tap resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. A block diagram is of the module shown in Figure 21-1. The resistor ladder is segmented to provide two ranges of CVREF values and has a power-down function to conserve power when the reference is not being used. The module's supply reference can be provided from either device VDD/VSS or an external voltage reference. 21.1 Configuring the Comparator Voltage Reference The voltage reference module is controlled through the CVRCON register (Register 21-1). The comparator voltage reference provides two ranges of output REGISTER 21-1: voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps selected by the CVREF selection bits (CVR3:CVR0), with one range offering finer resolution. The equations used to calculate the output of the comparator voltage reference are as follows: If CVRR = 1: CVREF = ((CVR3:CVR0)/24) x CVRSRC If CVRR = 0: CVREF = (CVDD x 1/4) + (((CVR3:CVR0)/32) x CVRSRC) The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF- that are multiplexed with RA2 and RA3. The voltage source is selected by the CVRSS bit (CVRCON<4>). The settling time of the comparator voltage reference must be considered when changing the CVREF output (see Table 27-3 in Section 27.0 "Electrical Characteristics"). CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit(1) 1 = CVREF voltage level is also output on the RA0/AN0/CVREF pin 0 = CVREF voltage is disconnected from the RA0/AN0/CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = 0.00 CVRSRC to 0.75 CVRSRC, with CVRSRC/24 step size 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = (VREF+) - (VREF-) 0 = Comparator reference source, CVRSRC = VDD - VSS bit 3-0 CVR3:CVR0: Comparator VREF Value Selection bits (0 (CVR3:CVR0) 15) When CVRR = 1: CVREF = ((CVR3:CVR0)/24) * (CVRSRC) When CVRR = 0: CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32) * (CVRSRC) Note 1: CVROE overrides the TRISA<0> bit setting. If enabled for output, RA2 must also be configured as an input by setting TRISA<2> to `1'. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 263 PIC18F2682/2685/4682/4685 FIGURE 21-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ VDD CVRSS = 1 8R CVRSS = 0 CVR3:CVR0 R CVREN R 16-to-1 MUX R R 16 Steps CVREF R R R CVRR VREF- 8R CVRSS = 1 CVRSS = 0 21.2 Voltage Reference Accuracy/Error The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 21-1) keep CVREF from approaching the reference source rails. The voltage reference is derived from the reference source; therefore, the CVREF output changes with fluctuations in that source. The tested absolute accuracy of the voltage reference can be found in Section 27.0 "Electrical Characteristics". 21.3 Operation During Sleep When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the CVRCON register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 21.4 Effects of a Reset A device Reset disables the voltage reference by clearing bit CVREN (CVRCON<7>). This Reset also disconnects the reference from the RA0 pin by clearing bit, CVROE (CVRCON<6>), and selects the highvoltage range by clearing bit, CVRR (CVRCON<5>). The CVR value select bits are also cleared. 21.5 Connection Considerations The voltage reference module operates independently of the comparator module. The output of the reference generator may be connected to the RA0 pin if the TRISA<0> bit and the CVROE bit are both set. Enabling the voltage reference output onto the RA0 pin, with an input signal present, will increase current consumption. Connecting RA0 as a digital output with CVRSS enabled will also increase current consumption. The RA0 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to VREF. Figure 21-2 shows an example buffering technique. DS39761B-page 264 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 FIGURE 21-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18F4682/4685 CVREF Module R(1) Voltage Reference Output Impedance + - RA0 CVREF Output Note 1: R is dependent upon the voltage reference configuration bits, CVRCON<3:0> and CVRCON<5>. TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 51 C1OUT C2INV C1INV CIS CM2 CM1 CM0 51 Name Bit 7 Bit 6 CVRCON(2) CVREN CMCON(2) C2OUT TRISA TRISA7 (1) TRISA6(1) PORTA Data Direction Register 52 Legend: Shaded cells are not used with the comparator voltage reference. Note 1: PORTA pins are enabled based on oscillator configuration. 2: These registers are unimplemented on PIC18F2682/2685 devices. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 265 PIC18F2682/2685/4682/4685 NOTES: DS39761B-page 266 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 22.0 HIGH/LOW-VOLTAGE DETECT (HLVD) PIC18F2682/2685/4682/4685 devices have a High/ Low-Voltage Detect module (HLVD). This is a programmable circuit that allows the user to specify both a device voltage trip point and the direction of change from that point. If the device experiences an excursion past the trip point in that direction, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. REGISTER 22-1: The High/Low-Voltage Detect Control register (Register 22-1) completely controls the operation of the HLVD module. This allows the circuitry to be "turned off" by the user under software control, which minimizes the current consumption for the device. The block diagram for the HLVD module is shown in Figure 22-1. HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 VDIRMAG -- IRVST HLVDEN HLVDL3(1) HLVDL2(1) HLVDL1(1) HLVDL0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 VDIRMAG: Voltage Direction Magnitude Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL3:HLDVL0) 0 = Event occurs when voltage equals or falls below trip point (HLVDL3:HLVDL0) bit 6 Unimplemented: Read as `0' bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage range and the HLVD interrupt should not be enabled bit 4 HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD enabled 0 = HLVD disabled bit 3-0 HLVDL3:HLVDL0: High/Low-Voltage Detection Limit bits(1) 1111 = External analog input is used (input comes from the HLVDIN pin) 1110 = 4.48V-4.69V 1101 = 4.23V-4.43V 1100 = 4.01V-4.20V 1011 = 3.81V-3.99V 1010 = 3.63V-3.80V 1001 = 3.46V-3.63V 1000 = 3.31V-3.47V 0111 = 3.05V-3.19V 0110 = 2.82V-2.95V 0101 = 2.72V-2.85V 0100 = 2.54V-2.66V 0011 = 2.38V-2.49V 0010 = 2.31V-2.42V 0001 = 2.18V-2.28V 0000 = 2.12V-2.22V Note 1: HLVDL3:HLVDL0 modes that result in a trip point below the valid operating voltage of the device are not tested. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 267 PIC18F2682/2685/4682/4685 The module is enabled by setting the HLVDEN bit. Each time that the HLVD module is enabled, the circuitry requires some time to stabilize. The IRVST bit is a read-only bit and is used to indicate when the circuit is stable. The module can only generate an interrupt after the circuit is stable and IRVST is set. event, depending on the configuration of the module. When the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the internal reference voltage generated by the voltage reference module. The comparator then generates an interrupt signal by setting the HLVDIF bit. The VDIRMAG bit determines the overall operation of the module. When VDIRMAG is cleared, the module monitors for drops in VDD below a predetermined set point. When the bit is set, the module monitors for rises in VDD above the set point. The trip point voltage is software programmable to any one of sixteen values. The trip point is selected by programming the HLVDL3:HLVDL0 bits (HLVDCON<3:0>). 22.1 Operation When the HLVD module is enabled, a comparator uses an internally generated reference voltage as the set point. The set point is compared with the trip point, where each node in the resistor divider represents a trip point voltage. The "trip point" voltage is the voltage level at which the device detects a high or low-voltage FIGURE 22-1: VDD HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT) Externally Generated Trip Point VDD HLVDL3:HLVDL0 HLVDCON Register HLVDEN HLVDIN 16-to-1 MUX HLVDIN The HLVD module has an additional feature that allows the user to supply the trip voltage to the module from an external source. This mode is enabled when bits HLVDL3:HLVDL0 are set to `1111'. In this state, the comparator input is multiplexed from the external input pin, HLVDIN. This gives users flexibility because it allows them to configure the High/Low-Voltage Detect interrupt to occur at any voltage in the valid operating range. VDIRMAG Set HLVDIF HLVDEN Internal Voltage Reference BOREN DS39761B-page 268 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 22.2 HLVD Setup The following steps are needed to set up the HLVD module: 1. 2. 3. 4. 5. 6. Disable the module by clearing the HLVDEN bit (HLVDCON<4>). Write the value to the HLVDL3:HLVDL0 bits that select the desired HLVD trip point. Set the VDIRMAG bit to detect high voltage (VDIRMAG = 1) or low voltage (VDIRMAG = 0). Enable the HLVD module by setting the HLVDEN bit. Clear the HLVD interrupt flag (PIR2<2>), which may have been set from a previous interrupt. Enable the HLVD interrupt if interrupts are desired by setting the HLVDIE and GIE bits (PIE<2> and INTCON<7>). An interrupt will not be generated until the IRVST bit is set. 22.3 22.4 HLVD Start-up Time The internal reference voltage of the HLVD module, specified in electrical specification parameter D420, may be used by other internal circuitry, such as the Programmable Brown-out Reset. If the HLVD or other circuits using the voltage reference are disabled to lower the device's current consumption, the reference voltage circuit will require time to become stable before a low or high-voltage condition can be reliably detected. This start-up time, TIRVST, is an interval that is independent of device clock speed. It is specified in electrical specification parameter 36. Current Consumption When the module is enabled, the HLVD comparator and voltage divider are enabled and will consume static current. The total current consumption, when enabled, is specified in electrical specification parameter D022B. FIGURE 22-2: Depending on the application, the HLVD module does not need to be operating constantly. To decrease the current requirements, the HLVD circuitry may only need to be enabled for short periods where the voltage is checked. After doing the check, the HLVD module may be disabled. The HLVD interrupt flag is not enabled until TIRVST has expired and a stable reference voltage is reached. For this reason, brief excursions beyond the set point may not be detected during this interval. Refer to Figure 22-2 or Figure 22-3. LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0) CASE 1: HLVDIF may not be set VDD VLVD HLVDIF Enable HLVD TIRVST IRVST Internal Reference is stable HLVDIF cleared in software CASE 2: VDD VLVD HLVDIF Enable HLVD TIRVST IRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 269 PIC18F2682/2685/4682/4685 FIGURE 22-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) CASE 1: HLVDIF may not be set VLVD VDD HLVDIF Enable HLVD TIRVST IRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VLVD VDD HLVDIF Enable HLVD TIRVST IRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists FIGURE 22-4: Applications In many applications, the ability to detect a drop below, or rise above a particular threshold is desirable. For example, the HLVD module could be periodically enabled to detect Universal Serial Bus (USB) attach or detach. This assumes the device is powered by a lower voltage source than the USB when detached. An attach would indicate a high-voltage detect from, for example, 3.3V to 5V (the voltage on USB) and vice versa for a detach. This feature could save a design a few extra components and an attach signal (input pin). VA VB For general battery applications, Figure 22-4 shows a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage VA, the HLVD logic generates an interrupt at time TA. The interrupt could cause the execution of an ISR, which would allow the application to perform "housekeeping tasks" and perform a controlled shutdown before the device voltage exits the valid operating range at TB. The HLVD, thus, would give the application a time window, represented by the difference between TA and TB, to safely exit. DS39761B-page 270 TYPICAL LOW-VOLTAGE DETECT APPLICATION Voltage 22.5 Preliminary Time TA TB Legend: VA = HLVD trip point VB = Minimum valid device operating voltage (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 22.6 Operation During Sleep 22.7 When enabled, the HLVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. TABLE 22-1: Effects of a Reset A device Reset forces all registers to their Reset state. This forces the HLVD module to be turned off. REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page HLVDCON VDIRMAG -- IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 50 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR2 OSCFIF CMIF(1) -- EEIF BCLIF HLVDIF TMR3IF ECCP1IF(1) 52 PIE2 OSCFIE CMIE(1) -- EEIE BCLIE HLVDIE TMR3IE ECCP1IE(1) 52 OSCFIP CMIP(1) -- EEIP BCLIP HLVDIP TMR3IP ECCP1IP(1) 51 IPR2 Legend: -- = unimplemented, read as `0'. Shaded cells are unused by the HLVD module. Note 1: These bits are available in PIC18F4682/4685 devices and reserved in PIC18F2682/2685 devices. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 271 PIC18F2682/2685/4682/4685 NOTES: DS39761B-page 272 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 23.0 ECANTM TECHNOLOGY 23.1 PIC18F2682/2685/4682/4685 devices contain an Enhanced Controller Area Network (ECAN) module. The ECAN module is fully backward compatible with the CAN module available in PIC18CXX8 and PIC18FXX8 devices. The Controller Area Network (CAN) module is a serial interface which is useful for communicating with other peripherals or microcontroller devices. This interface, or protocol, was designed to allow communications within noisy environments. The ECAN module is a communication controller, implementing the CAN 2.0A or B protocol as defined in the BOSCH specification. The module will support CAN 1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B Active versions of the protocol. The module implementation is a full CAN system; however, the CAN specification is not covered within this data sheet. Refer to the BOSCH CAN specification for further details. The module features are as follows: * Implementation of the CAN protocol CAN 1.2, CAN 2.0A and CAN 2.0B * DeviceNetTM data bytes filter support * Standard and extended data frames * 0-8 bytes data length * Programmable bit rate up to 1 Mbit/sec * Fully backward compatible with PIC18XXX8 CAN module * Three modes of operation: - Mode 0 - Legacy mode - Mode 1 - Enhanced Legacy mode with DeviceNet support - Mode 2 - FIFO mode with DeviceNet support * Support for remote frames with automated handling * Double-buffered receiver with two prioritized received message storage buffers * Six buffers programmable as RX and TX message buffers * 16 full (standard/extended identifier) acceptance filters that can be linked to one of four masks * Two full acceptance filter masks that can be assigned to any filter * One full acceptance filter that can be used as either an acceptance filter or acceptance filter mask * Three dedicated transmit buffers with application specified prioritization and abort capability * Programmable wake-up functionality with integrated low-pass filter * Programmable Loopback mode supports self-test operation * Signaling via interrupt capabilities for all CAN receiver and transmitter error states * Programmable clock source * Programmable link to timer module for time-stamping and network synchronization * Low-power Sleep mode (c) 2007 Microchip Technology Inc. Module Overview The CAN bus module consists of a protocol engine and message buffering and control. The CAN protocol engine automatically handles all functions for receiving and transmitting messages on the CAN bus. Messages are transmitted by first loading the appropriate data registers. Status and errors can be checked by reading the appropriate registers. Any message detected on the CAN bus is checked for errors and then matched against filters to see if it should be received and stored in one of the two receive registers. The CAN module supports the following frame types: * * * * * * Standard Data Frame Extended Data Frame Remote Frame Error Frame Overload Frame Reception Interframe Space Generation/Detection The CAN module uses the RB2/CANTX and RB3/ CANRX pins to interface with the CAN bus. In normal mode, the CAN module automatically overrides TRISB<2>. The user must ensure that TRISB<3> is set. 23.1.1 MODULE FUNCTIONALITY The CAN bus module consists of a protocol engine, message buffering and control (see Figure 23-1). The protocol engine can best be understood by defining the types of data frames to be transmitted and received by the module. The following sequence illustrates the necessary initialization steps before the ECAN module can be used to transmit or receive a message. Steps can be added or removed depending on the requirements of the application. 1. 2. 3. 4. 5. Preliminary Ensure that the ECAN module is in Configuration mode. Select ECAN operational mode. Set up the baud rate registers. Set up the filter and mask registers. Set the ECAN module to normal mode or any other mode required by the application logic. DS39761B-page 273 PIC18F2682/2685/4682/4685 BUFFERS 16 - 4 to 1 MUXs MESSAGE MSGREQ ABTF MLOA TXERR MTXBUFF MSGREQ ABTF MLOA TXERR MTXBUFF Acceptance Filters (RXF0-RXF05) MODE 0 TXB2 MESSAGE TXB1 MESSAGE MSGREQ ABTF MLOA TXERR MTXBUFF TXB0 A c c e p t Acceptance Filters (RXF06-RXF15) MODE 1, 2 MODE 0 2 RX Buffers Message Queue Control Transmit Byte Sequencer VCC Acceptance Mask RXM0 CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM Acceptance Mask RXM1 FIGURE 23-1: RXF15 Identifier Data Field M A B Rcv Byte MODE 1, 2 6 TX/RX Buffers Transmit Option MESSAGE BUFFERS PROTOCOL ENGINE Receive Error Counter Transmit<7:0> Transmit Error Counter Receive<8:0> REC TEC Err-Pas Bus-Off Shift<14:0> {Transmit<5:0>, Receive<8:0>} Comparator Protocol Finite State Machine CRC<14:0> Transmit Logic Bit Timing Logic Clock Generator TX RX Configuration Registers DS39761B-page 274 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 23.2 Note: 23.2.1 CAN Module Registers Not all CAN registers are available in the Access Bank. There are many control and data registers associated with the CAN module. For convenience, their descriptions have been grouped into the following sections: * * * * * * * CAN CONTROL AND STATUS REGISTERS The registers described in this section control the overall operation of the CAN module and show its operational status. Control and Status Registers Dedicated Transmit Buffer Registers Dedicated Receive Buffer Registers Programmable TX/RX and Auto RTR Buffers Baud Rate Control Registers I/O Control Register Interrupt Status and Control Registers Detailed descriptions of each register and their usage are described in the following sections. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 275 PIC18F2682/2685/4682/4685 REGISTER 23-1: Mode 0 Mode 1 Mode 2 CANCON: CAN CONTROL REGISTER R/W-1 R/W-0 R/W-0 R/S-0 R/W-0 R/W-0 R/W-0 U-0 REQOP2 REQOP1 REQOP0 ABAT WIN2 WIN1 WIN0 -- R/W-1 R/W-0 R/W-0 R/S-0 U0 U-0 U-0 U-0 REQOP2 REQOP1 REQOP0 ABAT -- -- -- -- R/W-1 R/W-0 R/W-0 R/S-0 R-0 R-0 R-0 R-0 REQOP2 REQOP1 REQOP0 ABAT FP3 FP2 FP1 FP0 bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-5 REQOP2:REQOP0: Request CAN Operation Mode bits 1xx = Request Configuration mode 011 = Request Listen Only mode 010 = Request Loopback mode 001 = Request Disable mode 000 = Request Normal mode bit 4 ABAT: Abort All Pending Transmissions bit 1 = Abort all pending transmissions (in all transmit buffers) 0 = Transmissions proceeding as normal bit 3-1 Mode 0: WIN2:WIN0: Window Address bits These bits select which of the CAN buffers to switch into the access bank area. This allows access to the buffer registers from any data memory bank. After a frame has caused an interrupt, the ICODE3:ICODE0 bits can be copied to the WIN3:WIN0 bits to select the correct buffer. See Example 23-2 for a code example. 111 = Receive Buffer 0 110 = Receive Buffer 0 101 = Receive Buffer 1 100 = Transmit Buffer 0 011 = Transmit Buffer 1 010 = Transmit Buffer 2 001 = Receive Buffer 0 000 = Receive Buffer 0 bit 0 Unimplemented: Read as `0' bit 4-0 Mode 1: Unimplemented: Read as `0' Mode 2: FP3:FP0: FIFO Read Pointer bits These bits point to the message buffer to be read. 0111:0000 = Message buffer to be read 1111:1000 = Reserved DS39761B-page 276 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 23-2: Mode 0 Mode 1,2 CANSTAT: CAN STATUS REGISTER R-1 R-0 R-0 (1) (1) OPMODE2 OPMODE1 OPMODE0(1) R-0 -- R-0 ICODE3 R-1 R-0 R-0 R-0 R-0 OPMODE2(1) OPMODE1(1) OPMODE0(1) EICODE4 EICODE3 bit 7 Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set R-0 ICODE2 R-0 ICODE1 R-0 EICODE2 R-0 EICODE1 U-0 -- R-0 EICODE0 bit 0 U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown OPMODE2:OPMODE0: Operation Mode Status bits(1) 111 = Reserved 110 = Reserved 101 = Reserved 100 = Configuration mode 011 = Listen Only mode 010 = Loopback mode 001 = Disable/Sleep mode 000 = Normal mode Mode 0: Unimplemented: Read as `0' ICODE3:ICODE1: Interrupt Code bits When an interrupt occurs, a prioritized coded interrupt value will be present in these bits. This code indicates the source of the interrupt. By copying ICODE3:ICODE1 to WIN2:WIN0 (Mode 0) or EICODE4:EICODE0 to EWIN4:EWIN0 (Mode 1 and 2), it is possible to select the correct buffer to map into the Access Bank area. See Example 23-2 for a code example. To simplify the description, the following table lists all five bits. bit 7-5 bit 4 bit 3-1 No interrupt Error interrupt TXB2 interrupt TXB1 interrupt TXB0 interrupt RXB1 interrupt RXB0 interrupt Wake-up interrupt RXB0 interrupt RXB1 interrupt RX/TX B0 interrupt RX/TX B1 interrupt RX/TX B2 interrupt RX/TX B3 interrupt RX/TX B4 interrupt RX/TX B5 interrupt bit 0 bit 4-0 Mode 0 00000 00010 00100 00110 01000 01010 01100 00010 --------------------------------- Mode 1 00000 00010 00100 00110 01000 10001 10000 01110 10000 10001 10010 10011 10100 10101 10110 10111 Mode 2 00000 00010 00100 00110 01000 ----10000 01110 10000 10000 10010 10011(2) 10100(2) 10101(2) 10110(2) 10111(2) Unimplemented: Read as `0' Mode 1, 2: EICODE4:EICODE0: Interrupt Code bits See ICODE3:ICODE1 above. Note 1: 2: To achieve maximum power saving and/or able to wake-up on CAN bus activity, switch CAN module in Disable mode before putting device to Sleep. If buffer is configured as receiver, EICODE bits will contain `10000' upon interrupt. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 277 PIC18F2682/2685/4682/4685 EXAMPLE 23-1: CHANGING TO CONFIGURATION MODE ; Request Configuration mode. MOVLW B'10000000' ; Set to Configuration Mode. MOVWF CANCON ; A request to switch to Configuration mode may not be immediately honored. ; Module will wait for CAN bus to be idle before switching to Configuration Mode. ; Request for other modes such as Loopback, Disable etc. may be honored immediately. ; It is always good practice to wait and verify before continuing. ConfigWait: MOVF CANSTAT, W ; Read current mode state. ANDLW B'10000000' ; Interested in OPMODE bits only. TSTFSZ WREG ; Is it Configuration mode yet? BRA ConfigWait ; No. Continue to wait... ; Module is in Configuration mode now. ; Modify configuration registers as required. ; Switch back to Normal mode to be able to communicate. EXAMPLE 23-2: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS TX/RX BUFFERS ; Save application required context. ; Poll interrupt flags and determine source of interrupt ; This was found to be CAN interrupt ; TempCANCON and TempCANSTAT are variables defined in Access Bank low MOVFF CANCON, TempCANCON ; Save CANCON.WIN bits ; This is required to prevent CANCON ; from corrupting CAN buffer access ; in-progress while this interrupt ; occurred MOVFF CANSTAT, TempCANSTAT ; Save CANSTAT register ; This is required to make sure that ; we use same CANSTAT value rather ; than one changed by another CAN ; interrupt. MOVF TempCANSTAT, W ; Retrieve ICODE bits ANDLW B'00001110' ADDWF PCL, F ; Perform computed GOTO ; to corresponding interrupt cause BRA NoInterrupt ; 000 = No interrupt BRA ErrorInterrupt ; 001 = Error interrupt BRA TXB2Interrupt ; 010 = TXB2 interrupt BRA TXB1Interrupt ; 011 = TXB1 interrupt BRA TXB0Interrupt ; 100 = TXB0 interrupt BRA RXB1Interrupt ; 101 = RXB1 interrupt BRA RXB0Interrupt ; 110 = RXB0 interrupt ; 111 = Wake-up on interrupt WakeupInterrupt BCF PIR3, WAKIF ; Clear the interrupt flag ; ; User code to handle wake-up procedure ; ; ; Continue checking for other interrupt source or return from here ... NoInterrupt ... ; PC should never vector here. User may ; place a trap such as infinite loop or pin/port ; indication to catch this error. DS39761B-page 278 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 EXAMPLE 23-2: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS TX/RX BUFFERS (CONTINUED) ErrorInterrupt BCF PIR3, ERRIF ; Clear the interrupt flag ... ; Handle error. RETFIE TXB2Interrupt BCF PIR3, TXB2IF ; Clear the interrupt flag GOTO AccessBuffer TXB1Interrupt BCF PIR3, TXB1IF ; Clear the interrupt flag GOTO AccessBuffer TXB0Interrupt BCF PIR3, TXB0IF ; Clear the interrupt flag GOTO AccessBuffer RXB1Interrupt BCF PIR3, RXB1IF ; Clear the interrupt flag GOTO Accessbuffer RXB0Interrupt BCF PIR3, RXB0IF ; Clear the interrupt flag GOTO AccessBuffer AccessBuffer ; This is either TX or RX interrupt ; Copy CANSTAT.ICODE bits to CANCON.WIN bits MOVF TempCANCON, W ; Clear CANCON.WIN bits before copying ; new ones. ANDLW B'11110001' ; Use previously saved CANCON value to ; make sure same value. MOVWF TempCANCON ; Copy masked value back to TempCANCON MOVF TempCANSTAT, W ; Retrieve ICODE bits ANDLW B'00001110' ; Use previously saved CANSTAT value ; to make sure same value. IORWF TempCANCON ; Copy ICODE bits to WIN bits. MOVFF TempCANCON, CANCON ; Copy the result to actual CANCON ; Access current buffer... ; User code ; Restore CANCON.WIN bits MOVF CANCON, W ; Preserve current non WIN bits ANDLW B'11110001' IORWF TempCANCON ; Restore original WIN bits ; Do not need to restore CANSTAT - it is read-only register. ; Return from interrupt or check for another module interrupt source (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 279 PIC18F2682/2685/4682/4685 REGISTER 23-3: ECANCON: ENHANCED CAN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 MDSEL1(1) MDSEL0(1) FIFOWM(2) EWIN4 EWIN3 EWIN2 EWIN1 EWIN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-6 MDSEL1:MDSEL0: Mode Select bits(1) 00 = Legacy mode (Mode 0, default) 01 = Enhanced Legacy mode (Mode 1) 10 = Enhanced FIFO mode (Mode 2) 11 = Reserved bit 5 FIFOWM: FIFO High Water Mark bit(2) 1 = Will cause FIFO interrupt when one receive buffer remains(3) 0 = Will cause FIFO interrupt when four receive buffers remain bit 4-0 EWIN4:EWIN0: Enhanced Window Address bits These bits map the group of 16 banked CAN SFRs into access bank addresses 0F60-0F6Dh. Exact group of registers to map is determined by binary value of these bits. Mode 0: Unimplemented: Read as `0' Mode 1, 2: 00000 = Acceptance Filters 0, 1, 2 and BRGCON2, 3 00001 = Acceptance Filters 3, 4, 5 and BRGCON1, CIOCON 00010 = Acceptance Filter Masks, Error and Interrupt Control 00011 = Transmit Buffer 0 00100 = Transmit Buffer 1 00101 = Transmit Buffer 2 00110 = Acceptance Filters 6, 7, 8 00111 = Acceptance Filters 9, 10, 11 01000 = Acceptance Filters 12, 13, 14 01001 = Acceptance Filters 15 01010-01110 = Reserved 01111 = RXINT0, RXINT1 10000 = Receive Buffer 0 10001 = Receive Buffer 1 10010 = TX/RX Buffer 0 10011 = TX/RX Buffer 1 10100 = TX/RX Buffer 2 10101 = TX/RX Buffer 3 10110 = TX/RX Buffer 4 10111 = TX/RX Buffer 5 11000-11111 = Reserved Note 1: 2: 3: These bits can only be changed in Configuration mode. See Register 23-1 to change to Configuration mode. This bit is used in Mode 2 only. FIFO length of 4 or less will cause this bit to be set. DS39761B-page 280 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 23-4: Mode 0 Mode 1 Mode 2 COMSTAT: COMMUNICATION STATUS REGISTER R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0 RXB0OVFL RXB1OVFL TXBO TXBP RXBP TXWARN RXWARN EWARN R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0 -- RXBnOVFL TXB0 TXBP RXBP TXWARN RXWARN EWARN R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0 TXBO TXBP RXBP TXWARN RXWARN EWARN FIFOEMPTY RXBnOVFL bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 Mode 0: RXB0OVFL: Receive Buffer 0 Overflow bit 1 = Receive Buffer 0 overflowed 0 = Receive Buffer 0 has not overflowed Mode 1: Unimplemented: Read as `0' Mode 2: FIFOEMPTY: FIFO Not Empty bit 1 = Receive FIFO is not empty 0 = Receive FIFO is empty bit 6 Mode 0: RXB1OVFL: Receive Buffer 1 Overflow bit 1 = Receive Buffer 1 overflowed 0 = Receive Buffer 1 has not overflowed Mode 1, 2: RXBnOVFL: Receive Buffer n Overflow bit 1 = Receive Buffer n has overflowed 0 = Receive Buffer n has not overflowed bit 5 TXBO: Transmitter Bus-Off bit 1 = Transmit error counter > 255 0 = Transmit error counter 255 bit 4 TXBP: Transmitter Bus Passive bit 1 = Transmit error counter > 127 0 = Transmit error counter 127 bit 3 RXBP: Receiver Bus Passive bit 1 = Receive error counter > 127 0 = Receive error counter 127 bit 2 TXWARN: Transmitter Warning bit 1 = Transmit error counter > 95 0 = Transmit error counter 95 bit 1 RXWARN: Receiver Warning bit 1 = 127 Receive error counter > 95 0 = Receive error counter 95 bit 0 EWARN: Error Warning bit This bit is a flag of the RXWARN and TXWARN bits. 1 = The RXWARN or the TXWARN bits are set 0 = Neither the RXWARN or the TXWARN bits are set (c) 2007 Microchip Technology Inc. Preliminary x = Bit is unknown DS39761B-page 281 PIC18F2682/2685/4682/4685 23.2.2 DEDICATED CAN TRANSMIT BUFFER REGISTERS This section describes the dedicated CAN Transmit Buffer registers and their associated control registers. REGISTER 23-5: Mode 0 Mode 1,2 R/C-0 TXBIF R-0 TXABT(1) R-0 TXLARB(1) R-0 R/W-0 TXERR(1) TXREQ(2) U-0 -- R/W-0 TXPRI1(3) R/W-0 TXPRI0(3) R/C-0 TXBIF bit 7 R-0 TXABT(1) R-0 TXLARB(1) R-0 R/W-0 TXERR(1) TXREQ(2) U-0 -- R/W-0 TXPRI1(3) R/W-0 TXPRI0(3) bit 0 Legend: R = Readable bit -n = Value at POR bit 7 TXBnCON: TRANSMIT BUFFER n CONTROL REGISTERS [0 n 2] C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TXBIF: Transmit Buffer Interrupt Flag bit 1 = Transmit buffer has completed transmission of message and may be reloaded 0 = Transmit buffer has not completed transmission of a message TXABT: Transmission Aborted Status bit(1) 1 = Message was aborted 0 = Message was not aborted TXLARB: Transmission Lost Arbitration Status bit(1) 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent TXERR: Transmission Error Detected Status bit(1) 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent TXREQ: Transmit Request Status bit(2) 1 = Requests sending a message. Clears the TXABT, TXLARB and TXERR bits. 0 = Automatically cleared when the message is successfully sent Unimplemented: Read as `0' TXPRI1:TXPRI0: Transmit Priority bits(3) 11 = Priority Level 3 (highest priority) 10 = Priority Level 2 01 = Priority Level 1 00 = Priority Level 0 (lowest priority) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1-0 Note 1: 2: 3: This bit is automatically cleared when TXREQ is set. While TXREQ is set, Transmit Buffer registers remain read-only. Clearing this bit in software while the bit is set will request a message abort. These bits define the order in which transmit buffers will be transferred. They do not alter the CAN message identifier. DS39761B-page 282 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 23-6: TXBnSIDH: TRANSMIT BUFFER n STANDARD IDENTIFIER REGISTERS, HIGH BYTE [0 n 2] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown SID10:SID3: Standard Identifier bits (if EXIDE (TXBnSIDL<3>) = 0) Extended Identifier bits EID28:EID21 (if EXIDE = 1). REGISTER 23-7: TXBnSIDL: TRANSMIT BUFFER n STANDARD IDENTIFIER REGISTERS, LOW BYTE [0 n 2] R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 -- EXIDE -- EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-5 SID2:SID0: Standard Identifier bits (if EXIDE (TXBnSIDL<3>) = 0) Extended Identifier bits EID20:EID18 (if EXIDE = 1). bit 4 Unimplemented: Read as `0' bit 3 EXIDE: Extended Identifier Enable bit 1 = Message will transmit extended ID, SID10:SID0 become EID28:EID18 0 = Message will transmit standard ID, EID17:EID0 are ignored bit 2 Unimplemented: Read as `0' bit 1-0 EID17:EID16: Extended Identifier bits REGISTER 23-8: TXBnEIDH: TRANSMIT BUFFER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE [0 n 2] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown EID15:EID8: Extended Identifier bits (not used when transmitting standard identifier message) (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 283 PIC18F2682/2685/4682/4685 REGISTER 23-9: TXBnEIDL: TRANSMIT BUFFER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE [0 n 2] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown EID7:EID0: Extended Identifier bits (not used when transmitting standard identifier message) REGISTER 23-10: TXBnDm: TRANSMIT BUFFER n DATA FIELD BYTE m REGISTERS [0 n 2, 0 m 7] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x TXBnDm7 TXBnDm6 TXBnDm5 TXBnDm4 TXBnDm3 TXBnDm2 TXBnDm1 TXBnDm0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown TXBnDm7:TXBnDm0: Transmit Buffer n Data Field Byte m bits (where 0 n < 3 and 0 m < 8) Each transmit buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers: TXB0D0 to TXB0D7. DS39761B-page 284 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 23-11: TXBnDLC: TRANSMIT BUFFER n DATA LENGTH CODE REGISTERS [0 n 2] U-0 R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x -- TXRTR -- -- DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6 TXRTR: Transmit Remote Frame Transmission Request bit 1 = Transmitted message will have TXRTR bit set 0 = Transmitted message will have TXRTR bit cleared bit 5-4 Unimplemented: Read as `0' bit 3-0 DLC3:DLC0: Data Length Code bits 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Data length = 8 bytes 0111 = Data length = 7 bytes 0110 = Data length = 6 bytes 0101 = Data length = 5 bytes 0100 = Data length = 4 bytes 0011 = Data length = 3 bytes 0010 = Data length = 2 bytes 0001 = Data length = 1 bytes 0000 = Data length = 0 bytes x = Bit is unknown REGISTER 23-12: TXERRCNT: TRANSMIT ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown TEC7:TEC0: Transmit Error Counter bits This register contains a value which is derived from the rate at which errors occur. When the error count overflows, the bus-off state occurs. When the bus has 128 occurrences of 11 consecutive recessive bits, the counter value is cleared. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 285 PIC18F2682/2685/4682/4685 EXAMPLE 23-3: TRANSMITTING A CAN MESSAGE USING BANKED METHOD ; Need to transmit Standard Identifier message 123h using TXB0 buffer. ; To successfully transmit, CAN module must be either in Normal or Loopback mode. ; TXB0 buffer is not in access bank. And since we want banked method, we need to make sure ; that correct bank is selected. BANKSEL TXB0CON ; One BANKSEL in beginning will make sure that we are ; in correct bank for rest of the buffer access. ; Now load transmit data into TXB0 buffer. MOVLW MY_DATA_BYTE1 ; Load first data byte into buffer MOVWF TXB0D0 ; Compiler will automatically set "BANKED" bit ; Load rest of data bytes - up to 8 bytes into TXB0 buffer. ... ; Load message identifier MOVLW 60H ; Load SID2:SID0, EXIDE = 0 MOVWF TXB0SIDL MOVLW 24H ; Load SID10:SID3 MOVWF TXB0SIDH ; No need to load TXB0EIDL:TXB0EIDH, as we are transmitting Standard Identifier Message only. ; Now that all data bytes are loaded, mark it for transmission. MOVLW B'00001000' ; Normal priority; Request transmission MOVWF TXB0CON ; If required, wait for message to get transmitted BTFSC TXB0CON, TXREQ ; Is it transmitted? BRA $-2 ; No. Continue to wait... ; Message is transmitted. DS39761B-page 286 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 EXAMPLE 23-4: TRANSMITTING A CAN MESSAGE USING WIN BITS ; Need to transmit Standard Identifier message 123h using TXB0 buffer. ; To successfully transmit, CAN module must be either in Normal or Loopback mode. ; TXB0 buffer is not in access bank. Use WIN bits to map it to RXB0 area. MOVF CANCON, W ; WIN bits are in lower 4 bits only. Read CANCON ; register to preserve all other bits. If operation ; mode is already known, there is no need to preserve ; other bits. ANDLW B'11110000' ; Clear WIN bits. IORLW B'00001000' ; Select Transmit Buffer 0 MOVWF CANCON ; Apply the changes. ; Now TXB0 is mapped in place of RXB0. All future access to RXB0 registers will actually ; yield TXB0 register values. ; Load transmit data into TXB0 buffer. MOVLW MY_DATA_BYTE1 ; Load first data byte into buffer MOVWF RXB0D0 ; Access TXB0D0 via RXB0D0 address. ; Load rest of the data bytes - up to 8 bytes into "TXB0" buffer using RXB0 registers. ... ; Load message identifier MOVLW 60H ; Load SID2:SID0, EXIDE = 0 MOVWF RXB0SIDL MOVLW 24H ; Load SID10:SID3 MOVWF RXB0SIDH ; No need to load RXB0EIDL:RXB0EIDH, as we are transmitting Standard Identifier Message only. ; Now that all data bytes are loaded, mark it for transmission. MOVLW B'00001000' ; Normal priority; Request transmission MOVWF RXB0CON ; If required, wait for message to get transmitted BTFSC RXB0CON, TXREQ ; Is it transmitted? BRA $-2 ; No. Continue to wait... ; Message is transmitted. ; If required, reset the WIN bits to default state. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 287 PIC18F2682/2685/4682/4685 23.2.3 DEDICATED CAN RECEIVE BUFFER REGISTERS This section shows the dedicated CAN Receive Buffer registers with their associated control registers. REGISTER 23-13: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER Mode 0 Mode 1,2 R/C-0 RXFUL(1) R/W-0 RXM1 R/W-0 RXM0 U-0 -- R/C-0 RXFUL(1) bit 7 R/W-0 RXM1 R-0 RTRRO R-0 FILHIT4 Legend: R = Readable bit -n = Value at POR C = Clearable bit W = Writable bit `1' = Bit is set R-0 R/W-0 RXRTRRO RXB0DBEN R-0 FILHIT3 R-0 FILHIT2 R-0 JTOFF(2) R-0 FILHIT0 R-0 FILHIT1 R-0 FILHIT0 bit 0 U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RXFUL: Receive Full Status bit(1) 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message Mode 0: RXM1: Receive Buffer Mode bit 1 (combines with RXM0 to form RXM<1:0> bits, see bit 5) 11 = Receive all messages (including those with errors); filter criteria is ignored 10 = Receive only valid messages with extended identifier; EXIDEN in RXFnSIDL must be `1' 01 = Receive only valid messages with standard identifier; EXIDEN in RXFnSIDL must be `0' 00 = Receive all valid messages as per EXIDEN bit in RXFnSIDL register Mode 1, 2: RXM1: Receive Buffer Mode bit 1 1 = Receive all messages (including those with errors); acceptance filters are ignored 0 = Receive all valid messages as per acceptance filters Mode 0: RXM0: Receive Buffer Mode bit 0 (combines with RXM1 to form RXM<1:0> bits, see bit 6) Mode 1, 2: RTRRO: Remote Transmission Request bit for Received Message (read-only) 1 = A remote transmission request is received 0 = A remote transmission request is not received Mode 0: Unimplemented: Read as `0' Mode 1, 2: FILHIT4: Filter Hit bit 4 This bit combines with other bits to form filter acceptance bits <4:0>. Mode 0: RXRTRRO: Remote Transmission Request bit for Received Message (read-only) 1 = A remote transmission request is received 0 = A remote transmission request is not received Mode 1, 2: FILHIT3: Filter Hit bit 3 This bit combines with other bits to form filter acceptance bits <4:0>. bit 7 bit 6 bit 5 bit 4 bit 3 Note 1: 2: This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer is read. As long as RXFUL is set, no new message will be loaded and buffer will be considered full. After clearing the RXFUL flag, the PIR3 bit, RXB0IF, can be cleared. If RXB0IF is cleared, but RXFUL is not cleared, then RXB0IF is set again. This bit allows same filter jump table for both RXB0CON and RXB1CON. DS39761B-page 288 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 23-13: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER (CONTINUED) bit 2 Mode 0: RXB0DBEN: Receive Buffer 0 Double-Buffer Enable bit 1 = Receive Buffer 0 overflow will write to Receive Buffer 1 0 = No Receive Buffer 0 overflow to Receive Buffer 1 Mode 1, 2: FILHIT2: Filter Hit bit 2 This bit combines with other bits to form filter acceptance bits <4:0>. Mode 0: JTOFF: Jump Table Offset bit (read-only copy of RXB0DBEN)(2) 1 = Allows jump table offset between 6 and 7 0 = Allows jump table offset between 1 and 0 Mode 1, 2: FILHIT1: Filter Hit bit 1 This bit combines with other bits to form filter acceptance bits <4:0>. Mode 0: FILHIT0: Filter Hit bit 0 This bit indicates which acceptance filter enabled the message reception into Receive Buffer 0. 1 = Acceptance Filter 1 (RXF1) 0 = Acceptance Filter 0 (RXF0) Mode 1, 2: FILHIT0: Filter Hit bit 0 This bit, in combination with FILHIT<4:1>, indicates which acceptance filter enabled the message reception into this receive buffer. 01111 = Acceptance Filter 15 (RXF15) 01110 = Acceptance Filter 14 (RXF14) ... 00000 = Acceptance Filter 0 (RXF0) bit 1 bit 0 Note 1: 2: This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer is read. As long as RXFUL is set, no new message will be loaded and buffer will be considered full. After clearing the RXFUL flag, the PIR3 bit, RXB0IF, can be cleared. If RXB0IF is cleared, but RXFUL is not cleared, then RXB0IF is set again. This bit allows same filter jump table for both RXB0CON and RXB1CON. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 289 PIC18F2682/2685/4682/4685 REGISTER 23-14: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER Mode 0 Mode 1,2 R/C-0 RXFUL(1) R/W-0 RXM1 R/W-0 RXM0 U-0 -- R-0 RXRTRRO R/W-0 FILHIT2 R-0 FILHIT1 R-0 FILHIT0 R/C-0 RXFUL(1) bit 7 R/W-0 RXM1 R-0 RTRRO R-0 FILHIT4 R-0 FILHIT3 R-0 FILHIT2 R-0 FILHIT1 R-0 FILHIT0 bit 0 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 bit 5 bit 4 bit 3 Note 1: C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RXFUL: Receive Full Status bit(1) 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message Mode 0: RXM1: Receive Buffer Mode bit 1 (combines with RXM0 to form RXM<1:0> bits, see bit 5) 11 = Receive all messages (including those with errors); filter criteria is ignored 10 = Receive only valid messages with extended identifier; EXIDEN in RXFnSIDL must be `1' 01 = Receive only valid messages with standard identifier, EXIDEN in RXFnSIDL must be `0' 00 = Receive all valid messages as per EXIDEN bit in RXFnSIDL register Mode 1, 2: RXM1: Receive Buffer Mode bit 1 = Receive all messages (including those with errors); acceptance filters are ignored 0 = Receive all valid messages as per acceptance filters Mode 0: RXM0: Receive Buffer Mode bit 0 (combines with RXM1 to form RXM<1:0> bits, see bit 6) Mode 1, 2: RTRRO: Remote Transmission Request bit for Received Message (read-only) 1 = A remote transmission request is received 0 = A remote transmission request is not received Mode 0: Unimplemented: Read as `0' Mode 1, 2: FILHIT4: Filter Hit bit 4 This bit combines with other bits to form filter acceptance bits <4:0>. Mode 0: RXRTRRO: Remote Transmission Request bit for Received Message (read-only) 1 = A remote transmission request is received 0 = A remote transmission request is not received Mode 1, 2: FILHIT3: Filter Hit bit 3 This bit combines with other bits to form filter acceptance bits <4:0>. This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer is read. As long as RXFUL is set, no new message will be loaded and buffer will be considered full. DS39761B-page 290 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 23-14: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER (CONTINUED) bit 2-0 Note 1: Mode 0: FILHIT2:FILHIT0: Filter Hit bits These bits indicate which acceptance filter enabled the last message reception into Receive Buffer 1. 111 = Reserved 110 = Reserved 101 = Acceptance Filter 5 (RXF5) 100 = Acceptance Filter 4 (RXF4) 011 = Acceptance Filter 3 (RXF3) 010 = Acceptance Filter 2 (RXF2) 001 = Acceptance Filter 1 (RXF1), only possible when RXB0DBEN bit is set 000 = Acceptance Filter 0 (RXF0), only possible when RXB0DBEN bit is set Mode 1, 2: FILHIT2:FILHIT0 Filter Hit bits <2:0> These bits, in combination with FILHIT<4:3>, indicate which acceptance filter enabled the message reception into this receive buffer. 01111 = Acceptance Filter 15 (RXF15) 01110 = Acceptance Filter 14 (RXF14) ... 00000 = Acceptance Filter 0 (RXF0) This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer is read. As long as RXFUL is set, no new message will be loaded and buffer will be considered full. REGISTER 23-15: RXBnSIDH: RECEIVE BUFFER n STANDARD IDENTIFIER REGISTERS, HIGH BYTE [0 n 1] R-x R-x R-x R-x R-x R-x R-x R-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown SID10:SID3: Standard Identifier bits (if EXID (RXBnSIDL<3>) = 0) Extended Identifier bits EID28:EID21 (if EXID = 1). (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 291 PIC18F2682/2685/4682/4685 REGISTER 23-16: RXBnSIDL: RECEIVE BUFFER n STANDARD IDENTIFIER REGISTERS, LOW BYTE [0 n 1] R-x R-x R-x R-x R-x U-0 R-x R-x SID2 SID1 SID0 SRR EXID -- EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-5 SID2:SID0: Standard Identifier bits (if EXID = 0) Extended Identifier bits EID20:EID18 (if EXID = 1). bit 4 SRR: Substitute Remote Request bit This bit is always `0' when EXID = 1 or equal to the value of RXRTRRO (RBXnCON<3>) when EXID = 0. bit 3 EXID: Extended Identifier bit 1 = Received message is an extended data frame, SID10:SID0 are EID28:EID18 0 = Received message is a standard data frame bit 2 Unimplemented: Read as `0' bit 1-0 EID17:EID16: Extended Identifier bits REGISTER 23-17: RXBnEIDH: RECEIVE BUFFER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE [0 n 1] R-x R-x R-x R-x R-x R-x R-x R-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown EID15:EID8: Extended Identifier bits REGISTER 23-18: RXBnEIDL: RECEIVE BUFFER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE [0 n 1] R-x R-x R-x R-x R-x R-x R-x R-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown EID7:EID0: Extended Identifier bits DS39761B-page 292 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 23-19: RXBnDLC: RECEIVE BUFFER n DATA LENGTH CODE REGISTERS [0 n 1] U-0 R-x R-x R-x R-x R-x R-x R-x -- RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6 RXRTR: Receiver Remote Transmission Request bit 1 = Remote transfer request 0 = No remote transfer request bit 5 RB1: Reserved bit 1 Reserved by CAN Spec and read as `0'. bit 4 RB0: Reserved bit 0 Reserved by CAN Spec and read as `0'. bit 3-0 DLC3:DLC0: Data Length Code bits 1111 = Invalid 1110 = Invalid 1101 = Invalid 1100 = Invalid 1011 = Invalid 1010 = Invalid 1001 = Invalid 1000 = Data length = 8 bytes 0111 = Data length = 7 bytes 0110 = Data length = 6 bytes 0101 = Data length = 5 bytes 0100 = Data length = 4 bytes 0011 = Data length = 3 bytes 0010 = Data length = 2 bytes 0001 = Data length = 1 bytes 0000 = Data length = 0 bytes x = Bit is unknown REGISTER 23-20: RXBnDm: RECEIVE BUFFER n DATA FIELD BYTE m REGISTERS [0 n 1, 0 m 7] R-x R-x R-x R-x R-x R-x R-x R-x RXBnDm7 RXBnDm6 RXBnDm5 RXBnDm4 RXBnDm3 RXBnDm2 RXBnDm1 RXBnDm0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown RXBnDm7:RXBnDm0: Receive Buffer n Data Field Byte m bits (where 0 n < 1 and 0 < m < 7) Each receive buffer has an array of registers. For example, Receive Buffer 0 has 8 registers: RXB0D0 to RXB0D7. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 293 PIC18F2682/2685/4682/4685 REGISTER 23-21: RXERRCNT: RECEIVE ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown REC7:REC0: Receive Error Counter bits This register contains the receive error value as defined by the CAN specifications. When RXERRCNT > 127, the module will go into an error-passive state. RXERRCNT does not have the ability to put the module in "bus-off" state. EXAMPLE 23-5: READING A CAN MESSAGE ; Need to read a pending message from RXB0 buffer. ; To receive any message, filter, mask and RXM1:RXM0 bits in RXB0CON registers must be ; programmed correctly. ; ; Make sure that there is a message pending in RXB0. BTFSS RXB0CON, RXFUL ; Does RXB0 contain a message? BRA NoMessage ; No. Handle this situation... ; We have verified that a message is pending in RXB0 buffer. ; If this buffer can receive both Standard or Extended Identifier messages, ; identify type of message received. BTFSS RXB0SIDL, EXID ; Is this Extended Identifier? BRA StandardMessage ; No. This is Standard Identifier message. ; Yes. This is Extended Identifier message. ; Read all 29-bits of Extended Identifier message. ... ; Now read all data bytes MOVFF RXB0DO, MY_DATA_BYTE1 ... ; Once entire message is read, mark the RXB0 that it is read and no longer FULL. BCF RXB0CON, RXFUL ; This will allow CAN Module to load new messages ; into this buffer. ... DS39761B-page 294 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 23.2.3.1 Programmable TX/RX and Auto-RTR Buffers The ECAN module contains 6 message buffers that can be programmed as transmit or receive buffers. Any of these buffers can also be programmed to automatically handle RTR messages. Note: These registers are not used in Mode 0. REGISTER 23-22: BnCON: TX/RX BUFFER n CONTROL REGISTERS IN RECEIVE MODE [0 n 5, TXnEN (BSEL0<n>) = 0](1) R/W-0 RXFUL (2) R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 RXFUL: Receive Full Status bit(2) 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message bit 6 RXM1: Receive Buffer Mode bit 1 = Receive all messages including partial and invalid (acceptance filters are ignored) 0 = Receive all valid messages as per acceptance filters bit 5 RXRTRRO: Read-Only Remote Transmission Request for Received Message bit 1 = Received message is a remote transmission request 0 = Received message is not a remote transmission request bit 4-0 FILHIT4:FILHIT0: Filter Hit bits These bits indicate which acceptance filter enabled the last message reception into this buffer. 01111 = Acceptance Filter 15 (RXF15) 01110 = Acceptance Filter 14 (RXF14) ... 00001 = Acceptance Filter 1 (RXF1) 00000 = Acceptance Filter 0 (RXF0) Note 1: 2: These registers are available in Mode 1 and 2 only. This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer is read. As long as RXFUL is set, no new message will be loaded and the buffer will be considered full. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 295 PIC18F2682/2685/4682/4685 REGISTER 23-23: BnCON: TX/RX BUFFER n CONTROL REGISTERS IN TRANSMIT MODE [0 n 5, TXnEN (BSEL0<n>) = 1](1) R/W-0 TXBIF R-0 (3) TXABT R-0 (3) TXLARB R-0 (3) R/W-0 (3) TXERR (2,4) TXREQ R/W-0 RTREN R/W-0 TXPRI1 (5) R/W-0 TXPRI0(5) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 TXBIF: Transmit Buffer Interrupt Flag bit(3) 1 = A message is successfully transmitted 0 = No message was transmitted bit 6 TXABT: Transmission Aborted Status bit(3) 1 = Message was aborted 0 = Message was not aborted bit 5 TXLARB: Transmission Lost Arbitration Status bit(3) 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent bit 4 TXERR: Transmission Error Detected Status bit(3) 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent bit 3 TXREQ: Transmit Request Status bit(2,4) 1 = Requests sending a message; clears the TXABT, TXLARB and TXERR bits 0 = Automatically cleared when the message is successfully sent bit 2 RTREN: Automatic Remote Transmission Request Enable bit 1 = When a remote transmission request is received, TXREQ will be automatically set 0 = When a remote transmission request is received, TXREQ will be unaffected bit 1-0 TXPRI1:TXPRI0: Transmit Priority bits(5) 11 = Priority Level 3 (highest priority) 10 = Priority Level 2 01 = Priority Level 1 00 = Priority Level 0 (lowest priority) Note 1: 2: 3: 4: 5: These registers are available in Mode 1 and 2 only. Clearing this bit in software while the bit is set will request a message abort. This bit is automatically cleared when TXREQ is set. While TXREQ is set or transmission is in progress, transmit buffer registers remain read-only. These bits set the order in which the transmit buffer will be transferred. They do not alter the CAN message identifier. DS39761B-page 296 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 23-24: BnSIDH: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS, HIGH BYTE IN RECEIVE MODE [0 n 5, TXnEN (BSEL0<n>) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: x = Bit is unknown SID10:SID3: Standard Identifier bits (if EXIDE (BnSIDL<3>) = 0) Extended Identifier bits EID28:EID21 (if EXIDE = 1). These registers are available in Mode 1 and 2 only. REGISTER 23-25: BnSIDH: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS, HIGH BYTE IN TRANSMIT MODE [0 n 5, TXnEN (BSEL0<n>) = 1](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: x = Bit is unknown SID10:SID3: Standard Identifier bits (if EXIDE (BnSIDL<3>) = 0) Extended Identifier bits EID28:EID21 (if EXIDE = 1). These registers are available in Mode 1 and 2 only. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 297 PIC18F2682/2685/4682/4685 REGISTER 23-26: BnSIDL: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0 n 5, TXnEN (BSEL0<n>) = 0](1) R-x R-x R-x R-x R-x U-0 R-x R-x SID2 SID1 SID0 SRR EXID -- EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-5 SID2:SID0: Standard Identifier bits (if EXID = 0) Extended Identifier bits EID20:EID18 (if EXID = 1). bit 4 SRR: Substitute Remote Transmission Request bit (only when EXID = 1) 1 = Remote transmission request occurred 0 = No remote transmission request occurred bit 3 EXID: Extended Identifier Enable bit 1 = Received message is an extended identifier frame (SID10:SID0 are EID28:EID18) 0 = Received message is a standard identifier frame bit 2 Unimplemented: Read as `0' bit 1-0 EID17:EID16: Extended Identifier bits Note 1: These registers are available in Mode 1 and 2 only. REGISTER 23-27: BnSIDL: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0 n 5, TXnEN (BSEL0<n>) = 1](1) R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 -- EXIDE -- EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-5 SID2:SID0: Standard Identifier bits (if EXIDE = 0) Extended Identifier bits EID20:EID18 (if EXIDE = 1). bit 4 Unimplemented: Read as `0' bit 3 EXIDE: Extended Identifier Enable bit 1 = Received message is an extended identifier frame (SID10:SID0 are EID28:EID18) 0 = Received message is a standard identifier frame bit 2 Unimplemented: Read as `0' bit 1-0 EID17:EID16: Extended Identifier bits Note 1: These registers are available in Mode 1 and 2 only. DS39761B-page 298 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 23-28: BnEIDH: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE IN RECEIVE MODE [0 n 5, TXnEN (BSEL0<n>) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: x = Bit is unknown EID15:EID8: Extended Identifier bits These registers are available in Mode 1 and 2 only. REGISTER 23-29: BnEIDH: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE IN TRANSMIT MODE [0 n 5, TXnEN (BSEL0<n>) = 1](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: x = Bit is unknown EID15:EID8: Extended Identifier bits These registers are available in Mode 1 and 2 only. REGISTER 23-30: BnEIDL: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0 n 5, TXnEN (BSEL<n>) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: x = Bit is unknown EID7:EID0: Extended Identifier bits These registers are available in Mode 1 and 2 only. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 299 PIC18F2682/2685/4682/4685 REGISTER 23-31: BnEIDL: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0 n 5, TXnEN (BSEL<n>) = 1](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: x = Bit is unknown EID7:EID0: Extended Identifier bits These registers are available in Mode 1 and 2 only. REGISTER 23-32: BnDm: TX/RX BUFFER n DATA FIELD BYTE m REGISTERS IN RECEIVE MODE [0 n 5, 0 m 7, TXnEN (BSEL<n>) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x BnDm7 BnDm6 BnDm5 BnDm4 BnDm3 BnDm2 BnDm1 BnDm0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared BnDm7:BnDm0: Receive Buffer n Data Field Byte m bits (where 0 n < 3 and 0 < m < 8) Each receive buffer has an array of registers. For example, Receive Buffer 0 has 7 registers: B0D0 to B0D7. bit 7-0 Note 1: x = Bit is unknown These registers are available in Mode 1 and 2 only. REGISTER 23-33: BnDm: TX/RX BUFFER n DATA FIELD BYTE m REGISTERS IN TRANSMIT MODE [0 n 5, 0 m 7, TXnEN (BSEL<n>) = 1](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x BnDm7 BnDm6 BnDm5 BnDm4 BnDm3 BnDm2 BnDm1 BnDm0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: x = Bit is unknown BnDm7:BnDm0: Transmit Buffer n Data Field Byte m bits (where 0 n < 3 and 0 < m < 8) Each transmit buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers: TXB0D0 to TXB0D7. These registers are available in Mode 1 and 2 only. DS39761B-page 300 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 23-34: BnDLC: TX/RX BUFFER n DATA LENGTH CODE REGISTERS IN RECEIVE MODE [0 n 5, TXnEN (BSEL<n>) = 0](1) U-0 R-x R-x R-x R-x R-x R-x R-x -- RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6 RXRTR: Receiver Remote Transmission Request bit 1 = This is a remote transmission request 0 = This is not a remote transmission request bit 5 RB1: Reserved bit 1 Reserved by CAN Spec and read as `0'. bit 4 RB0: Reserved bit 0 Reserved by CAN Spec and read as `0'. bit 3-0 DLC3:DLC0: Data Length Code bits 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Data length = 8 bytes 0111 = Data length = 7 bytes 0110 = Data length = 6 bytes 0101 = Data length = 5 bytes 0100 = Data length = 4 bytes 0011 = Data length = 3 bytes 0010 = Data length = 2 bytes 0001 = Data length = 1 bytes 0000 = Data length = 0 bytes Note 1: x = Bit is unknown These registers are available in Mode 1 and 2 only. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 301 PIC18F2682/2685/4682/4685 REGISTER 23-35: BnDLC: TX/RX BUFFER n DATA LENGTH CODE REGISTERS IN TRANSMIT MODE [0 n 5, TXnEN (BSEL<n>) = 1](1) U-0 R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x -- TXRTR -- -- DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6 TXRTR: Transmitter Remote Transmission Request bit 1 = Transmitted message will have RTR bit set 0 = Transmitted message will have RTR bit cleared bit 5-4 Unimplemented: Read as `0' bit 3-0 DLC3:DLC0: Data Length Code bits 1111-1001 = Reserved 1000 = Data length = 8 bytes 0111 = Data length = 7 bytes 0110 = Data length = 6 bytes 0101 = Data length = 5 bytes 0100 = Data length = 4 bytes 0011 = Data length = 3 bytes 0010 = Data length = 2 bytes 0001 = Data length = 1 bytes 0000 = Data length = 0 bytes Note 1: x = Bit is unknown These registers are available in Mode 1 and 2 only. REGISTER 23-36: BSEL0: BUFFER SELECT REGISTER 0(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 B5TXEN B4TXEN B3TXEN B2TXEN B1TXEN B0TXEN -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-2 B5TXEN:B0TXEN: Buffer 5 to Buffer 0 Transmit Enable bit 1 = Buffer is configured in Transmit mode 0 = Buffer is configured in Receive mode bit 1-0 Unimplemented: Read as `0' Note 1: x = Bit is unknown These registers are available in Mode 1 and 2 only. DS39761B-page 302 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 23.2.3.2 Message Acceptance Filters and Masks This section describes the message acceptance filters and masks for the CAN receive buffers. REGISTER 23-37: RXFnSIDH: RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER REGISTERS, HIGH BYTE [0 n 15](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: x = Bit is unknown SID10:SID3: Standard Identifier Filter bits (if EXIDEN = 0) Extended Identifier Filter bits EID28:EID21 (if EXIDEN = 1). Registers RXF6SIDH:RXF15SIDH are available in Mode 1 and 2 only. REGISTER 23-38: RXFnSIDL: RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER REGISTERS, LOW BYTE [0 n 15](1) R/W-x R/W-x SID2 SID1 R/W-x SID0 U-0 R/W-x U-0 R/W-x R/W-x -- EXIDEN(2) -- EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-5 SID2:SID0: Standard Identifier Filter bits (if EXIDEN = 0) Extended Identifier Filter bits EID20:EID18 (if EXIDEN = 1). bit 4 Unimplemented: Read as `0' bit 3 EXIDEN: Extended Identifier Filter Enable bit(2) 1 = Filter will only accept extended ID messages 0 = Filter will only accept standard ID messages bit 2 Unimplemented: Read as `0' bit 1-0 Note 1: 2: x = Bit is unknown EID17:EID16: Extended Identifier Filter bits Registers RXF6SIDL:RXF15SIDL are available in Mode 1 and 2 only. In Mode 0, this bit must be set/cleared as required, irrespective of corresponding mask register value. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 303 PIC18F2682/2685/4682/4685 REGISTER 23-39: RXFnEIDH: RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE [0 n 15](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: x = Bit is unknown EID15:EID8: Extended Identifier Filter bits Registers RXF6EIDH:RXF15EIDH are available in Mode 1 and 2 only. REGISTER 23-40: RXFnEIDL: RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE [0 n 15](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: x = Bit is unknown EID7:EID0: Extended Identifier Filter bits Registers RXF6EIDL:RXF15EIDL are available in Mode 1 and 2 only. REGISTER 23-41: RXMnSIDH: RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK REGISTERS, HIGH BYTE [0 n 1] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown SID10:SID3: Standard Identifier Mask bits or Extended Identifier Mask bits EID28:EID21 DS39761B-page 304 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 23-42: RXMnSIDL: RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK REGISTERS, LOW BYTE [0 n 1] R/W-x R/W-x SID2 SID1 R/W-x SID0 U-0 R/W-0 (1) -- EXIDEN U-0 R/W-x R/W-x -- EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-5 SID2:SID0: Standard Identifier Mask bits or Extended Identifier Mask bits EID20:EID18 bit 4 Unimplemented: Read as `0' bit 3 Mode 0: Unimplemented: Read as `0' Mode 1, 2: EXIDEN: Extended Identifier Filter Enable Mask bit(1) 1 = Messages selected by the EXIDEN bit in RXFnSIDL will be accepted 0 = Both standard and extended identifier messages will be accepted bit 2 Unimplemented: Read as `0' bit 1-0 EID17:EID16: Extended Identifier Mask bits Note 1: This bit is available in Mode 1 and 2 only. REGISTER 23-43: RXMnEIDH: RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK REGISTERS, HIGH BYTE [0 n 1] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown EID15:EID8: Extended Identifier Mask bits REGISTER 23-44: RXMnEIDL: RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK REGISTERS, LOW BYTE [0 n 1] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown EID7:EID0: Extended Identifier Mask bits (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 305 PIC18F2682/2685/4682/4685 REGISTER 23-45: RXFCONn: RECEIVE FILTER CONTROL REGISTER n [0 n 1](1) RXFCON0 RXFCON1 R/W-0 RXF7EN R/W-0 RXF6EN R/W-1 RXF5EN R/W-1 RXF4EN R/W-1 RXF3EN R/W-1 RXF2EN R/W-1 RXF1EN R/W-1 RXF0EN R/W-0 RXF15EN bit 7 R/W-0 RXF14EN R/W-0 RXF13EN R/W-1 R/W-0 RXF12EN RXF11EN R/W-0 RXF10EN R/W-0 RXF9EN R/W-0 RXF8EN bit 0 Legend: R = Readable bit -n = Value at POR bit 7-0 Note 1: Note: C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RXFnEN: Receive Filter n Enable bits 0 = Filter is disabled 1 = Filter is enabled This register is available in Mode 1 and 2 only. Register 23-46 through Register 23-51 are writable in Configuration mode only. REGISTER 23-46: SDFLC: STANDARD DATA BYTES FILTER LENGTH COUNT REGISTER(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- FLC4 FLC3 FLC2 FLC1 FLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as `0' bit 4-0 FLC4:FLC0: Filter Length Count bits Mode 0: Not used; forced to `00000'. 00000-10010 = 0 18 bits are available for standard data byte filter. Actual number of bits used depends on DLC3:DLC0 bits (RXBnDLC<3:0> or BnDLC<3:0> if configured as RX buffer) of message being received. If DLC3:DLC0 = 0000 No bits will be compared with incoming data bits. If DLC3:DLC0 = 0001 Up to 8 data bits of RXFnEID<7:0>, as determined by FLC2:FLC0, will be compared with the corresponding number of data bits of the incoming message. If DLC3:DLC0 = 0010 Up to 16 data bits of RXFnEID<15:0>, as determined by FLC3:FLC0, will be compared with the corresponding number of data bits of the incoming message. If DLC3:DLC0 = 0011 Up to 18 data bits of RXFnEID<17:0>, as determined by FLC4:FLC0, will be compared with the corresponding number of data bits of the incoming message. Note 1: This register is available in Mode 1 and 2 only. DS39761B-page 306 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 23-47: RXFBCONn: RECEIVE FILTER BUFFER CONTROL REGISTER n(1) RXFBCON0 R/W-0 F1BP_3 R/W-0 F1BP_2 R/W-0 F1BP_1 R/W-0 F1BP_0 R/W-0 F0BP_3 R/W-0 F0BP_2 R/W-0 F0BP_1 R/W-0 F0BP_0 RXFBCON1 R/W-0 F3BP_3 R/W-0 F3BP_2 R/W-0 F3BP_1 R/W-1 F3BP_0 R/W-0 F2BP_3 R/W-0 F2BP_2 R/W-0 F2BP_1 R/W-1 F2BP_0 RXFBCON2 R/W-0 F5BP_3 R/W-0 F5BP_2 R/W-0 F5BP_1 R/W-1 F5BP_0 R/W-0 F4BP_3 R/W-0 F4BP_2 R/W-0 F4BP_1 R/W-1 F4BP_0 RXFBCON3 R/W-0 F7BP_3 R/W-0 F7BP_2 R/W-0 F7BP_1 R/W-0 F7BP_0 R/W-0 F6BP_3 R/W-0 F6BP_2 R/W-0 F6BP_1 R/W-0 F6BP_0 RXFBCON4 R/W-0 F9BP_3 R/W-0 F9BP_2 R/W-0 F9BP_1 R/W-0 F9BP_0 R/W-0 F8BP_3 R/W-0 F8BP_2 R/W-0 F8BP_1 R/W-0 F8BP_0 RXFBCON5 R/W-0 F11BP_3 R/W-0 F11BP_2 R/W-0 F11BP_1 R/W-0 F11BP_0 R/W-0 F10BP_3 R/W-0 F10BP_2 R/W-0 F10BP_1 R/W-0 F10BP_0 RXFBCON6 R/W-0 F13BP_3 R/W-0 F13BP_2 R/W-0 F13BP_1 R/W-0 F13BP_0 R/W-0 F12BP_3 R/W-0 F12BP_2 R/W-0 F12BP_1 R/W-0 F12BP_0 R/W-0 F15BP_3 bit 7 R/W-0 F15BP_2 R/W-0 F15BP_1 R/W-0 F15BP_0 R/W-0 F14BP_3 R/W-0 F14BP_2 R/W-0 F14BP_1 R/W-0 F14BP_0 bit 0 RXFBCON7 Legend: R = Readable bit -n = Value at POR bit 7-0 Note 1: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown FnBP_3:FnBP_0: Filter n Buffer Pointer Nibble bits 0000 = Filter n is associated with RXB0 0001 = Filter n is associated with RXB1 0010 = Filter n is associated with B0 0011 = Filter n is associated with B1 ... 0111 = Filter n is associated with B5 1111-1000 = Reserved This register is available in Mode 1 and 2 only. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 307 PIC18F2682/2685/4682/4685 REGISTER 23-48: MSEL0: MASK SELECT REGISTER 0(1) R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 FIL3_1 FIL3_0 FIL2_1 FIL2_0 FIL1_1 FIL1_0 FIL0_1 FIL0_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-6 FIL3_1:FIL3_0: Filter 3 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL2_1:FIL2_0: Filter 2 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 3-2 FIL1_1:FIL1_0: Filter 1 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 1-0 FIL0_1:FIL0_0: Filter 0 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 Note 1: x = Bit is unknown This register is available in Mode 1 and 2 only. DS39761B-page 308 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 23-49: MSEL1: MASK SELECT REGISTER 1(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 FIL7_1 FIL7_0 FIL6_1 FIL6_0 FIL5_1 FIL5_0 FIL4_1 FIL4_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-6 FIL7_1:FIL7_0: Filter 7 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL6_1:FIL6_0: Filter 6 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 3-2 FIL5_1:FIL5_0: Filter 5 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 1-0 FIL4_1:FIL4_0: Filter 4 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 Note 1: x = Bit is unknown This register is available in Mode 1 and 2 only. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 309 PIC18F2682/2685/4682/4685 REGISTER 23-50: MSEL2: MASK SELECT REGISTER 2(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FIL11_1 FIL11_0 FIL10_1 FIL10_0 FIL9_1 FIL9_0 FIL8_1 FIL8_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-6 FIL11_1:FIL11_0: Filter 11 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL10_1:FIL10_0: Filter 10 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 3-2 FIL9_1:FIL9_0: Filter 9 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 1-0 FIL8_1:FIL8_0: Filter 8 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 Note 1: x = Bit is unknown This register is available in Mode 1 and 2 only. DS39761B-page 310 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 23-51: MSEL3: MASK SELECT REGISTER 3(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FIL15_1 FIL15_0 FIL14_1 FIL14_0 FIL13_1 FIL13_0 FIL12_1 FIL12_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-6 FIL15_1:FIL15_0: Filter 15 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL14_1:FIL14_0: Filter 14 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 3-2 FIL13_1:FIL13_0: Filter 13 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 1-0 FIL12_1:FIL12_0: Filter 12 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 Note 1: x = Bit is unknown This register is available in Mode 1 and 2 only. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 311 PIC18F2682/2685/4682/4685 23.2.4 CAN BAUD RATE REGISTERS This section describes the CAN Baud Rate registers. Note: These registers are Configuration mode only. writable in REGISTER 23-52: BRGCON1: BAUD RATE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-6 SJW1:SJW0: Synchronized Jump Width bits 11 = Synchronization jump width time = 4 x TQ 10 = Synchronization jump width time = 3 x TQ 01 = Synchronization jump width time = 2 x TQ 00 = Synchronization jump width time = 1 x TQ bit 5-0 BRP5:BRP0: Baud Rate Prescaler bits 111111 = TQ = (2 x 64)/FOSC 111110 = TQ = (2 x 63)/FOSC : : 000001 = TQ = (2 x 2)/FOSC 000000 = TQ = (2 x 1)/FOSC DS39761B-page 312 Preliminary x = Bit is unknown (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 23-53: BRGCON2: BAUD RATE CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 SEG2PHTS: Phase Segment 2 Time Select bit 1 = Freely programmable 0 = Maximum of PHEG1 or Information Processing Time (IPT), whichever is greater bit 6 SAM: Sample of the CAN bus Line bit 1 = Bus line is sampled three times prior to the sample point 0 = Bus line is sampled once at the sample point bit 5-3 SEG1PH2:SEG1PH0: Phase Segment 1 bits 111 = Phase Segment 1 time = 8 x TQ 110 = Phase Segment 1 time = 7 x TQ 101 = Phase Segment 1 time = 6 x TQ 100 = Phase Segment 1 time = 5 x TQ 011 = Phase Segment 1 time = 4 x TQ 010 = Phase Segment 1 time = 3 x TQ 001 = Phase Segment 1 time = 2 x TQ 000 = Phase Segment 1 time = 1 x TQ bit 2-0 PRSEG2:PRSEG0: Propagation Time Select bits 111 = Propagation time = 8 x TQ 110 = Propagation time = 7 x TQ 101 = Propagation time = 6 x TQ 100 = Propagation time = 5 x TQ 011 = Propagation time = 4 x TQ 010 = Propagation time = 3 x TQ 001 = Propagation time = 2 x TQ 000 = Propagation time = 1 x TQ (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 313 PIC18F2682/2685/4682/4685 REGISTER 23-54: BRGCON3: BAUD RATE CONTROL REGISTER 3 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 WAKDIS WAKFIL -- -- -- SEG2PH2(1) R/W-0 R/W-0 SEG2PH1(1) SEG2PH0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 WAKDIS: Wake-up Disable bit 1 = Disable CAN bus activity wake-up feature 0 = Enable CAN bus activity wake-up feature bit 6 WAKFIL: Selects CAN bus Line Filter for Wake-up bit 1 = Use CAN bus line filter for wake-up 0 = CAN bus line filter is not used for wake-up bit 5-3 Unimplemented: Read as `0' bit 2-0 SEG2PH2:SEG2PH0: Phase Segment 2 Time Select bits(1) 111 = Phase Segment 2 time = 8 x TQ 110 = Phase Segment 2 time = 7 x TQ 101 = Phase Segment 2 time = 6 x TQ 100 = Phase Segment 2 time = 5 x TQ 011 = Phase Segment 2 time = 4 x TQ 010 = Phase Segment 2 time = 3 x TQ 001 = Phase Segment 2 time = 2 x TQ 000 = Phase Segment 2 time = 1 x TQ Note 1: x = Bit is unknown Ignored if SEG2PHTS bit (BRGCON2<7>) is `0'. DS39761B-page 314 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 23.2.5 CAN MODULE I/O CONTROL REGISTER This register controls the operation of the CAN module's I/O pins in relation to the rest of the microcontroller. REGISTER 23-55: CIOCON: CAN I/O CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 -- -- ENDRHI(1) CANCAP -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as `0' bit 5 ENDRHI: Enable Drive High bit(1) 1 = CANTX pin will drive VDD when recessive 0 = CANTX pin will be tri-state when recessive bit 4 CANCAP: CAN Message Receive Capture Enable bit 1 = Enable CAN capture, CAN message receive signal replaces input on RC2/CCP1 0 = Disable CAN capture, RC2/CCP1 input to CCP1 module bit 3-0 Unimplemented: Read as `0' Note 1: Always set this bit when using differential bus to avoid signal crosstalk in CANTX from other nearby pins. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 315 PIC18F2682/2685/4682/4685 23.2.6 CAN INTERRUPT REGISTERS Register 23-56 through Register 23-58 in this section are the same as described in Section 9.0 "Interrupts". They are duplicated here for convenience. REGISTER 23-56: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 Mode 0 Mode 1,2 R/W-0 IRXIF R/W-0 WAKIF R/W-0 ERRIF R/W-0 TXB2IF R/W-0 TXB1IF(1) R/W-0 TXB0IF(1) R/W-0 RXB1IF R/W-0 RXB0IF R/W-0 IRXIF bit 7 R/W-0 WAKIF R/W-0 ERRIF R/W-0 TXBnIF R/W-0 TXB1IF(1) R/W-0 TXB0IF(1) R/W-0 RXBnIF R/W-0 FIFOWMIF bit 0 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown IRXIF: CAN Invalid Received Message Interrupt Flag bit 1 = An invalid message has occurred on the CAN bus 0 = No invalid message on CAN bus WAKIF: CAN bus Activity Wake-up Interrupt Flag bit 1 = Activity on CAN bus has occurred 0 = No activity on CAN bus ERRIF: CAN bus Error Interrupt Flag bit 1 = An error has occurred in the CAN module (multiple sources) 0 = No CAN module errors When CAN is in Mode 0: TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit 1 = Transmit Buffer 2 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 2 has not completed transmission of a message When CAN is in Mode 1 or 2: TXBnIF: Any Transmit Buffer Interrupt Flag bit 1 = One or more transmit buffers have completed transmission of a message and may be reloaded 0 = No transmit buffer is ready for reload TXB1IF: CAN Transmit Buffer 1 Interrupt Flag bit(1) 1 = Transmit Buffer 1 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 1 has not completed transmission of a message TXB0IF: CAN Transmit Buffer 0 Interrupt Flag bit(1) 1 = Transmit Buffer 0 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 0 has not completed transmission of a message When CAN is in Mode 0: RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit 1 = Receive Buffer 1 has received a new message 0 = Receive Buffer 1 has not received a new message When CAN is in Mode 1 or 2: RXBnIF: Any Receive Buffer Interrupt Flag bit 1 = One or more receive buffers has received a new message 0 = No receive buffer has received a new message When CAN is in Mode 0: RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit 1 = Receive Buffer 0 has received a new message 0 = Receive Buffer 0 has not received a new message When CAN is in Mode 1: Unimplemented: Read as `0' When CAN is in Mode 2: FIFOWMIF: FIFO Watermark Interrupt Flag bit 1 = FIFO high watermark is reached 0 = FIFO high watermark is not reached In CAN Mode 1 and 2, these bits are forced to `0'. DS39761B-page 316 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 23-57: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 Mode 0 Mode 1 R/W-0 R/W-0 R/W-0 R/W-0 IRXIE WAKIE ERRIE TXB2IE R/W-0 R/W-0 R/W-0 R/W-0 IRXIE WAKIE ERRIE TXBnIE R/W-0 (1) R/W-0 (1) TXB1IE TXB0IE R/W-0 R/W-0 (1) TXB1IE (1) TXB0IE R/W-0 R/W-0 RXB1IE RXB0IE R/W-0 R/W-0 RXBnIE FIFOWMIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 IRXIE: CAN Invalid Received Message Interrupt Enable bit 1 = Enable invalid message received interrupt 0 = Disable invalid message received interrupt bit 6 WAKIE: CAN bus Activity Wake-up Interrupt Enable bit 1 = Enable bus activity wake-up interrupt 0 = Disable bus activity wake-up interrupt bit 5 ERRIE: CAN bus Error Interrupt Enable bit 1 = Enable CAN bus error interrupt 0 = Disable CAN bus error interrupt bit 4 When CAN is in Mode 0: TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit 1 = Enable Transmit Buffer 2 interrupt 0 = Disable Transmit Buffer 2 interrupt When CAN is in Mode 1 or 2: TXBnIE: CAN Transmit Buffer Interrupts Enable bit 1 = Enable transmit buffer interrupt; individual interrupt is enabled by TXBIE and BIE0 0 = Disable all transmit buffer interrupts bit 3 TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit(1) 1 = Enable Transmit Buffer 1 interrupt 0 = Disable Transmit Buffer 1 interrupt bit 2 TXB0IE: CAN Transmit Buffer 0 Interrupt Enable bit(1) 1 = Enable Transmit Buffer 0 interrupt 0 = Disable Transmit Buffer 0 interrupt bit 1 When CAN is in Mode 0: RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit 1 = Enable Receive Buffer 1 interrupt 0 = Disable Receive Buffer 1 interrupt When CAN is in Mode 1 or 2: RXBnIE: CAN Receive Buffer Interrupts Enable bit 1 = Enable receive buffer interrupt; individual interrupt is enabled by BIE0 0 = Disable all receive buffer interrupts bit 0 When CAN is in Mode 0: RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit 1 = Enable Receive Buffer 0 interrupt 0 = Disable Receive Buffer 0 interrupt When CAN is in Mode 1: Unimplemented: Read as `0' When CAN is in Mode 2: FIFOWMIE: FIFO Watermark Interrupt Enable bit 1 = Enable FIFO watermark interrupt 0 = Disable FIFO watermark interrupt Note 1: In CAN Mode 1 and 2, these bits are forced to `0'. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 317 PIC18F2682/2685/4682/4685 REGISTER 23-58: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 Mode 0 Mode 1,2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IRXIP WAKIP ERRIP TXB2IP TXB1IP(1) TXB0IP(1) RXB1IP RXB0IP R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IRXIP WAKIP ERRIP TXBnIP TXB1IP(1) TXB0IP(1) RXBnIP FIFOWMIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 IRXIP: CAN Invalid Received Message Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 WAKIP: CAN bus Activity Wake-up Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 ERRIP: CAN bus Error Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 When CAN is in Mode 0: TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 1 or 2: TXBnIP: CAN Transmit Buffer Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 2 TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 1 When CAN is in Mode 0: RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 1 or 2: RXBnIP: CAN Receive Buffer Interrupts Priority bit 1 = High priority 0 = Low priority bit 0 When CAN is in Mode 0: RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 1: Unimplemented: Read as `0' When CAN is in Mode 2: FIFOWMIP: FIFO Watermark Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: x = Bit is unknown In CAN Mode 1 and 2, these bits are forced to `0'. DS39761B-page 318 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 23-59: TXBIE: TRANSMIT BUFFERS INTERRUPT ENABLE REGISTER(1) U-0 U-0 -- -- U-0 -- R/W-0 TXB2IE (2) R/W-0 (2) TXB1IE R/W-0 U-0 U-0 -- -- (2) TXB0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-5 Unimplemented: Read as `0' bit 4-2 TXB2IE:TXB0IE: Transmit Buffer 2-0 Interrupt Enable bit(2) 1 = Transmit buffer interrupt is enabled 0 = Transmit buffer interrupt is disabled bit 1-0 Unimplemented: Read as `0' Note 1: 2: x = Bit is unknown This register is available in Mode 1 and 2 only. TXBnIE in PIE3 register must be set to get an interrupt. REGISTER 23-60: BIE0: BUFFER INTERRUPT ENABLE REGISTER 0(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 B5IE(2) B4IE(2) B3IE(2) B2IE(2) B1IE(2) B0IE(2) RXB1IE(2) RXB0IE(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-2 B5IE:B0IE: Programmable Transmit/Receive Buffer 5-0 Interrupt Enable bit(2) 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1-0 RXB1IE:RXB0IE: Dedicated Receive Buffer 1-0 Interrupt Enable bit(2) 1 = Interrupt is enabled 0 = Interrupt is disabled Note 1: 2: This register is available in Mode 1 and 2 only. Either TXBnIE or RXBnIE in PIE3 register must be set to get an interrupt. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 319 PIC18F2682/2685/4682/4685 TABLE 23-1: Address(1) CAN CONTROLLER REGISTER MAP Name Address Name Address Name Address Name F7Fh SPBRGH(3) F7Eh BAUDCON(3) F5Eh CANSTAT_RO0 F3Eh CANSTAT_RO2 F1Eh RXM1EIDH F7Dh --(4) F5Dh RXB1D7 F3Dh TXB1D7 F1Dh RXM1SIDL F7Ch --(4) F5Ch RXB1D6 F3Ch TXB1D6 F1Ch RXM1SIDH F7Bh --(4) F5Bh RXB1D5 F3Bh TXB1D5 F1Bh RXM0EIDL F7Ah (4) -- F5Fh CANCON_RO0 F3Fh CANCON_RO2 F1Fh RXM1EIDL F5Ah RXB1D4 F3Ah TXB1D4 F1Ah RXM0EIDH F79h ECCP1DEL(3) F59h RXB1D3 F39h TXB1D3 F19h RXM0SIDL F78h --(4) F58h RXB1D2 F38h TXB1D2 F18h RXM0SIDH F77h ECANCON F57h RXB1D1 F37h TXB1D1 F17h RXF5EIDL F76h TXERRCNT F56h RXB1D0 F36h TXB1D0 F16h RXF5EIDH F75h RXERRCNT F55h RXB1DLC F35h TXB1DLC F15h RXF5SIDL F74h COMSTAT F54h RXB1EIDL F34h TXB1EIDL F14h RXF5SIDH F73h CIOCON F53h RXB1EIDH F33h TXB1EIDH F13h RXF4EIDL F72h BRGCON3 F52h RXB1SIDL F32h TXB1SIDL F12h RXF4EIDH F71h BRGCON2 F51h RXB1SIDH F31h TXB1SIDH F11h RXF4SIDL F50h RXB1CON F30h TXB1CON F70h BRGCON1 F6Fh CANCON F4Fh CANCON_RO1(2) F2Fh CANCON_RO3(2) F10h RXF4SIDH F6Eh CANSTAT F4Eh CANSTAT_RO1(2) F2Eh CANSTAT_RO3(2) F0Eh RXF3EIDH F6Dh RXB0D7 F4Dh TXB0D7 F2Dh TXB2D7 F0Dh RXF3SIDL F6Ch RXB0D6 F4Ch TXB0D6 F2Ch TXB2D6 F0Ch RXF3SIDH F6Bh RXB0D5 F4Bh TXB0D5 F2Bh TXB2D5 F0Bh RXF2EIDL F6Ah RXB0D4 F4Ah TXB0D4 F2Ah TXB2D4 F0Ah RXF2EIDH F69h RXB0D3 F49h TXB0D3 F29h TXB2D3 F09h RXF2SIDL F68h RXB0D2 F48h TXB0D2 F28h TXB2D2 F08h RXF2SIDH F67h RXB0D1 F47h TXB0D1 F27h TXB2D1 F07h RXF1EIDL F66h RXB0D0 F46h TXB0D0 F26h TXB2D0 F06h RXF1EIDH F65h RXB0DLC F45h TXB0DLC F25h TXB2DLC F05h RXF1SIDL F0Fh RXF3EIDL F64h RXB0EIDL F44h TXB0EIDL F24h TXB2EIDL F04h RXF1SIDH F63h RXB0EIDH F43h TXB0EIDH F23h TXB2EIDH F03h RXF0EIDL F62h RXB0SIDL F42h TXB0SIDL F22h TXB2SIDL F02h RXF0EIDH F61h RXB0SIDH F41h TXB0SIDH F21h TXB2SIDH F01h RXF0SIDL F60h RXB0CON F40h TXB0CON F20h TXB2CON F00h RXF0SIDH Note 1: 2: 3: 4: Shaded registers are available in Access Bank low area, while the rest are available in Bank 15. CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the controller register due to the Microchip header file requirement. These registers are not CAN registers. Unimplemented registers are read as `0'. DS39761B-page 320 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 23-1: CAN CONTROLLER REGISTER MAP (CONTINUED) Address(1) Name EFFh --(4) Address Name EDFh --(4) EFEh (4) -- EFDh --(4) EFCh (4) Address Name Address Name EBFh --(4) E9Fh --(4) EDEh (4) -- EBEh (4) -- E9Eh --(4) EDDh --(4) EBDh --(4) E9Dh --(4) -- EDCh -- (4) EBCh (4) -- E9Ch --(4) EFBh --(4) EDBh --(4) EBBh --(4) E9Bh --(4) EFAh (4) -- EDAh (4) -- EBAh (4) -- E9Ah --(4) EF9h --(4) ED9h --(4) EB9h --(4) E99h --(4) EF8h (4) -- ED8h (4) -- EB8h (4) -- E98h --(4) EF7h --(4) ED7h --(4) EB7h --(4) E97h --(4) EF6h (4) -- ED6h (4) -- EB6h (4) -- E96h --(4) EF5h --(4) ED5h --(4) EB5h --(4) E95h --(4) EF4h --(4) ED4h --(4) EB4h --(4) E94h --(4) EF3h --(4) ED3h --(4) EB3h --(4) E93h --(4) EF2h --(4) ED2h --(4) EB2h --(4) E92h --(4) EF1h --(4) ED1h --(4) EB1h --(4) E91h --(4) EF0h --(4) ED0h --(4) EB0h --(4) E90h --(4) EEFh --(4) ECFh --(4) EAFh --(4) E8Fh --(4) EEEh --(4) ECEh --(4) EAEh --(4) E8Eh --(4) EEDh --(4) ECDh --(4) EADh --(4) E8Dh --(4) EECh --(4) ECCh --(4) EACh --(4) E8Ch --(4) EEBh --(4) ECBh --(4) EABh --(4) E8Bh --(4) EEAh --(4) ECAh --(4) EAAh --(4) E8Ah --(4) EE9h --(4) EC9h --(4) EA9h --(4) E89h --(4) EE8h --(4) EC8h --(4) EA8h --(4) E88h --(4) EE7h --(4) EC7h --(4) EA7h --(4) E87h --(4) EE6h --(4) EC6h --(4) EA6h --(4) E86h --(4) EE5h --(4) EC5h --(4) EA5h --(4) E85h --(4) EE4h --(4) EC4h --(4) EA4h --(4) E84h --(4) EE3h --(4) EC3h --(4) EA3h --(4) E83h --(4) EE2h (4) -- EC2h (4) -- EA2h (4) -- E82h --(4) EE1h --(4) EC1h --(4) EA1h --(4) E81h --(4) EE0h --(4) EC0h --(4) EA0h --(4) E80h --(4) Note 1: 2: 3: 4: Shaded registers are available in Access Bank low area, while the rest are available in Bank 15. CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the controller register due to the Microchip header file requirement. These registers are not CAN registers. Unimplemented registers are read as `0'. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 321 PIC18F2682/2685/4682/4685 TABLE 23-1: CAN CONTROLLER REGISTER MAP (CONTINUED) Address(1) Name Address Name Address Name Address Name E7Fh CANCON_RO4(2) E5Fh CANCON_RO6(2) E3Fh CANCON_RO8(2) E1Fh --(4) (2) (2) (2) E7Eh CANSTAT_RO4 E5Eh CANSTAT_RO6 E3Eh CANSTAT_RO8 E1Eh --(4) E7Dh B5D7 E5Dh B3D7 E3Dh B1D7 E1Dh --(4) E7Ch B5D6 E5Ch B3D6 E3Ch B1D6 E1Ch --(4) E7Bh B5D5 E5Bh B3D5 E3Bh B1D5 E1Bh --(4) E7Ah B5D4 E5Ah B3D4 E3Ah B1D4 E1Ah --(4) E79h B5D3 E59h B3D3 E39h B1D3 E19h --(4) E78h B5D2 E58h B3D2 E38h B1D2 E18h --(4) E77h B5D1 E57h B3D1 E37h B1D1 E17h --(4) E76h B5D0 E56h B3D0 E36h B1D0 E16h --(4) E75h B5DLC E55h B3DLC E35h B1DLC E15h --(4) E74h B5EIDL E54h B3EIDL E34h B1EIDL E14h --(4) E73h B5EIDH E53h B3EIDH E33h B1EIDH E13h --(4) E72h B5SIDL E52h B3SIDL E32h B1SIDL E12h --(4) E71h B5SIDH E51h B3SIDH E31h B1SIDH E11h --(4) E70h B5CON E50h B3CON E30h B1CON E10h --(4) E6Fh CANCON_RO5 E4Fh CANCON_RO7 E2Fh CANCON_RO9 E0Fh --(4) E6Eh CANSTAT_RO5 E4Eh CANSTAT_RO7 E2Eh CANSTAT_RO9 E0Eh --(4) E6Dh B4D7 E4Dh B2D7 E2Dh B0D7 E0Dh --(4) E6Ch B4D6 E4Ch B2D6 E2Ch B0D6 E0Ch --(4) E6Bh B4D5 E4Bh B2D5 E2Bh B0D5 E0Bh --(4) E6Ah B4D4 E4Ah B2D4 E2Ah B0D4 E0Ah --(4) E69h B4D3 E49h B2D3 E29h B0D3 E09h --(4) E68h B4D2 E48h B2D2 E28h B0D2 E08h --(4) E67h B4D1 E47h B2D1 E27h B0D1 E07h --(4) E66h B4D0 E46h B2D0 E26h B0D0 E06h --(4) E65h B4DLC E45h B2DLC E25h B0DLC E05h --(4) E64h B4EIDL E44h B2EIDL E24h B0EIDL E04h --(4) E63h B4EIDH E43h B2EIDH E23h B0EIDH E03h --(4) E62h B4SIDL E42h B2SIDL E22h B0SIDL E02h --(4) E61h B4SIDH E41h B2SIDH E21h B0SIDH E01h --(4) E60h B4CON E40h B2CON E20h B0CON E00h --(4) Note 1: 2: 3: 4: Shaded registers are available in Access Bank low area, while the rest are available in Bank 15. CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the controller register due to the Microchip header file requirement. These registers are not CAN registers. Unimplemented registers are read as `0'. DS39761B-page 322 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 23-1: CAN CONTROLLER REGISTER MAP (CONTINUED) Address(1) Name DFFh --(4) Address Name DDFh --(4) DFEh (4) -- DFDh --(4) Address Name Address Name DBFh --(4) D9Fh --(4) DDEh (4) -- DBEh (4) -- D9Eh --(4) DDDh --(4) DBDh --(4) D9Dh --(4) (4) DBCh (4) -- D9Ch --(4) DFCh TXBIE DDCh -- DFBh --(4) DDBh --(4) DBBh --(4) D9Bh --(4) (4) DBAh (4) -- D9Ah --(4) DB9h --(4) D99h --(4) (4) DFAh BIE0 DDAh -- DF9h --(4) DD9h --(4) DF8h BSEL0 DD8h SDFLC DB8h -- D98h --(4) DF7h --(4) DD7h --(4) DB7h --(4) D97h --(4) DF6h (4) -- DD6h (4) DB6h (4) -- D96h --(4) DF5h --(4) DD5h DB5h --(4) D95h --(4) DF4h --(4) DD4h RXFCON0 DB4h --(4) D94h --(4) DF3h MSEL3 DD3h --(4) DB3h --(4) D93h RXF15EIDL DD2h --(4) DB2h --(4) D92h RXF15EIDH DB1h --(4) D91h RXF15SIDL DB0h --(4) D90h RXF15SIDH DF2h MSEL2 -- RXFCON1 DF1h MSEL1 DD1h --(4) DF0h MSEL0 DD0h --(4) DEFh --(4) DCFh --(4) DAFh --(4) D8Fh --(4) DEEh --(4) DCEh --(4) DAEh --(4) D8Eh --(4) DEDh --(4) DCDh --(4) DADh --(4) D8Dh --(4) DECh --(4) DCCh --(4) DACh --(4) D8Ch --(4) DEBh --(4) DCBh --(4) DABh --(4) D8Bh RXF14EIDL DEAh (4) -- DCAh --(4) DAAh --(4) D8Ah RXF14EIDH DE9h --(4) DC9h --(4) DA9h --(4) D89h RXF14SIDL DE8h --(4) DC8h --(4) DA8h --(4) D88h RXF14SIDH DC7h -- (4) DA7h --(4) D87h RXF13EIDL DC6h --(4) DA6h --(4) D86h RXF13EIDH DA5h --(4) D85h RXF13SIDL DA4h --(4) D84h RXF13SIDH D83h RXF12EIDL DE7h DE6h RXFBCON7 RXFBCON6 DE5h RXFBCON5 DC5h --(4) DE4h RXFBCON4 DC4h --(4) DE3h RXFBCON3 DC3h --(4) DA3h --(4) DE2h RXFBCON2 DC2h --(4) DA2h --(4) D82h RXF12EIDH DC1h -- (4) DA1h --(4) D81h RXF12SIDL DC0h --(4) DA0h --(4) D80h RXF12SIDH DE1h DE0h Note 1: 2: 3: 4: RXFBCON1 RXFBCON0 Shaded registers are available in Access Bank low area, while the rest are available in Bank 15. CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the controller register due to the Microchip header file requirement. These registers are not CAN registers. Unimplemented registers are read as `0'. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 323 PIC18F2682/2685/4682/4685 TABLE 23-1: CAN CONTROLLER REGISTER MAP (CONTINUED) Address(1) Name D7Fh --(4) D7Eh --(4) D7Dh --(4) D7Ch --(4) D7Bh RXF11EIDL D7Ah RXF11EIDH D79h RXF11SIDL D78h RXF11SIDH D77h RXF10EIDL D76h RXF10EIDH D75h RXF10SIDL D74h RXF10SIDH D73h RXF9EIDL D72h RXF9EIDH D71h RXF9SIDL D70h RXF9SIDH D6Fh --(4) D6Eh --(4) D6Dh --(4) D6Ch --(4) D6Bh RXF8EIDL D6Ah RXF8EIDH D69h RXF8SIDL D68h RXF8SIDH D67h RXF7EIDL D66h RXF7EIDH D65h RXF7SIDL D64h RXF7SIDH D63h RXF6EIDL D62h RXF6EIDH D61h RXF6SIDL D60h RXF6SIDH Note 1: 2: 3: 4: Shaded registers are available in Access Bank low area while the rest are available in Bank 15. CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the controller register due to the Microchip header file requirement. These registers are not CAN registers. Unimplemented registers are read as `0'. DS39761B-page 324 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 23.3 23.3.2 CAN Modes of Operation The PIC18F2682/2685/4682/4685 has six main modes of operation: * * * * * * Configuration mode Disable mode Normal Operation mode Listen Only mode Loopback mode Error Recognition mode All modes, except Error Recognition, are requested by setting the REQOP bits (CANCON<7:5>). Error Recognition mode is requested through the RXM bits of the Receive Buffer register(s). Entry into a mode is Acknowledged by monitoring the OPMODE bits. When changing modes, the mode will not actually change until all pending message transmissions are complete. Because of this, the user must verify that the device has actually changed into the requested mode before further operations are executed. 23.3.1 CONFIGURATION MODE The CAN module has to be initialized before the activation. This is only possible if the module is in the Configuration mode. The Configuration mode is requested by setting the REQOP2 bit. Only when the status bit, OPMODE2, has a high level can the initialization be performed. Afterwards, the Configuration registers, the Acceptance Mask registers and the Acceptance Filter registers can be written. The module is activated by setting the REQOP control bits to zero. The module will protect the user from accidentally violating the CAN protocol through programming errors. All registers which control the configuration of the module can not be modified while the module is online. The CAN module will not be allowed to enter the Configuration mode while a transmission or reception is taking place. The Configuration mode serves as a lock to protect the following registers: * * * * * * * Configuration Registers Functional Mode Selection Registers Bit Timing Registers Identifier Acceptance Filter Registers Identifier Acceptance Mask Registers Filter and Mask Control Registers Mask Selection Registers DISABLE MODE In Disable mode, the module will not transmit or receive. The module has the ability to set the WAKIF bit due to bus activity; however, any pending interrupts will remain and the error counters will retain their value. If the REQOP<2:0> bits are set to `001', the module will enter the module Disable mode. This mode is similar to disabling other peripheral modules by turning off the module enables. This causes the module internal clock to stop unless the module is active (i.e., receiving or transmitting a message). If the module is active, the module will wait for 11 recessive bits on the CAN bus, detect that condition as an Idle bus, then accept the module disable command. OPMODE<2:0> = 001 indicates whether the module successfully went into the module Disable mode. The WAKIF interrupt is the only module interrupt that is still active in the Disable mode. If the WAKDIS is cleared and WAKIE is set, the processor will receive an interrupt whenever the module detects recessive to dominant transition. On wake-up, the module will automatically be set to the previous mode of operation. For example, if the module was switched from Normal to Disable mode on bus activity wake-up, the module will automatically enter into Normal mode and the first message that caused the module to wake-up is lost. The module will not generate any error frame. Firmware logic must detect this condition and make sure that retransmission is requested. If the processor receives a wake-up interrupt while it is sleeping, more than one message may get lost. The actual number of messages lost would depend on the processor oscillator start-up time and incoming message bit rate. The I/O pins will revert to normal I/O function when the module is in the Disable mode. 23.3.3 NORMAL MODE This is the standard operating mode of the PIC18F2682/2685/4682/4685 devices. In this mode, the device actively monitors all bus messages and generates Acknowledge bits, error frames, etc. This is also the only mode in which the PIC18F2682/2685/4682/ 4685 devices will transmit messages over the CAN bus. In the Configuration mode, the module will not transmit or receive. The error counters are cleared and the interrupt flags remain unchanged. The programmer will have access to Configuration registers that are access restricted in other modes. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 325 PIC18F2682/2685/4682/4685 23.3.4 LISTEN ONLY MODE 23.4 Listen Only mode provides a means for the PIC18F2682/2685/4682/4685 devices to receive all messages, including messages with errors. This mode can be used for bus monitor applications or for detecting the baud rate in `hot plugging' situations. For Auto-Baud Detection, it is necessary that there are at least two other nodes which are communicating with each other. The baud rate can be detected empirically by testing different values until valid messages are received. The Listen Only mode is a silent mode, meaning no messages will be transmitted while in this state, including error flags or Acknowledge signals. The filters and masks can be used to allow only particular messages to be loaded into the receive registers or the filter masks can be set to all zeros to allow a message with any identifier to pass. The error counters are reset and deactivated in this state. The Listen Only mode is activated by setting the mode request bits in the CANCON register. 23.3.5 LOOPBACK MODE This mode will allow internal transmission of messages from the transmit buffers to the receive buffers without actually transmitting messages on the CAN bus. This mode can be used in system development and testing. In this mode, the ACK bit is ignored and the device will allow incoming messages from itself, just as if they were coming from another node. The Loopback mode is a silent mode, meaning no messages will be transmitted while in this state, including error flags or Acknowledge signals. The TXCAN pin will revert to port I/O while the device is in this mode. The filters and masks can be used to allow only particular messages to be loaded into the receive registers. The masks can be set to all zeros to provide a mode that accepts all messages. The Loopback mode is activated by setting the mode request bits in the CANCON register. 23.3.6 ERROR RECOGNITION MODE The module can be set to ignore all errors and receive any message. In functional Mode 0, the Error Recognition mode is activated by setting the RXM<1:0> bits in the RXBnCON registers to `11'. In this mode, the data which is in the message assembly buffer until the error time, is copied in the receive buffer and can be read via the CPU interface. DS39761B-page 326 ECAN Module Functional Modes In addition to CAN modes of operation, the ECAN module offers a total of 3 functional modes. Each of these modes are identified as Mode 0, Mode 1 and Mode 2. 23.4.1 MODE 0 - LEGACY MODE Mode 0 is designed to be fully compatible with CAN modules used in PIC18CXX8 and PIC18FXX8 devices. This is the default mode of operation on all Reset conditions. As a result, module code written for the PIC18XX8 CAN module may be used on the ECAN module without any code changes. The following is the list of resources available in Mode 0: * Three transmit buffers: TXB0, TXB1 and TXB2 * Two receive buffers: RXB0 and RXB1 * Two acceptance masks, one for each receive buffer: RXM0, RXM1 * Six acceptance filters, 2 for RXB0 and 4 for RXB1: RXF0, RXF1, RXF2, RXF3, RXF4, RXF5 23.4.2 MODE 1 - ENHANCED LEGACY MODE Mode 1 is similar to Mode 0, with the exception that more resources are available in Mode 1. There are 16 acceptance filter registers and two acceptance mask registers. Acceptance Filter 15 can be used as either an acceptance filter or an acceptance mask register. In addition to three transmit and two receive buffers, there are six more message buffers. One or more of these additional buffers can be programmed as transmit or receive buffers. These additional buffers can also be programmed to automatically handle RTR messages. Fourteen of sixteen acceptance filter registers can be dynamically associated to any receive buffer and acceptance mask register. One can use this capability to associate more than one filter to any one buffer. When a receive buffer is programmed to use standard identifier messages, part of the full acceptance filter register can be used as a data byte filter. The length of the data byte filter is programmable from 0 to 18 bits. This functionality simplifies implementation of high-level protocols, such as the DeviceNetTM protocol. The following is the list of resources available in Mode 1: * * * * * Three transmit buffers: TXB0, TXB1 and TXB2 Two receive buffers: RXB0 and RXB1 Six buffers programmable as TX or RX: B0-B5 Automatic RTR handling on B0-B5 Sixteen dynamically assigned acceptance filters: RXF0-RXF15 * Two dedicated acceptance mask registers; RXF15 programmable as third mask: RXM0-RXM1, RXF15 * Programmable data filter on standard identifier messages: SDFLC Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 23.4.3 MODE 2 - ENHANCED FIFO MODE In Mode 2, two or more receive buffers are used to form the receive FIFO (first in, first out) buffer. There is no one-to-one relationship between the receive buffer and acceptance filter registers. Any filter that is enabled and linked to any FIFO receive buffer can generate acceptance and cause FIFO to be updated. FIFO length is user programmable, from 2-8 buffers deep. FIFO length is determined by the very first programmable buffer that is configured as a transmit buffer. For example, if Buffer 2 (B2) is programmed as a transmit buffer, FIFO consists of RXB0, RXB1, B0 and B1 - creating a FIFO length of 4. If all programmable buffers are configured as receive buffers, FIFO will have the maximum length of 8. The following is the list of resources available in Mode 2: * Three transmit buffers: TXB0, TXB1 and TXB2 * Two receive buffers: RXB0 and RXB1 * Six buffers programmable as TX or RX; receive buffers form FIFO: B0-B5 * Automatic RTR handling on B0-B5 * Sixteen acceptance filters: RXF0-RXF15 * Two dedicated acceptance mask registers; RXF15 programmable as third mask: RXM0-RXM1, RXF15 * Programmable data filter on standard identifier messages: SDFLC, useful for DeviceNet protocol 23.5 23.5.1 CAN Message Buffers DEDICATED TRANSMIT BUFFERS The PIC18F2682/2685/4682/4685 devices implement three dedicated transmit buffers - TXB0, TXB1 and TXB2. Each of these buffers occupies 14 bytes of SRAM and are mapped into the SFR memory map. These are the only transmit buffers available in Mode 0. Mode 1 and 2 may access these and other additional buffers. Each transmit buffer contains one control register (TXBnCON), four identifier registers (TXBnSIDL, TXBnSIDH, TXBnEIDL, TXBnEIDH), one data length count register (TXBnDLC) and eight data byte registers (TXBnDm). 23.5.2 Each receive buffer contains one control register (RXBnCON), four identifier registers (RXBnSIDL, RXBnSIDH, RXBnEIDL, RXBnEIDH), one data length count register (RXBnDLC) and eight data byte registers (RXBnDm). There is also a separate Message Assembly Buffer (MAB) which acts as an additional receive buffer. MAB is always committed to receiving the next message from the bus and is not directly accessible to user firmware. The MAB assembles all incoming messages one by one. A message is transferred to appropriate receive buffers only if the corresponding acceptance filter criteria is met. 23.5.3 PROGRAMMABLE TRANSMIT/ RECEIVE BUFFERS The ECAN module implements six new buffers: B0-B5. These buffers are individually programmable as either transmit or receive buffers. These buffers are available only in Mode 1 and 2. As with dedicated transmit and receive buffers, each of these programmable buffers occupies 14 bytes of SRAM and are mapped into SFR memory map. Each buffer contains one control register (BnCON), four identifier registers (BnSIDL, BnSIDH, BnEIDL, BnEIDH), one data length count register (BnDLC) and eight data byte registers (BnDm). Each of these registers contains two sets of control bits. Depending on whether the buffer is configured as transmit or receive, one would use the corresponding control bit set. By default, all buffers are configured as receive buffers. Each buffer can be individually configured as a transmit or receive buffer by setting the corresponding TXENn bit in the BSEL0 register. When configured as transmit buffers, user firmware may access transmit buffers in any order similar to accessing dedicated transmit buffers. In receive configuration with Mode 1 enabled, user firmware may also access receive buffers in any order required. But in Mode 2, all receive buffers are combined to form a single FIFO. Actual FIFO length is programmable by user firmware. Access to FIFO must be done through the FIFO Pointer bits (FP<4:0>) in the CANCON register. It must be noted that there is no hardware protection against out of order FIFO reads. DEDICATED RECEIVE BUFFERS The PIC18F2682/2685/4682/4685 devices implement two dedicated receive buffers - RXB0 and RXB1. Each of these buffers occupies 14 bytes of SRAM and are mapped into SFR memory map. These are the only receive buffers available in Mode 0. Mode 1 and 2 may access these and other additional buffers. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 327 PIC18F2682/2685/4682/4685 23.5.4 PROGRAMMABLE AUTO-RTR BUFFERS In Mode 1 and 2, any of six programmable transmit/ receive buffers may be programmed to automatically respond to predefined RTR messages without user firmware intervention. Automatic RTR handling is enabled by setting the TXnEN bit in the BSEL0 register and the RTREN bit in the BnCON register. After this setup, when an RTR request is received, the TXREQ bit is automatically set and the current buffer content is automatically queued for transmission as a RTR response. As with all transmit buffers, once the TXREQ bit is set, buffer registers become read-only and any writes to them will be ignored. The following outlines the steps automatically handle RTR messages: 1. 2. 3. 4. required to Set buffer to Transmit mode by setting TXnEN bit to `1' in BSEL0 register. At least one acceptance filter must be associated with this buffer and preloaded with expected RTR identifier. Bit RTREN in BnCON register must be set to `1'. Buffer must be preloaded with the data to be sent as a RTR response. Normally, user firmware will keep buffer data registers up to date. If firmware attempts to update the buffer while an automatic RTR response is in the process of transmission, all writes to buffers are ignored. 23.6 23.6.1 CAN Message Transmission INITIATING TRANSMISSION For the MCU to have write access to the message buffer, the TXREQ bit must be clear, indicating that the message buffer is clear of any pending message to be transmitted. At a minimum, the SIDH, SIDL and DLC registers must be loaded. If data bytes are present in the message, the data registers must also be loaded. If the message is to use extended identifiers, the EIDH:EIDL registers must also be loaded and the EXIDE bit set. Setting the TXREQ bit does not initiate a message transmission; it merely flags a message buffer as ready for transmission. Transmission will start when the device detects that the bus is available. The device will then begin transmission of the highest priority message that is ready. When the transmission has completed successfully, the TXREQ bit will be cleared, the TXBnIF bit will be set and an interrupt will be generated if the TXBnIE bit is set. If the message transmission fails, the TXREQ will remain set, indicating that the message is still pending for transmission and one of the following condition flags will be set. If the message started to transmit but encountered an error condition, the TXERR and the IRXIF bits will be set and an interrupt will be generated. If the message lost arbitration, the TXLARB bit will be set. 23.6.2 ABORTING TRANSMISSION The MCU can request to abort a message by clearing the TXREQ bit associated with the corresponding message buffer (TXBnCON<3> or BnCON<3>). Setting the ABAT bit (CANCON<4>) will request an abort of all pending messages. If the message has not yet started transmission, or if the message started but is interrupted by loss of arbitration or an error, the abort will be processed. The abort is indicated when the module sets the TXABT bit for the corresponding buffer (TXBnCON<6> or BnCON<6>). If the message has started to transmit, it will attempt to transmit the current message fully. If the current message is transmitted fully and is not lost to arbitration or an error, the TXABT bit will not be set because the message was transmitted successfully. Likewise, if a message is being transmitted during an abort request and the message is lost to arbitration or an error, the message will not be retransmitted and the TXABT bit will be set, indicating that the message was successfully aborted. Once an abort is requested by setting the ABAT or TXABT bits, it cannot be cleared to cancel the abort request. Only CAN module hardware or a POR condition can clear it. To initiate message transmission, the TXREQ bit must be set for each buffer to be transmitted. When TXREQ is set, the TXABT, TXLARB and TXERR bits will be cleared. To successfully complete the transmission, there must be at least one node with matching baud rate on the network. DS39761B-page 328 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TRANSMIT PRIORITY buffer with the highest priority will be sent first. If two buffers have the same priority setting, the buffer with the highest buffer number will be sent first. There are four levels of transmit priority. If TXP bits for a particular message buffer are set to `11', that buffer has the highest possible priority. If TXP bits for a particular message buffer are set to `00', that buffer has the lowest possible priority. Transmit priority is a prioritization within the PIC18F2682/2685/4682/4685 devices of the pending transmittable messages. This is independent from and not related to any prioritization implicit in the message arbitration scheme built into the CAN protocol. Prior to sending the SOF, the priority of all buffers that are queued for transmission is compared. The transmit TRANSMIT BUFFERS Message Queue Control (c) 2007 Microchip Technology Inc. MESSAGE TXB2IF TXERR TXLARB TXABT TXREQ TXB3 - TXB8 MESSAGE TXB2IF TXERR TXLARB TXREQ TXB2 MESSAGE TXB1IF TXLARB TXABT TXREQ TXB1 MESSAGE TXB0IF TXERR TXLARB TXABT TXREQ TXB0 TXERR FIGURE 23-2: TXABT 23.6.3 Transmit Byte Sequencer Preliminary DS39761B-page 329 PIC18F2682/2685/4682/4685 23.7 23.7.1 Message Reception RECEIVING A MESSAGE Of all receive buffers, the MAB is always committed to receiving the next message from the bus. The MCU can access one buffer while the other buffer is available for message reception or holding a previously received message. Note: The entire contents of the MAB are moved into the receive buffer once a message is accepted. This means that regardless of the type of identifier (standard or extended) and the number of data bytes received, the entire receive buffer is overwritten with the MAB contents. Therefore, the contents of all registers in the buffer must be assumed to have been modified when any message is received. When a message is moved into either of the receive buffers, the associated RXFUL bit is set. This bit must be cleared by the MCU when it has completed processing the message in the buffer in order to allow a new message to be received into the buffer. This bit provides a positive lockout to ensure that the firmware has finished with the message before the module attempts to load a new message into the receive buffer. If the receive interrupt is enabled, an interrupt will be generated to indicate that a valid message has been received. Once a message is loaded into any matching buffer, user firmware may determine exactly what filter caused this reception by checking the filter hit bits in the RXBnCON or BnCON registers. In Mode 0, FILHIT<3:0> of RXBnCON serve as filter hit bits. In Mode 1 and 2, FILHIT<4:0> of BnCON serves as filter hit bits. The same registers also indicate whether the current message is an RTR frame or not. A received message is considered a standard identifier message if the EXID bit in the RXBnSIDL or the BnSIDL register is cleared. Conversely, a set EXID bit indicates an extended identifier message. If the received message is a standard identifier message, user firmware needs to read the SIDL and SIDH registers. In the case of an extended identifier message, firmware should read the SIDL, SIDH, EIDL and EIDH registers. If the RXBnDLC or BnDLC register contain non-zero data count, user firmware should also read the corresponding number of data bytes by accessing the RXBnDm or the BnDm registers. When a received message is an RTR and if the current buffer is not configured for automatic RTR handling, user firmware must take appropriate action and respond manually. Each receive buffer contains RXM bits to set special Receive modes. In Mode 0, RXM<1:0> bits in RXBnCON define a total of four Receive modes. In Mode 1 and 2, RXM1 bit, in combination with the EXID mask and filter bit, define the same four Receive DS39761B-page 330 modes. Normally, these bits are set to `00' to enable reception of all valid messages as determined by the appropriate acceptance filters. In this case, the determination of whether or not to receive standard or extended messages is determined by the EXIDE bit in the acceptance filter register. In Mode 0, if the RXM bits are set to `01' or `10', the receiver will accept only messages with standard or extended identifiers, respectively. If an acceptance filter has the EXIDE bit set such that it does not correspond with the RXM mode, that acceptance filter is rendered useless. In Mode 1 and 2, setting EXID in the SIDL Mask register will ensure that only standard or extended identifiers are received. These two modes of RXM bits can be used in systems where it is known that only standard or extended messages will be on the bus. If the RXM bits are set to `11' (RXM1 = 1 in Mode 1 and 2), the buffer will receive all messages regardless of the values of the acceptance filters. Also, if a message has an error before the end of frame, that portion of the message assembled in the MAB before the error frame will be loaded into the buffer. This mode may serve as a valuable debugging tool for a given CAN network. It should not be used in an actual system environment as the actual system will always have some bus errors and all nodes on the bus are expected to ignore them. In Mode 1 and 2, when a programmable buffer is configured as a transmit buffer and one or more acceptance filters are associated with it, all incoming messages matching this acceptance filter criteria will be discarded. To avoid this scenario, user firmware must make sure that there are no acceptance filters associated with a buffer configured as a transmit buffer. 23.7.2 RECEIVE PRIORITY When in Mode 0, RXB0 is the higher priority buffer and has two message acceptance filters associated with it. RXB1 is the lower priority buffer and has four acceptance filters associated with it. The lower number of acceptance filters makes the match on RXB0 more restrictive and implies a higher priority for that buffer. Additionally, the RXB0CON register can be configured such that if RXB0 contains a valid message and another valid message is received, an overflow error will not occur and the new message will be moved into RXB1 regardless of the acceptance criteria of RXB1. There are also two programmable acceptance filter masks available, one for each receive buffer (see Section 23.5 "CAN Message Buffers"). In Mode 1 and 2, there are a total of 16 acceptance filters available and each can be dynamically assigned to any of the receive buffers. A buffer with a lower number has higher priority. Given this, if an incoming message matches with two or more receive buffer acceptance criteria, the buffer with the lower number will be loaded with that message. Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 23.7.3 ENHANCED FIFO MODE 23.7.4 When configured for Mode 2, two of the dedicated receive buffers in combination with one or more programmable transmit/receive buffers, are used to create a maximum of an 8-buffer deep FIFO buffer. In this mode, there is no direct correlation between filters and receive buffer registers. Any filter that has been enabled can generate an acceptance. When a message has been accepted, it is stored in the next available Receive Buffer register and an Internal Write Pointer is incremented. The FIFO can be a maximum of 8 buffers deep. The entire FIFO must consist of contiguous receive buffers. The FIFO head begins at RXB0 buffer and its tail spans toward B5. The maximum length of the FIFO is limited by the presence or absence of the first transmit buffer starting from B0. If a buffer is configured as a transmit buffer, the FIFO length is reduced accordingly. For instance, if B3 is configured as a transmit buffer, the actual FIFO will consist of RXB0, RXB1, B0, B1 and B2, a total of 5 buffers. If B0 is configured as a transmit buffer, the FIFO length will be 2. If none of the programmable buffers are configured as a transmit buffer, the FIFO will be 8 buffers deep. A system that requires more transmit buffers should try to locate transmit buffers at the very end of B0-B5 buffers to maximize available FIFO length. When a message is received in FIFO mode, the interrupt flag code bits (EICODE<4:0>) in the CANSTAT register will have a value of `10000', indicating the FIFO has received a message. FIFO Pointer bits, FP<3:0> in the CANCON register, point to the buffer that contains data not yet read. The FIFO Pointer bits, in this sense, serve as the FIFO Read Pointer. The user should use FP bits and read corresponding buffer data. When receive data is no longer needed, the RXFUL bit in the current buffer must be cleared, causing FP<3:0> to be updated by the module. To determine whether FIFO is empty or not, the user may use FP<3:0> bits to access the RXFUL bit in the current buffer. If RXFUL is cleared, the FIFO is considered to be empty. If it is set, the FIFO may contain one or more messages. In Mode 2, the module also provides a bit called FIFO High Water Mark (FIFOWM) in the ECANCON register. This bit can be used to cause an interrupt whenever the FIFO contains only one or four empty buffers. The FIFO high water mark interrupt can serve as an early warning to a full FIFO condition. (c) 2007 Microchip Technology Inc. TIME-STAMPING The CAN module can be programmed to generate a time-stamp for every message that is received. When enabled, the module generates a capture signal for CCP1, which in turn, captures the value of either Timer1 or Timer3. This value can be used as the message time-stamp. To use the time-stamp capability, the CANCAP bit (CIOCAN<4>) must be set. This replaces the capture input for CCP1 with the signal generated from the CAN module. In addition, CCP1CON<3:0> must be set to `0011' to enable the CCP Special Event Trigger for CAN events. 23.8 Message Acceptance Filters and Masks The message acceptance filters and masks are used to determine if a message in the Message Assembly Buffer should be loaded into any of the receive buffers. Once a valid message has been received into the MAB, the identifier fields of the message are compared to the filter values. If there is a match, that message will be loaded into the appropriate receive buffer. The filter masks are used to determine which bits in the identifier are examined with the filters. A truth table is shown below in Table 23-2 that indicates how each bit in the identifier is compared to the masks and filters to determine if a message should be loaded into a receive buffer. The mask essentially determines which bits to apply the acceptance filters to. If any mask bit is set to a zero, then that bit will automatically be accepted regardless of the filter bit. TABLE 23-2: FILTER/MASK TRUTH TABLE Mask bit n Filter bit n Message Identifier bit n001 Accept or Reject bit n 0 x x Accept 1 0 0 Accept 1 0 1 Reject 1 1 0 Reject 1 1 1 Accept Legend: x = don't care In Mode 0, acceptance filters RXF0 and RXF1 and filter mask RXM0 are associated with RXB0. Filters RXF2, RXF3, RXF4 and RXF5 and mask RXM1 are associated with RXB1. Preliminary DS39761B-page 331 PIC18F2682/2685/4682/4685 In Mode 1 and 2, there are an additional 10 acceptance filters, RXF6-RXF15, creating a total of 16 available filters. RXF15 can be used either as an acceptance filter or acceptance mask register. Each of these acceptance filters can be individually enabled or disabled by setting or clearing the RXFENn bit in the RXFCONn register. Any of these 16 acceptance filters can be dynamically associated with any of the receive buffers. Actual association is made by setting appropriate bits in the RXFBCONn register. Each RXFBCONn register contains a nibble for each filter. This nibble can be used to associate a specific filter to any of available receive buffers. User firmware may associate more than one filter to any one specific receive buffer. The coding of the RXB0DBEN bit enables these three bits to be used similarly to the FILHIT bits and to distinguish a hit on filter RXF0 and RXF1, in either RXB0 or after a rollover into RXB1. In addition to dynamic filter to buffer association, in Mode 1 and 2, each filter can also be dynamically associated to available acceptance mask registers. The FILn_m bits in the MSELn register can be used to link a specific acceptance filter to an acceptance mask register. As with filter to buffer association, one can also associate more than one mask to a specific acceptance filter. In Mode 1 and 2, each buffer control register contains 5 bits of filter hit bits (FILHIT<4:0>). A binary value of `0' indicates a hit from RXF0 and 15 indicates RXF15. When a filter matches and a message is loaded into the receive buffer, the filter number that enabled the message reception is loaded into the FILHIT bit(s). In Mode 0 for RXB1, the RXB1CON register contains the FILHIT<2:0> bits. They are coded as follows: * * * * * * 101 = Acceptance Filter 5 (RXF5) 100 = Acceptance Filter 4 (RXF4) 011 = Acceptance Filter 3 (RXF3) 010 = Acceptance Filter 2 (RXF2) 001 = Acceptance Filter 1 (RXF1) 000 = Acceptance Filter 0 (RXF0) Note: * * * * 111 = Acceptance Filter 1 (RXF1) 110 = Acceptance Filter 0 (RXF0) 001 = Acceptance Filter 1 (RXF1) 000 = Acceptance Filter 0 (RXF0) If the RXB0DBEN bit is clear, there are six codes corresponding to the six filters. If the RXB0DBEN bit is set, there are six codes corresponding to the six filters, plus two additional codes corresponding to RXF0 and RXF1 filters, that rollover into RXB1. If more than one acceptance filter matches, the FILHIT bits will encode the binary value of the lowest numbered filter that matched. In other words, if filter RXF2 and filter RXF4 match, FILHIT will be loaded with the value for RXF2. This essentially prioritizes the acceptance filters with a lower number filter having higher priority. Messages are compared to filters in ascending order of filter number. The mask and filter registers can only be modified when the PIC18F2682/2685/4682/4685 devices are in Configuration mode. `000' and `001' can only occur if the RXB0DBEN bit is set in the RXB0CON register, allowing RXB0 messages to rollover into RXB1. FIGURE 23-3: MESSAGE ACCEPTANCE MASK AND FILTER OPERATION Acceptance Filter Register RXFn0 Acceptance Mask Register RXMn0 RXMn1 RXFn1 RXFnn RxRqst RXMnn Message Assembly Buffer Identifier DS39761B-page 332 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 23.9 Baud Rate Setting The Nominal Bit Time can be thought of as being divided into separate, non-overlapping time segments. These segments (Figure 23-4) include: All nodes on a given CAN bus must have the same nominal bit rate. The CAN protocol uses Non-Returnto-Zero (NRZ) coding which does not encode a clock within the data stream. Therefore, the receive clock must be recovered by the receiving nodes and synchronized to the transmitter's clock. * * * * As oscillators and transmission time may vary from node to node, the receiver must have some type of Phase Lock Loop (PLL) synchronized to data transmission edges to synchronize and maintain the receiver clock. Since the data is NRZ coded, it is necessary to include bit stuffing to ensure that an edge occurs at least every six bit times to maintain the Digital Phase Lock Loop (DPLL) synchronization. The time segments (and thus the Nominal Bit Time) are in turn made up of integer units of time called Time Quanta or TQ (see Figure 23-4). By definition, the Nominal Bit Time is programmable from a minimum of 8 TQ to a maximum of 25 TQ. Also by definition, the minimum Nominal Bit Time is 1 s, corresponding to a maximum 1 Mb/s rate. The actual duration is given by the following relationship. The bit timing of the PIC18F2682/2685/4682/4685 is implemented using a DPLL that is configured to synchronize to the incoming data and provides the nominal timing for the transmitted data. The DPLL breaks each bit time into multiple segments made up of minimal periods of time called the Time Quanta (TQ). EQUATION 23-2: Nominal Bit Time= TQ * (Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2) The Time Quantum is a fixed unit derived from the oscillator period. It is also defined by the programmable baud rate prescaler, with integer values from 1 to 64, in addition to a fixed divide-by-two for clock generation. Mathematically, this is: Bus timing functions executed within the bit time frame, such as synchronization to the local oscillator, network transmission delay compensation and sample point positioning, are defined by the programmable bit timing logic of the DPLL. All devices on the CAN bus must use the same bit rate. However, all devices are not required to have the same master oscillator clock frequency. For the different clock frequencies of the individual devices, the bit rate has to be adjusted by appropriately setting the baud rate prescaler and number of Time Quanta in each segment. The Nominal Bit Rate is the number of bits transmitted per second, assuming an ideal transmitter with an ideal oscillator, in the absence of resynchronization. The nominal bit rate is defined to be a maximum of 1 Mb/s. The Nominal Bit Time is defined as: EQUATION 23-1: Synchronization Segment (Sync_Seg) Propagation Time Segment (Prop_Seg) Phase Buffer Segment 1 (Phase_Seg1) Phase Buffer Segment 2 (Phase_Seg2) EQUATION 23-3: TQ (s) = (2 * (BRP + 1))/FOSC (MHz) or TQ (s) = (2 * (BRP + 1)) * TOSC (s) where FOSC is the clock frequency, TOSC is the corresponding oscillator period and BRP is an integer (0 through 63) represented by the binary values of BRGCON1<5:0>. The equation above refers to the effective clock frequency used by the microcontroller. If, for example, a 10 MHz crystal in HS mode is used, then the FOSC = 10 MHz and TOSC = 100 ns. If the same 10 MHz crystal is used in HSPLL mode, then the effective frequency is FOSC = 40 MHz and TOSC = 25 ns. TBIT = 1/Nominal Bit Rate FIGURE 23-4: BIT TIME PARTITIONING Input Signal Bit Time Intervals Sync Segment Propagation Segment Phase Segment 1 Phase Segment 2 TQ Sample Point Nominal Bit Time (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 333 PIC18F2682/2685/4682/4685 23.9.1 EXTERNAL CLOCK, INTERNAL CLOCK AND MEASURABLE JITTER IN HSPLL-BASED OSCILLATORS The microcontroller clock frequency generated from a PLL circuit is subject to a jitter, also defined as Phase Jitter or Phase Skew. For its PIC18 Enhanced microcontrollers, Microchip specifies phase jitter (Pjitter) as being 2% (Gaussian distribution, within 3 standard deviations, see parameter F13 in Table 27-7) and Total Jitter (Tjitter) as being 2 * Pjitter. FIGURE 23-5: The CAN protocol uses a bit-stuffing technique that inserts a bit of a given polarity following five bits with the opposite polarity. This gives a total of 10 bits transmitted without re-synchronization (compensation for jitter or phase error). Given the random nature of the jitter error added, it can be shown that the total error caused by the jitter tends to cancel itself over time. For a period of 10 bits, it is necessary to add only two jitter intervals to correct for jitter-induced error: one interval in the beginning of the 10-bit period and another at the end. The overall effect is shown in Figure 23-5. EFFECTS OF PHASE JITTER ON THE MICROCONTROLLER CLOCK AND CAN BIT TIME Nominal Clock Clock with Jitter Phase Skew (Jitter) CAN bit Time with Jitter CAN bit Jitter Once these considerations are taken into account, it is possible to show that the relation between the jitter and the total frequency error can be defined as: For example, assume a CAN bit rate of 125 Kb/s, which gives an NBT of 8 s. For a 16 MHz clock generated from a 4x PLL, the jitter at this clock frequency is: EQUATION 23-4: EQUATION 23-5: T jitter 2 x P jitter f = ------------------------ = -----------------------10 x NBT 10 x NBT 1 0.02 2% x ------------------- = -----------------6 = 1.25ns 16 MHz 16 x10 where jitter is expressed in terms of time and NBT is the Nominal Bit Time. The resultant frequency error is: EQUATION 23-6: -9 2 x ( 1.25 x10 ) -5 --------------------------------------- = 3.125 x10 = 0.0031% -6 10 x ( 8 x10 ) DS39761B-page 334 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Table 23-3 shows the relation between the clock generated by the PLL and the frequency error from jitter (measured jitter-induced error of 2%, Gaussian distribution, within 3 standard deviations), as a percentage of the nominal clock frequency. TABLE 23-3: This is clearly smaller than the expected drift of a crystal oscillator, typically specified at 100 ppm or 0.01%. If we add jitter to oscillator drift, we have a total frequency drift of 0.0132%. The total oscillator frequency errors for common clock frequencies and bit rates, including both drift and jitter, are shown in Table 23-4. FREQUENCY ERROR FROM JITTER AT VARIOUS PLL GENERATED CLOCK SPEEDS Frequency Error at Various Nominal Bit Times (Bit Rates) PLL Output Pjitter Tjitter 8 s (125 Kb/s) 4 s (250 Kb/s) 2 s (500 Kb/s) 1 s (1 Mb/s) 40 MHz 0.5 ns 1 ns 0.00125% 0.00250% 0.005% 0.01% 24 MHz 0.83 ns 1.67 ns 0.00209% 0.00418% 0.008% 0.017% 16 MHz 1.25 ns 2.5 ns 0.00313% 0.00625% 0.013% 0.025% TABLE 23-4: TOTAL FREQUENCY ERROR AT VARIOUS PLL GENERATED CLOCK SPEEDS (100 PPM OSCILLATOR DRIFT, INCLUDING ERROR FROM JITTER) Frequency Error at Various Nominal Bit Times (Bit Rates) Nominal PLL Output 8 s (125 Kb/s) 4 s (250 Kb/s) 2 s (500 Kb/s) 1 s (1 Mb/s) 40 MHz 0.01125% 0.01250% 0.015% 0.02% 24 MHz 0.01209% 0.01418% 0.018% 0.027% 16 MHz 0.01313% 0.01625% 0.023% 0.035% (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 335 PIC18F2682/2685/4682/4685 23.9.2 TIME QUANTA 23.9.3 SYNCHRONIZATION SEGMENT As already mentioned, the Time Quanta is a fixed unit derived from the oscillator period and baud rate prescaler. Its relationship to TBIT and the Nominal Bit Rate is shown in Example 23-6. This part of the bit time is used to synchronize the various CAN nodes on the bus. The edge of the input signal is expected to occur during the sync segment. The duration is 1 TQ. EXAMPLE 23-6: 23.9.4 CALCULATING TQ, NOMINAL BIT RATE AND NOMINAL BIT TIME TQ (s) = (2 * (BRP + 1))/FOSC (MHz) TBIT (s) = TQ (s) * number of TQ per bit interval Nominal Bit Rate (bits/s) = 1/TBIT This frequency (FOSC) refers to the effective frequency used. If, for example, a 10 MHz external signal is used along with a PLL, then the effective frequency will be 4 x 10 MHz which equals 40 MHz. CASE 1: For FOSC = 16 MHz, BRP<5:0> = 00h and Nominal Bit Time = 8 TQ: TQ = (2 * 1)/16 = 0.125 s (125 ns) TBIT = 8 * 0.125 = 1 s (10-6s) Nominal Bit Rate = 1/10-6 = 106 bits/s (1 Mb/s) CASE 2: For FOSC = 20 MHz, BRP<5:0> = 01h and Nominal Bit Time = 8 TQ: TQ = (2 * 2)/20 = 0.2 s (200 ns) Nominal Bit Rate = 1/1.6 * 10-6s = 23.9.5 PHASE BUFFER SEGMENTS The phase buffer segments are used to optimally locate the sampling point of the received bit within the nominal bit time. The sampling point occurs between Phase Segment 1 and Phase Segment 2. These segments can be lengthened or shortened by the resynchronization process. The end of Phase Segment 1 determines the sampling point within a bit time. Phase Segment 1 is programmable from 1 TQ to 8 TQ in duration. Phase Segment 2 provides delay before the next transmitted data transition and is also programmable from 1 TQ to 8 TQ in duration. However, due to IPT requirements, the actual minimum length of Phase Segment 2 is 2 TQ, or it may be defined to be equal to the greater of Phase Segment 1 or the Information Processing Time (IPT). The sampling point should be as late as possible or approximately 80% of the bit time. SAMPLE POINT The sample point is the point of time at which the bus level is read and the value of the received bit is determined. The sampling point occurs at the end of Phase Segment 1. If the bit timing is slow and contains many TQ, it is possible to specify multiple sampling of the bus line at the sample point. The value of the received bit is determined to be the value of the majority decision of three values. The three samples are taken at the sample point and twice before, with a time of TQ/2 between each sample. 625,000 bits/s (625 Kb/s) CASE 3: For FOSC = 25 MHz, BRP<5:0> = 3Fh and Nominal Bit Time = 25 TQ: TQ = (2 * 64)/25 = 5.12 s TBIT = 25 * 5.12 = 128 s (1.28 * 10-4s) Nominal Bit Rate = 1/1.28 * 10-4 = 7813 bits/s (7.8 Kb/s) 23.9.7 The frequencies of the oscillators in the different nodes must be coordinated in order to provide a system wide specified nominal bit time. This means that all oscillators must have a TOSC that is an integral divisor of TQ. It should also be noted that although the number of TQ is programmable from 4 to 25, the usable minimum is 8 TQ. There is no assurance that a bit time of less than 8 TQ in length will operate correctly. DS39761B-page 336 This part of the bit time is used to compensate for physical delay times within the network. These delay times consist of the signal propagation time on the bus line and the internal delay time of the nodes. The length of the Propagation Segment can be programmed from 1 TQ to 8 TQ by setting the PRSEG2:PRSEG0 bits. 23.9.6 TBIT = 8 * 0.2 = 1.6 s (1.6 * 10-6s) PROPAGATION SEGMENT INFORMATION PROCESSING TIME The Information Processing Time (IPT) is the time segment starting at the sample point that is reserved for calculation of the subsequent bit level. The CAN specification defines this time to be less than or equal to 2 TQ. The PIC18F2682/2685/4682/4685 devices define this time to be 2 TQ. Thus, Phase Segment 2 must be at least 2 TQ long. Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 23.10 Synchronization To compensate for phase shifts between the oscillator frequencies of each of the nodes on the bus, each CAN controller must be able to synchronize to the relevant signal edge of the incoming signal. When an edge in the transmitted data is detected, the logic will compare the location of the edge to the expected time (Sync_Seg). The circuit will then adjust the values of Phase Segment 1 and Phase Segment 2 as necessary. There are two mechanisms used for synchronization. 23.10.1 HARD SYNCHRONIZATION Hard synchronization is only done when there is a recessive to dominant edge during a bus Idle condition, indicating the start of a message. After hard synchronization, the bit time counters are restarted with Sync_Seg. Hard synchronization forces the edge which has occurred to lie within the synchronization segment of the restarted bit time. Due to the rules of synchronization, if a hard synchronization occurs, there will not be a resynchronization within that bit time. 23.10.2 RESYNCHRONIZATION As a result of resynchronization, Phase Segment 1 may be lengthened or Phase Segment 2 may be shortened. The amount of lengthening or shortening of the phase buffer segments has an upper bound given by the Synchronization Jump Width (SJW). The value of the SJW will be added to Phase Segment 1 (see Figure 23-6) or subtracted from Phase Segment 2 (see Figure 23-7). The SJW is programmable between 1 TQ and 4 TQ. Clocking information will only be derived from recessive to dominant transitions. The property, that only a fixed maximum number of successive bits have the same value, ensures resynchronization to the bit stream during a frame. FIGURE 23-6: The phase error of an edge is given by the position of the edge relative to Sync_Seg, measured in TQ. The phase error is defined in magnitude of TQ as follows: * e = 0 if the edge lies within Sync_Seg. * e > 0 if the edge lies before the sample point. * e < 0 if the edge lies after the sample point of the previous bit. If the magnitude of the phase error is less than, or equal to, the programmed value of the Synchronization Jump Width, the effect of a resynchronization is the same as that of a hard synchronization. If the magnitude of the phase error is larger than the Synchronization Jump Width and if the phase error is positive, then Phase Segment 1 is lengthened by an amount equal to the Synchronization Jump Width. If the magnitude of the phase error is larger than the resynchronization jump width and if the phase error is negative, then Phase Segment 2 is shortened by an amount equal to the Synchronization Jump Width. 23.10.3 SYNCHRONIZATION RULES * Only one synchronization within one bit time is allowed. * An edge will be used for synchronization only if the value detected at the previous sample point (previously read bus value) differs from the bus value immediately after the edge. * All other recessive to dominant edges fulfilling rules 1 and 2 will be used for resynchronization, with the exception that a node transmitting a dominant bit will not perform a resynchronization as a result of a recessive to dominant edge with a positive phase error. LENGTHENING A BIT PERIOD (ADDING SJW TO PHASE SEGMENT 1) Input Signal Bit Time Segments Sync Prop Segment Phase Segment 1 SJW Phase Segment 2 TQ Sample Point Nominal Bit Length Actual Bit Length (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 337 PIC18F2682/2685/4682/4685 FIGURE 23-7: Sync SHORTENING A BIT PERIOD (SUBTRACTING SJW FROM PHASE SEGMENT 2) Prop Segment Phase Segment 1 TQ Phase Segment 2 SJW Sample Point Actual Bit Length Nominal Bit Length 23.11 Programming Time Segments Some requirements for programming of the time segments: * Prop_Seg + Phase_Seg 1 Phase_Seg 2 * Phase_Seg 2 Sync Jump Width. For example, assume that a 125 kHz CAN baud rate is desired, using 20 MHz for FOSC. With a TOSC of 50 ns, a baud rate prescaler value of 04h gives a TQ of 500 ns. To obtain a Nominal Bit Rate of 125 kHz, the Nominal Bit Time must be 8 s or 16 TQ. Using 1 TQ for the Sync_Seg, 2 TQ for the Prop_Seg and 7 TQ for Phase Segment 1 would place the sample point at 10 TQ after the transition. This leaves 6 TQ for Phase Segment 2. By the rules above, the Sync Jump Width could be the maximum of 4 TQ. However, normally a large SJW is only necessary when the clock generation of the different nodes is inaccurate or unstable, such as using ceramic resonators. Typically, an SJW of 1 is enough. 23.12 Oscillator Tolerance As a rule of thumb, the bit timing requirements allow ceramic resonators to be used in applications with transmission rates of up to 125 Kbit/sec. For the full bus speed range of the CAN protocol, a quartz oscillator is required. A maximum node-to-node oscillator variation of 1.7% is allowed. 23.13 Bit Timing Configuration Registers The Baud Rate Control registers (BRGCON1, BRGCON2, BRGCON3) control the bit timing for the CAN bus interface. These registers can only be modified when the PIC18F2682/2685/4682/4685 devices are in Configuration mode. 23.13.1 BRGCON1 The BRP bits control the baud rate prescaler. The SJW<1:0> bits select the synchronization jump width in terms of multiples of TQ. 23.13.2 BRGCON2 The PRSEG bits set the length of the propagation segment in terms of TQ. The SEG1PH bits set the length of Phase Segment 1 in TQ. The SAM bit controls how many times the RXCAN pin is sampled. Setting this bit to a `1' causes the bus to be sampled three times: twice at TQ/2 before the sample point and once at the normal sample point (which is at the end of Phase Segment 1). The value of the bus is determined to be the value read during at least two of the samples. If the SAM bit is set to a `0', then the RXCAN pin is sampled only once at the sample point. The SEG2PHTS bit controls how the length of Phase Segment 2 is determined. If this bit is set to a `1', then the length of Phase Segment 2 is determined by the SEG2PH bits of BRGCON3. If the SEG2PHTS bit is set to a `0', then the length of Phase Segment 2 is the greater of Phase Segment 1 and the Information Processing Time (which is fixed at 2 TQ for the PIC18F2682/2685/4682/4685). 23.13.3 BRGCON3 The PHSEG2<2:0> bits set the length (in TQ) of Phase Segment 2 if the SEG2PHTS bit is set to a `1'. If the SEG2PHTS bit is set to a `0', then the PHSEG2<2:0> bits have no effect. DS39761B-page 338 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 23.14 Error Detection 23.14.6 The CAN protocol provides sophisticated error detection mechanisms. The following errors can be detected. Detected errors are made public to all other nodes via error frames. The transmission of the erroneous message is aborted and the frame is repeated as soon as possible. Furthermore, each CAN node is in one of the three error states: "error-active", "error-passive" or "bus-off", according to the value of the internal error counters. The error-active state is the usual state where the bus node can transmit messages and activate error frames (made of dominant bits) without any restrictions. In the error-passive state, messages and passive error frames (made of recessive bits) may be transmitted. The bus-off state makes it temporarily impossible for the station to participate in the bus communication. During this state, messages can neither be received nor transmitted. 23.14.1 CRC ERROR With the Cyclic Redundancy Check (CRC), the transmitter calculates special check bits for the bit sequence, from the start of a frame until the end of the data field. This CRC sequence is transmitted in the CRC field. The receiving node also calculates the CRC sequence using the same formula and performs a comparison to the received sequence. If a mismatch is detected, a CRC error has occurred and an error frame is generated. The message is repeated. 23.14.2 ACKNOWLEDGE ERROR 23.14.7 In the Acknowledge field of a message, the transmitter checks if the Acknowledge slot (which was sent out as a recessive bit) contains a dominant bit. If not, no other node has received the frame correctly. An Acknowledge error has occurred, an error frame is generated and the message will have to be repeated. 23.14.3 FORM ERROR If a node detects a dominant bit in one of the four segments, including End-of-Frame, interframe space, Acknowledge delimiter or CRC delimiter, then a form error has occurred and an error frame is generated. The message is repeated. 23.14.4 BIT ERROR A bit error occurs if a transmitter sends a dominant bit and detects a recessive bit, or if it sends a recessive bit and detects a dominant bit, when monitoring the actual bus level and comparing it to the just transmitted bit. In the case where the transmitter sends a recessive bit and a dominant bit is detected during the arbitration field and the Acknowledge slot, no bit error is generated because normal arbitration is occurring. 23.14.5 STUFF BIT ERROR lf, between the Start-of-Frame and the CRC delimiter, six consecutive bits with the same polarity are detected, the bit stuffing rule has been violated. A stuff bit error occurs and an error frame is generated. The message is repeated. (c) 2007 Microchip Technology Inc. ERROR STATES ERROR MODES AND ERROR COUNTERS The PIC18F2682/2685/4682/4685 devices contain two error counters: the Receive Error Counter (RXERRCNT) and the Transmit Error Counter (TXERRCNT). The values of both counters can be read by the MCU. These counters are incremented or decremented in accordance with the CAN bus specification. The PIC18F2682/2685/4682/4685 devices are erroractive if both error counters are below the error-passive limit of 128. They are error-passive if at least one of the error counters equals or exceeds 128. They go to busoff if the transmit error counter equals or exceeds the bus-off limit of 256. The devices remain in this state until the bus-off recovery sequence is received. The bus-off recovery sequence consists of 128 occurrences of 11 consecutive recessive bits (see Figure 23-8). Note that the CAN module, after going bus-off, will recover back to error-active without any intervention by the MCU if the bus remains Idle for 128 x 11 bit times. If this is not desired, the error Interrupt Service Routine should address this. The current Error mode of the CAN module can be read by the MCU via the COMSTAT register. Additionally, there is an Error State Warning flag bit, EWARN, which is set if at least one of the error counters equals or exceeds the error warning limit of 96. EWARN is reset if both error counters are less than the error warning limit. Preliminary DS39761B-page 339 PIC18F2682/2685/4682/4685 FIGURE 23-8: ERROR MODES STATE DIAGRAM Reset ErrorActive RXERRCNT < 127 or TXERRCNT < 127 RXERRCNT > 127 or TXERRCNT > 127 128 occurrences of 11 consecutive "recessive" bits ErrorPassive TXERRCNT > 255 BusOff 23.15 CAN Interrupts The module has several sources of interrupts. Each of these interrupts can be individually enabled or disabled. The PIR3 register contains interrupt flags. The PIE3 register contains the enables for the 8 main interrupts. A special set of read-only bits in the CANSTAT register, the ICODE bits, can be used in combination with a jump table for efficient handling of interrupts. All interrupts have one source, with the exception of the error interrupt and buffer interrupts in Mode 1 and 2. Any of the error interrupt sources can set the error interrupt flag. The source of the error interrupt can be determined by reading the Communication Status register, COMSTAT. In Mode 1 and 2, there are two interrupt enable/disable and flag bits - one for all transmit buffers and the other for all receive buffers. DS39761B-page 340 The interrupts can be broken up into two categories: receive and transmit interrupts. The receive related interrupts are: * * * * * Receive Interrupts Wake-up Interrupt Receiver Overrun Interrupt Receiver Warning Interrupt Receiver Error-Passive Interrupt The transmit related interrupts are: * * * * Transmit Interrupts Transmitter Warning Interrupt Transmitter Error-Passive Interrupt Bus-Off Interrupt Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 23.15.1 INTERRUPT CODE BITS To simplify the interrupt handling process in user firmware, the ECAN module encodes a special set of bits. In Mode 0, these bits are ICODE<3:1> in the CANSTAT register. In Mode 1 and 2, these bits are EICODE<4:0> in the CANSTAT register. Interrupts are internally prioritized such that the higher priority interrupts are assigned lower values. Once the highest priority interrupt condition has been cleared, the code for the next highest priority interrupt that is pending (if any) will be reflected by the ICODE bits (see Table 23-5). Note that only those interrupt sources that have their associated interrupt enable bit set will be reflected in the ICODE bits. In Mode 2, when a receive message interrupt occurs, the EICODE bits will always consist of `10000'. User firmware may use FIFO Pointer bits to actually access the next available buffer. 23.15.2 TRANSMIT INTERRUPT When the transmit interrupt is enabled, an interrupt will be generated when the associated transmit buffer becomes empty and is ready to be loaded with a new message. In Mode 0, there are separate interrupt enable/disable and flag bits for each of the three dedicated transmit buffers. The TXBnIF bit will be set to indicate the source of the interrupt. The interrupt is cleared by the MCU, resetting the TXBnIF bit to a `0'. In Mode 1 and 2, all transmit buffers share one interrupt enable/ disable bit and one flag bit. In Mode 1 and 2, TXBnIE in PIE3 and TXBnIF in PIR3 indicate when a transmit buffer has completed transmission of its message. TXBnIF, TXBnIE and TXBnIP in PIR3, PIE3 and IPR3, respectively, are not used in Mode 1 and 2. Individual transmit buffer interrupts can be enabled or disabled by setting or clearing TXBIE and BIE0 register bits. When a shared interrupt occurs, user firmware must poll the TXREQ bit of all transmit buffers to detect the source of interrupt. 23.15.3 In Mode 0, the RXBnIF bit is set to indicate the source of the interrupt. The interrupt is cleared by the MCU, resetting the RXBnIF bit to a `0'. In Mode 1 and 2, all receive buffers share RXBIE, RXBIF and RXBIP in PIE3, PIR3 and IPR3, respectively. Bits RXBnIE, RXBnIF and RXBnIP are not used. Individual receive buffer interrupts can be controlled by the TXBIE and BIE0 registers. In Mode 1, when a shared receive interrupt occurs, user firmware must poll the RXFUL bit of each receive buffer to detect the source of interrupt. In Mode 2, a receive interrupt indicates that the new message is loaded into FIFO. FIFO can be read by using FIFO Pointer bits, FP. TABLE 23-5: VALUES FOR ICODE<3:1> ICODE Interrupt <2:0> Boolean Expression 000 None ERR*WAK*TX0*TX1*TX2*RX0*RX1 001 Error ERR 010 TXB2 ERR*TX0*TX1*TX2 011 TXB1 ERR*TX0*TX1 100 TXB0 ERR*TX0 101 RXB1 ERR*TX0*TX1*TX2*RX0*RX1 110 RXB0 ERR*TX0*TX1*TX2*RX0 111 Wake on ERR*TX0*TX1*TX2*RX0*RX1*WAK Interrupt Legend: ERR = ERRIF * ERRIE RX0 = RXB0IF * RXB0IE TX0 = TXB0IF * TXB0IE RX1 = RXB1IF * RXB1IE TX1 = TXB1IF * TXB1IE WAK = WAKIF * WAKIE TX2 = TXB2IF * TXB2IE RECEIVE INTERRUPT When the receive interrupt is enabled, an interrupt will be generated when a message has been successfully received and loaded into the associated receive buffer. This interrupt is activated immediately after receiving the End-Of-Frame (EOF) field. (c) 2007 Microchip Technology Inc. 23.15.4 MESSAGE ERROR INTERRUPT When an error occurs during transmission or reception of a message, the message error flag, IRXIF, will be set and if the IRXIE bit is set, an interrupt will be generated. This is intended to be used to facilitate baud rate determination when used in conjunction with Listen Only mode. Preliminary DS39761B-page 341 PIC18F2682/2685/4682/4685 23.15.5 BUS ACTIVITY WAKE-UP INTERRUPT 23.15.6.3 When the PIC18F2682/2685/4682/4685 devices are in Sleep mode and the bus activity wake-up interrupt is enabled, an interrupt will be generated and the WAKIF bit will be set when activity is detected on the CAN bus. This interrupt causes the PIC18F2682/2685/4682/ 4685 devices to exit Sleep mode. The interrupt is reset by the MCU, clearing the WAKIF bit. 23.15.6 When the error interrupt is enabled, an interrupt is generated if an overflow condition occurs or if the error state of the transmitter or receiver has changed. The error flags in COMSTAT will indicate one of the following conditions. 23.15.6.1 Receiver Overflow An overflow condition occurs when the MAB has assembled a valid received message (the message meets the criteria of the acceptance filters) and the receive buffer associated with the filter is not available for loading of a new message. The associated RXBnOVFL bit in the COMSTAT register will be set to indicate the overflow condition. This bit must be cleared by the MCU. 23.15.6.2 The transmit error counter has reached the MCU warning limit of 96. 23.15.6.4 Receiver Bus Passive The receive error counter has exceeded the errorpassive limit of 127 and the device has gone to error-passive state. 23.15.6.5 ERROR INTERRUPT Transmitter Warning Transmitter Bus Passive The transmit error counter has exceeded the errorpassive limit of 127 and the device has gone to error-passive state. 23.15.6.6 Bus-Off The transmit error counter has exceeded 255 and the device has gone to bus-off state. 23.15.6.7 Interrupt Acknowledge Interrupts are directly associated with one or more status flags in the PIR register. Interrupts are pending as long as one of the flags is set. Once an interrupt flag is set by the device, the flag can not be reset by the microcontroller until the interrupt condition is removed. Receiver Warning The receive error counter has reached the MCU warning limit of 96. DS39761B-page 342 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 24.0 SPECIAL FEATURES OF THE CPU PIC18F2682/2685/4682/4685 devices include several features intended to maximize reliability and minimize cost through elimination of external components. These are: * Oscillator Selection * Resets: - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * Fail-Safe Clock Monitor * Two-Speed Start-up * Code Protection * ID Locations * In-Circuit Serial Programming All of these features are enabled and configured by setting the appropriate Configuration register bits. 24.1 The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (300000h-3FFFFFh), which can only be accessed using table reads and table writes. A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. In addition to their Power-up and Oscillator Start-up Timers provided for Resets, PIC18F2682/2685/4682/ 4685 devices have a Watchdog Timer, which is either permanently enabled via the Configuration bits or software controlled (if configured as disabled). Programming the Configuration registers is done in a manner similar to programming the Flash memory. The WR bit in the EECON1 register starts a self-timed write to the Configuration register. In normal operation mode, a TBLWT instruction with the TBLPTR pointing to the Configuration register sets up the address and the data for the Configuration register write. Setting the WR bit starts a long write to the Configuration register. The Configuration registers are written a byte at a time. To write or erase a configuration cell, a TBLWT instruction can write a `1' or a `0' into the cell. For additional details on Flash programming, refer to Section 6.5 "Writing to Flash Program Memory". CONFIGURATION BITS AND DEVICE IDs Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/ Unprogrammed Value CONFIG1H IESO FCMEN -- -- FOSC3 FOSC2 FOSC1 FOSC0 00-- 0111 BORV1 BORV0 BOREN1 File Name 300001h Configuration Bits The Configuration bits can be programmed (read as `0') or left unprogrammed (read as `1') to select various device configurations. These bits are mapped starting at program memory location 300000h. The oscillator can be configured for the application depending on frequency, power, accuracy and cost. All of the options are discussed in detail in Section 2.0 "Oscillator Configurations". TABLE 24-1: The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. TwoSpeed Start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays. 300002h CONFIG2L -- -- -- 300003h CONFIG2H -- -- -- 300005h CONFIG3H MCLRE -- -- -- 300006h CONFIG4L DEBUG XINST BBSIZ1 BBSIZ2 -- LVP -- STVREN 1000 -1-1 300008h CONFIG5L -- -- CP5(1) CP4 CP3 CP2 CP1 CP0 --11 1111 300009h CONFIG5H CPD CPB -- -- -- -- -- -- 11-- ---- (1) -- LPT1OSC PBADEN ---1 1111 WDTEN ---1 1111 -- 1--- -01- 30000Ah CONFIG6L -- -- WRT4 WRT3 WRT2 WRT1 WRT0 --11 1111 30000Bh CONFIG6H WRTD WRTB WRTC -- -- -- -- -- 111- ---- 30000Ch CONFIG7L -- -- EBTR5(1) EBTR4 EBTR3 EBTR2 EBTR1 EBTR0 --11 1111 30000Dh CONFIG7H -- EBTRB -- -- -- -- -- -- -1-- ---- 3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(2) 3FFFFFh DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 xxxx xxxx(2) DEVID2 WRT5 BOREN0 PWRTEN WDTPS3 WDTPS2 WDTPS1 WDTPS0 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as `0'. Note 1: Unimplemented in PIC18F2682/4682 devices; maintain this bIt set. 2: See Register 24-12 and Register 24-13 for DEVID1 and DEVID2 values. DEVID registers are read-only and cannot be programmed by the user. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 343 PIC18F2682/2685/4682/4685 REGISTER 24-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-0 R/P-0 U-0 U-0 R/P-0 R/P-1 R/P-1 R/P-1 IESO FCMEN -- -- FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' u = Unchanged from programmed state bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode enabled 0 = Oscillator Switchover mode disabled bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled bit 5-4 Unimplemented: Read as `0' bit 3-0 FOSC3:FOSC0: Oscillator Selection bits 11xx = External RC oscillator, CLKO function on RA6 101x = External RC oscillator, CLKO function on RA6 1001 = Internal oscillator block, CLKO function on RA6, port function on RA7 1000 = Internal oscillator block, port function on RA6 and RA7 0111 = External RC oscillator, port function on RA6 0110 = HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) 0101 = EC oscillator, port function on RA6 0100 = EC oscillator, CLKO function on RA6 0011 = External RC oscillator, CLKO function on RA6 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator DS39761B-page 344 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 24-2: U-0 CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 -- -- U-0 -- R/P-1 BORV1 R/P-1 BORV0 R/P-1 R/P-1 (1) BOREN1 BOREN0 bit 7 R/P-1 (1) PWRTEN(1) bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' u = Unchanged from programmed state bit 7-5 Unimplemented: Read as `0' bit 4-3 BORV1:BORV0: Brown-out Reset Voltage bits 11 = Minimum setting . . . 00 = Maximum setting bit 2-1 BOREN1:BOREN0: Brown-out Reset Enable bits(1) 11 = Brown-out Reset enabled in hardware only (SBOREN is disabled) 10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) 01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled) 00 = Brown-out Reset disabled in hardware and software bit 0 PWRTEN: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled Note 1: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 345 PIC18F2682/2685/4682/4685 REGISTER 24-3: U-0 CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 -- -- U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 -- WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' u = Unchanged from programmed state bit 7-5 Unimplemented: Read as `0' bit 4-1 WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) DS39761B-page 346 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 24-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 U-0 U-0 U-0 U-0 R/P-0 R/P-1 U-0 MCLRE -- -- -- -- LPT1OSC PBADEN -- bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' u = Unchanged from programmed state bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled; RE3 input pin disabled 0 = RE3 input pin enabled; MCLR disabled bit 6-3 Unimplemented: Read as `0' bit 2 LPT1OSC: Low-Power Timer1 Oscillator Enable bit 1 = Timer1 configured for low-power operation 0 = Timer1 configured for higher power operation bit 1 PBADEN: PORTB A/D Enable bit (Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin configuration.) 1 = PORTB<4:0> pins are configured as analog input channels on Reset 0 = PORTB<4:0> pins are configured as digital I/O on Reset bit 0 Unimplemented: Read as `0' REGISTER 24-5: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 R/P-0 R/P-0 R/P-0 U-0 R/P-1 U-0 R/P-1 DEBUG XINST BBSIZ1 BBSIZ2 -- LVP -- STVREN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' u = Unchanged from programmed state bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug bit 6 XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode) bit 5 BBSIZ1: Boot Block Size Select Bit 1 11 = 4K words (8 Kbytes) boot block 10 = 4K words (8 Kbytes) boot block bit 4 BBSIZ2: Boot Block Size Select Bit 0 01 = 2K words (4 Kbytes) boot block 00 = 1K words (2 Kbytes) boot block bit 3 Unimplemented: Read as `0' bit 2 LVP: Single-Supply ICSPTM Enable bit 1 = Single-Supply ICSP enabled 0 = Single-Supply ICSP disabled bit 1 Unimplemented: Read as `0' bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause Reset 0 = Stack full/underflow will not cause Reset (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 347 PIC18F2682/2685/4682/4685 REGISTER 24-6: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 -- -- CP5(1) CP4 CP3 CP2 CP1 CP0 bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-6 Unimplemented: Read as `0' bit 5 CP5: Code Protection bit(1) 1 = Block 5 (014000-017FFFh) not code-protected 0 = Block 5 (014000-017FFFh) code-protected bit 4 CP4: Code Protection bit 1 = Block 4 (010000-013FFFh) not code-protected 0 = Block 4 (010000-013FFFh) code-protected bit 3 CP3: Code Protection bit 1 = Block 3 (00C000-00FFFFh) not code-protected 0 = Block 3 (00C000-00FFFFh) code-protected bit 2 CP2: Code Protection bit 1 = Block 2 (008000-00BFFFh) not code-protected 0 = Block 2 (008000-00BFFFh) code-protected bit 1 CP1: Code Protection bit 1 = Block 1 (004000-007FFFh) not code-protected 0 = Block 1 (004000-007FFFh) code-protected bit 0 CP0: Code Protection bit 1 = Block 0 (000800-003FFFh) not code-protected 0 = Block 0 (000800-003FFFh) code-protected Note 1: Unimplemented in PIC18F2682/4682 devices; maintain this bit set. REGISTER 24-7: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h) R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD CPB -- -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM not code-protected 0 = Data EEPROM code-protected bit 6 CPB: Boot Block Code Protection bit 1 = Boot Block (000000-0007FFh) not code-protected 0 = Boot Block (000000-0007FFh) code-protected bit 5-0 Unimplemented: Read as `0' DS39761B-page 348 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 24-8: U-0 CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) U-0 -- -- R/C-1 (1) WRT5 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 WRT4 WRT3 WRT2 WRT1 WRT0 bit 7 bit 0 Legend: R = Readable bit C = Clearable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' u = Unchanged from programmed state bit 7-6 Unimplemented: Read as `0' bit 5 WRT5: Write Protection bit(1) 1 = Block 5 (014000-017FFFh) not write-protected 0 = Block 5 (014000-017FFFh) write-protected bit 4 WRT4: Write Protection bit 1 = Block 4 (010000-013FFFh) not write-protected 0 = Block 4 (010000-013FFFh) write-protected bit 3 WRT3: Write Protection bit 1 = Block 3 (00C000-00FFFFh) not write-protected 0 = Block 3 (00C000-00FFFFh) write-protected bit 2 WRT2: Write Protection bit 1 = Block 2 (008000-00BFFFh) not write-protected 0 = Block 2 (008000-00BFFFh) write-protected bit 1 WRT1: Write Protection bit 1 = Block 1 (004000-007FFFh) not write-protected 0 = Block 1 (004000-007FFFh) write-protected bit 0 WRT0: Write Protection bit 1 = Block 0 (000800-003FFFh) not write-protected 0 = Block 0 (000800-003FFFh) write-protected Note 1: Unimplemented in PIC18F2682/4682 devices; maintain this bit set. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 349 PIC18F2682/2685/4682/4685 REGISTER 24-9: R/C-1 CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh) R/C-1 WRTD WRTB R-1 (1) WRTC U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write-protected 0 = Data EEPROM write-protected bit 6 WRTB: Boot Block Write Protection bit 1 = Boot Block (000000-0007FFh) not write-protected 0 = Boot Block (000000-0007FFh) write-protected bit 5 WRTC: Configuration Register Write Protection bit(1) 1 = Configuration registers (300000-3000FFh) not write-protected 0 = Configuration registers (300000-3000FFh) write-protected bit 4-0 Unimplemented: Read as `0' Note 1: This bit is read-only in normal execution mode; it can be written only in Program mode. DS39761B-page 350 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 REGISTER 24-10: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 -- -- EBTR5(1) EBTR4 EBTR3 EBTR2 EBTR1 EBTR0 bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-6 Unimplemented: Read as `0' bit 5 EBTR5: Table Read Protection bit(1) 1 = Block 5 (014000-017FFFh) not protected from table reads executed in other blocks 0 = Block 5 (014000-017FFFh) protected from table reads executed in other blocks bit 4 EBTR4: Table Read Protection bit 1 = Block 4 (010000-013FFFh) not protected from table reads executed in other blocks 0 = Block 4 (010000-013FFFh) protected from table reads executed in other blocks bit 3 EBTR3: Table Read Protection bit 1 = Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks 0 = Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks bit 2 EBTR2: Table Read Protection bit(1) 1 = Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks 0 = Block 2 (008000-00BFFFh) protected from table reads executed in other blocks bit 1 EBTR1: Table Read Protection bit 1 = Block 1 (004000-007FFFh) not protected from table reads executed in other blocks 0 = Block 1 (004000-007FFFh) protected from table reads executed in other blocks bit 0 EBTR0: Table Read Protection bit 1 = Block 0 (000800-003FFFh) not protected from table reads executed in other blocks 0 = Block 0 (000800-003FFFh) protected from table reads executed in other blocks Note 1: Unimplemented in PIC18F2682/4682 devices; maintain this bit set. REGISTER 24-11: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh) U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 -- EBTRB -- -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit C = Clearable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' u = Unchanged from programmed state bit 7 Unimplemented: Read as `0' bit 6 EBTRB: Boot Block Table Read Protection bit 1 = Boot Block (000000-0007FFh) not protected from table reads executed in other blocks 0 = Boot Block (000000-0007FFh) protected from table reads executed in other blocks bit 5-0 Unimplemented: Read as `0' (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 351 PIC18F2682/2685/4682/4685 REGISTER 24-12: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2682/2685/4682/4685 R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Read-only bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' u = Unchanged from programmed state bit 7-5 DEV2:DEV0: Device ID bits 000 = PIC18F2682 001 = PIC18F2685 010 = PIC18F4682 011 = PIC18F4685 bit 4-0 REV3:REV0: Revision ID bits These bits are used to indicate the device revision. REGISTER 24-13: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F2682/2685/4682/4685 R R R R R R R R DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 0 Legend: R = Read-only bit P = Programmable bit -n = Value when device is unprogrammed bit 7-0 Note 1: U = Unimplemented bit, read as `0' u = Unchanged from programmed state DEV10:DEV3: Device ID bits These bits are used with the DEV2:DEV0 bits in Device ID Register 1 to identify the part number. 0010 0111 = PIC18F2682/2685/4682/4685 devices These values for DEV10:DEV3 may be shared with other devices. The specific device is always identified by using the entire DEV10:DEV0 bit sequence. DS39761B-page 352 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 24.2 Watchdog Timer (WDT) For PIC18F2682/2685/4682/4685 devices, the WDT is driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configuration Register 2H. Available periods range from 4 ms to 131.072 seconds (2.18 minutes). The WDT and postscaler are cleared when any of the following events occur: a SLEEP or CLRWDT instruction is executed, the IRCF bits (OSCCON<6:4>) are changed or a clock failure has occurred. . FIGURE 24-1: Note 1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts when executed. 2: Changing the setting of the IRCF bits (OSCCON<6:4>) clears the WDT and postscaler counts. 3: When a CLRWDT instruction is executed, the postscaler count will be cleared. 24.2.1 CONTROL REGISTER Register 24-14 shows the WDTCON register. This is a readable and writable register which contains a control bit that allows software to override the WDT enable Configuration bit, but only if the Configuration bit has disabled the WDT. WDT BLOCK DIAGRAM SWDTEN WDTEN Enable WDT INTRC Control WDT Counter INTRC Source Wake-up from Power-Managed Modes /128 Change on IRCF bits Programmable Postscaler 1:1 to 1:32,768 CLRWDT All Device Resets WDTPS<3:0> Reset WDT Reset WDT 4 Sleep (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 353 PIC18F2682/2685/4682/4685 REGISTER 24-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 -- -- -- -- -- -- -- SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-1 Unimplemented: Read as `0' bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled. TABLE 24-2: Name RCON WDTCON x = Bit is unknown SUMMARY OF WATCHDOG TIMER REGISTERS Bit 0 Reset Values on page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 IPEN SBOREN -- RI TO PD POR BOR 48 -- -- -- -- -- -- -- SWDTEN 50 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Watchdog Timer. DS39761B-page 354 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 24.3 Two-Speed Start-up Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting the IRCF2:IRCF0 bits prior to entering Sleep mode. The Two-Speed Start-up feature helps to minimize the latency period from oscillator start-up to code execution by allowing the microcontroller to use the INTRC oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO Configuration bit. In all other power-managed modes, Two-Speed Start-up is not used. The device will be clocked by the currently selected clock source until the primary clock source becomes available. The setting of the IESO bit is ignored. Two-Speed Start-up should be enabled only if the primary oscillator mode is LP, XT, HS or HSPLL (Crystal-based modes). Other sources do not require an OST start-up delay; for these, Two-Speed Start-up should be disabled. 24.3.1 While using the INTRC oscillator in Two-Speed Start-up, the device still obeys the normal command sequences for entering power-managed modes, including serial SLEEP instructions (refer to Section 3.1.4 "Multiple Sleep Commands"). In practice, this means that user code can change the SCS1:SCS0 bit settings or issue SLEEP instructions before the OST times out. This would allow an application to briefly wake-up, perform routine "housekeeping" tasks and return to Sleep before the device starts to operate from the primary oscillator. When enabled, Resets and wake-ups from Sleep mode cause the device to configure itself to run from the internal oscillator block as the clock source, following the time-out of the Power-up Timer after a Power-on Reset is enabled. This allows almost immediate code execution while the primary oscillator starts and the OST is running. Once the OST times out, the device automatically switches to PRI_RUN mode. Because the OSCCON register is cleared on Reset events, the INTOSC (or postscaler) clock source is not initially available after a Reset event; the INTRC clock is used directly at its base frequency. To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits, IRCF2:IRCF0, immediately after FIGURE 24-2: SPECIAL CONSIDERATIONS FOR USING TWO-SPEED START-UP User code can also check if the primary clock source is currently providing the device clocking by checking the status of the OSTS bit (OSCCON<3>). If the bit is set, the primary oscillator is providing the clock. Otherwise, the internal oscillator block is providing the clock during wake-up from Reset or Sleep mode. TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL) Q1 Q2 Q3 Q4 Q2 Q3 Q4 Q1 Q2 Q3 Q1 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 PLL Clock Output 2 n-1 n Clock Transition CPU Clock Peripheral Clock Program Counter PC Wake from Interrupt Event Note 1: PC + 2 PC + 4 PC + 6 OSTS bit Set TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 355 PIC18F2682/2685/4682/4685 24.4 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block. The FSCM function is enabled by setting the FCMEN Configuration bit. When FSCM is enabled, the INTRC oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure. Clock monitoring (shown in Figure 24-3) is accomplished by creating a sample clock signal, which is the INTRC output divided by 64. This allows ample time between FSCM sample clocks for a peripheral clock edge to occur. The peripheral device clock and the sample clock are presented as inputs to the Clock Monitor latch (CM). The CM is set on the falling edge of the device clock source, but cleared on the rising edge of the sample clock. FIGURE 24-3: FSCM BLOCK DIAGRAM Clock Monitor Latch (CM) (edge-triggered) Peripheral Clock INTRC Source (32 s) / 64 S Q C Q To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits, IRCF2:IRCF0, immediately after Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting the IRCF2:IRCF0 bits prior to entering Sleep mode. The FSCM will detect failures of the primary or secondary clock sources only. If the internal oscillator block fails, no failure would be detected, nor would any action be possible. 24.4.1 Both the FSCM and the WDT are clocked by the INTRC oscillator. Since the WDT operates with a separate divider and counter, disabling the WDT has no effect on the operation of the INTRC oscillator when the FSCM is enabled. As already noted, the clock source is switched to the INTOSC clock when a clock failure is detected. Depending on the frequency selected by the IRCF2:IRCF0 bits, this may mean a substantial change in the speed of code execution. If the WDT is enabled with a small prescale value, a decrease in clock speed allows a WDT time-out to occur and a subsequent device Reset. For this reason, fail-safe clock events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed and decreasing the likelihood of an erroneous time-out. 24.4.2 488 Hz (2.048 ms) Clock Failure Detected Clock failure is tested for on the falling edge of the sample clock. If a sample clock falling edge occurs while CM is still set, a clock failure has been detected (Figure 24-4). This causes the following: * the FSCM generates an oscillator fail interrupt by setting bit, OSCFIF (PIR2<7>); * the device clock source is switched to the internal oscillator block (OSCCON is not updated to show the current clock source - this is the fail-safe condition); and * the WDT is reset. FSCM AND THE WATCHDOG TIMER EXITING FAIL-SAFE OPERATION The fail-safe condition is terminated by either a device Reset or by entering a power-managed mode. On Reset, the controller starts the primary clock source specified in Configuration Register 1H (with any required start-up delays that are required for the oscillator mode, such as OST or PLL timer). The INTOSC multiplexer provides the device clock until the primary clock source becomes ready (similar to a TwoSpeed Start-up). The clock source is then switched to the primary clock (indicated by the OSTS bit in the OSCCON register becoming set). The Fail-Safe Clock Monitor then resumes monitoring the peripheral clock. The primary clock source may never become ready during start-up. In this case, operation is clocked by the INTOSC multiplexer. The OSCCON register will remain in its Reset state until a power-managed mode is entered. During switchover, the postscaler frequency from the internal oscillator block may not be sufficiently stable for timing sensitive applications. In these cases, it may be desirable to select another clock configuration and enter an alternate power-managed mode. This can be done to attempt a partial recovery or execute a controlled shutdown. See Section 3.1.4 "Multiple Sleep Commands" and Section 24.3.1 "Special Considerations for Using Two-Speed Start-up" for more details. DS39761B-page 356 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 FIGURE 24-4: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure Device Clock Output CM Output (Q) Failure Detected OSCFIF CM Test Note: 24.4.3 CM Test The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. FSCM INTERRUPTS IN POWER-MANAGED MODES By entering a power-managed mode, the clock multiplexer selects the clock source selected by the OSCCON register. Fail-Safe Monitoring of the powermanaged clock source resumes in the power-managed mode. If an oscillator failure occurs during power-managed operation, the subsequent events depend on whether or not the oscillator failure interrupt is enabled. If enabled (OSCFIF = 1), code execution will be clocked by the INTOSC multiplexer. An automatic transition back to the failed clock source will not occur. time considerably longer than the FCSM sample clock time, a false clock failure may be detected. To prevent this, the internal oscillator block is automatically configured as the device clock and functions until the primary clock is stable (the OST and PLL timers have timed out). This is identical to Two-Speed Start-up mode. Once the primary clock is stable, the INTRC returns to its role as the FSCM source. Note: If the interrupt is disabled, subsequent interrupts while in Idle mode will cause the CPU to begin executing instructions while being clocked by the INTOSC source. 24.4.4 CM Test POR OR WAKE-UP FROM SLEEP The FSCM is designed to detect oscillator failure at any point after the device has exited Power-on Reset (POR) or low-power Sleep mode. When the primary device clock is EC, RC or INTRC, monitoring can begin immediately following these events. The same logic that prevents false oscillator failure interrupts on POR, or wake from Sleep, will also prevent the detection of the oscillator's failure to start at all following these events. This can be avoided by monitoring the OSTS bit and using a timing routine to determine if the oscillator is taking too long to start. Even so, no oscillator failure interrupt will be flagged. As noted in Section 24.3.1 "Special Considerations for Using Two-Speed Start-up", it is also possible to select another clock configuration and enter an alternate power-managed mode while waiting for the primary clock to become stable. When the new power-managed mode is selected, the primary clock is disabled. For oscillator modes involving a crystal or resonator (HS, HSPLL, LP or XT), the situation is somewhat different. Since the oscillator may require a start-up (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 357 PIC18F2682/2685/4682/4685 24.5 Program Verification and Code Protection Each of the five blocks has three code protection bits associated with them. They are: The overall structure of the code protection on the PIC18 Flash devices differs significantly from other PIC devices. * Code-Protect bit (CPn) * Write-Protect bit (WRTn) * External Block Table Read bit (EBTRn) The user program memory is divided into five blocks. One of these is a boot block of 2 Kbytes. The remainder of the memory is divided into four blocks on binary boundaries. Figure 24-5 shows the program memory organization for 80- and 96-Kbyte devices and the specific code protection bit associated with each block. The actual locations of the bits are summarized in Table 24-3. FIGURE 24-5: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2682/2685/4682/4685 MEMORY SIZE/DEVICE 80 Kbytes (PIC18F2682/4682) 96 Kbytes (PIC18F2685/4685) Address Range Boot Block Boot Block 000000h 0007FFh Block 0 Block 0 Block Code Protection Controlled By: CPB, WRTB, EBTRB 000800h CP0, WRT0, EBTR0 003FFFh 004000h Block 1 Block 1 CP1, WRT1, EBTR1 007FFFh 008000h Block 2 CP2, WRT2, EBTR2 Block 2 00BFFFh 00C000h Block 3 Block 3 CP3, WRT3, EBTR3 00FFFFh 010000h Block 4 Block 4 CP4, WRT4, EBTR4 013FFFh Unimplemented Read `0's 014000h CP5, WRT5, EBTR5 Block 5 017FFFh 018000h Unimplemented Read `0's Unimplemented Read `0's (Unimplemented Memory Space) 1FFFFFh DS39761B-page 358 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 24-3: SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L -- -- CP5(1) CP4 CP3 CP2 CP1 CP0 300009h CONFIG5H CPD CPB -- -- -- -- -- -- WRT4 WRT3 WRT2 WRT1 WRT0 -- -- -- -- -- EBTR4 EBTR3 EBTR2 EBTR1 EBTR0 -- -- -- -- -- 30000Ah CONFIG6L -- -- 30000Bh CONFIG6H WRTD WRTB 30000Ch CONFIG7L -- -- 30000Dh CONFIG7H -- EBTRB WRT5 (1) WRTC EBTR5 -- (1) Legend: Shaded cells are unimplemented. Note 1: Unimplemented in PIC18F2682/4682 devices; maintain this bit set. 24.5.1 PROGRAM MEMORY CODE PROTECTION The program memory may be read to or written from any location using the table read and table write instructions. The Device ID may be read with table reads. The Configuration registers may be read and written with the table read and table write instructions. A table read instruction that executes from a location outside of that block is not allowed to read and will result in reading `0's. Figures 24-6 through 24-8 illustrate table write and table read protection. Note: In normal execution mode, the CPn bits have no direct effect. CPn bits inhibit external reads and writes. A block of user memory may be protected from table writes if the WRTn Configuration bit is `0'. The EBTRn bits control table reads. For a block of user memory with the EBTRn bit set to `0', a table read instruction that executes from within that block is allowed to read. (c) 2007 Microchip Technology Inc. Preliminary Code protection bits may only be written to a `0' from a `1' state. It is not possible to write a `1' to a bit in the `0' state. Code protection bits are only set to `1' by a full Chip Erase or Block Erase function. The full Chip Erase and Block Erase functions can only be initiated via ICSP or an external programmer. DS39761B-page 359 PIC18F2682/2685/4682/4685 FIGURE 24-6: TABLE WRITE (WRTn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0007FFh 000800h WRTB, EBTRB = 11 TBLPTR = 0008FFh WRT0, EBTR0 = 01 PC = 003FFEh TBLWT* 003FFFh 004000h WRT1, EBTR1 = 11 007FFFh 008000h PC = 00BFFEh WRT2, EBTR2 = 11 TBLWT* 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh 010000h WRT4, EBTR3 = 11 013FFFh 014000h WRT5, EBTR3 = 11 017FFFh Results: All table writes disabled to Blockn whenever WRTn = 0. FIGURE 24-7: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0007FFh 000800h WRTB, EBTRB = 11 TBLPTR = 0008FFh WRT0, EBTR0 = 01 003FFFh 004000h PC = 007FFEh TBLRD* WRT1, EBTR1 = 11 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh 010000h WRT4, EBTR3 = 11 013FFFh 014000h WRT5, EBTR3 = 11 017FFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. TABLAT register returns a value of `0'. DS39761B-page 360 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 FIGURE 24-8: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0007FFh 000800h TBLPTR = 0008FFh PC = 003FFEh WRTB, EBTRB = 11 WRT0, EBTR0 = 01 TBLRD* 003FFFh 004000h WRT1, EBTR1 = 11 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh 010000h WRT4, EBTR3 = 11 013FFFh 014000h WRT5, EBTR3 = 11 017FFFh Results: Table reads permitted within Blockn, even when EBTRBn = 0. TABLAT register returns the value of the data at the location TBLPTR. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 361 PIC18F2682/2685/4682/4685 24.5.2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits internal and external writes to data EEPROM. The CPU can continue to read and write data EEPROM regardless of the protection bit settings. 24.5.3 CONFIGURATION REGISTER PROTECTION The Configuration registers can be write-protected. The WRTC bit controls protection of the Configuration registers. In normal execution mode, the WRTC bit is readable only. WRTC can only be written via ICSP or an external programmer. 24.6 ID Locations Eight memory locations (200000h-200007h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are both readable and writable during normal execution through the TBLRD and TBLWT instructions or during program/verify. The ID locations can be read when the device is code-protected. 24.7 To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP/RE3, VDD, VSS, RB7 and RB6. This will interface to the In-Circuit Debugger module available from Microchip or one of the third party development tool companies. 24.9 The LVP Configuration bit enables Single-Supply ICSP programming (formerly known as Low-Voltage ICSP Programming or LVP). When Single-Supply Programming is enabled, the microcontroller can be programmed without requiring high voltage being applied to the MCLR/VPP/RE3 pin, but the RB5/KBI1/PGM pin is then dedicated to controlling Program mode entry and is not available as a general purpose I/O pin. While programming using Single-Supply Programming, VDD is applied to the MCLR/VPP/RE3 pin as in normal execution mode. To enter Programming mode, VDD is applied to the PGM pin. Note 1: High-voltage programming is always available, regardless of the state of the LVP bit, by applying VIHH to the MCLR pin. 2: While in Low-Voltage ICSP Programming mode, the RB5 pin can no longer be used as a general purpose I/O pin and should be held low during normal operation. In-Circuit Serial Programming 3: When using Low-Voltage ICSP Programming (LVP) and the pull-ups on PORTB are enabled, bit 5 in the TRISB register must be cleared to disable the pull-up on RB5 and ensure the proper operation of the device. PIC18F2682/2685/4682/4685 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. 24.8 TABLE 24-4: DEBUGGER RESOURCES I/O pins: RB6, RB7 Stack: 2 levels Note: 4: If the device Master Clear is disabled, verify that either of the following is done to ensure proper entry into ICSP mode: a) disable Low-Voltage Programming (CONFIG4L<2> = 0); or b) make certain that RB5/KBI1/PGM is held low during entry into ICSP. In-Circuit Debugger When the DEBUG Configuration bit is programmed to a `0', the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB(R) IDE. When the microcontroller has this feature enabled, some resources are not available for general use. Table 24-4 shows which resources are required by the background debugger. (R) Memory sources listed in MPLAB IDE. DS39761B-page 362 Single-Supply ICSP Programming If Single-Supply ICSP Programming mode will not be used, the LVP bit can be cleared. RB5/KBI1/PGM then becomes available as the digital I/O pin, RB5. The LVP bit may be set or cleared only when using standard high-voltage programming (VIHH applied to the MCLR/ VPP/RE3 pin). Once LVP has been disabled, only the standard high-voltage programming is available and must be used to program the device. Memory that is not code-protected can be erased using either a block erase, or erased row by row, then written at any specified VDD. If code-protected memory is to be erased, a block erase is required. If a block erase is to be performed when using Low-Voltage Programming, the device must be supplied with VDD of 4.5V to 5.5V. Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 25.0 INSTRUCTION SET SUMMARY PIC18F2682/2685/4682/4685 devices incorporate the standard set of 75 PIC18 core instructions, as well as an extended set of 8 new instructions, for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 25.1 Standard Instruction Set The standard PIC18 instruction set adds many enhancements to the previous PIC(R) MCU instruction sets, while maintaining an easy migration from these PIC MCU instruction sets. Most instructions are a single program memory word (16 bits), but there are four instructions that require two program memory locations. Each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: * * * * Byte-oriented operations Bit-oriented operations Literal operations Control operations The PIC18 instruction set summary in Table 25-2 lists byte-oriented, bit-oriented, literal and control operations. Table 25-1 shows the opcode field descriptions. Most byte-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The destination of the result (specified by `d') The accessed memory (specified by `a') The file register designator `f' specifies which file register is to be used by the instruction. The destination designator `d' specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the WREG register. If `d' is one, the result is placed in the file register specified in the instruction. All bit-oriented instructions have three operands: 1. 2. 3. The literal instructions may use some of the following operands: * A literal value to be loaded into a file register (specified by `k') * The desired FSR register to load the literal value into (specified by `f') * No operand required (specified by `--') The control instructions may use some of the following operands: * A program memory address (specified by `n') * The mode of the CALL or RETURN instructions (specified by `s') * The mode of the table read and table write instructions (specified by `m') * No operand required (specified by `--') All instructions are a single word, except for four double-word instructions. These instructions were made double-word to contain the required information in 32 bits. In the second word, the 4 MSbs are `1's. If this second word is executed as an instruction (by itself), it will execute as a NOP. All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. The double-word instructions execute in two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Two-word branch instructions (if true) would take 3 s. Figure 25-1 shows the general formats that the instructions can have. All examples use the convention `nnh' to represent a hexadecimal number. The Instruction Set Summary, shown in Table 25-2, lists the standard instructions recognized by the Microchip MPASMTM Assembler. Section 25.1.1 "Standard Instruction Set" provides a description of each instruction. The file register (specified by `f') The bit in the file register (specified by `b') The accessed memory (specified by `a') The bit field designator `b' selects the number of the bit affected by the operation, while the file register designator `f' represents the number of the file in which the bit is located. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 363 PIC18F2682/2685/4682/4685 TABLE 25-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. d Destination select bit d = 0: store result in WREG d = 1: store result in file register f dest Destination: either the WREG register or the specified register file location. f 8-bit Register file address (00h to FFh), or 2-bit FSR designator (0h to 3h). fs 12-bit Register file address (000h to FFFh). This is the source address. fd 12-bit Register file address (000h to FFFh). This is the destination address. GIE Global Interrupt Enable bit. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value) label Label name mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) Pre-Increment register (such as TBLPTR with table reads and writes) +* n The relative address (2's complement number) for relative branch instructions or the direct address for Call/Branch and Return instructions PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. PD Power-down bit. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return mode select bit s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) TBLPTR 21-bit Table Pointer (points to a Program Memory location). TABLAT 8-bit Table Latch. TO Time-out bit. TOS Top-of-Stack. u Unused or unchanged. WDT Watchdog Timer. WREG Working register (accumulator). x Don't care (`0' or `1'). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. zs 7-bit offset value for indirect addressing of register files (source). 7-bit offset value for indirect addressing of register files (destination). zd { } Optional argument. [text] Indicates an indexed address. (text) The contents of text. [expr]<n> Specifies bit n of the register indicated by the pointer expr. Assigned to. < > Register bit field. In the set of. italics User defined term (font is Courier). DS39761B-page 364 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 FIGURE 25-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 OPCODE Example Instruction 8 7 d 0 a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE 15 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE #) 1111 f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 0 OPCODE MOVLW 7Fh k (literal) k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 0 OPCODE 15 GOTO Label n<7:0> (literal) 12 11 0 n<19:8> (literal) 1111 n = 20-bit immediate value 15 8 7 OPCODE 15 S 0 CALL MYFUNC n<7:0> (literal) 12 11 0 n<19:8> (literal) 1111 S = Fast bit 15 11 10 OPCODE 15 0 8 7 OPCODE (c) 2007 Microchip Technology Inc. BRA MYFUNC n<10:0> (literal) 0 n<7:0> (literal) Preliminary BC MYFUNC DS39761B-page 365 PIC18F2682/2685/4682/4685 TABLE 25-2: PIC18FXXXX INSTRUCTION SET Mnemonic, Operands 16-Bit Instruction Word Description Cycles MSb LSb Status Bits Affected Notes BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a SUBWF SUBWFB f, d, a f, d, a SWAPF TSTFSZ XORWF f, d, a f, a f, d, a Note 1: 2: 3: 4: 5: Add WREG and f Add WREG and Carry bit to f AND WREG with f Clear f Complement f Compare f with WREG, skip = Compare f with WREG, skip > Compare f with WREG, skip < Decrement f Decrement f, Skip if 0 Decrement f, Skip if Not 0 Increment f Increment f, Skip if 0 Increment f, Skip if Not 0 Inclusive OR WREG with f Move f Move fs (source) to 1st word fd (destination)2nd word Move WREG to f Multiply WREG with f Negate f Rotate Left f through Carry Rotate Left f (No Carry) Rotate Right f through Carry Rotate Right f (No Carry) Set f Subtract f from WREG with borrow Subtract WREG from f Subtract WREG from f with borrow Swap nibbles in f Test f, skip if 0 Exclusive OR WREG with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 C, DC, Z, OV, N C, DC, Z, OV, N Z, N Z Z, N None None None C, DC, Z, OV, N None None C, DC, Z, OV, N None None Z, N Z, N None 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1 1 1 1 1 1 1 1 1 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff 1 1 0101 11da 0101 10da ffff ffff ffff C, DC, Z, OV, N 1, 2 ffff C, DC, Z, OV, N 1 0011 10da 1 (2 or 3) 0110 011a 1 0001 10da ffff ffff ffff ffff None ffff None ffff Z, N None None 1, 2 C, DC, Z, OV, N C, Z, N 1, 2 Z, N C, Z, N Z, N None 1, 2 C, DC, Z, OV, N 4 1, 2 When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, `d' = 1), the prescaler will be cleared if assigned. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. If the table write starts the write cycle to internal memory, the write will continue until terminated. DS39761B-page 366 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 25-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Bits Affected Notes BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG f, b, a f, b, a f, b, a f, b, a f, b, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s None None None None None None None None None None 1 1 1 1 2 1 2 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 2 2 1 0000 1100 0000 0000 0000 0000 kkkk 0001 0000 1, 2 1, 2 3, 4 3, 4 1, 2 CONTROL OPERATIONS BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL n n n n n n n n n n, s CLRWDT DAW GOTO -- -- n NOP NOP POP PUSH RCALL RESET RETFIE -- -- -- -- n s Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Call subroutine1st word 2nd word Clear Watchdog Timer Decimal Adjust WREG Go to address 1st word 2nd word No Operation No Operation Pop top of return stack (TOS) Push top of return stack (TOS) Relative Call Software device Reset Return from interrupt enable RETLW RETURN SLEEP k s -- Return with literal in WREG Return from Subroutine Go into Standby mode Note 1: 2: 3: 4: 5: 1 1 2 TO, PD C None None None None None None All GIE/GIEH, PEIE/GIEL kkkk None 001s None 0011 TO, PD 4 When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, `d' = 1), the prescaler will be cleared if assigned. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. If the table write starts the write cycle to internal memory, the write will continue until terminated. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 367 PIC18F2682/2685/4682/4685 TABLE 25-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Bits Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add literal and WREG AND literal with WREG Inclusive OR literal with WREG Move literal (12-bit) 2nd word to FSR(f) 1st word Move literal to BSR<3:0> Move literal to WREG Multiply literal with WREG Return with literal in WREG Subtract WREG from literal Exclusive OR literal with WREG 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z, OV, N Z, N Z, N None 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111 None None None None None None None None None None None None C, DC, Z, OV, N Z, N DATA MEMORY PROGRAM MEMORY OPERATIONS TBLRD* TBLRD*+ TBLRD*TBLRD+* TBLWT* TBLWT*+ TBLWT*TBLWT+* Note 1: 2: 3: 4: 5: Table Read 2 Table Read with post-increment Table Read with post-decrement Table Read with pre-increment Table Write 2 Table Write with post-increment Table Write with post-decrement Table Write with pre-increment 5 5 5 5 When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, `d' = 1), the prescaler will be cleared if assigned. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. If the table write starts the write cycle to internal memory, the write will continue until terminated. DS39761B-page 368 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 25.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW Syntax: ADDWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) + (f) dest Status Affected: N, OV, C, DC, Z k Operands: 0 k 255 Operation: (W) + k W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal `k' and the result is placed in W. Words: 1 Cycles: 1 Encoding: 0010 Description: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example: ADDLW 01da ffff ffff Add W to register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 15h Before Instruction W = 10h After Instruction W = 25h f {,d {,a}} Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: ADDWF Before Instruction W = REG = After Instruction W = REG = Note: REG, 0, 0 17h 0C2h 0D9h 0C2h All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 369 PIC18F2682/2685/4682/4685 ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC Syntax: ANDLW Operands: 0 f 255 d [0,1] a [0,1] f {,d {,a}} (W) + (f) + (C) dest Operation: Status Affected: Encoding: 0010 Description: 00da Operands: 0 k 255 Operation: (W) .AND. k W Status Affected: N, Z Encoding: N,OV, C, DC, Z ffff ffff Add W, the Carry flag and data memory location `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in data memory location `f'. Words: 1 Cycles: 1 0000 1011 kkkk kkkk Description: The contents of W are ANDed with the 8-bit literal `k'. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. k Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example: ANDLW Before Instruction W = After Instruction W = 05Fh A3h 03h Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: ADDWFC Before Instruction Carry bit = REG = W = After Instruction Carry bit = REG = W = DS39761B-page 370 REG, 0, 1 1 02h 4Dh 0 02h 50h Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 ANDWF AND W with f BC Branch if Carry Syntax: ANDWF Syntax: BC Operands: 0 f 255 d [0,1] a [0,1] Operands: -128 n 127 Operation: if Carry bit is `1' (PC) + 2 + 2n PC None f {,d {,a}} Operation: (W) .AND. (f) dest Status Affected: Status Affected: N, Z Encoding: Encoding: 0001 Description: 01da ffff ffff 1110 Description: The contents of W are ANDed with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). Words: 1 Cycles: 1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Before Instruction W = REG = After Instruction W = REG = REG, 0, 0 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation Example: HERE Before Instruction PC After Instruction If Carry PC If Carry PC 17h C2h 02h C2h (c) 2007 Microchip Technology Inc. nnnn If No Jump: Q1 ANDWF nnnn If the Carry bit is `1', then the program will branch. Words: Q Cycle Activity: Example: 0010 The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. n Preliminary BC 5 = address (HERE) = = = = 1; address (HERE + 12) 0; address (HERE + 2) DS39761B-page 371 PIC18F2682/2685/4682/4685 BCF Bit Clear f BN Branch if Negative Syntax: BCF Syntax: BN Operands: 0 f 255 0b7 a [0,1] Operands: -128 n 127 Operation: if Negative bit is `1' (PC) + 2 + 2n PC None f, b {,a} Operation: 0 f<b> Status Affected: Status Affected: None Encoding: Encoding: 1001 Description: bbba ffff ffff 1110 Description: Bit `b' in register `f' is cleared. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 nnnn nnnn If the Negative bit is `1', then the program will branch. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' BCF Before Instruction FLAG_REG = C7h After Instruction FLAG_REG = 47h DS39761B-page 372 0110 The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Q Cycle Activity: Example: n FLAG_REG, Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation If No Jump: 7, 0 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation Example: HERE Before Instruction PC After Instruction If Negative PC If Negative PC Preliminary BN Jump = address (HERE) = = = = 1; address (Jump) 0; address (HERE + 2) (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC Syntax: BNN n n Operands: -128 n 127 Operands: -128 n 127 Operation: if Carry bit is `0' (PC) + 2 + 2n PC Operation: if Negative bit is `0' (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0011 nnnn nnnn If the Carry bit is `0', then the program will branch. Encoding: 1110 Description: The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. nnnn nnnn The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: 0111 If the Negative bit is `0', then the program will branch. Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation No operation No operation No operation No operation Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation Decode Read literal `n' Process Data No operation If No Jump: Example: If No Jump: HERE Before Instruction PC After Instruction If Carry PC If Carry PC BNC Jump = address (HERE) = = = = 0; address (Jump) 1; address (HERE + 2) (c) 2007 Microchip Technology Inc. Example: HERE Before Instruction PC After Instruction If Negative PC If Negative PC Preliminary BNN Jump = address (HERE) = = = = 0; address (Jump) 1; address (HERE + 2) DS39761B-page 373 PIC18F2682/2685/4682/4685 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV Syntax: BNZ n n Operands: -128 n 127 Operands: -128 n 127 Operation: if Overflow bit is `0' (PC) + 2 + 2n PC Operation: if Zero bit is `0' (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0101 nnnn nnnn If the Overflow bit is `0', then the program will branch. Encoding: 1110 Description: The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. nnnn nnnn The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: 0001 If the Zero bit is `0', then the program will branch. Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation No operation No operation No operation No operation Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation Decode Read literal `n' Process Data No operation If No Jump: If No Jump: Example: HERE Before Instruction PC After Instruction If Overflow PC If Overflow PC DS39761B-page 374 BNOV Jump = address (HERE) = = = = 0; address (Jump) 1; address (HERE + 2) Example: HERE Before Instruction PC After Instruction If Zero PC If Zero PC Preliminary BNZ Jump = address (HERE) = = = = 0; address (Jump) 1; address (HERE + 2) (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 BRA Unconditional Branch BSF Bit Set f Syntax: BRA Syntax: BSF Operands: 0 f 255 0b7 a [0,1] Operation: 1 f<b> Status Affected: None n Operands: -1024 n 1023 Operation: (PC) + 2 + 2n PC Status Affected: None Encoding: 1101 Description: 0nnn nnnn nnnn Add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. Words: 1 Cycles: 2 Encoding: 1000 Description: Q1 Q2 Q3 Q4 Read literal `n' Process Data Write to PC No operation No operation No operation No operation bbba ffff ffff Bit `b' in register `f' is set. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Q Cycle Activity: Decode f, b {,a} Words: 1 Cycles: 1 Q Cycle Activity: Example: HERE Before Instruction PC After Instruction PC BRA Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Jump = address (HERE) = address (Jump) Example: BSF Before Instruction FLAG_REG After Instruction FLAG_REG (c) 2007 Microchip Technology Inc. Preliminary FLAG_REG, 7, 1 = 0Ah = 8Ah DS39761B-page 375 PIC18F2682/2685/4682/4685 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 f 255 0b7 a [0,1] Operands: 0 f 255 0b<7 a [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 Description: bbba ffff ffff If bit `b' in register `f' is `0', then the next instruction is skipped. If bit `b' is `0', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. Encoding: 1010 Description: bbba ffff ffff If bit `b' in register `f' is `1', then the next instruction is skipped. If bit `b' is `1', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data No operation Decode Read register `f' Process Data No operation Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation If skip: If skip: If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE FALSE TRUE Before Instruction PC After Instruction If FLAG<1> PC If FLAG<1> PC DS39761B-page 376 BTFSC : : FLAG, 1, 0 = address (HERE) = = = = 0; address (TRUE) 1; address (FALSE) Example: HERE FALSE TRUE Before Instruction PC After Instruction If FLAG<1> PC If FLAG<1> PC Preliminary BTFSS : : FLAG, 1, 0 = address (HERE) = = = = 0; address (FALSE) 1; address (TRUE) (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV Operands: 0 f 255 0b<7 a [0,1] Operands: -128 n 127 Operation: if Overflow bit is `1' (PC) + 2 + 2n PC Status Affected: None Operation: (f<b>) f<b> Status Affected: None Encoding: 0111 Description: Encoding: bbba ffff ffff 1110 Description: Bit `b' in data memory location `f' is inverted. 0100 nnnn nnnn If the Overflow bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. n Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: BTG PORTC, Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation 4, 0 Before Instruction: PORTC = 0111 0101 [75h] After Instruction: PORTC = 0110 0101 [65h] (c) 2007 Microchip Technology Inc. If No Jump: Example: HERE Before Instruction PC After Instruction If Overflow PC If Overflow PC Preliminary BOV Jump = address (HERE) = = = = 1; address (Jump) 0; address (HERE + 2) DS39761B-page 377 PIC18F2682/2685/4682/4685 BZ Branch if Zero CALL Subroutine Call Syntax: BZ Syntax: CALL k {,s} n Operands: -128 n 127 Operands: Operation: if Zero bit is `1' (PC) + 2 + 2n PC 0 k 1048575 s [0,1] Operation: Status Affected: None (PC) + 4 TOS, k PC<20:1>; if s = 1, (W) WS, (STATUS) STATUSS, (BSR) BSRS Status Affected: None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Encoding: 1st word (k<7:0>) Q2 Q3 Q4 Read literal `n' Process Data Write to PC No operation No operation No operation No operation If No Jump: Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation Example: HERE Before Instruction PC After Instruction If Zero PC If Zero PC DS39761B-page 378 BZ Q1 Q2 Q3 Q4 Decode Read literal `k'<7:0>, Push PC to stack Read literal `k'<19:8>, Write to PC No operation No operation No operation No operation Jump = address (HERE) = = = = 1; address (Jump) 0; address (HERE + 2) kkkk0 kkkk8 Subroutine call of entire 2-Mbyte memory range. First, return address (PC + 4) is pushed onto the return stack. If `s' = 1, the W, STATUS and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If `s' = 0, no update occurs (default). Then, the 20-bit value `k' is loaded into PC<20:1>. CALL is a two-cycle instruction. If Jump: Q1 k7kkk kkkk 110s k19kkk Description: Q Cycle Activity: Decode 1110 1111 2nd word(k<19:8>) Example: HERE Before Instruction PC = After Instruction PC = TOS = WS = BSRS = STATUSS= Preliminary CALL THERE, 1 address (HERE) address (THERE) address (HERE + 4) W BSR STATUS (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 CLRF Clear f Syntax: CLRF Operands: 0 f 255 a [0,1] f {,a} Operation: 000h f 1Z Status Affected: Z Encoding: 0110 Description: 101a ffff ffff Clears the contents of the specified register. CLRWDT Clear Watchdog Timer Syntax: CLRWDT Operands: None Operation: 000h WDT, 000h WDT postscaler, 1 TO, 1 PD Status Affected: TO, PD Encoding: 0000 Words: 1 Cycles: 1 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: CLRF Before Instruction FLAG_REG After Instruction FLAG_REG FLAG_REG,1 = 5Ah = 00h (c) 2007 Microchip Technology Inc. 0100 Words: Q1 Q2 Q3 Q4 Decode No operation Process Data No operation Example: Q1 0000 CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits TO and PD are set. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 0000 Description: Preliminary CLRWDT Before Instruction WDT Counter After Instruction WDT Counter WDT Postscaler TO PD = ? = = = = 00h 0 1 1 DS39761B-page 379 PIC18F2682/2685/4682/4685 COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF Syntax: CPFSEQ Operands: 0 f 255 a [0,1] Operation: (f) - (W), skip if (f) = (W) (unsigned comparison) Status Affected: None f {,d {,a}} 0 f 255 d [0,1] a [0,1] Operands: Operation: (f) dest Status Affected: N, Z Encoding: 0001 Description: 11da ffff ffff The contents of register `f' are complemented. If `d' is `1', the result is stored in W. If `d' is `0', the result is stored back in register `f' (default). Encoding: Description: If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: COMF Before Instruction REG = After Instruction REG = W = REG, 0, 0 ffff If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Decode Q2 Read register `f' Q3 Process Data Q4 No operation If skip: Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: HERE NEQUAL EQUAL Before Instruction PC Address W REG After Instruction If REG PC If REG PC DS39761B-page 380 ffff If `a' is `0', the Access Bank is selected. If `a' is `0', the BSR is used to select the GPR bank (default). 13h 13h ECh 001a Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If `f' = W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). Words: 0110 f {,a} Preliminary Q4 No operation Q4 No operation No operation CPFSEQ REG, 0 : : = = = HERE ? ? = = = W; Address (EQUAL) W; Address (NEQUAL) (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT Syntax: CPFSLT Operands: 0 f 255 a [0,1] Operands: Operation: (f) - (W), skip if (f) > (W) (unsigned comparison) 0 f 255 a [0,1] Operation: (f) - (W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: Description: 0110 f {,a} 010a ffff ffff Compares the contents of data memory location `f' to the contents of the W by performing an unsigned subtraction. Encoding: 0110 Description: If the contents of `f' are greater than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. Words: 3 cycles if skip and followed by a 2-word instruction. 1 Cycles: 1(2) Note: Q2 Read register `f' Q3 Process Data Q4 No operation Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Q4 No operation Q1 Q2 Q3 Q4 Decode Read register `f' Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation If skip: Example: HERE NGREATER GREATER Before Instruction PC W After Instruction If REG PC If REG PC Q4 No operation No operation Address (HERE) ? > = = W; Address (GREATER) W; Address (NGREATER) (c) 2007 Microchip Technology Inc. Example: CPFSGT REG, 0 : : = = 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Decode ffff Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. Words: 1(2) Note: ffff If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). 1 Cycles: 000a If the contents of `f' are less than the contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. f {,a} Preliminary HERE NLESS LESS Before Instruction PC W After Instruction If REG PC If REG PC CPFSLT REG, 1 : : = = Address (HERE) ? < = = W; Address (LESS) W; Address (NLESS) DS39761B-page 381 PIC18F2682/2685/4682/4685 DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: Operation: If [W<3:0> >9] or [DC = 1] then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0> 0 f 255 d [0,1] a [0,1] Operation: (f) - 1 dest Status Affected: C, DC, N, OV, Z Encoding: If [W<7:4> >9] or [C = 1] then (W<7:4>) + 6 W<7:4>; C = 1; else (W<7:4>) W<7:4> Status Affected: 0000 Description: C Encoding: 0000 0000 0000 DAW adjusts the eight-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register W Process Data Write W Before Instruction W = C = DC = After Instruction W = C = DC = DS39761B-page 382 Decrement register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination DAW A5h 0 0 ffff If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Example 1: Before Instruction W = C = DC = After Instruction W = C = DC = Example 2: ffff If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). 0111 Description: 01da Example: DECF Before Instruction CNT = Z = After Instruction CNT = Z = 05h 1 0 CNT, 1, 0 01h 0 00h 1 CEh 0 0 34h 1 0 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if Not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) - 1 dest, skip if result = 0 Operation: (f) - 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0010 Description: 11da ffff ffff The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). Encoding: 0100 Description: If the result is `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Words: 1 Cycles: 1(2) Note: Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination If skip: If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation DECFSZ GOTO CNT, 1, 1 LOOP Q2 Q3 Q4 No operation No operation No operation Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: CONTINUE HERE ZERO NZERO Before Instruction TEMP After Instruction TEMP If TEMP PC If TEMP PC Address (HERE) CNT - 1 0; Address (CONTINUE) 0; Address (HERE + 2) (c) 2007 Microchip Technology Inc. Q1 No operation If skip and followed by 2-word instruction: Q1 Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT PC = 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 HERE ffff If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Q Cycle Activity: Example: ffff If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Cycles: 11da The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is not `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). Words: f {,d {,a}} Preliminary DCFSNZ : : TEMP, 1, 0 = ? = = = = TEMP - 1, 0; Address (ZERO) 0; Address (NZERO) DS39761B-page 383 PIC18F2682/2685/4682/4685 GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF Operands: 0 k 1048575 Operands: Operation: k PC<20:1> Status Affected: None 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 1110 1111 2nd word(k<19:8>) Description: 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range. The 20-bit value `k' is loaded into PC<20:1>. GOTO is always a two-cycle instruction. Words: 2 Cycles: 2 Encoding: 0010 Description: Q1 Q2 Q3 Q4 Read literal `k'<7:0>, No operation Read literal `k'<19:8>, Write to PC No operation No operation No operation No operation Example: GOTO THERE ffff ffff The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q Cycle Activity: After Instruction PC = Address (THERE) Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: INCF Before Instruction CNT = Z = C = DC = After Instruction CNT = Z = C = DC = DS39761B-page 384 10da If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). Q Cycle Activity: Decode f {,d {,a}} Preliminary CNT, 1, 0 FFh 0 ? ? 00h 1 1 1 (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 INCFSZ Increment f, Skip if 0 INFSNZ Syntax: INCFSZ Syntax: INFSNZ 0 f 255 d [0,1] a [0,1] f {,d {,a}} Increment f, Skip if Not 0 f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: Operation: (f) + 1 dest, skip if result = 0 Operation: (f) + 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0011 Description: 11da ffff ffff The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). Encoding: 0100 Description: 10da ffff ffff The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If the result is not `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1(2) Note: Words: 1 Cycles: 1(2) 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Decode Read register `f' Process Data Write to destination Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation If skip: If skip: If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE NZERO ZERO Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT PC = INCFSZ : : CNT, 1, 0 Example: Before Instruction PC = After Instruction REG = If REG PC = If REG = PC = Address (HERE) CNT + 1 0; Address (ZERO) 0; Address (NZERO) (c) 2007 Microchip Technology Inc. HERE ZERO NZERO Preliminary INFSNZ REG, 1, 0 Address (HERE) REG + 1 0; Address (NZERO) 0; Address (ZERO) DS39761B-page 385 PIC18F2682/2685/4682/4685 IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF Operands: 0 k 255 Operands: Operation: (W) .OR. k W Status Affected: N, Z 0 f 255 d [0,1] a [0,1] Operation: (W) .OR. (f) dest Status Affected: N, Z Encoding: 0000 1001 kkkk kkkk Description: The contents of W are ORed with the eight-bit literal `k'. The result is placed in W. Words: 1 Cycles: 1 Encoding: 0001 Description: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example: IORLW Before Instruction W = After Instruction W = 00da ffff ffff Inclusive OR W with register `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 35h 9Ah BFh f {,d {,a}} Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: IORWF Before Instruction RESULT = W = After Instruction RESULT = W = DS39761B-page 386 Preliminary RESULT, 0, 1 13h 91h 13h 93h (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF Operands: 0f2 0 k 4095 Operands: Operation: k FSRf 0 f 255 d [0,1] a [0,1] Status Affected: None Operation: f dest Status Affected: N, Z Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal `k' is loaded into the file select register pointed to by `f'. Words: 2 Cycles: 2 Encoding: 0101 Description: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' MSB Process Data Write literal `k' MSB to FSRfH Decode Read literal `k' LSB Example: After Instruction FSR2H FSR2L Process Data 03h ABh 00da ffff ffff The contents of register `f' are moved to a destination dependent upon the status of `d'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Write literal `k' to FSRfL LFSR 2, 3ABh = = f {,d {,a}} Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write W Example: MOVF Before Instruction REG W After Instruction REG W (c) 2007 Microchip Technology Inc. Preliminary REG, 0, 0 = = 22h FFh = = 22h 22h DS39761B-page 387 PIC18F2682/2685/4682/4685 MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF fs,fd Syntax: MOVLW k Operands: 0 fs 4095 0 fd 4095 Operands: 0 k 255 Operation: k BSR None Operation: (fs) fd Status Affected: Status Affected: None Encoding: Encoding: 1st word (source) 1100 1111 2nd word (destin.) Description: ffff ffff ffff ffff 2 2 (3) kkkk Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write literal `k' to BSR MOVLB 5 Example: The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. Cycles: kkkk The eight-bit literal `k' is loaded into the Bank Select Register (BSR). The value of BSR<7:4> always remains `0', regardless of the value of k7:k4. Either source or destination can be W (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). 0001 Description: ffffs ffffd The contents of source register `fs' are moved to destination register `fd'. Location of source `fs' can be anywhere in the 4096-byte data space (000h to FFFh) and location of destination `fd' can also be anywhere from 000h to FFFh. Words: 0000 Before Instruction BSR Register = After Instruction BSR Register = 02h 05h Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' (src) Process Data No operation Decode No operation No operation Write register `f' (dest) No dummy read Example: MOVFF Before Instruction REG1 REG2 After Instruction REG1 REG2 DS39761B-page 388 REG1, REG2 = = 33h 11h = = 33h 33h Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF Operands: 0 k 255 Operands: Operation: kW 0 f 255 a [0,1] Status Affected: None Encoding: 0000 Description: 1110 kkkk kkkk The eight-bit literal `k' is loaded into W. Words: 1 Cycles: 1 Operation: (W) f Status Affected: None Encoding: 0110 Description: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example: After Instruction W = MOVLW f {,a} 111a ffff ffff Move data from W to register `f'. Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 5Ah 5Ah Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: MOVWF Before Instruction W = REG = After Instruction W = REG = (c) 2007 Microchip Technology Inc. Preliminary REG, 0 4Fh FFh 4Fh 4Fh DS39761B-page 389 PIC18F2682/2685/4682/4685 MULLW Multiply Literal with W MULWF Multiply W with f Syntax: MULLW Syntax: MULWF Operands: 0 f 255 a [0,1] Operation: (W) x (f) PRODH:PRODL Status Affected: None k Operands: 0 k 255 Operation: (W) x k PRODH:PRODL Status Affected: None Encoding: 0000 Description: 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal `k'. The 16-bit result is placed in the PRODH:PRODL register pair. PRODH contains the high byte. Encoding: 0000 Description: None of the Status flags are affected. Note that neither Overflow nor Carry is possible in this operation. A Zero result is possible but not detected. 1 Cycles: 1 Q1 Q2 Q3 Q4 Read literal `k' Process Data Write registers PRODH: PRODL Before Instruction W PRODH PRODL After Instruction W PRODH PRODL = = = Note that neither Overflow nor Carry is possible in this operation. A Zero result is possible but not detected. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 0C4h E2h ? ? Words: 1 Cycles: 1 Q Cycle Activity: = = = E2h ADh 08h Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write registers PRODH: PRODL Example: Before Instruction W REG PRODH PRODL After Instruction W REG PRODH PRODL DS39761B-page 390 ffff If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). Decode MULLW ffff None of the Status flags are affected. Q Cycle Activity: Example: 001a An unsigned multiplication is carried out between the contents of W and the register file location `f'. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and `f' are unchanged. W is unchanged. Words: f {,a} Preliminary MULWF REG, 1 = = = = C4h B5h ? ? = = = = C4h B5h 8Ah 94h (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 NEGF Negate f NOP No Operation Syntax: NEGF Syntax: NOP Operands: 0 f 255 a [0,1] f {,a} Operands: None Operation: No operation None Operation: (f)+1f Status Affected: Status Affected: N, OV, C, DC, Z Encoding: Encoding: 0110 Description: 110a ffff Location `f' is negated using two's complement. The result is placed in the data memory location `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 0000 1111 ffff 0000 xxxx Description: No operation. Words: 1 Cycles: 1 0000 xxxx 0000 xxxx Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation Example: None. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: NEGF Before Instruction REG = After Instruction REG = REG, 1 0011 1010 [3Ah] 1100 0110 [C6h] (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 391 PIC18F2682/2685/4682/4685 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) bit bucket Operation: (PC + 2) TOS Status Affected: None Status Affected: None Encoding: 0000 Description: 0000 0000 0110 The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. Words: 1 Cycles: 1 Encoding: Description: Q2 Q3 Q4 Decode No operation POP TOS value No operation POP GOTO NEW Before Instruction TOS Stack (1 level down) DS39761B-page 392 0000 0101 The PC + 2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. Words: 1 Cycles: 1 Q Cycle Activity: Q1 After Instruction TOS PC 0000 This instruction allows implementing a software stack by modifying TOS and then pushing it onto the return stack. Q Cycle Activity: Example: 0000 Q1 Q2 Q3 Q4 Decode PUSH PC + 2 onto return stack No operation No operation Example: = = = = 0031A2h 014332h 014332h NEW Preliminary PUSH Before Instruction TOS PC = = 345Ah 0124h After Instruction PC TOS Stack (1 level down) = = = 0126h 0126h 345Ah (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 RCALL Relative Call RESET Reset Syntax: RCALL Syntax: RESET n Operands: -1024 n 1023 Operands: None Operation: (PC) + 2 TOS, (PC) + 2 + 2n PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 Description: 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack. Then, add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. Words: 1 Cycles: 2 Encoding: Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation Push PC to stack Example: No operation HERE 1111 1111 Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Start Reset No operation No operation Example: Q1 0000 This instruction provides a way to execute a MCLR Reset in software. Q Cycle Activity: No operation 0000 Description: After Instruction Registers = Flags* = RESET Reset Value Reset Value RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS = Address (HERE + 2) (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 393 PIC18F2682/2685/4682/4685 RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s [0,1] Operands: 0 k 255 Operation: (TOS) PC, 1 GIE/GIEH or PEIE/GIEL; if s = 1, (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged Operation: k W, (TOS) PC, PCLATU, PCLATH are unchanged Status Affected: None Status Affected: Encoding: 0000 Description: 0000 0001 Words: 1 Cycles: 2 Q Cycle Activity: kkkk kkkk W is loaded with the eight-bit literal `k'. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. Words: 1 Cycles: 2 000s Return from interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low priority global interrupt enable bit. If `s' = 1, the contents of the shadow registers, WS, STATUSS and BSRS, are loaded into their corresponding registers, W, STATUS and BSR. If `s' = 0, no update of these registers occurs (default). 1100 Description: GIE/GIEH, PEIE/GIEL. Encoding: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data POP PC from stack, Write to W No operation No operation No operation No operation Example: Q1 Q2 Q3 Q4 Decode No operation No operation POP PC from stack Set GIEH or GIEL No operation 0000 No operation Example: RETFIE After Interrupt PC W BSR STATUS GIE/GIEH, PEIE/GIEL DS39761B-page 394 No operation No operation 1 = = = = = TOS WS BSRS STATUSS 1 CALL TABLE; W contains table ; offset value ; W now has ; table value : TABLE ADDWF PCL; W = offset RETLW k0; Begin table RETLW k1; : : RETLW kn; End of table Before Instruction W = After Instruction W = Preliminary 07h value of kn (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF Operands: s [0,1] Operands: Operation: (TOS) PC; if s = 1, (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged 0 f 255 d [0,1] a [0,1] Operation: (f<n>) dest<n + 1>, (f<7>) C, (C) dest<0> Status Affected: C, N, Z Status Affected: None Encoding: 0000 Description: Encoding: 0000 0001 001s 0011 Description: Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If `s'= 1, the contents of the shadow registers, WS, STATUSS and BSRS, are loaded into their corresponding registers, W, STATUS and BSR. If `s' = 0, no update of these registers occurs (default). Words: 1 Cycles: 2 Q1 Q2 Q3 Q4 No operation Process Data POP PC from stack No operation No operation No operation No operation Example: RETURN ffff ffff The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. register f C Words: 1 Cycles: 1 Q Cycle Activity: After Interrupt PC = TOS Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: Before Instruction REG = C = After Instruction REG = W = C = (c) 2007 Microchip Technology Inc. 01da If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). Q Cycle Activity: Decode f {,d {,a}} Preliminary RLCF REG, 0, 0 1110 0110 0 1110 0110 1100 1100 1 DS39761B-page 395 PIC18F2682/2685/4682/4685 RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: RLNCF Syntax: RRCF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f<n>) dest<n + 1>, (f<7>) dest<0> Operation: Status Affected: N, Z (f<n>) dest<n - 1>, (f<0>) C, (C) dest<7> Status Affected: C, N, Z Encoding: 0100 Description: f {,d {,a}} 01da ffff ffff The contents of register `f' are rotated one bit to the left. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f' (default). Encoding: 0011 Description: If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). Cycles: 1 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: Before Instruction REG = After Instruction REG = DS39761B-page 396 RLNCF Words: 1 Cycles: 1 register f Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination REG, 1, 0 1010 1011 ffff The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). C Q Cycle Activity: ffff If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. register f 1 00da If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: f {,d {,a}} Example: RRCF Before Instruction REG = C = After Instruction REG = W = C = 0101 0111 Preliminary REG, 0, 0 1110 0110 0 1110 0110 0111 0011 0 (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 RRNCF Rotate Right f (No Carry) SETF Syntax: RRNCF Syntax: SETF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 a [0,1] Operation: (f<n>) dest<n - 1>, (f<0>) dest<7> FFh f Operation: Status Affected: None Status Affected: Encoding: N, Z Encoding: 0100 Description: f {,d {,a}} 00da Set f ffff ffff 0110 Description: The contents of register `f' are rotated one bit to the right. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). 1 Cycles: 1 1 Cycles: 1 Q Cycle Activity: Q2 Q3 Q4 Read register `f' Process Data Write to destination Example 1: RRNCF Before Instruction REG = After Instruction REG = Example 2: Q2 Q3 Q4 Read register `f' Process Data Write register `f' SETF Before Instruction REG After Instruction REG REG,1 = 5Ah = FFh REG, 1, 0 1101 0111 1110 1011 RRNCF Before Instruction W = REG = After Instruction W = REG = Q1 Decode Example: Q1 ffff The contents of the specified register are set to FFh. Words: Q Cycle Activity: Decode ffff If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. register f Words: 100a If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. f {,a} REG, 0, 0 ? 1101 0111 1110 1011 1101 0111 (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 397 PIC18F2682/2685/4682/4685 SLEEP Enter Sleep mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB Operands: None Operands: Operation: 00h WDT, 0 WDT postscaler, 1 TO, 0 PD 0 f 255 d [0,1] a [0,1] Operation: (W) - (f) - (C) dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Encoding: 0000 0000 0011 0101 Description: The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set. Watchdog Timer and its postscaler are cleared. Description: 1 Cycles: 1 Q1 Q2 Q3 Q4 No operation Process Data Go to Sleep Example: SLEEP Before Instruction TO = ? ? PD = After Instruction 1 TO = PD = 0 If WDT causes wake-up, this bit is cleared. DS39761B-page 398 ffff ffff Subtract register `f' and Carry flag (borrow) from W (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored in register `f' (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Q Cycle Activity: Decode 01da If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). The processor is put into Sleep mode with the oscillator stopped. Words: f {,d {,a}} Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination SUBFWB REG, 1, 0 Example 1: Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive SUBFWB REG, 1, 0 Example 3: Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF Operands: 0 k 255 Operands: Operation: k - (W) W Status Affected: N, OV, C, DC, Z 0 f 255 d [0,1] a [0,1] Operation: (f) - (W) dest Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk Description: W is subtracted from the eight-bit literal `k'. The result is placed in W. Encoding: Words: 1 Description: Cycles: 1 0101 Q1 Q2 Q3 Q4 Read literal `k' Process Data Write to W Example 1: Before Instruction W = C = After Instruction W = C = Z = N = Example 2: Before Instruction W = C = After Instruction W = C = Z = N = Example 3: Before Instruction W = C = After Instruction W = C = Z = N = SUBLW 02h ffff If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 01h ? SUBLW ffff If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). 02h 01h 1 ; result is positive 0 0 11da Subtract W from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). Q Cycle Activity: Decode f {,d {,a}} Words: 1 Cycles: 1 Q Cycle Activity: 02h ? 00h 1 ; result is zero 1 0 SUBLW Q2 Q3 Q4 Read register `f' Process Data Write to destination SUBWF REG, 1, 0 Example 1: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = 02h 03h ? FFh ; (2's complement) 0 ; result is negative 0 1 Q1 Decode Example 2: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 3: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = (c) 2007 Microchip Technology Inc. Preliminary 3 2 ? 1 2 1 0 0 ; result is positive SUBWF REG, 0, 0 2 2 ? 2 0 1 1 0 SUBWF ; result is zero REG, 1, 0 1 2 ? FFh ; (2's complement) 2 0 ; result is negative 0 1 DS39761B-page 399 PIC18F2682/2685/4682/4685 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB Syntax: SWAPF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) - (W) - (C) dest Operation: (f<3:0>) dest<7:4>, Status Affected: N, OV, C, DC, Z Encoding: 0101 Description: f {,d {,a}} 10da (f<7:4>) dest<3:0> ffff ffff Subtract W and the Carry flag (borrow) from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). Status Affected: 0011 Description: If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Read register `f' Example 1: SUBWFB Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 2: Q4 Write to destination (0001 1001) (0000 1101) 0Ch 0Dh 1 0 0 (0000 1011) (0000 1101) ffff The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in register `f' (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination REG, 1, 0 19h 0Dh 1 ffff Example: SWAPF Before Instruction REG = After Instruction REG = REG, 1, 0 53h 35h ; result is positive SUBWFB REG, 0, 0 Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 3: 1Bh 1Ah 0 (0001 1011) (0001 1010) 1Bh 00h 1 1 0 (0001 1011) SUBWFB Before Instruction REG = W = C = After Instruction REG = W C Z N Q3 Process Data 10da If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: None Encoding: = = = = DS39761B-page 400 ; result is zero REG, 1, 0 03h 0Eh 1 (0000 0011) (0000 1101) F5h (1111 0100) ; [2's comp] (0000 1101) 0Eh 0 0 1 ; result is negative Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) TABLAT, TBLPTR - No Change; if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT, (TBLPTR) + 1 TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT, (TBLPTR) - 1 TBLPTR; if TBLRD +*, (TBLPTR) + 1 TBLPTR, (Prog Mem (TBLPTR)) TABLAT Before Instruction TABLAT TBLPTR MEMORY(00A356h) After Instruction TABLAT TBLPTR Example 2: Status Affected: None Encoding: Description: 0000 0000 0000 TBLRD Before Instruction TABLAT TBLPTR MEMORY(01A357h) MEMORY(01A358h) After Instruction TABLAT TBLPTR *+ ; = = = 55h 00A356h 34h = = 34h 00A357h +* ; = = = = 0AAh 01A357h 12h 34h = = 34h 01A358h 10nn nn=0 * =1 *+ =2 *=3 +* This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer, called Table Pointer (TBLPTR), is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: * * * * Words: 1 Cycles: 2 no change post-increment post-decrement pre-increment Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation No operation No operation (Write TABLAT) No No operation operation (Read Program Memory) (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 401 PIC18F2682/2685/4682/4685 TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Operation: if TBLWT*, (TABLAT) Holding Register, TBLPTR - No Change; if TBLWT*+, (TABLAT) Holding Register, (TBLPTR) + 1 TBLPTR; if TBLWT*-, (TABLAT) Holding Register, (TBLPTR) - 1 TBLPTR; if TBLWT+*, (TBLPTR) + 1 TBLPTR, (TABLAT) Holding Register Before Instruction TABLAT = 55h TBLPTR = 00A356h HOLDING REGISTER (00A356h) = FFh After Instructions (table write completion) TABLAT = 55h TBLPTR = 00A357h HOLDING REGISTER (00A356h) = 55h Example 2: Status Affected: None Encoding: Description: 0000 0000 0000 11nn nn=0 * =1 *+ =2 *=3 +* This instruction uses the 3 LSBs of the TBLPTR to determine which of the 8 holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section 6.0 "Flash Program Memory" for additional details on programming Flash memory.) TBLWT +*; Before Instruction TABLAT = 34h TBLPTR = 01389Ah HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = FFh After Instruction (table write completion) TABLAT = 34h TBLPTR = 01389Bh HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = 34h The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-MBtye address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: * * * * Words: 1 Cycles: 2 no change post-increment post-decrement pre-increment Q Cycle Activity: Q1 Decode Q2 Q3 Q4 No No No operation operation operation No No No No operation operation operation operation (Read (Write to TABLAT) Holding Register ) DS39761B-page 402 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 f 255 a [0,1] Operands: 0 k 255 Operation: (W) .XOR. k W Status Affected: N, Z Operation: skip if f = 0 Status Affected: None Encoding: Encoding: 0110 Description: 011a ffff ffff If `f' = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1(2) 0000 1010 kkkk kkkk Description: The contents of W are XORed with the 8-bit literal `k'. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example: Before Instruction W = After Instruction W = XORLW 0AFh B5h 1Ah Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE NZERO ZERO Before Instruction PC After Instruction If CNT PC If CNT PC TSTFSZ : : CNT, 1 = Address (HERE) = = = 00h, Address (ZERO) 00h, Address (NZERO) (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 403 PIC18F2682/2685/4682/4685 XORWF Exclusive OR W with f Syntax: XORWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 Description: f {,d {,a}} 10da ffff ffff Exclusive OR the contents of W with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in the register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: XORWF Before Instruction REG = W = After Instruction REG = W = DS39761B-page 404 REG, 1, 0 AFh B5h 1Ah B5h Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 25.2 Extended Instruction Set A summary of the instructions in the extended instruction set is provided in Table 25-3. Detailed descriptions are provided in Section 25.2.2 "Extended Instruction Set". The opcode field descriptions in Table 25-1 apply to both the standard and extended PIC18 instruction sets. In addition to the standard 75 instructions of the PIC18 instruction set, PIC18F2682/2685/4682/4685 devices also provide an optional extension to the core CPU functionality. The added features include eight additional instructions that augment indirect and indexed addressing operations and the implementation of Indexed Literal Offset Addressing mode for many of the standard PIC18 instructions. Note: The additional features are disabled by default. To enable them, users must set the XINST Configuration bit. The instructions in the extended set can all be classified as literal operations, which either manipulate the File Select Registers or use them for indexed addressing. Two of the instructions, ADDFSR and SUBFSR, each have an additional special instantiation for using FSR2. These versions (ADDULNK and SUBULNK) allow for automatic return after execution. 25.2.1 EXTENDED INSTRUCTION SYNTAX Most of the extended instructions use indexed arguments, using one of the File Select Registers and some offset to specify a source or destination register. When an argument for an instruction serves as part of indexed addressing, it is enclosed in square brackets ("[ ]"). This is done to indicate that the argument is used as an index or offset. MPASMTM Assembler will flag an error if it determines that an index or offset value is not bracketed. The extended instructions are specifically implemented to optimize re-entrant program code (that is, code that is recursive or that uses a software stack) written in high-level languages, particularly C. Among other things, they allow users working in high-level languages to perform certain operations on data structures more efficiently. These include: When the extended instruction set is enabled, brackets are also used to indicate index arguments in bitoriented and byte-oriented instructions. This is in addition to other changes in their syntax. For more details, see Section 25.2.3.1 "Extended Instruction Syntax with Standard PIC18 Commands". * Dynamic allocation and deallocation of software stack space when entering and leaving subroutines * Function Pointer invocation * Software Stack Pointer manipulation * Manipulation of variables located in a software stack TABLE 25-3: The instruction set extension and the Indexed Literal Offset Addressing mode were designed for optimizing applications written in C; the user may likely never use these instructions directly in assembler. The syntax for these commands is provided as a reference for users who may be reviewing code that has been generated by a compiler. Note: In the past, square brackets have been used to denote optional arguments in the PIC18 and earlier instruction sets. In this text and going forward, optional arguments are denoted by braces ("{ }"). EXTENSIONS TO THE PIC18 INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Operands ADDFSR ADDULNK CALLW MOVSF f, k k MOVSS zs, zd PUSHL k SUBFSR SUBULNK f, k k zs, fd Description Cycles MSb Add literal to FSR Add literal to FSR2 and return Call subroutine using WREG Move zs (source) to 1st word fd (destination) 2nd word Move zs (source) to 1st word zd (destination) 2nd word Store literal at FSR2, decrement FSR2 Subtract literal from FSR Subtract literal from FSR2 and return (c) 2007 Microchip Technology Inc. 1 2 2 2 LSb Status Affected 1000 1000 0000 1011 ffff 1011 xxxx 1010 ffkk 11kk 0001 0zzz ffff 1zzz xzzz kkkk kkkk kkkk 0100 zzzz ffff zzzz zzzz kkkk None None None None 1 1110 1110 0000 1110 1111 1110 1111 1110 1 2 1110 1110 1001 1001 ffkk 11kk kkkk kkkk None None 2 Preliminary None None DS39761B-page 405 PIC18F2682/2685/4682/4685 25.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 k 63 f [ 0, 1, 2 ] Operands: 0 k 63 FSR(f) + k FSR(f) Operation: Operation: FSR2 + k FSR2, PC = (TOS) Status Affected: None Status Affected: None Encoding: 1110 1000 ffkk kkkk Description: The 6-bit literal `k' is added to the contents of the FSR specified by `f'. Words: 1 Cycles: 1 Encoding: 1110 Description: Q1 Q2 Q3 Q4 Read literal `k' Process Data Write to FSR Example: ADDFSR 2, 23h Before Instruction FSR2 = 03FFh After Instruction FSR2 = 0422h 11kk kkkk The 6-bit literal `k' is added to the contents of FSR2. A RETURN is then executed by loading the PC with the TOS. This may be thought of as a special case of the ADDFSR instruction, where f = 3 (binary `11'); it operates only on FSR2. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to FSR No Operation No Operation No Operation No Operation Example: Note: 1000 The instruction takes two cycles to execute; a NOP is performed during the second cycle. Q Cycle Activity: Decode Add Literal to FSR2 and Return ADDULNK 23h Before Instruction FSR2 = PC = TOS = 03FFh 0100h 02AFh After Instruction FSR2 = PC = TOS = 0422h 02AFh TOS - 1 All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s). DS39761B-page 406 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 CALLW Subroutine Call Using WREG MOVSF Syntax: CALLW Syntax: MOVSF [zs], fd Operands: None Operands: Operation: (PC + 2) TOS, (W) PCL, (PCLATH) PCH, (PCLATU) PCU 0 zs 127 0 fd 4095 Operation: ((FSR2) + zs) fd Status Affected: None Status Affected: 0000 Description Encoding: None Encoding: Move Indexed to f 1st word (source) 0000 0001 0100 First, the return address (PC + 2) is pushed onto the return stack. Next, the contents of W are written to PCL; the existing value is discarded. Then, the contents of PCLATH and PCLATU are latched into PCH and PCU, respectively. The second cycle is executed as a NOP instruction while the new next instruction is fetched. Description: Unlike CALL, there is no option to update W, STATUS or BSR. Words: 1 Cycles: 2 Q1 Q2 Q3 Q4 Read WREG Push PC to stack No operation No operation No operation No operation Before Instruction PC = PCLATH = PCLATU = W = After Instruction PC = TOS = PCLATH = PCLATU = W = Words: 2 Cycles: 2 Q Cycle Activity: Decode CALLW Decode address (HERE) 10h 00h 06h 001006h address (HERE + 2) 10h 00h 06h (c) 2007 Microchip Technology Inc. zzzzs ffffd The contents of the source register are moved to destination register `fd'. The actual address of the source register is determined by adding the 7-bit literal offset `zs' in the first word to the value of FSR2. The address of the destination register is specified by the 12-bit literal `fd' in the second word. Both addresses can be anywhere in the 4096-byte data space (000h to FFFh). Q1 HERE 0zzz ffff If the resultant source address points to an indirect addressing register, the value returned will be 00h. Decode Example: 1011 ffff The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. Q Cycle Activity: No operation 1110 1111 2nd word (destin.) Q2 Q3 Determine Determine source addr source addr No operation No operation No dummy read Example: MOVSF Before Instruction FSR2 Contents of 85h REG2 After Instruction FSR2 Contents of 85h REG2 Preliminary Q4 Read source reg Write register `f' (dest) [05h], REG2 = 80h = = 33h 11h = 80h = = 33h 33h DS39761B-page 407 PIC18F2682/2685/4682/4685 MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: Syntax: PUSHL k Operands: MOVSS [zs], [zd] 0 zs 127 0 zd 127 Operands: 0 k 255 Operation: ((FSR2) + zs) ((FSR2) + zd) Operation: k (FSR2), FSR2 - 1 FSR2 Status Affected: None Status Affected: None Encoding: Encoding: 1st word (source) 1110 1111 2nd word (dest.) Description 1011 xxxx 1zzz xzzz zzzzs zzzzd The contents of the source register are moved to the destination register. The addresses of the source and destination registers are determined by adding the 7-bit literal offsets `zs' or `zd', respectively, to the value of FSR2. Both registers can be located anywhere in the 4096-byte data memory space (000h to FFFh). Description: Words: 2 Cycles: 2 1010 kkkk kkkk The 8-bit literal `k' is written to the data memory address specified by FSR2. FSR2 is decremented by 1 after the operation. This instruction allows users to push values onto a software stack. Words: 1 Cycles: 1 Q Cycle Activity: The MOVSS instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an indirect addressing register, the value returned will be 00h. If the resultant destination address points to an indirect addressing register, the instruction will execute as a NOP. 1111 Q1 Q2 Q3 Q4 Decode Read `k' Process data Write to destination Example: PUSHL 08h Before Instruction FSR2H:FSR2L Memory (01ECh) = = 01ECh 00h After Instruction FSR2H:FSR2L Memory (01ECh) = = 01EBh 08h Q Cycle Activity: Q1 Decode Decode Q2 Q3 Determine Determine source addr source addr Determine dest addr Example: Write to dest reg MOVSS [05h], [06h] Before Instruction FSR2 Contents of 85h Contents of 86h After Instruction FSR2 Contents of 85h Contents of 86h DS39761B-page 408 Determine dest addr Q4 Read source reg = 80h = 33h = 11h = 80h = 33h = 33h Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 SUBFSR Subtract Literal from FSR SUBULNK Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 k 63 f [ 0, 1, 2 ] Operands: 0 k 63 Operation: Operation: FSRf - k FSRf FSR2 - k FSR2, (TOS) PC Status Affected: None Encoding: 1110 Subtract Literal from FSR2 and Return Status Affected: None 1001 ffkk kkkk Description: The 6-bit literal `k' is subtracted from the contents of the FSR specified by `f'. Words: 1 Cycles: 1 Encoding: 1110 Description: 1001 11kk kkkk The 6-bit literal `k' is subtracted from the contents of the FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the SUBFSR instruction, where f = 3 (binary `11'); it operates only on FSR2. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Words: 1 Cycles: 2 Q Cycle Activity: Example: SUBFSR 2, 23h Before Instruction FSR2 = 03FFh After Instruction FSR2 = 03DCh Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination No Operation No Operation No Operation No Operation Example: (c) 2007 Microchip Technology Inc. Preliminary SUBULNK 23h Before Instruction FSR2 = PC = 03FFh 0100h After Instruction FSR2 = PC = 03DCh (TOS) DS39761B-page 409 PIC18F2682/2685/4682/4685 25.2.3 Note: BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing mode (Section 5.6.1 "Indexed Addressing with Literal Offset"). This has a significant impact on the way that many commands of the standard PIC18 instruction set are interpreted. When the extended set is disabled, addresses embedded in opcodes are treated as literal memory locations: either as a location in the Access Bank (a = 0), or in a GPR bank designated by the BSR (a = 1). When the extended instruction set is enabled and a = 0, however, a file register argument of 5Fh or less is interpreted as an offset from the pointer value in FSR2 and not as a literal address. For practical purposes, this means that all instructions that use the Access RAM bit as an argument - that is, all bit-oriented and byte-oriented instructions, or almost half of the core PIC18 instructions - may behave differently when the extended instruction set is enabled. When the content of FSR2 is 00h, the boundaries of the Access RAM are essentially remapped to their original values. This may be useful in creating backward compatible code. If this technique is used, it may be necessary to save the value of FSR2 and restore it when moving back and forth between `C' and assembly routines in order to preserve the Stack Pointer. Users must also keep in mind the syntax requirements of the extended instruction set (see Section 25.2.3.1 "Extended Instruction Syntax with Standard PIC18 Commands"). 25.2.3.1 Extended Instruction Syntax with Standard PIC18 Commands When the extended instruction set is enabled, the file register argument, `f', in the standard byte-oriented and bit-oriented commands, is replaced with the literal offset value, `k'. As already noted, this occurs only when `f' is less than or equal to 5Fh. When an offset value is used, it must be indicated by square brackets ("[ ]"). As with the extended instructions, the use of brackets indicates to the compiler that the value is to be interpreted as an index or an offset. Omitting the brackets, or using a value greater than 5Fh within brackets, will generate an error in the MPASMTM Assembler. If the index argument is properly bracketed for Indexed Literal Offset Addressing, the Access RAM argument is never specified; it will automatically be assumed to be `0'. This is in contrast to standard operation (extended instruction set disabled) when `a' is set on the basis of the target address. Declaring the Access RAM bit in this mode will also generate an error in the MPASM Assembler. The destination argument, `d', functions as before. In the latest versions of the MPASM Assembler, language support for the extended instruction set must be explicitly invoked. This is done with either the command line option, /y, or the PE directive in the source listing. 25.2.4 CONSIDERATIONS WHEN ENABLING THE EXTENDED INSTRUCTION SET It is important to note that the extensions to the instruction set may not be beneficial to all users. In particular, users who are not writing code that uses a software stack may not benefit from using the extensions to the instruction set. Although the Indexed Literal Offset Addressing mode can be very useful for dynamic stack and pointer manipulation, it can also be very annoying if a simple arithmetic operation is carried out on the wrong register. Users who are accustomed to the PIC18 programming must keep in mind that, when the extended instruction set is enabled, register addresses of 5Fh or less are used for Indexed Literal Offset Addressing. Additionally, the Indexed Literal Offset Addressing mode may create issues with legacy applications written to the PIC18 assembler. This is because instructions in the legacy code may attempt to address registers in the Access Bank below 5Fh. Since these addresses are interpreted as literal offsets to FSR2 when the instruction set extension is enabled, the application may read or write to the wrong data addresses. Representative examples of typical byte-oriented and bit-oriented instructions in the Indexed Literal Offset Addressing mode are provided on the following page to show how execution is affected. The operand conditions shown in the examples are applicable to all instructions of these types. When porting an application to the PIC18F2682/2685/ 4682/4685, it is very important to consider the type of code. A large, re-entrant application that is written in `C' and would benefit from efficient compilation will do well when using the instruction set extensions. Legacy applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set. DS39761B-page 410 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 ADDWF ADD W to Indexed (Indexed Literal Offset mode) BSF Bit Set Indexed (Indexed Literal Offset mode) Syntax: ADDWF Syntax: BSF [k], b Operands: 0 k 95 d [0,1] a=0 Operands: 0 f 95 0b7 a=0 Operation: (W) + ((FSR2) + k) dest Operation: 1 ((FSR2 + k))<b> Status Affected: None [k] {,d} Status Affected: N, OV, C, DC, Z Encoding: 0010 Description: 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offset by the value `k'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). Words: 1 Cycles: 1 Encoding: bbb0 kkkk kkkk Description: Bit `b' of the register indicated by FSR2, offset by the value `k', is set. Words: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read `k' Process Data Write to destination Example: 1000 ADDWF Before Instruction W OFST FSR2 Contents of 0A2Ch After Instruction W Contents of 0A2Ch 17h 2Ch 0A00h = 20h = 37h = 20h Q2 Q3 Q4 Read register `f' Process Data Write to destination Example: BSF Before Instruction FLAG_OFST FSR2 Contents of 0A0Ah After Instruction Contents of 0A0Ah [OFST] ,0 = = = Q1 Decode [FLAG_OFST], 7 = = 0Ah 0A00h = 55h = D5h Set Indexed (Indexed Literal Offset mode) SETF Syntax: SETF [k] Operands: 0 k 95 Operation: FFh ((FSR2) + k) Status Affected: None Encoding: 0110 1000 kkkk kkkk Description: The contents of the register indicated by FSR2, offset by `k', are set to FFh. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read `k' Process Data Write register Example: SETF Before Instruction OFST FSR2 Contents of 0A2Ch After Instruction Contents of 0A2Ch (c) 2007 Microchip Technology Inc. Preliminary [OFST] = = 2Ch 0A00h = 00h = FFh DS39761B-page 411 PIC18F2682/2685/4682/4685 25.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB(R) IDE TOOLS The latest versions of Microchip's software tools have been designed to fully support the extended instruction set of the PIC18F2682/2685/4682/4685 family of devices. This includes the MPLAB C18 C compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for the XINST Configuration bit is `0', disabling the extended instruction set and Indexed Literal Offset Addressing mode. For proper execution of applications developed to take advantage of the extended instruction set, XINST must be set during programming. DS39761B-page 412 To develop software for the extended instruction set, the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). Depending on the environment being used, this may be done in several ways: * A menu option, or dialog box within the environment, that allows the user to configure the language tool and its settings for the project * A command line option * A directive in the source code These options vary between different compilers, assemblers and development environments. Users are encouraged to review the documentation accompanying their development systems for the appropriate information. Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 26.0 DEVELOPMENT SUPPORT 26.1 The PIC(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer - PICkitTM 2 Development Programmer * Low-Cost Demonstration and Development Boards and Evaluation Kits MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Visual device initializer for easy register initialization * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 413 PIC18F2682/2685/4682/4685 26.2 MPASM Assembler 26.5 The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility 26.6 26.3 MPLAB C18 and MPLAB C30 C Compilers The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip's PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 26.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. MPLAB ASM30 Assembler, Linker and Librarian MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction DS39761B-page 414 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 26.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 26.9 The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows(R) 32-bit operating system were chosen to best make these features available in a simple, unified application. 26.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC(R) and MCU devices. It debugs and programs PIC(R) and dsPIC(R) Flash microcontrollers with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high speed, noise tolerant, lowvoltage differential signal (LVDS) interconnection (CAT5). MPLAB ICD 2 In-Circuit Debugger Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices. 26.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications. MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 415 PIC18F2682/2685/4682/4685 26.11 PICSTART Plus Development Programmer 26.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. 26.12 PICkit 2 Development Programmer The PICkitTM 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip's baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH's PICCTM Lite C compiler, and is designed to help get up to speed quickly using PIC(R) microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip's powerful, mid-range Flash memory family of microcontrollers. DS39761B-page 416 The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart(R) battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest "Product Selector Guide" (DS00148) for the complete list of demonstration, development and evaluation kits. Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 27.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings () Ambient temperature under bias.............................................................................................................-40C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V Total power dissipation (Note 1) ...............................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports ..................................................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL) 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR/VPP/RE3 pin, rather than pulling this pin directly to VSS. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 417 PIC18F2682/2685/4682/4685 FIGURE 27-1: PIC18F2682/2685/4682/4685 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18F268X/468X 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz Frequency FIGURE 27-2: PIC18LF2682/2685/4682/4685 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18LF268X/468X 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz 4 MHz Frequency FMAX = (16.36 MHz/V) (VDDAPPMIN - 2.0V) + 4 MHz Note: VDDAPPMIN is the minimum voltage of the PIC(R) device in the application. DS39761B-page 418 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 27.1 DC Characteristics: Supply Voltage PIC18F2682/2685/4682/4685 (Industrial) PIC18LF2682/2685/4682/4685 (Industrial) PIC18LF2682/2685/4682/4685 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F2682/2685/4682/4685 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Symbol Characteristic Min Typ Max Units VDD Supply Voltage 2.0 -- 5.5 V D002 VDR RAM Data Retention Voltage(1) 1.5 -- -- V D003 VPOR VDD Start Voltage to ensure internal Power-on Reset signal -- -- 0.7 V D004 SVDD VDD Rise Rate to ensure internal Power-on Reset signal 0.05 -- -- VBOR Brown-out Reset Voltage BORV1:BORV0 = 11 2.00 2.05 2.16 V BORV1:BORV0 = 10 2.65 2.79 2.93 V BORV1:BORV0 = 01 4.11 4.33 4.55 V BORV1:BORV0 = 00 4.36 4.59 4.82 V D001 D005 PIC18LF268X/468X See section on Power-on Reset for details V/ms See section on Power-on Reset for details PIC18LF268X/468X D005 Legend: Note 1: Conditions All Devices Shading of rows is to assist in readability of the table. This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 419 PIC18F2682/2685/4682/4685 27.2 DC Characteristics: Power-Down and Supply Current PIC18F2682/2685/4682/4685 (Industrial) PIC18LF2682/2685/4682/4685 (Industrial) PIC18LF2682/2685/4682/4685 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F2682/2685/4682/4685 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions Power-Down Current (IPD)(1) PIC18LF268X/468X PIC18LF268X/468X All devices Extended devices only Legend: Note 1: 2: 3: 4: 0.1 0.95 A -40C 0.1 1 A +25C 0.2 6 A +85C 0.1 1.4 A -40C 0.1 2 A +25C 0.3 8 A +85C 0.1 1.9 A -40C 0.1 2 A +25C 0.4 15 A +85C 10 120 A +125C VDD = 2.0V (Sleep mode) VDD = 3.0V (Sleep mode) VDD = 5.0V (Sleep mode) Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. DS39761B-page 420 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 27.2 DC Characteristics: Power-Down and Supply Current PIC18F2682/2685/4682/4685 (Industrial) PIC18LF2682/2685/4682/4685 (Industrial) (Continued) PIC18LF2682/2685/4682/4685 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F2682/2685/4682/4685 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions Supply Current (IDD)(2,3) PIC18LF268X/468X PIC18LF268X/468X All devices Extended devices only PIC18LF268X/468X PIC18LF268X/468X All devices Extended devices only PIC18LF268X/468X PIC18LF268X/468X All devices Extended devices only Legend: Note 1: 2: 3: 4: 15 36 A -40C 15 36 A +25C 15 36 A +85C 40 100 A -40C 35 100 A +25C 30 100 A +85C 105 200 A -40C 90 200 A +25C 80 200 A +85C 80 200 A +125C 0.32 1 mA -40C 0.33 1 mA +25C 0.33 1 mA +85C 0.6 1.6 mA -40C 0.55 1.6 mA +25C 0.6 1.6 mA +85C 1.1 3 mA -40C 1.1 3 mA +25C 1 3 mA +85C +125C 1 3 mA 0.8 2.2 mA -40C 0.8 2.2 mA +25C +85C 0.8 2.2 mA 1.3 3 mA -40C 1.3 3 mA +25C 1.3 3 mA +85C 2.5 5.3 mA -40C 2.5 5.3 mA +25C 2.5 5.3 mA +85C 2.5 8 mA +125C VDD = 2.0V VDD = 3.0V FOSC = 31 kHz (RC_RUN mode, Internal oscillator source) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 1 MHz (RC_RUN mode, Internal oscillator source) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 4 MHz (RC_RUN mode, Internal oscillator source) VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 421 PIC18F2682/2685/4682/4685 27.2 DC Characteristics: Power-Down and Supply Current PIC18F2682/2685/4682/4685 (Industrial) PIC18LF2682/2685/4682/4685 (Industrial) (Continued) PIC18LF2682/2685/4682/4685 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F2682/2685/4682/4685 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions 2.9 8 A -40C 3.1 8 A +25C 3.6 12 A +85C 4.5 12 A -40C 4.8 12 A +25C 5.8 17 A +85C 9.2 25 A -40C 9.8 25 A +25C 11.4 36 A +85C +125C Supply Current (IDD)(2,3) PIC18LF268X/468X PIC18LF268X/468X All devices Extended devices only 21 180 A PIC18LF268X/468X 165 400 A -40C 175 400 A +25C 190 400 A +85C 250 600 A -40C 270 600 A +25C 290 600 A +85C 0.5 1 mA -40C 0.5 1 mA +25C 0.5 1 mA +85C Extended devices only 0.6 1.4 mA +125C PIC18LF268X/468X 0.34 1.1 mA -40C 0.35 1.1 mA +25C 0.36 1.1 mA +85C PIC18LF268X/468X All devices PIC18LF268X/468X All devices Extended devices only Legend: Note 1: 2: 3: 4: 0.52 1.5 mA -40C 0.54 1.5 mA +25C 0.58 1.5 mA +85C 1 2.7 mA -40C 1.1 2.7 mA +25C 1.1 2.7 mA +85C 1.1 3.6 mA +125C VDD = 2.0V VDD = 3.0V FOSC = 31 kHz (RC_IDLE mode, Internal oscillator source) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 1 MHz (RC_IDLE mode, Internal oscillator source) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 4 MHz (RC_IDLE mode, Internal oscillator source) VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. DS39761B-page 422 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 27.2 DC Characteristics: Power-Down and Supply Current PIC18F2682/2685/4682/4685 (Industrial) PIC18LF2682/2685/4682/4685 (Industrial) (Continued) PIC18LF2682/2685/4682/4685 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F2682/2685/4682/4685 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions 250 600 A -40C 250 600 A +25C 250 600 A +85C Supply Current (IDD)(2,3) PIC18LF268X/468X PIC18LF268X/468X All devices Extended devices only 460 1.2 mA +85C 1.2 3 mA -40C 1.1 3 mA +25C 1 3 mA +85C VDD = 3.0V mA +125C mA -40C 0.74 2.2 mA +25C 0.74 2.2 mA +85C 1.3 3.3 mA -40C 1.3 3.3 mA +25C 1.3 3.3 mA +85C 2.7 6.6 mA -40C 2.6 6.6 mA +25C 2.5 6.6 mA +85C Extended devices only 2.6 6.6 mA +125C Extended devices only 8.4 21 mA +125C VDD = 4.2V 11 28 mA +125C VDD = 5.0V 15 38 mA -40C 16 38 mA +25C 16 38 mA +85C All devices 21 44 mA -40C 21 44 mA +25C 21 44 mA +85C FOSC = 1 MHZ (PRI_RUN, EC oscillator) VDD = 5.0V 3 All devices 4: -40C +25C 2.2 All devices 3: mA mA 1 PIC18LF268X/468X 2: 1.2 1.2 0.72 PIC18LF268X/468X Legend: Note 1: 550 480 VDD = 2.0V VDD = 2.0V VDD = 3.0V FOSC = 4 MHz (PRI_RUN, EC oscillator) VDD = 5.0V FOSC = 25 MHz (PRI_RUN, EC oscillator) VDD = 4.2V FOSC = 40 MHZ (PRI_RUN, EC oscillator) VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 423 PIC18F2682/2685/4682/4685 27.2 DC Characteristics: Power-Down and Supply Current PIC18F2682/2685/4682/4685 (Industrial) PIC18LF2682/2685/4682/4685 (Industrial) (Continued) PIC18LF2682/2685/4682/4685 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F2682/2685/4682/4685 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions Supply Current (IDD)(2,3) All devices Legend: Note 1: 2: 3: 4: 9.00 18.00 mA -40C 8.90 17.00 mA +25C 8.80 16.00 mA +85C All devices 12.00 24.00 mA -40C 12.00 22.00 mA +25C 12.00 21.00 mA +85C All devices 21.00 39.00 mA -40C 21.00 39.00 mA +25C +85C 21.00 39.00 mA All devices 28.00 44.00 mA -40C 28.00 44.00 mA +25C 28.00 44.00 mA +85C VDD = 4.2V FOSC = 4 MHZ (PRI_RUN HSPLL) VDD = 5.0V FOSC = 4 MHZ (PRI_RUN HSPLL) VDD = 4.2V FOSC = 10 MHZ (PRI_RUN HSPLL) VDD = 5.0V FOSC = 10 MHZ (PRI_RUN HSPLL) Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. DS39761B-page 424 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 27.2 DC Characteristics: Power-Down and Supply Current PIC18F2682/2685/4682/4685 (Industrial) PIC18LF2682/2685/4682/4685 (Industrial) (Continued) PIC18LF2682/2685/4682/4685 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F2682/2685/4682/4685 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions 65 220 A -40C 65 220 A +25C 70 220 A +85C 120 330 A -40C 120 330 A +25C 130 330 A +85C 300 600 A -40C 240 600 A +25C 300 600 A +85C Supply Current (IDD)(2,3) PIC18LF268X/468X PIC18LF268X/468X All devices Extended devices only 320 600 A +125C PIC18LF268X/468X 260 760 A -40C 255 760 A +25C 270 760 A +85C A -40C 1.4 A +25C 450 1.4 A +85C 0.9 2.2 mA -40C 0.9 2.2 mA +25C 0.9 2.2 mA +85C Extended devices only 1 3 mA +125C Extended devices only 2.8 7 mA +125C VDD = 4.2V 4.3 11 mA +125C VDD = 5.0V All devices 3: 4: VDD = 2.0V 1.4 All devices 6 18 mA -40C 6.2 18 mA +25C 6.6 18 mA +85C 8.1 22 mA -40C 9.1 22 mA +25C 8.3 22 mA +85C FOSC = 1 MHz (PRI_IDLE mode, EC oscillator) VDD = 5.0V 420 All devices 2: VDD = 3.0V 430 PIC18LF268X/468X Legend: Note 1: VDD = 2.0V VDD = 3.0V FOSC = 4 MHz (PRI_IDLE mode, EC oscillator) VDD = 5.0V FOSC = 25 MHz (PRI_IDLE mode, EC oscillator) VDD = 4.2 V FOSC = 40 MHz (PRI_IDLE mode, EC oscillator) VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 425 PIC18F2682/2685/4682/4685 27.2 DC Characteristics: Power-Down and Supply Current PIC18F2682/2685/4682/4685 (Industrial) PIC18LF2682/2685/4682/4685 (Industrial) (Continued) PIC18LF2682/2685/4682/4685 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F2682/2685/4682/4685 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions Supply Current (IDD)(2,3) PIC18LF268X/468X PIC18LF268X/468X All devices PIC18LF268X/468X PIC18LF268X/468X All devices Legend: Note 1: 2: 3: 4: 14 40 A -40C 15 40 A +25C 16 40 A +85C 40 86 A -40C 35 86 A +25C 31 86 A +85C 99 180 A -40C 81 180 A +25C 75 180 A +85C 2.5 20 A -40C 3.7 20 A +25C 4.5 20 A +85C 5 25 A -40C 5.4 25 A +25C 6.3 25 A +85C 8.5 30 A -40C 9 30 A +25C 10.5 30 A +85C VDD = 2.0V VDD = 3.0V FOSC = 32 kHz(4) (SEC_RUN mode, Timer1 as clock) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 32 kHz(4) (SEC_IDLE mode, Timer1 as clock) VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. DS39761B-page 426 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 27.2 DC Characteristics: Power-Down and Supply Current PIC18F2682/2685/4682/4685 (Industrial) PIC18LF2682/2685/4682/4685 (Industrial) (Continued) PIC18LF2682/2685/4682/4685 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F2682/2685/4682/4685 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions Module Differential Currents (IWDT, IBOR, ILVD, IOSCB, IAD) D022 (IWDT) D022A Watchdog Timer Brown-out Reset (IBOR) D022B High/Low-Voltage Detect (ILVD) D025 Timer1 Oscillator (IOSCB) A/D Converter D026 (IAD) Legend: Note 1: 2: 3: 4: 4.5 A -40C 1.4 4.5 A +25C 2 4.5 A +85C 1.3 VDD = 2.0V 1.9 5.5 A -40C 2 5.5 A +25C 2.8 5.5 A +85C 4 10 A -40C 5.5 10 A +25C 5.6 10 A +85C 13 14 A -40C to +125C 35 65 A -40C to +85C 40 75 A -40C to +85C 55 75 A -40C to +125C 22 45 A -40C to +85C VDD = 2.0V 25 45 A -40C to +85C VDD = 3.0V 29 55 A -40C to +85C 30 55 A -40C to +125C 2.1 4.5 A -40C to +85C 1.8 4.5 A -40C to +85C 2.1 4.5 A -40C to +125C 2.2 6 A -40C 2.6 6 A +25C 2.9 6 A +85C 3 8 A -40C 3.2 8 A +25C VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD = 5.0V VDD = 5.0V VDD = 2.0V 32 kHz on Timer1(4) VDD = 3.0V 32 kHz on Timer1(4) VDD = 5.0V 32 kHz on Timer1(4) 3.4 8 A +85C 1 2 A -40C to +85C VDD = 2.0V 1 2 A -40C to +85C VDD = 3.0V 1 2 A -40C to +85C 2 8 A -40C to +125C VDD = 5.0V A/D on, not converting 1.6 S TAD 6.4 S Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Standard low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 427 PIC18F2682/2685/4682/4685 27.3 DC Characteristics: PIC18F2682/2685/4682/4685 (Industrial) PIC18LF2682/2685/4682/4685 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Max Units Conditions VSS 0.15 VDD V VDD < 4.5V -- 0.8 V 4.5V VDD 5.5V Input Low Voltage I/O ports: D030 with TTL buffer D030A D031 with Schmitt Trigger buffer VSS 0.2 VDD V D031A RC3 and RC4 VSS 0.3 VDD V I2CTM enabled VSS 0.8 V SMBus enabled MCLR VSS 0.2 VDD V D033 OSC1 VSS 0.3 VDD V HS, HSPLL modes D033A OSC1 VSS 0.2 VDD V RC, EC modes(1) XT, LP modes D031B D032 D033B OSC1 VSS 0.3 V D034 T13CKI VSS 0.3 V 0.25 VDD + 0.8V VDD V VDD < 4.5V 2.0 VDD V 4.5V VDD 5.5V VIH Input High Voltage I/O ports: D040 with TTL buffer D040A D041 with Schmitt Trigger buffer 0.8 VDD VDD V D041A RC3 and RC4 0.7 VDD VDD V I2CTM enabled SMBus enabled D041B 2.1 VDD V VDD V D042 MCLR 0.8 VDD D043 OSC1 0.7 VDD VDD V HS, HSPLL modes D043A OSC1 0.8 VDD VDD V EC mode D043B OSC1 0.9 VDD VDD V RC mode(1) D043C OSC1 1.6 VDD V XT, LP modes D044 T13CKI 1.6 VDD V I/O ports -- 1 A VSS VPIN VDD, Pin at high-impedance D061 MCLR -- 5 A Vss VPIN VDD D063 OSC1 -- 5 A Vss VPIN VDD 50 400 A VDD = 5V, VPIN = VSS IIL D060 D070 Note 1: 2: 3: 4: Input Leakage Current(2,3) IPU Weak Pull-up Current IPURB PORTB weak pull-up current In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC(R) device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Parameter is characterized but not tested. DS39761B-page 428 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 27.3 DC Characteristics: PIC18F2682/2685/4682/4685 (Industrial) PIC18LF2682/2685/4682/4685 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial DC CHARACTERISTICS Param Symbol No. VOL Characteristic Min Max Units Conditions Output Low Voltage D080 I/O ports -- 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C D083 OSC2/CLKO (RC, RCIO, EC, ECIO modes) -- 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40C to +85C VOH Output High Voltage(3) D090 I/O ports VDD - 0.7 -- V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C D092 OSC2/CLKO (RC, RCIO, EC, ECIO modes) VDD - 0.7 -- V IOH = -1.3 mA, VDD = 4.5V, -40C to +85C Capacitive Loading Specs on Output Pins D100(4) COSC2 OSC2 pin -- 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O pins and OSC2 (in RC mode) -- 50 pF To meet the AC timing specifications D102 CB SCL, SDA -- 400 pF I2CTM specification Note 1: 2: 3: 4: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC(R) device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Parameter is characterized but not tested. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 429 PIC18F2682/2685/4682/4685 TABLE 27-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial DC Characteristics Param No. Sym Characteristic Min Typ Max Units Conditions 9.00 -- 13.25 V -- -- 10 mA E/W -40C to +85C Internal Program Memory Programming Specifications(1) D110 VPP Voltage on MCLR/VPP/RE3 pin D113 IDDP Supply Current during Programming D120 ED Byte Endurance 100K 1M -- D121 VDRW VDD for Read/Write VMIN -- 5.5 (Note 3) Data EEPROM Memory V Using EECON to read/write VMIN = Minimum operating voltage D122 TDEW Erase/Write Cycle Time -- 4 -- D123 TRETD Characteristic Retention 40 -- -- Year Provided no other specifications are violated ms D124 TREF Number of Total Erase/Write Cycles before Refresh(2) 1M 10M -- E/W -40C to +85C D130 EP Cell Endurance 10K 100K -- E/W -40C to +85C D131 VPR VDD for Read VMIN -- 5.5 D132 VIE VDD for Block Erase 4.5 -- 5.5 V Using ICSPTM port D132A VIW VDD for Externally Timed Erase or Write 4.5 -- 5.5 V Using ICSP port VMIN -- 5.5 V VMIN = Minimum operating voltage Program Flash Memory V VMIN = Minimum operating voltage D132B VPEW VDD for Self-timed Write D133 TIE ICSPTM Block Erase Cycle Time -- 4 -- ms VDD > 4.5V D133A TIW ICSP Erase or Write Cycle Time (externally timed) 1 -- -- ms VDD > 4.5V D133A TIW Self-timed Write Cycle Time D134 TRETD Characteristic Retention -- 2 -- 40 100 -- ms Year Provided no other specifications are violated Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: These specifications are for programming the on-chip program memory through the use of table write instructions. 2: Refer to Section 7.8 "Using the Data EEPROM" for a more detailed discussion on data EEPROM endurance. 3: Required only if Single-Supply Programming is disabled. DS39761B-page 430 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 27-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40C < TA < +85C (unless otherwise stated). Param No. Sym Characteristics Min Typ Max Units D300 VIOFF Input Offset Voltage -- 5.0 10 mV D301 VICM Input Common Mode Voltage* 0 -- VDD - 1.5 V Comments D302 CMRR Common Mode Rejection Ratio* 55 -- -- dB 300 TRESP Response Time(1)* -- 150 400 ns PIC18FXXXX -- 150 600 ns PIC18LFXXXX, VDD = 2.0V -- -- 10 s 300A 301 * Note 1: TMC2OV Comparator Mode Change to Output Valid* These parameters are characterized but not tested. Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from VSS to VDD. TABLE 27-3: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40C < TA < +85C (unless otherwise stated). Param No. Sym Characteristics Min Typ Max Units D310 VRES Resolution VDD/24 -- VDD/32 LSb D311 VRAA Absolute Accuracy -- -- -- -- 1/4 1/2 LSb LSb D312 VRUR Unit Resistor Value (R)* -- 2k -- TSET Time(1)* -- -- 10 s 310 * Note 1: Settling Comments Low Range (CVRR = 1) High Range (CVRR = 0) These parameters are characterized but not tested. Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from `0000' to `1111'. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 431 PIC18F2682/2685/4682/4685 FIGURE 27-3: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS VDD (HLVDIF can be cleared in software) VLVD (HLVDIF set by hardware) HLVDIF TABLE 27-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Param Sym No. D420 Characteristic HLVD Voltage on VDD Transition High-to-Low Min Typ Max Units HLVDL<3:0> = 0000 2.12 2.17 2.22 V HLVDL<3:0> = 0001 2.18 2.23 2.28 V HLVDL<3:0> = 0010 2.31 2.36 2.42 V HLVDL<3:0> = 0011 2.38 2.44 2.49 V HLVDL<3:0> = 0100 2.54 2.60 2.66 V HLVDL<3:0> = 0101 2.72 2.79 2.85 V HLVDL<3:0> = 0110 2.82 2.89 2.95 V HLVDL<3:0> = 0111 3.05 3.12 3.19 V HLVDL<3:0> = 1000 3.31 3.39 3.47 V HLVDL<3:0> = 1001 3.46 3.55 3.63 V HLVDL<3:0> = 1010 3.63 3.71 3.80 V HLVDL<3:0> = 1011 3.81 3.90 3.99 V HLVDL<3:0> = 1100 4.01 4.11 4.20 V HLVDL<3:0> = 1101 4.23 4.33 4.43 V HLVDL<3:0> = 1110 4.48 4.59 4.69 V HLVDL<3:0> = 1111 1.14 1.20 1.26 V Conditions Production tested at TAMB = 25C. Specifications over temperature limits ensured by characterization. DS39761B-page 432 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 27.4 27.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKO cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-Impedance) L Low I2C only AA output access BUF Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA Start condition (c) 2007 Microchip Technology Inc. 3. TCC:ST 4. Ts (I2C specifications only) (I2C specifications only) T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T13CKI WR P R V Z Period Rise Valid High-Impedance High Low High Low SU Setup STO Stop condition Preliminary DS39761B-page 433 PIC18F2682/2685/4682/4685 27.4.2 TIMING CONDITIONS Note: The temperature and voltages specified in Table 27-5 apply to all timing specifications unless otherwise noted. Figure 27-4 specifies the load conditions for the timing specifications. TABLE 27-5: Because of space limitations, the generic terms "PIC18FXXXX" and "PIC18LFXXXX" are used throughout this section to refer to the PIC18F2682/2685/4682/4685 and PIC18LF2682/2685/4682/4685 families of devices specifically and only those devices. TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC AC CHARACTERISTICS FIGURE 27-4: Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Operating voltage VDD range as described in DC spec Section 27.1 and Section 27.3. LF parts operate for industrial temperatures only. LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 Load Condition 2 VDD/2 RL CL Pin VSS CL Pin RL = 464 VSS DS39761B-page 434 CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 27.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 27-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 27-6: Param. No. 1A EXTERNAL CLOCK TIMING REQUIREMENTS Symbol FOSC Characteristic Min External CLKI Frequency(1) DC 1 MHz XT, RC Oscillator modes DC 25 MHz HS Oscillator mode DC 31.25 kHz LP Oscillator mode DC 40 MHz EC Oscillator mode DC 4 MHz RC Oscillator mode 0.1 4 MHz XT Oscillator mode 4 25 MHz HS Oscillator mode 4 10 MHz HSPLL Oscillator mode LP Oscillator mode Oscillator 1 TOSC Frequency(1) External CLKI Period(1) Oscillator Period(1) Time(1) 2 TCY Instruction Cycle 3 TOSL, TOSH External Clock in (OSC1) High or Low Time 4 Note 1: TOSR, TOSF External Clock in (OSC1) Rise or Fall Time Max Units Conditions 5 200 kHz 1000 -- ns XT, RC Oscillator modes 40 -- ns HS Oscillator mode 32 -- s LP Oscillator mode 25 -- ns EC Oscillator mode 250 -- ns RC Oscillator mode 250 1 s XT Oscillator mode 40 250 ns HS Oscillator mode 100 250 ns HSPLL Oscillator mode 5 200 s LP Oscillator mode 100 -- ns TCY = 4/FOSC 30 -- ns XT Oscillator mode 2.5 -- s LP Oscillator mode 10 -- ns HS Oscillator mode -- 20 ns XT Oscillator mode -- 50 ns LP Oscillator mode -- 7.5 ns HS Oscillator mode Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 435 PIC18F2682/2685/4682/4685 TABLE 27-7: Param No. PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V) Sym Characteristic Min Typ Max 4 16 -- -- 10 40 Units F10 F11 FOSC Oscillator Frequency Range FSYS On-Chip VCO System Frequency F12 trc PLL Start-up Time (Lock Time) -- -- 2 ms CLK CLKO Stability (Jitter) -2 -- +2 % F13 Conditions MHz HS mode only MHz HS mode only Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 27-8: AC CHARACTERISTICS: INTERNAL RC ACCURACY PIC18F2682/2685/4682/4685 (INDUSTRIAL) PIC18LF2682/2685/4682/4685 (INDUSTRIAL) PIC18LF2682/2685/4682/4685 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40C TA +85C for industrial PIC18F2682/2685/4682/4685 (Industrial) Param No. Device Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Min Typ Max Units Conditions INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1) PIC18LF268X/468X -2 +/-1 2 % +25C VDD = 2.7-3.3V -5 -- 5 % -10C to +85C VDD = 2.7-3.3V -10 +/-1 10 % -40C to +85C VDD = 2.7-3.3V 35.938 kHz -40C to +85C VDD = 2.7-3.3V INTRC Accuracy @ Freq = 31 kHz(2) PIC18LF268X/468X 26.562 -- Legend: Shading of rows is to assist in readability of the table. Note 1: Frequency calibrated at 25C. OSCTUNE register can be used to compensate for temperature drift. 2: INTRC frequency after calibration. DS39761B-page 436 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 FIGURE 27-6: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 19 14 12 18 16 I/O pin (Input) 15 17 I/O pin (Output) New Value Old Value 20, 21 Note: Refer to Figure 27-4 for load conditions. TABLE 27-9: Param No. CLKO AND I/O TIMING REQUIREMENTS Symbol Characteristic Min Typ Max Units Conditions 10 TOSH2CKL OSC1 to CLKO -- 75 200 ns 11 TOSH2CKH OSC1 to CLKO -- 75 200 ns (Note 1) 12 TCKR CLKO Rise Time -- 35 100 ns (Note 1) 13 TCKF CLKO Fall Time -- 35 100 ns (Note 1) 14 TCKL2IOV CLKO to Port Out Valid -- -- 0.5 TCY + 20 ns (Note 1) 15 TIOV2CKH Port In Valid before CLKO 16 TCKH2IOI 17 TOSH2IOV OSC1 (Q1 cycle) to Port Out Valid 18 TOSH2IOI 18A -- ns (Note 1) -- -- ns (Note 1) -- 50 150 ns 100 -- -- ns 200 -- -- ns 0 -- -- ns PIC18FXXXX -- 10 25 ns PIC18LFXXXX -- -- 60 ns PIC18FXXXX -- 10 25 ns PIC18LFXXXX -- -- 60 ns 20 TIOR Port Output Rise Time 20A TIOF -- 0 OSC1 (Q2 cycle) to Port PIC18FXXXX Input Invalid (I/O in hold PIC18LFXXXX time) TIOV2OSH Port Input Valid to OSC1 (I/O in setup time) 21 0.25 TCY + 25 Port In Hold after CLKO 19 Port Output Fall Time 21A (Note 1) 22 TINP INTx pin High or Low Time TCY -- -- ns 23 TRBP RB7:RB4 Change INTx High or Low Time TCY -- -- ns 24 TRCP RC7:RC4 Change INTx High or Low Time 20 -- -- ns VDD = 2.0V VDD = 2.0V VDD = 2.0V These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 437 PIC18F2682/2685/4682/4685 FIGURE 27-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure 27-4 for load conditions. FIGURE 27-8: BROWN-OUT RESET TIMING BVDD VDD 35 VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference Voltage Stable 36 TABLE 27-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. No. Sym Characteristic Min Typ Max Units 2 -- -- s 3.4 4.00 4.6 ms 1024 TOSC -- 1024 TOSC -- 55.6 65.5 75 ms -- 2 -- s 30 TMCL MCLR Pulse Width (low) 31 TWDT Watchdog Timer Time-out Period (no postscaler) 32 TOST Oscillation Start-up Timer Period 33 TPWRT Power-up Timer Period 34 TIOZ I/O High-Impedance from MCLR Low or Watchdog Timer Reset 35 TBOR Brown-out Reset Pulse Width 200 -- -- s 36 TIRVST Time for Internal Reference Voltage to become stable -- 20 50 s 37 TLVD High/Low-Voltage Detect Pulse Width 200 -- -- s 38 TCSD CPU Start-up Time -- 10 -- s 39 TIOBST Time for INTOSC to stabilize -- 1 -- s DS39761B-page 438 Preliminary Conditions TOSC = OSC1 period VDD BVDD (see D005) VDD VLVD (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 FIGURE 27-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T13CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 27-4 for load conditions. TABLE 27-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Sym Characteristic 40 TT0H T0CKI High Pulse Width No prescaler 41 TT0L T0CKI Low Pulse Width No prescaler 42 TT0P T0CKI Period No prescaler With prescaler With prescaler With prescaler 45 TT1H T13CKI High Time Synchronous, no prescaler TT1L T13CKI Low Time -- ns 10 -- ns 0.5 TCY + 20 -- ns 10 -- ns TCY + 10 -- ns Greater of: 20 ns or (TCY + 40)/N -- ns 0.5 TCY + 20 -- ns 10 -- ns PIC18LFXXXX 25 -- ns PIC18FXXXX 30 -- ns Synchronous, no prescaler Synchronous, with prescaler 50 -- ns 0.5 TCY + 5 -- ns Conditions N = prescale value (1, 2, 4,..., 256) VDD = 2.0V VDD = 2.0V PIC18FXXXX 10 -- ns PIC18LFXXXX 25 -- ns PIC18FXXXX 30 -- ns PIC18LFXXXX 50 -- ns VDD = 2.0V Greater of: 20 ns or (TCY + 40)/N -- ns N = prescale value (1, 2, 4, 8) TT1P T13CKI Input Synchronous Period FT 1 T13CKI Oscillator Input Frequency Range TCKE2TMRI Delay from External T13CKI Clock Edge to Timer Increment (c) 2007 Microchip Technology Inc. 0.5 TCY + 20 Asynchronous Asynchronous 48 Units PIC18FXXXX Asynchronous 47 Max Synchronous, with prescaler PIC18LFXXXX 46 Min Preliminary 60 -- ns DC 50 kHz 2 TOSC 7 TOSC -- VDD = 2.0V DS39761B-page 439 PIC18F2682/2685/4682/4685 FIGURE 27-10: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 Note: 54 Refer to Figure 27-4 for load conditions. TABLE 27-12: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param No. 50 Sym TCCL Characteristic Min CCPx Input Low No prescaler Time With prescaler PIC18FXXXX PIC18LFXXXX 51 TCCH CCPx Input High No prescaler Time With prescaler PIC18FXXXX TCCP 53 TCCR CCPx Output Fall Time 54 TCCF DS39761B-page 440 0.5 TCY + 20 -- ns 10 -- ns 20 -- ns 0.5 TCY + 20 -- ns Conditions VDD = 2.0V 10 -- ns -- ns VDD = 2.0V 3 TCY + 40 N -- ns N = prescale value (1, 4 or 16) PIC18FXXXX -- 25 ns PIC18LFXXXX -- 45 ns PIC18FXXXX -- 25 ns PIC18LFXXXX -- 45 ns CCPx Input Period CCPx Output Fall Time Units 20 PIC18LFXXXX 52 Max Preliminary VDD = 2.0V VDD = 2.0V (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 FIGURE 27-11: PARALLEL SLAVE PORT TIMING (PIC18F4682/4685) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 27-4 for load conditions. TABLE 27-13: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4682/4685) Param. No. Symbol Characteristic Min Max Units 20 -- ns PIC18FXXXX 20 -- ns PIC18LFXXXX 62 TDTV2WRH Data In Valid before WR or CS (setup time) 63 TWRH2DTI WR or CS to Data-In Invalid (hold time) 35 -- ns 64 TRDL2DTV RD and CS to Data-Out Valid -- 80 ns 65 TRDH2DTI RD or CS to Data-Out Invalid 10 30 ns 66 TIBFINH Inhibit of the IBF Flag bit being Cleared from WR or CS -- 3 TCY (c) 2007 Microchip Technology Inc. Preliminary Conditions VDD = 2.0V DS39761B-page 441 PIC18F2682/2685/4682/4685 FIGURE 27-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure 27-4 for load conditions. TABLE 27-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No. Symbol Characteristic Min Max Units 73 TDIV2SCH, TDIV2SCL Setup Time of SDI Data Input to SCK Edge 100 -- ns 74 TSCH2DIL, TSCL2DIL Hold Time of SDI Data Input to SCK Edge 100 -- ns 75 TDOR SDO Data Output Rise Time PIC18FXXXX -- 25 ns PIC18LFXXXX -- 45 ns 76 TDOF SDO Data Output Fall Time 78 TSCR SCK Output Rise Time 79 TSCF SCK Output Fall Time 80 TSCH2DOV, SDO Data Output Valid after TSCL2DOV SCK Edge DS39761B-page 442 -- 25 ns PIC18FXXXX -- 25 ns PIC18LFXXXX -- 45 ns -- 25 ns PIC18FXXXX -- 50 ns PIC18LFXXXX -- 100 ns Preliminary Conditions VDD = 2.0V VDD = 2.0V VDD = 2.0V (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 FIGURE 27-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 MSb SDO LSb bit 6 - - - - - -1 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 Note: Refer to Figure 27-4 for load conditions. TABLE 27-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No. Symbol Characteristic Min Max Units 73 TDIV2SCH, TDIV2SCL Setup Time of SDI Data Input to SCK Edge 100 -- ns 74 TSCH2DIL, TSCL2DIL Hold Time of SDI Data Input to SCK Edge 100 -- ns 75 TDOR SDO Data Output Rise Time -- 25 ns 76 TDOF SDO Data Output Fall Time 78 TSCR SCK Output Rise Time PIC18FXXXX PIC18LFXXXX 45 ns 25 ns PIC18FXXXX -- 25 ns PIC18LFXXXX -- 45 ns -- 25 ns PIC18FXXXX -- 50 ns -- 100 ns TCY -- ns 79 TSCF 80 TSCH2DOV, SDO Data Output Valid after TSCL2DOV SCK Edge SCK Output Fall Time 81 TDOV2SCH, SDO Data Output Setup to SCK Edge TDOV2SCL (c) 2007 Microchip Technology Inc. -- -- PIC18LFXXXX Preliminary Conditions VDD = 2.0V VDD = 2.0V VDD = 2.0V DS39761B-page 443 PIC18F2682/2685/4682/4685 FIGURE 27-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - -1 LSb 77 75, 76 MSb In SDI 73 Note: bit 6 - - - -1 LSb In 74 Refer to Figure 27-4 for load conditions. TABLE 27-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param No. Symbol Characteristic 70 TSSL2SCH, SS to SCK or SCK Input TSSL2SCL 71 TSCH SCK Input High Time 71A 72 TSCL SCK Input Low Time 72A Min -- ns Continuous 1.25 TCY + 30 -- ns 40 -- ns Continuous 1.25 TCY + 30 -- ns Single Byte 40 -- ns 100 -- ns -- ns -- ns TDIV2SCH, Setup Time of SDI Data Input to SCK Edge TDIV2SCL 73A TB2B 74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge TSCL2DIL 75 TDOR TDOF TCY Single Byte 73 76 Max Units Conditions Last Clock Edge of Byte1 to the First Clock Edge of Byte 2 1.5 TCY + 40 SDO Data Output Rise Time 100 PIC18FXXXX -- 25 ns PIC18LFXXXX -- 45 ns -- 25 ns SDO Data Output Fall Time 77 TSSH2DOZ SS to SDO Output High-Impedance 10 50 ns 80 TSCH2DOV, SDO Data Output Valid after SCK Edge PIC18FXXXX TSCL2DOV PIC18LFXXXX -- 50 ns -- 100 ns 83 TscH2ssH, SS after SCK Edge TscL2ssH 1.5 TCY + 40 -- ns Note 1: 2: (Note 1) (Note 1) (Note 2) VDD = 2.0V VDD = 2.0V Requires the use of parameter 73A. Only if parameter 71A and 72A are used. DS39761B-page 444 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 FIGURE 27-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - -1 LSb 75, 76 SDI MSb In 77 LSb In bit 6 - - - -1 74 Note: Refer to Figure 27-4 for load conditions. TABLE 27-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No. Symbol Characteristic Min 70 TSSL2SCH, SS to SCK or SCK Input TSSL2SCL 71 TSCH SCK Input High Time TSCL SCK Input Low Time 73A TB2B Last Clock Edge of Byte 1 to the fIrst Clock Edge of Byte 2 1.5 TCY + 40 74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge TSCL2DIL 75 TDOR Continuous 71A 72 72A 76 TDOF SDO Data Output Rise Time Max Units Conditions TCY -- ns 1.25 TCY + 30 -- ns Single Byte 40 -- ns Continuous 1.25 TCY + 30 -- ns Single Byte 40 100 -- ns (Note 1) -- ns (Note 2) -- ns PIC18FXXXX -- 25 ns PIC18LFXXXX -- 45 ns -- 25 ns SDO Data Output Fall Time 77 TSSH2DOZ SS to SDO Output High-Impedance 10 50 ns 80 TSCH2DOV, SDO Data Output Valid after SCK TSCL2DOV Edge -- 50 ns PIC18LFXXXX -- 100 ns 82 TSSL2DOV SDO Data Output Valid after SS PIC18FXXXX Edge PIC18LFXXXX -- 50 ns -- 100 ns 1.5 TCY + 40 -- ns 83 PIC18FXXXX TSCH2SSH, SS after SCK Edge TSCL2SSH Note 1: 2: (Note 1) VDD = 2.0V VDD = 2.0V VDD = 2.0V Requires the use of parameter 73A. Only if parameter 71A and 72A are used. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 445 PIC18F2682/2685/4682/4685 I2CTM BUS START/STOP BITS TIMING FIGURE 27-16: SCL 91 93 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 27-4 for load conditions. TABLE 27-18: I2CTM BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No. 90 91 92 93 TSU:STA THD:STA TSU:STO Characteristic Max Units Conditions ns Only relevant for Repeated Start condition ns After this period, the first clock pulse is generated Start Condition 100 kHz mode 4700 -- Setup Time 400 kHz mode 600 -- Start Condition 100 kHz mode 4000 -- Hold Time 400 kHz mode 600 -- Stop Condition 100 kHz mode 4700 -- Setup Time 400 kHz mode 600 -- 100 kHz mode 4000 -- 400 kHz mode 600 -- THD:STO Stop Condition Hold Time FIGURE 27-17: Min ns ns I2CTM BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 27-4 for load conditions. DS39761B-page 446 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 27-19: I2CTM BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. 100 Symbol THIGH 101 TLOW 102 TR 103 TF TSU:STA 90 91 THD:STA THD:DAT 106 107 TSU:DAT TSU:STO 92 109 TAA 110 TBUF D102 CB Note 1: 2: Characteristic Clock High Time Clock Low Time Min Max Units Conditions 100 kHz mode 4.0 -- s PIC18FXXXX must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 -- s PIC18FXXXX must operate at a minimum of 10 MHz MSSP module 1.5 TCY -- 100 kHz mode 4.7 -- s PIC18FXXXX must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 -- s PIC18FXXXX must operate at a minimum of 10 MHz MSSP module 1.5 TCY -- SDA and SCL Rise 100 kHz mode -- Time 400 kHz mode 20 + 0.1 CB 1000 ns 300 ns SDA and SCL Fall Time 100 kHz mode 300 ns 300 ns CB is specified to be from 10 to 400 pF Start Condition Setup Time 100 kHz mode 4.7 -- s 400 kHz mode 0.6 -- s Only relevant for Repeated Start condition Start Condition Hold Time 100 kHz mode 4.0 -- s 400 kHz mode 0.6 -- s Data Input Hold Time 100 kHz mode 0 -- ns 400 kHz mode 0 0.9 s Data Input Setup Time 100 kHz mode 250 -- ns 400 kHz mode 100 -- ns Stop Condition Setup Time Output Valid from Clock Bus Free Time -- 400 kHz mode 20 + 0.1 CB 100 kHz mode 4.7 -- s 400 kHz mode 0.6 -- s 100 kHz mode -- 3500 ns 400 kHz mode -- -- ns 100 kHz mode 4.7 -- s 400 kHz mode 1.3 -- s -- 400 pF Bus Capacitive Loading CB is specified to be from 10 to 400 pF After this period, the first clock pulse is generated (Note 2) (Note 1) Time the bus must be free before a new transmission can start As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode I2CTM bus device can be used in a Standard mode I2C bus system but the requirement, TSU:DAT 250 ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 447 PIC18F2682/2685/4682/4685 MASTER SSP I2CTM BUS START/STOP BITS TIMING WAVEFORMS FIGURE 27-18: SCL 93 91 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 27-4 for load conditions. TABLE 27-20: MASTER SSP I2CTM BUS START/STOP BITS REQUIREMENTS Param. Symbol No. 90 TSU:STA Characteristic Only relevant for Repeated Start condition ns After this period, the first clock pulse is generated Setup Time 400 kHz mode 2(TOSC)(BRG + 1) -- mode(1) 2(TOSC)(BRG + 1) -- 100 kHz mode 2(TOSC)(BRG + 1) -- 400 kHz mode 2(TOSC)(BRG + 1) -- 1 MHz mode(1) 2(TOSC)(BRG + 1) -- Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) -- Setup Time 400 kHz mode THD:STO Stop Condition Hold Time 2(TOSC)(BRG + 1) -- mode(1) 2(TOSC)(BRG + 1) -- 100 kHz mode 2(TOSC)(BRG + 1) -- 400 kHz mode 2(TOSC)(BRG + 1) -- 1 MHz mode(1) 2(TOSC)(BRG + 1) -- 2C Note 1: Maximum pin capacitance = 10 pF for all I FIGURE 27-19: ns -- 1 MHz 93 Conditions 2(TOSC)(BRG + 1) Hold Time 92 Units 100 kHz mode THD:STA Start Condition TSU:STO Max Start condition 1 MHz 91 Min ns ns pins. MASTER SSP I2CTM BUS DATA TIMING 103 102 100 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out Note: DS39761B-page 448 Refer to Figure 27-4 for load conditions. Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 27-21: MASTER SSP I2CTM BUS DATA REQUIREMENTS Param. Symbol No. 100 101 THIGH TLOW Characteristic Min Max Units 100 kHz mode 2(TOSC)(BRG + 1) -- ms 400 kHz mode 2(TOSC)(BRG + 1) -- ms 1 MHz mode(1) 2(TOSC)(BRG + 1) -- ms Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) -- ms 400 kHz mode 2(TOSC)(BRG + 1) -- ms (1) Clock High Time 2(TOSC)(BRG + 1) -- ms 100 kHz mode -- 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode(1) -- 300 ns 100 kHz mode -- 300 ns 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode(1) -- 100 ns 100 kHz mode 2(TOSC)(BRG + 1) -- ms 400 kHz mode 2(TOSC)(BRG + 1) -- ms 1 MHz mode(1) 2(TOSC)(BRG + 1) -- ms 1 MHz mode 102 103 90 91 TR TF TSU:STA SDA and SCL Rise Time SDA and SCL Fall Time Start Condition Setup Time THD:STA Start Condition Hold Time 100 kHz mode 2(TOSC)(BRG + 1) -- ms 400 kHz mode 2(TOSC)(BRG + 1) -- ms 1 MHz mode(1) 2(TOSC)(BRG + 1) -- ms 0 -- ns 106 THD:DAT Data Input Hold Time 100 kHz mode 400 kHz mode 0 0.9 ms 107 TSU:DAT 100 kHz mode 250 -- ns 400 kHz mode 100 -- ns 92 TSU:STO Stop Condition Setup Time 100 kHz mode 2(TOSC)(BRG + 1) -- ms 400 kHz mode 2(TOSC)(BRG + 1) -- ms 1 MHz mode(1) 2(TOSC)(BRG + 1) -- ms 100 kHz mode -- 3500 ns 400 kHz mode -- 1000 ns (1) -- -- ns 100 kHz mode 4.7 -- ms 400 kHz mode 1.3 -- ms -- 400 pF 109 TAA Data Input Setup Time Output Valid from Clock 1 MHz mode 110 D102 Note 1: 2: TBUF CB Bus Free Time Bus Capacitive Loading Conditions CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF Only relevant for Repeated Start condition After this period, the first clock pulse is generated (Note 2) Time the bus must be free before a new transmission can start 2C Maximum pin capacitance = 10 pF for all I pins. A Fast mode I2CTM bus device can be used in a Standard mode I2C bus system, but parameter 107 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, parameter 102 + parameter 107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the SCL line is released. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 449 PIC18F2682/2685/4682/4685 FIGURE 27-20: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 Note: 122 Refer to Figure 27-4 for load conditions. TABLE 27-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No. Symbol Characteristic TCKH2DTV SYNC XMIT (MASTER & SLAVE) Clock High to Data Out Valid 120 PIC18FXXXX Min Max Units -- 40 ns PIC18LFXXXX -- 100 ns 121 TCKRF Clock Out Rise Time and Fall Time (Master mode) PIC18FXXXX -- 20 ns PIC18LFXXXX -- 50 ns 122 TDTRF Data Out Rise Time and Fall Time PIC18FXXXX -- 20 ns PIC18LFXXXX -- 50 ns FIGURE 27-21: RC6/TX/CK pin Conditions VDD = 2.0V VDD = 2.0V VDD = 2.0V EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING 125 RC7/RX/DT pin 126 Note: Refer to Figure 27-4 for load conditions. TABLE 27-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Param. No. 125 126 Symbol Characteristic TDTV2CKL SYNC RCV (MASTER & SLAVE) Data Hold before CK (DT hold time) TCKL2DTL DS39761B-page 450 Data Hold after CK (DT hold time) Preliminary Min Max Units 10 -- ns 15 -- ns Conditions (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 27-24: A/D CONVERTER CHARACTERISTICS: PIC18F2682/2685/4682/4685 (INDUSTRIAL) PIC18LF2682/2685/4682/4685 (INDUSTRIAL) Param No. Sym Characteristic Min Typ Max Units -- -- 10 bit Conditions VREF 3.0V A01 NR Resolution A03 EIL Integral Linearity Error -- -- <1 LSb VREF 3.0V A04 EDL Differential Linearity Error -- -- <1 LSb VREF 3.0V A06 EOFF Offset Error -- -- <1 LSb VREF 3.0V A07 EGN Gain Error -- -- <1 LSb VREF 3.0V A10 -- A20 VREF Reference Voltage Range (VREFH - VREFL) Monotonicity Guaranteed A21 (1) -- 3 -- AVDD - AVSS V For 10-bit resolution VREFH Reference Voltage High AVSS + 3.0V -- AVDD + 0.3V V For 10-bit resolution A22 VREFL Reference Voltage Low AVSS - 0.3V -- AVDD - 3.0V V For 10-bit resolution A25 VAIN Analog Input Voltage VREFL -- VREFH V A28 AVDD Analog Supply Voltage VDD - 0.3 -- VDD + 0.3 V A29 AVSS Analog Supply Voltage VSS - 0.3 -- VSS + 0.3 V A30 ZAIN Recommended Impedance of Analog Voltage Source -- -- 2.5 k A40 IAD A/D Conversion PIC18FXXXX Current (VDD) -- 180 -- A Average current consumption when A/D is on (Note 2) -- 90 -- A VDD = 2.0V; average current consumption when A/D is on (Note 2) -- -- -- -- 5 150 A A During VAIN acquisition. During A/D conversion cycle. PIC18LFXXXX A50 IREF Note 1: 2: 3: VREF Input Current (Note 3) The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. VREFH current is from RA3/AN3/VREF+ pin or AVDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF- pin or AVSS, whichever is selected as the VREFL source. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 451 PIC18F2682/2685/4682/4685 FIGURE 27-22: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK(1) 132 9 A/D DATA 8 ... ... 7 2 1 0 NEW_DATA OLD_DATA ADRES TCY ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. TABLE 27-25: A/D CONVERSION REQUIREMENTS Param Symbol No. 130 TAD Characteristic A/D Clock Period Min Max Units Conditions PIC18FXXXX 0.7 25.0(1) s TOSC based, VREF 3.0V PIC18LFXXXX 1.4 25.0(1) s VDD = 2.0V; TOSC based, VREF full range PIC18FXXXX -- 1 s A/D RC mode VDD = 2.0V; A/D RC mode -- 3 s 131 TCNV Conversion Time (not including acquisition time) (Note 2) 11 12 TAD 132 TACQ Acquisition Time (Note 3) 1.4 -- s -40C to +85C 135 TSWC Switching Time from Convert Sample -- (Note 4) 136 TAMP Amplifier Settling Time (Note 5) 1 -- s This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 5 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). PIC18LFXXXX Note 1: 2: 3: 4: 5: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. ADRES register may be read on the following TCY cycle. The time for the holding capacitor to acquire the "New" input voltage when the voltage changes full scale after the conversion (AVDD to AVSS or AVSS to AVDD). The source impedance (RS) on the input channels is 50. On the following cycle of the device clock. See Section 19.0 "10-Bit Analog-to-Digital Converter (A/D) Module" for minimum conditions when input voltage has changed more than 1 LSb. DS39761B-page 452 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 28.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs and tables are not available at this time. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 453 PIC18F2682/2685/4682/4685 NOTES: DS39761B-page 454 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 29.0 PACKAGING INFORMATION 29.1 Package Marking Information 28-Lead PDIP (Skinny DIP) Example PIC18F2685-I/SP e3 0710017 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC Example PIC18F2685-E/SO e3 0710017 XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 40-Lead PDIP Example PIC18F4685-I/P e3 0710017 XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 455 PIC18F2682/2685/4682/4685 29.1 Package Marking Information (Continued) 44-Lead TQFP Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC18F4685 -I/PT e3 0710017 44-Lead QFN Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS39761B-page 456 PIC18F4685 -I/ML e3 0710017 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 29.2 Package Details The following sections give the technical details of the packages. 28-Lead Skinny Plastic Dual In-Line (SP) - 300 mil Body [SPDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 28 Pitch e Top to Seating Plane A - - .200 Molded Package Thickness A2 .120 .135 .150 Base to Seating Plane A1 .015 - - Shoulder to Shoulder Width E .290 .310 .335 Molded Package Width E1 .240 .285 .295 Overall Length D 1.345 1.365 1.400 Tip to Seating Plane L .110 .130 .150 Lead Thickness c .008 .010 .015 b1 .040 .050 .070 b .014 .018 .022 eB - - Upper Lead Width Lower Lead Width Overall Row Spacing .100 BSC .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-070B (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 457 PIC18F2682/2685/4682/4685 28-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 b e h A2 A h c L A1 Units Dimension Limits Number of Pins L1 MILLMETERS MIN N NOM MAX 28 Pitch e Overall Height A - 1.27 BSC - Molded Package Thickness A2 2.05 - - Standoff A1 0.10 - 0.30 Overall Width E Molded Package Width E1 7.50 BSC Overall Length D 17.90 BSC 2.65 10.30 BSC Chamfer (optional) h 0.25 - 0.75 Foot Length L 0.40 - 1.27 Footprint L1 1.40 REF Foot Angle Top 0 - 8 Lead Thickness c 0.18 - 0.33 Lead Width b 0.31 - 0.51 Mold Draft Angle Top 5 - 15 Mold Draft Angle Bottom 5 - 15 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-052B DS39761B-page 458 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 40-Lead Plastic Dual In-Line (P) - 600 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 40 Pitch e Top to Seating Plane A - - .250 Molded Package Thickness A2 .125 - .195 Base to Seating Plane A1 .015 - - Shoulder to Shoulder Width E .590 - .625 Molded Package Width E1 .485 - .580 Overall Length D 1.980 - 2.095 Tip to Seating Plane L .115 - .200 Lead Thickness c .008 - .015 b1 .030 - .070 b .014 - .023 eB - - Upper Lead Width Lower Lead Width Overall Row Spacing .100 BSC .700 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-016B (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 459 PIC18F2682/2685/4682/4685 44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 A c L A1 Units Dimension Limits Number of Leads A2 L1 MILLIMETERS MIN N NOM MAX 44 Lead Pitch e Overall Height A - 0.80 BSC - Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 - 0.15 Foot Length L 0.45 0.60 0.75 Footprint L1 1.20 1.00 REF Foot Angle Overall Width E 12.00 BSC Overall Length D 12.00 BSC Molded Package Width E1 10.00 BSC Molded Package Length D1 10.00 BSC 0 3.5 7 Lead Thickness c 0.09 - 0.20 Lead Width b 0.30 0.37 0.45 Mold Draft Angle Top 11 12 13 Mold Draft Angle Bottom 11 12 13 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-076B DS39761B-page 460 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D2 EXPOSED PAD e E E2 b 2 2 1 N 1 N NOTE 1 TOP VIEW K L BOTTOM VIEW A A3 A1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 44 Pitch e Overall Height A 0.80 0.65 BSC 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Width E Exposed Pad Width E2 Overall Length D Exposed Pad Length D2 6.30 6.45 6.80 b 0.25 0.30 0.38 Contact Length L 0.30 0.40 0.50 Contact-to-Exposed Pad K 0.20 - - Contact Width 8.00 BSC 6.30 6.45 6.80 8.00 BSC Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-103B (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 461 PIC18F2682/2685/4682/4685 NOTES: DS39761B-page 462 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 APPENDIX A: REVISION HISTORY Revision A (February 2006) Original data sheet for PIC18F2682/2685/4682/4685 devices. APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. Revision B (January 2007) Major edits to Section 27.0 "Electrical Characteristics". Packaging diagrams have been updated and minor edits to text have been made throughout document. TABLE B-1: DEVICE DIFFERENCES Features Program Memory (Bytes) Program Memory (Instructions) Interrupt Sources I/O Ports PIC18F2682 PIC18F2685 PIC18F4682 PIC18F4685 80K 96K 80K 96K 40960 49152 40960 49152 28 28 27 27 Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E Capture/Compare/PWM Modules 1 1 1 1 Enhanced Capture/Compare/ PWM Modules 0 0 1 1 No No Yes Yes 8 input channels 8 input channels 11 input channels 11 input channels 28-pin PDIP 28-pin SOIC 28-pin PDIP 28-pin SOIC 40-pin PDIP 44-pin TQFP 44-pin QFN 40-pin PDIP 44-pin TQFP 44-pin QFN Parallel Slave Port Communications (PSP) 10-Bit Analog-to-Digital Module Packages (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 463 PIC18F2682/2685/4682/4685 APPENDIX C: CONVERSION CONSIDERATIONS APPENDIX D: This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B. Not Applicable DS39761B-page 464 MIGRATION FROM BASELINE TO ENHANCED DEVICES This section discusses how to migrate from a Baseline device (i.e., PIC16C5X) to an Enhanced MCU device (i.e., PIC18FXXX). The following are the list of modifications over the PIC16C5X microcontroller family: Not Currently Available Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN716, "Migrating Designs from PIC16C74A/74B to PIC18C442." The changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations. APPENDIX F: MIGRATION FROM HIGH-END TO ENHANCED DEVICES A detailed discussion of the migration pathway and differences between the high-end MCU devices (i.e., PIC17CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN726, "PIC17CXXX to PIC18CXXX Migration." This Application Note is available as Literature Number DS00726. This Application Note is available as Literature Number DS00716. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 465 PIC18F2682/2685/4682/4685 NOTES: DS39761B-page 466 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 INDEX A A/D ................................................................................... 247 Acquisition Requirements ........................................ 252 ADCON0 Register .................................................... 247 ADCON1 Register .................................................... 247 ADCON2 Register .................................................... 247 ADRESH Register ............................................ 247, 250 ADRESL Register .................................................... 247 Analog Port Pins, Configuring .................................. 254 Associated Registers ............................................... 256 Automatic Acquisition Time ...................................... 253 Configuring the Module ............................................ 251 Conversion Clock (TAD) ........................................... 253 Conversion Requirements ....................................... 452 Conversion Status (GO/DONE Bit) .......................... 250 Conversions ............................................................. 255 Converter Characteristics ........................................ 451 Converter Interrupt, Configuring .............................. 251 Operation in Power-Managed Modes ...................... 254 Special Event Trigger (ECCP1) ....................... 174, 256 Use of the ECCP1 Trigger ....................................... 256 Absolute Maximum Ratings ............................................. 417 AC (Timing) Characteristics ............................................. 433 Load Conditions for Device Timing Specifications ....................................... 434 Parameter Symbology ............................................. 433 Temperature and Voltage Specifications ................. 434 Timing Conditions .................................................... 434 ACKSTAT ........................................................................ 217 ACKSTAT Status Flag ..................................................... 217 ADCON0 Register ............................................................ 247 GO/DONE Bit ........................................................... 250 ADCON1 Register ............................................................ 247 ADCON2 Register ............................................................ 247 ADDFSR .......................................................................... 406 ADDLW ............................................................................ 369 ADDULNK ........................................................................ 406 ADDWF ............................................................................ 369 ADDWFC ......................................................................... 370 ADRESH Register ............................................................ 247 ADRESL Register .................................................... 247, 250 Analog-to-Digital Converter. See A/D. ANDLW ............................................................................ 370 ANDWF ............................................................................ 371 Assembler MPASM Assembler .................................................. 414 B Baud Rate Generator ....................................................... 213 BC .................................................................................... 371 BCF .................................................................................. 372 BF .................................................................................... 217 BF Status Flag ................................................................. 217 Bit Timing Configuration Registers BRGCON1 ............................................................... 338 BRGCON2 ............................................................... 338 BRGCON3 ............................................................... 338 Block Diagrams A/D ........................................................................... 250 Analog Input Model .................................................. 251 Baud Rate Generator ............................................... 213 CAN Buffers and Protocol Engine ............................ 274 Capture Mode Operation ......................................... 166 (c) 2007 Microchip Technology Inc. Comparator Analog Input Model .............................. 261 Comparator I/O Operating Modes ........................... 258 Comparator Output .................................................. 260 Comparator Voltage Reference ............................... 264 Comparator Voltage Reference Output Buffer Example ................................................ 265 Compare Mode Operation ....................................... 167 Device Clock .............................................................. 28 Enhanced PWM ....................................................... 175 EUSART Receive .................................................... 238 EUSART Transmit ................................................... 236 External Power-on Reset Circuit (Slow VDD Power-up) ........................................ 43 Fail-Safe Clock Monitor ........................................... 356 Generic I/O Port Operation ...................................... 129 High/Low-Voltage Detect with External Input .......... 268 Interrupt Logic .......................................................... 114 MSSP (I2C Master Mode) ........................................ 211 MSSP (I2C Mode) .................................................... 196 MSSP (SPI Mode) ................................................... 187 On-Chip Reset Circuit ................................................ 41 PIC18F2682/2685 ..................................................... 10 PIC18F4682/4685 ..................................................... 11 PLL (HS Mode) .......................................................... 25 PORTD and PORTE (Parallel Slave Port) ............... 144 PWM Operation (Simplified) .................................... 169 Reads from Flash Program Memory ......................... 99 Single Comparator ................................................... 259 Table Read Operation ............................................... 95 Table Write Operation ............................................... 96 Table Writes to Flash Program Memory .................. 101 Timer0 in 16-Bit Mode ............................................. 148 Timer0 in 8-Bit Mode ............................................... 148 Timer1 ..................................................................... 152 Timer1 (16-Bit Read/Write Mode) ............................ 152 Timer2 ..................................................................... 158 Timer3 ..................................................................... 160 Timer3 (16-Bit Read/Write Mode) ............................ 160 Watchdog Timer ...................................................... 353 BN .................................................................................... 372 BNC ................................................................................. 373 BNN ................................................................................. 373 BNOV .............................................................................. 374 BNZ ................................................................................. 374 BOR. See Brown-out Reset. BOV ................................................................................. 377 BRA ................................................................................. 375 BRG. See Baud Rate Generator. Brown-out Reset (BOR) ..................................................... 44 Detecting ................................................................... 44 Disabling in Sleep Mode ............................................ 44 Software Enabled ...................................................... 44 BSF .................................................................................. 375 BTFSC ............................................................................. 376 BTFSS ............................................................................. 376 BTG ................................................................................. 377 BZ .................................................................................... 378 C C Compilers MPLAB C18 ............................................................. 414 MPLAB C30 ............................................................. 414 CALL ................................................................................ 378 CALLW ............................................................................ 407 Preliminary DS39761B-page 467 PIC18F2682/2685/4682/4685 Capture (CCP1 Module) ................................................... 165 Associated Registers ............................................... 168 CAN Message Time-Stamp ..................................... 165 CCP1 Pin Configuration ........................................... 165 CCPR1H:CCPR1L Registers ................................... 165 Prescaler .................................................................. 165 Software Interrupt .................................................... 165 Timer1/Timer3 Mode Selection ................................ 165 Capture (ECCP1 Module) ................................................ 174 Capture/Compare/PWM (CCP1) ...................................... 163 Capture Mode. See Capture. CCP1 Mode and Timer Resources .......................... 164 CCPR1H or ECCPR1H Register ............................. 164 CCPR1L or ECCPR1L Register ............................... 164 Compare Mode. See Compare. Interaction Between CCP1 and ECCP1 for Timer Resources ........................................ 164 Module Configuration ............................................... 164 Clock Sources .................................................................... 28 Effects of Power-Managed Modes ............................. 31 Selecting the 31 kHz Source ...................................... 29 Selection Using OSCCON Register ........................... 29 CLRF ................................................................................ 379 CLRWDT .......................................................................... 379 Code Examples 16 x 16 Signed Multiply Routine .............................. 112 16 x 16 Unsigned Multiply Routine .......................... 112 8 x 8 Signed Multiply Routine .................................. 111 8 x 8 Unsigned Multiply Routine .............................. 111 Changing Between Capture Prescalers ................... 165 Changing to Configuration Mode ............................. 278 Computed GOTO Using an Offset Value ................... 64 Data EEPROM Read ............................................... 107 Data EEPROM Refresh Routine .............................. 108 Data EEPROM Write ............................................... 107 Erasing a Flash Program Memory Row ................... 100 Fast Register Stack .................................................... 64 How to Clear RAM (Bank 1) Using Indirect Addressing ............................................ 88 Implementing a Real-Time Clock Using a Timer1 Interrupt Service ............................... 155 Initializing PORTA .................................................... 129 Initializing PORTB .................................................... 132 Initializing PORTC .................................................... 135 Initializing PORTD .................................................... 138 Initializing PORTE .................................................... 141 Loading the SSPBUF (SSPSR) Register ................. 190 Reading a CAN Message ........................................ 294 Reading a Flash Program Memory Word .................. 99 Saving STATUS, WREG and BSR Registers in RAM ............................................. 128 Transmitting a CAN Message Using Banked Method ................................................ 286 Transmitting a CAN Message Using WIN Bits ................................................. 287 WIN and ICODE Bits Usage in Interrupt Service Routine to Access TX/RX Buffers .................... 278 Writing to Flash Program Memory ................... 102-103 Code Protection ............................................................... 343 COMF ............................................................................... 380 DS39761B-page 468 Comparator ...................................................................... 257 Analog Input Connection Considerations ................ 261 Associated Registers ............................................... 261 Configuration ........................................................... 258 Effects of a Reset .................................................... 260 Interrupts ................................................................. 260 Operation ................................................................. 259 Operation During Sleep ........................................... 260 Outputs .................................................................... 259 Reference ................................................................ 259 External Signal ................................................ 259 Internal Signal .................................................. 259 Response Time ........................................................ 259 Comparator Specifications ............................................... 431 Comparator Voltage Reference ....................................... 263 Accuracy and Error .................................................. 264 Associated Registers ............................................... 265 Configuring .............................................................. 263 Connection Considerations ...................................... 264 Effects of a Reset .................................................... 264 Operation During Sleep ........................................... 264 Compare (CCP1 Module) ................................................ 167 Associated Registers ............................................... 168 CCP1 Pin Configuration ........................................... 167 CCPR1 Register ...................................................... 167 Software Interrupt .................................................... 167 Special Event Trigger .............................................. 167 Timer1/Timer3 Mode Selection ................................ 167 Compare (ECCP1 Module) .............................................. 174 Special Event Trigger .............................. 161, 174, 256 Configuration Bits ............................................................ 343 Configuration Mode ......................................................... 325 Configuration Register Protection ................................................................ 362 Context Saving During Interrupts ..................................... 128 Conversion Considerations .............................................. 464 CPFSEQ .......................................................................... 380 CPFSGT .......................................................................... 381 CPFSLT ........................................................................... 381 Crystal Oscillator/Ceramic Resonators .............................. 23 Customer Change Notification Service ............................ 478 Customer Notification Service ......................................... 478 Customer Support ............................................................ 478 D Data Addressing Modes .................................................... 88 Comparing Addressing Options with the Extended Instruction Set Enabled ..................... 92 Direct ......................................................................... 88 Indexed Literal Offset ................................................ 91 Affected Instructions .......................................... 91 BSR ................................................................... 93 Mapping the Access Bank ................................. 93 Indirect ....................................................................... 88 Inherent and Literal .................................................... 88 Data EEPROM Code Protection ....................................................... 362 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Data EEPROM Memory ................................................... 105 Associated Registers ............................................... 109 EEADR and EEADRH Registers ............................. 105 EECON1 and EECON2 Registers ........................... 105 Operation During Code-Protect ............................... 108 Protection Against Spurious Write ........................... 108 Reading .................................................................... 107 Use ........................................................................... 108 Write Verify .............................................................. 107 Writing ...................................................................... 107 Data Memory ..................................................................... 67 Access Bank .............................................................. 69 Bank Select Register (BSR) ....................................... 67 Extended Instruction Set ............................................ 91 General Purpose Register File ................................... 69 Map for PIC18F268X/468X ........................................ 68 Special Function Registers ........................................ 70 DAW ................................................................................. 382 DC and AC Characteristics .............................................. 453 DC Characteristics ........................................................... 428 Power-Down and Supply Current ............................ 420 Supply Voltage ......................................................... 419 DCFSNZ .......................................................................... 383 DECF ............................................................................... 382 DECFSZ ........................................................................... 383 Development Support ...................................................... 413 Device Differences ........................................................... 463 Device Overview .................................................................. 7 Features (table) ............................................................ 9 New Core Features ...................................................... 7 Device Reset Timers .......................................................... 45 Oscillator Start-up Timer (OST) ................................. 45 PLL Lock Time-out ..................................................... 45 Power-up Timer (PWRT) ........................................... 45 Direct Addressing ............................................................... 89 Disable Mode ................................................................... 325 E ECAN Technology ........................................................... 273 Baud Rate Setting .................................................... 333 Bit Time Partitioning ................................................. 333 Bit Timing Configuration Registers .......................... 338 Calculating TQ, Nominal Bit Rate and Nominal Bit Time ............................................. 336 CAN Interrupts ......................................................... 340 Acknowledge ................................................... 342 Bus Activity Wake-up ....................................... 342 Bus-Off ............................................................. 342 Code Bits ......................................................... 341 Error ................................................................. 342 Message Error ................................................. 341 Receive ............................................................ 341 Receiver Bus Passive ...................................... 342 Receiver Overflow ........................................... 342 Receiver Warning ............................................ 342 Transmit ........................................................... 341 Transmitter Bus Passive .................................. 342 Transmitter Warning ........................................ 342 CAN Message Buffers ............................................. 327 Dedicated Receive ........................................... 327 Dedicated Transmit .......................................... 327 Programmable Auto-RTR ................................ 328 Programmable Transmit/Receive .................... 327 (c) 2007 Microchip Technology Inc. CAN Message Transmission ................................... 328 Aborting ........................................................... 328 Initiating ........................................................... 328 Priority ............................................................. 329 CAN Modes of Operation ........................................ 325 CAN Registers ......................................................... 275 Baud Rate ....................................................... 312 Control and Status ........................................... 275 Controller Map ................................................. 320 Dedicated Receive Buffers .............................. 288 Dedicated Transmit Buffers ............................. 282 I/O Control ....................................................... 315 Interrupt ........................................................... 316 Configuration Mode ................................................. 325 Disable Mode ........................................................... 325 Error Detection ........................................................ 339 Acknowledge ................................................... 339 Bit .................................................................... 339 CRC ................................................................. 339 Error States ..................................................... 339 Form ................................................................ 339 Modes and Counters ....................................... 339 Stuff Bit ............................................................ 339 Error Modes State (diagram) ................................... 340 Error Recognition Mode ........................................... 326 Filter-Mask Truth (table) .......................................... 331 Functional Modes .................................................... 326 Mode 0 (Legacy Mode) .................................... 326 Mode 1 (Enhanced Legacy Mode) .................. 326 Mode 2 (Enhanced FIFO Mode) ...................... 327 Information Processing Time (IPT) .......................... 336 Lengthening a Bit Period ......................................... 337 Listen Only Mode ..................................................... 326 Loopback Mode ....................................................... 326 Message Acceptance Filters and Masks ......... 303, 331 Message Acceptance Mask and Filter Operation ................................................ 332 Message Reception ................................................. 330 Enhanced FIFO Mode ..................................... 331 Priority ............................................................. 330 Time-Stamping ................................................ 331 Normal Mode ........................................................... 325 Oscillator Tolerance ................................................. 338 Overview .................................................................. 273 Phase Buffer Segments ........................................... 336 Programmable TX/RX and Auto-RTR Buffers ............................................ 295 Programming Time Segments ................................. 338 Propagation Segment .............................................. 336 Sample Point ........................................................... 336 Shortening a Bit Period ............................................ 338 Synchronization ....................................................... 337 Hard ................................................................. 337 Resynchronization ........................................... 337 Rules ............................................................... 337 Synchronization Segment ........................................ 336 Time Quanta ............................................................ 336 Values for ICODE (table) ......................................... 341 Effect on Standard PIC Instructions ................................. 410 Electrical Characteristics ................................................. 417 Preliminary DS39761B-page 469 PIC18F2682/2685/4682/4685 Enhanced Capture/Compare/PWM (ECCP1) .................. 173 Associated Registers ............................................... 186 Capture and Compare Modes .................................. 174 Capture Mode. See Capture (ECCP1 Module). Outputs and Configuration ....................................... 174 Pin Configurations for ECCP1 ................................. 174 PWM Mode. See PWM (ECCP1 Module). Standard PWM Mode ............................................... 174 Timer Resources ...................................................... 174 Enhanced Universal Synchronous Receiver Transmitter (EUSART). See EUSART. Equations A/D Acquisition Time ................................................ 252 A/D Minimum Charging Time ................................... 252 Calculating the Minimum Required A/D Acquisition Time ........................................ 252 Errata ................................................................................... 5 Error Recognition Mode ................................................... 325 EUSART Asynchronous Mode ................................................ 236 Associated Registers, Receive ........................ 239 Associated Registers, Transmit ....................... 237 Auto-Wake-up on Sync Break Character ................................................. 240 Break Character Sequence .............................. 241 Receiver ........................................................... 238 Receiving a Break Character ........................... 241 Setting Up 9-Bit Mode with Address Detect ........................................ 238 Transmitter ....................................................... 236 Baud Rate Generator (BRG) .................................... 231 Associated Registers ....................................... 231 Auto-Baud Rate Detect .................................... 234 Baud Rate Error, Calculating ........................... 231 Baud Rates, Asynchronous Modes .................. 232 High Baud Rate Select (BRGH Bit) .................. 231 Operation in Power-Managed Modes .............. 231 Sampling .......................................................... 231 Synchronous Master Mode ...................................... 242 Associated Registers, Receive ........................ 244 Associated Registers, Transmit ....................... 243 Reception ......................................................... 244 Transmission .................................................... 242 Synchronous Slave Mode ........................................ 245 Associated Registers, Receive ........................ 246 Associated Registers, Transmit ....................... 245 Reception ......................................................... 246 Transmission .................................................... 245 Extended Instruction Set ADDFSR .................................................................. 406 ADDULNK ................................................................ 406 CALLW ..................................................................... 407 MOVSF .................................................................... 407 MOVSS .................................................................... 408 PUSHL ..................................................................... 408 SUBFSR .................................................................. 409 SUBULNK ................................................................ 409 External Clock Input ........................................................... 24 F Fail-Safe Clock Monitor ............................................ 343, 356 Exiting Operation ..................................................... 356 Interrupts in Power-Managed Modes ....................... 357 POR or Wake-up from Sleep ................................... 357 Watchdog Timer (WDT) ........................................... 356 DS39761B-page 470 Fast Register Stack ........................................................... 64 Firmware Instructions ...................................................... 363 Flash Program Memory ..................................................... 95 Associated Registers ............................................... 103 Control Registers ....................................................... 96 EECON1 ............................................................ 96 EECON2 ............................................................ 96 TABLAT ............................................................. 96 TABLAT (Table Latch) Register ........................ 98 TBLPTR ............................................................. 96 TBLPTR (Table Pointer) Register ...................... 98 Erase Sequence ...................................................... 100 Erasing .................................................................... 100 Operation During Code-Protect ............................... 103 Reading ..................................................................... 99 Table Pointer Boundaries Based on Operation ....................... 98 Table Pointer Boundaries .......................................... 98 Table Pointer Operations (table) ................................ 98 Table Reads and Table Writes .................................. 95 Write Sequence ....................................................... 101 Write Verify .............................................................. 103 Writing ..................................................................... 101 Protection Against Spurious Writes ................. 103 Unexpected Termination ................................. 103 FSCM. See Fail-Safe Clock Monitor. G GOTO .............................................................................. 384 H Hardware Multiplier .......................................................... 111 Introduction .............................................................. 111 Operation ................................................................. 111 Performance Comparison ........................................ 111 High/Low-Voltage Detect ................................................. 267 Associated Registers ............................................... 271 Characteristics ......................................................... 432 Current Consumption ............................................... 269 Effects of a Reset .................................................... 271 Operation ................................................................. 268 Operation During Sleep ........................................... 271 Setup ....................................................................... 269 Start-up Time ........................................................... 269 Typical Application ................................................... 270 HLVD. See High/Low-Voltage Detect. I I/O Ports ........................................................................... 129 I2C Mode (MSSP) Acknowledge Sequence Timing .............................. 220 Baud Rate Generator .............................................. 213 Bus Collision During a Repeated Start Condition .................. 224 During a Start Condition .................................. 222 During a Stop Condition .................................. 225 Clock Arbitration ...................................................... 214 Clock Stretching ....................................................... 206 10-Bit Slave Receive Mode (SEN = 1) ............ 206 10-Bit Slave Transmit Mode ............................ 206 7-Bit Slave Receive Mode (SEN = 1) .............. 206 7-Bit Slave Transmit Mode .............................. 206 Clock Synchronization and the CKP Bit ................... 207 Effect of a Reset ...................................................... 221 General Call Address Support ................................. 210 I2C Clock Rate w/BRG ............................................. 213 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Master Mode ............................................................ 211 Operation ......................................................... 212 Reception ......................................................... 217 Repeated Start Condition Timing ..................... 216 Start Condition ................................................. 215 Transmission ................................................... 217 Transmit Sequence .......................................... 212 Multi-Master Communication, Bus Collision and Arbitration ................................................. 221 Multi-Master Mode ................................................... 221 Operation ................................................................. 200 Read/Write Bit Information (R/W Bit) ............... 200, 201 Registers .................................................................. 196 Serial Clock (RC3/SCK/SCL) ................................... 201 Slave Mode .............................................................. 200 Addressing ....................................................... 200 Reception ......................................................... 201 Transmission ................................................... 201 Sleep Operation ....................................................... 221 Stop Condition Timing .............................................. 220 ID Locations ............................................................. 343, 362 INCF ................................................................................. 384 INCFSZ ............................................................................ 385 In-Circuit Debugger .......................................................... 362 In-Circuit Serial Programming (ICSP) ...................... 343, 362 Indexed Literal Offset Addressing Mode .......................... 410 and Standard PIC18 Instructions ............................. 410 Indirect Addressing ............................................................ 89 INFSNZ ............................................................................ 385 Initialization Conditions for All Registers ...................... 49-60 Instruction Cycle ................................................................ 65 Clocking Scheme ....................................................... 65 Flow/Pipelining ........................................................... 65 Instruction Set .................................................................. 363 ADDLW .................................................................... 369 ADDWF .................................................................... 369 ADDWF (Indexed Literal Offset Mode) .................... 411 ADDWFC ................................................................. 370 ANDLW .................................................................... 370 ANDWF .................................................................... 371 BC ............................................................................ 371 BCF .......................................................................... 372 BN ............................................................................ 372 BNC ......................................................................... 373 BNN ......................................................................... 373 BNOV ....................................................................... 374 BNZ .......................................................................... 374 BOV ......................................................................... 377 BRA .......................................................................... 375 BSF .......................................................................... 375 BSF (Indexed Literal Offset Mode) .......................... 411 BTFSC ..................................................................... 376 BTFSS ..................................................................... 376 BTG .......................................................................... 377 BZ ............................................................................ 378 CALL ........................................................................ 378 CLRF ........................................................................ 379 CLRWDT .................................................................. 379 COMF ...................................................................... 380 CPFSEQ .................................................................. 380 CPFSGT .................................................................. 381 CPFSLT ................................................................... 381 DAW ......................................................................... 382 DCFSNZ .................................................................. 383 (c) 2007 Microchip Technology Inc. DECF ....................................................................... 382 DECFSZ .................................................................. 383 Extended Instructions .............................................. 405 and Using MPLAB Tools ................................. 412 Considerations when Enabling ........................ 410 Syntax ............................................................. 405 General Format ....................................................... 365 GOTO ...................................................................... 384 INCF ........................................................................ 384 INCFSZ .................................................................... 385 INFSNZ .................................................................... 385 IORLW ..................................................................... 386 IORWF ..................................................................... 386 LFSR ....................................................................... 387 MOVF ...................................................................... 387 MOVFF .................................................................... 388 MOVLB .................................................................... 388 MOVLW ................................................................... 389 MOVWF ................................................................... 389 MULLW .................................................................... 390 MULWF ................................................................... 390 NEGF ....................................................................... 391 NOP ......................................................................... 391 Opcode Field Descriptions ...................................... 364 POP ......................................................................... 392 PUSH ....................................................................... 392 RCALL ..................................................................... 393 RESET ..................................................................... 393 RETFIE .................................................................... 394 RETLW .................................................................... 394 RETURN .................................................................. 395 RLCF ....................................................................... 395 RLNCF ..................................................................... 396 RRCF ....................................................................... 396 RRNCF .................................................................... 397 SETF ....................................................................... 397 SETF (Indexed Literal Offset Mode) ........................ 411 SLEEP ..................................................................... 398 Standard Instructions ............................................... 363 SUBFWB ................................................................. 398 SUBLW .................................................................... 399 SUBWF .................................................................... 399 SUBWFB ................................................................. 400 SWAPF .................................................................... 400 TBLRD ..................................................................... 401 TBLWT .................................................................... 402 TSTFSZ ................................................................... 403 XORLW ................................................................... 403 XORWF ................................................................... 404 Summary Table ....................................................... 366 INTCON Register RBIF Bit ................................................................... 132 INTCON Registers ........................................................... 115 Inter-Integrated Circuit. See I2C. Internal Oscillator Block ..................................................... 26 Adjustment ................................................................. 26 Frequency Drift .......................................................... 26 INTIO Modes ............................................................. 26 INTOSC Output Frequency ....................................... 26 OSCTUNE Register ................................................... 26 Internal RC Oscillator Use with WDT .......................................................... 353 Internet Address .............................................................. 478 Preliminary DS39761B-page 471 PIC18F2682/2685/4682/4685 Interrupt Sources .............................................................. 343 A/D Conversion Complete ....................................... 251 Capture Complete (CCP1) ....................................... 165 Compare Complete (CCP1) ..................................... 167 ECAN Module .......................................................... 340 Interrupt-on-Change (RB7:RB4) .............................. 132 INTx Pin ................................................................... 128 PORTB, Interrupt-on-Change .................................. 128 TMR0 ....................................................................... 128 TMR0 Overflow ........................................................ 149 TMR2 to PR2 Match (PWM) .................................... 169 TMR3 Overflow ........................................................ 161 Interrupts .......................................................................... 113 Interrupts, Flag Bits Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ......................................................... 132 INTOSC, INTRC. See Internal Oscillator Block. IORLW ............................................................................. 386 IORWF ............................................................................. 386 IPR Registers ................................................................... 124 L LFSR ................................................................................ 387 Listen Only Mode ............................................................. 325 Loopback Mode ................................................................ 325 Low-Voltage ICSP Programming. See Single-Supply ICSP Programming. M Master Clear Reset (MCLR) ............................................... 43 Master Synchronous Serial Port (MSSP). See MSSP. Memory Organization ......................................................... 61 Data Memory ............................................................. 67 Program Memory ....................................................... 61 Memory Programming Requirements .............................. 430 Microchip Internet Web Site ............................................. 478 Migration from Baseline to Enhanced Devices ................ 464 Migration from High-End to Enhanced Devices ............... 465 Migration from Mid-Range to Enhanced Devices ............. 465 MOVF ............................................................................... 387 MOVFF ............................................................................. 388 MOVLB ............................................................................. 388 MOVLW ............................................................................ 389 MOVSF ............................................................................ 407 MOVSS ............................................................................ 408 MOVWF ........................................................................... 389 MPLAB ASM30 Assembler, Linker, Librarian .................. 414 MPLAB ICD 2 In-Circuit Debugger ................................... 415 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator ................................... 415 MPLAB Integrated Development Environment Software .............................................. 413 MPLAB PM3 Device Programmer .................................... 415 MPLAB REAL ICE In-Circuit Emulator System ................ 415 MPLINK Object Linker/MPLIB Object Librarian ............... 414 MSSP ACK Pulse ........................................................ 200, 201 Control Registers (general) ...................................... 187 I2C Mode. See I2C Mode. Module Overview ..................................................... 187 SPI Master/Slave Connection .................................. 191 SSPBUF ................................................................... 192 SSPSR ..................................................................... 192 MULLW ............................................................................ 390 MULWF ............................................................................ 390 DS39761B-page 472 N NEGF ............................................................................... 391 NOP ................................................................................. 391 Normal Operation Mode .................................................. 325 O Oscillator Configuration ..................................................... 23 EC .............................................................................. 23 ECIO .......................................................................... 23 HS .............................................................................. 23 HSPLL ....................................................................... 23 Internal Oscillator Block ............................................. 26 INTIO1 ....................................................................... 23 INTIO2 ....................................................................... 23 LP .............................................................................. 23 RC ............................................................................. 23 RCIO .......................................................................... 23 XT .............................................................................. 23 Oscillator Selection .......................................................... 343 Oscillator Start-up Timer (OST) ................................... 31, 45 Oscillator Switching ........................................................... 28 Oscillator Transitions ......................................................... 29 Oscillator, Timer1 ............................................................. 161 Oscillator, Timer3 ..................................................... 151, 159 P Packaging Information ..................................................... 455 Details ...................................................................... 457 Marking .................................................................... 455 Parallel Slave Port (PSP) ................................................. 144 Associated Registers ............................................... 145 CS (Chip Select) ...................................................... 144 PORTD .................................................................... 144 RD (Read Input) ....................................................... 144 Select (PSPMODE Bit) .................................... 138, 144 WR (Write Input) ...................................................... 144 PICSTART Plus Development Programmer .................... 416 PIE Registers ................................................................... 121 Pin Functions MCLR/VPP/RE3 ................................................... 12, 16 OSC1/CLKI/RA7 .................................................. 12, 16 OSC2/CLKO/RA6 ................................................ 12, 16 RA0/AN0 .................................................................... 13 RA0/AN0/CVREF ........................................................ 17 RA1/AN1 .............................................................. 13, 17 RA2/AN2/VREF- ................................................... 13, 17 RA3/AN3/VREF+ .................................................. 13, 17 RA4/T0CKI .......................................................... 13, 17 RA5/AN4/SS/HLVDIN .......................................... 13, 17 RB0/INT0/AN10 ......................................................... 14 RB0/INT0/FLT0/AN10 ................................................ 18 RB1/INT1/AN8 ..................................................... 14, 18 RB2/INT2/CANTX ................................................ 14, 18 RB3/CANRX ........................................................ 14, 18 RB4/KBI0/AN9 ..................................................... 14, 18 RB5/KBI1/PGM .................................................... 14, 18 RB6/KBI2/PGC .................................................... 14, 18 RB7/KBI3/PGD .................................................... 14, 18 RC0/T1OSO/T13CKI ........................................... 15, 19 RC1/T1OSI .......................................................... 15, 19 RC2/CCP1 ........................................................... 15, 19 RC3/SCK/SCL ..................................................... 15, 19 RC4/SDI/SDA ...................................................... 15, 19 RC5/SDO ............................................................. 15, 19 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 RC6/TX/CK .......................................................... 15, 19 RC7/RX/DT .......................................................... 15, 19 RD0/PSP0/C1IN+ ...................................................... 20 RD1/PSP1/C1IN- ....................................................... 20 RD2/PSP2/C2IN+ ...................................................... 20 RD3/PSP3/C2IN- ....................................................... 20 RD4/PSP4/ECCP1/P1A ............................................. 20 RD5/PSP5/P1B .......................................................... 20 RD6/PSP6/P1C .......................................................... 20 RD7/PSP7/P1D .......................................................... 20 RE0/RD/AN5 .............................................................. 21 RE1/WR/AN6/C1OUT ................................................ 21 RE2/CS/AN7/C2OUT ................................................. 21 VDD ...................................................................... 15, 21 VSS ....................................................................... 15, 21 Pinout I/O Descriptions PIC18F2682/2685 ...................................................... 12 PIC18F4682/4685 ...................................................... 16 PIR Registers ................................................................... 118 PLL Frequency Multiplier ................................................... 25 HSPLL Oscillator Mode .............................................. 25 INTOSC Modes .......................................................... 26 Use with INTOSC ....................................................... 25 PLL Lock Time-out ............................................................. 45 POP ................................................................................. 392 POR. See Power-on Reset. PORTA Associated Registers ............................................... 131 I/O Summary ............................................................ 130 LATA Register .......................................................... 129 PORTA Register ...................................................... 129 TRISA Register ........................................................ 129 PORTB Associated Registers ............................................... 134 I/O Summary ............................................................ 133 LATB Register .......................................................... 132 PORTB Register ...................................................... 132 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ......................................................... 132 TRISB Register ........................................................ 132 PORTC Associated Registers ............................................... 137 I/O Summary ............................................................ 136 LATC Register ......................................................... 135 PORTC Register ...................................................... 135 RC3/SCK/SCL Pin ................................................... 201 TRISC Register ........................................................ 135 PORTD Associated Registers ............................................... 140 I/O Summary ............................................................ 139 LATD Register ......................................................... 138 Parallel Slave Port (PSP) Function .......................... 138 PORTD Register ...................................................... 138 TRISD Register ........................................................ 138 PORTE Associated Registers ............................................... 143 I/O Summary ............................................................ 143 LATE Register .......................................................... 141 PORTE Register ...................................................... 141 PSP Mode Select (PSPMODE Bit) .......................... 138 TRISE Register ........................................................ 141 Postscaler, WDT Assignment (PSA Bit) .............................................. 149 Rate Select (T0PS2:T0PS0 Bits) ............................. 149 Switching Between Timer0 and WDT ...................... 149 (c) 2007 Microchip Technology Inc. Power-Managed Modes ..................................................... 33 Clock Sources ........................................................... 33 Clock Transitions and Status Indicators .................... 34 Entering ..................................................................... 33 Exiting Idle and Sleep Modes .................................... 39 By Interrupt ........................................................ 39 By Reset ............................................................ 39 By WDT Time-out .............................................. 39 Without an Oscillator Start-up Delay ................. 40 Idle Modes ................................................................. 37 PRI_IDLE .......................................................... 38 RC_IDLE ........................................................... 39 SEC_IDLE ......................................................... 38 Multiple Sleep Commands ......................................... 34 Run Modes ................................................................ 34 PRI_RUN ........................................................... 34 RC_RUN ............................................................ 35 SEC_RUN ......................................................... 34 Selecting .................................................................... 33 Sleep Mode ............................................................... 37 Summary (table) ........................................................ 33 Power-on Reset (POR) ...................................................... 43 Power-up Timer (PWRT) ........................................... 45 Time-out Sequence ................................................... 45 Power-up Delays ............................................................... 31 Power-up Timer (PWRT) ............................................. 31, 45 Prescaler Timer2 ..................................................................... 176 Prescaler, Timer0 ............................................................ 149 Assignment (PSA Bit) .............................................. 149 Rate Select (T0PS2:T0PS0 Bits) ............................. 149 Switching Between Timer0 and WDT ...................... 149 Prescaler, Timer2 ............................................................ 170 PRI_IDLE Mode ................................................................. 38 PRI_RUN Mode ................................................................. 34 Program Counter ............................................................... 62 PCL, PCH and PCU Registers .................................. 62 PCLATH and PCLATU Registers .............................. 62 Program Memory Code Protection ....................................................... 359 Extended Instruction Set ........................................... 91 Instructions ................................................................ 66 Two-Word .......................................................... 66 Interrupt Vector .......................................................... 61 Look-up Tables .......................................................... 64 Map and Stack (diagram) .......................................... 61 Reset Vector .............................................................. 61 Program Verification and Code Protection ...................... 358 Associated Registers ............................................... 359 Programming, Device Instructions ................................... 363 PSP. See Parallel Slave Port. Pulse-Width Modulation. See PWM (CCP1/ECCP1 Modules). PUSH ............................................................................... 392 PUSH and POP Instructions .............................................. 63 PUSHL ............................................................................. 408 PWM (CCP1 Module) Associated Registers ............................................... 171 CCPR1H:CCPR1L Registers .................................. 169 Duty Cycle ............................................................... 169 Example Frequencies/Resolutions .......................... 170 Period ...................................................................... 169 Setup for PWM Operation ....................................... 170 TMR2 to PR2 Match ................................................ 169 Preliminary DS39761B-page 473 PIC18F2682/2685/4682/4685 PWM (ECCP1 Module) .................................................... 175 Auto-Shutdown ........................................................ 170 Direction Change in Full-Bridge Output Mode .................................................... 180 Duty Cycle ................................................................ 176 ECCPR1H:ECCPR1L Registers .............................. 175 Effects of a Reset ..................................................... 185 Enhanced Mode ....................................................... 175 Enhanced PWM Auto-Shutdown ............................. 182 Example Frequencies/Resolutions .......................... 176 Full-Bridge Application Example .............................. 180 Full-Bridge Mode ...................................................... 179 Half-Bridge Mode ..................................................... 178 Half-Bridge Output Mode Applications Example ........................................................... 178 Output Configurations .............................................. 176 Output Relationships (Active-High) .......................... 177 Output Relationships (Active-Low) ........................... 177 Period ....................................................................... 175 Programmable Dead-Band Delay ............................ 182 Setup ........................................................................ 185 Start-up Considerations ........................................... 184 TMR2 to PR2 Match ................................................ 175 Q Q Clock .................................................................... 170, 176 R RAM. See Data Memory. RC Oscillator ...................................................................... 25 RCIO Oscillator Mode ................................................ 25 RC_IDLE Mode .................................................................. 39 RC_RUN Mode .................................................................. 35 RCALL .............................................................................. 393 RCON Register Bit Status During Initialization .................................... 48 Reader Response ............................................................ 479 Register File Summary ................................................. 76-86 Registers ADCON0 (A/D Control 0) ......................................... 247 ADCON1 (A/D Control 1) ......................................... 248 ADCON2 (A/D Control 2) ......................................... 249 BAUDCON (Baud Rate Control) .............................. 230 BIE0 (Buffer Interrupt Enable 0) ............................... 319 BnCON (TX/RX Buffer n Control, Receive Mode) ................................................. 295 BnCON (TX/RX Buffer n Control, Transmit Mode) ................................................ 296 BnDLC (TX/RX Buffer n Data Length Code in Receive Mode) ............................................. 301 BnDLC (TX/RX Buffer n Data Length Code in Transmit Mode) ............................................ 302 BnDm (TX/RX Buffer n Data Field Byte m in Receive Mode) ............................................. 300 BnDm (TX/RX Buffer n Data Field Byte m in Transmit Mode) ............................................ 300 BnEIDH (TX/RX Buffer n Extended Identifier, High Byte in Receive Mode) ............................ 299 BnEIDH (TX/RX Buffer n Extended Identifier, High Byte in Transmit Mode) ........................... 299 BnEIDL (TX/RX Buffer n Extended Identifier, Low Byte in Receive Mode) ..................... 299, 300 BnSIDH (TX/RX Buffer n Standard Identifier, High Byte in Receive Mode) ............................ 297 BnSIDH (TX/RX Buffer n Standard Identifier, High Byte in Transmit Mode) ........................... 297 DS39761B-page 474 Preliminary BnSIDL (TX/RX Buffer n Standard Identifier, Low Byte in Receive Mode) ............................. 298 BRGCON1 (Baud Rate Control 1) ........................... 312 BRGCON2 (Baud Rate Control 2) ........................... 313 BRGCON3 (Baud Rate Control 3) ........................... 314 BSEL0 (Buffer Select 0) ........................................... 302 CCP1CON (Capture/Compare/PWM Control) ......... 163 CIOCON (CAN I/O Control) ..................................... 315 CMCON (Comparator Control) ................................ 257 COMSTAT (CAN Communication Status) ............... 281 CONFIG1H (Configuration 1 High) .......................... 344 CONFIG2H (Configuration 2 High) .......................... 346 CONFIG2L (Configuration 2 Low) ........................... 345 CONFIG3H (Configuration 3 High) .......................... 347 CONFIG4L (Configuration 4 Low) ........................... 347 CONFIG5H (Configuration 5 High) .......................... 348 CONFIG5L (Configuration 5 Low) ........................... 348 CONFIG6H (Configuration 6 High) .......................... 350 CONFIG6L (Configuration 6 Low) ........................... 349 CONFIG7H (Configuration 7 High) .......................... 351 CONFIG7L (Configuration 7 Low) ........................... 351 CVRCON (Comparator Voltage Reference Control) .......................................... 263 DEVID1 (Device ID 1) .............................................. 352 DEVID2 (Device ID 2) .............................................. 352 ECANCON (Enhanced CAN Control) ...................... 280 ECCP1AS (Enhanced Capture/Compare/PWM Auto-Shutdown Configuration) ........................ 183 ECCP1CON (Enhanced Capture/Compare/PWM Control) .................... 173 ECCP1DEL (PWM Dead-Band Delay) .................... 182 EECON1 (Data EEPROM Control 1) ................. 97, 106 HLVDCON (High/Low-Voltage Detect Control) ................................................ 267 INTCON (Interrupt Control) ...................................... 115 INTCON2 (Interrupt Control 2) ................................. 116 INTCON3 (Interrupt Control 3) ................................. 117 IPR1 (Peripheral Interrupt Priority 1) ....................... 124 IPR2 (Peripheral Interrupt Priority 2) ....................... 125 IPR3 (Peripheral Interrupt Priority 3) ............... 126, 318 MSEL0 (Mask Select 0) ........................................... 308 MSEL1 (Mask Select 1) ........................................... 309 MSEL2 (Mask Select 2) ........................................... 310 MSEL3 (Mask Select 3) ........................................... 311 OSCCON (Oscillator Control) .................................... 30 OSCTUNE (Oscillator Tuning) ................................... 27 PIE1 (Peripheral Interrupt Enable 1) ........................ 121 PIE2 (Peripheral Interrupt Enable 2) ........................ 122 PIE3 (Peripheral Interrupt Enable 3) ................ 123, 317 PIR1 (Peripheral Interrupt Request (Flag) 1) ............................................. 118 PIR2 (Peripheral Interrupt Request (Flag) 2) ............................................. 119 PIR3 (Peripheral Interrupt Request (Flag) 3) ..................................... 120, 316 RCON (Reset Control) ....................................... 42, 127 RCSTA (Receive Status and Control) ..................... 229 RXB0CON (Receive Buffer 0 Control) ..................... 288 RXB1CON (Receive Buffer 1 Control) ..................... 290 RXBnDLC (Receive Buffer n Data Length Code) .......................................... 293 RXBnDm (Receive Buffer n Data Field Byte m) ........................................... 293 RXBnEIDH (Receive Buffer n Extended Identifier, High Byte) ........................ 292 (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 RXBnEIDL (Receive Buffer n Extended Identifier, Low Byte) ......................... 292 RXBnSIDH (Receive Buffer n Standard Identifier, High Byte) ......................... 291 RXBnSIDL (Receive Buffer n Standard Identifier, Low Byte) ......................... 292 RXERRCNT (Receive Error Count) ......................... 294 RXFBCONn (Receive Filter Buffer Control n) .......... 307 RXFCONn (Receive Filter Control n) ....................... 306 RXFnEIDH (Receive Acceptance Filter n Extended Identifier, High Byte) ........................ 304 RXFnEIDL (Receive Acceptance Filter n Extended Identifier, Low Byte) ......................... 304 RXFnSIDH (Receive Acceptance Filter n Standard Identifier Filter, High Byte) ................ 303 RXFnSIDL (Receive Acceptance Filter n Standard Identifier Filter, Low Byte) ................ 303 RXMnEIDH (Receive Acceptance Mask n Extended Identifier Mask, High Byte) .............. 305 RXMnEIDL (Receive Acceptance Mask n Extended Identifier Mask, Low Byte) ............... 305 RXMnSIDH (Receive Acceptance Mask n Standard Identifier Mask, High Byte) ............... 304 RXMnSIDL (Receive Acceptance Mask n Standard Identifier Mask, Low Byte) ................ 305 SDFLC (Standard Data Bytes Filter Length Count) .................................................. 306 SSPCON1 (MSSP Control 1, I2C Mode) ................. 198 SSPCON1 (MSSP Control 1, SPI Mode) ................. 189 SSPCON2 (MSSP Control 2, I2C Mode) ................. 199 SSPSTAT (MSSP Status, I2C Mode) ....................... 197 SSPSTAT (MSSP Status, SPI Mode) ...................... 188 STATUS ..................................................................... 87 STKPTR (Stack Pointer) ............................................ 63 T0CON (Timer0 Control) .......................................... 147 T1CON (Timer1 Control) .......................................... 151 T2CON (Timer2 Control) .......................................... 157 T3CON (Timer3 Control) .......................................... 159 TRISE (PORTE/PSP Control) .................................. 142 TXBIE (Transmit Buffers Interrupt Enable) .............. 319 TXBnCON (Transmit Buffer n Control) .................... 282 TXBnDLC (Transmit Buffer n Data Length Code) .......................................... 285 TXBnDm (Transmit Buffer n Data Field Byte m) ........................................... 284 TXBnEIDH (Transmit Buffer n Extended Identifier, High Byte) ........................ 283 TXBnEIDL (Transmit Buffer n Extended Identifier, Low Byte) ......................... 284 TXBnSIDH (Transmit Buffer n Standard Identifier, High Byte) ......................... 283 TXBnSIDL (Transmit Buffer n Standard Identifier, Low Byte) ......................... 283 TXERRCNT (Transmit Error Count) ........................ 285 TXSTA (Transmit Status and Control) ..................... 228 WDTCON (Watchdog Timer Control) ...................... 354 RESET ............................................................................. 393 Resets ........................................................................ 41, 343 Brown-out Reset (BOR) ........................................... 343 Oscillator Start-up Timer (OST) ............................... 343 Power-on Reset (POR) ............................................ 343 Power-up Timer (PWRT) ......................................... 343 RETFIE ............................................................................ 394 RETLW ............................................................................ 394 RETURN .......................................................................... 395 (c) 2007 Microchip Technology Inc. Return Address Stack ........................................................ 62 Associated Registers ................................................. 62 Return Stack Pointer (STKPTR) ........................................ 63 Revision History ............................................................... 463 RLCF ............................................................................... 395 RLNCF ............................................................................. 396 RRCF ............................................................................... 396 RRNCF ............................................................................ 397 S SCK ................................................................................. 187 SDI ................................................................................... 187 SDO ................................................................................. 187 SEC_IDLE Mode ............................................................... 38 SEC_RUN Mode ................................................................ 34 Serial Clock, SCK ............................................................ 187 Serial Data In (SDI) .......................................................... 187 Serial Data Out (SDO) ..................................................... 187 Serial Peripheral Interface. See SPI Mode. SETF ............................................................................... 397 Slave Select (SS) ............................................................. 187 SLEEP ............................................................................. 398 Sleep OSC1 and OSC2 Pin States ...................................... 31 Software Simulator (MPLAB SIM) ................................... 414 Special Event Trigger. See Compare (CCP1/ECCP1 Modules). Special Event Trigger. See Compare (ECCP1 Module). Special Function Registers Map ...................................................................... 70-75 SPI Mode (MSSP) ........................................................... 187 Associated Registers ............................................... 195 Bus Mode Compatibility ........................................... 195 Effects of a Reset .................................................... 195 Enabling SPI I/O ...................................................... 191 Master Mode ............................................................ 192 Master/Slave Connection ........................................ 191 Operation ................................................................. 190 Operation in Power-Managed Modes ...................... 195 Serial Clock ............................................................. 187 Serial Data In ........................................................... 187 Serial Data Out ........................................................ 187 Slave Mode .............................................................. 193 Slave Select ............................................................. 187 Slave Select Synchronization .................................. 193 SPI Clock ................................................................. 192 Typical Connection .................................................. 191 SS .................................................................................... 187 SSPOV ............................................................................ 217 SSPOV Status Flag ......................................................... 217 SSPSTAT Register R/W Bit ............................................................ 200, 201 Stack Full/Underflow Resets .............................................. 64 Status Register .................................................................. 87 SUBFSR .......................................................................... 409 SUBFWB ......................................................................... 398 SUBLW ............................................................................ 399 SUBULNK ........................................................................ 409 SUBWF ............................................................................ 399 SUBWFB ......................................................................... 400 SWAPF ............................................................................ 400 Preliminary DS39761B-page 475 PIC18F2682/2685/4682/4685 T T0CON Register PSA Bit ..................................................................... 149 T0CS Bit ................................................................... 148 T0PS2:T0PS0 Bits ................................................... 149 T0SE Bit ................................................................... 148 Table Reads/Table Writes .................................................. 64 TBLRD ............................................................................. 401 TBLWT ............................................................................. 402 Time-out in Various Situations (table) ................................ 45 Timer0 .............................................................................. 147 Associated Registers ............................................... 149 Clock Source Edge Select (T0SE Bit) ...................... 148 Clock Source Select (T0CS Bit) ............................... 148 Operation ................................................................. 148 Overflow Interrupt .................................................... 149 Prescaler. See Prescaler, Timer0. Reads and Writes in 16-Bit Mode ............................ 148 Timer1 .............................................................................. 151 16-Bit Read/Write Mode ........................................... 153 Associated Registers ............................................... 155 Interrupt .................................................................... 154 Operation ................................................................. 152 Oscillator .................................................................. 153 Layout Considerations ..................................... 154 Resetting, Using a Special Event Trigger Output (CCP1) ..................................... 154 Special Event Trigger (ECCP1) ............................... 174 Use as a Real-Time Clock ....................................... 154 Timer2 .............................................................................. 157 Associated Registers ............................................... 158 Interrupt .................................................................... 158 Operation ................................................................. 157 Output ...................................................................... 158 PR2 Register .................................................... 169, 175 TMR2 to PR2 Match Interrupt .................................. 169 Timer3 .............................................................................. 159 16-Bit Read/Write Mode ........................................... 161 Associated Registers ............................................... 161 Operation ................................................................. 160 Oscillator .................................................. 151, 159, 161 Overflow Interrupt .................................................... 161 Special Event Trigger (ECCP1) ............................... 161 TMR3H Register .............................................. 151, 159 TMR3L Register ............................................... 151, 159 Timing Diagrams A/D Conversion ........................................................ 452 Acknowledge Sequence .......................................... 220 Asynchronous Reception ......................................... 239 Asynchronous Transmission .................................... 237 Asynchronous Transmission (Back-to-Back) ................................................. 237 Automatic Baud Rate Calculation ............................ 235 Auto-Wake-up Bit (WUE) During Normal Operation ............................................. 240 Auto-Wake-up Bit (WUE) During Sleep ................... 240 Baud Rate Generator with Clock Arbitration ............ 214 BRG Overflow Sequence ......................................... 235 BRG Reset Due to SDA Arbitration During Start Condition ...................................... 223 Brown-out Reset (BOR) ........................................... 438 Bus Collision During a Repeated Start Condition (Case 1) .................................. 224 Bus Collision During a Repeated Start Condition (Case 2) .................................. 224 DS39761B-page 476 Preliminary Bus Collision During a Start Condition (SCL = 0) ......................................................... 223 Bus Collision During a Start Condition (SDA Only) ...................................................... 222 Bus Collision During a Stop Condition (Case 1) ........................................................... 225 Bus Collision During a Stop Condition (Case 2) ........................................................... 225 Bus Collision for Transmit and Acknowledge ................................................... 221 Capture/Compare/PWM (All CCP Modules) ............ 440 CLKO and I/O .......................................................... 437 Clock Synchronization ............................................. 207 Clock/Instruction Cycle .............................................. 65 EUSART Synchronous Receive (Master/Slave) ................................................. 450 EUSART Synchronous Transmission (Master/Slave) ................................................. 450 Example SPI Master Mode (CKE = 0) ..................... 442 Example SPI Master Mode (CKE = 1) ..................... 443 Example SPI Slave Mode (CKE = 0) ....................... 444 Example SPI Slave Mode (CKE = 1) ....................... 445 External Clock (All Modes Except PLL) ................... 435 Fail-Safe Clock Monitor ........................................... 357 First Start Bit Timing ................................................ 215 Full-Bridge PWM Output .......................................... 179 Half-Bridge PWM Output ......................................... 178 High/Low-Voltage Detect Characteristics ................ 432 High-Voltage Detect (VDIRMAG = 1) ...................... 270 I2C Bus Data ............................................................ 446 I2C Bus Start/Stop Bits ............................................ 446 I2C Master Mode (7 or 10-Bit Transmission) ........... 218 I2C Master Mode (7-Bit Reception) .......................... 219 I2C Slave Mode (10-Bit Reception, SEN = 0) .......... 204 I2C Slave Mode (10-Bit Reception, SEN = 1) .......... 209 I2C Slave Mode (10-Bit Transmission) .................... 205 I2C Slave Mode (7-Bit Reception, SEN = 0) ............ 202 I2C Slave Mode (7-Bit Reception, SEN = 1) ............ 208 I2C Slave Mode (7-Bit Transmission) ...................... 203 I2C Slave Mode General Call Address Sequence (7 or 10-Bit Address Mode) ............ 210 Low-Voltage Detect (VDIRMAG = 0) ....................... 269 Master SSP I2C Bus Data ........................................ 448 Master SSP I2C Bus Start/Stop Bits ........................ 448 Parallel Slave Port (PIC18F4682/4685) ................... 441 Parallel Slave Port (PSP) Read ............................... 145 Parallel Slave Port (PSP) Write ............................... 145 PWM Auto-Shutdown (PRSEN = 0, Auto-Restart Disabled) .................................... 184 PWM Auto-Shutdown (PRSEN = 1, Auto-Restart Enabled) ..................................... 184 PWM Direction Change ........................................... 181 PWM Direction Change at Near 100% Duty Cycle ............................................. 181 PWM Output ............................................................ 169 Repeated Start Condition ........................................ 216 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) ................................................. 438 Send Break Character Sequence ............................ 241 Slave Synchronization ............................................. 193 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) ............................................ 47 SPI Mode (Master Mode) ......................................... 192 SPI Mode (Slave Mode with CKE = 0) ..................... 194 (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 SPI Mode (Slave Mode with CKE = 1) ..................... 194 Stop Condition Receive or Transmit Mode .............. 220 Synchronous Reception (Master Mode, SREN) ..................................... 244 Synchronous Transmission ...................................... 242 Synchronous Transmission (Through TXEN) .............................................. 243 Time-out Sequence on POR w/PLL Enabled (MCLR Tied to VDD) ............................. 47 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 1 ....................... 46 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 2 ....................... 46 Time-out Sequence on Power-up (MCLR Tied to VDD, VDD Rise Tpwrt) ................ 46 Timer0 and Timer1 External Clock .......................... 439 Transition for Entry to Idle Mode ................................ 38 Transition for Entry to SEC_RUN Mode .................... 35 Transition for Entry to Sleep Mode ............................ 37 Transition for Two-Speed Start-up (INTOSC to HSPLL) ........................................ 355 Transition for Wake From Idle to Run Mode ..................................................... 38 Transition for Wake From Sleep (HSPLL) ................. 37 Transition From RC_RUN Mode to PRI_RUN Mode ............................................. 36 Transition From SEC_RUN Mode to PRI_RUN Mode (HSPLL) .............................. 35 Transition to RC_RUN Mode ..................................... 36 Timing Diagrams and Specifications ................................ 435 AC Characteristics Internal RC Accuracy ....................................... 436 Capture/Compare/PWM Requirements (All CCP Modules) ........................................... 440 CLKO and I/O Requirements ................................... 437 EUSART Synchronous Receive Requirements .................................................. 450 EUSART Synchronous Transmission Requirements .................................................. 450 Example SPI Mode Requirements (Master Mode, CKE = 0) .................................. 442 Example SPI Mode Requirements (Master Mode, CKE = 1) .................................. 443 Example SPI Mode Requirements (Slave Mode, CKE = 0) .................................... 444 (c) 2007 Microchip Technology Inc. Example SPI Mode Requirements (Slave Mode, CKE = 1) .................................... 445 External Clock Requirements .................................. 435 I2C Bus Data Requirements (Slave Mode) .............. 447 I2C Bus Start/Stop Bits Requirements (Slave Mode) ................................................... 446 Master SSP I2C Bus Data Requirements ................ 449 Master SSP I2C Bus Start/Stop Bits Requirements .................................................. 448 Parallel Slave Port Requirements (PIC18F4682/4685) ......................................... 441 PLL Clock ................................................................ 436 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ........................................ 438 Timer0 and Timer1 External Clock Requirements ........................................ 439 Top-of-Stack Access .......................................................... 62 TRISE Register PSPMODE Bit ......................................................... 138 TSTFSZ ........................................................................... 403 Two-Speed Start-up ................................................. 343, 355 Two-Word Instructions Example Cases ......................................................... 66 TXSTA Register BRGH Bit ................................................................. 231 V Voltage Reference Specifications .................................... 431 W Watchdog Timer (WDT) ........................................... 343, 353 Associated Registers ............................................... 354 Control Register ....................................................... 353 Programming Considerations .................................. 353 WCOL ...................................................... 215, 216, 217, 220 WCOL Status Flag ................................... 215, 216, 217, 220 WWW Address ................................................................ 478 WWW, On-Line Support ...................................................... 5 X XORLW ........................................................................... 403 XORWF ........................................................................... 404 Preliminary DS39761B-page 477 PIC18F2682/2685/4682/4685 NOTES: DS39761B-page 478 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 479 PIC18F2682/2685/4682/4685 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC18F2682/2685/4682/4685 Literature Number: DS39761B Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39761B-page 480 Preliminary (c) 2007 Microchip Technology Inc. PIC18F2682/2685/4682/4685 PIC18F2682/2685/4682/4685 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device PIC18F2682/2685(1), PIC18F4682/4685(1), PIC18F2682/2685T(2), PIC18F4682/4685T(2); VDD range 4.2V to 5.5V PIC18LF2682/2685(1), PIC18LF4682/4685(1), PIC18LF2682/2685T(2), PIC18LF4682/4685T(2); VDD range 2.0V to 5.5V Temperature Range I = -40C to +85C (Industrial) Package PT SO SP P ML = = = = = TQFP (Thin Quad Flatpack) SOIC Skinny Plastic DIP PDIP QFN Pattern c) PIC18LF4685-I/P 301 = Industrial temp., PDIP package, Extended VDD limits, QTP pattern #301. PIC18LF2685-I/SO = Industrial temp., SOIC package, Extended VDD limits. PIC18F4685-I/P = Industrial temp., PDIP package, normal VDD limits. Note 1: 2: F = Standard Voltage Range LF = Wide Voltage Range T = in tape and reel PLCC and TQFP packages only. QTP, SQTP, Code or Special Requirements (blank otherwise) (c) 2007 Microchip Technology Inc. Preliminary DS39761B-page 481 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Habour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256 12/08/06 DS39761B-page 482 Preliminary (c) 2007 Microchip Technology Inc.