DS4402N+T&R - Maxim Integrated Products, Inc.

______________________________________________

Maxim Integrated Products

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

General Description

The DS4402 and DS4404 contain two and four I2C

adjustable current DACs, respectively, that are each

capable of sinking or sourcing current. Each output has

31 sink and 31 source settings that are programmed by

the I2C interface. External resistors set the full-scale

range and step size of each output.

Applications

Power-Supply Adjustment

Power-Supply Margining

Adjustable Current Sink or Source

Features

♦Two (DS4402) or Four (DS4404) Current DACs

♦Full-Scale Range for Each DAC Determined by

External Resistors

♦31 Settings Each for Sink and Source Modes

♦I2C-Compatible Serial Interface

♦Two Three-Level Address Pins Allow Nine

Devices on Same I2C Bus

♦Small Package (14-Pin TDFN)

♦-40°C to +85°C Temperature Range

♦2.7V to 5.5V Operation

DS4402/DS4404

Two/Four-Channel, I2C Adjustable Current DAC

DC/DC

CONVERTER

OUT

SDA

SCL

A1 OUT0

OUT1

GND

RFS0 RFS1

4.7kΩ4.7kΩVCC

VCC VOUT0

FS0 FS1

R0B

R0A

DS4402

DC/DC

CONVERTER

OUT

VOUT1

R1B

R1A

Typical Operating Circuit

Ordering Information

19-4641; Rev 3; 5/09

Denotes a lead(Pb)-free/RoHS-compliant package.

T&R = Tape and reel.

EP = Exposed pad.

PART TEMP RANGE PIN-PACKAGE

DS4402N+ -40°C to +85°C 14 TDFN-EP*

DS4402N+T&R -40°C to +85°C 14 TDFN-EP*

DS4404N+ -40°C to +85°C 14 TDFN-EP*

DS4404N+T&R -40°C to +85°C 14 TDFN-EP*

TDFN

TOP VIEW

VCC

OUT1

SCL

FS3 (N.C.)

FS2 (N.C.)

*EXPOSED PAD

( ) INDICATES FOR DS4402 ONLY.

14 OUT3 (N.C.)

OUT2 (N.C.)

SDA

312

GND

69A0FS1

78OUT0FS0

DS4404/

DS4402

*EP

(3mm

3mm

0.8mm)

Pin Configuration

DS4402/DS4404

Two/Four-Channel, I2C Adjustable Current DAC

2 ______________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

(TA= -40°C to +85°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

Voltage Range on VCC, SDA, and SCL

Relative to Ground.............................................-0.5V to +6.0V

Voltage Range on A0, A1, FS0, FS1, FS2, FS3,

OUT0, OUT1, OUT2, and OUT3 Relative to

Ground ................-0.5V to (VCC + 0.5V) (Not to exceed 6.0V.)

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range .............................-55°C to +125°C

Soldering Temperature .....................................Refer to IPC/JEDEC

J-STD-020 Specification

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Voltage VCC (Note 1) 2.7 5.5 V

Input Logic 1 (SDA, SCL, A0, A1) VIH 0.7 x VCC V

CC + 0.3 V

Input Logic 0 (SDA, SCL, A0, A1) VIL -0.3 0.3 x VCC V

DC ELECTRICAL CHARACTERISTICS

(VCC = +2.7V to +5.5V, TA= -40°C to +85°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DS4402 500

Supply Current ICC VCC = 5.5V

(Note 2) DS4404 500

μA

Input Leakage (SDA, SCL) IIL V

CC = 5.5V 1 μA

Output Leakage (SDA) IL 1 μA

VOL = 0.4V 3

Output Current Low (SDA) IOL VOL = 0.6V 6 mA

Address Input Resistors RIN 240 k

Reference Voltage VREF 1.23 V

I/O Capacitance CI/O 10 pF

OUTPUT CURRENT CHARACTERISTICS

(VCC = +2.7V to +5.5V, TA= -40°C to +85°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Voltage for Sinking Current VOUT:SINK (Note 3) 0.5 VCC V

Output Voltage for Sourcing

Current VOUT:SOURCE (Note 3) 0 VCC -

0.5 V

Full-Scale Sink Output Current IOUT:SINK (Note 3) 0.5 2.0 mA

Full-Scale Source Output Current IOUT:SOURCE (Note 3) -2.0 -0.5 mA

Output-Current Full-Scale

Accuracy IOUT:FS

+25°C, VCC = 4.0V; using ideal RFS

resistor; VOUT:SINK = 0.5V;

VOUT:SOURCE = VCC - 0.8V

2.5 5.0 %

Output-Current Temperature Drift IOUT:TC (Note 4) 70 ppm/°C

DS4402/DS4404

Two/Four-Channel, I2C Adjustable Current DAC

_____________________________________________________________________ 3

Note 1: All voltages with respect to ground. Currents entering the IC are specified positive, and currents exiting the IC are negative.

Note 2: Supply current specified with all outputs set to zero current setting with all inputs (except A1 and A0, which can be open) driven

to well-defined logic levels. SDA and SCL are connected to VCC. Excludes current through RFS resistors (IRFS). Total current

including IRFS is ICC + (2 x IRFS).

Note 3: The output-voltage full-scale current ranges must be satisfied to ensure the device meets its accuracy and linearity specifications.

Note 4: Temperature drift excludes drift caused by external resistor.

Note 5: Differential linearity is defined as the difference between the expected incremental current increase with respect to position

and the actual increase. The expected incremental increase is the full-scale range divided by 31.

Note 6: Integral linearity is defined as the difference between the expected value as a function of the setting and the actual value.

The expected value is a straight line between the zero and the full-scale values proportional to the setting.

Note 7: Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard-mode timing.

Note 8: CB—total capacitance of one bus line in pF.

OUTPUT CURRENT CHARACTERISTICS (continued)

(VCC = +2.7V to +5.5V, TA= -40°C to +85°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output-Current Power-Supply

Rejection Ratio DC 0.33 %/V

Output Leakage Current at Zero

Current Setting IZERO -1 +1 μA

Output-Current Differential

Linearity DNL (Note 5) 0.5 LSB

Output-Current Integral Linearity INL (Note 6) 1 LSB

I2C AC ELECTRICAL CHARACTERISTICS

(VCC = +2.7V to +5.5V, TA= -40°C to +85°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SCL Clock Frequency fSCL (Note 7) 0 400 kHz

Bus Free Time Between STOP

and START Conditions tBUF 1.3 µs

Hold Time (Repeated) START

Condition tHD:STA 0.6 µs

Low Period of SCL tLOW 1.3 µs

High Period of SCL tHIGH 0.6 µs

Data Hold Time tDH:DAT 0 0.9 µs

Data Setup Time tSU:DAT 100 ns

START Setup Time tSU:STA 0.6 µs

SDA and SCL Rise Time tR(Note 8) 20 +

0.1CB300 ns

SDA and SCL Fall Time tF(Note 8) 20 +

0.1CB300 ns

STOP Setup Time tSU:STO 0.6 µs

SDA and SCL Capacitive Loading CB(Note 8) 400 pF

DS4402/DS4404

Two/Four-Channel, I2C Adjustable Current DAC

4 ______________________________________________________________________

VCC

RFS0 RFS1 RFS2 RFS3

SDA SCL A1 A0

GND

FS0 FS1 OUT1OUT0

CURRENT

DAC0

F8h F9h

SOURCE OR

SINK MODE

FS2 OUT2 FS3 OUT3

CURRENT

DAC3

31-POSITIONS

EACH FOR SINK

AND SOURCE

MODE

FAh FBh

DS4402/DS4404

DS4404

CURRENT

DAC1

CURRENT

DAC2

I2C-COMPATIBLE

SERIAL INTERFACE

Figure 1. Functional Diagram

Pin Description

DS4404 DS4402

NAME FUNCTION

1 1 SDA I2C Serial Data. Input/output for I2C data.

2 2 SCL I2C Serial Clock. Input for I2C clock.

3 3 GND Ground

4 — FS3

5 — FS2

6 6 FS1

7 7 FS0

Full-Scale Calibration Input. A resistor to ground on these pins determines the full-scale

current for each output. FS0 controls OUT0, FS1 controls OUT1, etc. (DS4402 has only

two inputs: FS0 and FS1.)

8 8 OUT0

10 10 OUT1

12 — OUT2

14 — OUT3

Current Output. Sinks or sources the current determined by the I2C interface and the

resistance connected to FSx. (DS4402 has only two outputs: OUT0 and OUT1.)

9, 11 9, 11 A0, A1 Address Select Inputs. Tri-level inputs (VCC, GND, N.C.) determine the I2C slave address.

See the Detailed Description section for the nine available device addresses.

13 13 VCC Power Supply

— 4, 5, 12, 14 N.C. No Connection

— — EP Exposed Pad. Leave unconnected or connect to GND.

Detailed Description

The DS4402/DS4404 contain two/four I2C adjustable

current sources (Figure 1) that are each capable of

sinking and sourcing current. Each output has 31 sink

and 31 source settings that are programmed through

the I2C interface. The full-scale ranges (and corre-

sponding step sizes) of the outputs are determined by

external resistors that adjust the output currents over a

4:1 range. The formula to determine the external resis-

tor values (RFS) for each of the outputs is given by:

Equation 1:

RFS = (VREF / IFS) x (31 / 4)

where IFS = desired full-scale current

On power-up, the DS4402/DS4404 output zero current.

This is done to prevent it from sinking or sourcing an

incorrect current before the system host controller has

had a chance to modify the device’s setting.

As a source for biasing instrumentation or other cir-

cuits, the DS4402/DS4404 provide a simple and inex-

pensive current source with an I2C interface for control.

The adjustable full-scale range allows the application to

get the most out of its 5-bit sink or source resolution.

When used in adjustable power-supply applications

(see the

Typical Operating Circuit

), the DS4402/DS4404

do not affect the initial power-up supply voltage because

it defaults to providing zero output current on power-up.

As it sources or sinks current into the feedback voltage

node, it changes the amount of output voltage required

by the regulator to reach its steady state operating point.

By using the external resistor to set the output current

range, the devices provide flexibility for adjusting the

impedances of the feedback network or the range over

which the power supply can be controlled or margined.

I2C Slave Address

The DS4402/DS4404 respond to one of nine I2C slave

addresses determined by the two tri-level address

inputs. The three input states are connected to VCC,

connected to ground, or disconnected. To sense the

disconnected state (Figure 2), the address inputs have

weak internal resistors that pull the pins to mid-supply.

Table 1 lists the slave address determined by the

address input combinations.

DS4402/DS4404

Two/Four-Channel, I2C Adjustable Current DAC

_____________________________________________________________________ 5

Table 1. Slave Addresses

A1 A0 SLAVE ADDRESS

(HEXADECIMAL)

GND GND 90h

GND VCC 92h

VCC GND 94h

VCC VCC 96h

N.C. GND 98h

N.C. VCC 9Ah

GND N.C. 9Ch

VCC N.C. 9Eh

N.C. N.C. A0h

A1 I2C

ADDRESS

DECODE

RIN RIN

VCC

RIN RIN

Figure 2. I2C Address Inputs

DS4402/DS4404

Memory Organization

To control the DS4402/DS4404’s current sources, write

to the memory addresses listed in Table 2.

The format of each output control register is given by:

Where:

Example: IFS0 = 800µA, and register F8h is written to a

value of 92h. Calculate the value of external resistance

required, and the magnitude of the output current with

this register setting.

RFS = (VREF / 800µA) x (31 / 4) = 11.9kΩ

The MSB of the output register is 1, so the output is

sourcing the value corresponding to position 12h (18

decimal). The magnitude of the output current is equal to:

800µA x (18 / 31) = 465µA

I2C Serial Interface Description

I2C Definitions

The following terminology is commonly used to describe

I2C data transfers:

Master Device: The master device controls the slave

devices on the bus. The master device generates SCL

clock pulses, START and STOP conditions.

Slave Devices: Slave devices send and receive data

at the master’s request.

Bus Idle or Not Busy: Time between STOP and START

conditions when both SDA and SCL are inactive and in

their logic-high states. When the bus is idle it often initi-

ates a low-power mode for slave devices.

START Condition: A START condition is generated by

the master to initiate a new data transfer with a slave.

Transitioning SDA from high to low while SCL remains

high generates a START condition. See Figure 3 for

applicable timing.

STOP Condition: A STOP condition is generated by the

master to end a data transfer with a slave. Transitioning

SDA from low to high while SCL remains high generates

a STOP condition. See Figure 3 for applicable timing.

Repeated START Condition: The master can use a

repeated START condition at the end of one data trans-

fer to indicate that it will immediately initiate a new data

transfer following the current one. Repeated STARTs are

commonly used during read operations to identify a spe-

cific memory address to begin a data transfer. A repeat-

ed START condition is issued identically to a normal

START condition. See Figure 3 for applicable timing.

Bit Write: Transitions of SDA must occur during the low

state of SCL. The data on SDA must remain valid and

unchanged during the entire high pulse of SCL, plus the

setup and hold time requirements (Figure 3). Data is

shifted into the device during the rising edge of the SCL.

Bit Read: At the end of a write operation, the master

must release the SDA bus line for the proper amount of

setup time (Figure 3) before the next rising edge of SCL

during a bit read. The device shifts out each bit of data

on SDA at the falling edge of the previous SCL pulse

and the data bit is valid at the rising edge of the current

SCL pulse. Remember that the master generates all

SCL clock pulses, including when it is reading bits from

the slave.

Two/Four-Channel, I2C Adjustable Current DAC

6 ______________________________________________________________________

MSB LSB

SXXD

4D3D2D1D0

BIT NAME FUNCTION POWER-ON

DEFAULT

S Sign Bit

Determines if DAC sources

or sinks current. For sink

S = 0, for source S = 1.

X Reserved Reserved. Both bits read

zero. 00b

DXData

5-Bit Data Word Controlling

DAC Output. Setting 00000b

outputs zero current

regardless of the state of the

sign bit.

00000b

Table 2. Memory Addresses

MEMORY ADDRESS

(HEXADECIMAL) CURRENT SOURCE

F8h OUT0

F9h OUT1

FAh* OUT2*

FBh* OUT3*

*Only for DS4404.

Acknowledgement (ACK and NACK): An Acknowledge-

ment (ACK) or Not Acknowledge (NACK) is always the

ninth bit transmitted during a byte transfer. The device

receiving data (the master during a read or the slave

during a write operation) performs an ACK by transmit-

ting a zero during the ninth bit. A device performs a

NACK by transmitting a one during the ninth bit. Timing

for the ACK and NACK is identical to all other bit writes

(Figure 4). An ACK is the acknowledgment that the

device is properly receiving data. A NACK is used to

terminate a read sequence or as an indication that the

device is not receiving data.

Byte Write: A byte write consists of 8 bits of information

transferred from the master to the slave (most significant

bit first) plus a 1-bit acknowledgement from the slave to

the master. The 8 bits transmitted by the master are

done according to the bit-write definition, and the

acknowledgement is read using the bit-read definition.

Byte Read: A byte read is an 8-bit information transfer

from the slave to the master plus a 1-bit ACK or NACK

from the master to the slave. The 8 bits of information

that are transferred (most significant bit first) from the

slave to the master are read by the master using the bit

read definition above, and the master transmits an ACK

using the bit write definition to receive additional data

bytes. The master must NACK the last byte read to ter-

minated communication so the slave will return control

of SDA to the master.

Slave Address Byte: Each slave on the I2C bus

responds to a slave address byte sent immediately follow-

ing a START condition. The slave address byte contains

the slave address in the most significant 7 bits and the

R/Wbit in the least significant bit. The DS4402/DS4404s’

slave address is determined by the state of the A0 and A1

address pins. Table 1 describes the addresses corre-

sponding to the state of A0 and A1.

When the R/Wbit is 0 (such as in A0h), the master is

indicating it will write data to the slave. If R/W= 1 (A1h

in this case), the master is indicating it wants to read

from the slave. If an incorrect slave address is written,

the DS4402/DS4404 assume the master is communi-

cating with another I2C device and ignore the commu-

nication until the next START condition is sent.

Memory Address: During an I2C write operation, the

master must transmit a memory address to identify the

memory location where the slave is to store the data.

The memory address is always the second byte trans-

mitted during a write operation following the slave

address byte.

I2C Communication

Writing to a Slave: The master must generate a START

condition, write the slave address byte (R/W= 0), write

the memory address, write the byte of data, and gener-

ate a STOP condition. Remember that the master must

read the slave’s acknowledgement during all byte-write

operations.

Reading from a Slave: To read from the slave, the

master generates a START condition, writes the slave

address byte with R/W= 1, reads the data byte with a

NACK to indicate the end of the transfer, and generates

a STOP condition.

DS4402/DS4404

Two/Four-Channel, I2C Adjustable Current DAC

_____________________________________________________________________ 7

SCL

NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).

SDA

STOP START REPEATED

START

tBUF

tHD:STA

tHD:DAT tSU:DAT

tSU:STO

tHD:STA

tSP

tSU:STA

tHIGH

tLOW

Figure 3. I2C Timing Diagram

DS4402/DS4404

Two/Four-Channel, I2C Adjustable Current DAC

8 ______________________________________________________________________

Applications Information

Example Calculations

for an Adjustable Power Supply

Using the typical circuit, assuming a typical output volt-

age of 2.0V, a feedback voltage of 0.8V, R1 = 500Ω,

and R2 = 333Ω, to adjust or margin the supply 20%

requires a full-scale current equal to [(0.2 x 2.0V) /

500Ω= 800µA]. Using Equation 1, RFS can be calculat-

ed [RFS = (VREF / 800µA) x (31 / 4) = 11.9kΩ]. The cur-

rent DAC in this configuration allows the output voltage

to be stepped linearly from 1.6V to 2.4V using 63 set-

tings. This corresponds to a resolution of 12.7mV/step.

Power-Supply Feedback Voltage

The feedback voltage for adjustable power supplies

must be between 0.5V and VCC - 0.5V for the DS4402/

DS4404 to properly sink/source currents for adjusting

the voltage.

I2C Reset on Address Change

In addition to defining the I2C slave address, the DS4402/

DS4404 address select inputs have an alternate function.

Changing the address select inputs resets the I2C inter-

face. This function aborts the current transaction and puts

the SDA driver into a high-impedance state. This hard-

ware reset function should never be required because it

is achievable through software, but it does provide an

alternative way of resetting the I2C interface, if needed.

VCC Decoupling

To achieve the best results when using the DS4402/

DS4404, decouple the power supply with a 0.01µF or

0.1µF capacitor. Use a high-quality ceramic surface-

mount capacitor if possible. Surface-mount compo-

nents minimize lead inductance, which improves

performance, and ceramic capacitors tend to have

adequate high-frequency response for decoupling

applications.

Layout Considerations

Care should be taken to ensure that traces underneath

the DS4402/DS4404 do not short with the exposed pad.

The exposed pad should be connected to the signal

ground, or can be left unconnected.

SLAVE

ADDRESS*

START

a7 a6 a5 a4 a3 a2 a1 R/W SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

MSB LSB MSB LSB MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

READ/

WRITE

b7 b6 b5 b4 b3 b2 b1 b0

DATA

STOP

SINGLE BYTE WRITE

-WRITE RESISTOR

F9h TO 00h

SINGLE BYTE READ

-READ RESISTOR F8h START REPEATED

START

A1h

MASTER

NACK STOP

1 0100000 11111 000

F8h

10100 001

1 0100000 11111 001

A0h F9h

STOP

DATA

EXAMPLE I2C TRANSACTIONS (WHEN A0 AND A1 ARE N.C.)

TYPICAL I2C WRITE TRANSACTION

*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1 (SEE TABLE 1).

00000 000

A0h

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

Figure 4. I2C Communication Examples

Chip Information

TRANSISTOR COUNT: 10,992

Package Information

For the latest package outline information and land patterns, go

to www.maxim-ic.com/packages.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

14 TDFN-EP T1433+1 21-0137

DS4402/DS4404

Two/Four-Channel, I2C Adjustable Current DAC

Heaney

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________

is a registered trademark of Dallas Semiconductor Corporation.

Revision History

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES

CHANGED

0 4/06 Initial release. —

1 8/06 In the Features, corrected the operating range from 1.7V to 5.5V to 2.7V to 5.5V. 1

2 10/08

Added the I/O capacitance (CI/O) parameter to the DC Electrical Characteristics

table. 2

3 5/09

In the Output Current Characteristics table, added VOUT:SINK = 0.5V;

VOUT:SOURCE = VCC = 0.8V to the IOUT:FS conditions. 2