Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet April 2013 Document Number: 326514-002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death. 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Copyright (c) 2013, Intel Corporation 2 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Contents 1 Introduction ............................................................................................................ 41 1.1 About This Manual ............................................................................................. 41 1.2 Overview ......................................................................................................... 44 1.2.1 Capability Overview ................................................................................ 45 1.3 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset SKU Definition ............... 50 2 Signal Description ................................................................................................... 51 2.1 Direct Media Interface (DMI) to Host Controller ..................................................... 53 2.2 PCI Express* .................................................................................................... 53 2.3 PCI Express* Uplink (Intel(R) C606, C608 Chipset SKUs Only)................................... 54 2.4 PCI Interface .................................................................................................... 54 2.5 Serial ATA Interface........................................................................................... 56 2.6 SAS Interface (SRV/WS SKUs Only) ..................................................................... 58 2.7 LPC Interface.................................................................................................... 60 2.8 Interrupt Interface ............................................................................................ 60 2.9 USB 2.0 Interface.............................................................................................. 61 2.10 Power Management Interface.............................................................................. 62 2.11 Processor Interface............................................................................................ 64 2.12 SMBus Interface................................................................................................ 65 2.13 System Management Interface............................................................................ 65 2.14 SAS System Management Interface (SRV/WS SKUs Only)....................................... 65 2.15 Real Time Clock Interface ................................................................................... 66 2.16 Miscellaneous Signals ........................................................................................ 66 2.17 Intel(R) High Definition Audio (Intel(R) HD Audio) Link ............................................... 67 2.18 Serial Peripheral Interface (SPI) .......................................................................... 68 2.19 Thermal Signals ................................................................................................ 68 2.20 JTAG Signals .................................................................................................... 68 2.21 Clock Signals .................................................................................................... 69 2.22 General Purpose I/O Signals ............................................................................... 70 2.23 GPIO Serial Expander Signals.............................................................................. 73 2.24 Manageability Signals ........................................................................................ 73 2.25 Power and Ground Signals .................................................................................. 74 2.26 Pin Straps ........................................................................................................ 76 2.26.1 Functional Straps ................................................................................... 76 2.27 External RTC Circuitry ........................................................................................ 79 3 PCH Pin States......................................................................................................... 81 3.1 Integrated Pull-Ups and Pull-Downs ..................................................................... 81 3.2 Output and I/O Signals Planes and States............................................................. 82 3.3 Power Planes for Input Signals ............................................................................ 87 4 System Clock Domains............................................................................................. 91 4.1 System Clock Domains....................................................................................... 91 4.2 Functional Blocks .............................................................................................. 93 5 Functional Description ............................................................................................. 95 5.1 PCI-to-PCI Bridge (D30:F0) ................................................................................ 95 5.1.1 PCI Bus Interface ................................................................................... 95 5.1.2 PCI Bridge As an Initiator ........................................................................ 95 5.1.3 Parity Error Detection and Generation ....................................................... 97 5.1.4 PCIRST# ............................................................................................... 98 5.1.5 Peer Cycles ........................................................................................... 98 5.1.6 PCI-to-PCI Bridge Model.......................................................................... 98 5.1.7 IDSEL to Device Number Mapping ............................................................ 99 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 3 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 4 5.1.8 Standard PCI Bus Configuration Mechanism................................................99 PCI Legacy Mode ...............................................................................................99 PCI Express*................................................................................................... 100 5.3.1 PCI Express* UpLink Port (Bn:D0:F0) (SRV/WS SKUs Only) ....................... 100 5.3.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7) .......................... 106 Gigabit Ethernet Controller (B0:D25:F0) ............................................................. 110 5.4.1 GbE PCI Express Bus Interface ............................................................... 112 5.4.2 Error Events and Error Reporting ............................................................ 113 5.4.3 Ethernet Interface ................................................................................ 113 5.4.4 PCI Power Management ......................................................................... 113 5.4.5 Configurable LEDs................................................................................. 115 5.4.6 Function Level Reset Support (FLR) (SRV/WS SKUs Only) .......................... 116 LPC Bridge (with System and Management Functions) (D31:F0)............................. 117 5.5.1 LPC Interface ....................................................................................... 117 DMA Operation (D31:F0) .................................................................................. 121 5.6.1 Channel Priority.................................................................................... 122 5.6.2 Address Compatibility Mode ................................................................... 122 5.6.3 Summary of DMA Transfer Sizes ............................................................. 122 5.6.4 Autoinitialize ........................................................................................ 123 5.6.5 Software Commands ............................................................................. 123 LPC DMA ........................................................................................................ 124 5.7.1 Asserting DMA Requests ........................................................................ 124 5.7.2 Abandoning DMA Requests..................................................................... 124 5.7.3 General Flow of DMA Transfers ............................................................... 125 5.7.4 Terminal Count..................................................................................... 125 5.7.5 Verify Mode ......................................................................................... 125 5.7.6 DMA Request Deassertion ...................................................................... 126 5.7.7 SYNC Field / LDRQ# Rules ..................................................................... 126 8254 Timers (D31:F0) ...................................................................................... 127 5.8.1 Timer Programming .............................................................................. 127 5.8.2 Reading from the Interval Timer ............................................................. 128 8259 Interrupt Controllers (PIC) (D31:F0)........................................................... 130 5.9.1 Interrupt Handling ................................................................................ 131 5.9.2 Initialization Command Words (ICWx) ..................................................... 132 5.9.3 Operation Command Words (OCW) ......................................................... 133 5.9.4 Modes of Operation ............................................................................... 133 5.9.5 Masking Interrupts................................................................................ 135 5.9.6 Steering PCI Interrupts.......................................................................... 135 Advanced Programmable Interrupt Controller (APIC) (D31:F0)............................... 136 5.10.1 Interrupt Handling ................................................................................ 136 5.10.2 Interrupt Mapping................................................................................. 136 5.10.3 PCI / PCI Express* Message-Based Interrupts .......................................... 137 5.10.4 IOxAPIC Address Remapping (SRV/WS SKUs Only) ................................... 137 5.10.5 External Interrupt Controller Support ...................................................... 137 Serial Interrupt (D31:F0) .................................................................................. 138 5.11.1 Start Frame ......................................................................................... 138 5.11.2 Data Frames ........................................................................................ 139 5.11.3 Stop Frame.......................................................................................... 139 5.11.4 Specific Interrupts Not Supported using SERIRQ ....................................... 139 5.11.5 Data Frame Format............................................................................... 140 Real Time Clock (D31:F0) ................................................................................. 140 5.12.1 Update Cycles ...................................................................................... 141 5.12.2 Interrupts ............................................................................................ 141 5.12.3 Lockable RAM Ranges............................................................................ 141 5.12.4 Century Rollover................................................................................... 142 5.12.5 Clearing Battery-Backed RTC RAM........................................................... 142 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 5.13 5.14 5.15 5.16 5.17 5.18 5.19 Processor Interface (D31:F0) ............................................................................ 143 5.13.1 Processor Interface Signals and VLW Messages ........................................ 144 5.13.2 Dual-Processor Issues........................................................................... 145 5.13.3 Virtual Legacy Wire (VLW) Messages....................................................... 145 Power Management ......................................................................................... 146 5.14.1 Features ............................................................................................. 146 5.14.2 PCH and System Power States ............................................................... 146 5.14.3 System Power Planes ............................................................................ 148 5.14.4 SMI#/SCI Generation ........................................................................... 148 5.14.5 C-States ............................................................................................. 151 5.14.6 Sleep States ........................................................................................ 151 5.14.7 Event Input Signals and Their Usage....................................................... 155 5.14.8 ALT Access Mode.................................................................................. 158 5.14.9 System Power Supplies, Planes, and Signals ............................................ 161 5.14.10Legacy Power Management Theory of Operation ....................................... 163 5.14.11Reset Behavior..................................................................................... 163 System Management (D31:F0).......................................................................... 165 5.15.1 Theory of Operation.............................................................................. 166 5.15.2 TCO Modes .......................................................................................... 167 General Purpose I/O (D31:F0) .......................................................................... 169 5.16.1 Power Wells......................................................................................... 169 5.16.2 SMI# SCI and NMI Routing.................................................................... 169 5.16.3 Triggering ........................................................................................... 169 5.16.4 GPIO Registers Lockdown ...................................................................... 169 5.16.5 Serial POST Codes over GPIO................................................................. 170 5.16.6 GPIO Serial Expander (GSX) .................................................................. 172 SATA Host Controller (D31:F2, F5) .................................................................... 174 5.17.1 SATA 6 Gb/s Support ............................................................................ 174 5.17.2 SATA Feature Support........................................................................... 174 5.17.3 Theory of Operation.............................................................................. 175 5.17.4 SATA Swap Bay Support ....................................................................... 176 5.17.5 Hot-Plug Operation ............................................................................... 176 5.17.6 Function Level Reset Support (FLR) (SRV/WS SKUs Only) .......................... 176 5.17.7 Intel(R) Rapid Storage Technology Enterprise Configuration ......................... 177 5.17.8 Power Management Operation................................................................ 178 5.17.9 SATA Device Presence........................................................................... 179 5.17.10SATA LED............................................................................................ 180 5.17.11AHCI Operation.................................................................................... 180 5.17.12SGPIO Signals ..................................................................................... 181 5.17.13External SATA...................................................................................... 184 SAS/SATA Controller Overview (SAS is for SRV/WS SKUs Only) ............................. 185 5.18.1 SCU Features....................................................................................... 185 5.18.2 SCU Configurations............................................................................... 186 5.18.3 Storage Controller Unit (SCU) Architecture .............................................. 188 5.18.4 SCU Physical Layer/PHY Overview .......................................................... 196 5.18.5 Interrupts and Interrupt Coalescing ........................................................ 198 5.18.6 SMU Error and Event Generation ............................................................ 199 5.18.7 Host Interface Error Conditions .............................................................. 200 5.18.8 Host Interface Messages Received .......................................................... 204 5.18.9 Reset.................................................................................................. 204 5.18.10SGPIO ................................................................................................ 205 High Precision Event Timers (HPET) ................................................................... 214 5.19.1 Timer Accuracy .................................................................................... 214 5.19.2 Interrupt Mapping ................................................................................ 215 5.19.3 Periodic versus Non-Periodic Modes ........................................................ 216 5.19.4 Enabling the Timers.............................................................................. 217 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 5 5.20 5.21 5.22 5.23 5.24 5.25 5.26 5.27 5.28 5.29 6 5.19.5 Interrupt Levels.................................................................................... 217 5.19.6 Handling Interrupts............................................................................... 217 5.19.7 Issues Related to 64-Bit Timers with 32-Bit Processors .............................. 217 USB EHCI Host Controllers (D29:F0 and D26:F0) ................................................. 217 5.20.1 EHC Initialization .................................................................................. 217 5.20.2 Data Structures in Main Memory ............................................................. 218 5.20.3 USB 2.0 Enhanced Host Controller DMA ................................................... 218 5.20.4 Data Encoding and Bit Stuffing ............................................................... 218 5.20.5 Packet Formats .................................................................................... 218 5.20.6 USB 2.0 Interrupts and Error Conditions .................................................. 219 5.20.7 USB 2.0 Power Management .................................................................. 220 5.20.8 USB 2.0 Legacy Keyboard Operation ....................................................... 221 5.20.9 USB 2.0 Based Debug Port ..................................................................... 221 5.20.10EHCI Caching ....................................................................................... 225 5.20.11USB Pre-Fetch Based Pause ................................................................... 225 5.20.12Function Level Reset Support (FLR) (SRV/WS SKUs Only) .......................... 226 5.20.13USB Overcurrent Protection.................................................................... 226 Integrated USB 2.0 Rate Matching Hub ............................................................... 227 5.21.1 Overview ............................................................................................. 227 5.21.2 Architecture ......................................................................................... 227 SMBus Controller ............................................................................................. 228 5.22.1 Host SMBus Controller(D31:F3) .............................................................. 228 5.22.2 IDF SMbus Controllers (Bus x:Device 0:Function 3,4,5) (SRV/WS SKUs Only) ............................................................................ 228 5.22.3 Host Controller ..................................................................................... 229 5.22.4 Bus Arbitration ..................................................................................... 233 5.22.5 Bus Timing .......................................................................................... 234 5.22.6 Interrupts / SMI# ................................................................................. 234 5.22.7 SMBALERT#......................................................................................... 235 5.22.8 SMBus CRC Generation and Checking ...................................................... 235 5.22.9 SMBus Slave Interface........................................................................... 236 Thermal Management....................................................................................... 241 5.23.1 Thermal Sensor .................................................................................... 241 5.23.2 Thermal Reporting Over System Management Link 1 Interface (SMLink1)..... 243 Intel(R) High Definition Audio (Intel(R) HD Audio) Overview (D27:F0)......................... 251 PCH Intel(R) Management Engine Firmware........................................................... 251 5.25.1 Intel(R) Server Platform Services Firmware ................................................ 251 5.25.2 Intel(R) AMT 7.0 (SRV/WS SKUs Only) ...................................................... 253 5.25.3 Intel(R) Management Engine Requirements ................................................ 254 Serial Peripheral Interface (SPI) ........................................................................ 255 5.26.1 SPI Supported Feature Overview ............................................................ 255 5.26.2 Flash Descriptor ................................................................................... 256 5.26.3 Flash Access ........................................................................................ 258 5.26.4 Serial Flash Device Compatibility Requirements ........................................ 259 5.26.5 Multiple Page Write Usage Model............................................................. 261 5.26.6 Flash Device Configurations ................................................................... 262 5.26.7 SPI Flash Device Recommended Pinout.................................................... 263 5.26.8 Serial Flash Device Package ................................................................... 263 Fan Control/Thermal Management ..................................................................... 264 5.27.1 PWM Outputs ....................................................................................... 264 5.27.2 TACH Inputs ........................................................................................ 264 Feature Capability Mechanism ........................................................................... 265 Intel(R) Virtualization Technology (SRV/WS SKUs Only) .......................................... 265 5.29.1 Intel(R) Virtualization Technology (Intel(R) VT) for Directed I/O (Intel(R) VT-d) Objectives .................................................................. 265 5.29.2 Intel(R) VT-d features supported on PCH.................................................... 265 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 5.29.3 Support for Function Level Reset (FLR) in PCH.......................................... 266 5.29.4 Virtualization Support for PCH's IOxAPIC ................................................. 266 5.29.5 Virtualization Support for High Precision Event Timer (HPET)...................... 266 6 PCH Ballout Definition ........................................................................................... 267 7 Package Information ............................................................................................. 281 8 Electrical Characteristics ....................................................................................... 283 8.1 Thermal Specifications ..................................................................................... 283 8.2 Absolute Maximum Ratings............................................................................... 283 8.3 PCH Power Supply Range ................................................................................. 284 8.4 General DC Characteristics ............................................................................... 284 8.5 AC Characteristics ........................................................................................... 294 8.6 Power Sequencing and Reset Signal Timings ....................................................... 302 8.7 Power Management Timing Diagrams................................................................. 305 8.8 AC Timing Diagrams ........................................................................................ 309 9 Register and Memory Mapping............................................................................... 319 9.1 PCI Devices and Functions................................................................................ 320 9.2 PCI Configuration Map ..................................................................................... 321 9.3 I/O Map ......................................................................................................... 322 9.3.1 Fixed I/O Address Ranges ..................................................................... 322 9.3.2 Variable I/O Decode Ranges .................................................................. 324 9.4 Memory Map................................................................................................... 325 9.4.1 Boot-Block Update Scheme.................................................................... 327 10 Chipset Configuration Registers............................................................................. 329 10.1 Chipset Configuration Registers (Memory Space) ................................................. 329 10.1.2 RPC--Root Port Configuration Register .................................................... 331 10.1.4 FLRSTAT--FLR Pending Status Register ................................................... 333 10.1.6 TRCR--Trapped Cycle Register ............................................................... 334 10.1.7 TWDR--Trapped Write Data Register....................................................... 334 10.1.9 V0CTL--Virtual Channel 0 Resource Control Register ................................. 336 10.1.10V0STS--Virtual Channel 0 Resource Status Register .................................. 336 10.1.11V1CTL--Virtual Channel 1 Resource Control Register ................................. 336 10.1.12V1STS--Virtual Channel 1 Resource Status Register .................................. 337 10.1.13REC--Root Error Command Register ....................................................... 337 10.1.14LCAP--Link Capabilities Register ............................................................. 337 10.1.15LCTL--Link Control Register ................................................................... 338 10.1.16LLSTS--Link Status Register .................................................................. 338 10.1.17DLCTL2--DMI Link Control 2 Register ...................................................... 338 10.1.18DMIC--DMI Control Register .................................................................. 338 10.1.19TCTL--TCO Configuration Register .......................................................... 339 10.1.20D31IP--Device 31 Interrupt Pin Register.................................................. 339 10.1.21D30IP--Device 30 Interrupt Pin Register.................................................. 340 10.1.22D29IP--Device 29 Interrupt Pin Register.................................................. 340 10.1.23D28IP--Device 28 Interrupt Pin Register.................................................. 340 10.1.25D26IP--Device 26 Interrupt Pin Register.................................................. 342 10.1.26D25IP--Device 25 Interrupt Pin Register.................................................. 342 10.1.28D31IR--Device 31 Interrupt Route Register ............................................. 344 10.1.29D30IR--Device 30 Interrupt Route Register ............................................. 344 10.1.37PRSTS--Power and Reset Status Register ................................................ 351 10.1.38PM_CFG--Power Management Configuration............................................. 352 10.1.39DEEP_S4_POL--Deep S4/S5 From S4 Power Policies ................................. 353 10.1.40DEEP_S5_POL--Deep S4/S5 From S5 Power Policies ................................. 353 10.1.41RC--RTC Configuration Register ............................................................. 353 10.1.42HPTC--High Precision Timer Configuration Register ................................... 354 10.1.43GCS--General Control and Status Register............................................... 354 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 7 10.1.44BUC--Backed Up Control Register ........................................................... 356 10.1.45FD--Function Disable Register ................................................................ 356 10.1.46CG--Clock Gating.................................................................................. 359 10.1.47FDSW--Function Disable SUS Well .......................................................... 360 10.1.48FD2--Function Disable 2 ........................................................................ 360 10.1.49GSXBAR--GPIO Serial Expander Base Address .......................................... 361 10.1.50GSXCTRL--GPIO Serial Expander Control Register ..................................... 361 10.1.51MISCCTL--Miscellaneous Control Register ................................................ 361 10.1.52USBOCM1--Overcurrent MAP Register 1................................................... 362 10.1.53USBOCM2--Overcurrent MAP Register 2................................................... 363 10.1.54RMHWKCTL- Rate Matching Hub Wake Control Register ............................. 363 11 PCI-to-PCI Bridge Registers (D30:F0).................................................................... 365 11.1 PCI Configuration Registers (D30:F0) ................................................................. 365 11.1.1 VID--Vendor Identification Register (PCI-PCI--D30:F0).............................. 366 11.1.2 DID--Device Identification Register (PCI-PCI--D30:F0) .............................. 366 11.1.3 PCICMD--PCI Command (PCI-PCI--D30:F0) ............................................. 366 11.1.4 PSTS--PCI Status Register (PCI-PCI--D30:F0) .......................................... 367 11.1.5 RID--Revision Identification Register (PCI-PCI--D30:F0) ............................ 368 11.1.6 CC--Class Code Register (PCI-PCI--D30:F0)............................................. 368 11.1.7 PMLT--Primary Master Latency Timer Register (PCI-PCI--D30:F0)................................................................................ 368 11.1.8 HEADTYP--Header Type Register (PCI-PCI--D30:F0) ................................. 369 11.1.9 BNUM--Bus Number Register (PCI-PCI--D30:F0) ...................................... 369 11.1.10SMLT--Secondary Master Latency Timer Register (PCI-PCI--D30:F0)................................................................................ 369 11.1.11IOBASE_LIMIT--I/O Base and Limit Register (PCI-PCI--D30:F0)................................................................................ 370 11.1.12SECSTS--Secondary Status Register (PCI-PCI--D30:F0) ............................ 370 11.1.13MEMBASE_LIMIT--Memory Base and Limit Register (PCI-PCI--D30:F0)................................................................................ 371 11.1.14PREF_MEM_BASE_LIMIT--Prefetchable Memory Base and Limit Register (PCI-PCI--D30:F0) ..................................................... 371 11.1.15PMBU32--Prefetchable Memory Base Upper 32 Bits Register (PCI-PCI--D30:F0) ................................................................... 371 11.1.16PMLU32--Prefetchable Memory Limit Upper 32 Bits Register (PCI-PCI--D30:F0) ................................................................... 372 11.1.17CAPP--Capability List Pointer Register (PCI-PCI--D30:F0) .......................... 372 11.1.18INTR--Interrupt Information Register (PCI-PCI--D30:F0) ........................... 372 11.1.19BCTRL--Bridge Control Register (PCI-PCI--D30:F0) ................................... 372 11.1.20SPDH--Secondary PCI Device Hiding Register (PCI-PCI--D30:F0)................................................................................ 374 11.1.21DTC--Delayed Transaction Control Register (PCI-PCI--D30:F0)................................................................................ 374 11.1.22BPS--Bridge Proprietary Status Register (PCI-PCI--D30:F0)................................................................................ 375 11.1.23BPC--Bridge Policy Configuration Register (PCI-PCI--D30:F0)................................................................................ 376 11.1.24SVCAP--Subsystem Vendor Capability Register (PCI-PCI--D30:F0)................................................................................ 377 11.1.25SVID--Subsystem Vendor IDs Register (PCI-PCI--D30:F0) ......................... 377 12 Gigabit LAN Configuration Registers ...................................................................... 379 12.1 Gigabit LAN Configuration Registers (Gigabit LAN -- D25:F0) ................................................................................... 379 12.1.1 VID--Vendor Identification Register (Gigabit LAN--D25:F0) .......................................................................... 380 12.1.2 DID--Device Identification Register (Gigabit LAN--D25:F0) .......................................................................... 380 8 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 12.2 12.1.3 PCICMD--PCI Command Register (Gigabit LAN--D25:F0).......................................................................... 381 12.1.4 PCISTS--PCI Status Register (Gigabit LAN--D25:F0).......................................................................... 382 12.1.5 RID--Revision Identification Register (Gigabit LAN--D25:F0).......................................................................... 382 12.1.6 CC--Class Code Register (Gigabit LAN--D25:F0).......................................................................... 383 12.1.7 CLS--Cache Line Size Register (Gigabit LAN--D25:F0).......................................................................... 383 12.1.8 PLT--Primary Latency Timer Register (Gigabit LAN--D25:F0).......................................................................... 383 12.1.9 HEADTYP--Header Type Register (Gigabit LAN--D25:F0).......................................................................... 383 12.1.10MBARA--Memory Base Address Register A (Gigabit LAN--D25:F0).......................................................................... 384 12.1.11MBARB--Memory Base Address Register B (Gigabit LAN--D25:F0).......................................................................... 384 12.1.12MBARC--Memory Base Address Register C (Gigabit LAN--D25:F0).......................................................................... 385 12.1.13SVID--Subsystem Vendor ID Register (Gigabit LAN--D25:F0).......................................................................... 385 12.1.14SID--Subsystem ID Register (Gigabit LAN--D25:F0).......................................................................... 385 12.1.15ERBA--Expansion ROM Base Address Register (Gigabit LAN--D25:F0).......................................................................... 385 12.1.16CAPP--Capabilities List Pointer Register (Gigabit LAN--D25:F0).......................................................................... 386 12.1.17INTR--Interrupt Information Register (Gigabit LAN--D25:F0).......................................................................... 386 12.1.18MLMG--Maximum Latency/Minimum Grant Register (Gigabit LAN--D25:F0).......................................................................... 386 12.1.19CLIST 1--Capabilities List Register 1 (Gigabit LAN--D25:F0).......................................................................... 386 12.1.20PMC--PCI Power Management Capabilities Register (Gigabit LAN--D25:F0).......................................................................... 387 12.1.21PMCS--PCI Power Management Control and Status Register (Gigabit LAN--D25:F0) ............................................................. 388 12.1.23CLIST 2--Capabilities List Register 2 (Gigabit LAN--D25:F0).......................................................................... 389 12.1.24MCTL--Message Control Register (Gigabit LAN--D25:F0).......................................................................... 389 12.1.25MADDL--Message Address Low Register (Gigabit LAN--D25:F0).......................................................................... 389 12.1.26MADDH--Message Address High Register (Gigabit LAN--D25:F0).......................................................................... 389 12.1.27MDAT--Message Data Register (Gigabit LAN--D25:F0).......................................................................... 390 12.1.28FLRCAP--Function Level Reset Capability (Gigabit LAN--D25:F0).......................................................................... 390 12.1.29FLRCLV--Function Level Reset Capability Length and Version (Gigabit LAN--D25:F0).......................................................................... 390 12.1.301DEVCTRL--Device Control (Gigabit LAN--D25:F0) ................................... 391 Gigabit LAN Capabilities and Status Registers (CSR)............................................. 391 12.2.1 GBECSR1--Gigabit Ethernet Capabilities and Status Register 1 ................... 391 12.2.2 GBECSR2--Gigabit Ethernet Capabilities and Status Register 2 ................... 392 12.2.3 GBECSR3--Gigabit Ethernet Capabilities and Status Register 3 ................... 392 12.2.4 GBECSR4--Gigabit Ethernet Capabilities and Status Register 4 ................... 392 12.2.5 GBECSR5--Gigabit Ethernet Capabilities and Status Register 5 ................... 393 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 9 12.2.6 GBECSR6--Gigabit Ethernet Capabilities and Status Register 6.................... 393 12.2.7 GBECSR7--Gigabit Ethernet Capabilities and Status Register 7.................... 393 12.2.9 GBECSR9--Gigabit Ethernet Capabilities and Status Register 9.................... 394 13 10 LPC Interface Bridge Registers (D31:F0) ............................................................... 395 13.1 PCI Configuration Registers (LPC I/F--D31:F0) .................................................... 395 13.1.1 VID--Vendor Identification Register (LPC I/F--D31:F0) .............................. 396 13.1.2 DID--Device Identification Register (LPC I/F--D31:F0)............................... 396 13.1.3 PCICMD--PCI COMMAND Register (LPC I/F--D31:F0)................................. 397 13.1.4 PCISTS--PCI Status Register (LPC I/F--D31:F0)........................................ 397 13.1.5 RID--Revision Identification Register (LPC I/F--D31:F0) ............................ 398 13.1.6 PI--Programming Interface Register (LPC I/F--D31:F0) ............................. 398 13.1.7 SCC--Sub Class Code Register (LPC I/F--D31:F0) ..................................... 398 13.1.8 BCC--Base Class Code Register (LPC I/F--D31:F0) .................................... 398 13.1.10HEADTYP--Header Type Register (LPC I/F--D31:F0) .................................. 399 13.1.11SS--Sub System Identifiers Register (LPC I/F--D31:F0) ............................. 399 13.1.12CAPP--Capability List Pointer Register (LPC I/F--D31:F0) ........................... 399 13.1.15GPIOBASE--GPIO Base Address Register (LPC I/F -- D31:F0) .............................................................................. 401 13.1.17PIRQ[n]_ROUT--PIRQ[A,B,C,D] Routing Control Register (LPC I/F--D31:F0) ................................................................................ 402 13.1.18SIRQ_CNTL--Serial IRQ Control Register (LPC I/F--D31:F0) ................................................................................ 403 13.1.20LPC_IBDF--IOxAPIC Bus:Device:Function (LPC I/F--D31:F0) ................................................................................ 404 13.1.21LPC_HnBDF - HPET n Bus:Device:Function(LPC I/F--D31:F0) ..................... 405 13.1.22LPC_I/O_DEC--I/O Decode Ranges Register (LPC I/F--D31:F0) ................................................................................ 406 13.1.23LPC_EN--LPC I/F Enables Register (LPC I/F--D31:F0) ................................ 407 13.1.24GEN1_DEC--LPC I/F Generic Decode Range 1 Register (LPC I/F--D31:F0) ................................................................................ 408 13.1.25GEN2_DEC--LPC I/F Generic Decode Range 2 Register (LPC I/F--D31:F0) ................................................................................ 408 13.1.26GEN3_DEC--LPC I/F Generic Decode Range 3 Register (LPC I/F--D31:F0) ................................................................................ 409 13.1.27GEN4_DEC--LPC I/F Generic Decode Range 4 Register (LPC I/F--D31:F0) ................................................................................ 409 13.1.29LGMR -- LPC I/F Generic Memory Range (LPC I/F--D31:F0) ................................................................................ 411 13.1.30BIOS_SEL1--BIOS Select 1 Register (LPC I/F--D31:F0) ................................................................................ 411 13.1.31BIOS_SEL2--BIOS Select 2 Register (LPC I/F--D31:F0) ................................................................................ 412 13.1.32BIOS_DEC_EN1--BIOS Decode Enable Register (LPC I/F--D31:F0) ................................................................................ 412 13.1.33BIOS_CNTL--BIOS Control Register (LPC I/F--D31:F0) ................................................................................ 414 13.1.34FDCAP--Feature Detection Capability ID (LPC I/F--D31:F0) ................................................................................ 415 13.1.35FDLEN--Feature Detection Capability Length (LPC I/F--D31:F0) ................................................................................ 415 13.1.36FDVER--Feature Detection Version (LPC I/F--D31:F0) ................................................................................ 415 13.1.37FVECIDX--Feature Vector Index (LPC I/F--D31:F0) ................................................................................ 416 13.1.38FVECD--Feature Vector Data (LPC I/F--D31:F0) ................................................................................ 416 13.1.39Feature Vector Space ............................................................................ 416 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 13.1.40RCBA--Root Complex Base Address Register (LPC I/F--D31:F0) ................................................................................ 418 DMA I/O Registers........................................................................................... 418 13.2.1 DMABASE_CA--DMA Base and Current Address Registers .......................... 419 13.2.2 DMABASE_CC--DMA Base and Current Count Registers ............................. 420 13.2.3 DMAMEM_LP--DMA Memory Low Page Registers ....................................... 420 13.2.4 DMACMD--DMA Command Register ........................................................ 420 13.2.6 DMA_WRSMSK--DMA Write Single Mask Register...................................... 421 13.2.7 DMACH_MODE--DMA Channel Mode Register ........................................... 422 13.2.8 DMA Clear Byte Pointer Register............................................................. 422 13.2.9 DMA Master Clear Register .................................................................... 423 13.2.11DMA_WRMSK--DMA Write All Mask Register ............................................ 423 Timer I/O Registers ......................................................................................... 424 13.3.1 TCW--Timer Control Word Register ......................................................... 424 13.3.2 SBYTE_FMT--Interval Timer Status Byte Format Register........................... 426 13.3.3 Counter Access Ports Register ................................................................ 426 8259 Interrupt Controller (PIC) Registers ........................................................... 427 13.4.1 Interrupt Controller I/O MAP .................................................................. 427 13.4.2 ICW1--Initialization Command Word 1 Register ........................................ 427 13.4.3 ICW2--Initialization Command Word 2 Register ........................................ 428 13.4.4 ICW3--Master Controller Initialization Command Word 3 Register ................................................................................... 429 13.4.5 ICW3--Slave Controller Initialization Command Word 3 Register ................................................................................... 429 13.4.6 ICW4--Initialization Command Word 4 Register ........................................ 429 13.4.7 OCW1--Operational Control Word 1 (Interrupt Mask) Register .............................................................................................. 430 13.4.9 OCW3--Operational Control Word 3 Register ............................................ 431 13.4.10ELCR1--Master Controller Edge/Level Triggered Register ........................... 431 13.4.11ELCR2--Slave Controller Edge/Level Triggered Register ............................. 432 Advanced Programmable Interrupt Controller (APIC)............................................ 432 13.5.1 APIC Register Map................................................................................ 432 13.5.2 IND--Index Register ............................................................................. 433 13.5.3 DAT--Data Register .............................................................................. 434 13.5.4 EOIR--EOI Register .............................................................................. 434 13.5.5 ID--Identification Register ..................................................................... 434 13.5.6 VER--Version Register .......................................................................... 435 13.5.7 REDIR_TBL--Redirection Table ............................................................... 435 Real Time Clock Registers................................................................................. 437 13.6.1 I/O Register Address Map ...................................................................... 437 13.6.2 Indexed Registers ................................................................................ 437 Processor Interface Registers ............................................................................ 441 13.7.1 NMI_SC--NMI Status and Control Register ............................................... 441 13.7.3 PORT92-- Init Register.......................................................................... 442 13.7.4 COPROC_ERR--Coprocessor Error Register .............................................. 442 Power Management Registers ........................................................................... 443 13.8.1 Power Management PCI Configuration Registers (PM--D31:F0) ...................................................................................... 443 13.8.2 APM I/O Decode................................................................................... 450 13.8.3 Power Management I/O Registers ........................................................... 451 System Management TCO Registers................................................................... 469 13.9.1 TCO_RLD--TCO Timer Reload and Current Value Register .......................... 470 13.9.2 TCO_DAT_IN--TCO Data In Register ....................................................... 470 13.9.3 TCO_DAT_OUT--TCO Data Out Register .................................................. 470 13.9.4 TCO1_STS--TCO1 Status Register .......................................................... 470 13.9.5 TCO2_STS--TCO2 Status Register .......................................................... 472 13.9.6 TCO1_CNT--TCO1 Control Register ......................................................... 473 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 11 13.9.7 TCO2_CNT--TCO2 Control Register ......................................................... 473 13.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers ....................................... 474 13.9.9 TCO_WDCNT--TCO Watchdog Control Register ......................................... 474 13.9.10SW_IRQ_GEN--Software IRQ Generation Register ..................................... 474 13.9.11TCO_TMR--TCO Timer Initial Value Register ............................................. 475 13.10 General Purpose I/O Registers (D31:F0) ............................................................. 475 13.10.1GPIO_USE_SEL--GPIO Use Select Register ............................................... 476 13.10.2GP_IO_SEL--GPIO Input/Output Select Register ....................................... 476 13.10.3GP_LVL--GPIO Level for Input or Output Register...................................... 477 13.10.4GPO_BLINK--GPO Blink Enable Register................................................... 477 13.10.5GP_SER_BLINK--GP Serial Blink ............................................................. 478 13.10.6GP_SB_CMDSTS--GP Serial Blink Command Status ................................... 478 13.10.7GP_SB_DATA--GP Serial Blink Data......................................................... 479 13.10.8GPI_NMI_EN--GPI NMI Enable................................................................ 479 13.10.9GPI_NMI_STS--GPI NMI Status .............................................................. 479 13.10.10GPI_INV--GPIO Signal Invert Register.................................................... 480 13.10.11GPIO_USE_SEL2--GPIO Use Select 2 Register ......................................... 480 13.10.12GP_IO_SEL2--GPIO Input/Output Select 2 Register ................................. 480 13.10.13GP_LVL2--GPIO Level for Input or Output 2 Register................................ 481 13.10.15GP_IO_SEL3--GPIO Input/Output Select 3 Register ................................. 481 13.10.16GP_LVL3--GPIO Level for Input or Output 3 Register................................ 482 13.10.17GP_RST_SEL1 -- GPIO Reset Select....................................................... 482 13.10.18GP_RST_SEL2 -- GPIO Reset Select....................................................... 483 13.10.19GP_RST_SEL3 -- GPIO Reset Select....................................................... 483 13.11 GPIO Serial Expander MMIO Registers ................................................................ 484 13.11.1GSX_CxCAP -- GSX Capabilities Register 1............................................... 484 13.11.2GSX_CxCAP2 -- GSX Capabilities Register 2 ............................................. 485 13.11.3GSX_CxGPILVL -- GSX Input Level Register DW0...................................... 485 13.11.4GSX_CxGPILVL_DW1 -- GSX Input Level Register DW1 ............................. 485 13.11.5GSX_CxGPOLVL -- GSX Output Level Register DW0................................... 485 13.11.6GSX_CxGPOLVL_DW1 -- GSX Output Level Register DW1 .......................... 486 13.11.7GSX_CxCMD -- GSX Command Register .................................................. 486 14 12 SATA Controller Registers (D31:F2) ....................................................................... 487 14.1 PCI Configuration Registers (SATA-D31:F2) ........................................................ 487 14.1.1 VID--Vendor Identification Register (SATA--D31:F2) ................................. 488 14.1.2 DID--Device Identification Register (SATA--D31:F2) ................................. 488 14.1.4 PCISTS -- PCI Status Register (SATA-D31:F2) ......................................... 489 14.1.5 RID--Revision Identification Register (SATA--D31:F2) ............................... 490 14.1.6 PI--Programming Interface Register (SATA-D31:F2) ................................. 490 14.1.7 SCC--Sub Class Code Register (SATA-D31:F2) ......................................... 491 14.1.8 BCC--Base Class Code Register (SATA-D31:F2) .................................................................................... 491 14.1.9 PMLT--Primary Master Latency Timer Register (SATA-D31:F2) .................................................................................... 492 14.1.10HTYPE--Header Type (SATA-D31:F2) .................................................................................... 492 14.1.11PCMD_BAR--Primary Command Block Base Address Register (SATA-D31:F2)........................................................................ 492 14.1.12PCNL_BAR--Primary Control Block Base Address Register (SATA-D31:F2) .................................................................................... 492 14.1.13SCMD_BAR--Secondary Command Block Base Address Register (IDE D31:F2) ........................................................................... 493 14.1.14SCNL_BAR--Secondary Control Block Base Address Register (IDE D31:F2) ........................................................................... 493 14.1.15BAR -- Legacy Bus Master Base Address Register (SATA-D31:F2) .................................................................................... 493 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 14.2 14.3 14.4 15 14.1.16ABAR/SIDPBA1 -- AHCI Base Address Register/Serial ATA Index Data Pair Base Address (SATA-D31:F2).......................................... 494 14.1.17SVID--Subsystem Vendor Identification Register (SATA-D31:F2).................................................................................... 495 14.1.18SID--Subsystem Identification Register (SATA-D31:F2) ............................ 495 14.1.19CAP--Capabilities Pointer Register (SATA-D31:F2).................................... 495 14.1.20INT_LN--Interrupt Line Register (SATA-D31:F2) ...................................... 495 14.1.21INT_PN--Interrupt Pin Register (SATA-D31:F2)........................................ 495 14.1.22IDE_TIM -- IDE Timing Register (SATA-D31:F2) ...................................... 496 14.1.23SIDETIM--Slave IDE Timing Register (SATA-D31:F2)................................ 496 14.1.24SDMA_CNT--Synchronous DMA Control Register (SATA-D31:F2).................................................................................... 496 14.1.25SDMA_TIM--Synchronous DMA Timing Register (SATA-D31:F2).................................................................................... 497 14.1.26IDE_CONFIG--IDE I/O Configuration Register (SATA-D31:F2).................................................................................... 497 14.1.27PID--PCI Power Management Capability Identification Register (SATA-D31:F2) ....................................................................... 498 14.1.28PC--PCI Power Management Capabilities Register (SATA-D31:F2).................................................................................... 498 14.1.29PMCS--PCI Power Management Control and Status Register (SATA-D31:F2) ....................................................................... 499 14.1.30MSICI--Message Signaled Interrupt Capability Identification (SATA-D31:F2).................................................................................... 499 14.1.31MSIMC--Message Signaled Interrupt Message Control (SATA-D31:F2) ........ 500 14.1.33MSIMD--Message Signaled Interrupt Message Data (SATA-D31:F2)............ 501 14.1.34MAP--Address Map Register (SATA-D31:F2) ............................................ 502 14.1.35PCS--Port Control and Status Register (SATA-D31:F2).............................. 503 14.1.36SCLKCG--SATA Clock Gating Control Register .......................................... 504 14.1.37SGC--SATA General Configuration Register .............................................. 505 14.1.38FLRCID--FLR Capability ID (SATA-D31:F2) .............................................. 507 14.1.39FLRCLV--FLR Capability Length and Version (SATA-D31:F2) ...................... 507 14.1.40FLRC--FLR Control (SATA-D31:F2) ......................................................... 507 14.1.41ATC--APM Trapping Control Register (SATA-D31:F2) ................................ 508 14.1.42ATS--APM Trapping Status Register (SATA-D31:F2) ................................. 508 14.1.43SP Scratch Pad Register (SATA-D31:F2) ................................................. 508 14.1.44BFCS--BIST FIS Control/Status Register (SATA-D31:F2) ........................... 509 14.1.45BFTD1--BIST FIS Transmit Data1 Register (SATA-D31:F2) ........................ 510 14.1.46BFTD2--BIST FIS Transmit Data2 Register (SATA-D31:F2) ........................ 510 Bus Master IDE I/O Registers (D31:F2) .............................................................. 511 14.2.1 BMIC[P,S]--Bus Master IDE Command Register (D31:F2) .......................... 512 14.2.2 BMIS[P,S]--Bus Master IDE Status Register (D31:F2) ............................... 513 14.2.3 BMID[P,S]--Bus Master IDE Descriptor Table Pointer Register (D31:F2) ................................................................................ 513 14.2.4 AIR--AHCI Index Register (D31:F2) ........................................................ 514 14.2.5 AIDR--AHCI Index Data Register (D31:F2) .............................................. 514 Serial ATA Index/Data Pair Superset Registers .................................................... 514 14.3.1 SINDX - Serial ATA Index (D31:F2) ........................................................ 515 14.3.2 SDATA - Serial ATA Data (D31:F2) ......................................................... 515 AHCI Registers (D31:F2) .................................................................................. 519 14.4.1 AHCI Generic Host Control Registers (D31:F2) ......................................... 519 14.4.2 Port Registers (D31:F2) ........................................................................ 527 SATA Controller Registers (D31:F5)....................................................................... 541 15.1 PCI Configuration Registers (SATA-D31:F5)........................................................ 541 15.1.1 VID--Vendor Identification Register (SATA--D31:F5) ................................ 542 15.1.2 DID--Device Identification Register (SATA--D31:F5) ................................. 542 15.1.3 PCICMD--PCI Command Register (SATA-D31:F5)..................................... 543 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 13 15.1.4 15.1.5 15.1.6 15.1.7 15.1.8 15.2 15.3 16 14 PCISTS -- PCI Status Register (SATA-D31:F5) ......................................... 544 RID--Revision Identification Register (SATA--D31:F5) ............................... 545 PI--Programming Interface Register (SATA-D31:F5) ................................. 545 SCC--Sub Class Code Register (SATA-D31:F5) ......................................... 545 BCC--Base Class Code Register (SATA-D31:F5SATA-D31:F5)................................................................. 546 15.1.9 PMLT--Primary Master Latency Timer Register (SATA-D31:F5) .................................................................................... 546 15.1.10PCMD_BAR--Primary Command Block Base Address Register (SATA-D31:F5)........................................................................ 546 15.1.11PCNL_BAR--Primary Control Block Base Address Register (SATA-D31:F5) .................................................................................... 546 15.1.12SCMD_BAR--Secondary Command Block Base Address Register (IDE D31:F1) ........................................................................... 547 15.1.13SCNL_BAR--Secondary Control Block Base Address Register (IDE D31:F1) ........................................................................... 547 15.1.14BAR -- Legacy Bus Master Base Address Register (SATA-D31:F5) .................................................................................... 547 15.1.15SIDPBA -- SATA Index/Data Pair Base Address Register (SATA-D31:F5) .................................................................................... 548 15.1.16SVID--Subsystem Vendor Identification Register (SATA-D31:F5) .................................................................................... 548 15.1.17SID--Subsystem Identification Register (SATA-D31:F5)............................. 548 15.1.18CAP--Capabilities Pointer Register (SATA-D31:F5) .................................... 548 15.1.19INT_LN--Interrupt Line Register (SATA-D31:F5)....................................... 549 15.1.20INT_PN--Interrupt Pin Register (SATA-D31:F5) ........................................ 549 15.1.21IDE_TIM -- IDE Timing Register (SATA-D31:F5) ....................................... 549 15.1.22SDMA_CNT--Synchronous DMA Control Register (SATA-D31:F5) .................................................................................... 550 15.1.23SDMA_TIM--Synchronous DMA Timing Register (SATA-D31:F5) .................................................................................... 550 15.1.24IDE_CONFIG--IDE I/O Configuration Register (SATA-D31:F5) .................................................................................... 551 15.1.25PID--PCI Power Management Capability Identification Register (SATA-D31:F5)........................................................................ 551 15.1.26PC--PCI Power Management Capabilities Register (SATA-D31:F5) .................................................................................... 551 15.1.27PMCS--PCI Power Management Control and Status Register (SATA-D31:F5)........................................................................ 552 15.1.28MAP--Address Map Register (SATA-D31:F5)16 ......................................... 552 15.1.29PCS--Port Control and Status Register (SATA-D31:F5) .............................. 553 15.1.30SATACR0-- SATA Capability Register 0 (SATA-D31:F5) ............................. 554 15.1.31SATACR1-- SATA Capability Register 1 (SATA-D31:F5) ............................. 554 15.1.32FLRCID-- FLR Capability ID (SATA-D31:F5) ............................................. 554 15.1.33FLRCLV-- FLR Capability Length and Value (SATA-D31:F5) ........................ 555 15.1.34FLRCTRL-- FLR Control (SATA-D31:F5) ................................................... 555 15.1.35ATS--APM Trapping Status Register (SATA-D31:F5).................................. 555 15.1.36ATC--APM Trapping Control (SATA-D31:F5) ............................................. 556 Bus Master IDE I/O Registers (D31:F5)............................................................... 556 15.2.1 BMIC[P,S]--Bus Master IDE Command Register (D31:F5) .......................... 557 15.2.2 BMIS[P,S]--Bus Master IDE Status Register (D31:F5)................................ 557 15.2.3 BMID[P,S]--Bus Master IDE Descriptor Table Pointer Register (D31:F5)................................................................................. 558 Serial ATA Index/Data Pair Superset Registers..................................................... 558 15.3.1 SINDX--SATA Index Register (D31:F5) .................................................... 558 15.3.2 SDATA--SATA Index Data Register (D31:F5) ............................................ 559 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only)............................... 563 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 16.1 16.2 16.3 16.4 17 Register Attribute Definitions ............................................................................ 563 SCU Physical Function Configuration Registers..................................................... 565 16.2.1 PCI Standard Header Registers .............................................................. 567 16.2.2 PF Power Management Capability Structure ............................................. 574 16.2.3 PF MSI-X Capability Structure ................................................................ 576 16.2.4 PF PCI Express* Capability Structure ...................................................... 577 16.2.5 PF Advanced Error Reporting Extended Capability Structure ....................... 582 16.2.6 PF Alternative Routing ID Extended Capability Structure ............................ 586 16.2.7 PF SR-IOV Extended Capability Structure................................................. 587 16.2.8 PF TPH Requester Extended Capability Structure ...................................... 592 SCU Virtual Function Configuration Registers....................................................... 594 16.3.1 PCI Standard Header Registers .............................................................. 595 16.3.2 VF MSI-X Capability Structure ................................................................ 600 16.3.3 VF PCI Express* Capability Structure ...................................................... 602 16.3.4 VF Advanced Error Reporting Extended Capability Structure ....................... 606 16.3.5 Advanced Error Header Log Registers...................................................... 611 16.3.6 VF Alternative Routing ID Extended Capability Structure............................ 612 16.3.7 VF TPH Requester Extended Capability Structure ...................................... 613 SCU SGPIO Memory Mapped Registers ............................................................... 614 16.4.1 SGICR- SGPIO Interface Control Register ................................................ 614 16.4.2 SGPBR- SGPIO Programmable Blink Register............................................ 615 16.4.3 SGSDLR- SGPIO Start Drive Lower Register ............................................. 616 16.4.4 SGSDUR- SGPIO Start Drive Upper Register............................................. 617 16.4.5 SGSIDLR- SGPIO Input Data Lower Register ............................................ 618 16.4.6 SGSIDUR- SGPIO Input Data Upper Register............................................ 618 16.4.7 SGVSCR- SGPIO Vendor Specific Code Register ........................................ 618 16.4.8 SGODSR[0-7]--SGPIO Output Data Select Register[0-7] ........................... 620 EHCI Controller Registers (D29:F0, D26:F0) .......................................................... 621 17.1 USB EHCI Configuration Registers (USB EHCI--D29:F0, D26:F0) ........................................................................... 621 17.1.1 VID--Vendor Identification Register (USB EHCI--D29:F0, D26:F0) ................................................................ 622 17.1.2 DID--Device Identification Register (USB EHCI--D29:F0, D26:F0) ................................................................ 622 17.1.4 PCISTS--PCI Status Register (USB EHCI--D29:F0, D26:F0) ................................................................ 624 17.1.6 PI--Programming Interface Register (USB EHCI--D29:F0, D26:F0) ................................................................ 625 17.1.7 SCC--Sub Class Code Register (USB EHCI--D29:F0, D26:F0) ................................................................ 625 17.1.8 BCC--Base Class Code Register (USB EHCI--D29:F0, D26:F0) ................................................................ 625 17.1.9 PMLT--Primary Master Latency Timer Register (USB EHCI--D29:F0, D26:F0) ................................................................ 625 17.1.10HEADTYP--Header Type Register (USB EHCI--D29:F0, D26:F0) ................................................................ 626 17.1.11MEM_BASE--Memory Base Address Register (USB EHCI--D29:F0, D26:F0) ................................................................ 626 17.1.12SVID--USB EHCI Subsystem Vendor ID Register (USB EHCI--D29:F0, D26:F0) ................................................................ 626 17.1.13SID--USB EHCI Subsystem ID Register (USB EHCI--D29:F0, D26:F0) ................................................................ 627 17.1.14CAP_PTR--Capabilities Pointer Register (USB EHCI--D29:F0, D26:F0) ................................................................ 627 17.1.15INT_LN--Interrupt Line Register (USB EHCI--D29:F0, D26:F0) ................................................................ 627 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 15 17.2 18 16 17.1.16INT_PN--Interrupt Pin Register (USB EHCI--D29:F0, D26:F0)................................................................. 627 17.1.17PWR_CAPID--PCI Power Management Capability ID Register (USB EHCI--D29:F0, D26:F0) .................................................... 628 17.1.18NXT_PTR1--Next Item Pointer #1 Register (USB EHCI--D29:F0, D26:F0)................................................................. 628 17.1.19PWR_CAP--Power Management Capabilities Register (USB EHCI--D29:F0, D26:F0)................................................................. 628 17.1.20PWR_CNTL_STS--Power Management Control/ Status Register (USB EHCI--D29:F0, D26:F0) .......................................... 629 17.1.21DEBUG_CAPID--Debug Port Capability ID Register (USB EHCI--D29:F0, D26:F0)................................................................. 629 17.1.22NXT_PTR2--Next Item Pointer #2 Register (USB EHCI--D29:F0, D26:F0)................................................................. 630 17.1.23DEBUG_BASE--Debug Port Base Offset Register (USB EHCI--D29:F0, D26:F0)................................................................. 630 17.1.24USB_RELNUM--USB Release Number Register (USB EHCI--D29:F0, D26:F0)................................................................. 630 17.1.25FL_ADJ--Frame Length Adjustment Register (USB EHCI--D29:F0, D26:F0)................................................................. 630 17.1.26PWAKE_CAP--Port Wake Capability Register (USB EHCI--D29:F0, D26:F0)................................................................. 631 17.1.27LEG_EXT_CAP--USB EHCI Legacy Support Extended Capability Register (USB EHCI--D29:F0, D26:F0)...................................... 632 17.1.28LEG_EXT_CS--USB EHCI Legacy Support Extended Control / Status Register (USB EHCI--D29:F0, D26:F0) ............................. 632 17.1.29SPECIAL_SMI--Intel(R) Specific USB 2.0 Intel(R) SMI Register (USB EHCI--D29:F0, D26:F0) .................................................... 634 17.1.30ACCESS_CNTL--Access Control Register (USB EHCI--D29:F0, D26:F0)................................................................. 635 17.1.31EHCIIR1--EHCI Initialization Register 1 (USB EHCI--D29:F0, D26:F0)................................................................. 635 17.1.32EHCIIR2--EHCI Initialization Register 2 (USB EHCI--D29:F0, D26:F0) ......... 636 17.1.33FLR_CID--Function Level Reset Capability ID (USB EHCI--D29:F0, D26:F0)................................................................. 636 17.1.35FLR_CLV--Function Level Reset Capability Length and Version (USB EHCI--D29:F0, D26:F0)................................................................. 637 17.1.36FLR_CTRL--Function Level Reset Control Register (USB EHCI--D29:F0, D26:F0)................................................................. 637 17.1.37FLR_STAT--Function Level Reset Status Register (USB EHCI--D29:F0, D26:F0)................................................................. 638 17.1.38EHCIIR3--EHCI Initialization Register 3 (USB EHCI--D29:F0, D26:F0) ......... 638 17.1.39EHCIIR4--EHCI Initialization Register 4 (USB EHCI--D29:F0, D26:F0) ......... 638 Memory-Mapped I/O Registers .......................................................................... 639 17.2.1 Host Controller Capability Registers......................................................... 639 17.2.2 Host Controller Operational Registers ...................................................... 642 17.2.3 USB 2.0-Based Debug Port Registers ....................................................... 652 Intel(R) High Definition Audio Controller Registers (D27:F0).................................... 655 18.1 Intel(R) HD Audio PCI Configuration Space (Intel HD Audio--D27:F0) ....................... 655 18.1.1 VID--Vendor Identification Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 656 18.1.2 DID--Device Identification Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 657 18.1.3 PCICMD--PCI Command Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 657 18.1.4 PCISTS--PCI Status Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 658 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 18.1.5 RID--Revision Identification Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 658 18.1.6 PI--Programming Interface Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 658 18.1.8 BCC--Base Class Code Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 659 18.1.9 CLS--Cache Line Size Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 659 18.1.10LT--Latency Timer Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 659 18.1.11HEADTYP--Header Type Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 659 18.1.13HDBARU--Intel(R) HD Audio Upper Base Address Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 660 18.1.14SVID--Subsystem Vendor Identification Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 660 18.1.16CAPPTR--Capabilities Pointer Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 661 18.1.17INTLN--Interrupt Line Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 661 18.1.18INTPN--Interrupt Pin Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 661 18.1.20HDINIT1--Intel(R) High Definition Audio Initialization Register 1 (Intel(R) High Definition Audio Controller--D27:F0)..................................... 662 18.1.21PID--PCI Power Management Capability ID Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 662 18.1.22PC--Power Management Capabilities Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 662 18.1.23PCS--Power Management Control and Status Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 663 18.1.24MID--MSI Capability ID Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 663 18.1.25MMC--MSI Message Control Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 664 18.1.26MMLA--MSI Message Lower Address Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 664 18.1.27MMUA--MSI Message Upper Address Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 664 18.1.28MMD--MSI Message Data Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 664 18.1.30PXC--PCI Express* Capabilities Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 665 18.1.31DEVCAP--Device Capabilities Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 665 18.1.32DEVC--Device Control Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 666 18.1.33DEVS--Device Status Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 666 18.1.34VCCAP--Virtual Channel Enhanced Capability Header (Intel(R) HD Audio Controller--D27:F0) ..................................................... 667 18.1.35PVCCAP1--Port VC Capability Register 1 (Intel(R) HD Audio Controller--D27:F0) ..................................................... 667 18.1.36PVCCAP2 -- Port VC Capability Register 2 (Intel(R) HD Audio Controller--D27:F0) ..................................................... 667 18.1.37PVCCTL -- Port VC Control Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 668 18.1.38PVCSTS--Port VC Status Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 668 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 17 18.2 18 18.1.39VC0CAP--VC0 Resource Capability Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 668 18.1.40VC0CTL--VC0 Resource Control Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 669 18.1.41VC0STS--VC0 Resource Status Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 669 18.1.42VCiCAP--VCi Resource Capability Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 669 18.1.43VCiCTL--VCi Resource Control Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 670 18.1.44VCiSTS--VCi Resource Status Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 670 18.1.45RCCAP--Root Complex Link Declaration Enhanced Capability Header Register (Intel(R) HD Audio Controller--D27:F0)................ 670 18.1.46ESD--Element Self Description Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 671 18.1.47L1DESC--Link 1 Description Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 671 18.1.48L1ADDL--Link 1 Lower Address Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 671 18.1.49L1ADDU--Link 1 Upper Address Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 671 Intel(R) HD Audio Memory Mapped Configuration Registers (Intel(R) HD Audio-- D27:F0)................................................................ 672 18.2.1 GCAP--Global Capabilities Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 675 18.2.2 VMIN--Minor Version Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 675 18.2.3 VMAJ--Major Version Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 676 18.2.4 OUTPAY--Output Payload Capability Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 676 18.2.5 INPAY--Input Payload Capability Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 676 18.2.6 GCTL--Global Control Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 677 18.2.8 STATESTS--State Change Status Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 678 18.2.9 GSTS--Global Status Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 678 18.2.11INSTRMPAY--Input Stream Payload Capability (Intel(R) HD Audio Controller--D27:F0) ..................................................... 679 18.2.12INTCTL--Interrupt Control Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 679 18.2.13INTSTS--Interrupt Status Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 680 18.2.15SSYNC--Stream Synchronization Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 681 18.2.16CORBLBASE--CORB Lower Base Address Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 681 18.2.17CORBUBASE--CORB Upper Base Address Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 682 18.2.18CORBWP--CORB Write Pointer Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 682 18.2.19CORBRP--CORB Read Pointer Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 682 18.2.21CORBST--CORB Status Register (Intel(R) HD Audio Controller--D27:F0) ..................................................... 683 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 18.2.22CORBSIZE--CORB Size Register Intel(R) HD Audio Controller--D27:F0using) .............................................. 683 18.2.24RIRBUBASE--RIRB Upper Base Address Register (Intel(R) HD Audio Controller--D27:F0) .................................................... 684 18.2.25RIRBWP--RIRB Write Pointer Register (Intel(R) HD Audio Controller--D27:F0) .................................................... 684 18.2.27RIRBCTL--RIRB Control Register (Intel(R) HD Audio Controller--D27:F0) .................................................... 685 18.2.29RIRBSIZE--RIRB Size Register (Intel(R) HD Audio Controller--D27:F0) .................................................... 686 18.2.30IC--Immediate Command Register (Intel(R) HD Audio Controller--D27:F0) .................................................... 686 18.2.31IR--Immediate Response Register (Intel(R) HD Audio Controller--D27:F0) .................................................... 687 18.2.32ICS--Immediate Command Status Register (Intel(R) HD Audio Controller--D27:F0) .................................................... 687 18.2.33DPLBASE--DMA Position Lower Base Address Register (Intel(R) HD Audio Controller--D27:F0) .................................................... 687 18.2.34DPUBASE--DMA Position Upper Base Address Register (Intel(R) HD Audio Controller--D27:F0) .................................................... 688 18.2.35SDCTL--Stream Descriptor Control Register (Intel(R) HD Audio Controller--D27:F0) .................................................... 688 18.2.36SDSTS--Stream Descriptor Status Register (Intel(R) HD Audio Controller--D27:F0) .................................................... 689 18.2.37SDLPIB--Stream Descriptor Link Position in Buffer Register (Intel(R) High Definition Audio Controller--D27:F0) ........................ 690 18.2.38SDCBL--Stream Descriptor Cyclic Buffer Length Register (Intel(R) High Definition Audio Controller--D27:F0) .................................... 690 18.2.39SDLVI--Stream Descriptor Last Valid Index Register (Intel(R) High Definition Audio Controller--D27:F0) .................................... 691 18.2.40SDFIFOW--Stream Descriptor FIFO Watermark Register (Intel(R) HD Audio Controller--D27:F0) .................................................... 691 18.2.41ISDFIFOS--Stream Descriptor FIFO Size Register - Input Streams (Intel(R) High Definition Audio Controller--D27:F0)........................ 692 18.2.42SDFIFOS--Stream Descriptor FIFO Size Register - Output Streams (Intel(R) High Definition Audio Controller--D27:F0)........................ 692 18.2.43SDFMT--Stream Descriptor Format Register (Intel(R) High Definition Audio Controller--D27:F0) .................................... 693 18.2.44SDBDPL--Stream Descriptor Buffer Descriptor List Pointer Lower Base Address Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................................................... 694 19 SMBus Controller Registers (D31:F3) .................................................................... 695 19.1 PCI Configuration Registers (SMBus--D31:F3)..................................................... 695 19.1.1 VID--Vendor Identification Register (SMBus--D31:F3)............................... 695 19.1.2 DID--Device Identification Register (SMBus--D31:F3) ............................... 696 19.1.3 PCICMD--PCI Command Register (SMBus--D31:F3) .................................. 696 19.1.4 PCISTS--PCI Status Register (SMBus--D31:F3) ........................................ 697 19.1.5 RID--Revision Identification Register (SMBus--D31:F3) ............................. 697 19.1.6 PI--Programming Interface Register (SMBus--D31:F3) .............................. 698 19.1.7 SCC--Sub Class Code Register (SMBus--D31:F3)...................................... 698 19.1.8 BCC--Base Class Code Register (SMBus--D31:F3) .................................... 698 19.1.9 SMBMBAR0--D31_F3_SMBus Memory Base Address 0 (SMBus--D31:F3) ..... 698 19.1.10SMBMBAR1--D31_F3_SMBus Memory Base Address 1 (SMBus--D31:F3) ..... 699 19.1.11SMB_BASE--SMBus Base Address Register (SMBus--D31:F3)................................................................................. 699 19.1.12SVID--Subsystem Vendor Identification Register (SMBus--D31:F2/F4) ............................................................................ 699 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 19 19.1.13SID--Subsystem Identification Register (SMBus--D31:F2/F4)............................................................................. 699 19.1.15INT_PN--Interrupt Pin Register (SMBus--D31:F3) ..................................... 700 19.1.16HOSTC--Host Configuration Register (SMBus--D31:F3).............................. 700 19.2.2 HST_CNT--Host Control Register (SMBus--D31:F3) ................................... 703 19.2.3 HST_CMD--Host Command Register (SMBus--D31:F3) .............................. 704 19.2.4 XMIT_SLVA--Transmit Slave Address Register (SMBus--D31:F3) ................................................................................. 704 19.2.5 HST_D0--Host Data 0 Register (SMBus--D31:F3) ..................................... 704 19.2.6 HST_D1--Host Data 1 Register (SMBus--D31:F3) ..................................... 704 19.2.7 Host_BLOCK_DB--Host Block Data Byte Register (SMBus--D31:F3) ................................................................................. 705 19.2.8 PEC--Packet Error Check (PEC) Register (SMBus--D31:F3) ................................................................................. 705 19.2.9 RCV_SLVA--Receive Slave Address Register (SMBus--D31:F3) ................................................................................. 705 19.2.10SLV_DATA--Receive Slave Data Register (SMBus--D31:F3) ........................ 706 19.2.11AUX_STS--Auxiliary Status Register (SMBus--D31:F3) .............................. 706 19.2.12AUX_CTL--Auxiliary Control Register (SMBus--D31:F3) ............................. 706 19.2.13SMLINK_PIN_CTL--SMLink Pin Control Register (SMBus--D31:F3) ................................................................................. 707 19.2.14SMBus_PIN_CTL--SMBus Pin Control Register (SMBus--D31:F3) ................................................................................. 707 19.2.15SLV_STS--Slave Status Register (SMBus--D31:F3) ................................... 708 19.2.16SLV_CMD--Slave Command Register (SMBus--D31:F3) ............................. 708 19.2.17NOTIFY_DADDR--Notify Device Address Register (SMBus--D31:F3) ................................................................................. 709 19.2.19NOTIFY_DHIGH--Notify Data High Byte Register (SMBus--D31:F3) ................................................................................. 709 20 20 PCI Express* Configuration Registers .................................................................... 711 20.1 PCI Express* Configuration Registers (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) ................................................... 711 20.1.1 VID--Vendor Identification Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ............................... 713 20.1.2 DID--Device Identification Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ............................... 713 20.1.5 RID--Revision Identification Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ............................... 715 20.1.7 SCC--Sub Class Code Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ............................... 716 20.1.8 BCC--Base Class Code Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ............................... 716 20.1.9 CLS--Cache Line Size Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ............................... 716 20.1.10PLT--Primary Latency Timer Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ............................... 716 20.1.11HEADTYP--Header Type Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ............................... 717 20.1.12BNUM--Bus Number Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ............................... 717 20.1.13SLT--Secondary Latency Timer (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ............................... 717 20.1.14IOBL--I/O Base and Limit Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ............................... 717 20.1.15SSTS--Secondary Status Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ............................... 718 20.1.16MBL--Memory Base and Limit Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ............................... 718 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 20.1.17PMBL--Prefetchable Memory Base and Limit Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)............................... 719 20.1.18PMBU32--Prefetchable Memory Base Upper 32 Bits Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) .................. 719 20.1.19PMLU32--Prefetchable Memory Limit Upper 32 Bits Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) .................. 719 20.1.20CAPP--Capabilities List Pointer Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)............................... 720 20.1.21INTR--Interrupt Information Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)............................... 720 20.1.22BCTRL--Bridge Control Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)............................... 721 20.1.23CLIST--Capabilities List Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 721 20.1.25DCAP--Device Capabilities Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 722 20.1.26DCTL--Device Control Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 722 20.1.27DSTS--Device Status Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 723 20.1.28LCAP--Link Capabilities Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 724 20.1.29LCTL--Link Control Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 726 20.1.30LSTS--Link Status Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 727 20.1.31SLCAP--Slot Capabilities Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 728 20.1.32SLCTL--Slot Control Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 728 20.1.33SLSTS--Slot Status Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 729 20.1.34RCTL--Root Control Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 730 20.1.35RSTS--Root Status Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 730 20.1.36DCAP2--Device Capabilities 2 Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 731 20.1.37DCTL2--Device Control 2 Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 731 20.1.39LSTS2--Link Status 2 Register (PCI Express*-- D28:F0/F1/F2/F3/F4/F5/F6/F7)....................................... 732 20.1.40MID--Message Signaled Interrupt Identifiers Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 732 20.1.41MC--Message Signaled Interrupt Message Control Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 733 20.1.42MA--Message Signaled Interrupt Message Address Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................... 733 20.1.43MD--Message Signaled Interrupt Message Data Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 733 20.1.44SVCAP--Subsystem Vendor Capability Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 733 20.1.45SVID--Subsystem Vendor Identification Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 734 20.1.46PMCAP--Power Management Capability Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 734 20.1.47PMC--PCI Power Management Capabilities Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 734 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 21 20.1.49MPC2--Miscellaneous Port Configuration Register 2 (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................ 735 20.1.50MPC--Miscellaneous Port Configuration Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................ 736 20.1.51SMSCS--SMI/SCI Status Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................ 738 20.1.52RPDCGEN--Root Port Dynamic Clock Gating Enable (PCI Express-D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................... 739 20.1.53PECR1--PCI Express* Configuration Register 1 (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................ 739 20.1.55UES--Uncorrectable Error Status Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................ 740 20.1.57UEV -- Uncorrectable Error Severity (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................ 742 20.1.58CES -- Correctable Error Status Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................ 742 20.1.59CEM -- Correctable Error Mask Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................ 743 20.1.60AECC -- Advanced Error Capabilities and Control Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................ 743 20.1.61RES -- Root Error Status Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................ 744 20.1.62PEETM -- PCI Express* Extended Test Mode Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................ 744 21 High Precision Event Timer Registers..................................................................... 745 21.1 Memory Mapped Registers ................................................................................ 745 21.1.1 GCAP_ID--General Capabilities and Identification Register ......................... 746 21.1.3 GINTR_STA--General Interrupt Status Register......................................... 747 21.1.5 TIMn_CONF--Timer n Configuration and Capabilities Register ..................... 748 21.1.6 TIMn_COMP--Timer n Comparator Value Register ..................................... 750 21.1.7 TIMERn_PROCMSG_ROUT-- Timer n Processor Message Interrupt Rout Register ................................... 751 22 Serial Peripheral Interface (SPI) ........................................................................... 753 22.1 Serial Peripheral Interface Memory Mapped Configuration Registers........................ 753 22.1.1 BFPR -BIOS Flash Primary Region Register (SPI Memory Mapped Configuration Registers).......................................... 754 22.1.3 HSFC--Hardware Sequencing Flash Control Register (SPI Memory Mapped Configuration Registers).......................................... 756 22.1.4 FADDR--Flash Address Register (SPI Memory Mapped Configuration Registers).......................................... 756 22.1.6 FDATAN--Flash Data [N] Register (SPI Memory Mapped Configuration Registers).......................................... 757 22.1.8 FREG0--Flash Region 0 (Flash Descriptor) Register (SPI Memory Mapped Configuration Registers).......................................... 758 22.1.10FREG2--Flash Region 2 (Intel(R) ME) Register (SPI Memory Mapped Configuration Registers).......................................... 759 22.1.11FREG3--Flash Region 3 (GbE) Register (SPI Memory Mapped Configuration Registers).......................................... 759 22.1.12FREG4--Flash Region 4 (Platform Data) Register (SPI Memory Mapped Configuration Registers).......................................... 760 22.1.13PR0--Protected Range 0 Register (SPI Memory Mapped Configuration Registers).......................................... 760 22.1.14PR1--Protected Range 1 Register (SPI Memory Mapped Configuration Registers).......................................... 761 22.1.15PR2--Protected Range 2 Register (SPI Memory Mapped Configuration Registers).......................................... 761 22 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 22.2 22.4 23 22.1.17PR4--Protected Range 4 Register (SPI Memory Mapped Configuration Registers) ......................................... 762 22.1.19SSFC--Software Sequencing Flash Control Register (SPI Memory Mapped Configuration Registers) ......................................... 764 22.1.20PREOP--Prefix Opcode Configuration Register (SPI Memory Mapped Configuration Registers) ......................................... 765 22.1.21OPTYPE--Opcode Type Configuration Register (SPI Memory Mapped Configuration Registers) ......................................... 765 22.1.22OPMENU--Opcode Menu Configuration Register (SPI Memory Mapped Configuration Registers) ......................................... 766 22.1.23FDOC--Flash Descriptor Observability Control Register (SPI Memory Mapped Configuration Registers) ......................................... 766 22.1.24FDOD--Flash Descriptor Observability Data Register (SPI Memory Mapped Configuration Registers) ......................................... 767 22.1.25AFC--Additional Flash Control Register (SPI Memory Mapped Configuration Registers) ......................................... 767 22.1.26LVSCC-- Host Lower Vendor Specific Component Capabilities Register (SPI Memory Mapped Configuration Registers) ......................................... 767 22.1.27UVSCC-- Host Upper Vendor Specific Component Capabilities Register (SPI Memory Mapped Configuration Registers) ......................................... 768 22.1.28FPB -- Flash Partition Boundary (SPI Memory Mapped Configuration Registers) ......................................... 769 22.1.29SRDL -- Soft Reset Data Lock (SPI Memory Mapped Configuration Registers) ......................................... 770 22.1.30SRDC -- Soft Reset Data Control (SPI Memory Mapped Configuration Registers) ......................................... 770 22.1.31SRD -- Soft Reset Data (SPI Memory Mapped Configuration Registers) ......................................... 770 Flash Descriptor Records .................................................................................. 770 GbE SPI Flash Program Registers....................................................................... 771 22.4.2 HSFS--Hardware Sequencing Flash Status Register (GbE LAN Memory Mapped Configuration Registers) .................................. 772 22.4.3 HSFC--Hardware Sequencing Flash Control Register (GbE LAN Memory Mapped Configuration Registers) .................................. 773 22.4.4 FADDR--Flash Address Register (GbE LAN Memory Mapped Configuration Registers) .................................. 773 22.4.6 FRAP--Flash Regions Access Permissions Register (GbE LAN Memory Mapped Configuration Registers) .................................. 774 22.4.8 FREG1--Flash Region 1 (BIOS Descriptor) Register (GbE LAN Memory Mapped Configuration Registers) .................................. 775 22.4.9 FREG2--Flash Region 2 (Intel(R) ME) Register (GbE LAN Memory Mapped Configuration Registers) .................................. 775 22.4.11PR0--Protected Range 0 Register (GbE LAN Memory Mapped Configuration Registers) .................................. 776 22.4.13SSFS--Software Sequencing Flash Status Register (GbE LAN Memory Mapped Configuration Registers) .................................. 777 22.4.14SSFC--Software Sequencing Flash Control Register (GbE LAN Memory Mapped Configuration Registers) .................................. 778 22.4.15PREOP--Prefix Opcode Configuration Register (GbE LAN Memory Mapped Configuration Registers) .................................. 779 22.4.16OPTYPE--Opcode Type Configuration Register (GbE LAN Memory Mapped Configuration Registers) .................................. 779 22.4.17OPMENU--Opcode Menu Configuration Register (GbE LAN Memory Mapped Configuration Registers) .................................. 780 Thermal Sensor Registers (D31:F6) ....................................................................... 781 23.1 PCI Bus Configuration Registers ........................................................................ 781 23.1.1 VID--Vendor Identification Register ........................................................ 782 23.1.2 DID--Device Identification Register......................................................... 782 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 23 23.2 24 24 23.1.3 CMD--Command Register ...................................................................... 782 23.1.4 STS--Status Register ............................................................................ 783 23.1.5 RID--Revision Identification Register ....................................................... 783 23.1.6 PI-- Programming Interface Register ....................................................... 783 23.1.7 SCC--Sub Class Code Register................................................................ 784 23.1.8 BCC--Base Class Code Register .............................................................. 784 23.1.9 CLS--Cache Line Size Register................................................................ 784 23.1.10LT--Latency Timer Register .................................................................... 784 23.1.11HTYPE--Header Type Register ................................................................ 784 23.1.12TBAR--Thermal Base Register ................................................................ 785 23.1.13TBARH--Thermal Base High DWord Register ............................................. 785 23.1.14SVID--Subsystem Vendor ID Register ..................................................... 785 23.1.16CAP_PTR --Capabilities Pointer Register ................................................... 786 23.1.17Offset 3Ch - INTLN--Interrupt Line Register ............................................. 786 23.1.18INTPN--Interrupt Pin Register ................................................................ 786 23.1.19TBARB--BIOS Assigned Thermal Base Address Register ............................. 787 23.1.20TBARBH--BIOS Assigned Thermal Base High DWord Register...................... 787 23.1.21PID--PCI Power Management Capability ID Register .................................. 787 23.1.22PC--Power Management Capabilities Register ........................................... 788 23.1.23PCS--Power Management Control And Status Register ............................... 788 Thermal Memory Mapped Configuration Registers (Thermal Sensor - D31:F26) ............................................................................. 789 23.2.1 TSIU--Thermal Sensor In Use Register .................................................... 789 23.2.3 TSS--Thermal Sensor Status Register...................................................... 790 23.2.4 TSTR -- Thermal Sensor Thermometer Read Register ................................ 790 23.2.5 TSTTP--Thermal Sensor Temperature Trip Point Register ........................... 791 23.2.6 TSCO--Thermal Sensor Catastrophic Lock-Down Register........................... 791 23.2.7 TSES--Thermal Sensor Error Status Register ............................................ 791 23.2.8 TSGPEN--Thermal Sensor General Purpose Event Enable Register ............... 792 23.2.9 TSPC--Thermal Sensor Policy Control Register .......................................... 793 23.2.10PTA--PCH Temperature Adjust Register ................................................... 794 23.2.11TRC--Thermal Reporting Control Register................................................. 794 23.2.12AE--Alert Enable Register ...................................................................... 795 23.2.13PTL--Processor Temperature Limit Register .............................................. 795 23.2.14PTV--Processor Temperature Value Register ............................................. 795 23.2.15TT--Thermal Throttling Register.............................................................. 795 23.2.16PHL--PCH Hot Level Register .................................................................. 796 23.2.17TSPIEN--Thermal Sensor PCI Interrupt Enable Register ............................. 796 23.2.18TSLOCK--Thermal Sensor Register Lock Control Register ........................... 797 23.2.19TTC2--Thermal Compares 2 Register ....................................................... 797 23.2.20DTV--DIMM Temperature Values Register ................................................ 797 23.2.21ITV--Internal Temperature Values Register .............................................. 798 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) ............................. 799 24.1 First Intel(R) Management Engine Interface (Intel MEI) Configuration Registers (Intel MEI 1 -- D22:F0) .................................................................................... 799 24.1.1 PCI Configuration Registers (Intel MEI 1-- D22:F0) ................................... 799 24.1.2 MEI0_MBAR--MEI 1MMIO Registers (SRV/WS SKUs Only) .......................... 808 24.2 Second Host Embedded Controller Interface (Intel MEI 2) Configuration Registers (Intel MEI 2--D22:F1) ........................................................................ 810 24.2.1 PCI Configuration Registers (Intel MEI 2 -- D22:F0) .................................. 810 24.2.2 MEI1_MBAR--Intel MEI 2MMIO Registers ................................................. 818 24.3 IDE Function for Remote Boot and Installations PT IDER Registers (IDER -- D22:F2)................................................................... 820 24.3.1 PCI Configuration Registers (IDER--D22:f2) ............................................. 820 24.3.2 IDER BAR0 Registers............................................................................. 827 24.3.3 IDER BAR1 Registers............................................................................. 836 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 24.4 25 24.3.4 IDER BAR4 Registers ............................................................................ 837 Serial Port for Remote Keyboard and Text (KT) Redirection (KT -- D22:F3) ............................................................................... 842 24.4.1 PCI Configuration Registers (KT -- D22:F3) ............................................. 842 24.4.2 KT IO/ Memory Mapped Device Registers................................................. 848 PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) ............................................................................................. 853 25.1 PCI Express* Upstream Configuration Registers (PCI Express*--D0:F0).................. 853 25.1.1 VID--Vendor Identification Register (PCI Express*--D0:F0) ......................................................................... 855 25.1.2 DID--Device Identification Register (PCI Express*--D0:F0) ......................................................................... 855 25.1.3 PCICMD--PCI Command Register (PCI Express*--D0:F0) ......................................................................... 856 25.1.5 RID--Revision Identification Register (PCI Express*--D0:F0) ......................................................................... 858 25.1.6 PI--Programming Interface Register (PCI Express*--D0:F0) ......................................................................... 858 25.1.7 CLS--Cache Line Size Register (PCI Express*--D0:F0) ......................................................................... 858 25.1.8 PLT--Primary Latency Timer Register (PCI Express*--D0:F0) ......................................................................... 858 25.1.10EXPPTMBAR_U--Express Port Memory Base Address Register (PCI Express*--D0:F0) ............................................................. 859 25.1.11PRIBUS--Primiary Bus Number Register (PCI Express*--D0:F0........................................................................... 859 25.1.12SECBUS--Secondary Bus Number Register (PCI Express*--D0:F0) ......................................................................... 860 25.1.13SUBBus--Subordinate Bus Number Register (PCI Express*--D0:F0) ......................................................................... 860 25.1.14IOBL--I/O Base Register (PCI Express*--D0:F0) ......................................................................... 860 25.1.15IOLIMIT--I/O Limit Register (PCI Express*--D0:F0) ......................................................................... 860 25.1.16SSTS--Secondary Status Register (PCI Express*--D0:F0).......................... 861 25.1.18MEMLIMIT--Memory Limit Register (PCI Express*--D0:F0) ......................................................................... 862 25.1.19PFBASE--Prefetchable Memory Base (PCI Express*--D0:F0) ......................................................................... 862 25.1.20PFLIMIT--Prefetchable Limit Register (PCI Express*--D0:F0) ......................................................................... 862 25.1.21PMBU32--Prefetchable Memory Base Upper 32 Bits Register (PCI Express*--D0:F0) ............................................................. 863 25.1.22PMLU32--Prefetchable Memory Limit Upper 32 Bits Register (PCI Express*--D0:F0) ............................................................. 863 25.1.23CAPP--Capabilities List Pointer Register (PCI Express*--D0:F0) ......................................................................... 863 25.1.24INTR--Interrupt Information Register (PCI Express*--D0:F0) ......................................................................... 863 25.1.25BCTRL--Bridge Control Register (PCI Express*--D0:F0) ......................................................................... 864 25.1.26CLIST--Capabilities List Register (PCI Express*--D0:F0) ......................................................................... 865 25.1.27XCAP--PCI Express* Capabilities Register (PCI Express*--D0:F0) ......................................................................... 865 25.1.28DCAP--Device Capabilities Register (PCI Express*--D0:F0) ......................................................................... 866 25.1.29DCTL--Device Control Register (PCI Express*--D0:F0) .............................. 866 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 25 25.1.30DSTS--Device Status Register (PCI Express*--D0:F0) ............................... 867 25.1.31LCAP--Link Capabilities Register (PCI Express*--D0:F0) .......................................................................... 867 25.1.32LCTL--Link Control Register (PCI Express*--D:F0) .................................... 868 25.1.33LSTS--Link Status Register (PCI Express*--D0:F0) .......................................................................... 869 25.1.34DCAP2--Device Capabilities 2 Register (PCI Express*--D0:F0) .......................................................................... 870 25.1.35DCTL2--Device Control 2 Register (PCI Express*--D0:F0) .......................................................................... 871 25.1.36DEVSTS2--Device Status 2 Register (PCI Express*--D0:F0) .......................................................................... 871 25.1.37L2--Link Control 2 Register (PCI Express*--D0:F0) ................................... 872 25.1.38LINKSTS2--Link STatus2 Register (PCI Express*--D0:F0) .......................................................................... 873 25.1.39PMCAP--Power Management Capability Register (PCI Express*--D0:F0) .......................................................................... 873 25.1.40PMC--PCI Power Management Capabilities Register (PCI Express*--D0:F0) .......................................................................... 873 25.1.41PMCSR--PCI Power Management Control and Status Register (PCI Express*--D0:F0).............................................................. 874 25.1.42PMBSE--Power Management Bridge Support Extensions Register (PCI Express*--D0:F0).............................................................. 874 25.1.43SVCAP--Subsystem Capability List Register (PCI Express*--D0:F0) .......................................................................... 875 25.1.44SVID--Subsystem Vendor ID Register (PCI Express*--D0:F0) .......................................................................... 875 25.1.45SVID--Subsystem ID Register (PCI Express*--D0:F0) .......................................................................... 875 25.1.46AERCAPHDR--Advanced Error Reporting Capabilities Header Register (PCI Express*--D0:F0)................................................... 875 25.1.49UEV -- Uncorrectable Error Severity (PCI Express*--D0:F0) .......................................................................... 877 25.1.50CES--Correctable Error Status Register (PCI Express*--D0:F0) .......................................................................... 878 25.1.51CEM--Correctable Error Mask Register (PCI Express*--D0:F0) .......................................................................... 879 25.1.52AECC -- Advanced Error Capabilities and Control Register (PCI Express*--D0:F0) .......................................................................... 879 25.1.53AEHRDLOG [1-4]-- Advanced Error Header Log (PCI Express*--D0:F0) .......................................................................... 880 25.1.54ERRUNCDETMSK-- Uncorrectable Error Detect Mask Register (PCI Express*--D0:F0) .......................................................................... 880 25.1.55ERRCORDETMSK-- Correctable Error Detect Mask Register (PCI Express*--D0:F0) .......................................................................... 881 25.1.57MCSTCAP--Multicast Capability Register (PCI Express*--D0:F0) .......................................................................... 882 25.1.58MCSTCTL--Multicast Control Register (PCI Express*--D0:F0) .......................................................................... 882 25.1.60MCSTUBAR--Multicast Upper Base Address Register (PCI Express*--D0:F0) .......................................................................... 883 25.1.61MCSTRCV--Multicast Receive Register (PCI Express*--D0:F0) .......................................................................... 883 25.1.62MCSTRCV2--Multicast Receive 2 Register (PCI Express*--D0:F0) .......................................................................... 883 25.1.64MCSTBLKALL2--Multicast Block All 2 Register (PCI Express*--D0:F0) .......................................................................... 884 25.1.65MCSTBLKUT--Multicast Block Untranslated Register (PCI Express*--D0:F0) .......................................................................... 884 26 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 25.1.66MCSTBLKUT2--Multicast Block Untranslated 2 Register (PCI Express*--D0:F0) ......................................................................... 884 25.1.68MCSTUOLBAR--Multicast Upper Overlay Base Address Register (PCI Express*--D0:F0) ............................................................. 885 26 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only)............................................................................................. 887 26.1 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (PCI Express*--B0:D17:F0/Bn+1:D8:F0) ........................................................... 887 26.2 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (PCI Express*--B0:D17:F0/Bn+1:D8:F0) ........................................................... 887 26.2.1 VID--Vendor Identification Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 889 26.2.2 DID--Device Identification Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 889 26.2.6 PI--Programming Interface Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 892 26.2.7 CLS--Cache Line Size Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 892 26.2.8 PLT--Primary Latency Timer Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 892 26.2.9 HEADTYP--Header Type Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 893 26.2.10PRIBUS--Primiary Bus Number Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 893 26.2.11SECBUS--Secondary Bus Number Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 893 26.2.12SUBBus--Subordinate Bus Number Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 893 26.2.13IOBL--I/O Base Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 894 26.2.14IOBL--I/O Limit Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 894 26.2.15SSTS--Secondary Status Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 894 26.2.16MBL--Memory Base Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 895 26.2.17MBL--Memory Limit Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 895 26.2.19PMBL--Prefetchable Limit Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 896 26.2.20PMBU32--Prefetchable Memory Base Upper 32 Bits Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .. 896 26.2.21PMLU32--Prefetchable Memory Limit Upper 32 Bits Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .. 896 26.2.22CAPP--Capabilities List Pointer Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 897 26.2.23INTR--Interrupt Information Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 897 26.2.24BCTRL--Bridge Control Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 897 26.2.26XCAP--PCI Express* Capabilities Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 899 26.2.27DCAP--Device Capabilities Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 899 26.2.28DCTL--Device Control Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 900 26.2.29DSTS--Device Status Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 901 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 27 26.2.30LCAP--Link Capabilities Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0)............... 901 26.2.31LCTL--Link Control Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0)............... 902 26.2.32LSTS--Link Status Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0)............... 903 26.2.33ROOTCTL--Root Control Register (Virtual Root Port--B0:D17:F0)............................................................... 903 26.2.34ROOTCAP--Root Capabilities Register (Virtual Root Port--B0:D17:F0)............................................................... 904 26.2.35ROOTSTS--Root Status Register (Virtual Root Port--B0:D17:F0)............................................................... 904 26.2.37DCTL2--Device Control 2 Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0)............... 905 26.2.38DEVSTS2--Device Status 2 Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0)............... 906 26.2.40LINKSTS2--Link STatus2 Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0)............... 907 26.2.41PMCAP--Power Management Capability Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0)............... 907 26.2.42PMC--PCI Power Management Capabilities Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0)............... 907 26.2.43PMCSR--PCI Power Management Control and Status Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .. 908 26.2.44PMBSE--Power Management Bridge Support Extensions Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .. 908 26.2.45SVCAP--Subsystem Capability List Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0)............... 909 26.2.46SVID--Subsystem Vendor ID Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0)............... 909 26.2.47SVID--Subsystem ID Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0)............... 909 26.2.48MSICAPLST--MSI Capability List Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0)............... 909 26.2.49MSICTL--MSI Message Control Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0)............... 910 26.2.51MSIDATA--MSI Message Data Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0)............... 911 26.2.52AERCAPHDR--Advanced Error Reporting Capabilities Header (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0).... 911 26.2.53UES--Uncorrectable Error Status Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0)............... 912 26.2.54UEM--Uncorrectable Error Mask (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0)............... 913 26.2.55UEV -- Uncorrectable Error Severity (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0)............... 914 26.2.56CES--Correctable Error Status Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0)............... 915 26.2.57CEM--Correctable Error Mask Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0)............... 915 26.2.58AECC--Advanced Error Capabilities and Control Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0)............... 916 26.2.59AEHRDLOG [1-4]--Advanced Error Header Log (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0)............... 916 26.2.61ROOTERRSTS--Root Error Status Register (Virtual Root Port--B0:D17:F0)............................................................... 917 26.2.63ACSCAPHDR--Access Control Services Extended Capabilities Header (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0)............... 918 28 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 26.2.64ACSCAP-- Access Control Services Capability Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 918 26.2.65ACSCAP--Access Control Services Capability Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 919 26.2.66ERRUNCDETMSK--Uncorrectable Error Detect Mask Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 919 26.2.67ERRCORDETMSK--Correctable Error Detect Mask Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) .............. 921 27 Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) .. 923 27.1 IDF SMBus Registers........................................................................................ 923 27.1.1 SMBus Function Configuration Space Registers ......................................... 923 27.1.2 PCI Standard Header Registers .............................................................. 924 27.1.3 PCI Express* Capability Structure........................................................... 929 27.1.4 Power Management Capability Structure.................................................. 940 27.1.5 MSI Capability Structure ....................................................................... 942 27.1.6 Implementation Specific Registers .......................................................... 943 27.1.7 Alternative Routing-ID Interpretation Extended Capability Structure............ 950 27.2 SMBus IO and Memory Space Registers.............................................................. 951 27.2.1 SMBus Function IO and MEM BAR Space Registers .................................... 951 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 29 Figures 2-1 2-2 4-1 4-2 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 6-1 6-2 6-3 6-4 6-5 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 30 PCH Interface Signals Block Diagram.........................................................................52 Example External RTC Circuit ...................................................................................79 PCH High-Level Clock Diagram (SRV/WS SKUs Only) ...................................................92 PCH High-Level Clock Diagram (HEDT SKU Only) ........................................................93 Programming Model for Intel(R) C602, C602J, C604 Chipset SKUs................................. 101 Programming Model for the Intel(R) C606, C608 Chipset SKUs...................................... 102 Generation of SERR# to Platform ............................................................................ 108 LPC Interface Diagram .......................................................................................... 117 PCH DMA Controller .............................................................................................. 121 DMA Request Assertion through LDRQ#................................................................... 124 TCO Legacy/Compatible Mode SMBus Configuration .................................................. 167 Advanced TCO Mode ............................................................................................. 168 Serial Post over GPIO Reference Circuit ................................................................... 170 Flow for Port Enable / Device Present Bits ................................................................ 180 Serial Data Transmitted over the SGPIO Interface ..................................................... 184 Single SCU-4 Configuration .................................................................................... 186 Double SCU-4 Configuration................................................................................... 187 Storage Controller Block Diagram ........................................................................... 190 RNC Sizes and Indexing Example ............................................................................ 192 MSI-X Generation ................................................................................................. 199 Uncorrectable Error Signalling and Logging Flowchart ................................................ 201 SGPIO Bus Overview ............................................................................................. 205 SGPIO Repeating Bit Stream .................................................................................. 206 SLoad Signal........................................................................................................ 206 SDataOut Signal ................................................................................................... 207 SDataIn Signal ..................................................................................................... 207 Clock Structure .................................................................................................... 208 SGPIO Output OD0 Signal...................................................................................... 209 SGPIO Output OD1 Signal...................................................................................... 209 SGPIO Output OD2 Signal...................................................................................... 210 Output Signal Routing ........................................................................................... 213 SCU SGPIO Unit Pin Mapping.................................................................................. 214 EHCI with USB 2.0 with Rate Matching Hub .............................................................. 227 PCH Intel(R) Management Engine (Intel(R) ME) High-Level Block Diagram ....................... 254 Flash Descriptor Sections....................................................................................... 257 PCH Ballout (Top View).......................................................................................... 267 PCH Ballout (Top View - Upper Left) ........................................................................ 268 PCH Ballout (Top View - Upper Right) ...................................................................... 269 PCH Ballout (Top View - Lower Left) ........................................................................ 270 PCH Ballout (Top View - Lower Right) ...................................................................... 271 G3 w/RTC Loss to S4/S5 (With Deep S4/S5 Support) Timing Diagram ......................... 305 G3 w/RTC Loss to S4/S5 (Without Deep S4/S5 Support) Timing Diagram ..................... 305 S5 to S0 Timing Diagram....................................................................................... 306 S3/M3 to S0 Timing Diagram ................................................................................. 307 S5/Moff - S5/M3 Timing Diagram............................................................................ 307 S0 to S5 Timing Diagram....................................................................................... 308 S4/S5 to Deep S4/S5 to G3 w/ RTC Loss Timing Diagram ......................................... 309 DRAMPWROK Timing Diagram ................................................................................ 309 Clock Cycle Time .................................................................................................. 309 Transmitting Position (Data to Strobe)..................................................................... 310 Clock Timing ........................................................................................................ 310 Valid Delay from Rising Clock Edge ......................................................................... 310 Setup and Hold Times ........................................................................................... 311 Float Delay .......................................................................................................... 311 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 8-15 8-16 8-17 8-18 8-19 8-20 8-21 8-22 8-23 8-24 8-25 8-26 8-27 8-28 Pulse Width ......................................................................................................... 311 Output Enable Delay............................................................................................. 311 USB Rise and Fall Times ........................................................................................ 312 USB Jitter ........................................................................................................... 313 USB EOP Width .................................................................................................... 313 SMBus/SMLink Transaction .................................................................................... 313 SMBus/SMLink Timeout......................................................................................... 314 SPI Timings ......................................................................................................... 314 Intel(R) High Definition Audio Input and Output Timings .............................................. 315 Transmitting Position (Data to Strobe) .................................................................... 315 PCI Express* Transmitter Eye ................................................................................ 316 PCI Express* Receiver Eye .................................................................................... 316 Measurement Points for Differential Waveforms........................................................ 317 PCH Test Load ..................................................................................................... 318 Tables 1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 3-1 3-2 3-3 4-1 4-2 4-3 5-1 5-2 Industry Specifications ....................................................................................... 41 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset SKUs ............................ 50 Direct Media Interface Signals............................................................................. 53 PCI Express* Signals ......................................................................................... 53 PCI Express* Uplink Signals................................................................................ 54 PCI Interface Signals ......................................................................................... 54 Serial ATA Interface Signals................................................................................ 56 SAS Interface Signals ........................................................................................ 58 LPC Interface Signals ......................................................................................... 60 Interrupt Signals ............................................................................................... 60 USB 2.0 Interface Signals................................................................................... 61 Power Management Interface Signals ................................................................... 62 Processor Interface Signals................................................................................. 64 SM Bus Interface Signals.................................................................................... 65 System Management Interface Signals ................................................................. 65 SAS System Management Interface Signals .......................................................... 65 Real Time Clock Interface ................................................................................... 66 Miscellaneous Signals ........................................................................................ 66 Intel(R) High Definition Audio (Intel(R) HD Audio) Link Signals ................................... 67 Serial Peripheral Interface (SPI) Signals ............................................................... 68 Thermal Signals ................................................................................................ 68 JTAG Signals .................................................................................................... 68 Clock Interface Signals....................................................................................... 69 General Purpose I/O Signals ............................................................................... 70 GPIO Serial Expander Interface ........................................................................... 73 Manageability Signals ........................................................................................ 73 Power and Ground Signals .................................................................................. 74 Functional Strap Definitions ................................................................................ 76 Integrated Pull-Up and Pull-Down Resistors .......................................................... 81 Power Plane and States for Output and I/O Signals ................................................ 83 Power Plane for Input Signals ............................................................................. 87 PCH Clock Inputs .............................................................................................. 91 PCH Clock Outputs ............................................................................................ 92 PCH PLLs.......................................................................................................... 93 PCI Bridge Initiator Cycle Types .......................................................................... 95 Type 1 Address Format ...................................................................................... 98 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 31 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 5-32 5-33 5-34 5-35 5-36 5-37 5-38 5-39 5-40 5-41 5-42 5-43 5-44 5-45 5-46 5-47 5-48 5-49 5-50 5-51 5-52 5-53 32 Configuration Spaces Visible to Software in Intel(R) C602, C602J, C604 Chipset SKUs .................................................................................................. 101 Root Port and SCU Addressable Internal Spaces................................................... 102 Configuration Spaces Visible to Software in the Intel(R) C606, C608 Chipset SKUs...... 103 Intel(R) C606, C608 Chipset SKUs Addressable Internal Spaces ............................... 103 MSI versus PCI IRQ Actions............................................................................... 106 LAN Mode Support ........................................................................................... 113 LPC Cycle Types Supported ............................................................................... 118 Start Field Bit Definitions .................................................................................. 118 Cycle Type Bit Definitions ................................................................................. 119 Transfer Size Bit Definition................................................................................ 119 SYNC Bit Definition .......................................................................................... 119 DMA Transfer Size ........................................................................................... 123 Address Shifting in 16-Bit I/O DMA Transfers....................................................... 123 Counter Operating Modes ................................................................................. 128 Interrupt Controller Core Connections................................................................. 130 Interrupt Status Registers................................................................................. 131 Content of Interrupt Vector Byte ........................................................................ 131 APIC Interrupt Mapping1 .................................................................................. 136 Stop Frame Explanation.................................................................................... 139 Data Frame Format .......................................................................................... 140 Configuration Bits Reset by RTCRST# Assertion ................................................... 142 INIT# Going Active .......................................................................................... 144 NMI Sources ................................................................................................... 145 General Power States for Systems Using the PCH ................................................. 146 State Transition Rules for the PCH...................................................................... 147 System Power Plane......................................................................................... 148 Causes of Intel(R) Scalable Memory Interconnect (Intel(R) SMI) and SCI ................... 149 Sleep Types .................................................................................................... 152 Causes of Wake Events..................................................................................... 152 GPI Wake Events ............................................................................................. 153 Transitions Due to Power Failure ........................................................................ 154 Supported Deep S4/S5 Policy Configurations ....................................................... 155 Deep S4/S5 Wake Events ................................................................................. 155 Transitions Due to Power Button ........................................................................ 156 Transitions Due to RI# Signal............................................................................ 157 Write Only Registers with Read Paths in ALT Access Mode ..................................... 159 PIC Reserved Bits Return Values ........................................................................ 160 Register Write Accesses in ALT Access Mode ........................................................ 161 SLP_LAN# Pin Behavior .................................................................................... 162 SUSWARN#/GPIO30 Steady State Pin Behavior ................................................... 163 Causes of Host and Global Resets ...................................................................... 164 Event Transitions that Cause Messages............................................................... 167 Multi-Activity LED Message Type ........................................................................ 183 Context Command Type ................................................................................... 191 Completion Entry Format .................................................................................. 192 SGPIO Input Mapping ....................................................................................... 210 Legacy Replacement Routing ............................................................................. 215 Debug Port Behavior ........................................................................................ 222 I2C Block Read ................................................................................................ 232 Enable for SMBALERT#..................................................................................... 234 Enables for SMBus Slave Write and SMBus Host Events......................................... 235 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 5-54 5-55 5-56 5-57 5-58 5-59 5-60 5-61 5-62 5-63 5-64 5-65 5-66 5-67 6-1 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 8-18 8-19 8-20 8-21 8-22 8-23 8-24 8-25 8-26 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 10-1 Enables for the Host Notify Command ................................................................ 235 Slave Write Registers....................................................................................... 237 Command Types ............................................................................................. 237 Slave Read Cycle Format.................................................................................. 238 Data Values for Slave Read Registers ................................................................. 238 Host Notify Format .......................................................................................... 241 I2C Write Commands to the Intel(R) Management Engine ....................................... 244 Block Read Command - Byte Definition .............................................................. 245 Region Size versus Erase Granularity of Flash Components ................................... 256 Region Access Control Table ............................................................................. 258 Hardware Sequencing Commands and Opcode Requirements ................................ 261 Flash Protection Mechanism Summary................................................................ 262 Recommended Pinout for 8-Pin Serial Flash Device .............................................. 263 Recommended Pinout for 16-Pin Serial Flash Device............................................. 263 PCH Ballout by Signal Name ............................................................................. 272 PCH Absolute Maximum Ratings ........................................................................ 283 PCH Power Supply Range ................................................................................. 284 Power Supply ICC Specifications by Domain (Intel(R) C602, C602J, C604 Chipset and Intel(R) X79 Express Chipset SKUs).................................................... 284 Power Supply ICC Specifications by Domain (Intel(R) C606, C608 Chipset SKUs) ........ 285 DC Characteristic Input Signal Association .......................................................... 285 DC Input Characteristics................................................................................... 287 DC Characteristic Output Signal Association ........................................................ 290 DC Output Characteristics ................................................................................ 291 Other DC Characteristics .................................................................................. 292 PCI Express* and DMI Interface Timings ............................................................ 294 PCI Express* Uplink Interface Timings (Intel(R) C606, C608 Chipset SKUs Only) ....... 294 SAS Interface Timings (SRV/WS SKUs Only) ....................................................... 295 Clock Timings ................................................................................................. 295 PCI Interface Timing ........................................................................................ 297 Universal Serial Bus Timing .............................................................................. 297 SATA Interface Timings .................................................................................... 298 SMBus and SMLink Timing ................................................................................ 299 Intel(R) High Definition Audio Timing ................................................................... 299 LPC Timing ..................................................................................................... 299 Miscellaneous Timings...................................................................................... 300 SPI Timings (20 MHz) ...................................................................................... 300 SPI Timings (33 MHz) ...................................................................................... 300 SPI Timings (50 MHz) ...................................................................................... 301 SST Timings ................................................................................................... 301 PECI Timings .................................................................................................. 302 Power Sequencing and Reset Signal Timings ....................................................... 302 PCI Devices and Functions for all PCH SKUs ........................................................ 320 PCI Devices and Functions for PCH Intel(R) C602, C602J, C604 Chipset and Intel(R) X79 Express Chipset SKUs ...................................................................... 321 Additional PCI Devices and Functions for Intel(R) C606, C608 Chipset SKUs.............. 321 Additional PCI Devices and Functions for Intel(R) C608 Chipset SKU......................... 321 Fixed I/O Ranges Decoded by PCH..................................................................... 322 Variable I/O Decode Ranges ............................................................................. 324 Memory Decode Ranges from Processor Perspective............................................. 325 SPI Mode Address Swapping ............................................................................. 327 Chipset Configuration Register Memory Map (Memory Space)................................ 329 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 33 11-1 PCI Bridge Register Address Map (PCI-PCI--D30:F0) ............................................ 365 12-1 Gigabit LAN Configuration Registers Address Map (Gigabit LAN --D25:F0) .................................................................................... 379 12-2 Gigabit LAN Capabilities and Status Registers Address Map (Gigabit LAN --MBARA) .................................................................................... 391 13-1 LPC Interface PCI Register Address Map (LPC I/F--D31:F0) ................................... 395 13-2 DMA Registers................................................................................................. 418 13-3 PIC Registers .................................................................................................. 427 13-4 APIC Direct Registers ....................................................................................... 433 13-5 APIC Indirect Registers..................................................................................... 433 13-6 RTC I/O Registers ............................................................................................ 437 13-7 RTC (Standard) RAM Bank ................................................................................ 437 13-8 Processor Interface PCI Register Address Map ..................................................... 441 13-9 Power Management PCI Register Address Map (PM--D31:F0)................................. 443 13-10 APM Register Map ............................................................................................ 450 13-11 ACPI and Legacy I/O Register Map ..................................................................... 451 13-12 TCO I/O Register Address Map........................................................................... 469 13-13 Registers to Control GPIO Address Map............................................................... 475 13-14 Registers to Control GSX Address Map ................................................................ 484 14-1 SATA Controller PCI Register Address Map (SATA-D31:F2).................................... 487 14-2 Bus Master IDE I/O Register Address Map ........................................................... 511 14-3 AHCI Register Address Map ............................................................................... 519 14-4 Generic Host Controller Register Address Map...................................................... 519 14-5 Port [5:0] DMA Register Address Map ................................................................. 527 15-1 SATA Controller PCI Register Address Map (SATA-D31:F5).................................... 541 15-2 Bus Master IDE I/O Register Address Map ........................................................... 556 16-3 Register Base Attribute Definitions ..................................................................... 563 16-4 Register Attribute Modifier Definitions................................................................. 564 16-5 Register Domain Definitions .............................................................................. 564 16-6 SCU PF PCI Configuration Registers .................................................................... 565 16-7 SCU VF PCI Configuration Registers.................................................................... 594 16-8 SGPIO Memory Mapped Registers ...................................................................... 614 17-1 USB EHCI PCI Register Address Map (USB EHCI--D29:F0, D26:F0) ........................ 621 17-2 Enhanced Host Controller Capability Registers ..................................................... 639 17-3 Enhanced Host Controller Operational Register Address Map .................................. 642 17-4 Debug Port Register Address Map ...................................................................... 652 18-5 Intel(R) High Definition Audio PCI Register Address Map (Intel HD Audio D27:F0)....... 655 18-6 Intel(R) HD Audio PCI Register Address Map (Intel(R) HD Audio D27:F0)................................................................................. 672 19-1 SMBus Controller PCI Register Address Map (SMBus--D31:F3)............................... 695 19-2 SMBus I/O and Memory Mapped I/O Register Address Map.................................... 701 20-1 PCI Express* Configuration Registers Address Map (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/) .................................................. 711 21-1 Memory-Mapped Registers ................................................................................ 745 22-1 Serial Peripheral Interface (SPI) Register Address Map (SPI Memory Mapped Configuration Registers)..................................................... 753 22-2 Gigabit LAN SPI Flash Program Register Address Map (GbE LAN Memory Mapped Configuration Registers) ............................................. 771 23-1 Thermal Sensor Register Address Map ................................................................ 781 23-2 Thermal Memory Mapped Configuration Register Address Map ............................... 789 24-1 Intel MEI 1 Configuration Registers Address Map (Intel MEI 1 --D22:F0) ..................................................................................... 799 34 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 24-2 24-3 24-4 24-5 24-6 24-7 24-8 24-9 24-10 25-1 27-2 27-3 Intel MEI 1 MMIO Register Address Map ............................................................. 808 Intel MEI 2 Configuration Registers Address Map (Intel MEI 2--D22:F1).................. 810 Intel MEI 2 MMIO Register Address Map ............................................................. 818 IDE Function for remote boot and Installations PT IDER Register Address Map ......... 820 IDE BAR0 Register Address Map ........................................................................ 827 IDER BAR1 Register Address Map ...................................................................... 836 IDER BAR4 Register Address Map ...................................................................... 837 Serial Port for Remote Keyboard and Text (KT) Redirection Register Address Map................................................................................................... 842 KT IO/ Memory Mapped Device Register Address Map .......................................... 848 PCI Express* UpStream Configuration Registers Address Map (PCI Express*--D0:F0) .................................................................................... 853 SMBus PCI Function 3,4,5 Configuration Map ...................................................... 923 SMBus I/O and Memory Mapped I/O Register Address Map ................................... 951 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 35 Revision History Revision Number 001 Description * * * * * * * 002 * * * * * * * * * 36 Initial Release Date March 2012 (R) Added Intel X79 Express Chipset Minor Edits throughout for clarity Replaced SKU letter designators A/J/B/D/T with product numbers. References all of the lettered SKUs were replaced with SRV/WS. Chapter 1 -- Updated Table 1-2, Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset SKUs -- Added note to Section 1.2.1, Access Control Services Clarification -- Updated Section 1.2.1 SPI Overview Chapter 2 -- Updated PWRBTN# and SLP_SUS# descriptions in Table 2-10. -- Updated RTCRST# description in Table 2-16. -- Added Note 13 to Table 2-22, General Purpose I/O Signals -- Updated Table 2-25, SAS Power Signal Connections -- Updated Section 2.28, Device and Revision ID Table Chapter 5 -- Added Note 5 to Table 5-27, State Transition Rules for the PCH -- Updated Section 5.18.1.2, SCU Architectural Features, first bullet -- Added Note to Section 5.3.1 Valid PCI Express* uplink configuration -- Updated Table 5-29, Causes of Intel(R) Scalable Memory Interconnect (Intel(R) SMI) and SCI -- Updated Table 5-44, Event Transitions that Cause Messages -- Updated Section 5.14.7.1, PWRBTN# (Power Button) -- Added Note to Section 5.15.4, GPIO Registers Lockdown -- Updated Section 5.19, High Precision Event Timers Functional Description -- Updated Section 5.23.1, Thermal Sensor -- Updated Section 5.26.1.2.1, SPI Flash Regions -- Updated Section 5.27, Fan Control/Thermal Management Chapter 8 -- Updated Table 8-4 and 8-5, Icc Value for RTC Well -- Updated Table 8-13, Clock Timings -- Updated Table 8-26, Power Sequencing and Reset Signal Timings -- Added notes to Figures 8-2 and 8-20 Chapter 9 -- Updated Table 9-7, Memory Decode Ranges from Processor Perspective Chapter 10 -- Updated Table 10-1, Chipset Configuration Register Memory Map -- Updated 10.1.4, Function Level Reset Pending Status Register -- Updated 10.1.47, FDSW-Function Disable SUS Well Chapter 12 -- Updated Table 12-1, Gigabit LAN Configuration Registers Address Map Chapter 13 -- Updated Table 13-1, LPC Interface PCI Register Address Map -- Updated Section 13.8.3.7, SMI_EN--SMI Control and Enable Register -- Updated Section 13.8.3.11, UPRWC--USB Per-Port Registers Write Control Register -- Updated Table 13-13 Registers to Control GPIO Address Map Chapter 14 -- Updated Table 14-1, SATA Controller PCI Register Address Map -- Updated Section 14.1.37, SGC-SATA General Configuration Register Chapter 15 -- Updated Table 15-1, SATA Controller PCI Register Address Map Chapter 17 -- Updated Section 17.1.20, PWR_CNTL_SIS Register Chapter 20 -- Updated Table 20-1, PCI Express* Configuration Registers Address Map -- PECR2 -- PCI Express* Configuration Register 2 (PCI Express-- D28:F0/F1/F2/F3/F4/F5/F6/F7) and PEC1 -- PCI Express* Configuration Register 1 have been removed as no BIOS programing is necessary. March 2013 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Revision Number Description * * * * 002 (cont) * Chapter 22 -- Updated Table 22-1, Serial Peripheral Interface (SPI) Register Address Map -- Updated Table 22-1, Gigabit LAN SPI Flash Program Register Address Map Chapter 23 -- Updated Section 23.2.4, TSTR--Thermal Sensor Thermometer Read Register Chapter 24 -- Updated Table 24-1, Intel MEI 1 Configuration Registers Address Map Chapter 25 -- Updated Section 25.1.31, LCAP--Link Capabilities Register (PCI Express--D0:F0) -- Updated Section 25.1.33, LSTS--Link Status Register (PCI Express--D0:F0) -- Removed LINKCAP2 Register -- Updated Section 25.1.38, L2--Link Control 2 Register (PCI Express--D0:F0) Chapter 26 -- Updated Section 26.2.30, LCAP--Link Capabilities Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) -- Updated Section 26.2.321,LSTS--Link Status Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) -- Removed LINKCAP2 Register -- Updated Section 26.2.39, L2--Link Control 2 Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) Date March 2013 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 37 38 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Features * Direct Media Interface * USB -- NEW: Up to 20 Gb/s each direction, full duplex -- Lane reversal supported -- Transparent to software * PCI Express* Root Ports -- 8 PCI Express* root ports -- NEW: Supports PCI Express* 2.0 running at up to 5.0 GT/s -- Ports 1-4 and ports 5-8 can independently be configured to support eight x1s, two x4s, two x2s, and four x1s, or one x4 and four x1 port widths. -- Module based hot-plug supported (that is, ExpressCard*) -- Lane reversal supported on x4 configuration * NEW: PCI Express* Uplink Port (SRV/WS SKUs Only) * -- SKU specific x4 PCI Express* upstream port dedicated for SAS I/O * NEW: Serial Attached SCSI (SAS) Ports (SRV/WS SKUs Only) * -- -- -- -- -- SKU specific up to eight 3 Gb/s SAS ports Up to x4 SAS wide port configuration Independently configurable Compliant to SATA 3 Gb/s Automated Out of Band (OOB) Signaling & Speed Negotiation * SGPIO Ports -- New: 1 Serial GPIO controller for each 4 SAS ports (SRV/WS SKUs Only) -- Serial GPIO controller for SATA only ports * Integrated Serial ATA Host Controller -- Up to six SATA ports -- NEW: Data transfer rates up to 6.0 Gb/s (600 MB/s) on up to 2 ports. -- Data transfer rates up to 3.0 Gb/s (300 MB/s) on up to 1.5 Gb/s (150 MB/s) all ports. -- Integrated AHCI controller * External SATA support -- 3.0 Gb/s / 1.5 Gb/s support -- Port Disable Capability * Intel(R) Rapid Storage Technology enterprise * * -- Two EHCI Host Controllers, supporting up to fourteen external USB 2.0 ports -- New: Two USB 2.0 Rate Matching Hubs (RMH) to replace functionality of UHCI controllers -- Per-Port-Disable Capability -- Includes up to two USB 2.0 High-speed Debug Ports -- Supports wake-up from sleeping states S1-S4 -- Supports legacy Keyboard/Mouse software Integrated Gigabit LAN Controller -- NEW: Connection utilizes PCI Express* pins -- Integrated ASF Management Controller -- Network security with System Defense -- Supports IEEE 802.3 -- 10/100/1000 Mbps Ethernet Support -- Jumbo Frame Support Power Management Logic -- Supports ACPI 4.0a -- ACPI-defined power states (processor driven C states) -- ACPI Power Management Timer -- SMI# generation -- All registers readable/restorable for proper resume from 0 V core well suspend states -- Support for APM-based legacy power management for non-ACPI implementations External Glue Integration -- Integrated Pull-up, Pull-down and Series Termination resistors on processor I/F -- Integrated Pull-down and Series resistors on USB Enhanced DMA Controller -- Two cascaded 8237 DMA controllers -- Supports LPC DMA -- Supports SAS as well as SATA ports -- Configures the Intel(R) C600 Series chipset SAS ports as a RAID Controller supporting RAID 0/1/5/10 -- Configures the Intel(R) C600 Series chipset SATA ports as a RAID controller supporting RAID 0/1/5/10 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 39 * Intel(R) High Definition Audio Interface -- PCI Express* endpoint -- Independent Bus Master logic for eight general purpose streams: four input and four output -- Support four external Codecs -- Supports variable length stream slots -- Supports multichannel, 32-bit sample depth, 192 kHz sample rate output -- Provides mic array support -- Allows for non-48 kHz sampling output * Support for ACPI Device States -- Four PWM signals and Eight TACH signals * Simple Serial Transport (SST) 1.0 Bus and Platform Environmental Control Interface (PECI) * PCI Bus Interface * * * * * Note: -- Supports PCI Rev 2.3 specification at 33 MHz -- Four available PCI REQ/GNT pairs (shared with GPIO serial expander signals) -- Support for 64-bit addressing on PCI using DAC protocol SMBus -- Interface speeds greater than 100 kbps -- SMBus/SMLink architecture provides flexibility and optimizes the interface performance -- Provides independent manageability bus through SMLink interface -- Supports SMBus 2.0 Specification -- Host interface allows processor to communicate using SMBus -- Slave interface allows an external Microcontroller to communicate with PCH -- Compatible with most two-wire components that are also I2C* compatible -- Up to 3 additional SMBus master controllers High Precision Event Timers -- Advanced operating system interrupt scheduling Timers Based on 8254 -- System timer, Refresh request, Speaker tone output Real-Time Clock -- 256-byte battery-backed CMOS RAM -- Integrated oscillator components -- Lower Power DC/DC Converter implementation System TCO Reduction Circuits -- Timers to generate SMI# and Reset upon detection of system hang -- Timers to detect improper processor reset -- Integrated processor frequency strap logic -- Supports ability to disable external devices * Interrupt Controller -- Supports up to eight PCI interrupt pins -- Supports PCI 2.3 Message Signaled Interrupts -- Two cascaded 8259 with 15 interrupts -- Integrated I/O APIC capability with 24 interrupts -- Supports Processor System Bus interrupt delivery * Serial Peripheral Interface (SPI) -- Supports up to two SPI devices -- Supports 20 MHz, 33 MHz SPI devices -- Support up to two different erase granularities * Low Pin Count (LPC) I/F -- Supports two Master/DMA devices. -- Support for Security Device (Trusted Platform Module) connected to LPC. * GPIO -- Inversion, Open-Drain (not available on all GPIOs), -- GPIO lock down -- NEW: Additional GPIOs using GPIO Serial Expander * JTAG -- Boundary Scan for testing during board manufacturing * Technologies supported -- Intel(R) I/O Virtualization (VT-d) Support (SRV/WS SKUs Only) -- Intel(R) Trusted Execution Technology Support -- Intel(R) Anti-Theft Technology -- Intel(R) Active Management Technology with System Defense (SRV/WS SKUs Only) -- NEW: Network Outbreak Containment Heuristics * Miscellaneous -- Thermal sensor for die temp tracking -- 27x27 mm FCBGA package -- 901 pins (498 signals, 387 power and ground) -- 1.1 V operation with 1.5 and 3.3 V I/O -- Five Integrated Voltage Regulators for different power rails -- Firmware Hub I/F supports BIOS Memory size up to 8 MBytes Not all features are available on all PCH SKUs. See Section 1.3 for more details. 40 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Introduction 1 Introduction 1.1 About This Manual This manual is intended for Original Equipment Manufacturers and BIOS vendors creating Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset based products (See Section 1.3 for currently defined SKUs). Note: Throughout this document, the terms "Server/Workstation" and "Server/Workstation" Only" refer to information that is applicable only to the Intel(R) C602 Chipset, Intel(R) C602J Chipset, Intel(R) C604 Chipset, Intel(R) C606 Chipset, and Intel(R) C608 Chipset, unless specifically noted otherwise. Server/Workstation is abbreviated SRV/WS Note: Throughout this document, the terms "High End Desktop" and "High End Desktop" Only" refer to information that is applicable only to the Intel(R) X79 Chipset, unless specifically noted otherwise. High End Desktop is abbreviated HEDT. Note: Throughout this manual, Platform Controller Hub (PCH) is used as a general term and refers to all Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset SKUs, unless specifically noted otherwise. This manual assumes a working knowledge of the vocabulary and principles of interfaces and architectures such as PCI Express*, USB, AHCI, SATA, Intel(R) High Definition Audio (Intel(R) HD Audio), SMBus, PCI, ACPI and LPC. Although some details of these features are described within this manual, refer to the individual industry specifications listed in Table 1-1 for the complete details. Table 1-1. Industry Specifications (Sheet 1 of 2) Specification Location PCI Express* Base Specification, Revision 1.1 http://www.pcisig.com/specifications PCI Express* Base Specification, Revision 2.0 http://www.pcisig.com/specifications PCI Express* Base Specification, Revision 3.0 (draft) http://www.pcisig.com/specifications Low Pin Count Interface Specification, Revision 1.1 (LPC) http://developer.intel.com/design/chipsets/ industry/lpc.htm System Management Bus Specification, Version 2.0 (SMBus) http://www.smbus.org/specs/ PCI Local Bus Specification, Revision 2.3 (PCI) http://www.pcisig.com/specifications PCI Power Management Specification, Revision 1.2 http://www.pcisig.com/specifications Universal Serial Bus Specification (USB), Revision 2.0 http://www.usb.org/developers/docs Advanced Configuration and Power Interface, Version 4.0a (ACPI) http://www.acpi.info/spec.htm Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 (EHCI) http://developer.intel.com/technology/usb/ ehcispec.htm Serial ATA Specification, Revision 3.0 http://www.serialata.org/specifications.asp Serial ATA II: Extensions to Serial ATA 1.0, Revision 1.0 http://www.serialata.org/specifications.asp Serial ATA II Cables and Connectors Volume 2 Gold http://www.serialata.org/specifications.asp Serial Attached SCSI (SAS) revision 2.0r5 http://T10.org (T10 1760-D) Alert Standard Format Specification, Version 2.0 http://www.dmtf.org/standards/documents/ASF/ DSP0136.pdf Desktop and mobile Architecture for System Hardware (DASH) Specification 1.1 http://www.dmtf.org/standards/ published_documents/DSP2014_1.1.0.pdf Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 41 Introduction Table 1-1. Industry Specifications (Sheet 2 of 2) Specification Location IEEE 802.3 Fast Ethernet http://standards.ieee.org/getieee802/ AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6) http://T13.org (T13 1410D) IA-PC HPET (High Precision Event Timers) Specification, Revision 1.0a http://www.intel.com/content/www/us/en/ software-developers/software-developers-hpetspec-1-0a.html TPM Specification 1.02, Level 2 Revision 103 http://www.trustedcomputinggroup.org/specs/ TPM Intel (R) http://www.intel.com/technology/platformtechnology/virtualization/index.htm Virtualization Technology SFF-8485 Specification for Serial GPIO (SGPIO) Bus, Revision 0.7 ftp://ftp.seagate.com/sff/SFF-8485.PDF Advanced Host Controller Interface specification for Serial ATA, Revision 1.3 http://www.intel.com/content/www/us/en/io/ serial-ata/serial-ata-ahci-spec-rev1_3.html Intel(R) High Definition Audio Specification, Revision 1.0a http://www.intel.com/content/www/us/en/ standards/standards-high-def-audio-specsgeneral-technology.html MultiProcessor Specification http://www.intel.com/design/pentium/datashts/ 242016.HTM Chapter 1. Introduction Chapter 1 introduces the PCH and provides information on manual organization and gives a general overview of the PCH. Chapter 2. Signal Description Chapter 2 provides a block diagram of the PCH and a detailed description of each signal. Signals are arranged according to interface and details are provided as to the drive characteristics (Input/Output, Open Drain, and so forth) of all signals. Chapter 3. PCH Pin States Chapter 3 provides a complete list of signals, their associated power well, their logic level in each suspend state, and their logic level before and after reset. Chapter 4. PCH and System Clock Domains Chapter 4 provides a list of each clock domain associated with the PCH. Chapter 5. Functional Description Chapter 5 provides a detailed description of the functions in the PCH. All PCI buses, devices and functions in this manual are abbreviated using the following nomenclature; Bus:Device:Function. This manual abbreviates buses as Bn, devices as Dn, and functions as Fn. For example Device 31 Function 0 is abbreviated as D31:F0, Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus number will not be used, and can be considered to be Bus 0. Note that the PCH's external PCI bus is typically Bus 1, but may be assigned a different number depending upon system configuration. Chapter 6. Ballout Definition Chapter 6 provides a table of each signal and its ball assignment in the PCH package. Chapter 7. Package Information Chapter 7 provides drawings of the physical dimensions and characteristics of the 676-mBGA package. Chapter 8. Electrical Characteristics Chapter 8 provides all AC and DC characteristics including detailed timing diagrams. Chapter 9. Register and Memory Mappings Chapter 9 provides an overview of the registers, fixed I/O ranges, variable I/O ranges and memory ranges decoded by the PCH. 42 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Introduction Chapter 10. Chipset Configuration Registers Chapter 10 provides a detailed description of all registers and base functionality that is related to chipset configuration and not a specific interface (such as LPC, PCI, or PCI Express). It contains the root complex register block, which describes the behavior of the upstream internal link. Chapter 11. PCI-to-PCI Bridge Registers Chapter 11 provides a detailed description of all registers that reside in the PCI-to-PCI bridge. This bridge resides at Device 30, Function 0 (D30:F0). Chapter 12. Integrated LAN Controller Registers Chapter 12 provides a detailed description of all registers that reside in the PCH's integrated LAN controller. The integrated LAN Controller resides at Device 25, Function 0 (D25:F0). Chapter 13. LPC Bridge Registers Chapter 13 provides a detailed description of all registers that reside in the LPC bridge. This bridge resides at Device 31, Function 0 (D31:F0). This function contains registers for many different units within the PCH including DMA, Timers, Interrupts, Processor Interface, GPIO, Power Management, System Management and RTC. Chapter 14. SATA Controller Registers Chapter 14 provides a detailed description of all registers that reside in the SATA controller #1. This controller resides at Device 31, Function 2 (D31:F2). Chapter 15. SATA Controller Registers Chapter 15 provides a detailed description of all registers that reside in the SATA controller #2. This controller resides at Device 31, Function 5 (D31:F5). Chapter 16. SAS Controller Registers (SRV/WS SKUs Only) Chapter 16 provides a detailed description of all registers that reside in the SAS controller. The controllers resides at Bus X, Device 0, Functions 0 (BX:D0:F0). Chapter 17. EHCI Controller Registers Chapter 17 provides a detailed description of all registers that reside in the two EHCI host controllers. These controllers reside at Device 29, Function 7 (D29:F7) and Device 26, Function 7 (D26:F7). Chapter 18. Intel(R) High Definition Audio Controller Registers Chapter 18 provides a detailed description of all registers that reside in the Intel(R) High Definition Audio (Intel(R) HD Audio) controller. This controller resides at Device 27, Function 0 (D27:F0). Chapter 19. SMBus Controller Registers Chapter 19 provides a detailed description of all registers that reside in the SMBus controller. This controller resides at Device 31, Function 3 (D31:F3). Chapter 20. PCI Express* Port Controller Registers Chapter 20 provides a detailed description of all registers that reside in the PCI Express* controller. This controller resides at Device 28, Functions 0 to 5 (D30:F0-F5). Chapter 21. High Precision Event Timers Registers Chapter 21 provides a detailed description of all registers that reside in the multimedia timer memory mapped register space. Chapter 22. Serial Peripheral Interface Registers Chapter 22 provides a detailed description of all registers that reside in the SPI memory mapped register space. Chapter 23. Thermal Sensors Chapter 23 provides a detailed description of all registers that reside in the thermal sensors PCI configuration space. The registers reside at Device 31, Function 6 (D31:F6). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 43 Introduction Chapter 24. Intel(R) Management Engine (Intel(R) ME) Chapter 24 provides a detailed description of all registers that reside in the thermal sensors PCI configuration space. The registers reside at Device 31, Function 6 (D31:F6). Chapter 25. Upstream PCIe* Interface Registers (Intel(R) C606, C608 Chipset SKUs Only) Chapter 25 provides a detailed description of all registers that reside in the upstream PCI Express* controller. This controller resides at Bus N, Device 0, Function 0 (BN:D0:F0). Chapter 26. PCIe Virtual Root/Switch Port Interface Registers (SRV/WS SKUs Only) Chapter 26 provides a detailed description of all registers that reside in the virtual Root port (for Intel C602, C602J, C604 Chipset SKUs) or virtual switch port (for Intel C606, C608 Chipset SKUs) of PCI Express* controller. For virtual root port, this controller resides at Device 17, Function 0 (D17:F0). For virtual switch port, this controller resides at Bus N+1, Device 8, Function 0 (BN+1:D8:F0). Chapter 27. IDF SMBus Controller Registers (SRV/WS SKUs Only) Chapter 27 provides a detailed description of all registers that reside in the SMBus controllers that associated with SAS controller. These controllers reside at Bus X, Device 0, Function 3, 4, 5 (BX:D0:F3/F4/F5) 1.2 Overview The PCH provides extensive I/O support. Functions and capabilities include: * PCI Express* Base Specification, Revision 2.0 support for up to eight ports with transfers up to 5 GT/s. * PCI Express* Uplink. (Availiable on specific SKUs Only) * PCI Local Bus Specification, Revision 2.3 support for 33 MHz PCI operations (supports up to four Req/Gnt pairs). * ACPI Power Management Logic Support, Revision 4.0a * Enhanced DMA controller, interrupt controller, and timer functions * Integrated Serial Attached SCSI host controllers at transfer rate up to 3 Gb/s on up to eight ports. (Available on specific SKUs Only) * Integrated Serial ATA host controllers with independent DMA operation on up to six ports. * USB host interface with two EHCI high-speed USB 2.0 Host controllers and 2 rate matching hubs provide support for support for up to fourteen USB 2.0 ports * Integrated 10/100/1000 Gigabit Ethernet MAC with System Defense * System Management Bus (SMBus) Specification, Version 2.0 with additional support for I2C* devices * Supports Intel(R) High Definition Audio * Supports Intel(R) Rapid Storage Technology enterprise (Intel(R) RSTe) * Supports Intel(R) Active Management Technology (Intel(R) AMT). (Available on specific SKUs Only) * Supports Intel(R) Virtualization Technology for Directed I/O (Intel(R) VT-d). (Available on specific SKUs Only) * Supports Intel(R) Trusted Execution Technology (Intel(R) TXT) * Low Pin Count (LPC) interface * Firmware Hub (FWH) interface support * Serial Peripheral Interface (SPI) support * Intel(R) Anti-Theft Technology (Intel(R) AT) * JTAG Boundary Scan support 44 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Introduction The PCH incorporates a variety of PCI devices and functions. Refer to Table 9-1 for details. 1.2.1 Capability Overview The following sub-sections provide an overview of the PCH capabilities. Digital Media Interface (DMI) Digital Media Interface (DMI) is the chip-to-chip connection between the processor and PCH. This high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. Base functionality is completely software-transparent, permitting current and legacy software to operate normally. PCI Express* Root Port The PCH provides up to 8 PCI Express* Root Ports, supporting the PCI Express Base Specification, Revision 2.0. Each Root Port x1 lane supports up to 5 Gb/s bandwidth in each direction (10 Gb/s concurrent). PCI Express* Root Ports 1-4 or Ports 5-8 can independently be configured to support four x1s, two x2s, one x2 and two x1s, or one x4 port widths. Note: Access Control Services (ACS)/Alternative Routing ID (ARI) are not supported on the PCI Express* Root Port of the Intel(R) C600 series chipset, devices connected to these ports may not support direct assignment or Single Root I/O Virtualization (SR-IOV). PCI Express* Uplink (Available on specific SKUs Only) The PCI Express* Uplink here is an amalgram of two functions, and Uplink port connecting to a PCI Express* bus, and a virtual switch connecting the Uplink port to the MFD below. The MFD contains the SAS controllers, and SMBus controllers. The uplink can run at 5.0 Gt/s and 2.5 Gt/s, at x4, x2 and x1 configurations. However, because the PCI Express* uplink will be connected to Intel(R) components, no 3rd party devices, the expected/supported configuration is simply x4 as 1.0. Note: PCI Express* Uplink is only available on specific PCH SKUs. See Section 1.3 for details on SKU feature availability. Serial Attached SCSI (SAS)/SATA Controller (SAS Available on specific SKUs Only) The PCH supports upto 8 SAS ports that are compliant with SAS 2.0 Specification and all ports support rates up to 3.0 Gb/s. All 8 ports are also independently configurable and compliant with SATA Gen2 and support data transfer rates of up to 3.0 Gb/s. Note: SAS/SATA controller is only available on specific PCH SKUs. Certain SKUs are also limited to support 4 of 8 SAS/SATA ports only. See Section 1.3 for details on SKU feature availability. Serial ATA (SATA) Controller The PCH has two integrated SATA host controllers that support independent DMA operation on up to six ports and supports data transfer rates of up to 6.0 Gb/s (600 MB/s) on up to two ports (Port 0 and 1 Only) while all ports support rates up to 3.0 Gb/s (300 MB/s) and up to 1.5 Gb/s (150 MB/s). The SATA controller contains two modes of operation - a legacy mode using I/O space, and an AHCI mode using memory space. Software that uses legacy mode will not have AHCI capabilities. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 45 Introduction The PCH supports the Serial ATA Specification, Revision 3.0. The PCH also supports several optional sections of the Serial ATA II: Extensions to Serial ATA 1.0 Specification, Revision 1.0 (AHCI support is required for some elements). AHCI The PCH provides hardware support for Advanced Host Controller Interface (AHCI), a standardized programming interface for SATA host controllers. Platforms supporting AHCI may take advantage of performance features such as no master/slave designation for SATA devices--each device is treated as a master--and hardwareassisted native command queuing. AHCI also provides usability enhancements such as Hot-Plug. AHCI requires appropriate software support (for example, an AHCI driver) and for some features, hardware support in the SATA device or additional platform hardware. Intel(R) Rapid Storage Technology enterprise (Intel(R) RSTe) The PCH provides support for Intel(R) Rapid Storage Technology enterprise, providing both AHCI (see above for details on AHCI) and integrated RAID functionality. The industry-leading RAID capability provides high-performance RAID 0, 1, 5, and 10 functionality on up to 6 SATA ports of the PCH. Matrix RAID support is provided to allow multiple RAID levels to be combined on a single set of hard drives, such as RAID 0 and RAID 1 on two disks. Other RAID features include hot-spare support, SMART alerting, and RAID 0 auto replace. Software components include an Option ROM for pre-boot configuration and boot functionality, a Microsoft Windows* compatible driver, and a user interface for configuration and management of the RAID capability of the PCH. Please see Section 1.3 for details on SKU feature availability. PCI Interface The PCH PCI interface provides a 33 MHz, Revision 2.3 implementation. The PCH integrates a PCI arbiter that supports up to four external PCI bus masters in addition to the internal PCH requests. This allows for combinations of up to four PCI down devices and PCI slots. Low Pin Count (LPC) Interface The PCH implements an LPC Interface as described in the LPC 1.1 Specification. The Low Pin Count (LPC) bridge function of the PCH resides in PCI Device 31:Function 0. In addition to the LPC bridge interface function, D31:F0 contains other functional units including DMA, interrupt controllers, timers, power management, system management, GPIO, and RTC. Serial Peripheral Interface (SPI) The PCH provides an SPI Interface and is required to be used on the platform in order to provide chipset configuration settings and Intel(R) Management Engine (Intel(R) ME) firmware. If integrated Gigabit Ethernet MAC/PHY is implemented on the platform, the interface is used for this device configuration settings. The interface may also be used as the interface for the BIOS flash device or alternatively a FWH on LPC may be used. The PCH supports up to two SPI flash devices using two chip select pins with speeds up to 50 MHz. Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller) The DMA controller incorporates the logic of two 8237 DMA controllers, with seven independently programmable channels. Channels 0-3 are hardwired to 8-bit, count-bybyte transfers, and channels 5-7 are hardwired to 16-bit, count-by-word transfers. Any two of the seven DMA channels can be programmed to support fast Type-F transfers. Channel 4 is reserved as a generic bus master request. 46 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Introduction The PCH supports LPC DMA, which is similar to ISA DMA, through the PCH's DMA controller. LPC DMA is handled through the use of the LDRQ# lines from peripherals and special encoding on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported on the LPC interface. The timer/counter block contains three counters that are equivalent in function to those found in one 8254 programmable interval timer. These three counters are combined to provide the system timer function, and speaker tone. The 14.31818 MHz oscillator input provides the clock source for these three counters. The PCHPCH provides an ISA-Compatible Programmable Interrupt Controller (PIC) that incorporates the functionality of two, 8259 interrupt controllers. The two interrupt controllers are cascaded so that 14 external and two internal interrupts are possible. In addition, the PCH supports a serial interrupt scheme. All of the registers in these modules can be read and restored. This is required to save and restore system state after power has been removed and restored to the platform. Advanced Programmable Interrupt Controller (APIC) In addition to the standard ISA compatible Programmable Interrupt controller (PIC) described in the previous section, the PCH incorporates the Advanced Programmable Interrupt Controller (APIC). Universal Serial Bus (USB) Controllers The PCH has up to two Enhanced Host Controller Interface (EHCI) host controllers that support USB high-speed signaling. High-speed USB 2.0 allows data transfers up to 480 Mb/s which is 40 times faster than full-speed USB. The PCH supports up to fourteen USB 2.0 ports. All fourteen ports are high-speed, full-speed, and low-speed capable. Gigabit Ethernet Controller The Gigabit Ethernet Controller provides a system interface using a PCI function. The controller provides a full memory-mapped or IO mapped interface along with a 64-bit address master support for systems using more than 4 GB of physical memory and DMA (Direct Memory Addressing) mechanisms for high performance data transfers. Its bus master capabilities enable the component to process high-level commands and perform multiple operations; this lowers processor utilization by off-loading communication tasks from the processor. Two large configurable transmit and receive FIFOs (up to 20 KB each) help prevent data underruns and overruns while waiting for bus accesses. This enables the integrated LAN controller to transmit data with minimum interframe spacing (IFS). The LAN controller can operate at multiple speeds (10/100/1000 MB/s) and in either full duplex or half duplex mode. In full duplex mode the LAN controller adheres with the IEEE 802.3x Flow Control Specification. Half duplex performance is enhanced by a proprietary collision reduction mechanism. See Section 5.4 for details. RTC The PCH contains a Motorola MC146818B-compatible real-time clock with 256 bytes of battery-backed RAM. The real-time clock performs two key functions: keeping track of the time of day and storing system data, even when the system is powered down. The RTC operates on a 32.768 KHz crystal and a 3 V battery. The RTC also supports two lockable memory ranges. By setting bits in the configuration space, two 8-byte ranges can be locked to read and write accesses. This prevents unauthorized reading of passwords or other system security information. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 47 Introduction The RTC also supports a date alarm that allows for scheduling a wake up event up to 30 days in advance, rather than just 24 hours in advance. GPIO Various general purpose inputs and outputs are provided for custom system design. The number of inputs and outputs varies depending on the PCH configuration. Enhanced Power Management The PCH's power management functions include enhanced clock control and various low-power (suspend) states (for example, Suspend-to-RAM and Suspend-to-Disk). A hardware-based thermal management circuit permits software-independent entrance to low-power states. The PCH contains full support for the Advanced Configuration and Power Interface (ACPI) Specification, Revision 4.0a. Intel(R) Active Management Technology (Intel(R) AMT) (Available on specific SKUs Only) Intel(R) AMT is a fundamental component of Intel(R) vProTM technology. Intel(R) AMT is a set of advanced manageability features developed as a direct result of IT customer feedback gained through Intel market research. With the advent of powerful tools like the Intel(R) System Defense Utility, the extensive feature set of Intel(R) AMT easily integrates into any network environment. See Section 1.3 for details on SKU feature availability. Manageability In addition to Intel(R) AMT the PCH integrates several functions designed to manage the system and lower the total cost of ownership (TCO) of the system. These system management functions are designed to report errors, diagnose the system, and recover from system lockups without the aid of an external microcontroller. * TCO Timer. The PCH's integrated programmable TCO timer is used to detect system locks. The first expiration of the timer generates an SMI# that the system can use to recover from a software lock. The second expiration of the timer causes a system reset to recover from a hardware lock. * Processor Present Indicator. The PCH looks for the processor to fetch the first instruction after reset. If the processor does not fetch the first instruction, the PCH will reboot the system. * ECC Error Reporting. When detecting an ECC error, the host controller has the ability to send one of several messages to the PCH. The host controller can instruct the PCH to generate either an SMI#, NMI, SERR#, or TCO interrupt. * Function Disable. Function Disable. The PCH provides the ability to disable most integrated functions, including integrated LAN, USB, LPC, Intel HD Audio, SATA, PCI Express, and SMBus. Once disabled, functions no longer decode I/O, memory, or PCI configuration space. Also, no interrupts or power management events are generated from the disabled functions. * Intruder Detect. The PCH provides an input signal (INTRUDER#) that can be attached to a switch that is activated by the system case being opened. The PCH can be programmed to generate an SMI# or TCO interrupt due to an active INTRUDER# signal. 48 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Introduction System Management Bus (SMBus 2.0) The PCH contains an SMBus Host interface that allows the processor to communicate with SMBus slaves. This interface is compatible with most I2C devices. Special I2C commands are implemented. The PCH's SMBus host controller provides a mechanism for the processor to initiate communications with SMBus peripherals (slaves). Also, the PCH supports slave functionality, including the Host Notify protocol. Hence, the host controller supports eight command protocols of the SMBus interface (see System Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify. The PCH's SMBus also implements hardware-based Packet Error Checking for data robustness and the Address Resolution Protocol (ARP) to dynamically provide address to all SMBus devices. Intel(R) HD Audio Controller The Intel(R) High Definition Audio Specification defines a digital interface that can be used to attach different types of codecs, such as audio and modem codecs. The PCH Intel(R) HD Audio controller supports up to 4 codecs. The link can operate at either 3.3 V or 1.5 V. With the support of multi-channel audio stream, 32-bit sample depth, and sample rate up to 192 kHz, the Intel(R) HD Audio controller provides audio quality that can deliver CE levels of audio experience. On the input side, the PCH adds support for an array of microphones. Fan Speed Control The PCH integrates four fan speed sensors (four TACH signals) and four fan speed controllers (three Pulse Width Modulator signals), which enables monitoring and controlling up to four fans on the system. With the new implementation of the singlewire Simple Serial Transport (SST) 1.0 bus and Platform Environmental Control Interface (PECI), the PCH provides an easy way to connect to SST-based thermal sensors and access the processor thermal data. Intel(R) Virtualization Technology for Directed I/O (Intel(R) VT-d) (Not available on HEDT SKU) The PCH provides hardware support for implementation of Intel(R) Virtualization Technology with Directed I/O (Intel(R) VT-d). Intel(R) VT-d consists of technology components that support the virtualization of platforms based on Intel(R) Architecture Processors. Intel(R) VT-d 5 technology enables multiple operating systems and applications to run in independent partitions. A partition behaves like a virtual machine (VM) and provides isolation and protection across partitions. Each partition is allocated its own subset of host physical memory. JTAG Boundary-Scan The PCH adds the industry standard JTAG interface and enables Boundary-Scan in place of the XOR chains used in previous generations of chipsets. Boundary-Scan can be used to ensure device connectivity during the board manufacturing process. The JTAG interface allows system manufacturers to improve efficiency by using industry available tools to test the PCH on an assembled board. Since JTAG is a serial interface, it eliminates the need to create probe points for every pin in an XOR chain. This eases pin breakout and trace routing and simplifies the interface between the system and a bed-of-nails tester. Note: Contact your local Intel Field Sales Representative for additional information about JTAG usage on the PCH. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 49 Introduction Serial Over Lan (SOL) Function (Not available on HEDTSKU) This function supports redirection of keyboard and text screens to a terminal window on a remote console. The keyboard and text redirection enables the control of the client machine through the network without the need to be physically near that machine. Text and keyboard redirection allows the remote machine to control and configure a client system. The SOL function emulates a standard PCI device and redirects the data from the serial port to the management console using the integrated LAN. IDE-R Function (Not available on HEDT SKU) The IDE-R function is an IDE Redirection interface that provides client connection to management device attached through IDE-R is only visible to software during a management boot session. During normal boot session, the IDE-R controller does not appear as a PCI present device. 1.3 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset SKU Definition Table 1-2. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset SKUs Product Number SATA 6G Ports(#) SCU Ports(#) PCIe* Uplink SM Bus Intel(R) AMT Intel(R) VT-D Intel(R) C600 Series Chipset (Server/Workstation) Intel (R) C602 2 4 (SATA only) No 4 Yes Yes C602J 2 0 No 4 Yes Yes C604 2 4 No 4 Yes Yes C606 2 8 Yes 5 Yes Yes C608 2 8 Yes 6 Yes Yes No 3 No No X79 Express Chipset (High End Desktop) X79 2 No Notes: 1. Contact your local Intel Field Sales Representative for currently available Intel C600 Series Chipset and Intel X79 Express Chipset SKUs. 2. Table above shows feature difference between Intel C600 Series Chipset and Intel X79 Express Chipset SKUs. If a feature is not listed in the table it is considered a Base feature that is included in all SKUs. 50 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Signal Description 2 Signal Description This chapter provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The "#" symbol at the end of the signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When "#" is not present, the signal is asserted when at the high voltage level. The following notations are used to describe the signal type: I Input Pin O Output Pin OD O Open Drain Output Pin. I/OD Bi-directional Input/Open Drain Output Pin. I/O Bi-directional Input / Output Pin. CMOS CMOS buffers. 1.5 V tolerant. COD CMOS Open Drain buffers. 3.3 V tolerant. HVCMOS High Voltage CMOS buffers. 3.3 V tolerant. A Analog reference or output. The "Type" for each signal is indicative of the functional operating mode of the signal. Unless otherwise noted Section 3.2 or Section 3.3, a signal is considered to be in the functional operating mode after RTCRST# deasserts for signals in the RTC well, after RSMRST# deasserts for signals in the suspend well, and after PCH_PWROK asserts for signals in the core well, after DPWROK asserts for Signals in the Deep Sleep well, after APWROK asserts for Signals in the Active Sleep well. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 51 Signal Description Figure 2-1. PCH Interface Signals Block Diagram AD[31:0] C/BE[3:0]# DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PERR# REQ0# REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54 GNT0# GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55 SERR# PME# CLKIN_PCILOOPBACK PCIRST# PLOCK# INIT3_3V# RCIN# A20GATE PROCPWRGD PM_SYNC;PM_SYNC2 SPI_CS0#; SPI_CS1# SPI_MISO SPI_MOSI SPI_CLK PCIe Uplink (PBG - D/T) PCI Express* Interface PCI Interface Serial ATA Interface SPI Power Mgnt. CLKIN_SATA_[P:N] CLKIN_DOT96P;CLKIN_DOT96N REF14CLKIN Intel(R) High Definition Audio Clock Inputs CLKIN_SAS0_P;CLKIN_SAS0_N CLKIN_SAS1_P;CLKIN_SAS1_N Direct Media Interface CLKIN_SPCIE0_P;CLKIN_SPCIE0_N SERIRQ PIRQ[D:A]# PIRQ[H:E]#/GPIO[5:2] USB[13:0]P; USB[13:0]N OC0#/GPIO59; OC1#/GPIO40 OC2#/GPIO41; OC3#/GPIO42 OC4#/GPIO43; OC5#/GPIO9 OC6#/GPIO10; OC7#/GPIO14 USBRBIAS USBRBIAS# RTCX1 RTCX2 INTVRMEN SPKR SRTCRST#; RTCRST# DSWODVREN NMI# SMI# GPIO[72,57,35,32,28, 27,15,8] PWM[3:0] TACH0/GPIO17; TACH1/GPIO1 TACH2/GPIO6; TACH3/GPIO7 TACH4/GPIO68; TACH5/GPIO69 TACH6/GPIO70; TACH7/GPIO71 SST PECI 52 Interrupt Interface LPC / FWH Interface SMBus Interface System Mgnt. USB2 SAS SMBus RTC Misc. Signals General Purpose I/O PETp[8:1], PETn[8:1] PERp[8:1], PERn[8:1] SATA[5:0]TXP, SATA[5:0]TXN SATA[5:0]RXP, SATA[5:0]RXN SATAICOMPO SATAICOMPI SATALED# SATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36 SATA3GP/GPIO37 SATA4GP/GPIO16 SATA5GP/GPIO49 SCLOCK/GPIO22 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 Processor Interface CLKIN_DMI_P;CLKIN_DMI_N PEG0_RXN[3:0], PEG_RXP[3:0] PEG0_TXN[3:0], PEG0_TXP[3:0] PEG0_RBIASP, PEG0RBIASN Serial Attached SCSI Interface Fan Speed Control JTAG* THRMTRIP# SYS_RESET# RSMRST# SLP_S3# SLP_S4# SLP_S5#/GPIO63 SLP_A# SLP_SUS# PCH_PWROK APWROK PWRBTN# RI# WAKE# GPIO61 SUSCLK/GPIO62 SUSACK# SYS_PWROK PLTRST# SUSWARN#/SUSWRDNACK BMBUSY#/GPIO0 STP_PCI#/GPIO34 ADR_COMPLETE DRAMPWROK LAN_PHY_PWR_CTRL SLP_LAN#/GPIO29 HDA_RST# HDA_SYNC HDA_BCLK HDA_SDO HDA_SDIN[3:0] DMI[3:0]TXP, DMI[3:0]TXN DMI[3:0]RXP, DMI[3:0]RXN DMI_ZCOMP, DMIRBIAS DMI_IRCOMP LAD[3:0 LFRAME# LDRQ0#; LDRQ1#/GPIO23 SMBDATA; SMBCLK SMBALERT#/GPIO11 INTRUDER#; SML[0:1]DATA;SML[0:1]CLK; SML0ALERT#/GPIO60 SML1ALERT#/GPIO74 MEM_LED/GPIO24; SASSMBCLK0; SASSMBDATA0; SASSMBCLK1; SASSMBDATA1; SASSMBCLK2; SASSMBDATA2; SAS[3:0]TXP;SAS[3:0]TXN; SAS[3:0]RXP;SAS[3:0]RXN; SAS[7:4]TXP;SAS[7:4]TXN; (PBG-D/T) SAS[7:4]RXP;SAS[7:4]RXN;(PBG-D/T) SAS_CLOCK1;SAS_LOAD1; SAS_DATAIN1;SAS_DATAOUT1; SAS_CLOCK2;SAS_LOAD2; SAS_DATAIN2;SAS_DATAOUT2; SAS_LED# SAS_RBIASP0;SAS_RBIASN0; SAS_RBIASP1;SAS_RBIASN1; JTAGTCK JTAGTMS JTAGTDI JTAGTDO Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Signal Description 2.1 Direct Media Interface (DMI) to Host Controller Table 2-1. Direct Media Interface Signals Name Type Description DMI_TXP_0, DMI_TXN_0 O Direct Media Interface Differential Transmit Pair 0 DMI_RXP_0, DMI_RXN_0 I Direct Media Interface Differential Receive Pair 0 DMI_TXP_1, DMI_TXN_1 O Direct Media Interface Differential Transmit Pair 1 DMI_RXP_1, DMI_RXN_1 I Direct Media Interface Differential Receive Pair 1 DMI_TXP_2, DMI_TXN_2 O Direct Media Interface Differential Transmit Pair 2 DMI_RXP_2, DMI_RXN_2 I Direct Media Interface Differential Receive Pair 2 DMI_TXP_3, DMI_TXN_3 O Direct Media Interface Differential Transmit Pair 3 DMI_RXP_3, DMI_RXN_3 I Direct Media Interface Differential Receive Pair 3 DMI_ZCOMP I Impedance Compensation Input: Determines DMI input impedance. DMI_IRCOMP O Impedance/Current Compensation Output: Determines DMI output impedance and bias current. DMIRBIAS I/O DMIRBIAS: Analog connection point for 750 1% external precision resistor 2.2 PCI Express* Table 2-2. PCI Express* Signals Name PETp1, PETn1 Type Description O PCI Express* Differential Transmit Pair 1 PERp1, PERn1 I PCI Express Differential Receive Pair 1 PETp2, PETn2 O PCI Express Differential Transmit Pair 2 PERp2, PERn2 I PCI Express Differential Receive Pair 2 PETp3, PETn3 O PCI Express Differential Transmit Pair 3 PERp3, PERn3 I PCI Express Differential Receive Pair 3 PETp4, PETn4 O PCI Express Differential Transmit Pair 4 PERp4, PERn4 I PCI Express Differential Receive Pair 4 PETp5, PETn5 O PCI Express Differential Transmit Pair 5 PERp5, PERn5 I PCI Express Differential Receive Pair 5 PETp6, PETn6 O PCI Express Differential Transmit Pair 6 PERp6, PERn6 I PCI Express Differential Receive Pair 6 PETp7, PETn7 O PCI Express Differential Transmit Pair 7 PERp7, PERn7 I PCI Express Differential Receive Pair 7 PETp8, PETn8 O PCI Express Differential Transmit Pair 8 PERp8, PERn8 I PCI Express Differential Receive Pair 8 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 53 Signal Description 2.3 PCI Express* Uplink (Intel(R) C606, C608 Chipset SKUs Only) Note: These signals are not used on the HEDT SKU PCH and should be no connects. Table 2-3. PCI Express* Uplink Signals Name Type Description PEG0_Tp[3:0], PEG0_Tn[3:0] O PCI Express* Uplink Differential Transmit Pairs PEG0_Rp[3:0], PEG0_Rn[3:0] I PCI Express* Uplink Differential Receive Pairs PEG0_RBIASP, PEG0_RBIASN I Analog connection points for an external resistor. Used to set transmit currents and internal load resistors 2.4 PCI Interface Table 2-4. PCI Interface Signals (Sheet 1 of 3) Name Type Description AD[31:0] I/O PCI Address/Data: AD[31:0] is a multiplexed address and data bus. During the first clock of a transaction, AD[31:0] contain a physical address (32 bits). During subsequent clocks, AD[31:0] contain data. The PCH will drive all 0s on AD[31:0] during the address phase of all PCI Special Cycles. Bus Command and Byte Enables: The command and byte enable signals are multiplexed on the same PCI pins. During the address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase C/ BE[3:0]# define the Byte Enables. C/BE[3:0]# C/BE[3:0]# I/O Command Type 0000b Interrupt Acknowledge 0001b Special Cycle 0010b I/O Read 0011b I/O Write 0110b Memory Read 0111b Memory Write 1010b Configuration Read 1011b Configuration Write 1100b Memory Read Multiple 1110b Memory Read Line 1111b Memory Write and Invalidate All command encodings not shown are reserved. The PCH does not decode reserved values, and therefore will not respond if a PCI master generates a cycle using one of the reserved values. DEVSEL# FRAME# 54 I/O Device Select: The PCH asserts DEVSEL# to claim a PCI transaction. As an output, the PCH asserts DEVSEL# when a PCI master peripheral attempts an access to an internal PCH address or an address destined for DMI (main memory or graphics). As an input, DEVSEL# indicates the response to a PCHinitiated transaction on the PCI bus. DEVSEL# is tri-stated from the leading edge of PLTRST#. DEVSEL# remains tri-stated by the PCH until driven by a target device. I/O Cycle Frame: The current initiator drives FRAME# to indicate the beginning and duration of a PCI transaction. While the initiator asserts FRAME#, data transfers continue. When the initiator negates FRAME#, the transaction is in the final data phase. FRAME# is an input to the PCH when the PCH is the target, and FRAME# is an output from the PCH when the PCH is the initiator. FRAME# remains tri-stated by the PCH until driven by an initiator. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Signal Description Table 2-4. PCI Interface Signals (Sheet 2 of 3) Name Type Description I/O Initiator Ready: IRDY# indicates the PCH's ability, as an initiator, to complete the current data phase of the transaction. It is used in conjunction with TRDY#. A data phase is completed on any clock both IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates the PCH has valid data present on AD[31:0]. During a read, it indicates the PCH is prepared to latch data. IRDY# is an input to the PCH when the PCH is the target and an output from the PCH when the PCH is an initiator. IRDY# remains tri-stated by the PCH until driven by an initiator. TRDY# I/O Target Ready: TRDY# indicates the PCH's ability as a target to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed when both TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that the PCH, as a target, has placed valid data on AD[31:0]. During a write, TRDY# indicates the PCH, as a target is prepared to latch data. TRDY# is an input to the PCH when the PCH is the initiator and an output from the PCH when the PCH is a target. TRDY# is tri-stated from the leading edge of PLTRST#. TRDY# remains tri-stated by the PCH until driven by a target. STOP# I/O Stop: STOP# indicates that the PCH, as a target, is requesting the initiator to stop the current transaction. STOP# causes the PCH, as an initiator, to stop the current transaction. STOP# is an output when the PCH is a target and an input when the PCH is an initiator. PAR I/O Calculated/Checked Parity: PAR uses "even" parity calculated on 36 bits, AD[31:0] plus C/BE[3:0]#. "Even" parity means that the PCH counts the number of ones within the 36 bits plus PAR and the sum is always even. The PCH always calculates PAR on 36 bits regardless of the valid byte enables. The PCH generates PAR for address and data phases and only ensures PAR to be valid one PCI clock after the corresponding address or data phase. The PCH drives and tri-states PAR identically to the AD[31:0] lines except that the PCH delays PAR by exactly one PCI clock. PAR is an output during the address phase (delayed one clock) for all PCH initiated transactions. PAR is an output during the data phase (delayed one clock) when the PCH is the initiator of a PCI write transaction, and when it is the target of a read transaction. PCH checks parity when it is the target of a PCI write transaction. If a parity error is detected, the PCH will set the appropriate internal status bits, and has the option to generate an NMI# or SMI#. PERR# I/O Parity Error: An external PCI device drives PERR# when it receives data that has a parity error. The PCH drives PERR# when it detects a parity error. The PCH can either generate an NMI# or SMI# upon detecting a parity error (either detected internally or reported using the PERR# signal). I PCI Requests: The PCH supports up to 4 masters on the PCI bus. REQ[3:1]# pins can instead be used as GPIO. REQ[3:1]# pins can also be use as GSX signals. (See Section 2.23 for details.) Notes: External pull-up resistor is required. When used as native functionality, the pull-up resistor may be to either 3.3 V or 5.0 V per PCI specification. When used as GPIO or not used at all, the pull-up resistor should be to the Vcc3_3 rail IRDY# REQ0# REQ1#/ GPIO50 / GSXCLK REQ2#/ GPIO52 / GSXSLOAD REQ3#/GPIO54 / GSXRESET# PCI Grants: The PCH supports up to 4 masters on the PCI bus. GNT[3:1]# pins can instead be used as GPIO. GNT[2:1]# pins can also be use as GSX signals. (See Section 2.23 for details.) Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3 power rail. GNT0# GNT1#/ GPIO51 / GSXDOUT GNT2#/ GPIO53 / GSXDIN GNT3#/GPIO55 O PCIRST# O PCI Reset: This is the Secondary PCI Bus reset signal. It is a logical OR of the primary interface PLTRST# signal and the state of the Secondary Bus Reset bit of the Bridge Control register (D30:F0:3Eh, bit 6). PLOCK# I/O PCI Lock: This signal indicates an exclusive bus operation and may require multiple transactions to complete. PCH asserts PLOCK# when it performs non-exclusive transactions on the PCI bus. PLOCK# is ignored when PCI masters are granted the bus. SERR# I/OD System Error: SERR# can be pulsed active by any PCI device that detects a system error condition. Upon sampling SERR# active, the PCH has the ability to generate an NMI, SMI#, or interrupt. Note: Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet GNT[3:1]#/GPIO[55,53,51] are sampled as a functional strap. See Section 2.26.1 for details. 55 Signal Description Table 2-4. PCI Interface Signals (Sheet 3 of 3) Name PME# Type Description I/OD PCI Power Management Event: PCI peripherals drive PME# to wake the system from low-power states S1-S5. PME# assertion can also be enabled to generate an SCI from the S0 state. In some cases the PCH may drive PME# active due to an internal wake event. The PCH will not drive PME# high, but it will be pulled up to VccSus3_3 by an internal pull-up resistor. 2.5 Serial ATA Interface Table 2-5. Serial ATA Interface Signals (Sheet 1 of 2) Name Description SATA0TXP SATA0TXN O Serial ATA 0 Differential Transmit Pairs: These are outbound high-speed differential signals to Port 0. In compatible mode, SATA Port 0 is the primary master of SATA Controller 1. Supports up to 6 Gb/s, 3 Gb/s, and 1.5 Gb/s. SATA0RXP SATA0RXN I Serial ATA 0 Differential Receive Pair: These are inbound high-speed differential signals from Port 0. In compatible mode, SATA Port 0 is the primary master of SATA Controller 1. Supports up to 6 Gb/s, 3 Gb/s, and 1.5 Gb/s. SATA1TXP SATA1TXN O Serial ATA 1 Differential Transmit Pair: These are outbound high-speed differential signals to Port 1. In compatible mode, SATA Port 1 is the secondary master of SATA Controller 1. Supports up to 6 Gb/s, 3 Gb/s, and 1.5 Gb/s. I Serial ATA 1 Differential Receive Pair: These are inbound high-speed differential signals from Port 1. In compatible mode, SATA Port 1 is the secondary master of SATA Controller 1. Supports up to 6 Gb/s, 3 Gb/s, and 1.5 Gb/s. SATA2TXP SATA2TXN O Serial ATA 2 Differential Transmit Pair: These are outbound high-speed differential signals to Port 2. In compatible mode, SATA Port 2 is the primary slave of SATA Controller 1. Supports up to 3 Gb/s and 1.5 Gb/s. SATA2RXP SATA2RXN I Serial ATA 2 Differential Receive Pair: These are inbound high-speed differential signals from Port 2. In compatible mode, SATA Port 2 is the primary slave of SATA Controller 1 Supports up to 3 Gb/s and 1.5 Gb/s. SATA3TXP SATA3TXN O Serial ATA 3 Differential Transmit Pair: These are outbound high-speed differential signals to Port 3 In compatible mode, SATA Port 3 is the secondary slave of SATA Controller 1 Supports up to 3 Gb/s and 1.5 Gb/s. I Serial ATA 3 Differential Receive Pair: These are inbound high-speed differential signals from Port 3 In compatible mode, SATA Port 3 is the secondary slave of SATA Controller 1 Supports up to 3 Gb/s and 1.5 Gb/s. SATA4TXP SATA4TXN O Serial ATA 4 Differential Transmit Pair: These are outbound high-speed differential signals to Port 4. In compatible mode, SATA Port 4 is the primary master of SATA Controller 2. Supports up to 3 Gb/s and 1.5 Gb/s. SATA4RXP SATA4RXN I Serial ATA 4 Differential Receive Pair: These are inbound high-speed differential signals from Port 4. In compatible mode, SATA Port 4 is the primary master of SATA Controller 2. Supports up to 3 Gb/s and 1.5 Gb/s. SATA5TXP SATA5TXN O Serial ATA 5 Differential Transmit Pair: These are outbound high-speed differential signals to Port 5. In compatible mode, SATA Port 5 is the secondary master of SATA Controller 2. Supports up to 3 Gb/s and 1.5 Gb/s. SATA1RXP SATA1RXN SATA3RXP SATA3RXN 56 Type Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Signal Description Table 2-5. Serial ATA Interface Signals (Sheet 2 of 2) Name Type Description SATA5RXP SATA5RXN I Serial ATA 5 Differential Receive Pair: These are inbound high-speed differential signals from Port 5. In compatible mode, SATA Port 5 is the secondary master of SATA Controller 2. Supports up to 3 Gb/s and 1.5 Gb/s. SATAICOMPO O Serial ATA Compensation Output: Connected to an external precision resistor to VccCore. Must be connected to SATAICOMPI on the board. SATAICOMPI I Serial ATA Compensation Input: Connected to SATAICOMPO on the board. SATA0GP / GPIO21 I Serial ATA 0 General Purpose: This is an input pin which can be configured as an interlock switch corresponding to SATA Port 0. When used as an interlock switch status indication, this signal should be drive to `0' to indicate that the switch is closed and to `1' to indicate that the switch is open. If interlock switches are not required, this pin can be configured as GPIO21. SATA1GP / GPIO19 I Serial ATA 1 General Purpose: Same function as SATA0GP, except for SATA Port 1. If interlock switches are not required, this pin can be configured as GPIO19. SATA2GP / GPIO36 I Serial ATA 2 General Purpose: Same function as SATA0GP, except for SATA Port 2. If interlock switches are not required, this pin can be configured as GPIO36. SATA3GP / GPIO37 I Serial ATA 3 General Purpose: Same function as SATA0GP, except for SATA Port 3. If interlock switches are not required, this pin can be configured as GPIO37. SATA4GP / GPIO16 I Serial ATA 4 General Purpose: Same function as SATA0GP, except for SATA Port 4. If interlock switches are not required, this pin can be configured as GPIO16. SATA5GP / GPIO49 / TEMP_ALERT# I Serial ATA 5 General Purpose: Same function as SATA0GP, except for SATA Port 5. If interlock switches are not required, this pin can be configured as GPIO49 or TEMP_ALERT#. SATALED# OD O Serial ATA LED: This signal is an open-drain output pin driven during SATA command activity. It is to be connected to external circuitry that can provide the current to drive a platform LED. When active, the LED is on. When tristated, the LED is off. An external pull-up resistor to Vcc3_3 is required. SCLOCK/GPIO22 OD O SGPIO Reference Clock: The SATA controller uses rising edges of this clock to transmit serial data, and the target uses the falling edge of this clock to latch data. The SCLOCK frequency supported is 32 kHz. If SGPIO interface is not used, this signal can be used as a GPIO22. SLOAD/GPIO38 OD O SGPIO Load: The controller drives a `1' at the rising edge of SCLOCK to indicate either the start or end of a bit stream. A 4-bit vendor specific pattern will be transmitted right after the signal assertion. If SGPIO interface is not used, this signal can be used as a GPIO. SDATAOUT0/ GPIO39 SDATAOUT1/ GPIO48 OD O SGPIO Dataout: Driven by the controller to indicate the drive status in the following sequence: drive 0, 1, 2, 3, 4, 5, 0, 1, 2... If SGPIO interface is not used, the signals can be used as GPIO. SATA3RBIAS I/O SATA3COMPI I Impedance Compensation Input: Connected to a 50 ohm (1%) precision external pull-up resistor to vccsata3. SATA3COMPO O Impedance/Current Compensation Output: Connected to a 50 ohm (1%) precision external pull-up resistor.to vccsata3. DMI RBIAS: Analog connection point for an external precision resistor. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 57 Signal Description 2.6 SAS Interface (SRV/WS SKUs Only) Note: These signals are not used on the HEDT SKU. Table 2-6. SAS Interface Signals (Sheet 1 of 2) 58 Name Type Description SAS0TXP SAS0TXN O SAS/SATA 0 Differential Transmit Pairs: These are outbound highspeed differential signals to Port 0. Note: On Intel C602 Chipset SKU, work as SATA port only. Note: On HEDT SKU, these signals should be no connects. SAS0RXP SAS0RXN I SAS/SATA 0 Differential Receive Pair: These are inbound high-speed differential signals from Port 0. Note: On Intel C602 Chipset, work as SATA port only. Note: On HEDT SKU, these signals should be no connects. SAS1TXP SAS1TXN O SAS/SATA 1 Differential Transmit Pairs: These are outbound highspeed differential signals to Port 1. Note: On Intel C602 Chipset, work as SATA port only. Note: On HEDT SKU, these signals should be no connects. SAS1RXP SAS1RXN I SAS/SATA 1 Differential Receive Pair: These are inbound high-speed differential signals from Port 1. Note: On Intel C602 Chipset, work as SATA port only. Note: On HEDT SKU, these signals should be no connects. SAS2TXP SAS2TXN O SAS/SATA 2 Differential Transmit Pairs: These are outbound highspeed differential signals to Port 2. Note: On Intel C602 Chipset, work as SATA port only. Note: On HEDT SKU, these signals should be no connects. SAS2RXP SAS2RXN I SAS/SATA 2 Differential Receive Pair: These are inbound high-speed differential signals from Port 2. Note: On Intel C602 Chipset, work as SATA only. Note: On HEDT SKU, these signals should be no connects. SAS3TXP SAS3TXN O SAS/SATA 3 Differential Transmit Pairs: These are outbound highspeed differential signals to Port 3. Note: On Intel C602 Chipset, work as SATA port only. Note: On HEDT SKU, these signals should be no connects. SAS3RXP SAS3RXN I SAS/SATA 3 Differential Receive Pair: These are inbound high-speed differential signals from Port 3. Note: On Intel C602 Chipset, work as SATA port only. Note: On HEDT SKU, these signals should be no connects. SAS4TXP SAS4TXN (Intel(R) C606, C608 Chipset SKUs Only) O SAS 4 Differential Transmit Pairs: These are outbound high-speed differential signals to Port 4. Note: On HEDT SKU, these signals should be no connects. SAS4RXP SAS4RXN (Intel(R) C606, C608 Chipset SKUs Only) I SAS 4 Differential Receive Pair: These are inbound high-speed differential signals from Port 4. Note: On HEDT SKU, these signals should be no connects. SAS5TXP SAS5TXN (Intel(R) C606, C608 Chipset SKUs Only) O SAS 5 Differential Transmit Pairs: These are outbound high-speed differential signals to Port 5. Note: On HEDT SKU, these signals should be no connects. SAS5RXP SAS5RXN (Intel(R) C606, C608 Chipset SKUs Only) I SAS 5 Differential Receive Pair: These are inbound high-speed differential signals from Port 5. Note: On HEDT SKU, these signals should be no connects. SAS6TXP SAS6TXN (Intel(R) C606, C608 Chipset SKUs Only) O SAS 6 Differential Transmit Pairs: These are outbound high-speed differential signals to Port 6. Note: On HEDT SKU, these signals should be no connects. SAS6RXP SAS6RXN (Intel(R) C606, C608 Chipset SKUs Only) I SAS 6 Differential Receive Pair: These are inbound high-speed differential signals from Port 6. Note: On HEDT SKU, these signals should be no connects. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Signal Description Table 2-6. SAS Interface Signals (Sheet 2 of 2) Name Type SAS7TXP SAS7TXN (Intel(R) C606, C608 Chipset SKUs Only) O SAS 7 Differential Transmit Pairs: These are outbound high-speed differential signals to Port 7. Note: On HEDT SKU, these signals should be no connects. SAS7RXP SAS7RXN (Intel(R) C606, C608 Chipset SKUs Only) I SAS 7 Differential Receive Pair: These are inbound high-speed differential signals from Port 7. Note: On HEDT SKU, these signals should be no connects. SAS_CLOCK1 O SCU SGPIO reference clock Note: On HEDT SKU, this signal should be no connect. SAS_LOAD1 O SCU SGPIO load Note: On HEDT SKU, this signal should be no connect. SAS_DATAIN1 O SCU SGPIO data in Note: On HEDT SKU, this signal should be no connect. SAS_DATAOUT1 O SCU SGPIO data out Note: On HEDT SKU, this signal should be no connect. SAS_CLOCK2 (Intel(R) C606, C608 Chipset SKUs Only) O Used in Intel(R) C606, C608 Chipset SKUs Only Note: On HEDT SKU, this signal should be no connect. SAS_LOAD2 (Intel(R) C606, C608 Chipset SKUs Only) O Used in Intel(R) C606, C608 Chipset SKUs Only Note: On HEDT SKU, this signal should be no connect. SAS_DATAIN2 (Intel(R) C606, C608 Chipset SKUs Only) O Used in Intel(R) C606, C608 Chipset SKUs Only Note: On HEDT SKU, these signals should be no connects. SAS_DATAOUT2 (Intel(R) C606, C608 Chipset SKUs Only) O Used in Intel(R) C606, C608 Chipset SKUs Only Note: On HEDT SKU, this signal should be no connect. SAS_LED# O Open drain pin used to control the Front Panel LED. Note: On HEDT SKU, this signal should be no connect. I Analog connection points for an external resistor. Used to set transmit internal loads and currents. Notes: On HEDT SKU, this signal tied to SAS_RBIASN0 through a 6.0 K 1% resistor. SAS_RBIASNO should be connected to VSS at the resistor. SAS_RBIASN0 I Analog connection points for an external resistor. Used to set transmit internal loads and currents. Note: On HEDT SKU, this signal tied to SAS_RBIASN0 through a 6.0 K 1% resistor. SAS_RBIASNO should be connected to VSS at the resistor. SAS_RBIASP1 (Intel(R) C606, C608 Chipset SKUs Only) I Analog connection points for an external resistor. Used to set transmit internal loads and currents. Note: On HEDT SKU, this signal should be no connect. SAS_RBIASN1 (Intel(R) C606, C608 Chipset SKUs Only) I Analog connection points for an external resistor. Used to set transmit internal loads and currents. Note: On HEDT SKU, this signal should be no connect. SAS_RBIASP0 Description Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 59 Signal Description 2.7 LPC Interface Table 2-7. LPC Interface Signals Name Type LAD[3:0] I/O LFRAME# O LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort. I LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to request DMA or bus master access. These signals are typically connected to an external Super I/O device. An internal pull-up resistor is provided on these signals. LDRQ1# may optionally be used as GPIO. LDRQ0#, LDRQ1# / GPIO23 Description LPC Multiplexed Command, Address, Data: For LAD[3:0], internal pull-ups are provided. 2.8 Interrupt Interface Table 2-8. Interrupt Signals Name Type SERIRQ I/OD Serial Interrupt Request: This pin implements the serial interrupt protocol. I/OD PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in Section 5.9.6. Each PIRQx# line has a separate Route Control register. In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQA# is connected to IRQ16, PIRQB# to IRQ17, PIRQC# to IRQ18, and PIRQD# to IRQ19. This frees the legacy interrupts. These signals are 5 V tolerant. I/OD PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in Section 5.9.6. Each PIRQx# line has a separate Route Control register. In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQE# is connected to IRQ20, PIRQF# to IRQ21, PIRQG# to IRQ22, and PIRQH# to IRQ23. This frees the legacy interrupts. If not needed for interrupts, these signals can be used as GPIO. These signals are 5 V tolerant. PIRQ[D:A]# PIRQ[H:E]# / GPIO[5:2] Note: 60 Description PIRQ Interrupts can only be shared if it is configured as level sensitive. They cannot be shared if configured as edge triggered. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Signal Description 2.9 USB 2.0 Interface Table 2-9. USB 2.0 Interface Signals (Sheet 1 of 2) Name USBP0P, USBP0N, USBP1P, USBP1N USBP2P, USBP2N, USBP3P, USBP3N USBP4P, USBP4N, USBP5P, USBP5N USBP6P, USBP6N, USBP7P, USBP7N USBP8P, USBP8N, USBP9P, USBP9N USBP10P, USBP10N, USBP11P, USBP11N USBP12P, USBP12N, USBP13P, USBP13N Type I/O I/O I/O Description Universal Serial Bus Port [1:0] Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 0 and 1. These ports can be routed to EHCI controller #1. Note: No external resistors are required on these signals. The PCH integrates 15 k pull-downs and provides an output driver impedance of 45 which requires no external series resistor. Universal Serial Bus Port [3:2] Differential: These differential pairs are used to transmit data/address/command signals for ports 2 and 3. These ports can be routed to EHCI controller #1. Note: No external resistors are required on these signals. The PCH integrates 15 k pull-downs and provides an output driver impedance of 45 which requires no external series resistor. Universal Serial Bus Port [5:4] Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 4 and 5. These ports can be routed to EHCI controller #1. Note: No external resistors are required on these signals. The PCH integrates 15 k pull-downs and provides an output driver impedance of 45 which requires no external series resistor. Universal Serial Bus Port [7:6] Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 6 and 7. These ports can be routed to EHCI controller #1. I/O Note: I/O I/O I/O No external resistors are required on these signals. The PCH integrates 15 k pull-downs and provides an output driver impedance of 45 which requires no external series resistor. Universal Serial Bus Port [9:8] Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 8 and 9. These ports can be routed to EHCI controller #2. Note: No external resistors are required on these signals. The PCH integrates 15 k pull-downs and provides an output driver impedance of 45 which requires no external series resistor. Universal Serial Bus Port [11:10] Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 10 and 11. These ports can be routed to EHCI controller #2. Note: No external resistors are required on these signals. The PCH integrates 15 k pull-downs and provides an output driver impedance of 45 which requires no external series resistor. Universal Serial Bus Port [13:12] Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 13 and 12. These ports can be routed to EHCI controller #2. Note: No external resistors are required on these signals. The PCH integrates 15 k pull-downs and provides an output driver impedance of 45 which requires no external series resistor. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 61 Signal Description Table 2-9. USB 2.0 Interface Signals (Sheet 2 of 2) Name Type Description OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 I USBRBIAS O USB Resistor Bias: Analog connection point for an external resistor. Used to set transmit currents and internal load resistors. USBRBIAS# I USB Resistor Bias Complement: Analog connection point for an external resistor. Used to set transmit currents and internal load resistors. Overcurrent Indicators: These signals set corresponding bits in the USB controllers to indicate that an overcurrent condition has occurred. OC[7:0]# may optionally be used as GPIOs. Notes: 1. 2. 3. 4. OC# pins are not 5 V tolerant. OC# pins must be shared between ports OC#[3:0] can only be used for EHCI controller #1 OC#[4:7] can only be used for EHCI controller #2 2.10 Power Management Interface Note: Upon entry to S5 due to a power button override, if Deep S4/S5 is enabled and conditions are met per Section 5.14.6.6, the system will transition to Deep S4/S5. Table 2-10. Power Management Interface Signals (Sheet 1 of 3) Name Type Description APWROK I Active Sleep Well (ASW) Power OK: When asserted, indicates that power to the ASW sub-system is stable. BMBUSY# / GPIO0 I Bus Master Busy: Generic bus master activity indication driven into the PCH. Can be configured to set the PM1_STS.BM_STS bit. Can also be configured to assert indications transmitted from the PCH to the Processor using the PM_SYNC pin. DPWROK I DPWROK: Power OK Indication for the VccDSW3_3 voltage rail. This input is tied together with RSMRST# on platforms that do not support Deep S4/S5. This signal is in the RTC well. DRAMPWROK LAN_PHY_PWR_ CTRL / GPIO12 OD O O DRAM Power OK: This signal should connect to the Processor's SM_DRAMPWROK pin. The PCH asserts this pin to indicate when DRAM power is stable. This pin requires an external pull-up. LAN PHY Power Control: LAN_PHY_PWR_CTRL should be connected to LAN_DISABLE_N on the PHY. The PCH will drive LAN_PHY_PWR_CTRL low to put the PHY into a low power state when functionality is not needed. Note: PLTRST# PWRBTN# 62 LAN_PHY_PWR_CTRL can only be driven low if SLP_LAN# is deasserted. Signal can instead be used as GPIO12. O Platform Reset: The PCH asserts PLTRST# to reset devices on the platform (for example, SIO, FWH, LAN, Processor, etc.). The PCH asserts PLTRST# during power-up and when S/W initiates a hard reset sequence through the Reset Control register (I/O Register CF9h). The PCH drives PLTRST# active a minimum of 1 ms when initiated through the Reset Control register (I/O Register CF9h). Note: PLTRST# is in the VccSus3_3 well. I Power Button: The Power Button will cause SMI# or SCI to indicate a system request to go to a sleep state. If the system is already in a sleep state, this signal will cause a wake event. If PWRBTN# is pressed for more than 4 seconds, this will cause an unconditional transition (power button override) to the S5 state. Override will occur even if the system is in the S1-S4 states. This signal has an internal pull-up resistor and has an internal 16 ms de-bounce on the input. This signal is in the DSW well. Note: Upon entry to S5 due to a power button override, if Deep S4/S5 is enabled and conditions are met per Section 5.14.6.6, the system will transition to Deep S4/S5. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Signal Description Table 2-10. Power Management Interface Signals (Sheet 2 of 3) Name Type Description PCH_PWROK I Power OK: When asserted, PCH_PWROK is an indication to PCH that all of its core powerrails has been stable for at least 10 ms. PCH_PWROK can be driven asynchronously. When PCH_PWROK is negated, the PCH asserts PLTRST#. Note: It is required that the powerrails associated with PCI/PCIe* (typically the 3.3 V, 5 V, and 12 V core well rails) have been valid for 99 ms prior to PCH_PWROK assertion in order to comply with the 100 ms PCI 2.3/ PCIe 1.1 specification on PLTRST# deassertion. PCH_PWROK must not glitch, even if RSMRST# is low. RI# I Ring Indicate: This signal is an input from a modem. It can be enabled as a wake event, and this is preserved across power failures. RSMRST# I Resume Well Reset: This signal is used for resetting the resume power plane logic. This signal must remain asserted for at least 10 ms after the suspend power wells are valid. When deasserted, this signal is an indication that the suspend power wells are stable. SLP_A# O SLP_A#: Used to control power to the active sleep well (ASW) of the PCH. SLP_LAN# / GPIO29 O LAN Sub-System Sleep Control: When SLP_LAN# is deasserted it indicates that the PHY device must be powered. When SLP_LAN# is asserted, power can be shut off to the PHY device. SLP_LAN# will always be deasserted in S0 and anytime SLP_A# is deasserted. A SLP_LAN#/GPIO Select Soft-Strap can be used for systems NOT using SLP_LAN# functionality to revert to GPIO29 usage. When soft-strap is 0 (default), pin function will be SLP_LAN#. When soft-strap is set to 1, the pin returns to its regular GPIO mode. The pin behavior is summarized in Section 5.14.9.4 SLP_S3# O S3 Sleep Control: SLP_S3# is for power plane control. This signal shuts off power to all non-critical systems when in S3 (Suspend To RAM), S4 (Suspend to Disk), or S5 (Soft Off) states. SLP_S4# O S4 Sleep Control: Power plane control. Shuts power to non-critical systems when in the S4 (Suspend to Disk) or S5 (Soft Off) state. This pin must be used to control the DRAM power in order to use the PCH's DRAM power-cycling feature. Note: This pin must be used to control the DRAM power in order to use the PCH's DRAM power-cycling feature. Refer to Section 5.14.9.2 for details SLP_S5# / GPIO63 O S5 Sleep Control: SLP_S5# is for power plane control. This signal is used to shut power off to all non-critical systems when in the S5 (Soft Off) states. Pin may also be used as GPIO63. SLP_SUS# O Deep S4/S5 Indication: When asserted (low), this signal indicates PCH is in Deep S4/S5 state where internal Sus power is shut off for enhanced power saving. When deasserted (high), this signal indicates exit from Deep S4/S5 state and Sus power can be applied to PCH. If Deep S4/S5 is not supported, then this pin can be left unconnected. This pin is in the DSW power well. SUSACK# I SUSACK#: If Deep S4/S5 is supported, the EC must change SUSACK# to match SUSWARN# once the EC has completed the preparations discussed in the description for the SUSWARN# pin. Note: SUSWARN# must only change in response to SUSACK# if Deep S4/S5 is supported by the platform. This pin is in the Sus power well. SUSCLK /GPIO62 O Suspend Clock: This clock is an output of the RTC generator circuit to use by other chips for refresh clock. Pin may also be used as GPIO62. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 63 Signal Description Table 2-10. Power Management Interface Signals (Sheet 3 of 3) Name SUSWARN# GPIO30 / 2.11 Type Description O SUSWARN#: This pin asserts low when the PCH is planning to enter the Deep S4/S5 power state and remove Suspend power (using SLP_SUS#). The EC must observe edges on this pin, preparing for SUS well power loss on a falling edge and preparing for SUS well related activity (host/Intel ME wakes and runtime events) on a rising edge. SUSACK# should be asserted within a minimal amount of time from SUSWARN# assertion, as no wake events are supported if SUSWARN# is asserted, but SUSACK# is not asserted. Platforms supporting Deep S4/S5, but not wishing to participate in the handshake during wake and Deep S4/S5 entry may tie SUSACK# to SUSWARN#. This pin may be muxed with a GPIO for use in systems that do not support Deep S4/S5. Reset type: RSMRST# This signal is muxed with GPIO30 System Power OK: This generic power good input to the PCH is driven and utilized in a platform-specific manner. While PCH_PWROK always indicates that the CORE well of the PCH is stable, SYS_PWROK is used to inform the PCH that power is stable to some other system component(s) and the system is ready to start the exit from reset. SYS_PWROK I SYS_RESET# I System Reset: This pin forces an internal reset after being debounced. The PCH will reset immediately if the SMBus is idle; otherwise, it will wait up to 25 ms 2 ms for the SMBus to idle before forcing a reset on the system. WAKE# I PCI Express* Wake Event: Sideband wake signal on PCI Express asserted by components requesting wake up. ADR_COMPLETE O This pin is not used for server designs. Processor Interface Table 2-11. Processor Interface Signals Name RCIN# Type I Description Keyboard Controller Reset CPU: The keyboard controller can generate INIT# to the processor. This saves the external OR gate with the PCH's other sources of INIT#. When the PCH detects the assertion of this signal, INIT# is generated for 16 PCI clocks. Note: 64 The PCH will ignore RCIN# assertion during transitions to the S3, S4, and S5 states. A20GATE I A20 Gate: Functionality reserved. A20M# functionality is not supported. PROCPWRGD O Processor Power Good: This signal should be connected to the processor's PWRGOOD input to indicate when the processor power is valid. PM_SYNC O Power Management Sync: Provides state information from the PCH to the Processor relevant to C-state transitions. PM_SYNC2 O Power Management Sync 2: Provides state information from the PCH to the Processor relevant to C-state transitions. Used only in a 4-socket system. THRMTRIP# I Thermal Trip: When low, this signal indicates that a thermal trip from the processor occurred, and the PCH will immediately transition to a S5 state. The PCH will not wait for the processor stop grant cycle since the processor has overheated. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Signal Description 2.12 SMBus Interface Table 2-12. SM Bus Interface Signals Name Type SMBDATA I/OD SMBCLK I/OD SMBALERT# / GPIO11 2.13 I Description SMBus Data: External pull-up resistor is required. SMBus Clock: External pull-up resistor is required. SMBus Alert: This signal is used to wake the system or generate SMI#. This signal may be used as GPIO11. System Management Interface Table 2-13. System Management Interface Signals Name Type Description INTRUDER# I SML0DATA I/OD System Management Link 0 Data: SMBus link to external PHY. External pullup is required. SML0CLK I/OD System Management Link 0 Clock: SMBus link to external PHY. External pull-up is required. SML0ALERT# / GPIO60 / O OD SMLink Alert 0: Output of the integrated LAN controller to external PHY. External pull-up resistor is required. This signal can instead be used as a GPIO60. Intruder Detect: This signal can be set to disable system if box detected open. This signal's status is readable; thus, it can be used like a GPI if the Intruder Detection is not needed. PCHHOT#: This signal is used to indicate a PCH temperature out of bounds condition to an external EC, when PCH temperature is greater than value programmed by BIOS. An external pull-up resistor is required on this signal. SML1ALERT# / PCHHOT#/GPIO74 O OD SML1CLK / GPIO58 I/OD System Management Link 1 Clock: SMBus link to optional Embedded Controller or BMC. External pull-up resistor is required. SML1DATA / GPIO75 I/OD System Management Link 1 Data: SMBus link to optional Embedded Controller or BMC. External pull-up resistor is required. Note: A soft-strap determines the native function SML1ALERT# or PCHHOT# usage. When soft-strap is 0, function is SML1ALERT#, when soft-strap is 1, function is PCHHOT#. 2.14 SAS System Management Interface (SRV/WS SKUs Only) Note: These signals are not used on the HEDT SKU. Theses signals should be no connects on HEDT platform designs. Table 2-14. SAS System Management Interface Signals (Sheet 1 of 2) Name Type SASSMBDATA0 I/O SAS dedicated SMBus Master data SASSMBCLK0 O SAS dedicated SMBus Master Clock SASSMBDATA1 (Intel(R) C606, C608 Chipset SKUs Only) I/O SAS dedicated SMBus Master data Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Description 65 Signal Description Table 2-14. SAS System Management Interface Signals (Sheet 2 of 2) 2.15 Name Type Description SASSMBCL0K1 (Intel(R) C606, C608 Chipset SKUs Only) O SAS dedicated SMBus Master Clock SASSMBDATA2 (Intel(R) C608 Chipset SKUs Only) I/O SAS dedicated SMBus Master data SASSMBCLK2 (Intel(R) C608 Chipset SKUs Only) O SAS dedicated SMBus Master Clock Real Time Clock Interface Table 2-15. Real Time Clock Interface 2.16 Name Type Description RTCX1 Special Crystal Input 1: This signal is connected to the 32.768 kHz crystal. If no external crystal is used, then RTCX1 can be driven with the desired clock rate. RTCX2 Special Crystal Input 2: This signal is connected to the 32.768 kHz crystal. If no external crystal is used, then RTCX2 should be left floating. Miscellaneous Signals Table 2-16. Miscellaneous Signals (Sheet 1 of 2) Name Type Description INTVRMEN I Internal Voltage Regulator Enable: This signal enables the internal 1.5 V regulators. This signal must be always pulled-up to VccRTC. Note: See VccCore signal description for behavior when INTVRMEN is sampled low (external VR mode). DSWODVREN I Deep Sleep Well Internal Voltage Regulator Enable: This signal enables the internal Deep Sleep 1.1 V regulators. This signal must be always pulled up to VccRTC. SPKR O Speaker: The SPKR signal is the output of counter 2 and is internally "ANDed" with Port 61h bit 1 to provide Speaker Data Enable. This signal drives an external speaker driver device, which in turn drives the system speaker. Upon PLTRST#, its output state is 0. Note: SPKR is sampled as a functional strap. See Section 2.26.1 for more details. There is a weak integrated pull-down resistor on SPKR pin. RTC Reset: When asserted, this signal resets register bits in the RTC well. RTCRST# I Notes: 1. Unless CMOS is being cleared (only to be done in the G3 power state), the RTCRST# input must always be high when all other RTC power planes are on. 2. In the case where the RTC battery is dead or missing on the platform, the RTCRST# pin must rise before the DPWROK pin. Secondary RTC Reset: This signal resets the manageability register bits in the RTC well when the RTC battery is removed. SRTCRST# 66 I Notes: 1. The SRTCRST# input must always be high when all other RTC power planes are on. 2. In the case where the RTC battery is dead or missing on the platform, the SRTCRST# pin must rise before the DPWROK pin. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Signal Description Table 2-16. Miscellaneous Signals (Sheet 2 of 2) Name 2.17 Type Description PCHHOT#: This signal is used to indicate a PCH temperature out of bounds condition to an external EC, when PCH temperature is greater than value programmed by BIOS. An external pull-up resistor is required on this signal. SML1ALERT#/ PCHHOT#/ GPIO74 OD INIT3_3V# O Initialization 3.3 V: INIT3_3V# is asserted by the PCH for 16 PCI clocks to reset the processor. This signal is intended for Firmware Hub. NMI#/ GPIO35 O Non-Maskable Interrupt: NMI# is used to force a non-Maskable interrupt to the processor. Note: The NMI # function is enabled using softstrap SMI# / GPIO20 O System Management Interrupt: SMI# is an active low output synchronous to PCICLK. It is asserted by the PCH in response to one of many enabled hardware or software events. Note: The SMI# function is enabled using softstrap Note: A soft-strap determines the native function SML1ALERT# or PCHHOT# usage. When soft-strap is 0, function is SML1ALERT#, when soft-strap is 1, function is PCHHOT#. Intel(R) High Definition Audio (Intel(R) HD Audio) Link Table 2-17. Intel(R) High Definition Audio (Intel(R) HD Audio) Link Signals Name Type HDA_RST# O Description Intel HD Audio Reset: Master hardware reset to external codec(s). Intel HD Audio Sync: 48 kHz fixed rate sample sync to the codec(s). Also used to encode the stream number. HDA_SYNC O HDA_BCLK O HDA_SDO HDA_SDIN[3:0] O I Note: This signal is sampled as a functional strap. See Section 2.26.1 for more details. There is a weak integrated pull-down resistor on this pin. Intel HD Audio Bit Clock Output: 24.000 MHz serial data clock generated by the Intel High Definition Audio controller (the PCH). This signal has a weak internal pull-down resistor. Intel HD Audio Serial Data Out: Serial TDM data output to the codec(s). This serial output is double-pumped for a bit rate of 48 Mb/s for Intel High Definition Audio. Note: This signal is sampled as a functional strap. See Section 2.26.1 for more details. There is a weak integrated pull-down resistor on this pin. Intel HD Audio Serial Data In [3:0]: Serial TDM data inputs from the codecs. The serial input is single-pumped for a bit rate of 24 Mb/s for Intel High Definition Audio. These signals have integrated pull-down resistors, which are always enabled. Note: Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet During enumeration, the PCH will drive this signal. During normal operation, the CODEC will drive it. 67 Signal Description 2.18 Serial Peripheral Interface (SPI) Table 2-18. Serial Peripheral Interface (SPI) Signals 2.19 Name Type Description SPI_CS0# O SPI Chip Select 0: Used as the SPI bus request signal. SPI_CS1# O SPI Chip Select 1: Used as the SPI bus request signal. SPI_MISO I SPI Master IN Slave OUT: Data input pin for PCH. SPI_MOSI I/O SPI_CLK O SPI Master OUT Slave IN: Data output pin for PCH. SPI Clock: SPI clock signal, during idle the bus owner will drive the clock signal low. 17.86 MHz and 31.25. Thermal Signals Table 2-19. Thermal Signals Signal Name 2.20 Type Description PWM[3:0] OD O Fan Pulse Width Modulation Outputs: Pulse Width Modulated duty cycle output signal that is used for Intel(R) Quiet System Technology (Intel(R) QST). When controlling a 3-wire fan, this signal controls a power transistor that, in turn, controls power to the fan. When controlling a 4-wire fan, this signal is connected to the "Control" signal on the fan. The polarity of this signal is programmable. The output default is low. These signals are 5 V tolerant. TACH0 / GPIO17 TACH1 / GPIO1 TACH2 / GPIO6 TACH3 / GPIO7 TACH4 / GPIO68 TACH5 / GPIO69 TACH6 / GPIO70 TACH7 / GPIO71 I Fan Tachometer Inputs: Tachometer pulse input signal that is used to measure fan speed. This signal is connected to the "Sense" signal on the fan. Can instead be used as a GPIO. SST I/O Simple Serial Transport: Single-wire, serial bus. Connect to SST compliant devices such as SST thermal sensors or voltage sensors. PECI I/O Platform Environment Control Interface: Single-wire, serial bus. Connect to corresponding pin of the processor for accessing processor digital thermometer. JTAG Signals Table 2-20. JTAG Signals Name Type JTAG_TCK I Test Clock Input (TCK): The test clock input provides the clock for the JTAG test logic. JTAG_TMS I Test Mode Select (TMS): The signal is decoded by the Test Access Port (TAP) controller to control test operations. JTAG_TDI I Test Data Input (TDI): Serial test instructions and data are received by the test logic at TDI. JTAG_TDO OD Test Data Output (TDO): TDO is the serial output for test instructions and data from the test logic defined in this standard. Note: 68 Description JTAG Pin definitions are from IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE Std. 1149.1-2001) Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Signal Description 2.21 Clock Signals Table 2-21. Clock Interface Signals Name Type Description CLKIN_DMI_P, CLKIN_DMI_N I 100 MHz differential reference clock from CK420BQ (or CK505 on HEDT platforms) and used by DMI. CLKIN_SATA_P, CLKIN_SATA_N I 100 MHz differential reference clock from CK420BQ (or CK505 on HEDT platforms), provided separately from CLKIN_DMI, for use only as a 100 MHz source for SATA. CLKIN_DOT96P, CLKIN_DOT96N I 96 MHz differential reference clock from CK420BQ (or CK505 on HEDT platforms). REFCLK14IN I Single-ended 14.31818 MHz reference clock driven by CK420BQ (or CK505 on HEDT platforms). Used for 8254 Timer, ACPI Timer and HPET. CLKIN_SAS0_P, CLKIN_SAS0_N I 100 MHz differential reference clock from CK420BQ. Used for SAS differential clock. Note: For HEDT SKU, these signals must be tied to the 100 MHz reference clock CLKIN_SAS1_P, CLKIN_SAS1_N (Intel(R) C606, C608 Chipset SKUs Only) I 100 MHz differential reference clock from CK420BQ. Used for SAS differential clock. CLKIN_SPCIE0_P, CLKIN_SPCIE0_N (Intel(R) C606, C608 Chipset SKUs Only) I Upstream PCIe* Switch Port differential reference clock. CLKIN_PCI I PCI Clock: This is a 33 MHz clock feedback input to reduce skew between PCH PCI clock and clock observed by connected PCI devices. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 69 Signal Description 2.22 General Purpose I/O Signals 1. GPIO Configuration registers within the Core Well are reset whenever PCH_PWROK is deasserted. 2. GPIO Configuration registers within the Suspend Well are reset when RSMRST# is asserted, CF9h reset (06h or 0Eh) event occurs, or SYS_RESET# is asserted. However, CF9h reset and SYS_RESET# events can be masked from resetting the Suspend well GPIO by programming appropriate GPIO Reset Select (GPIO_RST_SEL) registers. 3. GPIO24 is an exception to the other GPIO Signals in the Suspend Well and is not reset by CF9h reset (06h or 0Eh). Table 2-22. General Purpose I/O Signals (Sheet 1 of 3) Default Glitch Protection during Power-On Sequence GPI Event Support Name Type GPIO75 I/O 3.3 V Suspend Native No No No Multiplexed with SML1DATA (Note 10) GPIO74 I/O 3.3 V Suspend Native No No No Multiplexed with SML1ALERT#/ PCHHOT# (Note 10) GPIO73 I/O 3.3 V Suspend GPI No No No Unmultiplexed Description GPIO72 I/O 3.3 V Suspend Native No No No Unmultiplexed (note 4) This signal must not be low prior to ASW well being valid; Requires pull-up resistor. GPIO71 I/O 3.3 V Core Native No No No Multiplexed with Tach7 GPIO70 I/O 3.3 V Core Native No No No Multiplexed with Tach6 GPIO69 I/O 3.3 V Core GPI No No No Multiplexed with Tach5 GPIO68 I/O 3.3 V Core GPI No No No Multiplexed with Tach4 GPIO67 I/O 3.3 V Core GPO No No No Unmultiplexed GPIO66 I/O 3.3 V Core GPO No No No Unmultiplexed GPIO65 I/O 3.3 V Core GPO No No No Unmultiplexed GPIO64 I/O 3.3 V Core GPO No No No Unmultiplexed GPIO63 I/O 3.3 V Suspend Native No Yes No Multiplexed with SLP_S5# GPIO62 I/O 3.3 V Suspend Native No No No Multiplexed with SUSCLK GPIO61 I/O 3.3 V Suspend GPO No Yes No Unmultiplexed (note 4) GPIO60 I/O 3.3 V Suspend Native No No No Multiplexed with SML0ALERT# No No Multiplexed with OC0# (Note 10) GPIO59 70 Power Well Blink Capability Tolerance I/O 3.3 V Suspend Native No GPIO58 I/O 3.3 V Suspend Native No No No Multiplexed with SML1CLK GPIO57 I/O 3.3 V Suspend GPI No Yes No Unmultiplexed GPIO56 I/O 3.3 V Suspend GPI No No No Unmultiplexed GPIO55 I/O 3.3 V Core Native No No No Multiplexed with GNT3# GPIO54 I/O 5.0 V Core Native No No No Multiplexed with REQ3#/ GSXRESET#.(Note 10) GPIO53 I/O 3.3 V Core Native No No No Multiplexed with GNT2#/GSXDIN GPIO52 I/O 5.0 V Core Native No No No Multiplexed with REQ2#/GSXSLOAD. (Note 10) GPIO51 I/O 3.3 V Core Native No No No Multiplexed with GNT1#/GSXDOUT GPIO50 I/O 5.0 V Core Native No No No Multiplexed with REQ1#/GSXCLK. (Note 10) Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Signal Description Table 2-22. General Purpose I/O Signals (Sheet 2 of 3) Power Well Core Default Blink Capability Glitch Protection during Power-On Sequence GPI Event Support GPI No No No Multiplexed with SATA5GP and TEMP_ALERT# Name Type Tolerance GPIO49 I/O 3.3 V GPIO48 I/O 3.3 V Core GPI No No No Multiplexed with SDATAOUT1. GPIO47 I/O 3.3 V Suspend GPI No No No Unmultiplexed GPIO46 I/O 3.3 V Suspend GPI No No No Unmultiplexed GPIO45 I/O 3.3 V Suspend GPI No No No Unmultiplexed Description GPIO44 I/O 3.3 V Suspend GPI No No No Unmultiplexed GPIO[43:40] I/O 3.3 V Suspend Native No No No Multiplexed with OC[4:1]#. (Note 10) GPIO39 I/O 3.3 V Core GPI No No No Multiplexed with SDATAOUT0. GPIO38 I/O 3.3 V Core GPI No No No Multiplexed with SLOAD. GPIO37 I/O 3.3 V Core GPI No No No Multiplexed with SATA3GP. GPIO36 I/O 3.3 V Core GPI No No No Multiplexed with SATA2GP. GPIO35 I/O 3.3 V Core GPO No No No Multiplexed with NMI#. GPIO34 I/O 3.3 V Core GPI No No No Unmultiplexed (Note 4) GPIO33 I/O 3.3 V Core GPO No No No Unmultiplexed (Note 4) GPIO32 I/O 3.3 V Core GPO No No No Unmultiplexed (Note 4) GPIO31 I/O 3.3 V DSW GPI Yes Yes No Unmultiplexed (Note 4) No Multiplexed with SUSWARN#. Can be used as SUSWARN# and GPIO30 only. GPIO30 I/O 3.3 V Suspend Native Yes Yes GPIO29 I/O 3.3 V Suspend Native Yes Yes No Multiplexed with SLP_LAN# Pin usage as GPIO is determined by SLP_LAN#/GPIO Select Softstrap.(Note 9) Soft-strap value is not preserved for this signal in the Sx/Moff state and the pin will return to its native functionality (SLP_LAN#) GPIO28 I/O 3.3 V Suspend GPO Yes No No Unmultiplexed GPIO27 I/O 3.3 V DSW11 GPI Yes No No Unmultiplexed Can be configured as wake input to allow wakes from Deep S4/S5. This GPIO has no GPIO functionality in the Deep S4/S5 states other than wake from Deep S4/S5 if this option has been configured. GPIO26 I/O 3.3 V Suspend GPO Yes No No Unmultiplexed GPIO25 I/O 3.3 V Suspend GPO Yes No No Unmultiplexed GPIO24 I/O 3.3 V Suspend GPO Yes Yes No Unmultiplexed Note: GPIO24 configuration register bits are cleared by RSMRST# and are not cleared by CF9h reset event. GPIO23 I/O 3.3 V Core Native Yes No No Multiplexed with LDRQ1#. GPIO22 I/O 3.3 V Core GPI Yes No No Multiplexed with SCLOCK GPIO21 I/O 3.3 V Core GPI Yes No No Multiplexed with SATA0GP GPIO20 I/O 3.3 V Core GPO Yes No No Multiplexed with SMI# GPIO19 I/O 3.3 V Core GPI Yes No No Multiplexed with SATA1GP Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 71 Signal Description Table 2-22. General Purpose I/O Signals (Sheet 3 of 3) Power Well Default Blink Capability Glitch Protection during Power-On Sequence GPI Event Support Name Type Tolerance GPIO18 I/O 3.3 V Core GPO Yes (Note 6) No No Unmultiplexed GPIO17 I/O 3.3 V Core GPI Yes No No Multiplexed with TACH0. GPIO16 I/O 3.3 V Core GPI Yes No No GPIO15 I/O 3.3 V Suspend GPO Yes No Yes2 Unmultiplexed GPIO14 I/O 3.3 V Suspend Native Yes No Yes2 Multiplexed with OC7# GPIO13 I/O 3.3 V or 1.5 V Suspend GPI Yes No Yes2 Unmultiplexed (Note 4, 13) Note: GPIO13 is powered by VccSusHDA (either 3.3 V or 1.5 V). Voltage tolerance on the signal is the same as VccSusHDA. GPIO12 I/O 3.3 V Suspend Native Yes No Yes2 Multiplexed with LAN_PHY_PWR_CTRL. GPIO / Native functionality controlled using soft strap (Note 7, 12) GPIO11 I/O 3.3 V Suspend Native Yes No Yes2 Multiplexed with SMBALERT#. (Note 10) GPIO10 I/O 3.3 V Suspend Native Yes No Yes2 Multiplexed with OC6# (Note 10) Multiplexed with OC5# (Note 10) Description Multiplexed with SATA4GP. GPIO9 I/O 3.3 V Suspend Native Yes No Yes2 GPIO8 I/O 3.3 V Suspend GPO Yes No Yes2 Unmultiplexed GPIO[7:6] I/O 3.3 V Core GPI Yes No Yes2 Multiplexed with TACH[3:2]. GPIO[5:2] I/OD 5V Core GPI Yes No Yes2 Multiplexed with PIRQ[H:E]# (Note 5). GPIO1 I/O 3.3 V Core GPI Yes No Yes2 Multiplexed with TACH1. GPIO0 I/O 3.3 V Core GPI Yes No Yes2 Multiplexed with BMBUSY# Notes: 1. All GPIOs can be configured as either input or output. 2. GPI[15:0] can be configured to cause a SMI# or SCI. A GPI can be routed to either an SMI# or an SCI, but not both. 3. Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO signals are not driven high into powered-down planes. Also, external devices should not be driving powered down GPIOs high. Some GPIOs may be connected to pins on devices that exist in the core well. If these GPIOs are outputs, there is a danger that a loss of core power (PCH_PWROK low) or a Power Button Override event will result in the PCH driving a pin to a logic 1 to another device that is powered down. 4. The functionality that is multiplexed with the GPIO is not used in the PCH. 5. When this signal is configured as GPO the output stage is an open drain. 6. GPIO18 will toggle at a frequency of approximately 1 Hz when the signal is programmed as a GPIO (when configured as an output) by BIOS. 7. For GPIOs where GPIO vs. Native Mode is configured using SPI Soft Strap, the corresponding GPIO_USE_SEL bits for these GPIOs have no effect. The GPIO_USE_SEL bits for these GPIOs may change to reflect the Soft-Strap configuration even though GPIO Lockdown Enable (GLE) bit is set. 8. These pins are used as Functional straps. See Section 2.26.1 for more details. 9. Once Soft-strap is set to GPIO mode, this pin will default to GP Input. When Soft-strap is SLP_LAN# usage and if Host BIOS does not configure as GP Output for SLP_LAN# control, SLP_LAN# behavior will be based on the setting of the RTC backed SLP_LAN# Default Bit(D31:F0:A4h:Bit 8). 10. When the multiplexed GPIO is used as GPIO functionality, care should be taken to ensure the signal is stable in its inactive state of the native functionality, immediately after reset until it is initialized to GPIO functionality. 11. GPIO functionality is only available when the Suspend well is powered although pin is in DSW. 12. GPIO will assume its native functionality until the soft strap is loaded after which time the functionality will be determined by the soft strap setting. 13. GPIO13 is powered by VccSusHDA (either 3.3 V or 1.5 V). Voltage tolerance on the signal is the same as VccSusHDA. 72 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Signal Description 2.23 GPIO Serial Expander Signals Table 2-23. GPIO Serial Expander Interface Name Type GSXCLK O GPIO Serial Expansion clock input. GSXCLK may optionally be used as REQ1# or GPIO50 GSXSLOAD O GPIO Serial Expansion data load select. GSXSLOAD may optionally be used as REQ2# or GPIO52 GSXSRESET# O GPIO Serial Expansion reset. GSXSRESET# may optionally be used as REQ3# or GPIO54 GSXDOUT O GPIO Serial Expansion serial data out. GSXDOUT may optionally be used as GNT1# or GPIO51 GSXDIN I GPIO Serial Expansion serial data in. GSXDIN may optionally be used as GNT2# or GPIO53 Note: 2.24 Description GSX (GPIO Serial Expander) signal functions are enabled using softstrap. Manageability Signals The following signals can be optionally utilized by PCH Intel ME supported applications and appropriately configured by Intel ME firmware. When configured and utilized as a Manageability function, the associated host GPIO functionality is no longer available. If the Manageability function is not utilized in a platform, the signal can be used as a host General Purpose I/O or a native function. Table 2-24. Manageability Signals (Sheet 1 of 2) Name Type Description MGPIO0/ PROC_MISSING/ GPIO24 I/O MGPIO0 can be used to connect to upgrade ROM. It is also used to indicate Processor Missing to the Intel(R) Management Engine (Intel(R) ME). Note: This signal is in the Suspend power well. MGPIO1/GPIO30 I/O MGPIO1 can be used as an alternative for MGPIO2 or MGPIO5 when neither pins are available for Intel ME. Note: This signal is in the Suspend power well. MGPIO2 / GPIO31 I/O MGPIO2 can be used as a SMBALERT# signal from PSU to PCH Note: This signal is in the Suspend power well. MGPIO3 / SLP_LAN# / GPIO29 I/O Intel ME General Purpose I/O 3. Note: This signal is in the Suspend power well. MGPIO4 / SML0ALERT# / GPIO60 I/O MGPIO4 can be used as an alternative for MGPIO2 or MGPIO5 when neither pins are available for Intel ME. Note: This signal is in the Suspend power well. MGPIO5 / GPIO57 I/O MGPIO5 can be used as Intel ME firmware recovery mode strap. MGPIO5 can be used as an alternative for MGPIO2 when it is not available for Intel ME. Note: This signal is in the Suspend power well. MGPIO6 / GPIO27 I/O MGPIO6 can be used as an alternative for MGPIO2 or MGPIO5 when neither pins are available for Intel ME. Note: This signal is in the Deep S4/S5(DSW) power well. MGPIO7 / GPIO28 I/O MGPIO7 can be used as an alternative for MGPIO2 or MGPIO5 when neither pins are available for Intel ME. Note: This signal is in the Suspend power well. MGPIO8 / SML1ALERT# / GPIO74 I/O MGPIO8 can be used as an alternative for MGPIO2 or MGPIO5 when neither pins are available for Intel ME. Note: This signal is in the Suspend power well. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 73 Signal Description Table 2-24. Manageability Signals (Sheet 2 of 2) Name Type MGPIO9 / SATA4GP / GPIO16 I/O Intel ME General Purpose I/O 9. Note: This signal is in the Core power well. MGPIO10/ TEMP_ALERT/ SATA5GP / GPIO49 I/O Used as an alert (active low) to indicate to the external controller (for example, EC or SIO) that temperatures are out of range for the PCH or Graphics/Memory Controller or the processor core. Note: This signal is in the Core power well. MGPIO11 / SML1CLK / GPIO58 I/O ME General Purpose I/O 11. Note: This signal is in the Suspend power well. MGPIO12 / SML1DATA / GPIO75 I/O ME General Purpose I/O 12. Note: This signal is in the Suspend power well. Note: 2.25 Description SLP_LAN#/GPIO29 may also be configured by Intel ME FW in Sx/Moff. Please refer to SLP_LAN#/ GPIO29 signal description for details. Power and Ground Signals Table 2-25. Power and Ground Signals (Sheet 1 of 2) Name DcpRTC Decoupling: This signal is for RTC decoupling only. This signal requires decoupling. DcpSST Decoupling: Internally generated 1.5 V powered off of Suspend Well. This signal requires decoupling. Decoupling is required even if this feature is not used. DcpSus 1.1 V Suspend well supply that is supplied internally by Internal VRs. DcpSusByp Internally generated 1.1 V Deep S4/S5 well power. This rail should not be supplied externally. Note: No decoupling capacitors should be used on this rail. V5REF Reference for 5 V tolerance on core well inputs. This power may be shut off in S3, S4, S5 or G3 states. V5REF_Sus Reference for 5 V tolerance on suspend well inputs. This power is not expected to be shut off unless the system is unplugged. VccCore 1.1 V supply for core well logic. This power may be shut off in S3, S4, S5 or G3 states. Note: In external VR mode (INTVRMEN sampled low), the voltage level of VccCore may be indeterminate while DcpSus (1.1 V Suspend Well Power) supply ramps and prior to PWROK assertion. VccIO 1.1 V supply for core well I/O buffers. This power may be shut off in S3, S4, S5 or G3 states. Vcc3_3 3.3 V supply for core well I/O buffers. This power may be shut off in S3, S4, S5 or G3 states. VccASW 1.1 V supply for Active Sleep Well. This plane must be on in S0 and other times the Intel ME is used or integrated LAN is used. VccDMI Power supply for DMI. 1.0 to 1.1 V based on the processor VTT voltage. Please refer to the respective processor documentation to find the appropriate voltage level. VccRTC 3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well. This power is not expected to be shut off unless the RTC battery is removed or completely drained. Note: Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Clearing CMOS in a PCH based platform can be done by using a jumper on RTCRST# or GPI. VccSus3_3 74 Description 3.3 V supply for suspend well I/O buffers. This power may be shut off in the Deep S4/S5 or G3 states. VccAUBG 3.3 V supply for suspend well USB reference. Note: This pin may require external filtering. VccAUPLL 1.1 V supply for core well USB PLL. Note: This pin may require external filtering. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Signal Description Table 2-25. Power and Ground Signals (Sheet 2 of 2) Name VccSusHDA VccVRM VccDFTERM Description Suspend supply for Intel HD Audio. This pin can be either 1.5 or 3.3 V. 1.5 V / 1.8 V supply for internal PLL and VRMs 1.8 V or 3.3 V supply for DF_TVS. Can be pulled up to 1.8 V or 3.3 V core. VccAPLLSATA 1.1 V Analog power supply for SATA. This signal is used for the analog power for SATA. This requires an LC filter and is supplied by the core well. Must be powered even if SATA is not used. Note: This pin can be left as no connect in On-Die VR enabled mode (default). VccAPLLEXP 1.1 V Analog Power for DMI. This power is supplied by the core well. This requires an LC filter. Note: This pin can be left as no connect in On-Die VR enabled mode (default). VccAPLLDMI2 1.1 V Analog Power for internal PLL. This power is supplied by the core well. This requires an LC filter. Note: This pin can be left as no connect in On-Die VR enabled mode (default). V_PROC_IO Powered by the same supply as the processor I/O voltage. This supply is used to drive the processor interface signals. Please refer to the respective processor documentation to find the appropriate voltage level. VccDSW3_3 3.3 V supply for Deep Sleep wells. If platform does not support Deep S4/S5, then tie to VccSus3_3. VccSPI 3.3 V supply for SPI controller logic. This must be powered when VccASW is powered. Note: This rail can be optionally powered on 3.3-V Suspend power (VccSus3_3) based on platform needs. VccXUS 1.1 V supply for PCI Express Uplink switch wells. Can be tied to Vss for Intel(R) C602, C604 Chipset SKUs. Note: This signal is not used on HEDT SKU and can be tied to VSS or VCC, but must be tied to the same power plane as VccSCUS. VccSCUS 1.1 V supply for SAS switch wells. Can be tied to Vss for Intel(R) C602, C602J, C604 Chipset SKUs. Note: This signal is not used on HEDT SKU and can be tied to VSS or VCC, but must be tied to the same power plane as VccXUS. VccPLLSAS0 1.1 V supply for x4 SAS port. This requires an LC filter and is supplied by the core well. Note: This signal must be connected on all SKUs. VccPLLSAS1 1.1 V supply for x4 SAS port. This requires an LC filter and is supplied by the core well. Note: This signal is not used on Intel(R) C602, C602J, C604 Chipset and Intel(R) X79 Express Chipset SKUs. VccPLLEXPU (Intel(R) C606, C608 Chipset SKUs Only) 1.1 V supply for PCI Express Uplink. This requires an LC filter and is supplied by the core well. Note: Must be tied to Vss if VccXUS is tied to Vss on Intel(R) C602, C602J, C604 Chipset and Intel(R) X79 Express Chipset SKUs. VccRBIAS_SAS0 1.1 V supply for x4 SAS port RBIAS. This is supplied by the core well. Note: This signal must be connected on all SKUs. VccRBIAS_SAS1 1.1 V supply for x4 SAS port RBIAS. This is supplied by the core well. Note: This signal is not used on Intel(R) C602, C602J, C604 Chipset and Intel(R) X79 Express Chipset SKUs. VccRBIAS_PU (Intel(R) C606, C608 Chipset SKUs Only) VccSAS1_5 Vss 1.1 V supply for PCI Express Uplink RBIAS. This is supplied by the core well. Note: Must be tied to Vss if VccXUS is tied to Vss on Intel(R) C602, C602J, C604 Chipset and Intel(R) X79 Express Chipset SKUs. 1.5 V supply for x4 SAS port. This is supplied by the core well. Note: This signal must be connected on all SKUs. Grounds. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 75 Signal Description 2.26 Pin Straps 2.26.1 Functional Straps The following signals are used for static configuration. They are sampled at the rising edge of PCH_PWROK to select configurations (except as noted), and then revert later to their normal usage. To invoke the associated mode, the signal should be driven at least four PCI clocks prior to the time it is sampled. PCH has implemented Soft Straps. Soft Straps are used to configure specific functions within the PCH and processor very early in the boot process before BIOS or SW intervention. When Descriptor Mode is enabled, the PCH will read Soft Strap data out of the SPI device prior to the de-assertion of reset to both the Intel ME and the Host system. Table 2-26. Functional Strap Definitions (Sheet 1 of 3) Signal 76 Usage When Sampled Comment SPKR No Reboot Rising edge of PCH_PWROK The signal has a weak internal pull-down. Note: The internal pull-down is disabled after PLTRST# de-asserts. If the signal is sampled high, this indicates that the system is strapped to the "No Reboot" mode (PCH will disable the TCO Timer system reboot feature). The status of this strap is readable using the NO REBOOT bit (Chipset Config Registers: Offset 3410h:bit 5). INIT3_3V# Reserved Rising edge of PCH_PWROK This signal has a weak internal pull-up. Note: The internal pull-up is disabled after PLTRST# de-asserts. Note: This signal should not be pulled low GNT3#/GPIO55 Top-Block Swap Override Rising edge of PCH_PWROK The signal has a weak internal pull-up. If the signal is sampled low, this indicates that the system is strapped to the "Top-Block Swap" mode. The status of this strap is readable using the Top Swap bit (Chipset Config Registers:Offset 3414h:bit 0). Notes: 1. The internal pull-up is disabled after PLTRST# deasserts. 2. Software will not be able to clear the Top Swap bit until the system is rebooted without GNT3#/GPIO55 being pulled down. INTVRMEN Integrated 1.1 V VRM Enable / Disable Always Integrated 1.1 V VRMs is enabled when high Note: This signal should always be pulled high. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Signal Description Table 2-26. Functional Strap Definitions (Sheet 2 of 3) Signal Usage When Sampled Comment This Signal has a weak internal pull-up. Note: The internal pull-up is disabled after PCIRST# de-asserts. This field determines the destination of accesses to the BIOS memory range. Also controllable using Boot BIOS Destination bit (Chipset Config Registers:Offset 3410h:bit 11). This strap is used in conjunction with Boot BIOS Destination Selection 0 strap. GNT1#/GPIO51 Boot BIOS Strap bit [1] BBS[1] Bit11 Bit 10 Boot BIOS Destination 0 1 Reserved 1 0 PCI 1 1 SPI Rising edge of PCH_PWROK 0 Note: Note: 0 LPC If option 00 LPC is selected BIOS may still be placed on LPC, but all platforms with PCH require SPI flash connected directly to the PCH's SPI bus with a valid descriptor in order to boot. Booting to PCI is intended for debut/ testing only. Boot BIOS Destination Select to LPC/PCI by functional strap or using Boot BIOS Destination Bit will not affect SPI accesses initiated by Intel ME or Integrated GbE LAN. This Signal has a weak internal pull-up. Note: The internal pull-up is disabled after PCIRST# de-asserts. This field determines the destination of accesses to the BIOS memory range. Also controllable using Boot BIOS Destination bit (Chipset Config Registers:Offset 3410h:bit 10). This strap is used in conjunction with Boot BIOS Destination Selection 1 strap. SATA1GP/ GPIO19 Boot BIOS Strap bit[0] BBS[0] Rising edge of PCH_PWROK Bit11 Bit 10 Boot BIOS Destination 0 1 Reserved 1 0 PCI 1 1 SPI 0 0 LPC Note: Note: GNT2#/ GPIO53 DMI AC Coupling Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Rising edge of PCH_PWROK If option 00 LPC is selected BIOS may still be placed on LPC, but all platforms with PCH require SPI flash connected directly to the PCH's SPI bus with a valid descriptor in order to boot. Booting to PCI is intended for debut/ testing only. Boot BIOS Destination Select to LPC/PCI by functional strap or using Boot BIOS Destination Bit will not affect SPI accesses initiated by Intel ME or Integrated GbE LAN. This Signal has a weak internal pull-up. Note: The internal pull-up is disabled after PLTRST# de-asserts. Tying this strap low enables DMI full voltage AC coupling. 77 Signal Description Table 2-26. Functional Strap Definitions (Sheet 3 of 3) Signal When Sampled Comment HDA_SDO Flash Descriptor Security Override/ Intel ME Debug Mode Rising edge of PCH_PWROK Signal has a weak internal pull-down. If strap is sampled low, the security measures defined in the Flash Descriptor will be in effect (default). If sampled high, the Flash Descriptor Security will be overridden. This strap should only be asserted high using external pull-up in manufacturing/debug environments ONLY. Note: The weak internal pull-down is disabled after PLTRST# de-asserts. Note: Asserting the HDA_SDO high on the rising edge of PCH_PWROK will also halt Intel ME after chipset bring up and disable runtime Intel ME features. This is a debug mode and must not be asserted after manufacturing/debug. DF_TVS DMI Tx /Rx Termination Voltage Rising edge of PCH_PWROK This signal has a weak internal pull-down. Note: The internal pull-down is disabled after PLTRST# de-asserts. GPIO28 On-Die PLL Voltage Regulator Rising edge of RSMRST# pin This signal has a weak internal pull-up. The On-Die PLL voltage regulator is enabled when sampled high. When sampled low the On-Die PLL Voltage Regulator is disabled. Note: The internal pull-up is disabled after RSMRST# deasserts. HDA_SYNC On-Die PLL Voltage Regulator Voltage Select Rising edge of RSMRST# pin This signal has a weak internal pull-down. On Die PLL VR is supplied by 1.5 V from VccVRM when sampled high, 1.8 V from VccVRM when sampled low. GPIO15 TLS Confidentiality Rising edge of RSMRST# pin Low = Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High = Intel ME Crypto TLS cipher suite with confidentiality This signal has a weak internal pull down. Notes: 1. A strong pull up may be needed for GPIO functionality. 2. This signal must be pulled up to support Intel RPAT and Intel AMT with TLS. Intel ME configuration parameters also need to be set correctly to enable TLS. DSWODVREN Deep S4/S5 Well On-Die Voltage Regulator Enable Always If strap is sampled high, the integrated Deep S4/ S5 Well (DSW) On-Die VR mode is enabled. Reserved Rising edge of PWROK SATA2GP/GPIO36 78 Usage This signal has a weak internal pull-down. Note: The internal pull-down is disabled after PLTRST# de-asserts. Note: This signal should not be pulled high when strap is sampled. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Signal Description 2.27 External RTC Circuitry The PCH implements an internal oscillator circuit that is sensitive to step voltage changes in VccRTC. Figure 2-2 shows an example schematic recommended to ensure correct operation of the PCH RTC. Figure 2-2. Example External RTC Circuit VccDSW3_3 (see note 3) VCCRTC 1uF Schottky Diodes 0.1uF RTCX2 1 K Vbatt 20 K 20 K R1 10M 32.768 KHz Xtal RTCX1 1.0 uF C1 1.0 uF C2 RTCRST# SRTCRST# Notes: 1. The exact capacitor values for C1 and C2 must be based on the crystal maker recommendations. 2. Reference designators are arbitrarily assigned. 3. For platforms not supporting Deep S4/S5, the VccDSW3_3 pins will be connected to the VccSus3_3 pins. 4. Vbatt is voltage provided by the RTC battery (for example, coin cell). 5. VccRTC, RTCX1, RTCX2, RTCRST#, and SRTCRST# are PCH pins. 6. VccRTC powers PCH RTC well. 7. RTCX1 is the input to the internal oscillator. 8. RTCX2 is the amplified feedback for the external crystal. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 79 Signal Description 80 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCH Pin States 3 PCH Pin States 3.1 Integrated Pull-Ups and Pull-Downs Table 3-1. Integrated Pull-Up and Pull-Down Resistors Resistor Nominal Notes GPIO[67:64] Signal Pull-down 20K 1, 10 GPIO15 Pull-down 20K 3 HDA_SDIN[3:0] Pull-down 20K 2 HDA_SYNC, HDA_SDO Pull-down 20K 2, 5 GNT[3:1]#/GPIO[55,53,51], Pull-up 20K 3, 6, 7 GPIO8 Pull-up 20K 3, 12 LAD[3:0]# Pull-up 20K 3 LDRQ0#, LDRQ1# / GPIO23 Pull-up 20K 3 DF_TVS PME# Pull-down 20k 8 Pull-up 20K 3 INIT3_3V# Pull-up 20K 3 PWRBTN# Pull-up 20K 3 SPI_MOSI Pull-down 20K 3, 5 SPI_MISO Pull-up 20K 3 Pull-down SPKR 20K 3, 9 Pull-up 20K 3 (only on TACH[7:0]) Pull-down 20K 4 GPIO72 Pull-up 20K 3 GPIO27 Pull-up 20K 3, 14 TACH[7:0]/GPIO[71:68,7,6,1,17] USB[13:0] [P,N] JTAG_TDI, JTAG_TMS JTAG_TCK GPIO28 Pull-up 20K 1, 11 Pull-down 20K 1, 11 Pull-up 20K 3, 12 SATA[3:2]GP/GPIO[37:36] Pull-down 20K 3, 9 GPIO31/MGPIO2 Pull-down 20K 3, 15 Pull-up 20K 1, 12 GPIO44 Pull-down 10K 16 GPIO46 SST Pull-up 20K 1, 12 SATA1GP/GPIO19 Pull-up 20K 3, 9 SUSACK# Pull-up 20K 3 Pull-down 350 17 SASSMBCLK0, SASSMBDATA0 PECI Pull-up 20K 3 SASSMBCLK1, SASSMBDATA1 Pull-up 20K 3 SASSMBCLK2, SASSMBDATA2 Pull-up 20K 3 Notes: 1. Simulation data shows that these resistor values can range from 10 k to 40 k. 2. Simulation data shows that these resistor values can range from 9 k to 50 k. 3. Simulation data shows that these resistor values can range from 15 k to 40 k. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 81 PCH Pin States 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 3.2 Simulation data shows that these resistor values can range from 14.25 k to 24.8 k The pull-up or pull-down on this signal is only enabled at boot/reset for strapping function. The pull-up on this signal is not enabled when PCIRST# is high. The pull-up on this signal is not enabled when PCH_PWROK is low. Simulation data shows that these resistor values can range from 15 k to 31 k. The Pull-up or pull down is not active when PLTRST# is NOT asserted. The pull-down is enabled when PCH_PWROK is low. External termination is also required on these signals for JTAG enabling. Pull-up is disabled after RSMRST# is deasserted. Not applicable for PCH. Pull-up is enabled only in Deep-S4/5 state. Pull-down is enabled only in Deep-S4/5 state. When the interface is in BUS IDLE, the Internal Pull-down of 10K is enabled. In normal transmission, a 400 ohm pull down takes effect, the signal will be override to logic 1 with pull-up resistor (37 ohms) to VCC 1.5 V. This is a 350- normal pull-down, signal will be overridden to logic 1 with pull-up resistor (31 ) to VCC 1.1 V. Output and I/O Signals Planes and States Table 3.2 shows the power plane associated with the output and I/O signals, as well as the state at various times. Within the table, the following terms are used: Note: "High-Z" Tri-state. PCH not driving the signal high or low. "High" PCH is driving the signal to a logic 1. "Low" PCH is driving the signal to a logic 0. "Defined" Driven to a level that is defined by the function or external pullup/pull-down resistor (will be high or low). "Undefined" PCH is driving the signal, but the value is indeterminate. "Running" Clock is toggling or signal is transitioning because function not stopping. "Off" The power plane is off; PCH is not driving when configured as an output or sampling when configured as an input. "Input" PCH is sampling and signal state determined by external driver. Signal levels are the same in S4 and S5, except as noted. PCH suspend well signal states are indeterminate and undefined and may glitch prior to RSMRST# deassertion. This does not apply to SLP_S3#, SLP_S4# and SLP_S5#. These signals are determinate and defined prior to RSMRST# deassertion. PCH core well signal states are indeterminate and undefined and may glitch prior to PCH_PWROK assertion. This does not apply to THRMTRIP#. This signal is determinate and defined prior to PCH_PWROK assertion. DSW indicates PCH Deep Sleep Well.This state provides a few wake events and critical context context to allow system to draw minimal power in S4 or S5 states. ASW indicates PCH Active Sleep Well. This power well contains functionality associated with active usage models while the host system is in Sx. 82 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCH Pin States Table 3-2. Power Plane and States for Output and I/O Signals (Sheet 1 of 4) Signal Name Power Plane During Reset2 Immediately after Reset2 S0/S1 S3 S4/S5 Low4 Defined OFF OFF Low Defined Off Off Low Low Off Off PCI Express PET[8:1]p, PET[8:1]n Core Low DMI DMI_TXP[3:0], DMI_TXN[3:0] Core Low PCI Bus AD[31:0] Core Low C/BE[3:0]# Core Low Low Low Off Off DEVSEL# Core High-Z High-Z High-Z Off Off FRAME# Core High-Z High-Z High-Z Off Off GNT0#7, GNT[3:1]#7/ GPIO[55, 53, 51] Core High High High Off Off IRDY#, TRDY# Core High-Z High-Z High-Z Off Off PAR Core Low Low Low Off Off PCIRST# Suspend Low High High Low Low PERR# Core High-Z High-Z High-Z Off Off PLOCK# Core High-Z High-Z High-Z Off Off STOP# Core High-Z High-Z High-Z Off Off LPC/FWH Interface LAD[3:0] Core High High High Off Off LFRAME# Core High High High Off Off INIT3_3V#7 Core High High High Off Off Defined Off Off SATA Interface SATA[5:0]TXP, SATA[5:0]TXN Core High-Z High-Z SATALED# Core High-Z High-Z Defined Off Off SATAICOMPO Core High High Defined Off Off SCLOCK/GPIO22 Core High-Z (Input) High-Z (Input) Defined Off Off SLOAD/GPIO38 Core High-Z (Input) High-Z (Input) Defined Off Off SDATAOUT[1:0]/GPIO[48,39] Core High-Z High-Z High-Z Off Off Core Terminated to Vss Terminated to Vss Terminated to Vss Off Off SATA3RBIAS SATA3ICOMPO Core High-Z High-Z High-Z Off Off SATA3RCOMPO Core High-Z High-Z High-Z Off Off Interrupts PIRQ[A:D]#, Core High-Z High-Z High-Z Off Off PIRQ[H:E]# / GPIO[5:2] Core High-Z (Input) High-Z (Input) Defined Off Off SERIRQ Core High-Z High-Z High-Z Off Off Low Defined Defined Defined USB Interface USB[13:0][P,N] Suspend Low Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 83 PCH Pin States Table 3-2. Power Plane and States for Output and I/O Signals (Sheet 2 of 4) Signal Name Power Plane During Reset2 Immediately after Reset2 S0/S1 S3 S4/S5 USBRBIAS Suspend High-Z High-Z High High High Power Management LAN_PHY_PWR_CTRL GPIO12 10 / Suspend Low Low Defined Defined Defined PLTRST# Suspend Low High High Low Low 5 Suspend Low High High Defined Defined SLP_S3# Suspend Low High High Low Low SLP_S4# Suspend Low High High High Defined SLP_S5#/GPIO63 Suspend Low High High High Defined2 High High High High SLP_A# SLP_SUS# DSW Low SUSCLK Suspend Low DRAMPWROK Suspend Low High-Z High-Z High-Z Low PM_SYNC Core Low Low Defined Off Off PM_SYNC2 Core SLP_LAN#/GPIO298 SLP_LAN# (using soft-strap) GPIO29 (using soft-strap) Running Low Low Defined Off Off Low Low8 High Defined Defined High-z High-z High-z High-z High-z High High Off Off High-Z Defined Defined Defined Defined Off Off Off Off Defined Off Off Defined Defined Defined Suspend Processor Interface PROCPWRGD Processor Low SMBus Interface SMBCLK, SMBDATA Suspend High-Z SAS SMBus Interface SASSMBCLK0, SASSMBDATA0 CORE High-Z High-Z SAS SMBus Interface (Intel(R) C606, C608 Chipset SKUs Only) SASSMBCLK1, SASSMBDATA1 CORE High-Z High-Z Defined SAS SMBus Interface (Intel(R) C608 Chipset SKU Only) SASSMBCLK2, SASSMBDATA2 CORE High-Z High-Z System Management Interface SML0ALERT# / GPIO60 Suspend High-Z High-Z12 SML0DATA Suspend High-Z High-Z Defined Defined Defined SML0CLK Suspend High-Z High-Z Defined Defined Defined GPIO58/SML1CLK Suspend High-Z High-Z Defined Defined Defined SML1ALERT#/PCH_HOT#/ GPIO74 Suspend High-Z High-Z Defined Defined Defined SML1DATA/GPIO75 Suspend High-Z High-Z Defined Defined Defined Miscellaneous Signals SPKR 7 JTAG_TDO Core Low Low Defined Off Off Suspend High-Z High-Z High-Z High-Z High-Z Defined Low Low Intel(R) HD Audio Interface HDA_RST# 84 Suspend Low Low3 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCH Pin States Table 3-2. Power Plane and States for Output and I/O Signals (Sheet 3 of 4) Signal Name Power Plane During Reset2 Immediately after Reset2 S0/S1 S3 S4/S5 HDA_SDO7 Suspend Low Low Defined Low Low HDA_SYNC7 Suspend Low Low Defined Low Low HDA_BCLK13 Suspend Low Low Low Low Low UnMultiplexed GPIO Signals GPIO8 Suspend High High Defined Defined Defined GPIO157 Suspend Low Low Defined Defined Defined GPIO24 Suspend Low Low Defined Defined Defined GPIO27(Non-Deep S4/S5 mode) DSW High-Z High-Z High-Z High-Z High-Z GPIO27(Deep S4/S5 mode) DSW High-Z High-Z High-Z High-Z High-Z GPIO2812 Suspend High Low Low Low Low GPIO32 Core High High Defined Off Off GPIO57 Suspend High-Z (Input) High-Z (Input) Defined Defined Defined GPIO729 Suspend High High Defined Defined Defined Multiplexed GPIO Signals used as GPIO only GPIO0 Core High-Z (Input) High-Z (Input) Defined Off Off GPIO139, 14 Suspend High-Z High-Z High-Z High-Z High-Z GPIO20 Core High-Z (Input) High-Z (Input) Defined Off Off GPIO309 Suspend High-Z (Input) High-Z (Input) Defined Defined Defined GPIO319 (Non Deep-S4/S5 mode) DSW High-Z (Input) High-Z (Input) Defined Defined Defined GPIO319 (Deep-S4/S5 mode) DSW High-Z (Input) High-Z (Input) Defined Defined Defined GPIO339 Core High High High Off Off GPIO34 Core High-Z (Input) High-Z (Input) Defined Off Off GPIO35/NMI# Core Low Low Defined Off Off GPIO[46:44] Suspend High-Z (Input) High-Z (Input) Defined Defined Defined GPIO61 Suspend Low High High Low Low SPI Interface SPI_CS0# ASW High12 High Defined Defined Defined SPI_CS1# ASW High12 High Defined Defined Defined SPI_MOSI ASW Low 12 Low Defined Defined Defined SPI_CLK ASW Low12 Low Running Defined Defined Thermal Reporting PWM[3:0] Core Low Low Defined Off Off SST Suspend Low Low Defined Off Off PECI Processor Low Low Defined Off Off Defined Off Off SAS Interface (SRV/WS SKUs Only) SAS[3:0]TXN, SAS[3:0]TXP CORE High-Z High-Z SAS_CLOCK1 CORE High-Z (Input) High-Z (Input) Defined Off Off SAS_LOAD1 CORE High-Z (Input) High-Z (Input) Defined Off Off SAS_DATAIN1 CORE High-Z (Input) High-Z (Input) Defined Off Off Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 85 PCH Pin States Table 3-2. Power Plane and States for Output and I/O Signals (Sheet 4 of 4) Signal Name Power Plane SAS_DATAOUT1 SAS_RBIASN0, SAS_RBIASP0 During Reset2 Immediately after Reset2 CORE High-Z Core Terminated to Vss S0/S1 S3 S4/S5 High-Z High-Z Off Off Terminated to Vss Terminated to Vss Off Off Off Off SAS Interface (Intel(R) C606, C608 Chipset SKUs Only) SAS[7:4]TXN, SAS[7:4]TXP CORE High-Z High-Z Defined SAS_CLOCK2 CORE High-Z (Input) High-Z (Input) Defined Off Off SAS_LOAD2 CORE High-Z (Input) High-Z (Input) Defined Off Off SAS_DATAIN2 CORE High-Z (Input) High-Z (Input) Defined Off Off SAS_DATAOUT2 CORE High-Z High-Z High-Z Off Off SAS_RBIASN1, SAS_RBIASP1 Core Terminated to Vss Terminated to Vss Terminated to Vss Off Off PCIe* Uplink (Intel(R) C606, C608 Chipset SKUs Only) PEG0_TXN_[3:0], PEG0_TXP_[3:0] CORE High-Z Defined Defined Off Off PEG0_RBIASN, PEG_RBIASP Core Terminated to Vss Terminated to Vss Terminated to Vss Off Off Notes: 1. The states of Core and processor signals are evaluated at the times During PLTRST# and Immediately after PLTRST#. The states of the Suspend signals are evaluated at the times During RSMRST# and Immediately after RSMRST#, with an exception to GPIO signals; refer to Section 2.23 for more details on GPIO state after reset. The states of the HDA signals are evaluated at the times During HDA_RST# and Immediately after HDA_RST# 2. SLP_S5# signals will be high in the S4 state and low in the S5 state. 3. Low until Intel HD Audio Controller Reset bit set (D27:F0:Offset HDBAR+08h:bit 0), at which time HDA_RST# will be High and HDA_BIT_CLK will be Running. 4. PETp/n[8:1] low until port is enabled by software. 5. The SLP_A# state will be determined by Intel ME Policies. 6. The state of signals in S3-5 will be defined by Intel ME Policies. 7. This signal is sampled as a functional strap during reset. Refer to Functional straps definition table for usage. 8. SLP_LAN# behavior after reset is dependent on value of SLP_LAN# default value bit. A soft-strap is used to select between SLP_LAN# and GPIO usage. When strap is set to 0 (default), pin is used as SLP_LAN#, when soft-strap is set to 1, pin is used as GPIO29. 9. Native functionality multiplexed with these GPIOs are not utilized in PCH. 10. Native/GPIO functionality controlled using soft straps. Default to Native functionality until soft straps are loaded. 11. State of the pins depend on the source of VccASW power. 12. Pin is tri-stated prior to APWROK assertion during Reset. 13. When Controller Reset Bit of Global Control Register (D27:F0 Offset HDBAR 08h bit 0) gets set, this pin will start toggling. 14. GPIO13 is powered by VccSusHDA (either 3.3 V or 1.5 V). Voltage tolerance on the signal is the same as VccSusHDA. 86 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCH Pin States 3.3 Power Planes for Input Signals Table 3-3 shows the power plane associated with each input signal, as well as what device drives the signal at various times. Valid states include: High Low Static: Will be high or low, but will not change Driven: Will be high or low, and is allowed to change Running: For input clocks PCH suspend well signal states are indeterminate and undefined and may glitch prior to RSMRST# deassertion. This does not apply to SLP_S3#, SLP_S4# and SLP_S5#. These signals are determinate and defined prior to RSMRST# deassertion. PCH core well signal states are indeterminate and undefined and may glitch prior to PCH_PWROK assertion. This does not apply to FERR# and THRMTRIP#. These signals are determinate and defined prior to PCH_PWROK assertion. Table 3-3. Power Plane for Input Signals (Sheet 1 of 3) Signal Name Power Well Driver During Reset S0/S1 S3 S4/S5 Driven Off Off Driven Off Off DMI DMI_RXP[3:0], DMI_RXN[3:0] Core Processor PCI Express PER[8:1]p, PER[8:1]n Core PCI Express* Device PCI Bus REQ0#, REQ1# / GPIO50 1 REQ2# / GPIO521 REQ3# / GPIO541 Core External Pull-up Driven Off Off PME# Suspend Internal Pull-up Driven Driven Driven SERR# Core PCI Bus Peripherals Driven Off Off LPC Interface LDRQ0# Core LPC Devices Driven Off Off LDRQ1# / GPIO231 Core LPC Devices Driven Off Off SATA Drive Driven Off Off SATA Interface SATA[5:0]RXP, SATA[5:0]RXN Core SATAICOMPI Core High-Z Driven Off Off SATA[5:4]GP/ GPIO[49,16]1 Core External Device or External Pull-up/Pull-down Driven Off Off SATA0GP / GPIO[ 21]1 Core External Device or External Pull-up/Pull-down Driven Off Off SATA1GP/GPIO19 Core Internal Pull-up Driven Off Off SATA[3:2]GP/ GPIO[37:36] Core Internal Pull-down Driven Off Off SATA3COMPI Core External Pull-up Driven Off Off Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 87 PCH Pin States Table 3-3. Power Plane for Input Signals (Sheet 2 of 3) Signal Name Power Well Driver During Reset S0/S1 S3 S4/S5 USB Interface OC[7:0]#/ GPIO[14,10,9,43:40,5 9]1 Suspend External Pull-ups Driven Driven Driven USBRBIAS# Suspend External Pull-down Driven Driven Driven Power Management APWROK Suspend External Circuit High Driven Driven PWRBTN# DSW Internal Pull-up Driven Driven Driven PCH_PWROK RTC External Circuit Driven Driven Driven DPWROK RTC External Circuit Driven Driven Driven RI# Suspend Serial Port Buffer Driven Driven Driven RSMRST# RTC External RC Circuit High High High SYS_RESET# Core External Circuit Driven Off Off SYS_PWROK Suspend External Circuit High Driven Driven THRMTRIP# Core (Processor) External Thermal Sensor Driven Off Off WAKE# Suspend External Pull-up Driven Driven Driven Processor Interface A20GATE Core External Micro controller or Pull-up Static Off Off RCIN# Core External Micro controller High Off Off System Management Interface SMBALERT# / GPIO11 Suspend External Pull-up Driven Driven Driven INTRUDER# RTC External Switch Driven Driven Driven Internal Pull-up High High High JTAG Interface JTAG_TDI3 Suspend JTAG_TMS3 Suspend Internal Pull-up High High High JTAG_TCK3 Suspend Internal Pull down Low Low Low External Pull-up High High High Miscellaneous Signals INTVRMEN2 RTC RTCRST# RTC External RC Circuit High High High SRTCRST# RTC External RC Circuit High High High Clock Interface 88 CLKIN_SATA_N, CLKIN_SATA_P Core Clock Generator Running Off Off CLKIN_DOT_96P, CLKIN_DOT_96N Core Clock Generator Running Off Off CLKIN_PCI Core Clock Generator Running Off Off CLKIN_SAS0_N, CLKIN_SAS0_P Core Clock Generator Running Off Off REFCLK14IN Core Clock Generator Running Off Off Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCH Pin States Table 3-3. Power Plane for Input Signals (Sheet 3 of 3) Signal Name Power Well Driver During Reset S0/S1 S3 S4/S5 Clock Interface (Intel(R) C606, C608 Chipset SKUs Only) CLKIN_SPCIE0_N, CLKIN_SPCIE0_P Core Clock Generator Running Off Off CLKIN_SAS1_N, CLKIN_SAS1_P Core Clock Generator Running Off Off Driven Low Low Driven Driven Driven Driven Off Off Driven Off Off Off Off Defined Off Intel(R) HD Audio Interface HDA_SDIN[3:0] Suspend Internal Pull-down SPI Interface SPI_MISO ASW Internal Pull-up Thermal Control TACH[7:0]/ GPIO[71:68,7,6,1,17]1 Core Internal Pull-up SAS Interface SAS[3:0]RXP, SAS[3:0]RXN Core Internal Pull-down SAS Interface (Intel(R) C606, C608 Chipset SKUs Only) SAS[7:4]RXP, SAS[7:4]RXN Core Internal Pull-down Driven PCIe3 Uplink (Intel(R) C606, C608 Chipset SKUs Only) PEG0_RXN_[3:0], PEG0_RXP_[3:0] CORE High-Z Defined Notes: 1. These signals can be configured as outputs in GPIO mode. 2. This signal is sampled as a functional strap during Reset. Refer to Functional straps definition table for usage. 3. External termination is also required for JTAG enabling. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 89 PCH Pin States 90 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet System Clock Domains 4 System Clock Domains The PCH uses clock source inputs provided by CK420BQ (SRV/WS SKUs Only) or CK505 (HEDT SKU Only), external clock chips. The inputs to PCH include: * 100 MHz differential, PCI Express 2.0 spec compliant, SSC capable * 100 MHz differential isolated for SATA, SSC capable * 100 MHz differential isolated for SAS, non SSC (SRV/WS SKUs Only) * 100 MHz differential for PCIe Uplink ports, SSC capable * 96 MHz differential, non SSC * 14.318 MHz single-ended non SSC 4.1 System Clock Domains Table 4-1 shows the system clock input to the PCH. Table 4-1 shows system clock domains generated by the PCH. Table 4-1. PCH Clock Inputs Signal Frequency Usage CLKIN_DMI_P, CLKIN_DMI_N 100 MHz 100 MHz differential reference clock from CK420BQ (SRV/WS SKUs Only) or CK505 (HEDT SKU Only). Used for DMI and PCIe 2.0 when clock isolation is disabled. Used for DMI only when clock isolation is enabled CLKIN_SATA_P, CLKIN_SATA_N 100 MHz 100 MHz differential reference clock from CK420BQ (SRV/WS SKUs Only) or CK505 (HEDT SKU Only). Used for SATA. CLKIN_DOT96_P, CLKIN_DOT96_N 96 MHz 96 MHz differential reference clock from CK420BQ (SRV/WS SKUs Only) or CK505 (HEDT SKU Only). CLKIN_PCI 33.3 MHz 33.3 MHZ PCI reference clock REFCLK14IN 14.31818 MHz Single-ended 14.31818 MHz reference clock from CK420BQ (SRV/WS SKUs Only) or CK505 (HEDT SKU Only). Used for 8254 Timer, ACPI Timer and HPET. RTCX1 32.768 KHz Reference input for RTC Oscillator RTCX2 32.768 KHz See above CLKIN_SAS0_P, CLKIN_SAS0_N 100 MHz 100 MHz differential reference clock from CK420BQ (SRV/WS SKUs Only). Used as SAS clock for SCU0 (SAS Controller Unit) and SCU1. CLKIN_SAS1_P, CLKIN_SAS1_N 100 MHz 100 MHz differential reference clock from CK420BQ (SRV/WS SKUs Only). Used as supplemental clock source for SCU1 in Intel(R) C606, C608 Chipset SKUs. CLKIN_SPCIE0_P, CLKIN_SPCIE0_N 100 MHz 100 MHz differential reference clock from CK420BQ (SRV/WS SKUs Only). Used as upstream PCIe Uplink switch port clock reference Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 91 System Clock Domains Table 4-2. PCH Clock Outputs Signal Frequency Usage GP22_SCLOCK 32.768 KHz SCLOCK is SATA SGPIO Reference Clock. Can also be used as GPIO22 SUSCLK_GP62 32.768 KHz SUSCLK is a suspend clock output from RTC generator circuit. Can also be used as GPIO62 SPI_CLK 17.86 MHz/ 20.83 MHz/ 31.25 MHz SPI Flash clock output Figure 4-1 and Figure 4-2 show the high level block diagram of PCH clocking. Figure 4-1. PCH High-Level Clock Diagram (SRV/WS SKUs Only) The image cannot be Processor displayed. Your computer may not have enough memory to open the image, or the image may h b 25 M Xtal DMI SATA 100 M SAS 100 M CK420BQ DOT96 REF14 PCIe Uplink The image cannot be display ed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may hav e to delete the image and then insert it again. SATA PLL SAS PLL Int OSC USB USB PLL PLL (USB 2.0/1.0) Legacy 14 M RTC 32.768 M SPI DMI DMI ME ME 100 M DMI DB1900Z PCIe Uplink 100 M 92 PCIe Gen2 PLL PCIe Gen3 Uplink PLL PCIe 2.0 PCH Patsburg Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet System Clock Domains Figure 4-2. PCH High-Level Clock Diagram (HEDT SKU Only) Gear Shift PLL DB1200GS SRC8 1:1 PLL CK505 CLKIN_PEG_Upstream CLKIN_DMI SRC6 PCI3 PCI4 SRC7 SRC5 PCI CLK Slot SRC Slot SRC CLKIN_CPY PCI_IN PCI Slot - Off PBG SRC3 SPI_CLK FLASH PCH PCIex1 Slot - Off PBG PCIex1 Slot - Off PBG CLKIN_SATA CLKIN_DOT96 DOT96 SRC4 100MHz Clock Source Non SSC 4.2 CLKIN_SAS Functional Blocks Table 4-3 describes the PLLs on the PCH and the clock domains that are driven from the PLLs. Table 4-3. PCH PLLs (Sheet 1 of 2) PLL DMI PLL PCIe2 PLL SATA PLL Outputs Frequency Description/Usage 2.5 GHz/625 MHz/250 MHz Source clock is 100 MHz from CK420BQ (SRV/WS SKUs Only) or CK505 (HEDT SKU Only). The PLL resource to generate the DMI port clocks when clock isolation is enabled. Uses CLKIN_DMI input. This PLL is shut down when clock isolation is disabled. Resides in core power well and is not powered in S3 and below states. 2.5 GHz/625 MHz/250 MHz Source clock is 100 MHz from CK420BQ (SRV/WS SKUs Only) or CK505 (HEDT SKU Only). PCIe2 PLL drives clocks to PCIe 2.0 ports, Intel ME/VE engines2 (in S0 state) and the NAND interface logic2 (in S0 state). It is also used to supply DMI clocks when clock isolation is disabled. Can be configured to use CLKIN_DMI (when clock isolation is disabled) or optional CLKIN_CPY input (when clock isolation is enabled). Resides in core power well and is not powered in S3 and below states. 3.0 GHz/1.5 GHz/ 300 MHz/150 MHz Source clock is 100 MHz from CK420BQ (SRV/WS SKUs Only) or CK505 (HEDT SKU Only). This PLL generates clocks for SATA Gen2 and SATA Gen3 ports. Uses CLKIN_SATA input. Resides in core power well and is not powered in S3 and below states. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 93 System Clock Domains Table 4-3. PCH PLLs (Sheet 2 of 2) PLL USB PLL PCIe Uplink PLL (SRV/WS SKUs Only) SAS PLL (SRV/WS SKUs Only) Outputs Frequency Description/Usage 24 MHz/48 MHz/240 MHz/ 480 MHz Source clock is 96 MHz from CK420BQ (SRV/WS SKUs Only) or CK505 (HEDT SKU Only). Uses CLKIN_DOT96 input. Used for USB 2.0/1.0 logic. Resides in core power well and is not powered in S3 and below states. 4.0 GHz/500 MHz/250 MHz Source clock is 100 MHz from CK420BQ (SRV/WS SKUs Only) or CK505 (HEDT SKU Only). There are two PCIe Uplink PLLs in PCH. They generate clocks for PCIe Uplink ports. Uses CLKIN_SPCIE0 input. Resides in core power well and is not powered in S3 and below states. 3.0 GHz/1.5 GHz Source clock is 100 MHz from CK420BQ (SRV/WS SKUs Only). For Intel(R) C602, C602J, C604 Chipset SKUs, the SAS PLL generates all the required SAS clocks. It uses CLKIN_SAS0 input. For Intel(R) C606, C608 Chipset SKUs, there are two SAS PLLs and each SCU (SAS Controller Unit) has one SAS PLL to provide SAS clocks for it. They use CLKIN_SAS[1:0] as inputs, where CLKIN_SAS0 is used for the first SCU and CLKIN_SAS1 for the second SCU. Resides in core power well and is not powered in S3 and below states. 94 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5 Functional Description This chapter describes the functions and interfaces of the PCH. 5.1 PCI-to-PCI Bridge (D30:F0) The PCI-to-PCI bridge resides in PCI Device 30, Function 0 on bus #0. This portion of the PCH implements the buffering and control logic between PCI and Direct Media Interface (DMI). The arbitration for the PCI bus is handled by this PCI device. The PCI decoder in this device must decode the ranges for the DMI. All register contents are lost when core well power is removed. DMI is the chip-to-chip connection between the Processor and PCH. This high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. Base functionality is completely software transparent permitting current and legacy software to operate normally. New for PCH the DMI interface operates at 5.0 GT/s. To provide for true isochronous transfers and configurable Quality of Service (QoS) transactions, the PCH supports two virtual channels on DMI -- VC0 and VC1. These two channels provide a fixed arbitration scheme where VC1 is always the highest priority. VC0 is the default conduit of traffic for DMI and is always enabled. VC1 must be specifically enabled and configured at both ends of the DMI link (that is, the PCH and processor). Configuration registers for DMI, virtual channel support, and DMI active state power management (ASPM) are in the RCRB space in the Chipset Config Registers (Chapter 10.1). DMI is also capable of operating in the AC terminated mode for servers. A hardware strap is used to configure DMI in AC terminated mode, see Section 2.26 for details. 5.1.1 PCI Bus Interface The PCH PCI interface supports PCI Local Bus Specification, Revision 2.3, at 33 MHz. The PCH integrates a PCI arbiter that supports up to four external PCI bus masters in addition to the internal PCH requests. See Section 5.2 for alternative methods for supporting PCI devices. 5.1.2 PCI Bridge As an Initiator The bridge initiates cycles on the PCI bus when granted by the PCI arbiter. The bridge generates the cycle types shown in Table 5-1. Table 5-1. PCI Bridge Initiator Cycle Types Command C/BE# Notes I/O Read/Write 2h/3h Non-posted Memory Read/Write 6h/7h Writes are posted Configuration Read/Write Ah/Bh Non-posted Special Cycles 1h Posted Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 95 Functional Description 5.1.2.1 Memory Reads and Writes The bridge bursts memory writes on PCI that are received as a single packet from DMI. 5.1.2.2 I/O Reads and Writes The bridge generates single DW I/O read and write cycles. When the cycle completes on the PCI bus, the bridge generates a corresponding completion on DMI. If the cycle is retried, the cycle is kept in the down bound queue and may be passed by a postable cycle. 5.1.2.3 Configuration Reads and Writes The bridge generates single DW configuration read and write cycles. When the cycle completes on the PCI bus, the bridge generates a corresponding completion. If the cycle is retried, the cycle is kept in the down bound queue and may be passed by a postable cycle. 5.1.2.4 Locked Cycles The bridge propagates locks from DMI per the PCI Local Bus Specification. The PCI bridge implements bus lock, which means the arbiter will not grant to any agent except DMI while locked. If a locked read results in a target or master abort, the lock is not established (as per the PCI Local Bus Specification). Agents north of the PCH must not forward a subsequent locked read to the bridge if they see the first one finish with a failed completion. 5.1.2.5 Target / Master Aborts When a cycle initiated by the bridge is master/target aborted, the bridge will not reattempt the same cycle. For multiple DW cycles, the bridge increments the address and attempts the next DW of the transaction. For all non-postable cycles, a target abort response packet is returned for each DW that was master or target aborted on PCI. The bridge drops posted writes that abort. 5.1.2.6 Secondary Master Latency Timer The bridge implements a Master Latency Timer using the SMLT register which, upon expiration, causes the deassertion of FRAME# at the next legal clock edge when there is another active request to use the PCI bus. 5.1.2.7 Dual Address Cycle (DAC) The bridge will issue full 64-bit dual address cycles for device memory-mapped registers above 4 GB. 96 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.1.2.8 Memory and I/O Decode to PCI The PCI bridge in the PCH is a subtractive decode agent, which follows the following rules when forwarding a cycle from DMI to the PCI interface: * The PCI bridge will positively decode any memory/IO address within its window registers, assuming PCICMD.MSE (D30:F0:Offset 04h:bit 1) is set for memory windows and PCICMD.IOSE (D30:F0:Offset 04h:bit 0) is set for I/O windows. * The PCI bridge will subtractively decode any 64-bit memory address not claimed by another agent, assuming PCICMD.MSE (D30:F0:Offset 04h:bit 1) is set. * The PCI bridge will subtractively decode any 16-bit I/O address not claimed by another agent assuming PCICMD.IOSE (D30:F0:Offset 04h:bit 0) is set. * If BCTRL.IE (D30:F0:Offset 3Eh:bit 2) is set, the PCI bridge will not positively forward from primary to secondary called out ranges in the I/O window per PCI Local Bus Specification (I/O transactions addressing the last 768 bytes in each, 1 KB block: offsets 100h to 3FFh). The PCI bridge will still take them subtractively assuming the above rules. * If BCTRL.VGAE (D30:F0:Offset 3Eh:bit 3) is set, the PCI bridge will positively forward from primary to secondary I/O and memory ranges as called out in the PCI Bridge Specification, assuming the above rules are met. 5.1.3 Parity Error Detection and Generation PCI parity errors can be detected and reported. The following behavioral rules apply: * When a parity error is detected on PCI, the bridge sets the SECSTS.DPE (D30:F0:Offset 1Eh:Bit 15). * If the bridge is a master and BCTRL.PERE (D30:F0:Offset 3Eh:Bit 0) is set and one of the parity errors defined below is detected on PCI, then the bridge will set SECSTS.DPD (D30:F0:Offset 1Eh:Bit 8) and will also generate an internal SERR#. -- During a write cycle, the PERR# signal is active, or -- A data parity error is detected while performing a read cycle * If an address or command parity error is detected on PCI and PCICMD.SEE (D30:F0:Offset 04h:bit 8), BCTRL.PERE, and BCTRL.SEE (D30:F0:Offset 3Eh:Bit 1) are all set, the bridge will set PSTS.SSE (D30:F0:Offset 06h:Bit 14) and generate an internal SERR#. * If the PSTS.SSE is set because of an address parity error and the PCICMD.SEE is set, the bridge will generate an internal SERR#. * When bad parity is detected from DMI, bad parity will be driven on all data from the bridge. * When an address parity error is detected on PCI, the PCI bridge will never claim the cycle. This is a slight deviation from the PCI bridge spec, which says that a cycle should be claimed if BCTRL.PERE is not set. However, DMI does not have a concept of address parity error, so claiming the cycle could result in the rest of the system seeing a bad transaction as a good transaction. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 97 Functional Description 5.1.4 PCIRST# The PCIRST# pin is generated under two conditions: * PLTRST# active * BCTRL.SBR (D30:F0:Offset 3Eh:Bit 6) set to 1 The PCIRST# pin is in the suspend well. PCIRST# should be tied to PCI bus agents, but not other agents in the system. 5.1.5 Peer Cycles The PCI bridge may be the initiator of peer cycles. Peer cycles include memory, I/O, and configuration cycle types. Peer cycles are only allowed through VC0, and are enabled with the following bits: * BPC.PDE (D30:F0:Offset 4Ch:Bit 2) - Memory and I/O cycles * BPC.CDE (D30:F0:Offset 4Ch:Bit 1) - Configuration cycles When enabled for peer for one of the above cycle types, the PCI bridge will perform a peer decode to see if a peer agent can receive the cycle. When not enabled, memory cycles (posted and/or non-posted) are sent to DMI, and I/O and/or configuration cycles are not claimed. Configuration cycles have special considerations. Under the PCI Local Bus Specification, these cycles are not allowed to be forwarded upstream through a bridge. However, to enable things such as manageability, BPC.CDE can be set. When set, type 1 cycles are allowed into the part. The address format of the type 1 cycle is slightly different from a standard PCI configuration cycle to allow addressing of extended PCI space. The format is shown as in Table 5-2: Table 5-2. Type 1 Address Format Bits Definition 31:27 Reserved (same as the PCI Local Bus Specification) 26:24 Extended Configuration Address - allows addressing of up to 4K. These bits are combined with Bits 7:2 to get the full register. 23:16 Bus Number (same as the PCI Local Bus Specification) 15:11 Device Number (same as the PCI Local Bus Specification) 10:8 Function Number (same as the PCI Local Bus Specification) 7:2 Register (same as the PCI Local Bus Specification) 1 0 0 Must be 1 to indicate a type 1 cycle. Type 0 cycles are not decoded. Note: The PCH's USB controllers cannot perform peer-to-peer traffic. 5.1.6 PCI-to-PCI Bridge Model From a software perspective, the PCH contains a PCI-to-PCI bridge. This bridge connects DMI to the PCI bus. By using the PCI-to-PCI bridge software model, the PCH can have its decode ranges programmed by existing plug-and-play software such that PCI ranges do not conflict with graphics aperture ranges in the Host controller. 98 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.1.7 IDSEL to Device Number Mapping When addressing devices on the external PCI bus (with the PCI slots), the PCH asserts one address signal as an IDSEL. When accessing Device 0, the PCH asserts AD16. When accessing Device 1, the PCH asserts AD17. This mapping continues all the way up to Device 15 where the PCH asserts AD31. Note that the PCH internal functions (Intel High Definition Audio, USB, SATA and PCI Bridge) are enumerated like they are off of a separate PCI bus (DMI) from the external PCI bus. 5.1.8 Standard PCI Bus Configuration Mechanism The PCI Bus defines a slot based "configuration space" that allows each device to contain up to eight functions with each function containing up to 256, 8-bit configuration registers. The PCI Local Bus Specification, Revision 2.3 defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration Write. Memory and I/O spaces are supported directly by the processor. Configuration space is supported by a mapping mechanism implemented within the PCH. The PCI Local Bus Specification, Revision 2.3 defines two mechanisms to access configuration space, Mechanism 1 and Mechanism 2. The PCH only supports Mechanism 1. Warning: Configuration writes to internal devices, when the devices are disabled, are illegal and may cause undefined results. 5.2 PCI Legacy Mode PCH may optionally use PCIe-to-PCI bridges to enable external PCI I/O devices. To be able to use PCIe-to-PCI bridges and attached legacy PCI devices, the PCH provides PCI Legacy Mode. PCI Legacy Mode allows both the PCI Express* root port and PCIe-to-PCI bridge look like subtractive PCI-to-PCI bridges. This allows the PCI Express* root port to subtractively decode and forward legacy cycles to the bridge, and the PCIe-to-PCI bridge continues forwarding legacy cycles to downstream PCI devices. For designs that would like to utilize PCI Legacy Mode, BIOS must program registers in the PCI-to-PCI bridge (Device 30:Function 0) and in the desired PCI Express* Root Port (Device 28:Functions 0-7) to enable subtractive decode. Note: Software must ensure that only one PCH device is enabled for Subtractive decode at a time. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 99 Functional Description 5.3 PCI Express* The PCH contains up to 8 PCI Express* root ports and one uplink port. All versions of the PCH contain the 8 root ports. The Intel(R) C606, C608 Chipset SKUs contain a x4 uplink port while the Intel(R) C602, C602J, C604 Chipset and Intel(R) X79 Express Chipset SKUs do not. The purpose of the uplink port is to provide a direct path for the SAS controllers, SGPIO used by the SAS controllers, and SMBus ports to the processor/ memory without having to be multiplexed onto the DMI bus and sharing bandwidth with the rest of the component. The uplink port is not connected to the downstream root ports (Section 5.3.2). In all configurations, the SMBus, SGPIO and SAS (SRV/WS SKUs Only) controllers are part of a multifunction device. In the Intel(R) C602, C602J, C604 Chipset SKUs, the SCU, SGPIO and SMBus controllers are connected to a virtual root port that is connected to the PCH's backbone. This is Device 31 off of Bus0. For the Intel(R) C606, C608 Chipset, the SCU, SGPIo, and SMBus devices are connected through a virtual switch to the uplink port. 5.3.1 PCI Express* UpLink Port (Bn:D0:F0) (SRV/WS SKUs Only) The PCI Express* Uplink here is an amalgram of two functions, an uplink port connecting to a PCI Express* bus, and a virtual switch connecting the uplink port to the MFD (Multi-Function Device) below. The MFD contains the SAS controllers, and SMBus controllers. This uplink has the following capabilities: * X4 link width at Gen1 speed * MSI Interrupt Messaging * ASPM support for L1 states * No ISOC support Because the PCI Express* uplink will be connected to Intel components, not 3rd party devices, the expected/supported configuration is simply x4 as Gen1. Note: 100 The only valid configuration for the PCI Express* uplink is a x4 operating at Gen1 speeds. Any other configurations or speeds are out of spec and not supported. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.3.1.1 Programming Model and Addressing for the Intel(R) C602, C602J, C604 Chipset SKUs 5.3.1.1.1 Programming Model for Intel(R) C602, C602J, C604 Chipset SKUs The functions of the integrated MFD are exposed to software through a Root Port connected off the PCH internal fabric since there is no PCI Express* uplink in the Intel(R) C602, C602J, C604 Chipset SKUs. There is no physical PCI Express* link between the root port and the MFD so the link is "virtual". Software will discover a virtual root port with an attached multi-function end point device. Figure 5-1 shows how the virtual Root Port and the Multi-Function Device as seen by software. Figure 5-1. Programming Model for Intel(R) C602, C602J, C604 Chipset SKUs PCI Bus #0 PCH Internal Fabric) Device #17 Function #0 Virtual Root Port Virtual PCI to PCI Bridge PCI Bus #X (Internal Fabric) Device #0 Function #0 PCI Express Endpoint MultiFunction Device Note: The SAS Controller Unit supports SR-IOV. Table 5-3 displays the functions visible to software for the Intel(R) C602, C602J, C604 Chipset SKUs. Table 5-3. Configuration Spaces Visible to Software in Intel(R) C602, C602J, C604 Chipset SKUs Function Virtual Root Port1 PCI Bus Number PCI Device Number PCIe Function Number 0 17 0 SAS Controller Unit 0 X2 0 0 Multi-function Glue unit X 0 1 SMBus Controller 0 Unit X 0 3 Note: 1. The current Bus/Device/Function of virtual root port is TBD. 2. X is a Bus number greater than Bus 0 assigned by Software. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 101 Functional Description 5.3.1.1.2 Address Space for Intel(R) C602, C602J, C604 Chipset SKUs Table 5-4 provides a summary of all the addressable spaces within Root Port and the MFD as seen from PCI Bus 0. A detailed description of these spaces follows in later sections. Table 5-4. Root Port and SCU Addressable Internal Spaces Addressable Space Virtual Root Port Config Space SCU Config Space(s), SCU Memory Space, SCU I/O Space SMBus 0 Config Space, SMBus 0 Memory Space, SMBus 0 I/O Space SMbus 1 Config Space, SMBus 1 Memory Space, SMBus 1 I/O Space 5.3.1.2 Programming Model and Addressing for the Intel(R) C606, C608 Chipset SKUs The functions of the integrated MFD are exposed similarly to software through a downstream switch port. Again there is no physical PCI Express* link so the link is "virtual" between the downstream switch port and the MFD. 5.3.1.3 Programming Model for the Intel(R) C606, C608 Chipset SKUs The Intel(R) C606, C608 Chipset SKUs contain a PCI Express* switch. The Intel(R) C606, C608 Chipset SKUs contains a x4 uplink and a "virtual" switch port that serves as the connection for the integrated MFD shown in Figure 5-2. Software will discover a virtual switch port with an attached multi-function end point device. The PCI Express* switch is compliant to the PCI Express Base specification 2.0. Figure 5-2. Programming Model for the Intel(R) C606, C608 Chipset SKUs PCI Bus #N (PCIELink) Bus#N Device#0 Function#0 Virtual PCI to PCI Bridge PCI Express Upstream Port Internal PCI Bus #N+1 Device#8 Function#0 Virtual PCI to PCI Bridge Virtual SwitchPort PCI Bus #X (Internal bus) SCU 0/1 102 SMBus 0/1/2 NVSRAM Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description Table 5-5 shows that configuration spaces visible to software for the Intel(R) C606, C608 Chipset SKUs. Table 5-5. Configuration Spaces Visible to Software in the Intel(R) C606, C608 Chipset SKUs Function PCI Bus Number PCI Device Number PCIe Function Number N 0 0 PCIe Upstream Virtual Switch Port SAS Controller Unit 0/1 N+1 8 0 X1 0 0 Multi-Function Glue X 0 1 SMBus Controller 0 X 0 3 SMBus Controller 1 X 0 4 SMBus Controller 2 (Intel(R) C608 Chipset SKU Only) X 0 5 1. X is a value greater than N+1 assigned by the BIOS. 5.3.1.4 Address Space for Intel(R) C606, C608 Chipset SKUs Table 5-6 provides a summary of all addressable spaces within the Intel(R) C606, C608 Chipset SKUs. Table 5-6. Intel(R) C606, C608 Chipset SKUs Addressable Internal Spaces Addressable Space PCIe Upstream Port Config Space PCIe Upstream Port Memory Space Point-to-Point Fabric Config Space Multi-Function Glue Config Space SAS Controller Config Space SAS Controller Memory Space SAS Controller I/O Space SMBus Controller 0-2 Config Space (only 2 for Intel(R) C606 Chipset SKU) SMBus Controller 0-2 Memory Space (only 2 for Intel(R) C606 Chipset SKU) SMBus Controller 0-2 IO Space (only 2 for Intel(R) C606 Chipset SKU) 5.3.1.5 Power Management The uplink PCI Express* port will support Active State Power Management (ASPM). The states supported are L0s and L1. ASPM is a hardware only form of power management. Software does not cause/force the link to go into L1. HW will enter these states based upon the state of the devices downstream. If the MFD devices are all in D3 hot, then the link can go into L3 depending on the capability programmed for both the Uplink and to what the Uplink is connected. 5.3.1.6 Error Handling The PCIe uplink supports the full AER (Advanced Error Reporting) error handling. It's use, however, is somewhat more controlled or restricted here. A lot of the error handling is there to handle communication/interface errors between the root port and an unknown device downstream. In this case, both ends of the PCI Express* link are known (Intel(R) Xeon(R) processor E5-1600/E5-2600 product families and the PCH). The endpoints for this link are the devices within PCH. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 103 Functional Description 5.3.1.6.1 Poisoned TLP If the upstream port receives a TLP with the EP bit set from the processor, it will set the Detected Data Parity Error bit of the Primary Status register and the Poisoned TLP Status bit of the Uncorrectable Error Status register. The Upstream port will send the appropriate error message to the root. If the chip detects a data parity error from data coming from the MFD, it will set the same bits for the downstream port and send the same error messages. 5.3.1.6.2 Unsupported Request When the upstream port receives a non-posted transaction (IO/Mem/Cfg) that did not match the address/ID range programmed in the upstream port, the upstream port will set the Unsupported Request Error Status of its Uncorrectable Error Status Register and send an ERR_NONFATAL message or ERR_COR message as an Advisory Non-Fatal error. 5.3.1.6.3 Completion Timeout While the upstream port will not create completion timeouts (it only passes through packets), the SCU at the end could generate a completion timeout if it doesn't get an response back from the CPU in the necessary time. 5.3.1.6.4 Completer Abort If the downstream port receives an inbound (to the memory) non-posted request from the MFD with an ACS violation, it will return a CA status to the MFD. In addition it will log the ACS violation in it's Uncorrectable Error Status Register and send an ERR_NONFATAL or ERR_COR message as an Advisory Non-Fatal error to the root port. 5.3.1.6.5 Unexpected completion The upstream port will generate this error if it receives a completion with a routing ID that does not contain a bus number within the programmed valid range. The upstream port will set the Unexpected Completion bit of it's Uncorrectable Error Status Register and send an ERR_COR messages as an Advisory Non-Fatal Error to the root port. 5.3.1.6.6 Receiver overflow When a port detects a receiver overflow error, the port will set bit the Receiver Overflow bit in the Uncorrectable Error Status Register and send an ERR_FATAL message to the root complex. 5.3.1.6.7 Flow Control Protocol Error When a port detects a flow control protocol error, the port will set the Flow Control Protocol Error bit in the Uncorrectable Error Status Register and send an ERR_FATAL message to the root complex. 5.3.1.6.8 Malformed Packet When a port receives a malformed TLP, the port will set the Malformed TLP Status bit in its Uncorrectable Error Status Register and send an ERR_FATAL message to the root complex. 5.3.1.6.9 Error Message Forwarding Error messages (ERR_COR, ERR_NONFATAL, ERR_FATAL) that are received from the MFD are forwarded from the secondary to the primary side only if the SERR# Enable bit in the Bridge Control Register is set. The error messages are forwarded by the primary side when either the SERR# Enable bit is set in the Command Register or the appropriate bit(s) are set in the Device Control Register. Note that the error messages do not have any effect on the Advanced Error Reporting bits. 104 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.3.1.6.10 Poisoned Data Forwarding When a transaction (request and completion) with bad data (poisoned TLP) enters an ingress port, the transaction will be forwarded to an egress port as a poisoned TLP. Similarly, a transaction whose data is corrupted while flowing through the switch fabric will be poisoned by the egress port. The switch internal fabric supports parity on the data bus. 5.3.1.6.11 PWROK Reset Mechanism All the voltage sources in the system are tracked by a system component that asserts the PWROK signal only after all the voltages have been stable for some predetermined time. The switch receives the PWROK signal as an asynchronous input, meaning that there is no assumed relationship between the assertion or the de-assertion of PWROK and the reference clock. While the PWROK is de-asserted, the switch holds all logic in reset. The PWROK reset clears all internal state machines and logic, and initializes all registers to their default states, including "sticky" error bits that are persistent through all other reset classes. To eliminate potential system-reliability problems, all devices are also required to either tri-state their outputs or to drive them to safe levels during such a power-on reset. Refer to the PCI Express Specification, Revision 2.0 for details of the relationship between PWROK assertion and the stability of the clocks and power at the inputs of the switch. 5.3.1.6.12 Fundamental Reset Mechanism As soon as the system is up and running, a full system reset may be required to recover from system-error conditions related to various device or subsystem failures. Fundamental reset mechanism is a warm-reset mechanism that accomplishes this recovery without clearing the "sticky" error-status bits which track the cause of the error conditions of the device or subsystem. It is equivalent to receiving a PERST# which results in a return to initial conditions. 5.3.1.6.13 PCI Express Reset Mechanism There is no reset signal on the PCI Express, and all reset communication is in-band. The upstream PCI Express device communicates the fact that it is entering and coming out of a reset using messages. The switch responds by also going through a reset. In accordance with the PCI Express protocol, this incoming message is asynchronous to the reference clock. When the uPCIe bridge is put in reset, it communicates that fact to the dPCIe bridges. Each dPCIe then sends Hot Reset indication on its link and reset their non-PRST and non-sticky registers. As long as the uPCIe is in reset, the dPCIe links are kept in reset. For example, if the dPCIe link comes out of reset and sees that the uPCIe bridge is in reset, it immediately sends a Hot Reset in-band indication and resets itself. 5.3.1.6.14 Software PCI Reset (SBR--Secondary Bus Reset) This reset is initiated by a write to the bridge control registers and resets only the particular dPCIe segment or hierarchy south of the function receiving the SBR. This reset can be used for various reasons including recovering from error conditions on the secondary bus, to redo enumeration, and so forth. This reset is synchronous to the clock domain in which it is used. The SBR is strictly restricted to the particular segment and affects neither the other segments nor the rest of the switch logic. For the dPCIe ports, SBR is strictly restricted to the particular segment and affects neither the other segments nor the rest of the switch logic. For uPCIe, SBR affects all the downstream PCI Express* segments and resets all the dPCIe register except for sticky bits. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 105 Functional Description Note that the dPCIe segment resets on the SBR bit being set and comes out of reset when the SBR bit is cleared. 5.3.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7) There are eight root ports available in the PCH. The root ports are compliant to the PCI Express 2.0 specification running at 5 GT/s. The ports all reside in Device 28, and take Function 0 - 7. Port 1 is Function 0, Port 2 is Function 1, Port 3 is Function 2, Port 4 is Function 3, Port 5 is Function 4, Port 6 is Function 5, Port 7 is function 6, and Port 8 is Function 7. PCI Express* Root Ports 1-4 or Ports 5-8 can independently be configured as four x1s, two x2s, one x2 and two x1s, or one x4 port widths.The port configuration is set by soft straps in the Flash Descriptor. Note: This section assumes the default PCI Express* Function Number-to-Root Port mapping is used. Function numbers for a given root port are assignable through the "Root Port Function Number and Hide for PCI Express* Root Ports" registers (RCBA+0404h). 5.3.2.1 Interrupt Generation The root port generates interrupts on behalf of Hot-Plug and power management events, when enabled. These interrupts can either be pin based, or can be MSIs, when enabled. When an interrupt is generated using the legacy pin, the pin is internally routed to the PCH interrupt controllers. The pin that is driven is based upon the setting of the chipset configuration registers. Specifically, the chipset configuration registers used are the D28IP (Base address + 310Ch) and D28IR (Base address + 3146h) registers. Table 5-7 summarizes interrupt behavior for MSI and wire-modes. In the table "bits" refers to the Hot-Plug and PME interrupt bits. Table 5-7. MSI versus PCI IRQ Actions Interrupt Register 106 Wire-Mode Action MSI Action All bits 0 Wire inactive No action One or more bits set to 1 Wire active Send message One or more bits set to 1, new bit gets set to 1 Wire active Send message One or more bits set to 1, software clears some (but not all) bits Wire active Send message One or more bits set to 1, software clears all bits Wire inactive No action Software clears one or more bits, and one or more bits are set on the same clock Wire active Send message Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.3.2.2 Power Management 5.3.2.2.1 S3/S4/S5 Support Software initiates the transition to S3/S4/S5 by performing an IO write to the Power Management Control register in the PCH. After the IO write completion has been returned to the processor, each root port will send a PME_Turn_Off TLP (Transaction Layer Packet) message on its downstream link. The device attached to the link will eventually respond with a PME_TO_Ack TLP message followed by sending a PM_Enter_L23 DLLP (Data Link Layer Packet) request to enter the L2/L3 Ready state. When all of the PCH root ports links are in the L2/L3 Ready state, the PCH power management control logic will proceed with the entry into S3/S4/S5. Prior to entering S3, software is required to put each device into D3HOT. When a device is put into D3HOT it will initiate entry into a L1 link state by sending a PM_Enter_L1 DLLP. Thus under normal operating conditions when the root ports sends the PME_Turn_Off message the link will be in state L1. However, when the root port is instructed to send the PME_Turn_Off message, it will send it whether or not the link was in L1. Endpoints attached to the PCH can make no assumptions about the state of the link prior to receiving a PME_Turn_Off message. Note: The PME_Turn_Off TLP messaging flow is also issued during a host reset with and without power cycle. Refer to Table 5-43 for a list of host reset resources. 5.3.2.2.2 Resuming from Suspended State The root port contains enough circuitry in the suspend well to detect a wake event through the WAKE# signal and to wake the system. When WAKE# is detected asserted, an internal signal is sent to the power management controller of the PCH to cause the system to wake up. This internal message is not logged in any register, nor is an interrupt/GPE generated due to it. 5.3.2.2.3 Device Initiated PM_PME Message When the system has returned to a working state from a previous low power state, a device requesting service will send a PM_PME message continuously, until acknowledge by the root port. The root port will take different actions depending upon whether this is the first PM_PME has been received, or whether a previous message has been received but not yet serviced by the operating system. If this is the first message received (RSTS.PS - D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 60h:Bit 16 is cleared), the root port will set RSTS.PS, and log the PME Requester ID into RSTS.RID (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 60h:Bits 15:0). If an interrupt is enabled using RCTL.PIE (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 5Ch:Bit 3), an interrupt will be generated. This interrupt can be either a pin or an MSI if MSI is enabled using MC.MSIE (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 82h:bit 0). See Section 5.3.2.2.4 for Intel(R) Scalable Memory Interconnect (Intel(R) SMI)/SCI generation. If this is a subsequent message received (RSTS.PS is already set), the root port will set RSTS.PP (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 60h:Bit 17) and log the PME Requester ID from the message in a hidden register. No other action will be taken. When the first PME event is cleared by software clearing RSTS.PS, the root port will set RSTS.PS, clear RSTS.PP, and move the requester ID from the hidden register into RSTS.RID. If RCTL.PIE is set, an interrupt will be generated. If RCTL.PIE is not set, a message will be sent to the power management controller so that a GPE can be set. If messages have been logged (RSTS.PS is set), and RCTL.PIE is later written from a 0 to a 1, and Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 107 Functional Description interrupt will be generated. This last condition handles the case where the message was received prior to the operating system re-enabling interrupts after resuming from a low power state. 5.3.2.2.4 Intel(R) Scalable Memory Interconnect (Intel(R) SMI)/SCI Generation Interrupts for power management events are not supported on legacy operating systems. To support power management on non-PCI Express* aware operating systems, PM events can be routed to generate SCI. To generate SCI, MPC.PMCE must be set. When set, a power management event will cause SMSCS.PMCS (D28:F0/F1/F2/ F3/F4/F5/F6/F7:Offset DCh:Bit 31) to be set. Additionally, BIOS workarounds for power management can be supported by setting MPC.PMME (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset D8h:Bit 0). When this bit is set, power management events will set SMSCS.PMMS (D28:F0/F1/F2/F3/F4/F5/F6/ F7:Offset DCh:Bit 0), and SMI# will be generated. This bit will be set regardless of whether interrupts or SCI is enabled. The SMI# may occur concurrently with an interrupt or SCI. 5.3.2.3 SERR# Generation SERR# may be generated using two paths - through PCI mechanisms involving bits in the PCI header, or through PCI Express* mechanisms involving bits in the PCI Express* capability structure. Figure 5-3. Generation of SERR# to Platform Secondary Parity Error PCI PSTS.SSE Primary Parity Error Secondary SERR# PCICMD.SEE SERR# Correctable SERR# Fatal SERR# PCI Express Non-Fatal SERR# 5.3.2.4 Hot-Plug Each root port implements a Hot-Plug controller which performs the following: * Messages to turn on/off/blink LEDs * Presence and attention button detection * Interrupt generation The root port only allows Hot-Plug with modules (for example, ExpressCard*). Edgeconnector based Hot-Plug is not supported. 5.3.2.4.1 Presence Detection When a module is plugged in and power is supplied, the physical layer will detect the presence of the device, and the root port sets SLSTS.PDS (D28:F0/F1/F2/F3/F4/ F5:Offset 5Ah:Bit 6) and SLSTS.PDC (D28:F0/F1/F2/F3:Offset 6h:Bit 3). If SLCTL.PDE (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 58h:Bit 3) and SLCTL.HPE (D28:F0/F1/F2/F3/ F4/F5/F6/F7:Offset 58h:Bit 5) are both set, the root port will also generate an interrupt. 108 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description When a module is removed (using the physical layer detection), the root port clears SLSTS.PDS and sets SLSTS.PDC. If SLCTL.PDE and SLCTL.HPE are both set, the root port will also generate an interrupt. 5.3.2.4.2 Message Generation When system software writes to SLCTL.AIC (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 58h:Bits 7:6) or SLCTL.PIC (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 58h:Bits 9:8), the root port will send a message down the link to change the state of LEDs on the module. Writes to these fields are non-postable cycles, and the resulting message is a postable cycle. When receiving one of these writes, the root port performs the following: * Changes the state in the register. * Generates a completion into the upstream queue. * Formulates a message for the downstream port if the field is written to regardless of if the field changed. * Generates the message on the downstream port. * When the last message of a command is transmitted, sets SLSTS.CCE (D28:F0/F1/ F2/F3/F4/F5/F6/F7:Offset 58h:Bit 4) to indicate the command has completed. If SLCTL.CCE and SLCTL.HPE (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 58h:Bit 5) are set, the root port generates an interrupt. The command completed register (SLSTS.CC) applies only to commands issued by software to control the Attention Indicator (SLCTL.AIC), Power Indicator (SLCTL.PIC), or Power Controller (SLCTL.PCC). However, writes to other parts of the Slot Control Register would invariably end up writing to the indicators, power controller fields; Hence, any write to the Slot Control Register is considered a command and if enabled, will result in a command complete interrupt. The only exception to this rule is a write to disable the command complete interrupt which will not result in a command complete interrupt. A single write to the Slot Control register is considered to be a single command, and hence receives a single command complete, even if the write affects more than one field in the Slot Control Register. 5.3.2.4.3 Attention Button Detection When an attached device is ejected, an attention button could be pressed by the user. This attention button press will result in a the PCI Express* message "Attention_Button_Pressed" from the device. Upon receiving this message, the root port will set SLSTS.ABP (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 5Ah:Bit 0). If SLCTL.ABE (D28:F0/F1/F2/F3/F4/F5:Offset 58h:bit 0) and SLCTL.HPE (D28:F0/F1/ F2/F3/F4/F5/F6/F7:Offset 58h:Bit 5) are set, the Hot-Plug controller will also generate an interrupt. The interrupt is generated on an edge-event. For example, if SLSTS.ABP is already set, a new interrupt will not be generated. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 109 Functional Description 5.3.2.4.4 Intel(R) SMI/SCI Generation Interrupts for Hot-Plug events are not supported on legacy operating systems. To support Hot-Plug on non-PCI Express* aware operating systems, Hot-Plug events can be routed to generate SCI. To generate SCI, MPC.HPCE (D28:F0/F1/F2/F3/F4/F5/F6/ F7:Offset D8h:Bit 30) must be set. When set, enabled Hot-Plug events will cause SMSCS.HPCS (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset DCh:Bit 30) to be set. Additionally, BIOS workarounds for Hot-Plug can be supported by setting MPC.HPME (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset D8h:Bit 1). When this bit is set, Hot-Plug events can cause Intel SMI status bits in SMSCS to be set. Supported Hot-Plug events and their corresponding SMSCS bit are: * Command Completed - SCSCS.HPCCM (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset DCh:Bit 3) * Presence Detect Changed - SMSCS.HPPDM (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset DCh:Bit 1) * Attention Button Pressed - SMSCS.HPABM (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset DCh:Bit 2) * Link Active State Changed - SMSCS.HPLAS (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset DCh:Bit 4) When any of these bits are set, SMI# will be generated. These bits are set regardless of whether interrupts or SCI is enabled for Hot-Plug events. The SMI# may occur concurrently with an interrupt or SCI. 5.4 Gigabit Ethernet Controller (B0:D25:F0) The PCH integrates a Gigabit Ethernet (GbE) controller. The integrated GbE controller is compatible with the Intel(R) 82579 Platform LAN Connect device. The integrated GbE controller provides two interfaces for 10/100/1000 Mb/s and manageability operation: * Based on PCI Express* - A high-speed SerDes interface using PCI Express* electrical signaling at half speed while keeping the logical protocol for active state operation mode. * System Management Bus (SMBus) - A very low speed connection for low power state mode for manageability communication only. At this low power state mode the Ethernet link speed is reduced to 10 Mb/s. The Intel 82579 can be connected to any available downstream PCI Express* port in the PCH. The Intel 82579 Phy only runs at a speed of 1250 Mb/s, which is 1/2 of the gen1 2.5 Gb/s PCI Express* frequency. Each of the PCI Express* root ports in the PCH chipset have the ability to run at the 1250 Mb/s rate. There is no need to implement a mechanism to detect that the Intel 82579 LAN device is connected. The port configuration (if any), attached to the Intel 82579 LAN device, is pre-loaded from the SPI flash. The selected port adjusts the transmitter to run at the 1250 Mb/s rate and does not need to be PCI Express* compliant. Note: For more detailed information about Intel 82579 LAN Connect device, refer to Intel(R) 82579 Gigabit Ethernet PHY Datasheet. Note: PCIe validation tools cannot be used for electrical validation of this interface; however, PCIe layout rules apply for on-board routing. The integrated GbE controller operates at full-duplex at all supported speeds or halfduplex at 10/100 Mb/s. It also adheres to the IEEE 802.3x Flow Control Specification. Note: 110 GbE operation (1000 Mb/s) is only supported in S0 mode. In Sx modes, SMBus is the only active bus and is used to support manageability/remote wake-up functionality. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description The integrated GbE controller provides a system interface using a PCI Express* function. A full memory-mapped or I/O-mapped interface is provided to the software, along with DMA mechanisms for high performance data transfer. The integrated GbE controller features are: * Network Features -- Compliant with the 1 Gb/s Ethernet 802.3 802.3u 802.3ab specifications -- Multi-speed operation: 10/100/1000 Mb/s -- Full-duplex operation at 10/100/1000 Mb/s: Half-duplex at 10/100 Mb/s -- Flow control support compliant with the 802.3X specification -- VLAN support compliant with the 802.3q specification -- MAC address filters: perfect match unicast filters; multicast hash filtering, broadcast filter and promiscuous mode -- PCI Express/SMBus interface to GbE PHYs * Host Interface Features -- 64-bit address master support for systems using more than 4 GB of physical memory -- Programmable host memory receive buffers (256 Bytes to 16 KB) -- Intelligent interrupt generation features to enhance driver performance -- Descriptor ring management hardware for transmit and receive -- Software controlled reset (resets everything except the configuration space) -- Message Signaled Interrupts * Performance Features -- Configurable receive and transmit data FIFO, programmable in 1 KB increments -- TCP segmentation capability compatible with Windows NT* 5.x off loading features -- Fragmented UDP checksum offload for packet reassembly -- IPv4 and IPv6 checksum offload support (receive, transmit, and TCP segmentation offload) -- Split header support to eliminate payload copy from user space to host space -- Receive Side Scaling (RSS) with two hardware receive queues -- Supports 9018 bytes of jumbo packets -- Packet buffer size 32k bytes -- LinkSec offload compliant with 802.3ae specification -- TimeSync offload compliant with 802.1as specification * Intel Virtualization Technology Features (SRV/WS SKUs Only) -- Warm function reset - function level reset (FLR) -- VMDq1 * Power Management Features -- Magic Packet wake-up enable with unique MAC address -- ACPI register set and power down functionality supporting D0 and D3 states -- Full wake up support (APM, ACPI) -- MAC power down at Sx, DMoff with and without WoL Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 111 Functional Description 5.4.1 GbE PCI Express Bus Interface The GbE controller has a PCI Express* interface to the host processor and host memory. The following sections detail the bus transactions. 5.4.1.1 Transaction Layer The upper layer of the host architecture is the transaction layer. The transaction layer connects to the device core using an implementation specific protocol. Through this core-to-transaction-layer protocol, the application-specific parts of the device interact with the subsystem and transmit and receive requests to or from the remote agent, respectively. 5.4.1.2 Data Alignment 5.4.1.2.1 4-KB Boundary PCI requests must never specify an address/length combination that causes a memory space access to cross a 4 KB boundary. It is hardware's responsibility to break requests into 4 KB-aligned requests (if needed). This does not pose any requirement on software. However, if software allocates a buffer across a 4-KB boundary, hardware issues multiple requests for the buffer. Software should consider aligning buffers to 4 KB boundary in cases where it improves performance. The alignment to the 4-KB boundaries is done in the core. The transaction layer does not do any alignment according to these boundaries. 5.4.1.2.2 64 Bytes PCI requests are multiples of 64 bytes and aligned to make better use of memory controller resources. Writes, however, can be on any boundary and can cross a 64-byte alignment boundary. 5.4.1.3 Configuration Request Retry Status The integrated GbE controller might have a delay in initialization due to an NVM read. If the NVM configuration read operation is not completed and the device receives a configuration request, the device responds with a configuration request retry completion status to terminate the request, and thus effectively stalls the configuration request until such time that the sub-system has completed local initialization and is ready to communicate with the host. 112 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.4.2 Error Events and Error Reporting 5.4.2.1 Data Parity Error The PCI host bus does not provide parity protection, but it does forward parity errors from bridges. The integrated GbE controller recognizes parity errors through the internal bus interface and sets the Parity Error bit in PCI configuration space. If parity errors are enabled in configuration space, a system error is indicated on the PCI host bus. The offending cycle with a parity error is dropped and not processed by the integrated GbE controller. 5.4.2.2 Completion with Unsuccessful Completion Status A completion with unsuccessful completion status (any status other than 000) is dropped and not processed by the integrated GbE controller. Furthermore, the request that corresponds to the unsuccessful completion is not retried. When this unsuccessful completion status is received, the System Error bit in the PCI configuration space is set. If the system errors are enabled in configuration space, a system error is indicated on the PCI host bus. 5.4.3 Ethernet Interface The integrated GbE controller provides a complete CSMA/CD function supporting IEEE 802.3 (10 Mb/s), 802.3u (100 Mb/s) implementations. It also supports the IEEE 802.3z and 802.3ab (1000 Mb/s) implementations. The device performs all of the functions required for transmission, reception, and collision handling called out in the standards. The mode used to communicate between the PCH and the Intel 82579 PHY supports 10/100/1000 Mb/s operation, with both half- and full-duplex operation at 10/100 Mb/s, and full-duplex operation at 1000 Mb/s. 5.4.3.1 Intel(R) 82579 LAN PHY Interface The integrated GbE controller and the Intel 82579 PHY communicate through the PCIe and SMBus interfaces. All integrated GbE controller configuration is performed using device control registers mapped into system memory or I/O space. The Intel 82579 device is configured using the PCI Express* or SMBus interface. The integrated GbE controller supports various modes as listed in Table 5-8. Table 5-8. LAN Mode Support Mode System State Interface Active Connections Normal 10/100/1000 Mb/s S0 PCI Express* or SMBus1 Intel 82579 Manageability and Remote Wake-up Sx SMBus Intel 82579 1. GbE operation is not supported in Sx states. 5.4.4 PCI Power Management The integrated GbE controller supports the Advanced Configuration and Power Interface (ACPI) specification as well as Advanced Power Management (APM). This enables the network-related activity (using an internal host wake signal) to wake up the host. For example, from Sx (S3-S5) to S0. The integrated GbE controller contains power management registers for PCI and supports D0 and D3 states. PCIe transactions are only allowed in the D0 state, except for host accesses to the integrated GbE controller's PCI configuration registers. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 113 Functional Description 5.4.4.1 Wake Up The integrated GbE controller supports two types of wake-up mechanisms: 1. Advanced Power Management (APM) Wake Up 2. ACPI Power Management Wake Up Both mechanisms use an internal logic signal to wake the system up. The wake-up steps are as follows: 1. Host wake event occurs (note that packet is not delivered to host). 2. The Intel 82579 receives a WoL packet/link status change. 3. The Intel 82579 wakes up the integrated GbE controller using an SMBus message. 4. The integrated GbE controller sets the PME_STATUS bit. 5. System wakes from Sx state to S0 state. 6. The host LAN function is transitioned to D0. 7. The host clears the PME_STATUS bit. 5.4.4.1.1 Advanced Power Management Wake Up Advanced Power Management Wake Up or APM Wake Up was previously known as Wake on LAN (WoL). It is a feature that has existed in the 10/100 Mb/s NICs for several generations. The basic premise is to receive a broadcast or unicast packet with an explicit data pattern and then to assert a signal to wake up the system. In earlier generations, this was accomplished by using a special signal that ran across a cable to a defined connector on the motherboard. The NIC would assert the signal for approximately 50 ms to signal a wake up. The integrated GbE controller uses (if configured to) an in-band PM_PME message for this. At power up, the integrated GbE controller reads the APM Enable bits from the NVM PCI Init Control Word into the APM Enable (APME) bits of the Wake Up Control (WUC) register. These bits control enabling of APM wake up. When APM wake up is enabled, the integrated GbE controller checks all incoming packets for Magic Packets. Once the integrated GbE controller receives a matching Magic Packet, it: * Sets the Magic Packet Received bit in the Wake Up Status (WUS) register. * Sets the PME_Status bit in the Power Management Control/Status Register (PMCSR). APM wake up is supported in all power states and only disabled if a subsequent NVM read results in the APM Wake Up bit being cleared or the software explicitly writes a 0b to the APM Wake Up (APM) bit of the WUC register. Note: APM wake up settings will be restored to NVM default by the PCH when LAN connected Device (PHY) power is turned off and subsequently restored. Some example host WOL flows are: * When system transitions to G3 after WOL is disabled from the BIOS, APM host WOL would get enabled. * Anytime power to the LAN Connected Device (PHY) is cycled while in S4/S5 after WOL is disabled from the BIOS, APM host WOL would get enabled. Anytime power to the LAN Connected Device (PHY) is cycled while in S3, APM host WOL configuration is lost. 114 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.4.4.1.2 ACPI Power Management Wake Up The integrated GbE controller supports ACPI Power Management based Wake ups. It can generate system wake-up events from three sources: * Receiving a Magic Packet. * Receiving a Network Wake Up Packet. * Detecting a link change of state. Activating ACPI Power Management Wakeup requires the following steps: * The software device driver programs the Wake Up Filter Control (WUFC) register to indicate the packets it needs to wake up from and supplies the necessary data to the IPv4 Address Table (IP4AT) and the Flexible Filter Mask Table (FFMT), Flexible Filter Length Table (FFLT), and the Flexible Filter Value Table (FFVT). It can also set the Link Status Change Wake Up Enable (LNKC) bit in the Wake Up Filter Control (WUFC) register to cause wake up when the link changes state. * The operating system (at configuration time) writes a 1b to the PME_EN bit of the Power Management Control/Status Register (PMCSR.8). Normally, after enabling wake up, the operating system writes a 11b to the lower two bits of the PMCSR to put the integrated GbE controller into low-power mode. Once wake up is enabled, the integrated GbE controller monitors incoming packets, first filtering them according to its standard address filtering method, then filtering them with all of the enabled wake-up filters. If a packet passes both the standard address filtering and at least one of the enabled wake-up filters, the integrated GbE controller: * Sets the PME_Status bit in the PMCSR * Sets one or more of the Received bits in the Wake Up Status (WUS) register. (More than one bit is set if a packet matches more than one filter.) If enabled, a link state change wake up causes similar results, setting the Link Status Changed (LNKC) bit in the Wake Up Status (WUS) register when the link goes up or down. After receiving a wake-up packet, the integrated GbE controller ignores any subsequent wake-up packets until the software device driver clears all of the Received bits in the Wake Up Status (WUS) register. It also ignores link change events until the software device driver clears the Link Status Changed (LNKC) bit in the Wake Up Status (WUS) register. Note: ACPI wake up settings are not preserved when the LAN Connected Device (PHY) power is turned off and subsequently restored. Some example host WOL flows are: * Anytime power to the LAN Connected Device (PHY) is cycled while in S3 or S4, ACPI host WOL configuration is lost. 5.4.5 Configurable LEDs The integrated GbE controller supports three controllable and configurable LEDs that are driven from the Intel 82579 LAN device. Each of the three LED outputs can be individually configured to select the particular event, state, or activity, which is indicated on that output. In addition, each LED can be individually configured for output polarity as well as for blinking versus non-blinking (steady-state) indication. The configuration for LED outputs is specified using the LEDCTL register. Furthermore, the hardware-default configuration for all the LED outputs, can be specified using NVM fields, thereby supporting LED displays configurable to a particular OEM preference. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 115 Functional Description Each of the three LEDs might be configured to use one of a variety of sources for output indication. The MODE bits control the LED source: * * * * * * * * * * * * LINK_100/1000 is asserted when link is established at either 100 or 1000 Mb/s. LINK_10/1000 is asserted when link is established at either 10 or 1000 Mb/s. LINK_UP is asserted when any speed link is established and maintained. ACTIVITY is asserted when link is established and packets are being transmitted or received. LINK/ACTIVITY is asserted when link is established AND there is NO transmit or receive activity. LINK_10 is asserted when a 10 Mb/ps link is established and maintained. LINK_100 is asserted when a 100 Mb/s link is established and maintained. LINK_1000 is asserted when a 1000 Mb/s link is established and maintained. FULL_DUPLEX is asserted when the link is configured for full duplex operation. COLLISION is asserted when a collision is observed. PAUSED is asserted when the device's transmitter is flow controlled. LED_ON is always asserted; LED_OFF is always deasserted. The IVRT bits enable the LED source to be inverted before being output or observed by the blink-control logic. LED outputs are assumed to normally be connected to the negative side (cathode) of an external LED. The BLINK bits control whether the LED should be blinked while the LED source is asserted, and the blinking frequency (either 200 ms on and 200 ms off or 83 ms on and 83 ms off). The blink control can be especially useful for ensuring that certain events, such as ACTIVITY indication, cause LED transitions, which are sufficiently visible to a human eye. The same blinking rate is shared by all LEDs. 5.4.6 Function Level Reset Support (FLR) (SRV/WS SKUs Only) The integrated GbE controller supports FLR capability. FLR capability can be used in conjunction with Intel Virtualization Technology. FLR allows an operating system in a Virtual Machine to have complete control over a device, including its initialization, without interfering with the rest of the platform. The device provides a software interface that enables the operating system to reset the entire device as if a PCI reset was asserted. 5.4.6.1 FLR Steps 5.4.6.1.1 FLR Initialization 1. FLR is initiated by software by writing a 1b to the Initiate FLR bit. 2. All subsequent requests targeting the function is not claimed and will be master abort immediate on the bus. This includes any configuration, I/O or memory cycles, however, the function must continue to accept completions targeting the function. 5.4.6.1.2 FLR Operation Function resets all configuration, I/O and memory registers of the function except those indicated otherwise and resets all internal states of the function to the default or initial condition. 5.4.6.1.3 FLR Completion The Initiate FLR bit is reset (cleared) when the FLR reset completes. This bit can be used to indicate to the software that the FLR reset completed. Note: 116 From the time the Initiate FLR bit is written to 1b, software must wait at least 100 ms before accessing the function. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.5 LPC Bridge (with System and Management Functions) (D31:F0) The LPC bridge function of the PCH resides in PCI Device 31:Function 0. In addition to the LPC bridge function, D31:F0 contains other functional units including DMA, Interrupt controllers, Timers, Power Management, System Management, GPIO, and RTC. In this chapter, registers and functions associated with other functional units (power management, GPIO, USB, and so forth) are described in their respective sections. Note: The LPC bridge cannot be configured as a subtractive decode agent. 5.5.1 LPC Interface The PCH implements an LPC interface as described in the Low Pin Count Interface Specification, Revision 1.1. The LPC interface to the PCH is shown in Figure 5-4. Note that the PCH implements all of the signals that are shown as optional, but peripherals are not required to do so. Figure 5-4. LPC Interface Diagram PCI Bus PCI CLK PCI RST# PCI SERIRQ PCI PME# LAD [3:0] PCH LFRAME# LDRQ[1:0]# (Optional) GPI LPC Device LSMI# (Optional) Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 117 Functional Description 5.5.1.1 LPC Cycle Types The PCH implements all of the cycle types described in the Low Pin Count Interface Specification, Revision 1.1. Table 5-9 shows the cycle types supported by the PCH. Table 5-9. LPC Cycle Types Supported Cycle Type Comment Memory Read 1 byte only. (See Note 1 below) Memory Write 1 byte only. (See Note 1 below) I/O Read 1 byte only. The PCH breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. I/O Write 1 byte only. The PCH breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. DMA Read Can be 1, or 2 bytes DMA Write Can be 1, or 2 bytes Bus Master Read Can be 1, 2, or 4 bytes. (See Note 2 below) Bus Master Write Can be 1, 2, or 4 bytes. (See Note 2 below) Notes: 1. The PCH provides a single generic memory range (LGMR) for decoding memory cycles and forwarding them as LPC Memory cycles on the LPC bus. The LGMR memory decode range is 64 KB in size and can be defined as being anywhere in the 4 GB memory space. This range needs to be configured by BIOS during POST to provide the necessary memory resources. BIOS should advertise the LPC Generic Memory Range as Reserved to the OS in order to avoid resource conflict. For larger transfers, the PCH performs multiple 8-bit transfers. If the cycle is not claimed by any peripheral, it is subsequently aborted, and the PCH returns a value of all 1s to the processor. This is done to maintain compatibility with ISA memory cycles where pull-up resistors would keep the bus high if no device responds. 2. Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer can be to any address. However, the 2-byte transfer must be word-aligned (that is, with an address where A0=0). A DWord transfer must be DWord-aligned (that is, with an address where A1 and A0 are both 0). 5.5.1.2 Start Field Definition Table 5-10. Start Field Bit Definitions Bits[3:0] Encoding 0000 Start of cycle for a generic target 0010 Grant for bus master 0 0011 Grant for bus master 1 1111 Stop/Abort: End of a cycle for a target. Note: 118 Definition All other encodings are RESERVED. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.5.1.3 Cycle Type / Direction (CYCTYPE + DIR) The PCH always drives Bit 0 of this field to 0. Peripherals running bus master cycles must also drive Bit 0 to 0. Table 5-11 shows the valid bit encodings. Table 5-11. Cycle Type Bit Definitions Bits[3:2] 5.5.1.4 Bit1 Definition 00 0 I/O Read 00 1 I/O Write 01 0 Memory Read 01 1 Memory Read 10 0 DMA Read 10 1 DMA Write 11 x Reserved. If a peripheral performing a bus master cycle generates this value, the PCH aborts the cycle. Size Bits[3:2] are reserved. The PCH always drives them to 00. Peripherals running bus master cycles are also supposed to drive 00 for Bits 3:2; however, the PCH ignores those bits. Bits[1:0] are encoded as listed in Table 5-12. Table 5-12. Transfer Size Bit Definition Bits[1:0] 00 5.5.1.5 Size 8-bit transfer (1 byte) 01 16-bit transfer (2 bytes) 10 Reserved. The PCH never drives this combination. If a peripheral running a bus master cycle drives this combination, the PCH may abort the transfer. 11 32-bit transfer (4 bytes) SYNC Valid values for the SYNC field are shown in Table 5-13. Table 5-13. SYNC Bit Definition Bits[3:0] Indication 0000 Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA request deassertion and no more transfers desired for that channel. 0101 Short Wait: Part indicating wait-states. For bus master cycles, the PCH does not use this encoding. Instead, the PCH uses the Long Wait encoding (see next encoding below). 0110 Long Wait: Part indicating wait-states, and many wait-states will be added. This encoding driven by the PCH for bus master cycles, rather than the Short Wait (0101). 1001 Ready More (Used only by peripheral for DMA cycle): SYNC achieved with no error and more DMA transfers desired to continue after this transfer. This value is valid only on DMA transfers and is not allowed for any other type of cycle. 1010 Error: Sync achieved with error. This is generally used to replace the SERR# or IOCHK# signal on the PCI/ISA bus. It indicates that the data is to be transferred, but there is a serious error in this transfer. For DMA transfers, this not only indicates an error, but also indicates DMA request deassertion and no more transfers desired for that channel. Notes: 1. All other combinations are RESERVED. 2. If the LPC controller receives any SYNC returned from the device other than short (0101), long wait (0110), or ready (0000) when running a FWH cycle, indeterminate results may occur. A FWH device is not allowed to assert an Error SYNC. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 119 Functional Description 5.5.1.6 SYNC Time-Out There are several error cases that can occur on the LPC interface. The PCH responds as defined in section 4.2.1.9 of the Low Pin Count Interface Specification, Revision 1.1 to the stimuli described therein. There may be other peripheral failure conditions; however, these are not handled by the PCH. 5.5.1.7 SYNC Error Indication The PCH responds as defined in section 4.2.1.10 of the Low Pin Count Interface Specification, Revision 1.1. Upon recognizing the SYNC field indicating an error, the PCH treats this as a SERR by reporting this into the Device 31 Error Reporting Logic. 5.5.1.8 LFRAME# Usage The PCH follows the usage of LFRAME# as defined in the Low Pin Count Interface Specification, Revision 1.1. The PCH performs an abort for the following cases (possible failure cases): * The PCH starts a Memory, I/O, or DMA cycle, but no device drives a valid SYNC after four consecutive clocks. * The PCH starts a Memory, I/O, or DMA cycle, and the peripheral drives an invalid SYNC pattern. * A peripheral drives an illegal address when performing bus master cycles. * A peripheral drives an invalid value. 5.5.1.9 I/O Cycles For I/O cycles targeting registers specified in the PCH's decode ranges, the PCH performs I/O cycles as defined in the Low Pin Count Interface Specification, Revision 1.1. These are 8-bit transfers. If the processor attempts a 16-bit or 32-bit transfer, the PCH breaks the cycle up into multiple 8-bit transfers to consecutive I/O addresses. Note: If the cycle is not claimed by any peripheral (and subsequently aborted), the PCH returns a value of all 1s (FFh) to the processor. This is to maintain compatibility with ISA I/O cycles where pull-up resistors would keep the bus high if no device responds. 5.5.1.10 Bus Master Cycles The PCH supports Bus Master cycles and requests (using LDRQ#) as defined in the Low Pin Count Interface Specification, Revision 1.1. The PCH has two LDRQ# inputs, and thus supports two separate bus master devices. It uses the associated START fields for Bus Master 0 (0010b) or Bus Master 1 (0011b). Note: 120 The PCH does not support LPC Bus Masters performing I/O cycles. LPC Bus Masters should only perform memory read or memory write cycles. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.5.1.11 Configuration and PCH Implications LPC I/F Decoders To allow the I/O cycles and memory mapped cycles to go to the LPC interface, the PCH includes several decoders. During configuration, the PCH must be programmed with the same decode ranges as the peripheral. The decoders are programmed using the Device 31:Function 0 configuration space. Note: The PCH cannot accept PCI write cycles from PCI-to-PCI bridges or devices with similar characteristics (specifically those with a "Retry Read" feature which is enabled) to an LPC device if there is an outstanding LPC read cycle towards the same PCI device or bridge. These cycles are not part of normal system operation, but may be encountered as part of platform validation testing using custom test fixtures. Bus Master Device Mapping and START Fields Bus Masters must have a unique START field. In the case of the PCH that supports two LPC bus masters, it drives 0010 for the START field for grants to Bus Master 0 (requested using LDRQ0#) and 0011 for grants to Bus Master 1 (requested using LDRQ1#.). Thus, no registers are needed to configure the START fields for a particular bus master. 5.6 DMA Operation (D31:F0) The PCH supports LPC DMA using the PCH's DMA controller. The DMA controller has registers that are fixed in the lower 64 KB of I/O space. The DMA controller is configured using registers in the PCI configuration space. These registers allow configuration of the channels for use by LPC DMA. The DMA circuitry incorporates the functionality of two 8237 DMA controllers with seven independently programmable channels (Figure 5-5). DMA Controller 1 (DMA-1) corresponds to DMA Channels 0-3 and DMA Controller 2 (DMA-2) corresponds to Channels 5-7. DMA Channel 4 is used to cascade the two controllers and defaults to cascade mode in the DMA Channel Mode (DCM) Register. Channel 4 is not available for any other purpose. In addition to accepting requests from DMA slaves, the DMA controller also responds to requests that software initiates. Software may initiate a DMA service request by setting any bit in the DMA Channel Request Register to a 1. Figure 5-5. PCH DMA Controller Channel 4 Channel 0 Channel 1 Channel 5 DMA-1 Channel 2 Channel 6 Channel 3 Channel 7 DMA-2 Each DMA channel is hardwired to the compatible settings for DMA device size: Channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and Channels [7:5] are hardwired to 16-bit, count-by-words (address shifted) transfers. The PCH provides 24-bit addressing in compliance with the ISA-Compatible specification. Each channel includes a 16-bit ISA-Compatible Current Register which holds the 16 least-significant bits of the 24-bit address, an ISA-Compatible Page Register which contains the eight next most significant bits of address. The DMA controller also features refresh address generation, and auto-initialization following a DMA termination. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 121 Functional Description 5.6.1 Channel Priority For priority resolution, the DMA consists of two logical channel groups: Channels 0-3 and Channels 4-7. Each group may be in either fixed or rotate mode, as determined by the DMA Command Register. DMA I/O slaves normally assert their DREQ line to arbitrate for DMA service. However, a software request for DMA service can be presented through each channel's DMA Request Register. A software request is subject to the same prioritization as any hardware request. See the detailed register description for Request Register programming information in Section 13.2. 5.6.1.1 Fixed Priority The initial fixed priority structure is as follows: High priority Low priority 0, 1, 2, 3 5, 6, 7 The fixed priority ordering is 0, 1, 2, 3, 5, 6, and 7. In this scheme, channel 0 has the highest priority, and Channel 7 has the lowest priority. Channels [3:0] of DMA-1 assume the priority position of Channel 4 in DMA-2, thus taking priority over Channels 5, 6, and 7. 5.6.1.2 Rotating Priority Rotation allows for "fairness" in priority resolution. The priority chain rotates so that the last channel serviced is assigned the lowest priority in the channel group (0-3, 5-7). Channels 0-3 rotate as a group of 4. They are always placed between Channel 5 and Channel 7 in the priority list. Channel 5-7 rotate as part of a group of 4. That is, Channels (5-7) form the first three positions in the rotation, while Channel Group (0-3) comprises the fourth position in the arbitration. 5.6.2 Address Compatibility Mode When the DMA is operating, the addresses do not increment or decrement through the High and Low Page Registers. Therefore, if a 24-bit address is 01FFFFh and increments, the next address is 010000h, not 020000h. Similarly, if a 24-bit address is 020000h and decrements, the next address is 02FFFFh, not 01FFFFh. However, when the DMA is operating in 16-bit mode, the addresses still do not increment or decrement through the High and Low Page Registers but the page boundary is now 128 K. Therefore, if a 24-bit address is 01FFFEh and increments, the next address is 000000h, not 0100000h. Similarly, if a 24-bit address is 020000h and decrements, the next address is 03FFFEh, not 02FFFEh. This is compatible with the 8237 and Page Register implementation used in the PC-AT. This mode is set after CPURST is valid. 5.6.3 Summary of DMA Transfer Sizes Table 5-14 lists each of the DMA device transfer sizes. The column labeled "Current Byte/Word Count Register" indicates that the register contents represents either the number of bytes to transfer or the number of 16-bit words to transfer. The column labeled "Current Address Increment/Decrement" indicates the number added to or taken from the Current Address register after each DMA transfer cycle. The DMA Channel Mode Register determines if the Current Address Register will be incremented or decremented. 122 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.6.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words Table 5-14. DMA Transfer Size Current Byte/Word Count Register Current Address Increment/Decrement 8-Bit I/O, Count By Bytes Bytes 1 16-Bit I/O, Count By Words (Address Shifted) Words 1 DMA Device Date Size And Word Count The PCH maintains compatibility with the implementation of the DMA in the PC AT that used the 8237. The DMA shifts the addresses for transfers to/from a 16-bit device count-by-words. Note: The least significant bit of the Low Page Register is dropped in 16-bit shifted mode. When programming the Current Address Register (when the DMA channel is in this mode), the Current Address must be programmed to an even address with the address value shifted right by one bit. The address shifting is shown in Table 5-15. Table 5-15. Address Shifting in 16-Bit I/O DMA Transfers Note: 5.6.4 Output Address 8-Bit I/O Programmed Address (Ch 0-3) 16-Bit I/O Programmed Address (Ch 5-7) (Shifted) A0 A[16:1] A[23:17] A0 A[16:1] A[23:17] 0 A[15:0] A[23:17] The least significant bit of the Page Register is dropped in 16-bit shifted mode. Autoinitialize By programming a bit in the DMA Channel Mode Register, a channel may be set up as an autoinitialize channel. When a channel undergoes autoinitialization, the original values of the Current Page, Current Address and Current Byte/Word Count Registers are automatically restored from the Base Page, Address, and Byte/Word Count Registers of that channel following TC. The Base Registers are loaded simultaneously with the Current Registers by the microprocessor when the DMA channel is programmed and remain unchanged throughout the DMA service. The mask bit is not set when the channel is in autoinitialize. Following autoinitialize, the channel is ready to perform another DMA service, without processor intervention, as soon as a valid DREQ is detected. 5.6.5 Software Commands There are three additional special software commands that the DMA controller can execute. The three software commands are: * Clear Byte Pointer Flip-Flop * Master Clear * Clear Mask Register They do not depend on any specific bit pattern on the data bus. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 123 Functional Description 5.7 LPC DMA DMA on LPC is handled through the use of the LDRQ# lines from peripherals and special encodings on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported on the LPC interface. Channels 0-3 are 8-bit channels. Channels 5-7 are 16-bit channels. Channel 4 is reserved as a generic bus master request. 5.7.1 Asserting DMA Requests Peripherals that need DMA service encode their requested channel number on the LDRQ# signal. To simplify the protocol, each peripheral on the LPC I/F has its own dedicated LDRQ# signal (they may not be shared between two separate peripherals). The PCH has two LDRQ# inputs, allowing at least two devices to support DMA or bus mastering. LDRQ# is synchronous with LCLK (PCI clock). As shown in Figure 5-6, the peripheral uses the following serial encoding sequence: * Peripheral starts the sequence by asserting LDRQ# low (start bit). LDRQ# is high during idle conditions. * The next three bits contain the encoded DMA channel number (MSB first). * The next bit (ACT) indicates whether the request for the indicated DMA channel is active or inactive. The ACT bit is 1 (high) to indicate if it is active and 0 (low) if it is inactive. The case where ACT is low is rare, and is only used to indicate that a previous request for that channel is being abandoned. * After the active/inactive indication, the LDRQ# signal must go high for at least 1 clock. After that one clock, LDRQ# signal can be brought low to the next encoding sequence. If another DMA channel also needs to request a transfer, another sequence can be sent on LDRQ#. For example, if an encoded request is sent for Channel 2, and then Channel 3 needs a transfer before the cycle for Channel 2 is run on the interface, the peripheral can send the encoded request for Channel 3. This allows multiple DMA agents behind an I/O device to request use of the LPC interface, and the I/O device does not need to self-arbitrate before sending the message. Figure 5-6. DMA Request Assertion through LDRQ# LCLK LDRQ# 5.7.2 Start MSB LSB ACT Start Abandoning DMA Requests DMA Requests can be deasserted in two fashions: on error conditions by sending an LDRQ# message with the `ACT' bit set to 0, or normally through a SYNC field during the DMA transfer. This section describes boundary conditions where the DMA request needs to be removed prior to a data transfer. There may be some special cases where the peripheral desires to abandon a DMA transfer. The most likely case of this occurring is due to a floppy disk controller which has overrun or underrun its FIFO, or software stopping a device prematurely. 124 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description In these cases, the peripheral wishes to stop further DMA activity. It may do so by sending an LDRQ# message with the ACT bit as 0. However, since the DMA request was seen by the PCH, there is no assurance that the cycle has not been granted and will shortly run on LPC. Therefore, peripherals must take into account that a DMA cycle may still occur. The peripheral can choose not to respond to this cycle, in which case the host will abort it, or it can choose to complete the cycle normally with any random data. This method of DMA deassertion should be prevented whenever possible, to limit boundary conditions both on the PCH and the peripheral. 5.7.3 General Flow of DMA Transfers Arbitration for DMA channels is performed through the 8237 within the host. Once the host has won arbitration on behalf of a DMA channel assigned to LPC, it asserts LFRAME# on the LPC I/F and begins the DMA transfer. The general flow for a basic DMA transfer is as follows: 1. The PCH starts transfer by asserting 0000b on LAD[3:0] with LFRAME# asserted. 2. The PCH asserts `cycle type' of DMA, direction based on DMA transfer direction. 3. The PCH asserts channel number and, if applicable, terminal count. 4. The PCH indicates the size of the transfer: 8 or 16 bits. 5. If a DMA read... -- The PCH drives the first 8 bits of data and turns the bus around. -- The peripheral acknowledges the data with a valid SYNC. -- If a 16-bit transfer, the process is repeated for the next 8 bits. 6. If a DMA write: -- The PCH turns the bus around and waits for data. -- The peripheral indicates data ready through SYNC and transfers the first byte. -- If a 16-bit transfer, the peripheral indicates data ready and transfers the next byte. 7. The peripheral turns around the bus. 5.7.4 Terminal Count Terminal count is communicated through LAD[3] on the same clock that DMA channel is communicated on LAD[2:0]. This field is the CHANNEL field. Terminal count indicates the last byte of transfer, based upon the size of the transfer. For example, on an 8-bit transfer size (SIZE field is 00b), if the TC bit is set, then this is the last byte. On a 16-bit transfer (SIZE field is 01b), if the TC bit is set, then the second byte is the last byte. The peripheral, therefore, must internalize the TC bit when the CHANNEL field is communicated, and only signal TC when the last byte of that transfer size has been transferred. 5.7.5 Verify Mode Verify mode is supported on the LPC interface. A verify transfer to the peripheral is similar to a DMA write, where the peripheral is transferring data to main memory. The indication from the host is the same as a DMA write, so the peripheral will be driving data onto the LPC interface. However, the host will not transfer this data into main memory. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 125 Functional Description 5.7.6 DMA Request Deassertion An end of transfer is communicated to the PCH through a special SYNC field transmitted by the peripheral. An LPC device must not attempt to signal the end of a transfer by deasserting LDREQ#. If a DMA transfer is several bytes (for example, a transfer from a demand mode device) the PCH needs to know when to deassert the DMA request based on the data currently being transferred. The DMA agent uses a SYNC encoding on each byte of data being transferred, which indicates to the PCH whether this is the last byte of transfer or if more bytes are requested. To indicate the last byte of transfer, the peripheral uses a SYNC value of 0000b (ready with no error), or 1010b (ready with error). These encodings tell the PCH that this is the last piece of data transferred on a DMA read (PCH to peripheral), or the byte that follows is the last piece of data transferred on a DMA write (peripheral to the PCH). When the PCH sees one of these two encodings, it ends the DMA transfer after this byte and deasserts the DMA request to the 8237. Therefore, if the PCH indicated a 16-bit transfer, the peripheral can end the transfer after one byte by indicating a SYNC value of 0000b or 1010b. The PCH does not attempt to transfer the second byte, and deasserts the DMA request internally. If the peripheral indicates a 0000b or 1010b SYNC pattern on the last byte of the indicated size, then the PCH only deasserts the DMA request to the 8237 since it does not need to end the transfer. If the peripheral wishes to keep the DMA request active, then it uses a SYNC value of 1001b (ready plus more data). This tells the 8237 that more data bytes are requested after the current byte has been transferred, so the PCH keeps the DMA request active to the 8237. Therefore, on an 8-bit transfer size, if the peripheral indicates a SYNC value of 1001b to the PCH, the data will be transferred and the DMA request will remain active to the 8237. At a later time, the PCH will then come back with another START- CYCTYPE-CHANNEL-SIZE, and so forth, combination to initiate another transfer to the peripheral. The peripheral must not assume that the next START indication from the PCH is another grant to the peripheral if it had indicated a SYNC value of 1001b. On a single mode DMA device, the 8237 will re-arbitrate after every transfer. Only demand mode DMA devices can be assured that they will receive the next START indication from the PCH. Note: Indicating a 0000b or 1010b encoding on the SYNC field of an odd byte of a 16-bit channel (first byte of a 16-bit transfer) is an error condition. Note: The host stops the transfer on the LPC bus as indicated, fills the upper byte with random data on DMA writes (peripheral to memory), and indicates to the 8237 that the DMA transfer occurred, incrementing the 8237's address and decrementing its byte count. 5.7.7 SYNC Field / LDRQ# Rules Since DMA transfers on LPC are requested through an LDRQ# assertion message, and are ended through a SYNC field during the DMA transfer, the peripheral must obey the following rule when initiating back-to-back transfers from a DMA channel. The peripheral must not assert another message for eight LCLKs after a deassertion is indicated through the SYNC field. This is needed to allow the 8237, that typically runs off a much slower internal clock, to see a message deasserted before it is re-asserted so that it can arbitrate to the next agent. Under default operation, the host only performs 8-bit transfers on 8-bit channels and 16-bit transfers on 16-bit channels. 126 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description The method by which this communication between host and peripheral through system BIOS is performed is beyond the scope of this specification. Since the LPC host and LPC peripheral are motherboard devices, no "plug-n-play" registry is required. The peripheral must not assume that the host is able to perform transfer sizes that are larger than the size allowed for the DMA channel, and be willing to accept a SIZE field that is smaller than what it may currently have buffered. To that end, it is recommended that future devices that may appear on the LPC bus, that require higher bandwidth than 8-bit or 16-bit DMA allow, do so with a bus mastering interface and not rely on the 8237. 5.8 8254 Timers (D31:F0) The PCH contains three counters that have fixed uses. All registers and functions associated with the 8254 timers are in the core well. The 8254 unit is clocked by a 14.31818 MHz clock. Counter 0, System Timer This counter functions as the system timer by controlling the state of IRQ0 and is typically programmed for Mode 3 operation. The counter produces a square wave with a period equal to the product of the counter period (838 ns) and the initial count value. The counter loads the initial count value 1 counter period after software writes the count value to the counter I/O address. The counter initially asserts IRQ0 and decrements the count value by two each counter period. The counter negates IRQ0 when the count value reaches 0. It then reloads the initial count value and again decrements the initial count value by two each counter period. The counter then asserts IRQ0 when the count value reaches 0, reloads the initial count value, and repeats the cycle, alternately asserting and negating IRQ0. Counter 1, Refresh Request Signal This counter provides the refresh request signal and is typically programmed for Mode 2 operation and only impacts the period of the REF_TOGGLE bit in Port 61. The initial count value is loaded one counter period after being written to the counter I/O address. The REF_TOGGLE bit will have a square wave behavior (alternate between 0 and 1) and will toggle at a rate based on the value in the counter. Programming the counter to anything other than Mode 2 will result in undefined behavior for the REF_TOGGLE bit. Counter 2, Speaker Tone This counter provides the speaker tone and is typically programmed for Mode 3 operation. The counter provides a speaker frequency equal to the counter clock frequency (1.193 MHz) divided by the initial count value. The speaker must be enabled by a write to port 061h (see NMI Status and Control ports). 5.8.1 Timer Programming The counter/timers are programmed in the following fashion: 1. Write a control word to select a counter. 2. Write an initial count for that counter. 3. Load the least and/or most significant bytes (as required by Control Word Bits 5, 4) of the 16-bit counter. 4. Repeat with other counters. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 127 Functional Description Only two conventions need to be observed when programming the counters. First, for each counter, the control word must be written before the initial count is written. Second, the initial count must follow the count format specified in the control word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). A new initial count may be written to a counter at any time without affecting the counter's programmed mode. Counting is affected as described in the mode definitions. The new count must follow the programmed count format. If a counter is programmed to read/write two-byte counts, the following precaution applies: A program must not transfer control between writing the first and second byte to another routine which also writes into that same counter. Otherwise, the counter will be loaded with an incorrect count. The Control Word Register at port 43h controls the operation of all three counters. Several commands are available: * Control Word Command. Specifies which counter to read or write, the operating mode, and the count format (binary or BCD). * Counter Latch Command. Latches the current count so that it can be read by the system. The countdown process continues. * Read Back Command. Reads the count value, programmed mode, the current state of the OUT pins, and the state of the Null Count Flag of the selected counter. Table 5-16 lists the six operating modes for the interval counters. Table 5-16. Counter Operating Modes Mode 5.8.2 Function Description 0 Out signal on end of count (=0) Output is 0. When count goes to 0, output goes to 1 and stays at 1 until counter is reprogrammed. 1 Hardware retriggerable one-shot Output is 0. When count goes to 0, output goes to 1 for one clock time. 2 Rate generator (divide by n counter) Output is 1. Output goes to 0 for one clock time, then back to 1 and counter is reloaded. 3 Square wave output Output is 1. Output goes to 0 when counter rolls over, and counter is reloaded. Output goes to 1 when counter rolls over, and counter is reloaded, and so forth. 4 Software triggered strobe Output is 1. Output goes to 0 when count expires for one clock time. 5 Hardware triggered strobe Output is 1. Output goes to 0 when count expires for one clock time. Reading from the Interval Timer It is often desirable to read the value of a counter without disturbing the count in progress. There are three methods for reading the counters: a simple read operation, counter Latch command, and the Read-Back command. Each is explained below. With the simple read and counter latch command methods, the count must be read according to the programmed format; specifically, if the counter is programmed for two byte counts, two bytes must be read. The two bytes do not have to be read one right after the other. Read, write, or programming operations for other counters may be inserted between them. 128 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.8.2.1 Simple Read The first method is to perform a simple read operation. The counter is selected through port 40h (Counter 0), 41h (Counter 1), or 42h (Counter 2). Note: Performing a direct read from the counter does not return a determinate value, because the counting process is asynchronous to read operations. However, in the case of Counter 2, the count can be stopped by writing to the GATE bit in Port 61h. 5.8.2.2 Counter Latch Command The Counter Latch command, written to Port 43h, latches the count of a specific counter at the time the command is received. This command is used to ensure that the count read from the counter is accurate, particularly when reading a two-byte count. The count value is then read from each counter's Count register as was programmed by the Control register. The count is held in the latch until it is read or the counter is reprogrammed. The count is then unlatched. This allows reading the contents of the counters on the fly without affecting counting in progress. Multiple Counter Latch Commands may be used to latch more than one counter. Counter Latch commands do not affect the programmed mode of the counter in any way. If a Counter is latched and then, some time later, latched again before the count is read, the second Counter Latch command is ignored. The count read is the count at the time the first Counter Latch command was issued. 5.8.2.3 Read Back Command The Read Back command, written to Port 43h, latches the count value, programmed mode, and current states of the OUT pin and Null Count flag of the selected counter or counters. The value of the counter and its status may then be read by I/O access to the counter address. The Read Back command may be used to latch multiple counter outputs at one time. This single command is functionally equivalent to several counter latch commands, one for each counter latched. Each counter's latched count is held until it is read or reprogrammed. Once read, a counter is unlatched. The other counters remain latched until they are read. If multiple count Read Back commands are issued to the same counter without reading the count, all but the first are ignored. The Read Back command may additionally be used to latch status information of selected counters. The status of a counter is accessed by a read from that counter's I/O port address. If multiple counter status latch operations are performed without reading the status, all but the first are ignored. Both count and status of the selected counters may be latched simultaneously. This is functionally the same as issuing two consecutive, separate Read Back commands. If multiple count and/or status Read Back commands are issued to the same counters without any intervening reads, all but the first are ignored. If both count and status of a counter are latched, the first read operation from that counter returns the latched status, regardless of which was latched first. The next one or two reads, depending on whether the counter is programmed for one or two type counts, returns the latched count. Subsequent reads return unlatched count. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 129 Functional Description 5.9 8259 Interrupt Controllers (PIC) (D31:F0) The PCH incorporates the functionality of two 8259 interrupt controllers that provide system interrupts for the ISA compatible interrupts. These interrupts are: system timer, keyboard controller, serial ports, parallel ports, floppy disk,mouse, and DMA channels. In addition, this interrupt controller can support the PCI based interrupts, by mapping the PCI interrupt onto the compatible ISA interrupt line. Each 8259 core supports eight interrupts, numbered 0-7. Table 5-17 shows how the cores are connected. . Table 5-17. Interrupt Controller Core Connections 8259 Master Slave 8259 Input Typical Interrupt Source Connected Pin / Function 0 Internal Internal Timer / Counter 0 output / HPET #0 1 Keyboard IRQ1 using SERIRQ 2 Internal Slave controller INTR output 3 Serial Port A IRQ3 using SERIRQ, PIRQ# 4 Serial Port B IRQ4 using SERIRQ, PIRQ# 5 Parallel Port / Generic IRQ5 using SERIRQ, PIRQ# 6 Floppy Disk IRQ6 using SERIRQ, PIRQ# 7 Parallel Port / Generic IRQ7 using SERIRQ, PIRQ# 0 Internal Real Time Clock Internal RTC / HPET #1 1 Generic IRQ9 using SERIRQ, SCI, TCO, or PIRQ# 2 Generic IRQ10 using SERIRQ, SCI, TCO, or PIRQ# 3 Generic IRQ11 using SERIRQ, SCI, TCO, or PIRQ#, or HPET #2 4 PS/2 Mouse IRQ12 using SERIRQ, SCI, TCO, or PIRQ#, or HPET #3 5 Internal State Machine output based on processor FERR# assertion. May optionally be used for SCI or TCO interrupt if FERR# not needed. 6 SATA SATA Primary (legacy mode), or using SERIRQ or PIRQ# 7 SATA SATA Secondary (legacy mode) or using SERIRQ or PIRQ# The PCH cascades the slave controller onto the master controller through master controller interrupt input 2. This means there are only 15 possible interrupts for the PCH's PIC. Interrupts can individually be programmed to be edge or level, except for IRQ0, IRQ2, IRQ8, and IRQ13. Note: 130 Active-low interrupt sources (for example, the PIRQ#s) are inverted inside the PCH. In the following descriptions of the 8259s, the interrupt levels are in reference to the signals at the internal interface of the 8259s, after the required inversions have occurred. Therefore, the term "high" indicates "active," which means "low" on an originating PIRQ#. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.9.1 Interrupt Handling 5.9.1.1 Generating Interrupts The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each interrupt level. These bits are used to determine the interrupt vector returned, and status of any other pending interrupts. Table 5-18 defines the IRR, ISR, and IMR. Table 5-18. Interrupt Status Registers 5.9.1.2 Bit Description IRR Interrupt Request Register. This bit is set on a low to high transition of the interrupt line in edge mode, and by an active high level in level mode. This bit is set whether or not the interrupt is masked. However, a masked interrupt will not generate INTR. ISR Interrupt Service Register. This bit is set, and the corresponding IRR bit cleared, when an interrupt acknowledge cycle is seen, and the vector returned is for that interrupt. IMR Interrupt Mask Register. This bit determines whether an interrupt is masked. Masked interrupts will not generate INTR. Acknowledging Interrupts The processor generates an interrupt acknowledge cycle that is translated by the host bridge into a PCI Interrupt Acknowledge Cycle to the PCH. The PIC translates this command into two internal INTA# pulses expected by the 8259 cores. The PIC uses the first internal INTA# pulse to freeze the state of the interrupts for priority resolution. On the second INTA# pulse, the master or slave sends the interrupt vector to the processor with the acknowledged interrupt code. This code is based upon bits [7:3] of the corresponding ICW2 register, combined with three bits representing the interrupt within that controller. Table 5-19. Content of Interrupt Vector Byte Master, Slave Interrupt Bits [2:0] IRQ7,15 111 IRQ6,14 110 IRQ5,13 101 IRQ4,12 IRQ3,11 5.9.1.3 Bits [7:3] ICW2[7:3] 100 011 IRQ2,10 010 IRQ1,9 001 IRQ0,8 000 Hardware/Software Interrupt Sequence 1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or seen high in level mode, setting the corresponding IRR bit. 2. The PIC sends INTR active to the processor if an asserted interrupt is not masked. 3. The processor acknowledges the INTR and responds with an interrupt acknowledge cycle. The cycle is translated into a PCI interrupt acknowledge cycle by the host bridge. This command is broadcast over PCI by the PCH. 4. Upon observing its own interrupt acknowledge cycle on PCI, the PCH converts it into the two cycles that the internal 8259 pair can respond to. Each cycle appears as an interrupt acknowledge pulse on the internal INTA# pin of the cascaded interrupt controllers. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 131 Functional Description 5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR bit is set and the corresponding IRR bit is reset. On the trailing edge of the first pulse, a slave identification code is broadcast by the master to the slave on a private, internal three bit wide bus. The slave controller uses these bits to determine if it must respond with an interrupt vector during the second INTA# pulse. 6. Upon receiving the second internally generated INTA# pulse, the PIC returns the interrupt vector. If no interrupt request is present because the request was too short in duration, the PIC returns vector 7 from the master controller. 7. This completes the interrupt cycle. In Automatic End of Interrupt (AEOI) mode the ISR bit is reset at the end of the second INTA# pulse. Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt subroutine. 5.9.2 Initialization Command Words (ICWx) Before operation can begin, each 8259 must be initialized. In the PCH, this is a four byte sequence. The four initialization command words are referred to by their acronyms: ICW1, ICW2, ICW3, and ICW4. The base address for each 8259 initialization command word is a fixed location in the I/O memory space: 20h for the master controller, and A0h for the slave controller. 5.9.2.1 ICW1 An I/O write to the master or slave controller base address with data bit 4 equal to 1 is interpreted as a write to ICW1. Upon sensing this write, the PCH PIC expects three more byte writes to 21h for the master controller, or A1h for the slave controller, to complete the ICW sequence. A write to ICW1 starts the initialization sequence during which the following automatically occur: 1. Following initialization, an interrupt request (IRQ) input must make a low-to-high transition to generate an interrupt. 2. The Interrupt Mask Register is cleared. 3. IRQ7 input is assigned priority 7. 4. The slave mode address is set to 7. 5. Special mask mode is cleared and Status Read is set to IRR. 5.9.2.2 ICW2 The second write in the sequence (ICW2) is programmed to provide bits [7:3] of the interrupt vector that will be released during an interrupt acknowledge. A different base is selected for each interrupt controller. 5.9.2.3 ICW3 The third write in the sequence (ICW3) has a different meaning for each controller. * For the master controller, ICW3 is used to indicate which IRQ input line is used to cascade the slave controller. Within the PCH, IRQ2 is used. Therefore, bit 2 of ICW3 on the master controller is set to a 1, and the other bits are set to 0s. * For the slave controller, ICW3 is the slave identification code used during an interrupt acknowledge cycle. On interrupt acknowledge cycles, the master controller broadcasts a code to the slave controller if the cascaded interrupt won arbitration on the master controller. The slave controller compares this identification code to the value stored in its ICW3, and if it matches, the slave controller assumes responsibility for broadcasting the interrupt vector. 132 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.9.2.4 ICW4 The final write in the sequence (ICW4) must be programmed for both controllers. At the very least, bit 0 must be set to a 1 to indicate that the controllers are operating in an Intel Architecture-based system. 5.9.3 Operation Command Words (OCW) These command words reprogram the Interrupt controller to operate in various interrupt modes. * OCW1 masks and unmasks interrupt lines. * OCW2 controls the rotation of interrupt priorities when in rotating priority mode, and controls the EOI function. * OCW3 sets up ISR/IRR reads, enables/disables the special mask mode (SMM), and enables/disables polled interrupt mode. 5.9.4 Modes of Operation 5.9.4.1 Fully Nested Mode In this mode, interrupt requests are ordered in priority from 0 through 7, with 0 being the highest. When an interrupt is acknowledged, the highest priority request is determined and its vector placed on the bus. Additionally, the ISR for the interrupt is set. This ISR bit remains set until: the processor issues an EOI command immediately before returning from the service routine; or if in AEOI mode, on the trailing edge of the second INTA#. While the ISR bit is set, all further interrupts of the same or lower priority are inhibited, while higher levels generate another interrupt. Interrupt priorities can be changed in the rotating priority mode. 5.9.4.2 Special Fully-Nested Mode This mode is used in the case of a system where cascading is used, and the priority has to be conserved within each slave. In this case, the special fully-nested mode is programmed to the master controller. This mode is similar to the fully-nested mode with the following exceptions: * When an interrupt request from a certain slave is in service, this slave is not locked out from the master's priority logic and further interrupt requests from higher priority interrupts within the slave are recognized by the master and initiate interrupts to the processor. In the normal-nested mode, a slave is masked out when its request is in service. * When exiting the Interrupt Service routine, software has to check whether the interrupt serviced was the only one from that slave. This is done by sending a NonSpecific EOI command to the slave and then reading its ISR. If it is 0, a nonspecific EOI can also be sent to the master. 5.9.4.3 Automatic Rotation Mode (Equal Priority Devices) In some applications, there are a number of interrupting devices of equal priority. Automatic rotation mode provides for a sequential 8-way rotation. In this mode, a device receives the lowest priority after being serviced. In the worst case, a device requesting an interrupt has to wait until each of seven other devices are serviced at most once. There are two ways to accomplish automatic rotation using OCW2; the Rotation on Non-Specific EOI Command (R=1, SL=0, EOI=1) and the rotate in automatic EOI mode which is set by (R=1, SL=0, EOI=0). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 133 Functional Description 5.9.4.4 Specific Rotation Mode (Specific Priority) Software can change interrupt priorities by programming the bottom priority. For example, if IRQ5 is programmed as the bottom priority device, then IRQ6 is the highest priority device. The Set Priority Command is issued in OCW2 to accomplish this, where: R=1, SL=1, and LO-L2 is the binary priority level code of the bottom priority device. In this mode, internal status is updated by software control during OCW2. However, it is independent of the EOI command. Priority changes can be executed during an EOI command by using the Rotate on Specific EOI Command in OCW2 (R=1, SL=1, EOI=1 and LO-L2=IRQ level to receive bottom priority. 5.9.4.5 Poll Mode Poll mode can be used to conserve space in the interrupt vector table. Multiple interrupts that can be serviced by one interrupt service routine do not need separate vectors if the service routine uses the poll command. Poll mode can also be used to expand the number of interrupts. The polling interrupt service routine can call the appropriate service routine, instead of providing the interrupt vectors in the vector table. In this mode, the INTR output is not used and the microprocessor internal Interrupt Enable flip-flop is reset, disabling its interrupt input. Service to devices is achieved by software using a Poll command. The Poll command is issued by setting P=1 in OCW3. The PIC treats its next I/O read as an interrupt acknowledge, sets the appropriate ISR bit if there is a request, and reads the priority level. Interrupts are frozen from the OCW3 write to the I/O read. The byte returned during the I/O read contains a 1 in bit 7 if there is an interrupt, and the binary code of the highest priority level in bits 2:0. 5.9.4.6 Edge and Level Triggered Mode In ISA systems this mode is programmed using bit 3 in ICW1, which sets level or edge for the entire controller. In the PCH, this bit is disabled and a new register for edge and level triggered mode selection, per interrupt input, is included. This is the Edge/Level control Registers ELCR1 and ELCR2. If an ELCR bit is 0, an interrupt request will be recognized by a low-to-high transition on the corresponding IRQ input. The IRQ input can remain high without generating another interrupt. If an ELCR bit is 1, an interrupt request will be recognized by a high level on the corresponding IRQ input and there is no need for an edge detection. The interrupt request must be removed before the EOI command is issued to prevent a second interrupt from occurring. In both the edge and level triggered modes, the IRQ inputs must remain active until after the falling edge of the first internal INTA#. If the IRQ input goes inactive before this time, a default IRQ7 vector is returned. 5.9.4.7 End of Interrupt (EOI) Operations An EOI can occur in one of two fashions: by a command word write issued to the PIC before returning from a service routine, the EOI command; or automatically when AEOI bit in ICW4 is set to 1. 5.9.4.8 Normal End of Interrupt In normal EOI, software writes an EOI command before leaving the interrupt service routine to mark the interrupt as completed. There are two forms of EOI commands: Specific and Non-Specific. When a Non-Specific EOI command is issued, the PIC clears the highest ISR bit of those that are set to 1. Non-Specific EOI is the normal mode of operation of the PIC within the PCH, as the interrupt being serviced currently is the interrupt entered with the interrupt acknowledge. When the PIC is operated in modes 134 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description that preserve the fully nested structure, software can determine which ISR bit to clear by issuing a Specific EOI. An ISR bit that is masked is not cleared by a Non-Specific EOI if the PIC is in the special mask mode. An EOI command must be issued for both the master and slave controller. 5.9.4.9 Automatic End of Interrupt Mode In this mode, the PIC automatically performs a Non-Specific EOI operation at the trailing edge of the last interrupt acknowledge pulse. From a system standpoint, this mode should be used only when a nested multi-level interrupt structure is not required within a single PIC. The AEOI mode can only be used in the master controller and not the slave controller. 5.9.5 Masking Interrupts 5.9.5.1 Masking on an Individual Interrupt Request Each interrupt request can be masked individually by the Interrupt Mask Register (IMR). This register is programmed through OCW1. Each bit in the IMR masks one interrupt channel. Masking IRQ2 on the master controller masks all requests for service from the slave controller. 5.9.5.2 Special Mask Mode Some applications may require an interrupt service routine to dynamically alter the system priority structure during its execution under software control. For example, the routine may wish to inhibit lower priority requests for a portion of its execution but enable some of them for another portion. The special mask mode enables all interrupts not masked by a bit set in the Mask register. Normally, when an interrupt service routine acknowledges an interrupt without issuing an EOI to clear the ISR bit, the interrupt controller inhibits all lower priority requests. In the special mask mode, any interrupts may be selectively enabled by loading the Mask Register with the appropriate pattern. The special mask mode is set by OCW3 where: SSMM=1, SMM=1, and cleared where SSMM=1, SMM=0. 5.9.6 Steering PCI Interrupts The PCH can be programmed to allow PIRQA#-PIRQH# to be routed internally to interrupts 3-7, 9-12, 14 or 15. The assignment is programmable through the PIRQx Route Control registers, located at 60-63h and 68-6Bh in Device 31:Function 0. One or more PIRQx# lines can be routed to the same IRQx input. If interrupt steering is not required, the Route registers can be programmed to disable steering. The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts on a PCI board to share a single line across the connector. When a PIRQx# is routed to specified IRQ line, software must change the IRQ's corresponding ELCR bit to level sensitive mode. The PCH internally inverts the PIRQx# line to send an active high level to the PIC. When a PCI interrupt is routed onto the PIC, the selected IRQ can no longer be used by an active high device (through SERIRQ). However, active low interrupts can share their interrupt with PCI interrupts. Internal sources of the PIRQs, including SCI and TCO interrupts, cause the external PIRQ to be asserted. The PCH receives the PIRQ input, like all of the other external sources, and routes it accordingly. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 135 Functional Description 5.10 Advanced Programmable Interrupt Controller (APIC) (D31:F0) In addition to the standard ISA-compatible PIC described in the previous chapter, the PCH incorporates the APIC. While the standard interrupt controller is intended for use in a uni-processor system, APIC can be used in either a uni-processor or multiprocessor system. 5.10.1 Interrupt Handling The I/O APIC handles interrupts very differently than the 8259. Briefly, these differences are: * Method of Interrupt Transmission. The I/O APIC transmits interrupts through memory writes on the normal datapath to the processor, and interrupts are handled without the need for the processor to run an interrupt acknowledge cycle. * Interrupt Priority. The priority of interrupts in the I/O APIC is independent of the interrupt number. For example, interrupt 10 can be given a higher priority than interrupt 3. * More Interrupts. The I/O APIC in the PCH supports a total of 24 interrupts. * Multiple Interrupt Controllers. The I/O APIC architecture allows for multiple I/O APIC devices in the system with their own interrupt vectors. 5.10.2 Interrupt Mapping The I/O APIC within the PCH supports 24 APIC interrupts. Each interrupt has its own unique vector assigned by software. The interrupt vectors are mapped as follows, and match "Config 6" of the Multi-Processor Specification. Table 5-20. APIC Interrupt Mapping1 (Sheet 1 of 2) Using SERIRQ Direct from Pin 0 No No No 1 Yes No Yes 2 No No No 3 Yes No Yes 4 Yes No Yes 5 Yes No Yes 6 Yes No Yes 7 Yes No Yes 8 No No No RTC, HPET #1 (legacy mode) 9 Yes No Yes Option for SCI, TCO IRQ # 136 Using PCI Message Internal Modules Cascade from 8259 #1 8254 Counter 0, HPET #0 (legacy mode) 10 Yes No Yes Option for SCI, TCO 11 Yes No Yes HPET #2, Option for SCI, TCO (Note2) 12 Yes No Yes HPET #3 (Note 3) 13 No No No FERR# logic 14 Yes No Yes SATA Primary (legacy mode) 15 Yes No Yes SATA Secondary (legacy mode) 16 PIRQA# PIRQA# 17 PIRQB# PIRQB# 18 PIRQC# PIRQC# Yes Internal devices are routable; see Section 10.1.20 though Section 10.1.29. 19 PIRQD# PIRQD# Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description Table 5-20. APIC Interrupt Mapping1 (Sheet 2 of 2) IRQ # Using SERIRQ Direct from Pin 20 N/A PIRQE#4 21 N/A PIRQF#4 22 N/A PIRQG# 4 23 N/A PIRQH#4 Using PCI Message Yes Internal Modules Option for SCI, TCO, HPET #0,1,2, 3. Other internal devices are routable; see Section 10.1.20 though Section 10.1.29. Notes: 1. When programming the polarity of internal interrupt sources on the APIC, interrupts 0 through 15 receive active-high internal interrupt sources, while interrupts 16 through 23 receive active-low internal interrupt sources. 2. If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared with any other devices to ensure the proper operation of HPET #2. PCH hardware does not prevent sharing of IRQ 11. 3. If IRQ 12 is used for HPET #3, software should ensure IRQ 12 is not shared with any other devices to ensure the proper operation of HPET #3. PCH hardware does not prevent sharing of IRQ 12. 4. PIRQ[E:H]# are Multiplexed with GPIO pins. Interrupts PIRQ[E:H]# will not be exposed if they are configured as GPIOs. 5.10.3 PCI / PCI Express* Message-Based Interrupts When external devices through PCI / PCI Express* wish to generate an interrupt, they will send the message defined in the PCI Express* Base Specification, Revision 1.0a for generating INTA# - INTD#. These will be translated internal assertions/deassertions of INTA# - INTD#. 5.10.4 IOxAPIC Address Remapping (SRV/WS SKUs Only) To support Intel Virtualization Technology, interrupt messages are required to go through similar address remapping as any other memory request. Address remapping allows for domain isolation for interrupts, so a device assigned in one domain is not allowed to generate an interrupt to another domain. The address remapping is based on the Bus: Device: Function field associated with the requests. The internal APIC is required to initiate the interrupt message using a unique Bus: Device: function. The PCH allows BIOS to program the unique Bus: Device: Function address for the internal APIC. This address field does not change the APIC functionality and the APIC is not promoted as a stand-alone PCI device. See Device 31: Function 0 Offset 6Ch for additional information. 5.10.5 External Interrupt Controller Support The PCH supports external APICs off of PCI Express* ports, and does not support APICs on the PCI bus. The EOI special cycle is only forwarded to PCI Express* ports. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 137 Functional Description 5.11 Serial Interrupt (D31:F0) The PCH supports a serial IRQ scheme. This allows a single signal to be used to report interrupt requests. The signal used to transmit this information is shared between the host, the PCH, and all peripherals that support serial interrupts. The signal line, SERIRQ, is synchronous to PCI clock, and follows the sustained tri-state protocol that is used by all PCI signals. This means that if a device has driven SERIRQ low, it will first drive it high synchronous to PCI clock and release it the following PCI clock. The serial IRQ protocol defines this sustained tri-state signaling in the following fashion: * S - Sample Phase. Signal driven low * R - Recovery Phase. Signal driven high * T - Turn-around Phase. Signal released The PCH supports a message for 21 serial interrupts. These represent the 15 ISA interrupts (IRQ0-1, 3-15), the four PCI interrupts, and the control signals SMI# and IOCHK#. The serial IRQ protocol does not support the additional APIC interrupts (20- 23). Note: When the SATA controller is configured for legacy IDE mode, IRQ14 and IRQ15 are expected to behave as ISA legacy interrupts, which cannot be shared (that is, through the Serial Interrupt pin). If IRQ14 and IRQ15 are shared with Serial Interrupt pin then abnormal system behavior may occur. For example, IRQ14/15 may not be detected by PCH's interrupt controller. When the SATA controller is not running in Native IDE mode, IRQ14 and IRQ15 are used as special interrupts. If the SATA controller is in native modes, these interrupts can be mapped to other devices accordingly. 5.11.1 Start Frame The serial IRQ protocol has two modes of operation which affect the start frame. These two modes are: Continuous, where the PCH is solely responsible for generating the start frame; and Quiet, where a serial IRQ peripheral is responsible for beginning the start frame. The mode that must first be entered when enabling the serial IRQ protocol is continuous mode. In this mode, the PCH asserts the start frame. This start frame is 4, 6, or 8 PCI clocks wide based upon the Serial IRQ Control Register, bits 1:0 at 64h in Device 31:Function 0 configuration space. This is a polling mode. When the serial IRQ stream enters quiet mode (signaled in the Stop Frame), the SERIRQ line remains inactive and pulled up between the Stop and Start Frame until a peripheral drives the SERIRQ signal low. The PCH senses the line low and continues to drive it low for the remainder of the Start Frame. Since the first PCI clock of the start frame was driven by the peripheral in this mode, the PCH drives the SERIRQ line low for 1 PCI clock less than in continuous mode. This mode of operation allows for a quiet, and therefore lower power, operation. 138 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.11.2 Data Frames Once the Start frame has been initiated, all of the SERIRQ peripherals must start counting frames based on the rising edge of SERIRQ. Each of the IRQ/DATA frames has exactly 3 phases of 1 clock each: * Sample Phase. During this phase, the SERIRQ device drives SERIRQ low if the corresponding interrupt signal is low. If the corresponding interrupt is high, then the SERIRQ devices tri-state the SERIRQ signal. The SERIRQ line remains high due to pull-up resistors (there is no internal pull-up resistor on this signal, an external pull-up resistor is required). A low level during the IRQ0-1 and IRQ2-15 frames indicates that an active-high ISA interrupt is not being requested, but a low level during the PCI INT[A:D], SMI#, and IOCHK# frame indicates that an active-low interrupt is being requested. * Recovery Phase. During this phase, the device drives the SERIRQ line high if in the Sample Phase it was driven low. If it was not driven in the sample phase, it is tri-stated in this phase. * Turn-around Phase. The device tri-states the SERIRQ line. 5.11.3 Stop Frame After all data frames, a Stop Frame is driven by the PCH. The SERIRQ signal is driven low by the PCH for 2 or 3 PCI clocks. The number of clocks is determined by the SERIRQ configuration register. The number of clocks determines the next mode: Table 5-21. Stop Frame Explanation Stop Frame Width 5.11.4 Next Mode 2 PCI clocks Quiet Mode. Any SERIRQ device may initiate a Start Frame 3 PCI clocks Continuous Mode. Only the host () may initiate a Start Frame Specific Interrupts Not Supported using SERIRQ There are three interrupts seen through the serial stream that are not supported by the PCH. These interrupts are generated internally, and are not sharable with other devices within the system. These interrupts are: * IRQ0. Heartbeat interrupt generated off of the internal 8254 counter 0. * IRQ8#. RTC interrupt can only be generated internally. * IRQ13. Floating point error interrupt generated off of the processor assertion of FERR#. The PCH ignores the state of these interrupts in the serial stream, and does not adjust their level based on the level seen in the serial stream. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 139 Functional Description 5.11.5 Data Frame Format Table 5-22 shows the format of the data frames. For the PCI interrupts (A-D), the output from the PCH is AND'd with the PCI input signal. This way, the interrupt can be signaled using both the PCI interrupt input signal and using the SERIRQ signal (they are shared). Table 5-22. Data Frame Format 5.12 Data Frame # Interrupt Clocks Past Start Frame 1 IRQ0 2 2 IRQ1 5 3 SMI# 8 4 IRQ3 11 5 IRQ4 14 6 IRQ5 17 7 IRQ6 20 8 IRQ7 23 9 IRQ8 26 10 IRQ9 29 11 IRQ10 32 12 IRQ11 35 13 IRQ12 38 Comment Ignored. IRQ0 can only be generated using the internal 8524 Causes SMI# if low. Will set the SERIRQ_SMI_STS bit. Ignored. IRQ8# can only be generated internally. 14 IRQ13 41 Ignored. IRQ13 can only be generated from FERR# 15 IRQ14 44 Not attached to SATA logic 16 IRQ15 47 Not attached to SATA logic 17 IOCHCK# 50 Same as ISA IOCHCK# going active. 18 PCI INTA# 53 Drive PIRQA# 19 PCI INTB# 56 Drive PIRQB# 20 PCI INTC# 59 Drive PIRQC# 21 PCI INTD# 62 Drive PIRQD# Real Time Clock (D31:F0) The Real Time Clock (RTC) module provides a battery backed-up date and time keeping device with two banks of static RAM with 128 bytes each, although the first bank has 114 bytes for general purpose usage. Three interrupt features are available: time of day alarm with once a second to once a month range, periodic rates of 122 s to 500 ms, and end of update cycle notification. Seconds, minutes, hours, days, day of week, month, and year are counted. Daylight savings compensation is no longer supported. The hour is represented in twelve or twenty-four hour format, and data can be represented in BCD or binary format. The design is functionally compatible with the Motorola MS146818B. The time keeping comes from a 32.768 kHz oscillating source, which is divided to achieve an update every second. The lower 14 bytes on the lower RAM block has very specific functions. The first ten are for time and date information. The next four (0Ah to 0Dh) are registers, which configure and report RTC functions. The time and calendar data should match the data mode (BCD or binary) and hour mode (12 or 24 hour) as selected in register B. It is up to the programmer to make sure that data stored in these locations is within the reasonable values ranges and represents a possible date and time. The exception to these ranges is to store a value 140 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description of C0-FFh in the Alarm bytes to indicate a don't care situation. All Alarm conditions must match to trigger an Alarm Flag, which could trigger an Alarm Interrupt if enabled. The SET bit must be 1 while programming these locations to avoid clashes with an update cycle. Access to time and date information is done through the RAM locations. If a RAM read from the ten time and date bytes is attempted during an update cycle, the value read do not necessarily represent the true contents of those locations. Any RAM writes under the same conditions are ignored. Note: The leap year determination for adding a 29th day to February does not take into account the end-of-the-century exceptions. The logic simply assumes that all years divisible by 4 are leap years. According to the Royal Observatory Greenwich, years that are divisible by 100 are typically not leap years. In every fourth century (years divisible by 400, like 2000), the 100-year-exception is over-ridden and a leap-year occurs. Note that the year 2100 will be the first time in which the current RTC implementation would incorrectly calculate the leap-year. The PCH does not implement month/year alarms. 5.12.1 Update Cycles An update cycle occurs once a second, if the SET bit of register B is not asserted and the divide chain is properly configured. During this procedure, the stored time and date are incremented, overflow is checked, a matching alarm condition is checked, and the time and date are rewritten to the RAM locations. The update cycle will start at least 488 s after the UIP bit of register A is asserted, and the entire cycle does not take more than 1984 s to complete. The time and date RAM locations (0-9) are disconnected from the external bus during this time. To avoid update and data corruption conditions, external RAM access to these locations can safely occur at two times. When a updated-ended interrupt is detected, almost 999 ms is available to read and write the valid time and date data. If the UIP bit of Register A is detected to be low, there is at least 488 s before the update cycle begins. Warning: The overflow conditions for leap years adjustments are based on more than one date or time item. To ensure proper operation when adjusting the time, the new time and data values should be set at least two seconds before leap year occurs. 5.12.2 Interrupts The real-time clock interrupt is internally routed within the PCH both to the I/O APIC and the 8259. It is mapped to interrupt vector 8. This interrupt does not leave the PCH, nor is it shared with any other interrupt. IRQ8# from the SERIRQ stream is ignored. However, the High Performance Event Timers can also be mapped to IRQ8#; in this case, the RTC interrupt is blocked. 5.12.3 Lockable RAM Ranges The RTC battery-backed RAM supports two 8-byte ranges that can be locked using the configuration space. If the locking bits are set, the corresponding range in the RAM will not be readable or writable. A write cycle to those locations will have no effect. A read cycle to those locations will not return the location's actual value (resultant value is undefined). Once a range is locked, the range can be unlocked only by a hard reset, which will invoke the BIOS and allow it to relock the RAM range. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 141 Functional Description 5.12.4 Century Rollover The PCH detects a rollover when the Year byte (RTC I/O space, index Cffset 09h) transitions form 99 to 00. Upon detecting the rollover, the PCH sets the NEWCENTURY_STS bit (TCOBASE + 04h, bit 7). If the system is in an S0 state, this causes an SMI#. The SMI# handler can update registers in the RTC RAM that are associated with century value. If the system is in a sleep state (S1-S5) when the century rollover occurs, the PCH also sets the NEWCENTURY_STS bit, but no SMI# is generated. When the system resumes from the sleep state, BIOS should check the NEWCENTURY_STS bit and update the century value in the RTC RAM. 5.12.5 Clearing Battery-Backed RTC RAM Clearing CMOS RAM in an PCH-based platform can be done by using a jumper on RTCRST# or GPI. Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Using RTCRST# to Clear CMOS A jumper on RTCRST# can be used to clear CMOS values, as well as reset to default, the state of those configuration bits that reside in the RTC power well. When the RTCRST# is strapped to ground, the RTC_PWR_STS bit (D31:F0:A4h bit 2) will be set and those configuration bits in the RTC power well will be set to their default state. BIOS can monitor the state of this bit, and manually clear the RTC CMOS array once the system is booted. The normal position would cause RTCRST# to be pulled up through a weak pull-up resistor. Table 5-23 shows which bits are set to their default state when RTCRST# is asserted. This RTCRST# jumper technique allows the jumper to be moved and then replaced--all while the system is powered off. Then, once booted, the RTC_PWR_STS can be detected in the set state. Table 5-23. Configuration Bits Reset by RTCRST# Assertion (Sheet 1 of 2) Bit Name 142 Register Location Bit(s) Default State Alarm Interrupt Enable (AIE) Register B (General Configuration) (RTC_REGB) I/O space (RTC Index + 0Bh) 5 X Alarm Flag (AF) Register C (Flag Register) (RTC_REGC) I/O space (RTC Index + 0Ch) 5 X SWSMI_RATE_SEL General PM Configuration 3 Register GEN_PMCON_3 D31:F0:A4h 7:6 0 SLP_S4# Minimum Assertion Width General PM Configuration 3 Register GEN_PMCON_3 D31:F0:A4h 5:4 0 SLP_S4# Assertion Stretch Enable General PM Configuration 3 Register GEN_PMCON_3 D31:F0:A4h 3 0 RTC Power Status (RTC_PWR_STS) General PM Configuration 3 Register GEN_PMCON_3 D31:F0:A4h 2 0 Power Failure (PWR_FLR) General PM Configuration 3 Register (GEN_PMCON_3) D31:F0:A4h 1 0 AFTERG3_EN General PM Configuration 3 Register GEN_PMCON_3 D31:F0:A4h 0 0 Power Button Override Status (PRBTNOR_STS) Power Management 1 Status Register (PM1_STS) PMBase + 00h 11 0 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description Table 5-23. Configuration Bits Reset by RTCRST# Assertion (Sheet 2 of 2) Bit Name Register Location Bit(s) Default State RTC Event Enable (RTC_EN) Power Management 1 Enable Register (PM1_EN) PMBase + 02h 10 0 Sleep Type (SLP_TYP) Power Management 1 Control (PM1_CNT) PMBase + 04h 12:10 0 PME_EN General Purpose Event 0 Enables Register (GPE0_EN) PMBase + 2Ch 11 0 BATLOW_EN General Purpose Event 0 Enables Register (GPE0_EN) PMBase + 2Ch 10 0 RI_EN General Purpose Event 0 Enables Register (GPE0_EN) PMBase + 2Ch 8 0 NEWCENTURY_STS TCO1 Status Register (TCO1_STS) TCOBase + 04h 7 0 Intruder Detect (INTRD_DET) TCO2 Status Register (TCO2_STS) TCOBase + 06h 0 0 Top Swap (TS) Backed Up Control Register (BUC) Chipset Config Registers:Offset 3414h 0 X Using a GPI to Clear CMOS A jumper on a GPI can also be used to clear CMOS values. BIOS would detect the setting of this GPI on system boot-up, and manually clear the CMOS array. Note: The GPI strap technique to clear CMOS requires multiple steps to implement. The system is booted with the jumper in new position, then powered back down. The jumper is replaced back to the normal position, then the system is rebooted again. Warning: Do not implement a jumper on VccRTC to clear CMOS. 5.13 Processor Interface (D31:F0) The PCH interfaces to the processor with following pin-based signals other than DMI: * Standard Outputs to processor: PROCPWRGD, PM_SYNC, PM_SYNC2, PECI * Standard Input from processor: THRMTRIP# Most PCH outputs to the processor use standard buffers. The PCH has separate V_PROC_IO signals that are pulled up at the system level to the processor voltage, and thus determines VOH for the outputs to the processor. The following Processor interface legacy pins were removed from the PCH: * IGNNE#, STPCLK#, DPSLP#, are DPRSLPVR are no longer required on PCH based systems. * SMI#, NMI, INIT#, INTR, FERR#: Functionality has been replaced by in-band Virtual Legacy Wire (VLW) messages. See Section 5.13.3. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 143 Functional Description 5.13.1 Processor Interface Signals and VLW Messages This section describes each of the signals that interface between the PCH and the processor(s). Note that the behavior of some signals may vary during processor reset, as the signals are used for frequency strapping. 5.13.1.1 INIT (Initialization) The INIT# VLW Message is asserted based on any one of several events described in Table 5-24. When any of these events occur, INIT# is asserted for 16 PCI clocks, then driven high. Note: INIT3_3V# is functionally identical to INIT# VLW but it is a physical signal at 3.3 V. Table 5-24. INIT# Going Active Cause of INIT3_3V# Going Active Shutdown special cycle from processor observed on PCH-Processor interconnect. Comment INIT assertion based on value of Shutdown Policy Select register (SPS) PORT92 write, where INIT_NOW (bit 0) transitions from a 0 to a 1. PORTCF9 write, where SYS_RST (bit 1) was a 0 and RST_CPU (bit 2) transitions from 0 to 1. 5.13.1.2 RCIN# input signal goes low. RCIN# is expected to be driven by the external microcontroller (KBC). 0 to 1 transition on RCIN# must occur before the PCH will arm INIT3_3V# to be generated again. Note: RCIN# signal is expected to be low during S3, S4, and S5 states. Transition on the RCIN# signal in those states (or the transition to those states) may not necessarily cause the INIT3_3V# signal to be generated to the processor. Processor BIST To enter BIST, software sets CPU_BIST_EN bit and then does a full processor reset using the CF9 register. FERR# (Numeric Coprocessor Error) The PCH supports the coprocessor error function with the FERR# message. The function is enabled using the CEN bit. If FERR# is driven active by the processor, IRQ13 goes active (internally). When it detects a write to the COPROC_ERR register (I/O Register F0h), the PCH negates the internal IRQ13 and IGNNE# will be active. IGNNE# remains active until FERR# is driven inactive. IGNNE# is never driven active unless FERR# is active. Note: 144 IGNNE# - Ignore Numeric Error is now internally generated by the processor. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.13.1.3 NMI (Non-Maskable Interrupt) Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in Table 5-25. Table 5-25. NMI Sources Cause of NMI 5.13.1.4 Comment SERR# goes active (either internally, externally using SERR# signal, or using message from Processor) Can instead be routed to generate an SCI, through the NMI2SCI_EN bit (Device 31:Function 0, TCO Base + 08h, bit 11). IOCHK# goes active using SERIRQ# stream (ISA system Error) Can instead be routed to generate an SCI, through the NMI2SCI_EN bit (Device 31:Function 0, TCO Base + 08h, bit 11). SECSTS Register Device 31: Function F0 Offset 1Eh, bit 8. This is enabled by the Parity Error Response Bit (PER) at Device 30: Function 0 Offset 04, bit 6. DEV_STS Register Device 31:Function F0 Offset 06h, bit 8 This is enabled by the Parity Error Response Bit (PER) at Device 30: Function 0 Offset 04, bit 6. GPIO[15:0] when configured as a General Purpose input and routed as NMI (by GPIO_ROUT at Device 31: Function 0 Offset B8) This is enabled by GPI NMI Enable (GPI_NMI_EN) bits at Device 31: Function 0 Offset: GPIOBASE + 28h bits 15:0 Processor Power Good (PROCPWRGD) This signal is connected to the processor's PRWGOOD input to indicate when the processor power is valid. 5.13.2 Dual-Processor Issues 5.13.2.1 Usage Differences In dual-processor designs, some of the processor signals are unused or used differently than for uniprocessor designs. * FERR# is generally not used, but still supported. * I/O APIC and SMI# are assumed to be used. 5.13.3 Virtual Legacy Wire (VLW) Messages The PCH supports VLW messages as alternative method of conveying the status of the following legacy sideband interface signals to the Processor: * INTR, SMI#, INIT#, NMI Note: IGNNE# VLW message is not required to be generated by the PCH as it is internally emulated by the Processor. VLW are inbound messages to the Processor. They are communicated using Vendor Defined Message over the DMI link. Legacy processor signals can only be delivered using VLW in PCH. Delivery of legacy processor signals (INTR, SMI#, INIT# or NMI) using I/O APIC controller is not supported. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 145 Functional Description 5.14 Power Management 5.14.1 Features * Support for Advanced Configuration and Power Interface, Version 3.0b (ACPI) providing power and thermal management -- ACPI 24-Bit Timer SCI and SMI# Generation * PCI PME# signal for Wake Up from Low-Power states * System Sleep State Control -- ACPI S3 state -- Suspend to RAM (STR) -- ACPI S4 state -- Suspend-to-Disk (STD) -- ACPI G2/S5 state -- Soft Off (SOFF) -- Power Failure Detection and Recovery -- Deep S4/S5 * Intel ME Power Management Support -- Wake events from the Intel ME (enabled from all S-States including Catastrophic S5 conditions) 5.14.2 PCH and System Power States Table 5-26 shows the power states defined for PCH-based platforms. The state names generally match the corresponding ACPI states. Table 5-26. General Power States for Systems Using the PCH State/ Substates 146 Legacy Name / Description G0/S0/C0 Full On: Processor operating. Individual devices may be shut down or be placed into lower power states to save power. G0/S0/Cx Cx State: Cx states are processor power states within the S0 system state that provide for various levels of power savings. The Processor initiates C-state entry and exit while interacting with the PCH through DMI messaging. The PCH will base its behavior on the Processor state. G1/S1 S1: PCH provides the S1 messages and the S0 messages on a wake event. It is much preferred for systems to use C-states than S1. G1/S3 Suspend-To-RAM (STR): The system context is maintained in system DRAM, but power is shut off to non-critical circuits. Memory is retained and refreshes continue. All external clocks stop except RTC. G1/S4 Suspend-To-Disk (STD): The context of the system is maintained on the disk. All power is then shut off to the system except for the logic required to resume. G2/S5 Soft Off (SOFF): System context is not maintained. All power is shut off except for the logic required to restart. A full boot is required when waking. Deep S4/S5 Deep S4/S5: An optional low power state where system context may or may not be maintained depending upon entry condition. All power is shut off except for minimal logic that allows exiting Deep S4/S5. If Deep S4/S5 state was entered from S4 state, then the resume path will place system back into S4. If Deep S4/S5 state was entered from S5 state, then the resume path will place system back into S5. G3 Mechanical OFF (MOFF): System context not maintained. All power is shut off except for the RTC. No "Wake" events are possible. This state occurs if the user turns off a mechanical switch or if the system power supply is at a level that is insufficient to power the "waking" logic. When system power returns, transition will depend on the state just prior to the entry to G3 and the AFTERG3 bit in the GEN_PMCON_3 register (D31:F0, offset A4). Refer to Table 5-33 for more details. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description Table 5-27 shows the transitions rules among the various states. Note that transitions among the various states may appear to temporarily transition through intermediate states. For example, in going from S0 to S3, it may appear to pass through the G1/S1 states. These intermediate transitions and states are not listed in the table. Table 5-27. State Transition Rules for the PCH Present State Transition Trigger G0/S0/C0 * * * * DMI Msg SLP_EN bit set Power Button Override22 Mechanical Off/Power Failure * * * * G0/S0/Cx G1/Sx or G2/S5 state G2/S5 G3 G0/S0/Cx * * * DMI Msg Power Button Override2 Mechanical Off/Power Failure * * * G0/S0/C0 G2/S5 G3 G1/S1 or G1/S3 * * * Any Enabled Wake Event Power Button Override2 Mechanical Off/Power Failure * * * G0/S0/C0 G2/S5 G3 * Any Enabled Wake Event * Power Button Override G1/S4 G2/S5 * 2 Conditions met as described in Section 5.14.6.6.1 and Section 5.14.6.6.2 * G0/S0/C0 * G2/S5 * Deep S4/S5 * Mechanical Off/Power Failure * G3 * Any Enabled Wake Event * G0/S0/C02 * Conditions met as described in Section 5.14.6.6.1 and Section 5.14.6.6.2 * Deep S4/S5 * Mechanical Off/Power Failure * G3 G2/Deep S4/S5 * * Any Enabled Wake Event Mechanical Off/Power Failure * * * G0/S0/C0 G1/S4 or G2/S5 (see Section 5.14.6.6.2) G3 G3 * Power Returns * Optional to go to S0/C0 (reboot) or G2/S5 (stay off until power button pressed or other wake event). (See Note 1) Notes: 1. 2. 3. 4. 5. Next State Some wake events can be preserved through power failure. Includes all other applicable types of events that force the host into and stay in G2/S5. If the system was in G1/S4 before G3 entry, then the system will go to S0/C0 or G1/S4. Upon entry to S5 due to a power button override, if Deep S4/S5 is enabled and conditions are met per Section 5.14.6.6 the system will transition to Deep S4/S5. Upon entry to S5 due to a power button override, if Deep S4/S5 is enabled and conditions are met per section 5.13.7.6, the system will transition to Deep S4/S5. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 147 Functional Description 5.14.3 System Power Planes The system has several independent power planes, as described in Table 5-28. Note that when a particular power plane is shut off, it should go to a 0 V level. s Table 5-28. System Power Plane Plane Controlled By Processor SLP_S3# signal The SLP_S3# signal can be used to cut the power to the processor completely. SLP_S3# signal When SLP_S3# goes active, power can be shut off to any circuit not required to wake the system from the S3 state. Since the S3 state requires that the memory context be preserved, power must be retained to the main memory. The processor, devices on the PCI bus, LPC I/F, and graphics will typically be shut off when the Main power plane is off, although there may be small subsections powered. Memory SLP_S4# signal SLP_S5# signal When SLP_S4# goes active, power can be shut off to any circuit not required to wake the system from the S4. Since the memory context does not need to be preserved in the S4 state, the power to the memory can also be shut down. When SLP_S5# goes active, power can be shut off to any circuit not required to wake the system from the S5 state. Since the memory context does not need to be preserved in the S5 state, the power to the memory can also be shut. Intel ME SLP_A# LAN SLP_LAN# This signal is asserted in Sx/Moff when both host and Intel ME WOL are not supported. This signal can be use to control power to the Intel GbE PHY. Suspend SLP_SUS# This signal that the Sus rails externally can be shut off for enhanced power saving. DEVICE[n] GPIO Individual subsystems may have their own power plane. For example, GPIO signals may be used to control the power to disk drives, audio amplifiers, or the display screen. Main 5.14.4 Description This signal is asserted when the manageability platform goes to MOff. Depending on the platform, this pin may be used to control the Intel ME power planes, LAN subsystem power, and the SPI flash power. SMI#/SCI Generation Upon any enabled Intel SMI event taking place while the End of Intel SMI (EOS) bit is set, the PCH will clear the EOS bit and assert Intel SMI to the processor, which will cause it to enter SMM space. Intel SMI assertion is performed using a Virtual Legacy Wire (VLW) message. Prior system generations (those based upon legacy processors) used an actual SMI# pin. Once the Intel SMI VLW has been delivered, the PCH takes no action on behalf of active Intel SMI events until Host software sets the End of Intel SMI (EOS) bit. At that point, if any Intel SMI events are still active, the PCH will send another Intel SMI VLW. The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating system. In non-APIC systems (which is the default), the SCI IRQ is routed to one of the 8259 interrupts (IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed to level mode for that interrupt. In systems using the APIC, the SCI can be routed to interrupts 9, 10, 11, 20, 21, 22, or 23. The interrupt polarity changes depending on whether it is on an interrupt shareable with a PIRQ or not (see Section 13.1.14). The interrupt remains asserted until all SCI sources are removed. Table 5-29 shows which events can cause an Intel SMI and SCI. Note that some events can be programmed to cause either an Intel SMI or SCI. The usage of the event for SCI (instead of Intel SMI) is typically associated with an ACPI-based system. Each Intel SMI or SCI source has a corresponding enable and status bit. 148 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description Table 5-29. Causes of Intel(R) Scalable Memory Interconnect (Intel(R) SMI) and SCI (Sheet 1 of 2) Cause SCI SMI Additional Enables Where Reported PME# Yes Yes PME_EN=1 PME_STS PME_B0 (Internal, Bus 0, PME-Capable Agents) Yes Yes PME_B0_EN=1 PME_B0_STS PCI Express* PME Messages Yes Yes PCI_EXP_EN=1 (Not enabled for SMI) PCI_EXP_STS PCI Express* Hot-Plug Message Yes Yes HOT_PLUG_EN=1 (Not enabled for SMI) HOT_PLUG_STS Power Button Press Yes Yes PWRBTN_EN=1 PWRBTN_STS Power Button Override (Note 7) Yes No None PRBTNOR_STS RTC Alarm Yes Yes RTC_EN=1 RTC_STS Ring Indicate Yes Yes RI_EN=1 RI_STS USB#1 wakes Yes Yes USB1_EN=1 USB1_STS USB#2 wakes Yes Yes INTEL_USB2_EN=1 INTEL_USB2_STS USB#3 wakes Yes Yes USB3_EN=1 USB3_STS USB#4 wakes Yes Yes USB4_EN=1 USB4_STS USB#5 wakes Yes Yes USB5_EN=1 USB5_STS USB#6 wakes Yes Yes USB6_EN=1 USB6_STS USB#9wakes Yes Yes USB9_EN=1 USB9_STS ACPI Timer overflow (2.34 sec.) Yes Yes TMROF_EN=1 TMROF_STS GPI[x]_STS ALT_GPI_SMI[x]_STS Any GPI[15:0] Yes Yes GPI[x]_Route=10; GPI[x]_EN=1 (SCI) GPI[x]_Route=01; ALT_GPI_SMI[x]_EN=1 (SMI) GPIO[27] Yes Yes GP27_EN=1 GP27_STS TCO SCI Logic Yes No TCOSCI_EN=1 TCOSCI_STS TCO SCI message from MCH Yes none MCHSCI_STS MCHSMI_STS TCO SMI Logic No TCO_EN=1 TCO_STS Yes Yes TCO SMI -- Year 2000 Rollover No Yes none NEWCENTURY_STS TCO SMI -- TCO TIMEROUT No Yes none TIMEOUT TCO SMI -- OS writes to TCO_DAT_IN register No Yes none SW_TCO_SMI TCO SMI -- Message from processor No Yes none DMISMI_STS TCO SMI -- NMI occurred (and NMIs mapped to SMI) No Yes NMI2SMI_EN=1 NMI2SMI_STS TCO SMI -- INTRUDER# signal goes active No Yes INTRD_SEL=10 INTRD_DET TCO SMI -- Change of the BIOSWE (D31:F0:DCh, bit 0) bit from 0 to 1 No Yes BCLE=1 BIOSWR_STS TCO SMI -- Write attempted to BIOS No Yes BC.WPD =0 (Write Protect Disable) BIOSWR_STS NMI (and NMI's mapped to SMI) See NMI section for causes of NMI No Yes NMI2SMI_EN=1 TCO_STS_NMI2SMI_STS BIOS_RLS written to Yes No GBL_EN=1 GBL_STS GBL_RLS written to No Yes BIOS_EN=1 BIOS_STS Write to B2h register No Yes APMC_EN = 1 APM_STS Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 149 Functional Description Table 5-29. Causes of Intel(R) Scalable Memory Interconnect (Intel(R) SMI) and SCI (Sheet 2 of 2) Cause SCI Periodic timer expires No SMI Yes Additional Enables Where Reported PERIODIC_EN=1 PERIODIC_STS 64 ms timer expires No Yes SWSMI_TMR_EN=1 SWSMI_TMR_STS Enhanced USB Legacy Support Event No Yes LEGACY_USB2_EN = 1 LEGACY_USB2_STS Enhanced USB Intel Specific Event No Yes INTEL_USB2_EN = 1 INTEL_USB2_STS Serial IRQ Intel SMI reported No Yes none SERIRQ_SMI_STS Device monitors match address in its range No Yes See DEVTRAP_STS register description SMBus Host Controller No Yes SMB_SMI_EN Host Controller Enabled SMBus host status reg. DEVTRAP_STS SMBus Slave Intel SMI message No Yes none SMBUS_SMI_STS SMBus SMBALERT# signal active No Yes none SMBUS_SMI_STS SMBus Host Notify message received No Yes HOST_NOTIFY_INTREN SMBUS_SMI_STS HOST_NOTIFY_STS Access microcontroller 62h/66h No Yes MCSMI_EN MCSMI_STS SLP_EN bit written to 1 No Yes SLP_SMI_EN=1 SLP_SMI_STS SPI Command Completed No Yes See SPI section SPI_STS Software Generated GPE Yes Yes SWGPE_EN=1 SWGPE_STS INTEL_USB2_STS, Write Enable Status USB Per-Port Registers Write Enable bit changes to 1 No Yes INTEL_USB2_EN=1, Write_Enable_SMI_Enable=1 GPIO Lockdown Enable bit changes from `1' to `0' No Yes GPIO_UNLOCK_SMI_EN=1 GPIO_UNLOCK_SMI_STS VE Host Interface Yes Yes VEHCI_SCI_EN = 1 VEHCI_SMI_EN = 1 VEHCI_SCI_STS VEHCI_SMI_STS VE Intel ME Interface Yes Yes VEMCI_SCI_EN = 1 VEMCI_SMI_EN = 1 VEMCI_SCI_STS VEMCI_SMI_STS Intel ME Interface Yes Yes ME_SCI_EN = 1 ME_SMI_EN = 1 ME_SCI_STS ME_SMI_STS Classic USB Legacy logic (Port 64/60 rd/wr, End of pass-through) No Yes LEGACY_USB_EN = 1 LEGACY_USB_STS RTC Update-in-progress No Yes see I/O Trap Register section RTC_UIP_SMI_STS Notes: 1. 2. 3. 4. 5. 6. 7. 8. 150 SCI_EN must be 1 to enable SCI, except for BIOS_RLS. SCI_EN must be 0 to enable SMI. SCI can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in APIC mode). GBL_SMI_EN must be 1 to enable SMI. EOS must be written to 1 to re-enable Intel SMI for the next 1. PCH must have Intel SMI fully enabled when PCH is also enabled to trap cycles. If Intel SMI is not enabled in conjunction with the trap enabling, then hardware behavior is undefined. Only GPI[15:0] may generate an Intel SMI or SCI. When a power button override first occurs, the system will transition immediately to S5. The SCI will only occur after the next wake to S0 if the residual status bit (PRBTNOR_STS) is not cleared prior to setting SCI_EN. GBL_STS being set will cause an SCI, even if the SCI_EN bit is not set. Software must take great care not to set the BIOS_RLS bit (which causes GBL_STS to be set) if the SCI handler is not in place. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.14.4.1 PCI Express* SCI PCI Express* ports and the Processor (using DMI) have the ability to cause PME using messages. When a PME message is received, PCH will set the PCI_EXP_STS bit. If the PCI_EXP_EN bit is also set, the PCH can cause an SCI using the GPE1_STS register. 5.14.4.2 PCI Express* Hot-Plug PCI Express* has a Hot-Plug mechanism and is capable of generating a SCI using the GPE1 register. It is also capable of generating an Intel SMI. However, it is not capable of generating a wake event. 5.14.5 C-States PCH-based systems implement C-states by having the Processor control the states. The chipset exchanges messages with the Processor as part of the C-state flow, but the chipset does not directly control any of the Processor impacts of C-states, such as voltage levels or Processor clocking. In addition to the new messages, the PCH also provides additional information to the Processor using a sideband pin (PM_SYNC). All of the legacy C-state related pins (STPCLK#, STP_CPU#, DPRSLP#, DPRSLPVR#, and so forth) do not exist on PCH. 5.14.6 Sleep States 5.14.6.1 Sleep State Overview The PCH directly supports different sleep states (S1-S5), which are entered by methods such as setting the SLP_EN bit, or due to a Power Button press. The entry to the Sleep states is based on several assumptions: * The G3 state cannot be entered using any software mechanism. The G3 state indicates a complete loss of power. 5.14.6.2 Initiating Sleep State Sleep states (S1-S5) are initiated by: * Masking interrupts, turning off all bus master enable bits, setting the desired type in the SLP_TYP field, and then setting the SLP_EN bit. The hardware then attempts to gracefully put the system into the corresponding Sleep state. * Pressing the PWRBTN# Signal for more than 4 seconds to cause a Power Button Override event. In this case the transition to the S5 state is less graceful, since there are no dependencies on DMI messages from the processor or on clocks other than the RTC clock. * Assertion of the THRMTRIP# signal will cause a transition to the S5 state. This can occur when system is in S0 or S1 state. * Shutdown by integrated manageability functions (ASF/Intel AMT) * Internal watchdog timer timeout events Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 151 Functional Description Table 5-30. Sleep Types Sleep Type 5.14.6.3 Comment S1 System lowers the processor's power consumption. No snooping is possible in this state. S3 Asserts SLP_S3#. The SLP_S3# signal controls the power to non-critical circuits. Power is only retained to devices needed to wake from this sleeping state, as well as to the memory. S4 Asserts SLP_S3# and SLP_S4#. The SLP_S4# signal shuts off the power to the memory subsystem. Only devices needed to wake from this state should be powered. S5 Same power state as S4. asserts SLP_S3#, SLP_S4# and SLP_S5#. Exiting Sleep States Sleep states (S1-S5) are exited based on Wake events. The Wake events forces the system to a full on state (S0), although some non-critical subsystems might still be shut off and have to be brought back manually. For example, the hard disk may be shut off during a sleep state, and have to be enabled using a GPIO pin before it can be used. Upon exit from software entered sleep states (that is, those initiated using the SLP_EN bit) the WAK_STS bit is set. The possible causes of Wake Events (and their restrictions) are shown in Table 5-31. Table 5-31. Causes of Wake Events (Sheet 1 of 2) Cause How Enabled Wake from Deep S4/S5 Wake from S1, Sx After Power Loss (Note 1) Wake from "Reset" Types (Note 2) RTC Alarm Set RTC_EN bit in PM1_EN register. Y Y Y Power Button Always enabled as Wake event. Y Y Y Y GPI[15:0] GPE0_EN register Note: GPI's that are in the core well are not capable of waking the system from sleep states when the core well is not powered. Y GPIO27 Set GP27_EN in GPE0_EN Register. Y Y Y Y LAN Will use PME#. Wake enable set with LAN logic. Y Y RI# Set RI_EN bit in GPE0_EN register. Y Y Intel(R) High Definition Audio Event sets PME_B0_STS bit; PM_B0_EN must be enabled. Can not wake from S5 state if it was entered due to power failure or power button override. Y Y Primary PME# PME_B0_EN bit in GPE0_EN register. Y Y Secondary PME# Set PME_EN bit in GPE0_EN register. Y Y Y Y PCI_EXP_WAK PCI_EXP_WAKE bit. (Note 3) E# 152 Wake from S1, Sx SATA Set PME_EN bit in GPE0_EN register. (Note 4) S1 S1 PCI_EXP PME Message Must use the PCI Express* WAKE# pin rather than messages for wake from S3, S4, or S5. S1 S1 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description Table 5-31. Causes of Wake Events (Sheet 2 of 2) Cause SMBALERT# Wake from S1, Sx How Enabled Wake from Deep S4/S5 Wake from S1, Sx After Power Loss (Note 1) Wake from "Reset" Types (Note 2) Always enabled as Wake event. Y Y Y Wake/SMI# command always enabled as a Wake event. SMBus Slave Note: SMBus Slave Message Wake Message can wake the system (01h) from S1-S5, as well as from S5 due to Power Button Override. Y Y Y SMBus Host Notify message received Y Y Y Intel(R) ME Non-Maskable Always enabled as a wake event. Wake Y Y Y Integrated WOL Enable Override Y Y Y HOST_NOTIFY_WKEN bit SMBus Slave Command register. Reported in the SMB_WAK_STS bit in the GPEO_STS register. WOL Enable Override bit (in Configuration Space). Notes: 1. This column represents what the PCH would honor as wake events but there may be enabling dependencies on the device side which are not enabled after a power loss. 2. Reset Types include: Power Button override, Intel ME initiated power button override, Intel ME initiated host partition reset with power down, Intel ME Watchdog Timer, SMBus unconditional power down, Processor thermal trip, PCH catastrophic temperature event. 3. When the WAKE# pin is active and the PCI Express* device is enabled to wake the system, the PCH will wake the platform. 4. SATA can only trigger a wake event in S1, but if PME is asserted prior to S3/S4/S5 entry and software does not clear the PME_B0_STS, a wake event would still result. It is important to understand that the various GPIs have different levels of functionality when used as wake events. The GPIs that reside in the core power well can only generate wake events from sleep states where the core well is powered. Also, only certain GPIs are "ACPI Compliant," meaning that their Status and Enable bits reside in ACPI I/O space. Table 5-32 summarizes the use of GPIs as wake events. Table 5-32. GPI Wake Events GPI Power Well Wake From Notes GPI[7:0] Core S1 ACPI Compliant GPI[15:8] Suspend S1-S5 ACPI Compliant The latency to exit the various Sleep states varies greatly and is heavily dependent on power supply design, so much so that the exit latencies due to the PCH are insignificant. 5.14.6.4 PCI Express* WAKE# Signal and PME Event Message PCI Express* ports can wake the platform from any sleep state (S1, S3, S4, or S5) using the WAKE# pin. WAKE# is treated as a wake event, but does not cause any bits to go active in the GPE_STS register. PCI Express* ports and the processor (using DMI) have the ability to cause PME using messages. When a PME message is received, PCH will set the PCI_EXP_STS bit. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 153 Functional Description 5.14.6.5 Sx-G3-Sx, Handling Power Failures Depending on when the power failure occurs and how the system is designed, different transitions could occur due to a power failure. The AFTERG3_EN bit provides the ability to program whether or not the system should boot once power returns after a power loss event. If the policy is to not boot, the system remains in an S5 state (unless previously in S4). There are only three possible events that will wake the system after a power failure. 1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low (G3 state), the PWRBTN_STS bit is reset. When the PCH exits G3 after power returns (RSMRST# goes high), the PWRBTN# signal is already high (because VCCstandby goes high before RSMRST# goes high) and the PWRBTN_STS bit is 0. 2. RI#: RI# does not have an internal pull-up. Therefore, if this signal is enabled as a wake event, it is important to keep this signal powered during the power loss event. If this signal goes low (active), when power returns the RI_STS bit is set and the system interprets that as a wake event. 3. RTC Alarm: The RTC_EN bit is in the RTC well and is preserved after a power loss. Like PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low. The PCH monitors both PCH_PWROK and RSMRST# to detect for power failures. If PCH_PWROK goes low, the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set. Note: Although PME_EN is in the RTC well, this signal cannot wake the system after a power loss. PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#. Table 5-33. Transitions Due to Power Failure State at Power Failure AFTERG3_EN bit Transition When Power Returns S0, S1, S3 1 0 S5 S0 S4 1 0 S4 S0 S5 1 0 S5 S0 Deep S4/S5 1 0 Deep S4/S51 S0 Notes: 1. Entry state to Deep S4/S5 is preserved through G3 allowing resume from Deep S4/S5 to take appropriate path (that is, return to S4 or S5). 5.14.6.6 Deep S4/S5 To minimize power consumption while in S4/S5, the PCH supports a lower power, lower featured version of these power states known as Deep S4/S5. In these Deep S4/S5 states, the Suspend wells are powered off, while the new Deep S4/S5 Well (DSW) remains powered. A limited set of wake events are supported by the logic located in the DSW. 154 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.14.6.6.1 Entry Into Deep S4/S5 A combination of conditions is required for entry into Deep S4/S5. All of the following must be met: -- Intel ME in Moff -- AND ((DPS4_EN_AC AND S4) OR (DPS5_EN_AC AND S5)) Table 5-34. Supported Deep S4/S5 Policy Configurations Configuration DPS4_EN_DC DPS4_EN_AC DPS5_EN_DC DPS5_EN_AC 1: Enabled in S5 0 0 1 1 2: Enabled in S4 and S5 1 1 1 1 3: Deep S4 / S5 disabled 0 0 0 0 The PCH also performs a SUSWARN#/SUSACK# handshake to ensure the platform is ready to enter Deep S4/S5. The PCH asserts SUSWARN# as notification that it is about to enter Deep S4/S5. Before the PCH proceeds and asserts SLP_SUS#, the PCH waits for SUSACK# to assert. 5.14.6.6.2 Exit from Deep S4/S5 While in Deep S4/S5, the PCH monitors and responds to a limited set of wake events (RTC Alarm, Power Button, and GPIO27). Upon sensing an enabled Deep S4/S5 wake event, the PCH brings up the Suspend well by deasserting SLP_SUS#. Table 5-35. Deep S4/S5 Wake Events 5.14.7 Event Enable RTC Alarm RTC_DS_WAKE_DIS (RCBA+3318h:Bit 21) Power Button Always enabled GPIO27 GPIO27_EN (PMBASE+28h:Bit 35) Event Input Signals and Their Usage The PCH has various input signals that trigger specific events. This section describes those signals and how they should be used. 5.14.7.1 PWRBTN# (Power Button) The PCH PWRBTN# signal operates as a "Fixed Power Button" as described in the Advanced Configuration and Power Interface, Version 2.0b. PWRBTN# signal has a 16 ms de-bounce on the input. The state transition descriptions are included in Table 5-36. Note that the transitions start as soon as the PWRBTN# is pressed (but after the debounce logic), and does not depend on when the Power Button is released. Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width (if enabled), the Power Button is not a wake event. Refer to the following Power Button Override Function section for further detail. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 155 Functional Description Table 5-36. Transitions Due to Power Button Present State Event Transition/Action Comment S0/Cx PWRBTN# goes low Intel SMI or SCI generated (depending on SCI_EN, PWRBTN_EN and GLB_SMI_EN) Software typically initiates a Sleep state S1-S5 PWRBTN# goes low Wake Event. Transitions to S0 state Standard wakeup G3 PWRBTN# pressed None No effect since no power Not latched nor detected PWRBTN# held low for at least 4 consecutive seconds Unconditional transition to S5 state and if Deep S4/S5 is enabled and conditions are met per Section 5.14.6.6, the system will then transition to Deep S4/S5. No dependence on processor (DMI Messages) or any other subsystem S0-S4 Power Button Override Function If PWRBTN# is observed active for at least four consecutive seconds, the state machine unconditionally transitions to the G2/S5 state or Deep S4/S5, regardless of present state (S0-S4), even if the PCH PWROK is not active. In this case, the transition to the G2/S5 state or Deep S4/S5 does not depend on any particular response from the processor (such as, a DMI Messages), nor any similar dependency from any other subsystem. The PWRBTN# status is readable to check if the button is currently being pressed or has been released. The status is taken after the de-bounce, and is readable using the PWRBTN_LVL bit. Note: The 4-second PWRBTN# assertion should only be used if a system lock-up has occurred. The 4-second timer starts counting when the PCH is in a S0 state. If the PWRBTN# signal is asserted and held active when the system is in a suspend state (S1-S5), the assertion causes a wake event. Once the system has resumed to the S0 state, the 4-second timer starts. Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width (if enabled by D31:F0:A4h Bit 3), the Power Button is not a wake event. As a result, it is conceivable that the user will press and continue to hold the Power Button waiting for the system to awake. Since a 4-second press of the Power Button is already defined as an Unconditional Power down, the power button timer will be forced to inactive while the power-cycle timer is in progress. Once the power-cycle timer has expired, the Power Button awakes the system. Once the minimum SLP_S4# power cycle expires, the Power Button must be pressed for another 4 to 5 seconds to create the Override condition. Sleep Button The Advanced Configuration and Power Interface, Version 2.0b defines an optional Sleep button. It differs from the power button in that it only is a request to go from S0 to S1-S4 (not S5). Also, in an S5 state, the Power Button can wake the system, but the Sleep Button cannot. Although the PCH does not include a specific signal designated as a Sleep Button, one of the GPIO signals can be used to create a "Control Method" Sleep Button. See the Advanced Configuration and Power Interface, Version 2.0b for implementation details. 156 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.14.7.2 RI# (Ring Indicator) The Ring Indicator can cause a wake event (if enabled) from the S1-S5 states. Table 5-37 shows when the wake event is generated or ignored in different states. If in the G0/S0/Cx states, the PCH generates an interrupt based on RI# active, and the interrupt will be set up as a Break event. Table 5-37. Transitions Due to RI# Signal Present State Event RI_EN S0 RI# Active X Ignored RI# Active 0 1 Ignored Wake Event S1-S5 Event Note: Filtering/Debounce on RI# will not be done in PCH. Can be in modem or external. 5.14.7.3 PME# (PCI Power Management Event) The PME# signal comes from a PCI device to request that the system be restarted. The PME# signal can generate an SMI#, SCI, or optionally a Wake event. The event occurs when the PME# signal goes from high to low. No event is caused when it goes from low to high. There is also an internal PME_B0 bit. This is separate from the external PME# signal and can cause the same effect. 5.14.7.4 SYS_RESET# Signal When the SYS_RESET# pin is detected as active after the 16 ms debounce logic, the PCH attempts to perform a "graceful" reset, by waiting up to 25 ms for the SMBus to go idle. If the SMBus is idle when the pin is detected active, the reset occurs immediately; otherwise, the counter starts. If at any point during the count the SMBus goes idle the reset occurs. If, however, the counter expires and the SMBus is still active, a reset is forced upon the system even though activity is still occurring. Once the reset is asserted, it remains asserted for 5 to 6 ms regardless of whether the SYS_RESET# input remains asserted or not. It cannot occur again until SYS_RESET# has been detected inactive after the debounce logic, and the system is back to a full S0 state with PLTRST# inactive. Note that if bit 3 of the CF9h I/O register is set then SYS_RESET# will result in a full power cycle reset. 5.14.7.5 THRMTRIP# Signal If THRMTRIP# goes active, the processor is indicating an overheat condition, and the PCH immediately transitions to an S5 state, driving SLP_S3#, SLP_S4#, SLP_S5# low, and setting the CTS bit. The transition looks like a power button override. When a THRMTRIP# event occurs, the PCH will power down immediately without following the normal S0 -> S5 path. The PCH will immediately drive SLP_S3#, SLP_S4#, and SLP_S5# low after sampling THRMTRIP# active. If the processor is running extremely hot and is heating up, it is possible (although very unlikely) that components around it, such as the PCH, are no longer executing cycles properly. Therefore, if THRMTRIP# goes active, and the PCH is relying on state machine logic to perform the power down, the state machine may not be working, and the system will not power down. The PCH provides filtering for short low glitches on the THRMTRIP# signal in order to prevent erroneous system shut downs from noise. Glitches shorter than 25 nsec are ignored. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 157 Functional Description During boot, THRMTRIP# is ignored until SLP_S3#, PCH_PWROK, and PLTRST# are all `1'. During entry into a powered-down state (due to S3, S4, S5 entry, power cycle reset, etc.) THRMTRIP# is ignored until either SLP_S3# = 0, or PCH_PWROK = 0, or SYS_PWROK= 0. Note: A thermal trip event will: * Clear the PWRBTN_STS bit * Clear all the GPE0_EN register bits * Clear the SMB_WAK_STS bit only if SMB_SAK_STS was set due to SMBus slave receiving message and not set due to SMBAlert 5.14.8 ALT Access Mode Before entering a low power state, several registers from powered down parts may need to be saved. In the majority of cases, this is not an issue, as registers have read and write paths. However, several of the ISA compatible registers are either read only or write only. To get data out of write-only registers, and to restore data into read-only registers, the PCH implements an ALT access mode. If the ALT access mode is entered and exited after reading the registers of the PCH timer (8254), the timer starts counting faster (13.5 ms). The following steps listed below can cause problems: 1. BIOS enters ALT access mode for reading the PCH timer related registers. 2. BIOS exits ALT access mode. 3. BIOS continues through the execution of other needed steps and passes control to the operating system. After getting control in step #3, if the operating system does not reprogram the system timer again, the timer ticks may be happening faster than expected. For example Microsoft MS-DOS* and its associated software assume that the system timer is running at 54.6 ms and as a result the time-outs in the software may be happening faster than expected. Operating systems (for example, Microsoft Windows* 98 and Windows* 2000) reprogram the system timer and therefore do not encounter this problem. For other operating systems (for example, Microsoft MS-DOS*) the BIOS should restore the timer back to 54.6 ms before passing control to the operating system. If the BIOS is entering ALT access mode before entering the suspend state it is not necessary to restore the timer contents after the exit from ALT access mode. 158 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.14.8.1 Write Only Registers with Read Paths in ALT Access Mode The registers described in Table 5-38 have read paths in ALT access mode. The access number field in the table indicates which register will be returned per access to that port. Table 5-38. Write Only Registers with Read Paths in ALT Access Mode (Sheet 1 of 2) Restore Data I/O Addr 00h 01h 02h 03h 04h 05h 06h 07h 08h # of Rds Access Restore Data Data I/O Addr # of Rds Access Data 1 DMA Chan 0 base address low byte 1 Timer Counter 0 status, bits [5:0] 2 DMA Chan 0 base address high byte 2 Timer Counter 0 base count low byte 1 DMA Chan 0 base count low byte 3 Timer Counter 0 base count high byte 2 DMA Chan 0 base count high byte 4 Timer Counter 1 base count low byte 1 DMA Chan 1 base address low byte 5 Timer Counter 1 base count high byte 2 DMA Chan 1 base address high byte 6 Timer Counter 2 base count low byte 1 DMA Chan 1 base count low byte 7 Timer Counter 2 base count high byte 2 DMA Chan 1 base count high byte 41h 1 Timer Counter 1 status, bits [5:0] 1 DMA Chan 2 base address low byte 42h 1 Timer Counter 2 status, bits [5:0] 2 DMA Chan 2 base address high byte 70h 1 Bit 7 = NMI Enable, Bits [6:0] = RTC Address 1 DMA Chan 2 base count low byte C4h 2 C6h 2 2 2 2 2 2 2 2 DMA Chan 2 base count high byte 1 DMA Chan 3 base address low byte 2 2 6 2 DMA Chan 3 base address high byte 1 DMA Chan 3 base count low byte 2 DMA Chan 3 base count high byte 1 DMA Chan 0-3 Command2 2 DMA Chan 0-3 Request 3 DMA Chan 0 Mode: Bits(1:0) = 00 4 DMA Chan 1 Mode: Bits(1:0) = 01 5 DMA Chan 2 Mode: Bits(1:0) = 10 6 DMA Chan 3 Mode: Bits(1:0) = 11. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 40h 7 C8h 2 CAh 2 CCh 2 CEh 1 DMA Chan 5 base address low byte 2 DMA Chan 5 base address high byte 1 DMA Chan 5 base count low byte 2 DMA Chan 5 base count high byte 1 DMA Chan 6 base address low byte 2 DMA Chan 6 base address high byte 1 DMA Chan 6 base count low byte 2 DMA Chan 6 base count high byte 1 DMA Chan 7 base address low byte 2 DMA Chan 7 base address high byte 1 DMA Chan 7 base count low byte 2 DMA Chan 7 base count high byte 2 159 Functional Description Table 5-38. Write Only Registers with Read Paths in ALT Access Mode (Sheet 2 of 2) Restore Data I/O Addr # of Rds 20h 12 Access Restore Data I/O Addr Data # of Rds Access DMA Chan 4-7 Command2 1 PIC ICW2 of Master controller 2 PIC ICW3 of Master controller 2 DMA Chan 4-7 Request 3 PIC ICW4 of Master controller 3 DMA Chan 4 Mode: Bits(1:0) = 00 4 PIC OCW1 of Master controller1 4 DMA Chan 5 Mode: Bits(1:0) = 01 5 PIC OCW2 of Master controller 5 DMA Chan 6 Mode: Bits(1:0) = 10 6 PIC OCW3 of Master controller 6 DMA Chan 7 Mode: Bits(1:0) = 11. 7 PIC ICW2 of Slave controller 8 PIC ICW3 of Slave controller 9 PIC ICW4 of Slave controller 10 PIC OCW1 of Slave controller1 11 PIC OCW2 of Slave controller 12 PIC OCW3 of Slave controller 1 Data D0h 6 Notes: 1. The OCW1 register must be read before entering ALT access mode. 2. Bits 5, 3, 1, and 0 return 0. 5.14.8.2 PIC Reserved Bits Many bits within the PIC are reserved, and must have certain values written in order for the PIC to operate properly. Therefore, there is no need to return these values in ALT access mode. When reading PIC registers from 20h and A0h, the reserved bits shall return the values listed in Table 5-39. Table 5-39. PIC Reserved Bits Return Values 160 PIC Reserved Bits Value Returned ICW2(2:0) 000 ICW4(7:5) 000 ICW4(3:2) 00 ICW4(0) 0 OCW2(4:3) 00 OCW3(7) 0 OCW3(5) Reflects bit 6 OCW3(4:3) 01 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.14.8.3 Read Only Registers with Write Paths in ALT Access Mode The registers described in Table 5-40 have write paths to them in ALT access mode. Software restores these values after returning from a powered down state. These registers must be handled special by software. When in normal mode, writing to the base address/count register also writes to the current address/count register. Therefore, the base address/count must be written first, then the part is put into ALT access mode and the current address/count register is written. Table 5-40. Register Write Accesses in ALT Access Mode I/O Address Register Write Value 08h DMA Status Register for channels 0-3. D0h DMA Status Register for channels 4-7. 5.14.9 System Power Supplies, Planes, and Signals 5.14.9.1 Power Plane Control with SLP_S3#, SLP_S4#, SLP_S5#, SLP_A# and SLP_LAN# The SLP_S3# output signal can be used to cut power to the system core supply, since it only goes active for the Suspend-to-RAM state (typically mapped to ACPI S3). Power must be maintained to the PCH suspend well, and to any other circuits that need to generate Wake signals from the Suspend-to-RAM state. During S3 (Suspend-to-RAM) all signals attached to powered down plans will be tri-stated or driven low, unless they are pulled using a pull-up resistor. Cutting power to the core may be done using the power supply, or by external FETs on the motherboard. The SLP_S4# or SLP_S5# output signal can be used to cut power to the system core supply, as well as power to the system memory, since the context of the system is saved on the disk. Cutting power to the memory may be done using the power supply, or by external FETs on the motherboard. The SLP_S4# output signal is used to remove power to additional subsystems that are powered during SLP_S3#. SLP_S5# output signal can be used to cut power to the system core supply, as well as power to the system memory, since the context of the system is saved on the disk. Cutting power to the memory may be done using the power supply, or by external FETs on the motherboard. SLP_A# output signal can be used to cut power to the Intel ME, Clock chip and SPI flash on a platform that supports the M3 state (for example, certain power policies in Intel AMT). SLP_LAN# output signal can be used to cut power to the external Intel 82579 Gbe PHY device. 5.14.9.2 SLP_S4# and Suspend-To-RAM Sequencing The system memory suspend voltage regulator is controlled by the Glue logic. The SLP_S4# signal should be used to remove power to system memory rather than the SLP_S5# signal. The SLP_S4# logic in the PCH provides a mechanism to fully cycle the power to the DRAM and/or detect if the power is not cycled for a minimum time. Note: To utilize the minimum DRAM power-down feature that is enabled by the SLP_S4# Assertion Stretch Enable bit (D31:F0:A4h bit 3), the DRAM power must be controlled by the SLP_S4# signal. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 161 Functional Description 5.14.9.3 PCH_PWROK Signal When asserted, PCH_PWROK is an indication to the PCH that its core well power rails have been powered and stable. PCH_PWROK can be driven asynchronously. When PCH_PWROK is low, the PCH asynchronously asserts PLTRST#. PCH_PWROK must not glitch, even if RSMRST# is low. It is required that the power associated with PCI/PCIe have been valid for 99 ms prior to PCH_PWROK assertion in order to comply with the 100 ms PCI 2.3 / PCIe 1.1 specification on PLTRST# deassertion. Note: SYS_RESET# is recommended for implementing the system reset button. This saves external logic that is needed if the PCH_PWROK input is used. Additionally, it allows for better handling of the SMBus and processor resets and avoids improperly reporting power failures. 5.14.9.4 SLP_LAN# Pin Behavior The following table summarizes SLP_LAN# pin behavior. Table 5-41. SLP_LAN# Pin Behavior Pin Functionality (Determined by soft strap) GPIO29 Input / Output (Determined by GP_IO_SEL bit) Pin Value In S0 or M3 Value in S3-S5/ Moff In (Default) 1 0 Out 1 Depends on GPIO29 output data value In (Default) 1 1 Out 1 Depends on GPIO29 output data value 0 (Default) In Z (tri-state) 0 1 In Z (tri-state) 1 Out Depends on GPIO29 output data value Depends on GPIO29 output data value SLP_LAN Default Value Bit 0 (Default) SLP_LAN# 1 GPIO29 N/A 5.14.9.5 RTCRST# and SRTCRST# RTCRST# is used to reset PCH registers in the RTC Well to their default value. If a jumper is used on this pin, it should only be pulled low when system is in the G3 state and then replaced to the default jumper position. Upon booting, BIOS should recognize that RTCRST# was asserted and clear internal PCH registers accordingly. It is imperative that this signal not be pulled low in the S0 to S5 states. SRTCRST# is used to reset portions of the Intel Management Engine and should not be connected to a jumper or button on the platform. The only time this signal gets asserted (driven low in combination with RTCRST#) should be when the coin cell battery is removed or not installed and the platform is in the G3 state. Pulling this signal low independently (without RTCRST# also being driven low) may cause the platform to enter an indeterminate state. Similar to RTCRST#, it is imperative that SRTCRST# not be pulled low in the S0 to S5 states. See Figure 2-2 which demonstrates the proper circuit connection of these pins. 162 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.14.9.6 SUSWARN#/GPIO30 Pin Behavior Table 5-42 summarize SUSWARN#/GPIO30 pin behavior. Table 5-42. SUSWARN#/GPIO30 Steady State Pin Behavior SUSWARN# GPIO30 Deep S4/S5 (Supported/NotSupported) GPIO30 Input/ Output (Determine by GP_IO_SEL bit) Pin Value in S0 Pin Value in Sx/Moff Pin Value in Sx/M3 Pin Value in Deep S4/ S5 Supported Native 1 1 (Note 1) 1 Off Don't Care IN High-Z High-Z High-Z Off Don't Care OUT Depends on GPIO30 output data value Depends on GPIO30 output data value Depends on GPIO30 output data value Off Notes: 1. If entering Deep S4/S5, pin will assert and become undriven ("Off") when suspend well drops upon Deep S4/S5 entry. 5.14.10 Legacy Power Management Theory of Operation Instead of relying on ACPI software, legacy power management uses BIOS and various hardware mechanisms. The scheme relies on the concept of detecting when individual subsystems are idle, detecting when the whole system is idle, and detecting when accesses are attempted to idle subsystems. However, the operating system is assumed to be at least APM enabled. Without APM calls, there is no quick way to know when the system is idle between keystrokes. The PCH does not support burst modes. 5.14.10.1 APM Power Management The PCH has a timer that, when enabled by the 1MIN_EN bit in the Intel SMI Control and Enable register, generates an Intel SMI once per minute. The Intel SMI handler can check for system activity by reading the DEVTRAP_STS register. If none of the system bits are set, the Intel SMI handler can increment a software counter. When the counter reaches a sufficient number of consecutive minutes with no activity, the Intel SMI handler can then put the system into a lower power state. If there is activity, various bits in the DEVTRAP_STS register will be set. Software clears the bits by writing a 1 to the bit position. The DEVTRAP_STS register allows for monitoring various internal devices, or Super I/O devices (SP, PP, FDC) on LPC or PCI, keyboard controller accesses, or audio functions on LPC or PCI. Other PCI activity can be monitored by checking the PCI interrupts. 5.14.11 Reset Behavior When a reset is triggered, the PCH will send a warning message to the Processor to allow the Processor to attempt to complete any outstanding memory cycles and put memory into a safe state before the platform is reset. When the Processor is ready, it will send an acknowledge message to the PCH. Once the message is received the PCH asserts PLTRST#. The PCH does not require an acknowledge message from the processor to trigger PLTRST#. A global reset will occur after 4 seconds if an acknowledge from the processor is not received. When the PCH causes a reset by asserting PLTRST# its output signals will go to their reset states as defined in Chapter 3. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 163 Functional Description A reset in which the host platform is reset and PLTRST# is asserted is called a Host Reset or Host Partition Reset. Depending on the trigger a host reset may also result in power cycling see Table 5-43 for details. If a host reset is triggered and the PCH times out before receiving an acknowledge message from the Processor a Global Reset with power cycle will occur. A reset in which the host and Intel ME partitions of the platform are reset is called a Global Reset. During a Global Reset, all PCH functionality is reset except RTC Power Well backed information and Suspend well status, configuration, and functional logic for controlling and reporting the reset. Intel ME and Host power back up after the power cycle period. Straight to S5 is another reset type where all power wells that are controlled by the SLP_S3#, SLP_S4#, and SLP_A# pins, as well as SLP_S5# and SLP_LAN# (if pins are not configured as GPIOs), are turned off. All PCH functionality is reset except RTC Power Well backed information and Suspend well status, configuration, and functional logic for controlling and reporting the reset. The host stays there until a valid wake event occurs. Table 5-43 shows the various reset triggers: Table 5-43. Causes of Host and Global Resets (Sheet 1 of 2) Host Reset without Power Cycle1 Host Reset with Power Cycle2 Global Reset with Power Cycle3 Write of 0Eh to CF9h (RST_CNT Register) No Yes No (Note 4) Write of 06h to CF9h (RST_CNT Register) Yes No No (Note 4) SYS_RESET# Asserted and CF9h (RST_CNT Register) Bit 3 = 0 Yes No No (Note 4) SYS_RESET# Asserted and CF9h (RST_CNT Register) Bit 3 = 1 No Yes No (Note 4) SMBus Slave Message received for Reset with Power Cycle No Yes No (Note 4) SMBus Slave Message received for Reset without Power Cycle Yes No No (Note 4) SMBus Slave Message received for unconditional Power Down No No No TCO Watchdog Timer reaches zero two times Yes No No (Note 4) Power Failure: PWROK signal goes inactive in S0/S1 or DPWROK drops No No Yes SYS_PWROK Failure: SYS_PWROK signal goes inactive in S0/S1 No No Yes Processor Thermal Trip (THRMTRIP#) causes transition to S5 and reset asserts No No No Yes PCH internal thermal sensors signals a catastrophic temperature condition No No No Yes Power Button 4 second override causes transition to S5 and reset asserts No No No Yes Special shutdown cycle from processor causes CF9h-like PLTRST# and CF9h (RST_CNT Register) Bit 3 = 1 No Yes No (Note 4) Special shutdown cycle from processor causes CF9h-like PLTRST# and CF9h (RST_CNT Register) Bit 3 = 0 Yes No No (Note 4) Intel ME Triggered Host Reset without power cycle Yes No No (Note 4) Intel ME Triggered Host Reset with power cycle No Yes No (Note 4) Trigger 164 Straight to S56 (Host Stays there) Yes Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description Table 5-43. Causes of Host and Global Resets (Sheet 2 of 2) Trigger Host Reset without Power Cycle1 Host Reset with Power Cycle2 Global Reset with Power Cycle3 Straight to S56 (Host Stays there) Intel ME Triggered Power Button Override No No No Yes Intel ME Watchdog Timer Timeout No No No Yes Intel ME Triggered Global Reset No No Yes Intel ME Triggered Host Reset with power down (host stays there) No Yes (Note 5) No (Note 4) PLTRST# Entry Time-out No No Yes S3/4/5 Entry Timeout No No No Yes PROCPWRGD Stuck Low No No Yes Power Management Watchdog Timer No No No Yes Intel ME Hardware Uncorrectable Error No No No Yes Notes: 1. The PCH drops this type of reset request if received while the system is in S3/S4/S5. 2. PCH does not drop this type of reset request if received while system is in a software-entered S3/S4/ S5 state. However, the PCH is allowed to perform the reset without executing the RESET_WARN protocol in these states. 3. The PCH does not send warning message to processor, reset occurs without delay. 4. Trigger will result in Global Reset with power cycle if the acknowledge message is not received by the PCH. 5. The PCH waits for enabled wake event to complete reset. 6. Upon entry to S5, if Deep S4/S5 is enabled and conditions are met per Section 5.14.6.6, the system will transition to Deep S4/S5. 5.15 System Management (D31:F0) The PCH provides various functions to make a system easier to manage and to lower the Total Cost of Ownership (TCO) of the system. Features and functions can be augmented using external A/D converters and GPIO, as well as an external microcontroller. The following features and functions are supported by the PCH: * Processor present detection -- Detects if processor fails to fetch the first instruction after reset * Various Error detection (such as ECC Errors) indicated by host controller -- Can generate SMI#, SCI, SERR, NMI, or TCO interrupt * Intruder Detect input -- Can generate TCO interrupt or SMI# when the system cover is removed -- INTRUDER# allowed to go active in any power state, including G3 * Detection of bad BIOS Flash (FWH or Flash on SPI) programming -- Detects if data on first read is FFh (indicates that BIOS flash is not programmed) * Ability to hide a PCI device -- Allows software to hide a PCI device in terms of configuration space through the use of a device hide register. (See Section 10.1.45) Note: Voltage ID from the processor can be read using GPI signals. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 165 Functional Description 5.15.1 Theory of Operation The System Management functions are designed to allow the system to diagnose failing subsystems. The intent of this logic is that some of the system management functionality can be provided without the aid of an external microcontroller. 5.15.1.1 Detecting a System Lockup When the processor is reset, it is expected to fetch its first instruction. If the processor fails to fetch the first instruction after reset, the TCO timer times out twice and the PCH asserts PLTRST#. 5.15.1.2 Handling an Intruder The PCH has an input signal, INTRUDER#, that can be attached to a switch that is activated by the system's case being open. This input has a two RTC clock debounce. If INTRUDER# goes active (after the debouncer), this will set the INTRD_DET bit in the TCO2_STS register. The INTRD_SEL bits in the TCO_CNT register can enable the PCH to cause an SMI# or interrupt. The BIOS or interrupt handler can then cause a transition to the S5 state by writing to the SLP_EN bit. The software can also directly read the status of the INTRUDER# signal (high or low) by clearing and then reading the INTRD_DET bit. This allows the signal to be used as a GPI if the intruder function is not required. If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written as a 1, then the INTRD_DET signal will go to a 0 when INTRUDER# input signal goes inactive. Note that this is slightly different than a classic sticky bit, since most sticky bits would remain active indefinitely when the signal goes active and would immediately go inactive when a 1 is written to the bit. Note: The INTRD_DET bit resides in the PCH's RTC well, and is set and cleared synchronously with the RTC clock. Thus, when software attempts to clear INTRD_DET (by writing a 1 to the bit location) there may be as much as two RTC clocks (about 65 s) delay before the bit is actually cleared. Also, the INTRUDER# signal should be asserted for a minimum of 1 ms to ensure that the INTRD_DET bit will be set. Note: If the INTRUDER# signal is still active when software attempts to clear the INTRD_DET bit, the bit remains set and the Intel SMI is generated again immediately. The Intel SMI handler can clear the INTRD_SEL bits to avoid further Intel SMIs. However, if the INTRUDER# signal goes inactive and then active again, there will not be further Intel SMIs, since the INTRD_SEL bits would select that no SMI# be generated. 5.15.1.3 Detecting Improper Flash Programming The PCH can detect the case where the BIOS flash is not programmed. This results in the first instruction fetched to have a value of FFh. If this occurs, the PCH sets the BAD_BIOS bit. The BIOS flash may reside in FWH or flash on the SPI bus. 5.15.1.4 Heartbeat and Event Reporting using SMLink/SMBus (SRV/WS SKUs Only) Heartbeat and event reporting using SMLink/SMBus is no longer supported. The Intel AMT logic in PCH can be programmed to generate an interrupt to the Intel ME when an event occurs. The Intel ME will poll the TCO registers to gather appropriate bits to send the event message to the Gigabit Ethernet controller, if Intel ME is programmed to do so. 166 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.15.2 TCO Modes 5.15.2.1 TCO Legacy/Compatible Mode In TCO Legacy/Compatible mode, only the host SMBus is utilized. The TCO Slave is connected to the host SMBus internally by default. In this mode, the Intel ME SMBus controllers are not used and should be disabled by soft strap. Figure 5-7. TCO Legacy/Compatible Mode SMBus Configuration PCH TCO Legacy/Compatible Mode Intel ME SMBus Controller 3 X Intel ME SMBus Controller 2 X Intel ME SMBus Controller 1 X SPD (Slave) PCI/PCIe* Device uCtrl SMBus Host SMBus TCO Slave Legacy Sensors (Master or Slave with ALERT) 3rd Party NIC In TCO Legacy/Compatible mode the PCH can function directly with an external LAN controller or equivalent external LAN controller to report messages to a network management console without the aid of the system processor. This is crucial in cases where the processor is malfunctioning or cannot function due to being in a low-power state. Table 5-44 includes a list of events that will report messages to the network management console. Table 5-44. Event Transitions that Cause Messages Event Assertion? Deassertion? INTRUDER# pin yes no Must be in "S1 or hung S0" state THRM# pin yes yes Must be in "S1 or hung S0" state. Note that the THRM# pin is isolated when the core power is off, thus preventing this event in S3S5. Watchdog Timer Expired yes no (NA) GPIO[11]/SMBALERT# pin yes yes Must be in "S1 or hung S0" state BATLOW# yes yes Must be in "S1 or hung S0" state Note: Comments "S1 or hung S0" state entered The GPIO11/SMBALERT# pin will trigger an event message (when enabled by the GPIO11_ALERT_DISABLE bit) regardless of whether it is configured as a GPI or not. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 167 Functional Description 5.15.2.2 Advanced TCO Mode PCH supports the Advanced TCO mode in which SMLink0 and SMLink1 are used in addition to the host SMBus. See Figure 5-8 for more details. In this mode, the Intel ME SMBus controllers must be enabled by soft strap (*TCO Slave Select) in the flash descriptor. The SMLink0 is dedicated to integrated LAN use and when an Intel PHY 82579 is connected to SMLink0, a soft strap must be set to indicate that the PHY is connected to SMLink0. The interface will be running at the frequency of 300 KHz - 400 KHz depending on different factors such as board routing or bus loading when the Fast Mode is enabled using a soft strap. Note: With Intel SPS FW, the SMLink0 can also be used with BMC. However, this precludes use of the Intel PHY 82579. SMLink1 is dedicated to Embedded Controller (EC) or Baseboard Management Controller (BMC) use. In the case where a BMC is connected to SMLink1, the BMC communicates with Intel ME through Intel ME SMBus connected to SMLink1. The host and TCO slave communicated with BMC through SMBus. Figure 5-8. Advanced TCO Mode PCH Intel ME SMBus Controller 3 Intel ME SMBus Controller 2 Intel ME SMBus Controller 1 Advanced TCO Mode SMLink1 EC or BMC SMLink0 Intel 82579 SPD (Slave) PCI/PCIe* Device Host SMBus SMBus TCO Slave 168 Legacy Sensors (Master or Slave with ALERT) Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.16 General Purpose I/O (D31:F0) The PCH contains up to 70 General Purpose Input/Output (GPIO) signals. Each GPIO can be configured as an input or output signal. The number of inputs and outputs varies depending on the configuration. Below is a brief summary of new GPIO features. -- Capability to mask Suspend well GPIOs from CF9h events configured using GP_RST_SEL registers) -- Added capability to program GPIO prior to switching to output 5.16.1 Power Wells Some GPIOs exist in the suspend power plane. Care must be taken to make sure GPIO signals are not driven high into powered-down planes. Some PCH GPIOs may be connected to pins on devices that exist in the core well. If these GPIOs are outputs, there is a danger that a loss of core power (PCH_PWROK low) or a Power Button Override event results in PCH driving a pin to a logic 1 to another device that is powered down. 5.16.2 SMI# SCI and NMI Routing The routing bits for GPIO[15:0] allow an input to be routed to SMI#, SCI, NMI or neither. Note that a bit can be routed to either an SMI# or an SCI, but not both. 5.16.3 Triggering GPIO[15:0] have "sticky" bits on the input. Refer to the GPE0_STS register and the ALT_GPI_SMI_STS register. As long as the signal goes active for at least 2 clock cycles, the PCH keeps the sticky status bit active. The active level can be selected in the GP_INV register. This does not apply to GPI_NMI_STS residing in GPIO IO space. If the system is in an S0 or an S1 state, the GPI inputs are sampled at 33 MHz, so the signal only needs to be active for about 60 ns to be latched. In the S3-S5 states, the GPI inputs are sampled at 32.768 kHz, and thus must be active for at least 61 microseconds to be latched. Note: GPIs that are in the core well are not capable of waking the system from sleep states where the core well is not powered. If the input signal is still active when the latch is cleared, it will again be set. Another edge trigger is not required. This makes these signals "level" triggered inputs. 5.16.4 GPIO Registers Lockdown The following GPIO registers are locked down when the GPIO Lockdown Enable (GLE) bit is set. The GLE bit resides in D31:F0:GPIO Control (GC) register. * Offset 00h: GPIO_USE_SEL[31:0] * Offset 04h: GP_IO_SEL[31:0] * Offset 0Ch: GP_LVL[31:0] * Offset 28h: GPI_NMI_EN[15:0] * Offset 2Ch: GPI_INV[31:0] * Offset 30h: GPIO_USE_SEL2[63:32] * Offset 34h: GPI_IO_SEL2[63:32] * Offset 38h: GP_LVL2[63:32] * Offset 40h: GPIO_USE_SEL3[95:64] Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 169 Functional Description * Offset 44h: GPI_IO_SEL3[95:64] * Offset 48h: GP_LVL3[95:64] * Offset 60h: GP_RST_SEL[31:0] * Offset 64h: GP_RST_SEL2[63:32] * Offset 68h: GP_RST_SEL3[95:64] Once these registers are locked down, they become Read-Only registers and any software writes to these registers will have no effect. To unlock the registers, the GPIO Lockdown Enable (GLE) bit is required to be cleared to `0'. When the GLE bit changes from a `1' to a `0' a System Management Interrupt (SMI#) is generated if enabled. Once the GPIO_UNLOCK_SMI bit is set, it can not be changed until a PLTRST# occurs. This ensures that only BIOS can change the GPIO configuration. If the GLE bit is cleared by unauthorized software, BIOS will set the GLE bit again when the SMI# is triggered and these registers will continue to be locked down. 5.16.5 Serial POST Codes over GPIO PCH adds the extended capability allowing system software to serialize POST or other messages on GPIO. This capability negates the requirement for dedicated diagnostic LEDs on the platform. Additionally, based on the newer BTX form factors, the PCI bus as a target for POST codes is increasingly difficult to support as the total number of PCI devices supported are decreasing. 5.16.5.1 Theory of Operation For the PCH generation POST code serialization logic will be shared with GPIO. These GPIOs will likely be shared with LED control offered by the Super I/O (SIO) component. Figure 5-9 shows a likely configuration. Figure 5-9. Serial Post over GPIO Reference Circuit VccSus3_3 R PCH SIO LED Note: The pull-up value is based on the brightness required. The anticipated usage model is that either the PCH or the SIO can drive a pin low to turn off an LED. In the case of the power LED, the SIO would normally leave its corresponding pin in a high-Z state to allow the LED to turn on. In this state, the PCH can blink the LED by driving its corresponding pin low and subsequently tri-stating the buffer. The I/O buffer should not drive a `1' when configured for this functionality and should be capable of sinking 24 mA of current. 170 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description An external optical sensing device can detect the on/off state of the LED. By externally post-processing the information from the optical device, the serial bit stream can be recovered. The hardware will supply a `sync' byte before the actual data transmission to allow external detection of the transmit frequency. The frequency of transmission should be limited to 1 transition every 1 s to ensure the detector can reliably sample the on/off state of the LED. To allow flexibility in pull-up resistor values for power optimization, the frequency of the transmission is programmable using the DRS field in the GP_GB_CMDSTS register. The serial bit stream is Manchester encoded. This choice of transmission ensures that a transition will be seen on every clock. The 1 or 0 data is based on the transmission happening during the high or low phase of the clock. As the clock will be encoded within the data stream, hardware must ensure that the Z-0 and 0-Z transitions are glitch-free. Driving the pin directly from a flop or through glitch-free logic are possible methods to meet the glitch-free requirement. A simplified hardware/software register interface provides control and status information to track the activity of this block. Software enabling the serial blink capability should implement an algorithm referenced below to send the serialized message on the enabled GPIO. 1. Read the Go/Busy status bit in the GP_GB_CMDSTS register and verify it is cleared. This will ensure that the GPIO is idled and a previously requested message is still not in progress. 2. Write the data to serialize into the GP_GB_DATA register. 3. Write the DLS and DRS values into the GP_GB_CMDSTS register and set the Go bit. This may be accomplished using a single write. The reference diagram shows the LEDs being powered from the suspend supply. By providing a generic capability that can be used both in the main and the suspend power planes maximum flexibility can be achieved. A key point to make is that the PCH will not unintentionally drive the LED control pin low unless a serialization is in progress. System board connections utilizing this serialization capability are required to use the same power plane controlling the LED as the GPIO pin. Otherwise, the PCH GPIO may float low during the message and prevent the LED from being controlled from the SIO. The hardware will only be serializing messages when the core power well is powered and the processor is operational. Care should be taken to prevent the PCH from driving an active `1' on a pin sharing the serial LED capability. Since the SIO could be driving the line to 0, having the PCH drive a 1 would create a high current path. A recommendation to avoid this condition involves choosing a GPIO defaulting to an input. The GP_SER_BLINK register should be set first before changing the direction of the pin to an output. This sequence ensures the open-drain capability of the buffer is properly configured before enabling the pin as an output. 5.16.5.2 Serial Message Format In order to serialize the data onto the GPIO, an initial state of high-Z is assumed. The SIO is required to have its LED control pin in a high-Z state as well to allow PCH to blink the LED (refer to the reference diagram). The three components of the serial message include the sync, data, and idle fields. The sync field is 7 bits of `1' data followed by 1 bit of `0' data. Starting from the high-Z state (LED on) provides external hardware a known initial condition and a known pattern. In case one or more of the leading 1 sync bits are lost, the 1s followed by 0 provide a clear indication of `end of sync'. This pattern will be used to `lock' external sampling logic to the encoded clock. The data field is shifted out with the highest byte first (MSB). Within each byte, the most significant bit is shifted first (MSb). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 171 Functional Description The idle field is enforced by the hardware and is at least 2 bit times long. The hardware will not clear the Busy and Go bits until this idle time is met. Supporting the idle time in hardware prevents time-based counting in BIOS as the hardware is immediately ready for the next serial code when the Go bit is cleared. Note that the idle state is represented as a high-Z condition on the pin. If the last transmitted bit is a 1, returning to the idle state will result in a final 0-1 transition on the output Manchester data. Two full bit times of idle correspond to a count of 4 time intervals (the width of the time interval is controlled by the DRS field). The following waveform shows a 1-byte serial write with a data byte of 5Ah. The internal clock and bit position are for reference purposes only. The Manchester D is the resultant data generated and serialized onto the GPIO. Since the buffer is operating in open-drain mode the transitions are from high-Z to 0 and back. Bit 7 6 5 4 3 2 1 0 Internal Clock Manchester D 8-bit sync field (1111_1110) 5A data byte 5.16.6 GPIO Serial Expander (GSX) 5.16.6.1 Overview 2 clk idle There are a finite number of GPIOs available to be used in the PCH and servers frequently runs out of GPIOs. To help alleviate this issue, a new capability has been added to the PCH, the GPIO Serial Expander. This is a new interface that uses external serial-to-parallel and parallel-to-serial expander chips to provide up to 64 additional general purpose I/O signals in steps of 8 while only consuming 5 PCH's I/O pins. 5.16.6.2 Configuration GSX uses 5 signals, Clock (GSXCLK), Dataout (GSXSDOUT), Datain (GSXSDIN), Reset (GSXSRESET#) and Load (GSXSLOAD). These signals are multiplexed onto PCI Grant and PCI Request signals. A soft strap is used to configure whether GSX is enabled or not. There is no hardstrap configuration or post-boot BIOS setting to change this. Note: All GSX native functions are determined by GPIO Serial Expander Enable soft strap. Software MUST NOT program the GPIO53/GSXDIN pin to GPIO mode by setting GPIO_USE_SEL[53] bit when GSX is enabled through soft strap. GPIO mode will override GSX operational mode and possible cause board contention on GPIO53 if the platform had planned to use this pin as GSXDIN. It is also recommend that GPIO_IO_SEL[53] be set to 1 when operating in GSX mode as added protection against board contention. 5.16.6.3 Operation When the soft straps for the PCH are read, the multiplexed signals become GSX only signals and can not be used as PCI signals or general purpose I/O signals. Coming out of reset, the GSXSRESET# signal automatically gets asserted to clear the outputs. This signal stays active until the first cycle to program/upload data. Software is required to set up the appropriate registers. It defines how many output registers and input registers there are. The max number of combined registers is 8 as the maximum GPIOs are 64. The registers can be any mix and match of input and 172 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description output. For example, you could have 64 outputs and no inputs, 64 inputs and no outputs, 8 inputs and 56 outputs, and so forth. Also, it's not required to add up to a maximum of 64 I/O. The GSX bus could also support only 8 inputs and 8 outputs, for example. After resetting the GSX bus with a write to IOERST, software will load up the CxGPOLVL and CxGPOLVL_DW1 registers with data to be written out to the serial to parallel output expanders (how many bits are programmed, is dependent upon how many outputs are defined in the capabilities register). A write to the START (ST) bit will cause the serialization process to begin. First all the output bits are shifted out to the serial to parallel buffers. Then GSXSLOAD goes high to latch in and enable the output of the buffers. At the same time, GSXSLOAD latches in the data into the parallel-to-serial buffers and that data is read into the input buffers (CxGPILVL and CxGPILVL_DW1). Once the START bit is set, the serialization process starts running continuously... writing out the contents of the CxGPOLVL registers and programming the contents of the CxGPILVL registers. Clearing this bit (writing a "0" to it) will stop the process but only on an atomic boundary. That is HW will finish serializing the output and finishing reading in the serial data if it began the cycle. There are two read only bits to help software with the programming of the CxGPOLVL registers and the reading of the CxGPILVL registers. RUNNING (RUN) is set to a "1" as long as the HW is in the process of writing out and reading in data. BUSY (BSY) is a "1" as long as the CxGPOLVL data has not been completely written out at least once. For software to make sure that data is not in the middle of being updated, it needs to wait until RUNNING is a "0". SW will program START to a "0" and wait for RUNNING to be a "0" before it knows it's safe to load in new data to the output buffers, or read data from the input buffers without fear of data being updated in the middle of the cycle. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 173 Functional Description 5.17 SATA Host Controller (D31:F2, F5) The SATA function in the PCH has three modes of operation to support different operating system conditions. In the case of Native IDE enabled operating systems, the PCH uses two controllers to enable all six ports of the bus. The first controller (Device 31: Function 2) supports ports 0 -3 and the second controller (Device 31: Function 5) supports ports 4 and 5. When using a legacy operating system, only one controller (Device 31: Function 2) is available that supports ports 0 - 3. In AHCI or RAID mode, only one controller (Device 31: Function 2) is utilized enabling all six ports and the second controller (Device 31: Function 5) shall be disabled. The MAP register Section 15.1.28 provides the ability to share PCI functions. When sharing is enabled, all decode of I/O is done through the SATA registers. Device 31, Function 1 (IDE controller) is hidden by software writing to the Function Disable Register (D31, F0, offset F2h, bit 1), and its configuration registers are not used. The PCH SATA controllers feature six sets of interface signals (ports) that can be independently enabled or disabled (they cannot be tri-stated or driven low). Each interface is supported by an independent DMA controller. The PCH SATA controllers interact with an attached mass storage device through a register interface that is equivalent to that presented by a traditional IDE host adapter (when AHCI/RAID disabled). The host software follows existing standards and conventions when accessing the register interface and follows standard command protocol conventions. Note: SATA interface transfer rates are independent of UDMA mode settings. SATA interface transfer rates will operate at the bus's maximum speed, regardless of the UDMA mode reported by the SATA device or the system BIOS. 5.17.1 SATA 6 Gb/s Support The PCH supports SATA 6 Gb/s transfers with all capable SATA devices. SATA 6 Gb/s supports s available on PCH Ports 0 and 1 only. Note: PCH ports 0 and 1 also supports SATA 1.5 Gb/s and 3.0 Gb/s device transfers, while ports 2-5 only support SATA 1.5 Gb/s and 3.0 Gb/s device transfers. 5.17.2 SATA Feature Support PCH (AHCI/RAID Disabled) PCH (AHCI/RAID Enabled) Native Command Queuing (NCQ) N/A Supported Auto Activate for DMA N/A Supported Hot-Plug Support N/A Supported Asynchronous Signal Recovery N/A Supported Feature 3 Gb/s Transfer Rate Supported Supported ATAPI Asynchronous Notification N/A Supported Host & Link Initiated Power Management N/A Supported Supported Supported Staggered Spin-Up 174 Command Completion Coalescing N/A N/A External SATA N/A Supported Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description Feature Description Native Command Queuing (NCQ) Allows the device to reorder commands for more efficient data transfers Auto Activate for DMA Collapses a DMA Setup then DMA Activate sequence into a DMA Setup only Hot Plug Support Allows for device detection without power being applied and ability to connect and disconnect devices without prior notification to the system Asynchronous Signal Recovery Provides a recovery from a loss of signal or establishing communication after hot plug 6 Gb/s Transfer Rate Capable of data transfers up to 6Gb/s ATAPI Asynchronous Notification A mechanism for a device to send a notification to the host that the device requires attention Host & Link Initiated Power Management Capability for the host controller or device to request Partial and Slumber interface power states Staggered Spin-Up Enables the host the ability to spin up hard drives sequentially to prevent power load problems on boot Command Completion Coalescing Reduces interrupt and completion overhead by allowing a specified number of commands to complete and then generating an interrupt to process the commands External SATA Technology that allows for an outside the box connection of up to 2 meters (when using the cable defined in SATA-IO) 5.17.3 Theory of Operation 5.17.3.1 Standard ATA Emulation The PCH contains a set of registers that shadow the contents of the legacy IDE registers. The behavior of the Command and Control Block registers, PIO, and DMA data transfers, resets, and interrupts are all emulated. Note: The PCH will assert INTR when the master device completes the EDD command regardless of the command completion status of the slave device. If the master completes EDD first, an INTR is generated and BSY will remain '1' until the slave completes the command. If the slave completes EDD first, BSY will be '0' when the master completes the EDD command and asserts INTR. Software must wait for busy to clear (0) before completing an EDD command, as required by the ATA5 through ATA7 (T13) industry standards. 5.17.3.2 48-Bit LBA Operation The SATA host controller supports 48-bit LBA through the host-to-device register FIS when accesses are performed using writes to the task file. The SATA host controller will ensure that the correct data is put into the correct byte of the host-to-device FIS. There are special considerations when reading from the task file to support 48-bit LBA operation. Software may need to read all 16-bits. Since the registers are only 8-bits wide and act as a FIFO, a bit must be set in the device/control register, which is at offset 3F6h for primary and 376h for secondary (or their native counterparts). If software clears bit 7 of the control register before performing a read, the last item written will be returned from the FIFO. If software sets bit 7 of the control register before performing a read, the first item written will be returned from the FIFO. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 175 Functional Description 5.17.4 SATA Swap Bay Support The PCH provides for basic SATA swap bay support using the PSC register configuration bits and power management flows. A device can be powered down by software and the port can then be disabled, allowing removal and insertion of a new device. Note: This SATA swap bay operation requires board hardware (implementation specific), BIOS, and operating system support. 5.17.5 Hot-Plug Operation PCH supports Hot-Plug Surprise removal and Insertion Notification. An internal SATA port with a Mechanical Presence Switch can support PARTIAL and SLUMBER with Hot Plug Enabled. Software can take advantage of power savings in the low power states while enabling hot-plug operation. Refer to chapter 7 of the AHCI specification for details. 5.17.6 Function Level Reset Support (FLR) (SRV/WS SKUs Only) The SATA Host Controller supports the Function Level Reset (FLR) capability. The FLR capability can be used in conjunction with Intel Virtualization Technology. FLR allows an Operating System in a Virtual Machine to have complete control over a device, including its initialization, without interfering with the rest of the platform. The device provides a software interface that enables the Operating System to reset the whole device as if a PCI reset was asserted. 5.17.6.1 FLR Steps 5.17.6.1.1 FLR Initialization 1. A FLR is initiated by software writing a `1' to the Initiate FLR bit. 2. All subsequent requests targeting the Function will not be claimed and will be Master Abort Immediate on the bus. This includes any configuration, I/O or Memory cycles, however, the Function shall continue to accept completions targeting the Function. 5.17.6.1.2 FLR Operation The Function will Reset all configuration, I/O and memory registers of the Function except those indicated otherwise and reset all internal states of the Function to the default or initial condition. 5.17.6.1.3 FLR Completion The Initiate FLR bit is reset (cleared) when the FLR reset is completed. This bit can be used to indicate to the software that the FLR reset is completed. Note: 176 From the time Initiate FLR bit is written to '1' software must wait at least 100 ms before accessing the function. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.17.7 Intel(R) Rapid Storage Technology Enterprise Configuration The Intel(R) Rapid Storage Technology enterprise (Intel(R) RSTe) offers several diverse options for RAID (redundant array of independent disks) to meet the needs of the end user. AHCI support provides higher performance and alleviates disk bottlenecks by taking advantage of the independent DMA engines that each SATA port offers in PCH. * RAID Level 0 performance scaling up to 4 drives, enabling higher throughput for data intensive applications such as video editing. * Data redundancy is offered through RAID Level 1, which performs mirroring. * RAID Level 10 provides high levels of storage performance with increased data protection, combining the fault-tolerance of RAID Level 1 with the performance of RAID Level 0. By striping RAID Level 1 segments, high I/O rates can be achieved on systems that require both performance and fault-tolerance. RAID Level 10 requires 4 hard drives, and provides the capacity of two drives. * RAID Level 5 provides highly efficient storage while maintaining fault-tolerance on 3 or more drives. By striping parity, and rotating it across all disks, fault tolerance of any single drive is achieved while only consuming 1 drive worth of capacity. That is, a 3 drive RAID 5 has the capacity of 2 drives, or a 4 drive RAID 5 has the capacity of 3 drives. RAID 5 has high read transaction rates, with a medium write rate. RAID 5 is well suited for applications that require high amounts of storage while maintaining fault tolerance. By using the PCH's built-in Intel Rapid Storage Technology, there is no loss of additional PCIe/system resources or add-in card slot/motherboard space footprint used compared to when a discrete RAID controller is implemented. Intel Rapid Storage Technology enterprise functionality requires the following items: 1. PCH SKU enabled for Intel Rapid Storage Technology enterprise (see Section 1.3) 2. Intel Rapid Storage Manager RAID Option ROM must be on the platform 3. Intel Rapid Storage Manager drivers, most recent revision. 4. At least two SATA hard disk drives (minimum depends on RAID configuration). Intel Rapid Storage Technology enterprise is not available in the following configurations: 1. The SATA controller is in compatible mode. 2. The SATA controller is programmed in RAID mode, but the AIE bit (D31:F2:Offset 9Ch bit 7) is set to 1. 5.17.7.1 Intel Rapid Storage Technology Manager RAID Option ROM The Intel Rapid Storage Technology Manager RAID Option ROM is a standard PnP Option ROM that is easily integrated into any System BIOS. When in place, it provides the following three primary functions: * Provides a text mode user interface that allows the user to manage the RAID configuration on the system in a pre-operating system environment. Its feature set is kept simple to keep size to a minimum, but allows the user to create and delete RAID volumes and select recovery options when problems occur. * Provides boot support when using a RAID volume as a boot disk. It does this by providing Int13 services when a RAID volume needs to be accessed by MS-DOS applications (such as NTLDR) and by exporting the RAID volumes to the System BIOS for selection in the boot order. * At each boot up, provides the user with a status of the RAID volumes and the option to enter the user interface by pressing CTRL-I. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 177 Functional Description 5.17.8 Power Management Operation Power management of the PCH SATA controller and ports will cover operations of the host controller and the SATA wire. 5.17.8.1 Power State Mappings The D0 PCI power management state for device is supported by the PCH SATA controller. SATA devices may also have multiple power states. From parallel ATA, three device states are supported through ACPI. They are: * D0 - device is working and instantly available. * D1 - device enters when it receives a STANDBY IMMEDIATE command. Exit latency from this state is in seconds * D3 - from the SATA device's perspective, no different than a D1 state, in that it is entered using the STANDBY IMMEDIATE command. However, an ACPI method is also called which will reset the device and then cut its power. Each of these device states are subsets of the host controller's D0 state. Finally, SATA defines three PHY layer power states, which have no equivalent mappings to parallel ATA. They are: * PHY READY - PHY logic and PLL are both on and active * Partial - PHY logic is powered, but in a reduced state. Exit latency is no longer than 10 ns * Slumber - PHY logic is powered, but in a reduced state. Exit latency can be up to 10 ms. Since these states have much lower exit latency than the ACPI D1 and D3 states, the SATA controller defines these states as sub-states of the device D0 state. 5.17.8.2 Power State Transitions 5.17.8.2.1 Partial and Slumber State Entry/Exit The partial and slumber states save interface power when the interface is idle. The SATA controller defines PHY layer power management (as performed using primitives) as a driver operation from the host side, and a device proprietary mechanism on the device side. The SATA controller accepts device transition types, but does not issue any transitions as a host. All received requests from a SATA device will be ACKed. When an operation is performed to the SATA controller such that it needs to use the SATA cable, the controller must check whether the link is in the Partial or Slumber states, and if so, must issue a COM_WAKE to bring the link back online. Similarly, the SATA device must perform the same action. 5.17.8.2.2 Device D1, D3 States These states are entered after some period of time when software has determined that no commands will be sent to this device for some time. The mechanism for putting a device in these states does not involve any work on the host controller, other then sending commands over the interface to the device. The command most likely to be used in ATA/ATAPI is the "STANDBY IMMEDIATE" command. 178 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.17.8.2.3 Host Controller D3HOT State After the interface and device have been put into a low power state, the SATA host controller may be put into a low power state. This is performed using the PCI power management registers in configuration space. There are two very important aspects to note when using PCI power management. 1. When the power state is D3, only accesses to configuration space are allowed. Any attempt to access the memory or I/O spaces will result in master abort. 2. When the power state is D3, no interrupts may be generated, even if they are enabled. If an interrupt status bit is pending when the controller transitions to D0, an interrupt may be generated. When the controller is put into D3, it is assumed that software has properly shut down the device and disabled the ports. Therefore, there is no need to sustain any values on the port wires. The interface will be treated as if no device is present on the cable, and power will be minimized. When returning from a D3 state, an internal reset will not be performed. 5.17.8.2.4 Non-AHCI Mode PME# Generation When in non-AHCI mode (legacy mode) of operation, the SATA controller does not generate PME#. This includes attach events (since the port must be disabled), or interlock switch events (using the SATAGP pins). 5.17.8.3 Intel(R) Scalable Memory Interconnect (Intel(R) SMI) Trapping (APM) Device 31:Function2:Offset C0h (see Section 14.1.41) control for generating SMI# on accesses to the IDE I/O spaces. These bits map to the legacy ranges (1F0-1F7h, 3F6h, 170-177h, and 376h) and native IDE ranges defined by PCMDBA, PCTLBA, SCMDBA an SCTLBA. If the SATA controller is in legacy mode and is using these addresses, accesses to one of these ranges with the appropriate bit set causes the cycle to not be forwarded to the SATA controller, and for an SMI# to be generated. If an access to the Bus-Master IDE registers occurs while trapping is enabled for the device being accessed, then the register is updated, an SMI# is generated, and the device activity status bits (Section 14.1.42) are updated indicating that a trap occurred. 5.17.9 SATA Device Presence In legacy mode, the SATA controller does not generate interrupts based on hot plug/ unplug events. However, the SATA PHY does know when a device is connected (if not in a partial or slumber state), and it s beneficial to communicate this information to host software as this will greatly reduce boot times and resume times. The flow used to indicate SATA device presence is shown in Figure 5-10. The `PxE' bit refers to PCS.P[3:0]E bits, depending on the port being checked and the `PxP' bits refer to the PCS.P[3:0]P bits, depending on the port being checked. If the PCS/PxP bit is set a device is present, if the bit is cleared a device is not present. If a port is disabled, software can check to see if a new device is connected by periodically re-enabling the port and observing if a device is present, if a device is not present it can disable the port and check again later. If a port remains enabled, software can periodically poll PCS.PxP to see if a new device is connected. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 179 Functional Description Figure 5-10. Flow for Port Enable / Device Present Bits 5.17.10 SATA LED The SATALED# output is driven whenever the BSY bit is set in any SATA port. The SATALED# is an active-low open-drain output. When SATALED# is low, the LED should be active. When SATALED# is high, the LED should be inactive. 5.17.11 AHCI Operation The PCH provides hardware support for Advanced Host Controller Interface (AHCI), a programming interface for SATA host controllers developed through a joint industry effort. AHCI defines transactions between the SATA controller and software and enables advanced performance and usability with SATA. Platforms supporting AHCI may take advantage of performance features such as no master/slave designation for SATA devices--each device is treated as a master--and hardware assisted native command queuing. AHCI also provides usability enhancements such as Hot-Plug. AHCI requires appropriate software support (such as, an AHCI driver) and for some features, hardware support in the SATA device or additional platform hardware. The PCH supports all of the mandatory features of the Serial ATA Advanced Host Controller Interface Specification, Revision 1.2 and many optional features, such as hardware assisted native command queuing, aggressive power management, LED indicator support, and Hot-Plug through the use of interlock switch support (additional platform hardware and software may be required depending upon the implementation). Note: 180 For reliable device removal notification while in AHCI operation without the use of interlock switches (surprise removal), interface power management should be disabled for the associated port. See Section 7.3.1 of the AHCI Specification for more information. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.17.12 SGPIO Signals The SGPIO signals, in accordance to the SFF-8485 specification, support per-port LED signaling. These signals are not related to SATALED#, which allows for simplified indication of SATA command activity. The SGPIO group interfaces with an external controller chip that fetches and serializes the data for driving across the SGPIO bus. The output signals then control the LEDs. This feature is only valid in AHCI/RAID mode. Intel does not validate all possible usage cases of this feature. Customers should validate their specific design implementation on their own platforms. 5.17.12.1 Mechanism The enclosure management for SATA Controller 1 (Device 31: Function 2) involves sending messages that control LEDs in the enclosure. The messages for this function are stored after the normal registers in the AHCI BAR, at Offset 580h bytes for PCH from the beginning of the AHCI BAR as specified by the EM_LOC global register (Section 14.4.1.6). Software creates messages for transmission in the enclosure management message buffer. The data in the message buffer should not be changed if CTL.TM bit is set by software to transmit an update message. Software should only update the message buffer when CTL.TM bit is cleared by hardware otherwise the message transmitted will be indeterminate. Software then writes a register to cause hardware to transmit the message or take appropriate action based on the message content. The software should only create message types supported by the controller, which is LED messages for PCH. If the software creates other non LED message types (such as SAF-TE, SES2), the SGPIO interface may hang and the result is indeterminate. During reset all SGPIO pins will be in tri-state state. The interface will continue to be in tri-state state after reset until the first transmission occurs when software programs the message buffer and sets the transmit bit CTL.TM. The SATA Host controller will initiate the transmission by driving SCLOCK and at the same time drive the SLOAD to `0' prior to the actual bit stream transmission. The Host will drive SLOAD low for at least 5 SCLOCK then only start the bit stream by driving the SLOAD to high. SLOAD will be driven high for 1 SCLOCK follow by vendor specific pattern that is default to "0000" if software has yet to program the value. A total of 21-bit stream from 7 ports (Port0, Port1, Port2, Port3, Port4 Port5 and Port6) of 3-bit per port LED message will be transmitted on SDATAOUT0 pin after the SLOAD is driven high for 1 SCLOCK. Only 3 ports (Port4, Port5 and Port6) of 9 bit total LED message follow by 12 bits of tri-state value will be transmitted out on SDATAOUT1 pin. All the default LED message values will be high prior to software setting them, except the Activity LED message that is configured to be hardware driven that will be generated based on the activity from the respective port. All the LED message values will be driven to `1' for the port that is unimplemented as indicated in the Port Implemented register regardless of the software programmed value through the message buffer. There are 2 different ways of resetting PCH SGPIO interface, asynchronous reset and synchronous reset. Asynchronous reset is caused by platform reset to cause the SGPIO interface to be tri-state asynchronously. Synchronous reset is caused by setting the CTL.RESET bit, clearing the GHC.AE bit or HBA reset, where Host Controller will complete the existing full bit stream transmission then only tri-state all the SGPIO pins. After the reset, both synchronous and asynchronous, the SGPIO pins will stay tristated. Note: PCH Host Controller does not ensure that it will cause the target SGPIO device or controller to be reset. Software is responsible to keep PCH SGPIO interface in tri-state for 2 second in order to cause a reset on the target of the SGPIO interface. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 181 Functional Description 5.17.12.2 Message Format Messages shall be constructed with a one DWord header that describes the message to be sent followed by the actual message contents. The first DWord shall be constructed as follows: Bit Description 31:28 Reserved 27:24 Message Type (MTYPE): Specifies the type of the message. The message types are: 0h = LED 1h = SAF-TE 2h = SES-2 3h = SGPIO (register based interface) All other values reserved 23:16 Data Size (DSIZE): Specifies the data size in bytes. If the message (enclosure services command) has a data buffer that is associated with it that is transferred, the size of that data buffer is specified in this field. If there is no separate data buffer, this field shall have a value of `0'. The data directly follows the message in the message buffer. For PCH, this value should always be `0'. 15:8 Message Size (MSIZE): Specifies the size of the message in bytes. The message size does not include the one DWord header. A value of `0' is invalid. For PCH, the message size is always 4 bytes. 7:0 Reserved The SAF-TE, SES-2, and SGPIO message formats are defined in the corresponding specifications, respectively. The LED message type is defined in Section 5.17.12.3. It is the responsibility of software to ensure the content of the message format is correct. If the message type is not programmed as 'LED' for this controller, the controller shall not take any action to update its LEDs. Note that for LED message type, the message size is always consisted of 4 bytes. 182 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.17.12.3 LED Message Type The LED message type specifies the status of up to three LEDs. Typically, the usage for these LEDs is activity, fault, and locate. Not all implementations necessarily contain all LEDs (for example, some implementations may not have a locate LED). The message identifies the HBA port number and the Port Multiplier port number that the slot status applies to. If a Port Multiplier is not in use with a particular device, the Port Multiplier port number shall be `0'. The format of the LED message type is defined in Table 5-45. The LEDs shall retain their values until there is a following update for that particular slot. Table 5-45. Multi-Activity LED Message Type Byte Description Value (VAL): This field describes the state of each LED for a particular location. There are three LEDs that may be supported by the HBA. Each LED has 3 bits of control. LED values are: 000b - LED shall be off 001b - LED shall be solid on as perceived by human eye All other values reserved The LED bit locations are: Bits 2:0 - Activity LED (may be driven by hardware) Bits 5:3 - Vendor Specific LED (such as, locate) 3-2 Bits 8:6 - Vendor Specific LED (such as, fault) Bits 15:9 - Reserved Vendor specific message is: Bit 3:0 - Vendor Specific Pattern Bit 15:4 - Reserved Note: If Activity LED Hardware Driven (ATTR.ALHD) bit is set, host will output the hardware LED value sampled internally and will ignore software written activity value on bit [2:0]. Since PCH Enclosure Management does not support port multiplier based LED message, the LED message will be generated independently based on respective port's operation activity. Vendor specific LED values Locate (Bits 5:3) and Fault (Bits 8:6) always are driven by software. Port Multiplier Information: Specifies slot specific information related to Port Multiplier. 1 Bits 3:0 specify the Port Multiplier port number for the slot that requires the status update. If a Port Multiplier is not attached to the device in the affected slot, the Port Multiplier port number shall be '0'. Bits 7:4 are reserved. PCH does not support LED messages for devices behind a Port MUltiplier. This byte should be 0. HBA Information: Specifies slot specific information related to the HBA. Bits 4:0 - HBA port number for the slot that requires the status update. 0 Bit 5 - If set to '1', Value is a vendor specific message that applies to the entire enclosure. If cleared to '0', Value applies to the port specified in bits 4:0. Bits 7:6 - Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 183 Functional Description 5.17.12.4 SGPIO Waveform Figure 5-11. Serial Data Transmitted over the SGPIO Interface 5.17.13 External SATA PCH supports external SATA. External SATA utilizes the SATA interface outside of the system box. The usage model for this feature must comply with the Serial ATA II Cables and Connectors Volume 2 Gold specification at www.sata-io.org. Intel validates two configurations: 1. The cable-up solution involves an internal SATA cable that connects to the SATA motherboard connector and spans to a back panel PCI bracket with an eSATA connector. A separate eSATA cable is required to connect an eSATA device. 2. The back-panel solution involves running a trace to the I/O back panel and connecting a device using an external SATA connector on the board. 184 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.18 SAS/SATA Controller Overview (SAS is for SRV/WS SKUs Only) Note: SAS is not available on HEDT. 5.18.1 SCU Features 5.18.1.1 Other Relevant Documents * ISO/IEC 14776-372, SCSI Enclosure Services-2 (SES-2) (INCITS T10/1559-D) * ISO/IEC 14776-453, SCSI Primary Commands-4 (SPC-4) * ISO/IEC 14776-322, SCSI Block Commands-3 (SBC-3) * ISO/IEC 14776-413, SCSI Architecture Model-4 (SAM-4) * ISO/IEC 14776-971, AT Attachment with Packet Interface-7 Volume 1 (ATA/ATAPI7 V1) (ANSI INCITS 397-2005) * ISO/IEC 14776-971, AT Attachment with Packet Interface-7 Volume 3 (ATA/ATAPI7 V3)(Serial ATA) (ANSI INCITS 397-2005) * Serial Attached SCSI (SAS) [ANSI INCITS 376-2003] * Serial Attached SCSI (SAS) revision 2.0r5 * Serial ATA: Data Link Interface revision 2.5 5.18.1.2 SCU Architectural Features The Storage Controller Unit is a stand alone I/O controller that supports Serial Attached SCSI (SAS) and Serial ATA (SATA) by incorporating dedicated messaging unit, DMA engines, frame buffering and protocol controllers to execute I/O requests. The Storage Controller Unit (SCU) supports execution of I/O requests for multiple modes of operations such as SSP, STP and SMP initiator and SATA host operations. Each of four SCU protocol engines can operate independently in any of the modes and can also execute SAS wide port operations. The SCU incorporates the following features: * Protocol Engine Group -- SSP, SMP, STP Initiator mode -- SATA Host mode -- SATA Port Selector (PS), Native Command Queueing (NCQ) supported -- Automated Out Of Band (OOB) signaling -- Automated Speed Negotiation (SN) -- Automated Transport Layer -- Automated Link Layer -- 1.5 Gbps and 3.0 Gbps Link operations for SAS and SATA -- Link Level Power Management -- Automated task scheduling -- Wide Ports up to x4 * Storage DMA Engine -- Automated Scatter Gather List processing -- Intel(R) Block Protection Technology Context management * End to End data path protection * using Parity, ECC and BPT Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 185 Functional Description 5.18.1.3 Features Excluded in Current SCU Architecture * STP Host/SATA Target functions * SSP Target Mode * SMP Target Mode * Bi-Directional SCSI commands support. * Multiple Task Priority Level - only support Normal and High. * Full Staggered spin-up in SATA devices (only support partial power on staggered spinup for SATA devices) * SAS Connection Multiplexing 5.18.2 SCU Configurations 5.18.2.1 SCU Configurations and Numbering Conventions There are two distinct configurations of the SCU: * Single SCU-4 * Double SCU-4 The Single SCU-4 is shown in Figure 5-12. Figure 5-12. Single SCU-4 Configuration Protocol Engine[3:0] Context RAM TC_RAM RNC_RAM SMU Transport Link Scheduler Scheduler Scheduler Scheduler Layer [3:0] Layer [3:0] IHSPI [3:0] A F E Phy [3:0] SAS / SATA Domain Host SDMA Port Task Scheduler Group Protocol Engine Group[0] FBMCU RxBuf TxBuf Storage Controller Unit [0] The single SCU-4 appears to the Driver as SCU[0]. There is a single Protocol Engine Group, PEG[0]. Within this Protocol Engine Group there are four Protocol Engines, PE[3:0], which connect to Phy[3:0]. There are four Port Task Schedulers (PTS), some of which are disabled depending on how the Driver configures it for Wide Port. Note that although the figure shows the SCU connecting to a SAS/SATA Domain, this could be direct-attached SAS or SATA disks. The next configuration is a Dual SCU-4, as shown in Figure 5-13. 186 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description Figure 5-13. Double SCU-4 Configuration Context RAM TC_RAM RNC_RAM SMU Protocol Engine[3:0] Transport Link Scheduler Scheduler Scheduler Scheduler Layer [3:0] Layer [3:0] IHSPI [3:0] A F E Phy [3:0] SAS / SATA Domain IHSPI [3:0] A F E Phy [7:4] SAS / SATA Domain Host Interface SDMA Port Task Scheduler Group Protocol Engine Group[0] FBMCU RxBuf TxBuf Common, Shared or Mirrored Config Registers Context RAM TC_RAM RNC_RAM SMU Storage Controller Unit [0] Protocol Engine[3:0] Transport Link Scheduler Scheduler Scheduler Scheduler Layer [3:0] Layer [3:0] Host Interface SDMA Port Task Scheduler Group Protocol Engine Group[0] FBMCU RxBuf TxBuf Storage Controller Unit [1] The Dual SCU-4 appears to the Driver as SCU[0] + SCU[1] behind a common PCIe function. Both SCUs are mapped behind a common set of PCIe BARs. Each SCU contains a single PEG. Note that on SCU[1] the Phys are numbered 4 thru 7 and the PEG is numbered as PEG[0]. The Intel C602 Chipset SKU includes a single SCU-4 to provide 4 ports of SATA. The Intel C604 Chipset SKU includes a single SCU-4 to provide 4 ports of SATA/SAS. The Intel C606, C608 Chipset SKUs includes a Dual SCU-4 that provides 8 ports of SATA/SAS. 5.18.2.1.1 Run-Time Configurations In addition to the other types of configurations, the Driver will be able to change the run-time configuration of the SCU. These allow the driver to configure a subset of features. At a high level these are: Protocol Support: Each link can be configured to support SSP, SMP, STP, or SATA. Wide Port Configuration:The PTS is configured to support Wide Ports. Transport Layer Retry: Support of TLR can be disabled for the part as a whole. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 187 Functional Description 5.18.3 Storage Controller Unit (SCU) Architecture The SCU Architecture can be divided into 4 major layers: * Host Queue/Memory Communication Interface which includes the Storage Messaging Unit (SMU) and the Storage DMA (SDMA) functional blocks * Port Task Scheduler Group which includes 4 Port Task Schedulers, Port Configuration Switch, Task Schedule RAM and Remote Node Schedule RAM * 4 Transport Layer functional blocks which are part of the Protocol Engine Group * 4 Link Layer functional blocks which are part of the Protocol Engine Group The Protocol Engine Group also includes the Context RAM Memory Controller (CRAMC) with Task Context (TC RAM) and Remote Node Context RAM (RNC RAM). The Frame Buffer Memory Controller Unit (FBMCU) with SRAM are used by the Transport Layer functional blocks for Tx and Rx frames buffers storage. The term "Task" is used throughout this document. Following description clarifies the kinds of Tasks the SCU supports. A Task can be one of the following types (TaskType): IORead: A request to perform an I/O Read as an initiator. IOWrite: A request to perform an I/O Write as an initiator. TaskMgmt: A request to perform a task management function, that is, a non-I/O task (initiator). RawFrame: A raw frame where the entire header is provided by the Driver. Primitive: A request to send a primitive outside of a connection. In addition to the TaskType, each Task will define the Protocol to use. Four different Protocol types are supported for a task: SMP: SMP supported for initiator. SSP: SSP supported for initiator STP/SATA: STP and SATA use the same protocol type, only initiator/host mode is supported. None: Used for sending primitives. The TaskType `Primitive' will support sending the following: * NOTIFY(POWER FAIL) * BROADCAST(SES) 188 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.18.3.1 SCU Theory of Operation The SCU Architectural terms and Definitions referenced in this document are defined below: * Task - a job issued by the driver to SCU to request SCU to perform some amount of work described with the associated task context information. * Local Port - a communication entity that contains one or more Transport Layer (TL)/Link Layer (LL) pairs that are associated with a single PTS. * Remote Node - a SAS or SATA device which can be communicated to using an SCU local port including SSP Initiator, Expander, SMP Initiator and SATA Device. * Index - a SCU internal addressing mechanism used to refer to data structure, memory, PTS or TL. -- Remote Node Index (RNi) - an index used by SCU to reference to data structure RNC associated to a remote device which can be communicated through the SCU port. -- Task Context Index (TCi) - an index used by the TL/SDMA to reference to data structure TC that contains all the information associated with the task execution. * Context - it is a data structure that usually resides in memory that contains all the necessary information for the functional block that is using the context to perform it's function.. -- Task Context (TC) - a data structure that contains all the necessary information for SCU to execute a task. -- Remote Node Context (RNC) - a data structure that contains all the necessary information about the characteristic of the remote node for SCU to manage connection and task execution. When the SCU is initialized and configured by the driver after power up and topology discovery, the driver assigns a task to the SCU in the form of a Task Context in a host work queue in host memory. The Task Context contains all the necessary information for the SCU to execute the entire task until completion or until terminated with an error posted in the host completion queue in host memory. The host driver will notify the Storage Messaging Unit (SMU) when a task is ready. The SMU will inform the Storage DMA Engine (SDMA) to fetch the Task Context (TC) from the host memory. The SDMA will load the TC into TC RAM as indexed by the TCi and at the same time transfer the Task Schedule portion of the context within the TC to the Port Task Scheduler (PTS). The Port Task Scheduler will link the task to the task list that is associated with the task under the corresponding Remote Node. The Port Task Scheduler will schedule the tasks based on a round robin algorithm. When a task is assigned to a Transport Layer function block, the TL will fetch the Task Context associated with the assigned task from the TC RAM using the CRAMC after the Link Layer Connection Manager establishes a connection to the remote node. The Link Layer is responsible for Link Initialization, Connection Management, Data Encoding/Decoding, Basic Frame Validation, elasticity-FIFO, Link Level Flow Control, Frame CRC-Generation/Verification, Data Scrambling/De-Scrambling, Primitive Sequence Management, Frame Building and Remote Node Context Management. The SAS Port Layer functions (such as wide port mapping) are managed by the Port Task Scheduler. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 189 Functional Description Figure 5-14. Storage Controller Block Diagram 5.18.3.2 SCU Functional Block Overview The functional blocks of the SCU are detailed in the following sub-sections. 5.18.3.2.1 SMU Overview The SMU (Storage Messaging Unit) provides the interface of the SCU to the Driver. The major functions of the SMU are as follows: * Allow the Driver to initiate new TCs to the SCU, the SMU then requests that the SDMA perform the actual DMA of the TCs * Manage the completion queue (which contains Task Completions, Unsolicited Frame Notifications, and Event Notifications) * Provide the locations in Host Memory to the TL where to put Unsolicited Frame payload and headers * Provide a means for all units to pass Event Notifications to the Driver * Allow the Driver to post new RNCs to the SCU * Coalesce interrupts to allow more efficient Driver use 190 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description In general the SMU is responsible for determining where in Host Memory a particular data element is stored and passes requests so that the SDMA can transfer between Host Memory and the appropriate internal data structure. Note that Host Memory is either system memory or RAID cache memory, depending on the usage model. 5.18.3.2.1.1 Memory Mapped Register (MMR) Interface The Memory Mapped Registers provide a way for the Driver to configure parameters throughout the SCU. The entire memory mapped register space is claimed by the SMU. Each PCI Function within the SMU consumes memory space for SMU control/status and the MSI-X Table and Pending Bit Array. These registers are mapped into PCI Memory Space through the Base Address Registers (SCUPBAR0, SRIOVBAR0). 5.18.3.2.1.2 Post Context Queue The "Post Context Queue" is used to pass new Tasks and Remote Node Contexts (TCs and RNCs) from the Driver to the SDMA. The value written includes the Context command Type, Protocol Engine Group Index (PEGi), Local Port Index (LPi) and Context Index (TCi/RNi). The valid Context commands are specified in Table 5-46. Table 5-46. Context Command Type Context Command Type Task Context Commands Post_TC Post_TC_Abort Dump_TC Remote Node Context Commands1 Post_RNC_32 Post_RNC_96 Post_RNC_Invalidate Dump_RNC_32 Dump_RNC_96 Post_RNC_Suspend Post_RNC_Resume Post_I_T_Nexus_Loss_Timer_Enable Post_I_T_Nexus_Loss_Timer_Disable 1. The RNC commands can only be posted through function 0. The Post_TC, Abort_TC, and Dump_TC commands all reference a Task Context index (TCi) and are referred to collectively as TC Commands. When posting a TC Command, the Driver will identify the Protocol Engine Group, Local Port, and provide a Task Context index (TCi). The Post_RNC, Dump_RNC, and Post_I_T_Nexus commands all reference a Remote Node index (RNi) and are referred to collectively as RNC Commands. When posting a RNC Command, the Driver will identify the Protocol Engine Group, Local Port, and provide a Remote Node Index (RNi). The Post_RNC_32/96 commands will result in an RNC data transfer from host memory to the RNC_RAM. The Dump_RNC_32/96 commands will result in an RNC data transfer from the RNC_RAM to host memory. The other commands operate on RNCs in the RNC_RAM but do not result in a data transfer to/from host memory. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 191 Functional Description Each Task Context is 256 bytes in size and is laid out in contiguous memory space A Remote Node Context is either 32 or 96 Bytes in size and will be laid out on 32 Byte aligned address offsets. The RNi indicates the starting address of the RNC in multiples of 32-bytes regardless of whether it is a 32-byte of 96-byte context. See Figure 5-15 as an example. Figure 5-15. RNC Sizes and Indexing Example 32 Bytes RNi = 0 RNi = 1 RNi = 2 RNi = 3 RNi = 0 RNi = 3 RNi = 4 RNi = 5 RNi = 6 RNi = 7 RNi = 8 Offset 288 (9x32) RNi = 0 RNi = 1 RNi = 2 96 Bytes RNi = 5 RNi = 6 RNi = 6 RNi = 9 RNi = 10 RNi = 11 RNi = 9 RNi = 9 RNi = 10 RNi = 11 Uniform 32 Byte RNC Uniform 96 Byte RNC Mixed 32/96 Byte RNC 5.18.3.2.1.3 Completion Queue The Completion Queue is located in host memory and is used as a circular queue for posting completions back to the Driver. After receiving notification from the other SCU units, the SMU puts a Completion Entry into the Completion Queue by directly issuing a 32-bit write. The Completion Entry can be one of the types shown in Table 5-47. Table 5-47. Completion Entry Format 3 1 3 0 C T=0 C T=1 C T=2 C T=3 Notification Code C T = 42 Event Code C T=5 C T=6 C T=7 2 8 2 7 2 4 2 3 1 8 Status Status Command 1 7 1 6 PEGi PEGi Command Status 1 2 1 1 0 LPi TCi Type Task Completion LPi TCi/RNi PEi RNi Unsolicited Frame Notification PEGi LPi/PEi1 TCi Critical Notification (such as, I_T_Nexus Time Out) PEGi LPi/PEi TCi/RNi Event Notification (can get dropped) LPi TCi/RNi SMU (PCQ) Events UFi Status 1 5 PEGi RegisterOffset/AM Reserved SDMA (CDMA) Completion SMU Generated Events Reserved 1. Events from the Transport and Link Layers will use PEi, events from the PTSG will use LPi 2. Type 4-7 are considered Events and will be discarded if there is no room in the Completion Queue for Events. Every completion entry contains a Cycle bit "C", a Type field "T" and a Protocol Engine Group index (PEGi). 192 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.18.3.2.2 SDMA Overview The SDMA (Storage DMA Unit) consists of two DMA channels: the Context DMA (CDMA) and the Payload DMA (PDMA). The CDMA consists of a CDMA Descriptor Manager (CDMA DM) and a CDMA Engine, and the PDMA consists of a PDMA Descriptor Manager (PDMA DM) and a PDMA Engine. Each DMA Engine consists of a Receive DMA Engine (writing to host memory) and a Transmit DMA Engine (reading from host memory). Note that in this document the term host memory is used to imply a memory subsystem outside of the SCU. The CDMA and PDMA Engines operate on descriptors. A descriptor describes a single DMA Engine operation between a host memory buffer and an SCU unit. The maximum DMA length that a descriptor can describe is up to 256 bytes and 1024 bytes for the CDMA and PDMA respectively. The CDMA or PDMA Descriptor Manager determines the DMA request type and generates a single descriptor or multiple descriptors with the proper source address, destination address and transfer length to define the DMA transfer operation either for receiving data (writing to host memory) or transmitting data (reading from host memory). Note that based on how the host memory buffers are described by the Scatter-Gather List (SGL), a single DMA request issued to the PDMA Descriptor Manager may yield multiple descriptors. When the CDMA or PDMA Engine operation is completed, the result of the operation is written to the Completion RAM of the CDMA or PDMA Engine for inspection and processing of the completion DWord by the CDMA or PDMA Descriptor Manager. 5.18.3.2.2.1 Intel(R) Block Protection Technology Unit An Intel Block Protection Technology Unit (BGU) is integrated on the Host output data path of the PDMA Engine to perform block guard operations on data from the Frame Buffer Memory Controller Unit (FBMCU)-to-Host. Similarly, a BGU is integrated on the FBMCU output data path of the PDMA Engine to perform block guard operations on data from Host-to-FBMCU. Each BGU is capable of the Generation, Stripping, Updating, and Verification of the Data Integrity fields (DIF) that can be embedded into the data streams. 5.18.3.2.3 SMCU Overview The Storage Controller Unit integrates two identical high performance, multi-ported SRAM Memory Controller units (SMCU). The first SMCU, called Frame Buffer Memory Controller Unit (FBMCU), is used to provide access to the on-chip frame buffer SRAM Memory. The second SMCU, called Context RAM Controller (CRAMC), is used to provide access to the on-chip context SRAM memory. The SRAM Memory Controller supports: * Error Correction Code (ECC) -- Single-bit error correction, multi-bit error detection -- 7-bit ECC across every DW data * Read-modify-write when the byte enables for DW data to write are not all asserted. * 256-bit wide SRAM Memory Interface with ECC protection * 10 Read and 10 Write, Memory Port Interfaces (MPI) -- Each MPI is 128-bit wide with data parity protection * Two request arbiters -- One for Read and one for Write requests * One MMR interface -- Decodes and accepts any MMR requests targeting the SMCU's MMR space * Interleave read and write requests in every other SRAM memory clock to minimize SRAM read latency Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 193 Functional Description The SRAM interface provides a direct connection to a high bandwidth and reliable memory subsystem. An 7-bit Error Correction Code (ECC) across every 32-bit word improves system reliability. 5.18.3.2.4 Port Task Scheduler Overview The key functions of the PTSG are to schedule outbound tasks to the appropriate protocol engine to be executed by transport layer and post status to the driver through SMU when the task is completed; manage SAS Port Layer functions, such as wide port management and I_T Nexus Loss timeout management; handle other functions like task timeout, task abortion, local port suspension, remote node suspension, etc. Each PTSG includes the following major functional blocks: * 4 Port Task Schedulers (PTS) - PTS schedules tasks to be executed by the TLs of the configured port. * 1 Port Configuration Switch (PCS) - This switch is configured by the Driver by programming the MMRs through SMU after link initialization to map the PEs to a particular PTS based on the information that was exchanged by the Identify Address Frames. * 1 Event Timeout Manager (ETM) - The Event Timeout Manager is responsible for checking any active task that has timed out and also monitoring the I_T Nexus timeout situation for the active remote node. * 1 Task Schedule Context RAM (TSC RAM) - this memory is used by all the PTSs within the PTSG to store TSCs for task scheduling. * 1 Remote Node Schedule Context RAM (RNSC RAM) - this memory is used by all the PTSs within the PTSG to store RNSCs for remote node scheduling. The PTSG also manages the SAS port layer function that handles the SAS Wide Port functionality. The PTS will ensure that the order of IO command frames sent to the target port (as an initiator) will be the same order as the tasks issued by the driver unless it is a high priority new command task. 5.18.3.2.5 Transport Layer Overview The transport layer consists of five major sub-modules in the SCU. They are: * Transport Layer Back End (TLBE) The Transport Layer Back End provides a shared interface between the SDMA and core TL blocks, and acts as a central arbiter for all Event Notifications within the Protocol Engine Group (PEG). * SSP Transport Layer Group (SSP TL) * SMP Transport Layer Group (SMP TL) * STP/SATA Transport Layer Group (STP TL) * Transport Layer Front End (TLFE) The Transport Layer Front End (TLFE) is located between the transport layers and link layers. Its main function is to provide Context RAM access arbitration between Transport and Link layer logic. 5.18.3.2.6 Link Layer Overview The SCU Protocol engine (PE) supports SSP, SMP, STP and SATA Link Layer protocol operations through a combination of protocol specific functions and common protocol functions. The link layer manages frame transmission, frame reception, encoding/ decoding of characters, connection management, primitive sequence detection and processing, and the protocol link flow control. The PE implements a common link layer architecture that enables each link to operate with any of the supported protocols based on OOB and connection assignments. The PE also implements a common Connection manager used to manage SSP, SMP and STP connections automatically. The 194 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description link layer for each protocol engine also has common Out of Band sequence and Speed Negotiation controls to perform SAS or SATA operations. The PE link layers interfaces to a common Frame Transmit and Frame Receive DMA controller that manages the movement of frame data to FBMCU and from the AFE. 5.18.3.2.6.1 PE Link Layer Features The following list of link layer functions are executed by the PE Link Layer. * Out of Band sequence handling * Speed Negotiation * Frame Transmission * Frame Reception * Primitive Generation/Detection -- SAS Primitive sequences -- SATA Primitive sequences * 8b10b ENDEC -- SAS characters -- SATA characters * Scrambling/de-scrambling -- SSP, SMP -- STP, SATA * SSP Link Layer functionality -- Initiator * SMP Link Layer functionality -- Initiator * STP/SATA Host Link Layer state machine * SAS Link Connection Control * Rate Matching * Flow Control -- SSP -- SATA * Frame Buffer data storage/retrieval * 1.5/3.0 Link rate support 5.18.3.2.6.2 PE Link Layer Theory of Operation After the SCU has been brought out of reset and the protocol transceivers have been initialized the PE link layer is prepared to start operations. The device driver will enable each protocol engine individually, this enable will start the automated link layer operations for Out of Band (OOB) sequences and Speed Negotiation (SN) to perform the Phy Reset Sequence. The OOB/SN manager will perform SAS OOB functions to detect if a SAS device or a SATA device is present. The OOB/SN manager also provides the mechanism for the device driver to initiate the transmission of the protocol based Port Selector switching sequence. The OOB/SN manager will further conduct SAS or SATA speed negotiation dependent upon the detection of a SAS PHY or SATA PHY. Link initialization can be initiated independently for each protocol engine by the device driver through a dedicated link initialization control register. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 195 Functional Description 5.18.3.2.7 Staggered Spin-Up Control The SCU needs supports Staggered Spin-Up as a feature, under the control of the Driver. This allows the Driver to stagger when drives are spun-up, thus avoiding any power surges that might overload a power supply. The process for handling Staggered Spin-Up for a nominal start-up procedure is as follows: 1. The Driver starts all links 2. On SATA links (detected by OOB), the LL will default to the SATA SPINUP HOLD state. 3. On SAS links, the LL completes the entire start-up sequence. By default, the LL will not send NOTIFY(ENABLE SPINUP) primitives. 4. The Driver walks through each link every X seconds (an OEM configured parameter), and sets LL registers to either start sending NOTIFY(ENABLE SPINUP) or release the link from the SPINUP HOLD state, depending on whether the link is SAS or SATA. 5.18.3.2.8 Discovery The discovery process begins after Link Initialization is complete. The Driver is responsible for discovering all SAS devices in the domain (determining the device type, SAS address, and supported protocols), and configuring the devices if necessary (that is, expander routing tables). 5.18.3.2.9 Port Configuration /SAS Address After power up, the driver will assign the SAS address - usually the same local SAS address (unless SCU is programmed to be SATA direct attached only) to all the links in the Local SAS Address register in the Connection Manager. 5.18.4 SCU Physical Layer/PHY Overview 5.18.4.1 Introduction The physical layer (Phy) integrated with the SCU is a four-port SAS/SATA transceiver (called the Storage Phy- SPhy) supporting 1.5 Gbps and 3.0 Gbps with an Analog frontend (AFE) and a Digital interface block (DIF). The PCH supports either a single instantiation of the Sphy or a dual instantiation of the SPhy. The DIF block contains the registers that control several aspects of the AFE. 5.18.4.2 SPhy Functionality & Features SPhy Features * Link rates of 1.5 Gbps and 3.0 Gbps. * Meets SAS and SATA industry electrical requirements at all of the supported rates. * BER of less than 1 x 10 -15 * 40-to-1 bit serializer and 1-to-40 bit de-serializer with embedded clock extraction. * Independent transceiver operation with respect to protocol and data rate. * Independent transmit and receive data rates on a per-transceiver basis; this mode is not part of normal SAS/SATA signaling, but it is utilized during speed negotiation. * On-chip termination. * Independent reset and power-down/enable controls for each receiver and each transmitter. 196 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description * OOB envelope detection with programmable threshold of OOB burst envelope amplitude on a per-transceiver basis. * Control for putting the transmitter into a DC idle state on a per-transceiver basis. * Several loop-back modes: far-end retimed (in protocol engine), far-end digital (in DIF), near-end analog (in AFE), and external analog (outside the package on the PC board) * 40-bit data path for each receiver and transmitter * Comma sequence detection and notification for the protocol engine to manage the link * Disabling and enabling of comma sequence detection * Spread-Spectrum Clocking (SSC) transmission is available on a per-transceiver basis for SATA. SSC is not available for SAS * Controls for entering and exiting SAS and SATA Partial and Slumber power management states on a per-transceiver basis 5.18.4.2.1 OOB Burst Detection and Control In order to support the SAS and SATA protocol signaling requirements, the protocol engine has ability to select OOB burst amplitude detection levels. 5.18.4.2.2 Transmit Amplitude Control The transmitter control block supports the SAS and SATA protocol signaling requirements by providing the protocol engine the ability to select transmitter amplitude transmission levels on a per-transmitter basis using the register interface and the table-based look-up structure of the transmitter. 5.18.4.2.3 Common Mode Voltage Control The transmitter control block supports a function that allows the protocol engine to individually place each transmitter into a DC idle state. The transmitter will place the transmitter output driver into DC idle condition until the protocol engine or dictates a transition into a new state. 5.18.4.2.4 Tx/Rx Bit Rate Selection The transceivers support 1.5, and 3.0 Gbps by providing independent transmitter and receiver rate selection control in each transceiver. This control also provides the ability to transmit at one bit rate and receive data at a different bit rate. 5.18.4.2.5 Comma Detection Enable/Disable The AFE receiver control block provides control to enable/disable notification to the protocol engine that it has detected a comma sequence in the de-serialized bit stream. This control also enables/disables the DWord alignment functions in the receiver control block allowing data to be transferred without interruption. 5.18.4.2.6 Reset and Power-Down The SPhy supports the ability to reset and power-down each transceiver unit independently. 5.18.4.2.7 Power Management States The SATA power management states of Partial and Slumber are supported. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 197 Functional Description 5.18.4.2.8 Tx/Rx Data Loop Back Modes The DIF block supports several modes and controls to loop-back data within the transceiver, thereby enabling the data stream between the transmitter and receiver to be connected to each other. The digital wrap back, near end analog loop-back, far end retimed loop-back, and far end digital loop-back capabilities are contained locally to each transceiver; the external analog loop-back may occur between transceivers depending upon HVM testing requirements. The DIF block supports controls to enable implementation of a far-end retimed loop back mode within the SAS/SATA protocol engine. 5.18.4.2.9 Reference Clocking Requirements The AFE common block develops the PLL output clocks for each of the transceiver blocks from a differential off-chip oscillator. The crystal oscillator shall be 100 MHz and shall not have spread-spectrum clocking (SSC). The SPhy could share this reference clock with any other interfaces on the same product as long as they do not require SSC. 5.18.5 Interrupts and Interrupt Coalescing There are two types of interrupts: Completion Queue Interrupt: This interrupt can occur whenever the completion queue is not empty. This interrupt is coalesced as explained below. Error Interrupt: 5.18.5.1 This interrupt indicates one or more error conditions have occurred which will impact the Driver and SCU operation. This causes an immediate interrupt. Interrupts The SMU implements support for both Legacy INTx interrupts and MSI-X interrupts.For a multi-function device, including an IOV aware device, the interrupt logic is replicated per function. 5.18.5.1.1 Legacy Interrupts PCI Express implements a legacy INTx virtual wire interrupt signaling mechanism that uses the Assert_INTx / Deassert_INTx semantics to convey the level sensitive nature of traditional INTx# interrupt pins. The "SCU PF Interrupt Pin Register (SCUPIPR)", (see Section 16.2.1.22)specifies which interrupt line is used for the normal runtime interrupt. 5.18.5.1.2 MSI-X Capability If a host processor enables Message-Signaled Interrupts (MSI-X), the SMU is responsible to signal interrupt to the host using a PCI write instead of generating an Assert_INTx PCI Express* message. The Interrupt Disable bit in the PCI Command Register does not affect the generation of MSI-X interrupts. 198 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description Figure 5-16. MSI-X Generation MSI-X Message Generation Normal Interrupt Pending Bit Array Edge Detect Logic Error Interrupt Function Mask Per Vector Mask SMU MSI-X Enable MSI-X Message To signal an Interrupt with MSI-X enabled, a memory write transaction will be created using the Message Address and the Message Data of the associated entry. 5.18.6 SMU Error and Event Generation The SMU is the only unit that will generate the Error interrupt. All other SCU units will signal detected `errors' using an `Event Notification'. 5.18.6.1 Event Generation For most errors, the SMU will generate an Event Notification using the affected Address Modifier to direct the event to the appropriate Completion Queue. Some events are directed to the physical function (PF) and are indicated in the description. The SMU generates the following errors: * Uncorrectable Error on read of PCQ (Uncorr_PCQ_Rd) This Event is generated by the Post Context Queue(PCQ) processing logic * Invalid Context Command Error (Invalid_Context_Cmd) This Event is generated by the Post Context Queue processing logic and is the result of an Invalid Context Command, an index out of range, or an RNC command by a Virtual Function. * Parity Error Detected on write to SMU (Uncorr_Reg_Wr) This error is detected by the MMR interface logic and is the result of receiving a PCIe poisoned TLP, or the result of internal parity corruption. * Uncorrectable error on read of HTTLBAR, HTTUBAR, and TCR or MSI-X MT_MLAR, MT_MUAR, and MT_MDR (Uncorr_Reg_Rd) Above registers are implemented in a RAM and a double-bit ECC error during a read of the Host Task Table or MSI-X registers will result in an event notification. The SMU also receives status information from the PCIe Interface and converts it to an event notification: * Function Level Reset (Function_Level_Reset) This is an indication that the Initiate FLR bit has been set in the PCIe Configuration Space of a VF. When a rising edge is detected on the FLR signal from the PCIe Configuration Space, the SMU will: -- Generate a Critical Notification to the physical function (PF). Note that an FLR to the PF will not generate an Event Notification. This event will also trigger the Function Level reset mechanism defined in Section 5.18.9. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 199 Functional Description 5.18.6.2 Error Interrupt * Uncorrectable Error on read of CQLBAR, or CQUBAR. Above registers are implemented in a RAM and a double-bit ECC error during a read of the Completion Queue BAR can not be signalled as an event. * Completion Queue Suspended This condition should not occur under normal operations and is likely the result of a programming error. 5.18.7 Host Interface Error Conditions The SCU adheres to the error conditions defined within the PCI Express* specification for both requester and completer operation. IOSF (PCH's On-Chip System Fabric) and PCI Express* error conditions cause the SCU to log header information and to set status bits to inform error handling code of the exact cause of the error condition. PCI Express* classifies errors as Correctable or Uncorrectable. Since all PCI Express* Correctable errors are link related (and the SCU does not contain a link) the SCU does not detect any PCI Express* Correctable errors (all errors are detected as Uncorrectable). The following is a simplified summary of the flow. The entire flow is outlined in detail in Figure 5-17. First determine the Severity of the Uncorrectable error (Fatal or Non-Fatal). The Severity of each error type is defined by the programming of bits in the "SCU PF PCI Express* Uncorrectable Error Severity (SCU P I ERRUNC SEV)" register. (see Section 16.2.5.4) * Fatal: Log (if enabled). Send ERR_FATAL message (if enabled). * Non-Fatal: Determine whether the error can be considered Advisory or not. This is done in an SCU implementation-specific manner. Errors are generally considered Advisory if the other party in the transaction is better suited to handling/reporting the error (such as, Unsupported Request) in a non-posted transaction (in this case the original requester will receive UR in the completion status and can decide what the appropriate error recovery/reporting mechanism should be). -- Advisory: Log (if enabled). Send ERR_COR message (if enabled). -- Non-Advisory: Log (if enabled). Send ERR_NONFATAL message (if enabled). 200 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description Figure 5-17. Uncorrectable Error Signalling and Logging Flowchart Uncorrectable Error Detected If UR, set Unsupported Request Detected bit in Device Status Reg [VFi **] Note: [VFi **] Unaffiliated: Use the [PF] Affiliated: Use appropriate [VFi] Determine the severity according to Uncorrectable Error Severity Reg [PF] Fatal Severity? Non-Fatal Advisory? Yes No Set Fatal Error Detected bit in Device Status Reg [VFi **] Set Non-Fatal Error Detected bit in Device Status Reg [VFi **] Set Correctable Error Detected bit in Device Status Reg [VFi **] Set Advisory-Non-Fatal bit in Correctable Error Status Reg [VFi **] Advisory Masked in Correctable Error Mask Reg [PF]? No Set corresponding bit in Uncorrectable Error Status Reg [VFi **] Masked in Uncorrectable Error Mask Reg [PF]? No Yes END Set corresponding bit in Uncorrectable Error Status reg [VFi **] Masked in Uncorrectable Error Mask Reg [PF]? Yes END Yes No If First Error Pointer [VFi **] not valid, update First Error Pointer [VFi **] and Header Log Reg [VFi **] If First Error Pointer [VFi **] not valid, update First Error Pointer [VFi **] and Header Log Reg [VFi **] (Error is UR AND DCR.URRE = 0 AND CMD.SERR_EN = 0) or Unaffiliated ? (Error is UR AND DCR.URRE= 0) or Unaffiliated ? Yes END No No Fatal (CMD.SERR_EN = 1 or DCR.FERE) = ? Yes Severity? No END Yes END Non-Fatal (CMD.SERR_EN = 1 or DCR.NERE) = ? Yes DCR.CERE = 1? Yes Send ERR_FATAL Msg Send ERR_NONFATAL Msg Send ERR_COR Msg END END END Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet No END 201 Functional Description The following sections detail all error conditions on the PCI Express/IOSF. 5.18.7.1 Unaffiliated Errors (Non-Function-Specific Errors) Unaffiliated errors are those which cannot be unambiguously associated with a single function. for example, a Memory transaction which misses all of the Memory BARs of all of the functions (PFs and VFs) in the endpoint. 5.18.7.1.1 Malformed Note that per the PCI Express* specification all malformed TLPs are treated as unaffiliated errors. The following checks are made to detect malformed TLPs. * Data Payload exceeds the length specified by the value in the Max_Payload_Size field of the Device Control Register. -- This error will be detected by the Integrated Device Fabric (IDF). * Transactions having reserved combinations of Fmt and Type Field, that is, all commands not in the following set: -- MRd32, MRd64, LTMRd32, LTMRd64, MRdLk32, MRdLk64, MWr32, MWr64, LTMWr32, LTMWr64, IORd, IOWr, CfgRd0, CfgWr0, CfgRd1, CfgWr1, Msg, MsgD, Cpl, CplD, CplLk, CpDLk -- The SCU instead handles this as an Unexpected Completion. 5.18.7.1.2 Unaffiliated Unsupported Requests (UR) The following checks are made to detect unaffiliated Unsupported Requests: * Memory or IO transactions which fail to match any of the active Memory or I/O BARs. * Configuration requests which fail to target a valid function. * Certain types of Messages which go unclaimed as stated in the rules in Section 5.18.8. 5.18.7.1.3 Unaffiliated Unexpected Completions The following checks are made to detect unaffiliated Unexpected Completions: * Completions in which the Requester ID (Bus#, Dev# Fn#) does not target any valid function (PF or VF). 5.18.7.2 Affiliated Errors (Function-Specific Errors) Affiliated errors are those which can be unambiguously associated with a single function. For example, a Memory transaction which hits a Memory BAR of a function (PF or VF) in the endpoint but violates the programming model of that function. Affiliated cases are handled entirely by the endpoint. 202 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.18.7.2.1 Affiliated Unsupported Requests (UR) The following checks are made to detect affiliated Unsupported Requests: * Certain types of Messages which are claimed but treated as UR as stated in the rules in Section 5.18.8. * Poisoned I/O or Configuration write request (EP bit set). * Configuration write with an IOSF data parity error. * Memory or I/O transaction while in a non-D0 power state. * MRdLk32/64, LTMrd32/64, LTMwr32/64 transactions. 5.18.7.2.2 Completer Abort (CA) Completer Aborts are transactions which violate the programming model of the SCU. The following checks are made to detect Completer Aborts: * Memory transactions which target the Memory Controllers and which cross a 16B aligned boundary. * Memory transactions which target the MSI-X table and which cross a 16B aligned boundary. * Memory transactions which target registers and which cross a 4B aligned boundary. These requests must first have passed the Malformed TLP checks as well as the Unsupported Request checks. 5.18.7.2.3 Affiliated Unexpected Completions Completions are considered affiliated when the Requester ID (Bus#, Dev# Fn#) targets a valid function (PF or VF). The following checks are made to detect affiliated Unexpected Completions. In all the following error cases the completion data is discarded (not sent to the SDMA). * The Tag does not match that of any outstanding non-posted request performed by the SCU as the Initiator. * TC /= 0. * The Status of a completion without data is other than Successful, CA or UR. * Locked Completions (CplLk, CplDLk). * Completion with data for which the length exceeds the remaining length expected for the outstanding non-posted request. 5.18.7.2.4 Poisoned Completion or Poisoned Posted Memory Write A completion or posted memory transaction is considered poisoned if the EP bit is set. * Poisoned Completions are passed through to the SDMA with bad parity. * Poisoned Memory Writes are passed through to the SMU with bad parity. Poisoned TLPs received for I/O or Configuration Writes are treated as URs. 5.18.7.2.5 Completion Timeout A completion timeout occurs when an outstanding non-posted request initiated by the SCU fails to receive all of its completion data within the completion timeout period (16 ms to 32 ms). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 203 Functional Description 5.18.7.3 Data Parity Error on the Integrated Device Fabric (IDF) Data parity will be forwarded to the internal units (SMU or SDMA). The SCU will indicate the error to the SCU driver. 5.18.8 Host Interface Messages Received The following sections describe how the SCU handles PCI-Express messages as a target. Any message which goes unclaimed by all enabled functions on the Integrated Device Fabric (IDF) will be logged in all enabled physical functions as an unaffiliated Unexpected Request (UR) with the exception of PME_TO. 5.18.8.1 Messages Routed by ID * If the Routing ID (RID) fails to match any enabled SCU function (PF or VF) then the SCU will not claim the transaction. * If the RID matches one of the enabled SCU functions, then the transaction will be claimed and: -- Type-1 Vendor Defined Messages (VDMs) are silently dropped. -- Others are dropped and are logged as UR. 5.18.8.2 Messages Routed by Broadcast * Type-1 VDMs are claimed and silently dropped. * UNLOCK is claimed and silently dropped. * PME_TO is not claimed. * Others are claimed, dropped and are logged as UR. 5.18.8.3 All other Messages All other message formats are not claimed by the SCU. 5.18.9 Reset 5.18.9.1 Fundamental Reset Fundamental Reset is a hardware mechanism for setting or returning the PCI Express* Port states and all MMR registers to their default condition. The fundamental reset can be generated through: * Primary Reset, or * Secondary Bus Reset 5.18.9.2 Function Level Reset (FLR) Function level reset is initiated by a configuration write which sets the Initiate FLR bit in "SCU VF PCI Express* Device Control Register x (SCU V I EXP DCTL x)" (VF, see Section 16.3.3.5) or "SCU PF PCI Express* Device Control Register (SCU P I EXP DCTL)" (PF, see Section 16.2.4.5). An FLR to a VF resets only that VF. Other VFs and the PF are unaffected (SR-IOV continues to operate). 204 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.18.9.2.1 Function Level Reset (Virtual Function) When the Initiate FLR bit is set, in the "SCU VF PCI Express* Device Control Register x (SCU V I EXP DCTL x)" (VF, see Section 16.3.3.5) the SMU will reset a subset of the VF MMR registers and generate an Event Notification to the master Driver in the physical function (PF) indicating that it should abort all outstanding tasks and re-initialize the VF. 5.18.9.2.2 Function Level Reset (Physical Function) When the Initiate FLR bit is set, in the "SCU PF PCI Express* Device Control Register (SCU P I EXP DCTL)" (PF, see Section 16.2.4.5) a hardware reset is asserted to all of the SCU (except for the IOSF interface). Therefore, the SMU, SDMA, and PEG are all reset. 5.18.10 SGPIO 5.18.10.1 Overview This chapter describes the Serial General Purpose Input Output (SGPIO) Unit that is used in the Storage Controller Unit (SCU). The SCU is organized into Protocol Engine Groups (PEGs). Each Protocol Engine Group (PEG) can support up to four Protocol Engines (PEs). Each PEG supports one SGPIO unit. The SGPIO unit also provides a feature that allows two PEGs to use a single SGPIO unit. However, this feature is only valid in SGPIO (serial) mode of operation. Therefore, the SGPIO unit can support up to eight devices. The SGPIO is a serial bus consisting of four signals: SClock, SLoad, SDataOut, and SDataIn. The SGPIO is used to serialize general purpose I/O signals. The SGPIO defines communication between an initiator and a target. The target typically converts output signals into multiple parallel LED signals and provides inputs from general purpose inputs. Figure 5-1 shows the SGPIO bus. A target typically consists of multiple devices, and SGPIO protocol allows each device on the target to support up to three output and three input signals. The SGPIO interface on the SCU can support up to eight devices (drives) on the target end. Each device can control up to three output bits and three input bits. Therefore, the SGPIO interface on the SCU can support up to twenty-four input signals and twentyfour output signals. Figure 5-18. SGPIO Bus Overview Device SClock SLoad Initiator Target SDataOut SDataIn Device Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 205 Functional Description 5.18.10.2 Theory of Operation The SGPIO is used to serialize general purpose I/O signals. For example, the initiator may want to drive multiple LEDs on the target, and thus do so by sampling and serializing the parallel initiator LED signals at a fixed sampling rate dictated by the lowto-high transition of the SLoad signal. Note that SClock is a free-running clock. The receiver (initiator or target) would then take the bit samples from the bit stream and converts them into parallel LED signals. Figure 5-19 shows the input and output bit streams relative to SClock and SLoad signals. Note that the SGPIO interface sends a repeating bit stream on SDataOut and receives a repeating bit stream SDataIn. The bit stream is restarted each time the SLoad signal is set high. Note that the example in Figure 5-19 shows four drives and five drives. The bit stream need not be the same length every time. Figure 5-19. SGPIO Repeating Bit Stream SClock Bit Stream Bit Stream SLoad Drive 0 Drive 1 Drive 2 Drive 3 Drive 0 Drive 1 Drive 2 Drive 3 Drive 4 SDataOut SDataIn 5.18.10.2.1 SGPIO SClock Output Signal SClock is a free-running clock running at a fixed frequency of up to 100 KHz. The rising edge of SClock is used to transmit SLoad, SDataOut, and SDataIn. The falling edge of SClock is used to latch SLoad, SDataOut, and SDataIn. 5.18.10.2.2 SGPIO SLoad Output Signal The initiator shall repeatedly send SDataOut bits and receives SDataIn bits. The SLoad signal indicates when the bit stream is ending or being restarted. After SLoad is asserted (set to 1), the next four bits positions on SLoad contain a vendor-specific pattern. Following the vendor-specific pattern, the initiator shall set the SLoad to 0 until it wants to restart the bits stream. Figure 5-20. SLoad Signal Bit 0 Vendor-Specific 1 206 Bit 1 Vendor-Specific Vendor-Specific Bit 2 Vendor-Specific Bit 3 Vendor-Specific .... 0's 1 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.18.10.2.3 SDataOut The SDataOut signal carries output bits associated with devices on the target. For example, on the SCU the SGPIO can drive up to three bits per device and up to eight devices on the target, thus is able to control twenty-four outputs on the target. The SDataOut signal carries the 3-bit outputs for each device in the same order in each repeated bit stream. Figure 5-21. SDataOut Signal Device 0 Bit0 Device 0 Bit1 Device 0 Bit2 Device1 Bit0 Device 0 Device1 Bit1 Device1 Bit2 .... Device N-1 Device N-1 Device N-1 Bit1 Bit0 Bit2 Device N-1 Device 1 5.18.10.2.4 SGPIO SDataIn Signal The SDataIn signal carries input bits associated with devices on the target. For example, on the SCU the SGPIO can receive up to three bits per device and up to eight devices on the target, thus is able to receive twenty-four inputs from the target. The SDataIn signal carries the 3-bit inputs for each device in the same order in each repeated bit stream. Figure 5-22. SDataIn Signal Device 0 Bit0 Device 0 Bit1 Device 0 Bit2 Device 1 Bit0 Device 0 5.18.10.3 Device 1 Bit1 Device 1 Device 1 Bit2 .... Device N-1 Device N-1 Device N-1 Bit1 Bit0 Bit2 Device N-1 Clock Requirements The SCU generates and drives three clock signals that are used to run the various blocks of the SGPIO units. * SClock - is the output clock of the SGPIO interface and runs at a either 49.9 KHz or 99.8 KHz. * Load Clock - this clock is used internally to load the internal latches. This clock runs at 1/12 or 1/24 the SClock rate. * Blink Generator Clock - this clock is used to drive the blink generator. This clock runs at 1/12500 of the SClock rate. Figure 5-23 shows the clock structure. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 207 Functional Description Figure 5-23. Clock Structure 1/12500 8 Hz Blink Rate Generator 1/24 Drives Latches 1/12 Bit 2 of SGICRx 1/2 49.9 KHz 150 MHz 99.8 KHz 1/1503 SClock Bit 1 of SGICRx 5.18.10.4 Output Signals The SGPIO unit can support up to eight drives, and each drive can support up to three output signals. This allows the SGPIO unit to be able to drive up to twenty-four output signals. The SGPIO supports the following output signals: * Fixed High * PE Activity, PE Status, or Reserved * Two programmable Blinks (A and B) In addition the outputs can be optionally inverted. Each output bit can be independently selected using the "SGPIO Output Data Select Register[0:7]". The selected output can in turn be inverted by software driver using the "SGPIO Output Data Select Register[0:7]". Figure 5-24, Figure 5-25, and Figure 5-26 respectively show the three output signals supported per drive (OD0, OD1, and OD2) and the supported output signal selections. 208 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description Figure 5-24. SGPIO Output OD0 Signal Output Signal (OD0) Control bit 3 in SGODSR[0:7]x JOG Logic Inverting Logic (XOR) Control bit 2 in SGODSR[0:7]x Control bits[1:0] in SGODSR[0:7]x Fixed High Pre-Conditioning Logic FSENG Activity Programmable Pattern A Programmable Pattern B Figure 5-25. SGPIO Output OD1 Signal Output Signal (OD1) JOG Logic Inverting Logic (XOR) Control bit 7 in SGODSR[0:7]x Control bit 6 in SGODSR[0:7]x Control bits[5:4] in SGODSR[0:7]x Fixed High Pre-Conditioning Logic FSENG Status Programmable Pattern A Programmable Pattern B Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 209 Functional Description Figure 5-26. SGPIO Output OD2 Signal Output Signal (OD2) Control bit 11 in SGODSR[0:7]x JOG Logic Inverting Logic (XOR) Control bit 10 in SGODSR[0:7]x Control bits[9:8] in SGODSR[0:7]x Fixed High Pre-Conditioning Logic Reserved Programmable Pattern A Programmable Pattern B 5.18.10.5 SCU Input Signals Each SCU PEG (Protocol Engine Group) supports one SGPIO unit. And each PEG can support up to four PEs (Protocol Engines). The SGPIO unit is designed to accommodate up to two PEGs (eight PEs). For example, the SGPIO unit can support eight sets of drives inputs. Note that each drive input set supports three inputs OD[2:0]. The lower four sets of drive inputs are driven by the local PEG, whereas the upper four sets of drive inputs are driven by the other PEG (or other SCU). Each PE drives two signals: activity (PE_ACT) and status (PE_STAT). Each PE_ACT/PE_STAT pair is driven to one of the SGPIO unit drive inputs. These PE activity and status signals can be selected as optional output signals of the SGPIO unit that can be driven serially on the SDataOut pin or on the direct LED signals. Refer to Figure 5-24 and Figure 5-25 for the output selections. Table 5-48 shows how the input signals are mapped to the ODx inputs of the SGPIO unit. Table 5-48. SGPIO Input Mapping (Sheet 1 of 2) Input Signals SGPIOx Inputs Fixed High PE Activity [0] Programmable Pattern A Drive0.OD0 Other PEG, PE Activity [0] Programmable Pattern A Programmable Pattern B Programmable Pattern B Fixed High Programmable Pattern A Programmable Pattern B SGPIOx Inputs Fixed High Fixed High PE Status [0] 210 Input Signals Drive0.OD1 Other PEG, PE Status [0] Programmable Pattern A Drive4.OD0 Drive4.OD1 Programmable Pattern B Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description Table 5-48. SGPIO Input Mapping (Sheet 2 of 2) Input Signals SGPIOx Inputs Fixed High Reserved Programmable Pattern A Input Signals Fixed High Drive0.OD2 Reserved Programmable Pattern A Programmable Pattern B Programmable Pattern B Fixed High Fixed High PE Activity [1] Programmable Pattern A Drive1.OD0 Other PEG, PE Activity [1] Programmable Pattern A Programmable Pattern B Programmable Pattern B Fixed High Fixed High PE Status [1] Programmable Pattern A Drive1.OD1 Other PEG, PE Status [1] Programmable Pattern A Programmable Pattern B Programmable Pattern B Fixed High Fixed High Reserved Programmable Pattern A Drive1.OD2 Reserved Programmable Pattern A Programmable Pattern B Programmable Pattern B Fixed High Fixed High PE Activity [2] Programmable Pattern A Drive2.OD0 Other PEG, PE Activity [2] Programmable Pattern A Programmable Pattern B Programmable Pattern B Fixed High Fixed High PE Status [2] Programmable Pattern A Drive2.OD1 Other PEG, PE Status [2] Programmable Pattern A Programmable Pattern B Programmable Pattern B Fixed High Fixed High Reserved Programmable Pattern A Drive2.OD2 Reserved Programmable Pattern A Programmable Pattern B Programmable Pattern B Fixed High Fixed High PE Activity [3] Programmable Pattern A Drive3.OD0 Other PEG, PE Activity [3] Programmable Pattern A Programmable Pattern B Programmable Pattern B Fixed High Fixed High PE Status [3] Programmable Pattern A Drive3.OD1 Other PEG, PE Status [3] Programmable Pattern A Programmable Pattern B Programmable Pattern B Fixed High Fixed High Reserved Programmable Pattern A SGPIOx Inputs Drive3.OD2 Programmable Pattern B Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Reserved Programmable Pattern A Drive4.OD2 Drive5.OD0 Drive5.OD1 Drive5.OD2 Drive6.OD0 Drive6.OD1 Drive6.OD2 Drive7.OD0 Drive7.OD1 Drive7.OD2 Programmable Pattern B 211 Functional Description 5.18.10.5.1 JOG Requirements The jog feature is optional and is controlled by the "SGPIO Output Data Select Register[0:7]". When enabled, this feature monitors the input signal and if the input signal is detected low for about 4 seconds it will be forced high for a 250 ms duration. 5.18.10.5.2 SCU Drive Pre-Conditioning Requirements All the SCU activity and status signals are pre-conditioned when entering the SGPIO units. The pre-conditioning logic monitors for any short pulse or any high frequency input signal and ensures that the input signal is stretched and held high for at least 125 ms. 5.18.10.5.3 Programmable Blink Patterns Each of the SGPIO output signal supports two programmable blink patterns that can be selected using the "SGPIO Output Data Select Register[0:7]". The blink rate generator is clocked using an 8 Hz clock and allows the user to program a low and a high duration time using two 4-bit fields located in the "SGPIO Programmable Blink Register. The shortest low/high duration time that can be program is 125 milliseconds and the longest low/high duration time that can be programmed is 2 seconds. The shortest blink rate period is 250 milliseconds and the longest blink rate period is 4 seconds. 5.18.10.6 SGPIO Serializer Modes of Operations The SGPIO serializer supports the following modes simultaneously: * Direct (parallel) LED mode (up to 8 LEDs; Drives[3:0], OD[1:0]) * SGPIO (serial) mode (up to 24 LEDs; Drives[7:0], OD[2:0]) The SGPIO serializer requires up to 8 pins to support the direct drive mode and 4 pins to support the serial mode of operation. A Drive-Position multiplexer block provides the ability to route any input Drive number to any output Drive number before being driven to the shift register and to the direct LED signals (refer to Figure 5-27). Note, all three signals of a Drive are routed simultaneously. Note that the SGPIO unit can support up to 3 LEDs per PE and up to eight PEs in SGPIO (serial) mode. However, the Direct parallel LED mode can only support 2 LEDs per PE and four PEs. 212 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description Figure 5-27. Output Signal Routing To SDataOut Shift Register Bit 23 Bit 22 Bit 21 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 2 Bit 1 Bit 0 OD1 OD0 To Direct LED Signals OD1 OD0 Output 7 Output 4 OD2 OD1 OD0 Bit 23 Bit 22 Bit 21 OD2 OD1 Bit 14 Bit 13 Output 3 Output 0 OD0 OD2 OD1 OD0 OD2 OD1 OD0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 2 Bit 1 Bit 0 Control bits from SGSDRx Multiplexer Block (Drive Position Selector) 24x (8-to-1) Bit 23 OD2 Bit 22 OD1 Bit 21 Bit 14 Bit 13 OD0 OD2 OD1 Input 7 Other PEG PE3 Bit 12 OD0 Bit 11 Bit 10 Bit 9 Bit 2 Bit 1 OD2 OD1 OD0 OD2 OD1 Input 4 Input 3 Input 0 Other PEG PE0 PE3 PE0 Bit 0 OD0 Note 1: Only OD0 and OD1 of the lower four sets of the Multiplexer Block outputs are driven to the Direct LED pins. Note 2: The Multiplexer Block only allows steering an entire Input X set to an Output Y set. 5.18.10.7 Serial Pin Multiplexing The SGPIO unit's serial pins also support a Direct (parallel) Activity LED mode. Figure 5-28 shows how the SGPIO unit signals are used and multiplexed. Bit 0 of the "SGPIO Interface Control Register" is used to select between the SGPIO (serial) mode and the direct Activity LED (parallel) mode, and by default bit 0 selects the parallel mode. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 213 Functional Description Figure 5-28. SCU SGPIO Unit Pin Mapping SGPIO Unit ACT[0] S_ACT[0] / S_A_CLOCK Control bit 0 of the SGICCR0 Register SCLOCK ACT[1] S_ACT[1] / S_A_LOAD SLOAD PE_STAT[1] PE_STAT[2] PE_STAT[3] PE_ACT[0] Dr4 OD1 in SCLOCK Dr5 OD1 in SLOAD Dr4 OD0 in ACT[3] PE_ACT[1] Dr5 OD0 in Dr6 OD0 in PE_ACT[3] Dr7 OD0 in PE_STAT[0] PE_STAT[1] PE_STAT[2] PE_STAT[3] PE_ACT[0] PE_ACT[2] PE_ACT[3] S_ACT[3] / S_A_DATAOUT SDATAOUT Dr0 OD1 in Dr0 OD1 out Dr1 OD1 in Dr1 OD1 out Dr2 OD1 in Dr2 OD1 out Dr3 OD1 in Dr3 OD1 out Dr0 OD0 in Dr0 OD0 out Dr1 OD0 in Dr1 OD0 out Dr2 OD0 in Dr2 OD0 out Dr3 OD0 in Dr3 OD0 out PE_ACT[1] S_ACT[2] / S_A_DATAIN SDATAOUT Dr7 OD1 in PE_ACT[2] ACT[2] 1 Dr6 OD1 in STAT[0] STAT[1] STAT[2] STAT[3] ACT[0] ACT[1] Direct LED Signals Other PEG/SCU Signals PE_STAT[0] ACT[2] ACT[3] Default Mapping of input to output for Direct LED 5.19 High Precision Event Timers (HPET) This function provides a set of timers that can be used by the operating system. The timers are defined such that in the future, the operating system may be able to assign specific timers to be used directly by specific applications. Each timer can be configured to cause a separate interrupt. PCH provides eight timers. The timers are implemented as a single counter, and each timer has its own comparator and value register. The counter increases monotonically. Each individual timer can generate an interrupt when the value in its value register matches the value in the main counter. The registers associated with these timers are mapped to a memory space (much like the I/O APIC). However, it is not implemented as a standard PCI function. The BIOS reports to the operating system the location of the register space. The hardware can support an assignable decode space; however, the BIOS sets this space prior to handing it over to the operating system. It is not expected that the operating system will move the location of these timers once it is set by the BIOS. 5.19.1 Timer Accuracy 1. The timers are accurate over any 1 ms period to within 0.05% of the time specified in the timer resolution fields. 2. Within any 100 microsecond period, the timer reports a time that is up to two ticks too early or too late. Each tick is less than or equal to 100 ns, so this represents an error of less than 0.2%. 3. The timer is monotonic. It does not return the same value on two consecutive reads (unless the counter has rolled over and reached the same value). 214 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description The main counter is clocked by the 14.31818 MHz clock, synchronized into the 66.666 MHz domain. This results in a non-uniform duty cycle on the synchronized clock, but does have the correct average period. The accuracy of the main counter is as accurate as the 14.31818 MHz clock. 5.19.2 Interrupt Mapping The interrupts associated with the various timers have several interrupt mapping options. When reprogramming the HPET interrupt routing scheme (LEG_RT_CNF bit in the General Configuration Register), a spurious interrupt may occur. This is because the other source of the interrupt (8254 timer) may be asserted. Software should mask interrupts prior to clearing the LEG_RT_CNF bit. Mapping Option #1 (Legacy Replacement Option) In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is set. This forces the mapping found in Table 5-49. Table 5-49. Legacy Replacement Routing Timer 8259 Mapping APIC Mapping 0 IRQ0 IRQ2 In this case, the 8254 timer will not cause any interrupts 1 IRQ8 IRQ8 In this case, the RTC will not cause any interrupts. 2&3 Per IRQ Routing Field. Per IRQ Routing Field 4, 5, 6, 7 not available not available Note: Comment The Legacy Option does not preclude delivery of IRQ0/IRQ8 using processor message interrupts. Mapping Option #2 (Standard Option) In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is 0. Each timer has its own routing control. The interrupts can be routed to various interrupts in the 8259 or I/O APIC. A capabilities field indicates which interrupts are valid options for routing. If a timer is set for edge-triggered mode, the timers should not be share with any PCI interrupts. For the PCH, the only supported interrupt values are as follows: Timer 0 and 1: IRQ20, 21, 22 & 23 (I/O APIC only). Timer 2: IRQ11 (8259 or I/O APIC) and IRQ20, 21, 22 & 23 (I/O APIC only). Timer 3: IRQ12 (8259 or I/O APIC) and IRQ 20, 21, 22 & 23 (I/O APIC only). Interrupts from Timer 4, 5, 6, 7 can only be delivered using processor message interrupts. Mapping Option #3 (Processor Message Option) In this case, the interrupts are mapped directly to processor messages without going to the 8259 or I/O (x) APIC. To use this mode, the interrupt must be configured to edgetriggered mode. The Tn_PROCMSG_EN_CNF bit must be set to enable this mode. When the interrupt is delivered to the processor, the message is delivered to the address indicated in the Tn_PROCMSG_INT_ADDR field. The data value for the write cycle is specified in the Tn_PROCMSG_INT_VAL field. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 215 Functional Description Notes: 1. The processor message interrupt delivery option has HIGHER priority and is mutually exclusive to the standard interrupt delivery option. Thus, if the Tn_PROCMSG_EN_CNF bit is set, the interrupts will be delivered directly to the processor rather than via the APIC or 8259. 2. The processor message interrupt delivery can be used even when the legacy mapping is used. 3. The IA-PC HPET Specification uses the term "FSB Interrupt" to describe these type of interrupts. 5.19.3 Periodic versus Non-Periodic Modes Non-Periodic Mode Timer 0 is configurable to 32 (default) or 64-bit mode, whereas Timers 1:7 only support 32-bit mode (See Section 21.1.5). Warning: Software must be careful when programming the comparator registers. If the value written to the register is not sufficiently far in the future, then the counter may pass the value before it reaches the register and the interrupt will be missed. The BIOS should pass a data structure to the OS to indicate that the OS should not attempt to program the periodic timer to a rate faster than 5 microseconds. All of the timers support non-periodic mode. Refer to Section 2.3.9.2.1 of the IA-PC HPET Specification for more details of this mode. Periodic Mode Timer 0 is the only timer that supports periodic mode. Refer to Section 2.3.9.2.2 of the IA-PC HPET Specification for more details of this mode. If the software resets the main counter, the value in the comparator's value register needs to reset as well. This can be done by setting the TIMERn_VAL_SET_CNF bit. Again, to avoid race conditions, this should be done with the main counter halted. The following usage model is expected: 1. Software clears the ENABLE_CNF bit to prevent any interrupts 2. Software Clears the main counter by writing a value of 00h to it. 3. Software sets the TIMER0_VAL_SET_CNF bit. 4. Software writes the new value in the TIMER0_COMPARATOR_VAL register 5. Software sets the ENABLE_CNF bit to enable interrupts. The Timer 0 Comparator Value register cannot be programmed reliably by a single 64-bit write in a 32-bit environment except if only the periodic rate is being changed during run-time. If the actual Timer 0 Comparator Value needs to be reinitialized, then the following software solution will always work regardless of the environment: 1. Set TIMER0_VAL_SET_CNF bit 2. Set the lower 32 bits of the Timer0 Comparator Value register 3. Set TIMER0_VAL_SET_CNF bit 4. Set the upper 32 bits of the Timer0 Comparator Value register 216 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.19.4 Enabling the Timers The BIOS or operating system PnP code should route the interrupts. This includes the Legacy Rout bit, Interrupt Rout bit (for each timer), and interrupt type (to select the edge or level type for each timer) The Device Driver code should do the following for an available timer: 1. Set the Overall Enable bit (Offset 10h, bit 0). 2. Set the timer type field (selects one-shot or periodic). 3. Set the interrupt enable 4. Set the comparator value 5.19.5 Interrupt Levels Interrupts directed to the internal 8259s are active high. See Section 5.10 for information regarding the polarity programming of the I/O APIC for detecting internal interrupts. If the interrupts are mapped to the 8259 or I/O APIC and set for level-triggered mode, they can be shared with PCI interrupts. They may be shared although it's unlikely for the operating system to attempt to do this. If more than one timer is configured to share the same IRQ (using the TIMERn_INT_ROUT_CNF fields), then the software must configure the timers to leveltriggered mode. Edge-triggered interrupts cannot be shared. 5.19.6 Handling Interrupts Section 2.4.6 of the IA-PC HPET Specification describes Handling Interrupts. 5.19.7 Issues Related to 64-Bit Timers with 32-Bit Processors Section 2.4.7 of the IA-PC HPET Specification describes Issues Related to 64-Bit Timers with 32-Bit Processors. 5.20 USB EHCI Host Controllers (D29:F0 and D26:F0) The PCH contains two Enhanced Host Controller Interface (EHCI) host controllers which support up to fourteen USB 2.0 high-speed root ports. USB 2.0 allows data transfers up to 480 Mb/s. USB 2.0 based Debug Port is also implemented in the PCH. 5.20.1 EHC Initialization The following descriptions step through the expected PCH Enhanced Host Controller (EHC) initialization sequence in chronological order, beginning with a complete power cycle in which the suspend well and core well have been off. 5.20.1.1 BIOS Initialization BIOS performs a number of platform customization steps after the core well has powered up. Contact your Intel Field Representative for additional PCH BIOS information. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 217 Functional Description 5.20.1.2 Driver Initialization See Chapter 4 of the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0. 5.20.1.3 EHC Resets In addition to the standard PCH hardware resets, portions of the EHC are reset by the HCRESET bit and the transition from the D3HOT device power management state to the D0 state. The effects of each of these resets are: Reset Does Reset Does not Reset Comments HCRESET bit set. Memory space registers except Structural Parameters (which is written by BIOS). Configuration registers. The HCRESET must only affect registers that the EHCI driver controls. PCI Configuration space and BIOS-programmed parameters can not be reset. Software writes the Device Power State from D3HOT (11b) to D0 (00b). Core well registers (except BIOSprogrammed registers). Suspend well registers; BIOSprogrammed core well registers. The D3-to-D0 transition must not cause wake information (suspend well) to be lost. It also must not clear BIOS-programmed registers because BIOS may not be invoked following the D3-to-D0 transition. If the detailed register descriptions give exceptions to these rules, those exceptions override these rules. This summary is provided to help explain the reasons for the reset policies. 5.20.2 Data Structures in Main Memory See Section 3 and Appendix B of the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 for details. 5.20.3 USB 2.0 Enhanced Host Controller DMA The PCH USB 2.0 EHC implements three sources of USB packets. They are, in order of priority on USB during each microframe: 1. The USB 2.0 Debug Port (see Section USB 2.0 Based Debug Port), 2. The Periodic DMA engine, and 3. The Asynchronous DMA engine. The PCH always performs any currently-pending debug port transaction at the beginning of a microframe, followed by any pending periodic traffic for the current microframe. If there is time left in the microframe, then the EHC performs any pending asynchronous traffic until the end of the microframe (EOF1). Note that the debug port traffic is only presented on Port 1 and Port 9, while the other ports are idle during this time. 5.20.4 Data Encoding and Bit Stuffing See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0. 5.20.5 Packet Formats See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0. 218 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description The PCH EHCI allows entrance to USB test modes, as defined in the USB 2.0 specification, including Test J, Test Packet, etc. However note that the PCH Test Packet test mode interpacket gap timing may not meet the USB 2.0 specification. 5.20.6 USB 2.0 Interrupts and Error Conditions Section 4 of the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 goes into detail on the EHC interrupts and the error conditions that cause them. All error conditions that the EHC detects can be reported through the EHCI Interrupt status bits. Only PCH-specific interrupt and error-reporting behavior is documented in this section. The EHCI Interrupts Section must be read first, followed by this section of the datasheet to fully comprehend the EHC interrupt and error-reporting functionality. * Based on the EHC Buffer sizes and buffer management policies, the Data Buffer Error can never occur on the PCH. * Master Abort and Target Abort responses from hub interface on EHC-initiated read packets will be treated as Fatal Host Errors. The EHC halts when these conditions are encountered. * The PCH may assert the interrupts which are based on the interrupt threshold as soon as the status for the last complete transaction in the interrupt interval has been posted in the internal write buffers. The requirement in the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 (that the status is written to memory) is met internally, even though the write may not be seen on DMI before the interrupt is asserted. * Since the PCH supports the 1024-element Frame List size, the Frame List Rollover interrupt occurs every 1024 milliseconds. * The PCH delivers interrupts using PIRQH#. * The PCH does not modify the CERR count on an Interrupt IN when the "Do Complete-Split" execution criteria are not met. * For complete-split transactions in the Periodic list, the "Missed Microframe" bit does not get set on a control-structure-fetch that fails the late-start test. If subsequent accesses to that control structure do not fail the late-start test, then the "Missed Microframe" bit will get set and written back. 5.20.6.1 Aborts on USB 2.0-Initiated Memory Reads If a read initiated by the EHC is aborted, the EHC treats it as a fatal host error. The following actions are taken when this occurs: * The Host System Error status bit is set * The DMA engines are halted after completing up to one more transaction on the USB interface * If enabled (by the Host System Error Enable), then an interrupt is generated * If the status is Master Abort, then the Received Master Abort bit in configuration space is set * If the status is Target Abort, then the Received Target Abort bit in configuration space is set * If enabled (by the SERR Enable bit in the function's configuration space), then the Signaled System Error bit in configuration bit is set. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 219 Functional Description 5.20.7 USB 2.0 Power Management 5.20.7.1 Pause Feature This feature allows platforms to dynamically enter low-power states during brief periods when the system is idle (that is, between keystrokes). This is useful for enabling power management features in the PCH. The policies for entering these states typically are based on the recent history of system bus activity to incrementally enter deeper power management states. Normally, when the EHC is enabled, it regularly accesses main memory while traversing the DMA schedules looking for work to do; this activity is viewed by the power management software as a non-idle system, thus preventing the power managed states to be entered. Suspending all of the enabled ports can prevent the memory accesses from occurring, but there is an inherent latency overhead with entering and exiting the suspended state on the USB ports that makes this unacceptable for the purpose of dynamic power management. As a result, the EHCI software drivers are allowed to pause the EHC DMA engines when it knows that the traffic patterns of the attached devices can afford the delay. The pause only prevents the EHC from generating memory accesses; the SOF packets continue to be generated on the USB ports (unlike the suspended state). 5.20.7.2 Suspend Feature The Enhanced Host Controller Interface (EHCI) For Universal Serial Bus Specification, Section 4.3 describes the details of Port Suspend and Resume. 5.20.7.3 ACPI Device States The USB 2.0 function only supports the D0 and D3 PCI Power Management states. Notes regarding the PCH implementation of the Device States: 1. The EHC hardware does not inherently consume any more power when it is in the D0 state than it does in the D3 state. However, software is required to suspend or disable all ports prior to entering the D3 state such that the maximum power consumption is reduced. 2. In the D0 state, all implemented EHC features are enabled. 3. In the D3 state, accesses to the EHC memory-mapped I/O range will master abort. Note that, since the Debug Port uses the same memory range, the Debug Port is only operational when the EHC is in the D0 state. 4. In the D3 state, the EHC interrupt must never assert for any reason. The internal PME# signal is used to signal wake events, and so forth. 5. When the Device Power State field is written to D0 from D3, an internal reset is generated. See section EHC Resets for general rules on the effects of this reset. 6. Attempts to write any other value into the Device Power State field other than 00b (D0 state) and 11b (D3 state) will complete normally without changing the current value in this field. 5.20.7.4 ACPI System States The EHC behavior as it relates to other power management states in the system is summarized in the following list: -- The System is always in the S0 state when the EHC is in the D0 state. However, when the EHC is in the D3 state, the system may be in any power management state (including S0). -- When in D0, the Pause feature (See Section 5.20.7.1) enables dynamic processor low-power states to be entered. -- The PLL in the EHC is disabled when entering the S3/S4/S5 states (core power turns off). -- All core well logic is reset in the S3/S4/S5 states. 220 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.20.8 USB 2.0 Legacy Keyboard Operation The PCH must support the possibility of a keyboard downstream from either a fullspeed/low-speed or a high-speed port. The description of the legacy keyboard support is unchanged from USB 1.1. -- The EHC provides the basic ability to generate SMIs on an interrupt event, along with more sophisticated control of the generation of Intel SMIs. 5.20.9 USB 2.0 Based Debug Port The PCH supports the elimination of the legacy COM ports by providing the ability for new debugger software to interact with devices on a USB 2.0 port. High-level restrictions and features are: * * * * Operational before USB 2.0 drivers are loaded. Functions even when the port is disabled. Allows normal system USB 2.0 traffic in a system that may only have one USB port. Debug Port device (DPD) must be high-speed capable and connect directly to Port 1 and Port 9 on PCH systems (such as, the DPD cannot be connected to Port 1/Port 9 through a hub. When a DPD is detected the PCH EHCI will bypass the integrated Rate Matching Hub and connect directly to the port and the DPD). * Debug Port FIFO always makes forward progress (a bad status on USB is simply presented back to software). * The Debug Port FIFO is only given one USB access per microframe. The Debug port facilitates operating system and device driver debug. It allows the software to communicate with an external console using a USB 2.0 connection. Because the interface to this link does not go through the normal USB 2.0 stack, it allows communication with the external console during cases where the operating system is not loaded, the USB 2.0 software is broken, or where the USB 2.0 software is being debugged. Specific features of this implementation of a debug port are: * Only works with an external USB 2.0 debug device (console) * Implemented for a specific port on the host controller * Operational anytime the port is not suspended AND the host controller is in D0 power state. * Capability is interrupted when port is driving USB RESET 5.20.9.1 Theory of Operation There are two operational modes for the USB debug port: 1. Mode 1 is when the USB port is in a disabled state from the viewpoint of a standard host controller driver. In Mode 1, the Debug Port controller is required to generate a "keepalive" packets less than 2 ms apart to keep the attached debug device from suspending. The keepalive packet should be a standalone 32-bit SYNC field. 2. Mode 2 is when the host controller is running (that is, host controller's Run/Stop# bit is 1). In Mode 2, the normal transmission of SOF packets will keep the debug device from suspending. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 221 Functional Description Behavioral Rules 1. In both modes 1 and 2, the Debug Port controller must check for software requested debug transactions at least every 125 microseconds. 2. If the debug port is enabled by the debug driver, and the standard host controller driver resets the USB port, USB debug transactions are held off for the duration of the reset and until after the first SOF is sent. 3. If the standard host controller driver suspends the USB port, then USB debug transactions are held off for the duration of the suspend/resume sequence and until after the first SOF is sent. 4. The ENABLED_CNT bit in the debug register space is independent of the similar port control bit in the associated Port Status and Control register. Table 5-50 shows the debug port behavior related to the state of bits in the debug registers as well as bits in the associated Port Status and Control register. Table 5-50. Debug Port Behavior 5.20.9.1.1 OWNER_CNT ENABLED_CT Port Enable Run / Stop Suspend 0 X X X X Debug port is not being used. Normal operation. 1 0 X X X Debug port is not being used. Normal operation. 1 1 0 0 X Debug port in Mode 1. SYNC keepalives sent plus debug traffic Debug Port Behavior 1 1 0 1 X Debug port in Mode 2. SOF (and only SOF) is sent as keepalive. Debug traffic is also sent. Note that no other normal traffic is sent out this port, because the port is not enabled. 1 1 1 0 0 Invalid. Host controller driver should never put controller into this state (enabled, not running and not suspended). 1 1 1 0 1 Port is suspended. No debug traffic sent. 1 1 1 1 0 Debug port in Mode 2. Debug traffic is interspersed with normal traffic. 1 1 1 1 1 Port is suspended. No debug traffic sent. OUT Transactions An Out transaction sends data to the debug device. It can occur only when the following are true: * The debug port is enabled * The debug software sets the GO_CNT bit * The WRITE_READ#_CNT bit is set The sequence of the transaction is: 1. Software sets the appropriate values in the following bits: -- USB_ADDRESS_CNF -- USB_ENDPOINT_CNF -- DATA_BUFFER[63:0] -- TOKEN_PID_CNT[7:0] -- SEND_PID_CNT[15:8] 222 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description -- DATA_LEN_CNT -- WRITE_READ#_CNT: (Note: This will always be 1 for OUT transactions.) -- GO_CNT: (note: this will always be 1 to initiate the transaction) 2. The debug port controller sends a token packet consisting of: -- SYNC -- TOKEN_PID_CNT field -- USB_ADDRESS_CNT field -- USB_ENDPOINT_CNT field -- 5-bit CRC field 3. After sending the token packet, the debug port controller sends a data packet consisting of: -- SYNC -- SEND_PID_CNT field -- The number of data bytes indicated in DATA_LEN_CNT from the DATA_BUFFER -- 16-bit CRC Note: A DATA_LEN_CNT value of 0 is valid in which case no data bytes would be included in the packet. 4. After sending the data packet, the controller waits for a handshake response from the debug device. * If a handshake is received, the debug port controller: -- a. Places the received PID in the RECEIVED_PID_STS field -- b. Resets the ERROR_GOOD#_STS bit -- c. Sets the DONE_STS bit * If no handshake PID is received, the debug port controller: -- a. Sets the EXCEPTION_STS field to 001b -- b. Sets the ERROR_GOOD#_STS bit -- c. Sets the DONE_STS bit 5.20.9.1.2 IN Transactions An IN transaction receives data from the debug device. It can occur only when the following are true: * The debug port is enabled * The debug software sets the GO_CNT bit * The WRITE_READ#_CNT bit is reset The sequence of the transaction is: 1. Software sets the appropriate values in the following bits: -- USB_ADDRESS_CNF -- USB_ENDPOINT_CNF -- TOKEN_PID_CNT[7:0] -- DATA_LEN_CNT -- WRITE_READ#_CNT: (Note: This will always be 0 for IN transactions.) -- GO_CNT: (Note: This will always be 1 to initiate the transaction.) Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 223 Functional Description 2. The debug port controller sends a token packet consisting of: -- SYNC -- TOKEN_PID_CNT field -- USB_ADDRESS_CNT field -- USB_ENDPOINT_CNT field -- 5-bit CRC field. 3. After sending the token packet, the debug port controller waits for a response from the debug device. If a response is received: -- The received PID is placed into the RECEIVED_PID_STS field -- Any subsequent bytes are placed into the DATA_BUFFER -- The DATA_LEN_CNT field is updated to show the number of bytes that were received after the PID. 4. If a valid packet was received from the device that was one byte in length (indicating it was a handshake packet), then the debug port controller: -- Resets the ERROR_GOOD#_STS bit -- Sets the DONE_STS bit 5. If a valid packet was received from the device that was more than one byte in length (indicating it was a data packet), then the debug port controller: -- Transmits an ACK handshake packet -- Resets the ERROR_GOOD#_STS bit -- Sets the DONE_STS bit 6. If no valid packet is received, then the debug port controller: -- Sets the EXCEPTION_STS field to 001b -- Sets the ERROR_GOOD#_STS bit -- Sets the DONE_STS bit. 5.20.9.1.3 Debug Software Enabling the Debug Port There are two mutually exclusive conditions that debug software must address as part of its startup processing: * The EHCI has been initialized by system software * The EHCI has not been initialized by system software Debug software can determine the current `initialized' state of the EHCI by examining the Configure Flag in the EHCI USB 2.0 Command Register. If this flag is set, then system software has initialized the EHCI. Otherwise the EHCI should not be considered initialized. Debug software will initialize the debug port registers depending on the state of the EHCI. However, before this can be accomplished, debug software must determine which root USB port is designated as the debug port. Determining the Debug Port Debug software can easily determine which USB root port has been designated as the debug port by examining bits 20:23 of the EHCI Host Controller Structural Parameters register. This 4-bit field represents the numeric value assigned to the debug port (that is, 0001=port 1). 224 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description Debug Software Startup with Non-Initialized EHCI Debug software can attempt to use the debug port if after setting the OWNER_CNT bit, the Current Connect Status bit in the appropriate (See Determining the Debug Port Presence) PORTSC register is set. If the Current Connect Status bit is not set, then debug software may choose to terminate or it may choose to wait until a device is connected. If a device is connected to the port, then debug software must reset/enable the port. Debug software does this by setting and then clearing the Port Reset bit the PORTSC register. To ensure a successful reset, debug software should wait at least 50 ms before clearing the Port Reset bit. Due to possible delays, this bit may not change to 0 immediately; reset is complete when this bit reads as 0. Software must not continue until this bit reads 0. If a high-speed device is attached, the EHCI will automatically set the Port Enabled/ Disabled bit in the PORTSC register and the debug software can proceed. Debug software should set the ENABLED_CNT bit in the Debug Port Control/Status register, and then reset (clear) the Port Enabled/Disabled bit in the PORTSC register (so that the system host controller driver does not see an enabled port when it is first loaded). Debug Software Startup with Initialized EHCI Debug software can attempt to use the debug port if the Current Connect Status bit in the appropriate (See Determining the Debug Port) PORTSC register is set. If the Current Connect Status bit is not set, then debug software may choose to terminate or it may choose to wait until a device is connected. If a device is connected, then debug software must set the OWNER_CNT bit and then the ENABLED_CNT bit in the Debug Port Control/Status register. Determining Debug Peripheral Presence After enabling the debug port functionality, debug software can determine if a debug peripheral is attached by attempting to send data to the debug peripheral. If all attempts result in an error (Exception bits in the Debug Port Control/Status register indicates a Transaction Error), then the attached device is not a debug peripheral. If the debug port peripheral is not present, then debug software may choose to terminate or it may choose to wait until a debug peripheral is connected. 5.20.10 EHCI Caching EHCI Caching is a power management feature in the USB (EHCI) host controllers which enables the controller to execute the schedules entirely in cache and eliminates the need for the DMA engine to access memory when the schedule is idle. EHCI caching allows the processor to maintain longer C-state residency times and provides substantial system power savings. 5.20.11 USB Pre-Fetch Based Pause The Pre-Fetch Based Pause is a power management feature in USB (EHCI) host controllers to ensure maximum C3/C4 processor power state time with C2 popup. This feature applies to the period schedule, and works by allowing the DMA engine to identify periods of idleness and preventing the DMA engine from accessing memory when the periodic schedule is idle. Typically in the presence of periodic devices with multiple millisecond poll periods, the periodic schedule will be idle for several frames between polls. The USB Pre-Fetch Based Pause feature is disabled by setting bit 4 of EHCI Configuration Register Section 17.2.1. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 225 Functional Description 5.20.12 Function Level Reset Support (FLR) (SRV/WS SKUs Only) The USB EHCI Controllers support the Function Level Reset (FLR) capability. The FLR capability can be used in conjunction with Intel Virtualization Technology. FLR allows an Operating System in a Virtual Machine to have complete control over a device, including its initialization, without interfering with the rest of the platform. The device provides a software interface that enables the Operating System to reset the whole device as if a PCI reset was asserted. 5.20.12.1 FLR Steps 5.20.12.1.1 FLR Initialization 1. A FLR is initiated by software writing a `1' to the Initiate FLR bit. 2. All subsequent requests targeting the Function will not be claimed and will be Master Abort Immediate on the bus. This includes any configuration, I/O or Memory cycles, however, the Function shall continue to accept completions targeting the Function. 5.20.12.1.2 FLR Operation The Function will Reset all configuration, I/O and memory registers of the Function except those indicated otherwise and reset all internal states of the Function to the default or initial condition. 5.20.12.1.3 FLR Completion The Initiate FLR bit is reset (cleared) when the FLR reset is completed. This bit can be used to indicate to the software that the FLR reset is completed. Note: From the time Initiate FLR bit is written to 1, software must wait at least 100 ms before accessing the function. 5.20.13 USB Overcurrent Protection The PCH has implemented programmable USB Overcurrent signals. The PCH provides a total of 8 overcurrent pins to be shared across the 14 ports. Four overcurrent signals have been allocated to the ports in each USB Device: * OC[3:0]# for Device 29 (Ports 0-7) * OC[7:4]# for Device 26 (Ports 8-13) Each pin is mapped to one or more ports by setting bits in the USBOCM1 and USBOCM2 registers.See Section 10.1.52 and Section 10.1.53. It is system BIOS' responsibility to ensure that each port is mapped to only one over current pin. Operation with more than one overcurrent pin mapped to a port is undefined. It is expected that multiple ports are mapped to a single overcurrent pin, however they should be connected at the port and not at the PCH pin. Shorting these pins together may lead to reduced test capabilities. By default, two ports are routed to each of the OC[6:0]# pins. OC7# is not used by default. Notes: 1. All USB ports routed out of the package must have Overcurrent protection. It is system BIOS responsibility to ensure all used ports have OC protection 2. USB Ports that are unused on the system (not routed out from the package) should not have OC pins assigned to them. 226 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.21 Integrated USB 2.0 Rate Matching Hub 5.21.1 Overview The PCH has integrated two USB 2.0 Rate Matching Hubs (RMH). One hub is connected to each of the EHCI controllers as shown in the figure below. The Hubs convert low and full-speed traffic into high-speed traffic. The RMHs will appear to software like an external hub is connected to Port 0 of each EHCI controller. In addition, port 1 of each of the RMHs is muxed with Port 1 of the EHCI controllers and is able to bypass the RMH for use as the Debug Port. The hub operates like any USB 2.0 Discrete Hub and will consume one tier of hubs allowed by the USB 2.0 Spec. section 4.1.1. A maximum of four additional non-root hubs can be supported on any of the PCH USB Ports. The RMH will report the following Vendor ID = 8087h and Product ID = 0024h. Figure 5-29. EHCI with USB 2.0 with Rate Matching Hub 5.21.2 Architecture A hub consists of three components: the Hub Repeater, the Hub Controller, and the Transaction Translator. 1. The Hub Repeater is responsible for connectivity setup and tear-down. It also supports exception handling, such as bus fault detection and recovery and connect/ disconnect detect. 2. The Hub Controller provides the mechanism for host-to-hub communication. Hubspecific status and control commands permit the host to configure a hub and to monitor and control its individual downstream facing ports. 3. The Transaction Translator (TT) responds to high-speed split transactions and translates them to full-/low-speed transactions with full-/low-speed devices attached on downstream facing ports. There is 1 TT per RMH in PCH. See chapter 11 of the USB 2.0 Specification for more details on the architecture of the hubs. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 227 Functional Description 5.22 SMBus Controller Depending on the SKU, the PCH contains two kinds of SMBus Controllers - the Host SMbus Controller and the IDF (Integrated Device Fabric) SMbus Controller. Note: The IDF (Integrated Device Fabric) SMbus Controller is not available on the HEDT SKU. 5.22.1 Host SMBus Controller(D31:F3) The PCH provides an System Management Bus (SMBus) 2.0 host controller as well as an SMBus Slave Interface. The host controller provides a mechanism for the processor to initiate communications with SMBus peripherals (slaves). The PCH is also capable of operating in a mode in which it can communicate with I2C compatible devices. The PCH can perform SMBus messages with either packet error checking (PEC) enabled or disabled. The actual PEC calculation and checking is performed in hardware by the PCH. The Slave Interface allows an external master to read from or write to the PCH. Write cycles can be used to cause certain events or pass messages, and the read cycles can be used to determine the state of various status bits. The PCH's internal host controller cannot access the PCH's internal Slave Interface. The PCH SMBus logic exists in Device 31:Function 3 configuration space, and consists of a transmit data path, and host controller. The transmit data path provides the data flow logic needed to implement the seven different SMBus command protocols and is controlled by the host controller. The PCH SMBus controller logic is clocked by RTC clock. The SMBus Address Resolution Protocol (ARP) is supported by using the existing host controller commands through software, except for the new Host Notify command (which is actually a received message). The programming model of the host controller is combined into two portions: a PCI configuration portion, and a system I/O mapped portion. All static configuration, such as the I/O base address, is done using the PCI configuration space. Real-time programming of the Host interface is done in system I/O space. The PCH SMBus host controller checks for parity errors as a target. If an error is detected, the detected parity error bit in the PCI Status Register (Device 31:Function 3:Offset 06h:bit 15) is set. If bit 6 and bit 8 of the PCI Command Register (Device 31:Function 3:Offset 04h) are set, an SERR# is generated and the signaled SERR# bit in the PCI Status Register (bit 14) is set. 5.22.2 IDF SMbus Controllers (Bus x:Device 0:Function 3,4,5) (SRV/WS SKUs Only) There are three additional host SMBus functions in the Integrated Device Function (function 3, 4, and 5) for a total of potentially 4 host accessible controllers on the PCH. Host software will have the ability to use a number of the host SMBus controllers depending on the PCH SKUs. The IDF SMBus controllers are similar to the host SMBus in their operations and programming interface. The primary difference is that the IDF SMBus controllers are PCI Express* function that support message signalled interrupts. The IDF SMBus controllers are SMBus 2.0 compliant devices supporting all protocols defined in the SMBus specification: Quick, Byte, Word, Block, and process call. The controllers also support an I2C mode to communicate with I2C compatible devices. SMBus messages can be sent either with PEC enabled or disabled though the actual PEC calculation and checking is performed by software. 228 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.22.3 Host Controller The SMBus host controller is used to send commands to other SMBus slave devices. Software sets up the host controller with an address, command, and, for writes, data and optional PEC; and then tells the controller to start. When the controller has finished transmitting data on writes, or receiving data on reads, it generates an SMI# or interrupt, if enabled. The host controller supports 8 command protocols of the SMBus interface (see System Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, Block Write-Block Read Process Call, and Host Notify. The SMBus host controller requires that the various data and command fields be setup for the type of command to be sent. When software sets the START bit, the SMBus Host controller performs the requested transaction, and interrupts the processor (or generates an SMI#) when the transaction is completed. Once a START command has been issued, the values of the "active registers" (Host Control, Host Command, Transmit Slave Address, Data 0, Data 1) should not be changed or read until the interrupt status message (INTR) has been set (indicating the completion of the command). Any register values needed for computation purposes should be saved prior to issuing of a new command, as the SMBus host controller updates all registers while completing the new command. The PCH supports the System Management Bus (SMBus) Specification, Version 2.0. Slave functionality, including the Host Notify protocol, is available on the SMBus pins. The SMLink and SMBus signals can be tied together externally depending on TCO mode used. Refer to section 5.14.2 for more details. Using the SMB host controller to send commands to the PCH's SMB slave port is not supported. 5.22.3.1 Command Protocols In all of the following commands, the Host Status Register (offset 00h) is used to determine the progress of the command. While the command is in operation, the HOST_BUSY bit is set. If the command completes successfully, the INTR bit will be set in the Host Status Register. If the device does not respond with an acknowledge, and the transaction times out, the DEV_ERR bit is set. If software sets the KILL bit in the Host Control Register while the command is running, the transaction will stop and the FAILED bit will be set. Quick Command When programmed for a Quick Command, the Transmit Slave Address Register is sent. The PEC byte is never appended to the Quick Protocol. Software should force the PEC_EN bit to 0 when performing the Quick Command. Software must force the I2C_EN bit to 0 when running this command. See section 5.5.1 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Send Byte / Receive Byte For the Send Byte command, the Transmit Slave Address and Device Command Registers are sent For the Receive Byte command, the Transmit Slave Address Register is sent. The data received is stored in the DATA0 register. Software must force the I2C_EN bit to 0 when running this command. The Receive Byte is similar to a Send Byte, the only difference is the direction of data transfer. See sections 5.5.2 and 5.5.3 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 229 Functional Description Write Byte/Word The first byte of a Write Byte/Word access is the command code. The next 1 or 2 bytes are the data to be written. When programmed for a Write Byte/Word command, the Transmit Slave Address, Device Command, and Data0 Registers are sent. In addition, the Data1 Register is sent on a Write Word command. Software must force the I2C_EN bit to 0 when running this command. See section 5.5.4 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Read Byte/Word Reading data is slightly more complicated than writing data. First the PCH must write a command to the slave device. Then it must follow that command with a repeated start condition to denote a read from that device's address. The slave then returns 1 or 2 bytes of data. Software must force the I2C_EN bit to 0 when running this command. When programmed for the read byte/word command, the Transmit Slave Address and Device Command Registers are sent. Data is received into the DATA0 on the read byte, and the DAT0 and DATA1 registers on the read word. See section 5.5.5 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Process Call The process call is so named because a command sends data and waits for the slave to return a value dependent on that data. The protocol is simply a Write Word followed by a Read Word, but without a second command or stop condition. When programmed for the Process Call command, the PCH transmits the Transmit Slave Address, Host Command, DATA0 and DATA1 registers. Data received from the device is stored in the DATA0 and DATA1 registers. The Process Call command with I2C_EN set and the PEC_EN bit set produces undefined results. Software must force either I2C_EN or PEC_EN to 0 when running this command. See section 5.5.6 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Note: For process call command, the value written into bit 0 of the Transmit Slave Address Register (SMB I/O register, offset 04h) needs to be 0. Note: If the I2C_EN bit is set, the protocol sequence changes slightly: the Command Code (bits 18:11 in the bit sequence) are not sent - as a result, the slave will not acknowledge (bit 19 in the sequence). 230 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description Block Read/Write The PCH contains a 32-byte buffer for read and write data which can be enabled by setting bit 1 of the Auxiliary Control register at offset 0Dh in I/O space, as opposed to a single byte of buffering. This 32-byte buffer is filled with write data before transmission, and filled with read data on reception. In the PCH, the interrupt is generated only after a transmission or reception of 32 bytes, or when the entire byte count has been transmitted/received. Note: When operating in I2C mode (I2C_EN bit is set), the PCH will never use the 32-byte buffer for any block commands. The byte count field is transmitted but ignored by the PCH as software will end the transfer after all bytes it cares about have been sent or received. For a Block Write, software must either force the I2C_EN bit or both the PEC_EN and AAC bits to 0 when running this command. The block write begins with a slave address and a write condition. After the command code the PCH issues a byte count describing how many more bytes will follow in the message. If a slave had 20 bytes to send, the first byte would be the number 20 (14h), followed by 20 bytes of data. The byte count may not be 0. A Block Read or Write is allowed to transfer a maximum of 32 data bytes. When programmed for a block write command, the Transmit Slave Address, Device Command, and Data0 (count) registers are sent. Data is then sent from the Block Data Byte register; the total data sent being the value stored in the Data0 Register. On block read commands, the first byte received is stored in the Data0 register, and the remaining bytes are stored in the Block Data Byte register. See section 5.5.7 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Note: For Block Write, if the I2C_EN bit is set, the format of the command changes slightly. The PCH will still send the number of bytes (on writes) or receive the number of bytes (on reads) indicated in the DATA0 register. However, it will not send the contents of the DATA0 register as part of the message. Also, the Block Write protocol sequence changes slightly: the Byte Count (bits 27:20 in the bit sequence) are not sent - as a result, the slave will not acknowledge (bit 28 in the sequence). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 231 Functional Description I2C Read This command allows the PCH to perform block reads to certain I2C devices, such as serial E2PROMs. The SMBus Block Read supports the 7-bit addressing mode only. However, this does not allow access to devices using the I2C "Combined Format" that has data bytes after the address. Typically these data bytes correspond to an offset (address) within the serial memory chips. Note: This command is supported independent of the setting of the I2C_EN bit. The I2C Read command with the PEC_EN bit set produces undefined results. Software must force both the PEC_EN and AAC bit to 0 when running this command. For I2C Read command, the value written into bit 0 of the Transmit Slave Address Register (SMB I/O register, offset 04h) needs to be 0. The format that is used for the command is shown in Table 5-51. Table 5-51. I2C Block Read Bit 1 8:2 9 10 18:11 Description Start Slave Address -- 7 bits Write Acknowledge from slave Send DATA1 register 19 Acknowledge from slave 20 Repeated Start 27:21 Slave Address -- 7 bits 28 Read 29 Acknowledge from slave 37:30 38 46:39 47 Data byte 1 from slave -- 8 bits Acknowledge Data byte 2 from slave -- 8 bits Acknowledge - Data bytes from slave / Acknowledge - Data byte N from slave -- 8 bits - NOT Acknowledge - Stop The PCH will continue reading data from the peripheral until the NAK is received. 232 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description Block Write-Block Read Process Call The block write-block read process call is a two-part message. The call begins with a slave address and a write condition. After the command code the host issues a write byte count (M) that describes how many more bytes will be written in the first part of the message. If a master has 6 bytes to send, the byte count field will have the value 6 (0000 0110b), followed by the 6 bytes of data. The write byte count (M) cannot be 0. The second part of the message is a block of read data beginning with a repeated start condition followed by the slave address and a Read bit. The next byte is the read byte count (N), which may differ from the write byte count (M). The read byte count (N) cannot be 0. The combined data payload must not exceed 32 bytes. The byte length restrictions of this process call are summarized as follows: * M 1 byte * N 1 byte * M + N 32 bytes The read byte count does not include the PEC byte. The PEC is computed on the total message beginning with the first slave address and using the normal PEC computational rules. It is highly recommended that a PEC byte be used with the Block Write-Block Read Process Call. Software must do a read to the command register (offset 2h) to reset the 32 byte buffer pointer prior to reading the block data register. Note that there is no STOP condition before the repeated START condition, and that a NACK signifies the end of the read transfer. Note: E32B bit in the Auxiliary Control register must be set when using this protocol. See section 5.5.8 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. 5.22.4 Bus Arbitration Several masters may attempt to get on the bus at the same time by driving the SMBDATA line low to signal a start condition. The PCH continuously monitors the SMBDATA line. When the PCH is attempting to drive the bus to a 1 by letting go of the SMBDATA line, and it samples SMBDATA low, then some other master is driving the bus and the PCH will stop transferring data. If the PCH sees that it has lost arbitration, the condition is called a collision. The PCH will set the BUS_ERR bit in the Host Status Register, and if enabled, generate an interrupt or SMI#. The processor is responsible for restarting the transaction. When the PCH is a SMBus master, it drives the clock. When the PCH is sending address or command as an SMBus master, or data bytes as a master on writes, it drives data relative to the clock it is also driving. It will not start toggling the clock until the start or stop condition meets proper setup and hold time. The PCH will also ensure minimum time between SMBus transactions as a master. Note: The PCH supports the same arbitration protocol for both the SMBus and the System Management (SMLink) interfaces. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 233 Functional Description 5.22.5 Bus Timing 5.22.5.1 Clock Stretching Some devices may not be able to handle their clock toggling at the rate that the PCH as an SMBus master would like. They have the capability of stretching the low time of the clock. When the PCH attempts to release the clock (allowing the clock to go high), the clock will remain low for an extended period of time. The PCH monitors the SMBus clock line after it releases the bus to determine whether to enable the counter for the high time of the clock. While the bus is still low, the high time counter must not be enabled. Similarly, the low period of the clock can be stretched by an SMBus master if it is not ready to send or receive data. 5.22.5.2 Bus Time Out (PCH as SMBus Master) If there is an error in the transaction, such that an SMBus device does not signal an acknowledge, or holds the clock lower than the allowed time-out time, the transaction will time out. The PCH will discard the cycle and set the DEV_ERR bit. The time out minimum is 25 ms (800 RTC clocks). The time-out counter inside the PCH will start after the last bit of data is transferred by the PCH and it is waiting for a response. The 25 ms timeout counter will not count under the following conditions: 1. BYTE_DONE_STATUS bit (SMBus I/O Offset 00h, bit 7) is set 2. The SECOND_TO_STS bit (TCO I/O Offset 06h, bit 1) is not set (this indicates that the system has not locked up). 5.22.6 Interrupts / SMI# The PCH SMBus controller uses PIRQB# as its interrupt pin. However, the system can alternatively be set up to generate SMI# instead of an interrupt, by setting the SMBUS_SMI_EN bit (Device 31:Function 0:Offset 40h:bit 1). Table 5-53 and Table 5-54 specify how the various enable bits in the SMBus function control the generation of the interrupt, Host and Slave SMI, and Wake internal signals. The rows in the tables are additive, which means that if more than one row is true for a particular scenario then the Results for all of the activated rows will occur. Table 5-52. Enable for SMBALERT# Event SMBALERT# asserted low (always reported in Host Status Register, Bit 5) 234 INTREN (Host Control I/O Register, Offset 02h, Bit 0) SMB_SMI_EN (Host Configuration Register, D31:F3:Offset 40h, Bit 1) SMBALERT_DIS (Slave Command I/ O Register, Offset 11h, Bit 2) X X X Wake generated X 1 0 Slave SMI# generated (SMBUS_SMI_STS) 1 0 0 Interrupt generated Result Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description Table 5-53. Enables for SMBus Slave Write and SMBus Host Events INTREN (Host Control I/O Register, Offset 02h, Bit 0) SMB_SMI_EN (Host Configuration Register, D31:F3:Offset 40h, Bit1) Slave Write to Wake/ SMI# Command X X Wake generated when asleep. Slave SMI# generated when awake (SMBUS_SMI_STS). Slave Write to SMLINK_SLAVE_SMI Command X X Slave SMI# generated when in the S0 state (SMBUS_SMI_STS) 0 X None 1 0 Interrupt generated 1 1 Host SMI# generated Event Any combination of Host Status Register [4:1] asserted Event Table 5-54. Enables for the Host Notify Command 5.22.7 HOST_NOTIFY_INTRE N (Slave Control I/O Register, Offset 11h, Bit 0) SMB_SMI_EN (Host Config Register, D31:F3:Off40h, Bit 1) HOST_NOTIFY_WKEN (Slave Control I/O Register, Offset 11h, Bit 1) 0 X 0 None X X 1 Wake generated 1 0 X Interrupt generated 1 1 X Slave SMI# generated (SMBUS_SMI_STS) Result SMBALERT# SMBALERT# is multiplexed with GPIO[11]. When enable and the signal is asserted, The PCH can generate an interrupt, an SMI#, or a wake event from S1-S5. 5.22.8 SMBus CRC Generation and Checking If the AAC bit is set in the Auxiliary Control register, the PCH automatically calculates and drives CRC at the end of the transmitted packet for write cycles, and will check the CRC for read cycles. It will not transmit the contents of the PEC register for CRC. The PEC bit must not be set in the Host Control register if this bit is set, or unspecified behavior will result. If the read cycle results in a CRC error, the DEV_ERR bit and the CRCE bit in the Auxiliary Status register at offset 0Ch will be set. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 235 Functional Description 5.22.9 SMBus Slave Interface The PCH's SMBus Slave interface is accessed using the SMBus. The SMBus slave logic will not generate or handle receiving the PEC byte and will only act as a Legacy Alerting Protocol device. The slave interface allows the PCH to decode cycles, and allows an external microcontroller to perform specific actions. Key features and capabilities include: * Supports decode of three types of messages: Byte Write, Byte Read, and Host Notify. * Receive Slave Address register: This is the address that the PCH decodes. A default value is provided so that the slave interface can be used without the processor having to program this register. * Receive Slave Data register in the SMBus I/O space that includes the data written by the external microcontroller. * Registers that the external microcontroller can read to get the state of the PCH. * Status bits to indicate that the SMBus slave logic caused an interrupt or SMI# due to the reception of a message that matched the slave address. -- Bit 0 of the Slave Status Register for the Host Notify command -- Bit 16 of the Intel SMI Status Register Section 13.8.3.8 for all others Note: The external microcontroller should not attempt to access the PCH's SMBus slave logic until either: -- 800 milliseconds after both: RTCRST# is high and RSMRST# is high, OR -- The PLTRST# de-asserts If a master leaves the clock and data bits of the SMBus interface at 1 for 50 s or more in the middle of a cycle, the PCH slave logic's behavior is undefined. This is interpreted as an unexpected idle and should be avoided when performing management activities to the slave logic. Note: 236 When an external microcontroller accesses the SMBus Slave Interface over the SMBus a translation in the address is needed to accommodate the least significant bit used for read/write control. For example, if the PCH slave address (RCV_SLVA) is left at 44h (default), the external micro controller would use an address of 88h/89h (write/read). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.22.9.1 Format of Slave Write Cycle The external master performs Byte Write commands to the PCH SMBus Slave I/F. The "Command" field (bits 11:18) indicate which register is being accessed. The Data field (bits 20:27) indicate the value that should be written to that register. Table 5-55 has the values associated with the registers. Table 5-55. Slave Write Registers Register 0 1-3 Function Command Register. See Table 5-56 below for legal values written to this register. Reserved 4 Data Message Byte 0 5 Data Message Byte 1 6-7 Reserved 8 Reserved 9-FFh Reserved Note: The external microcontroller is responsible to make sure that it does not update the contents of the data byte registers until they have been read by the system processor. The PCH overwrites the old value with any new value received. A race condition is possible where the new value is being written to the register just at the time it is being read. PCH will not attempt to cover this race condition (that is, unpredictable results in this case). . Table 5-56. Command Types Command Type Description 0 Reserved 1 WAKE/SMI#. This command wakes the system if it is not already awake. If system is already awake, an SMI# is generated. Note: The SMB_WAK_STS bit will be set by this command, even if the system is already awake. The Intel SMI handler should then clear this bit. 2 Unconditional Powerdown. This command sets the PWRBTNOR_STS bit, and has the same effect as the Powerbutton Override occurring. 3 HARD RESET WITHOUT CYCLING: This command causes a hard reset of the system (does not include cycling of the power supply). This is equivalent to a write to the CF9h register with bits 2:1 set to 1, but bit 3 set to 0. 4 HARD RESET SYSTEM. This command causes a hard reset of the system (including cycling of the power supply). This is equivalent to a write to the CF9h register with bits 3:1 set to 1. 5 Disable the TCO Messages. This command will disable the PCH from sending Heartbeat and Event messages (as described in Section 5.15). Once this command has been executed, Heartbeat and Event message reporting can only be re-enabled by assertion and deassertion of the RSMRST# signal. 6 WD RELOAD: Reload watchdog timer. 7 Reserved 8 SMLINK_SLV_SMI. When PCH detects this command type while in the S0 state, it sets the SMLINK_SLV_SMI_STS bit. This command should only be used if the system is in an S0 state. If the message is received during S1-S5 states, the PCH acknowledges it, but the SMLINK_SLV_SMI_STS bit does not get set. Note: It is possible that the system transitions out of the S0 state at the same time that the SMLINK_SLV_SMI command is received. In this case, the SMLINK_SLV_SMI_STS bit may get set but not serviced before the system goes to sleep. Once the system returns to S0, the Intel SMI associated with this bit would then be generated. Software must be able to handle this scenario. 9-FFh Reserved. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 237 Functional Description 5.22.9.2 Format of Read Command The external master performs Byte Read commands to the PCH SMBus Slave interface. The "Command" field (bits 18:11) indicate which register is being accessed. The Data field (bits 30:37) contain the value that should be read from that register. Table 5-57. Slave Read Cycle Format Bit 1 Description Driven by Comment Start External Microcontroller Slave Address - 7 bits External Microcontroller Must match value in Receive Slave Address register 9 Write External Microcontroller Always 0 10 ACK PCH Command code - 8 bits External Microcontroller 19 ACK PCH 20 Repeated Start External Microcontroller Slave Address - 7 bits External Microcontroller Must match value in Receive Slave Address register 28 Read External Microcontroller Always 1 29 ACK PCH 30-37 Data Byte PCH 38 NOT ACK External Microcontroller 39 Stop External Microcontroller 2-8 11-18 21-27 Indicates which register is being accessed. See Table 5-58 below for list of implemented registers. Value depends on register being accessed. Table 5-58 below for list of implemented registers. Table 5-58. Data Values for Slave Read Registers (Sheet 1 of 2) Register Bits 0 7:0 Reserved for capabilities indication. Should always return 00h. Future chips may return another value to indicate different capabilities. 2:0 System Power State 000 = S0 001 = S1 010 = Reserved 011 = S3 100 = S4 101 = S5 110 = Reserved 111 = Reserved 1 2 3 238 Description 7:3 Reserved 3:0 Reserved 7:4 Reserved 5:0 Watchdog Timer current value Note that Watchdog Timer has 10 bits, but this field is only 6 bits. If the current value is greater than 3Fh, PCH will always report 3Fh in this field. 7:6 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description Table 5-58. Data Values for Slave Read Registers (Sheet 2 of 2) Register 4 Bits Description 0 1 = The Intruder Detect (INTRD_DET) bit is set. This indicates that the system cover has probably been opened. 1 1 = BTI Temperature Event occurred. This bit will be set if the PCH's THRM# input signal is active. Else this bit will read "0." 2 DOA Processor Status. This bit will be 1 to indicate that the processor is dead 3 1 = SECOND_TO_STS bit set. This bit will be set after the second time-out (SECOND_TO_STS bit) of the Watchdog Timer occurs. 6:4 Reserved. Will always be 0, but software should ignore. 7 Reflects the value of the GPIO[11]/SMBALERT# pin (and is dependent upon the value of the GPI_INV[11] bit. If the GPI_INV[11] bit is 1, then the value in this bit equals the level of the GPI[11]/SMBALERT# pin (high = 1, low = 0). If the GPI_INV[11] bit is 0, then the value of this bit will equal the inverse of the level of the GPIO[11]/SMBALERT# pin (high = 0, low = 1). 0 FWH bad bit. This bit will be 1 to indicate that the FWH read returned FFh, which indicates that it is probably blank. 1 Reserved 2 SYS_PWROK Power Failure Status: This bit will be 1 if the SYSPWR_FLR bit in the GEN_PMCON_2 register is set. 3 INIT3_3V# due to receiving Shutdown message: This event is visible from the reception of the shutdown message until a platform reset is done if the Shutdown Policy Select bit (SPS) is configured to drive INIT3_3V#. When the SPS bit is configured to generate PLTRST# based on shutdown, this register bit will always return 0. Events on signal will not create a event message 4 Reserved 5 POWER_OK_BAD: Indicates the failure core power well ramp during boot/resume. This bit will be active if the SLP_S3# pin is de-asserted and PCH_PWROK pin is not asserted. 6 Thermal Trip: This bit will shadow the state of processor Thermal Trip status bit (CTS) (16.2.1.2, GEN_PMCON_2, bit 3). Events on signal will not create a event message 7 Reserved: Default value is "X" Note: Software should not expect a consistent value when this bit is read through SMBUS/SMLink. 6 7:0 Contents of the Message 1 register. Refer to Section 13.9.8 for the description of this register. 7 7:0 Contents of the Message 2 register. Refer to Section 13.9.8 for the description of this register. 8 7:0 Contents of the TCO_WDCNT register. Refer to Section 13.9.9 for the description of this register. 9 7:0 Seconds of the RTC A 7:0 Minutes of the RTC B 7:0 Hours of the RTC 5 C 7:0 "Day of Week" of the RTC D 7:0 "Day of Month" of the RTC E 7:0 Month of the RTC F 7:0 Year of the RTC 10h-FFh 7:0 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 239 Functional Description Behavioral Notes According to SMBus protocol, Read and Write messages always begin with a Start bit - Address- Write bit sequence. When the PCH detects that the address matches the value in the Receive Slave Address register, it will assume that the protocol is always followed and ignore the Write bit (bit 9) and signal an Acknowledge during bit 10. In other words, if a Start -Address-Read occurs (which is illegal for SMBus Read or Write protocol), and the address matches the PCH's Slave Address, the PCH will still grab the cycle. Also according to SMBus protocol, a Read cycle contains a Repeated Start-Address- Read sequence beginning at bit 20. Once again, if the Address matches the PCH's Receive Slave Address, it will assume that the protocol is followed, ignore bit 28, and proceed with the Slave Read cycle. Note: An external microcontroller must not attempt to access the PCH's SMBus Slave logic until at least 1 second after both RTCRST# and RSMRST# are de-asserted (high). 5.22.9.3 Slave Read of RTC Time Bytes The PCH SMBus slave interface allows external SMBus master to read the internal RTC's time byte registers. The RTC time bytes are internally latched by the PCH's hardware whenever RTC time is not changing and SMBus is idle. This ensures that the time byte delivered to the slave read is always valid and it does not change when the read is still in progress on the bus. The RTC time will change whenever hardware update is in progress, or there is a software write to the RTC time bytes. The PCH SMBus slave interface only supports Byte Read operation. The external SMBus master will read the RTC time bytes one after another. It is software's responsibility to check and manage the possible time rollover when subsequent time bytes are read. For example, assuming the RTC time is 11 hours: 59 minutes: 59 seconds. When the external SMBus master reads the hour as 11, then proceeds to read the minute, it is possible that the rollover happens between the reads and the minute is read as 0. This results in 11 hours: 0 minute instead of the correct time of 12 hours: 0 minutes. Unless it is certain that rollover will not occur, software is required to detect the possible time rollover by reading multiple times such that the read time bytes can be adjusted accordingly if needed. 5.22.9.4 Format of Host Notify Command The PCH tracks and responds to the standard Host Notify command as specified in the System Management Bus (SMBus) Specification, Version 2.0. The host address for this command is fixed to 0001000b. If the PCH already has data for a previously-received host notify command which has not been serviced yet by the host software (as indicated by the HOST_NOTIFY_STS bit), then it will NACK following the host address byte of the protocol. This allows the host to communicate non-acceptance to the master and retain the host notify address and data values for the previous cycle until host software completely services the interrupt. Note: Host software must always clear the HOST_NOTIFY_STS bit after completing any necessary reads of the address and data registers. Table 5-59 shows the Host Notify format. 240 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description Table 5-59. Host Notify Format Bit 1 8:2 9 10 Description Driven By Start External Master SMB Host Address -- 7 bits External Master Write External Master ACK (or NACK) PCH Comment Always 0001_000 Always 0 PCH NACKs if HOST_NOTIFY_STS is 1 Device Address - 7 bits External Master Indicates the address of the master; loaded into the Notify Device Address Register 18 Unused -- Always 0 External Master 7-bit-only address; this bit is inserted to complete the byte 19 ACK PCH Data Byte Low -- 8 bits External Master ACK PCH Data Byte High -- 8 bits External Master 37 ACK PCH 38 Stop External Master 17:11 27:20 28 36:29 5.23 Thermal Management 5.23.1 Thermal Sensor Loaded into the Notify Data Low Byte Register Loaded into the Notify Data High Byte Register The PCH incorporates one on-die Digital thermal sensor (DTS) for thermal management. The thermal sensor can provide PCH temperature information to an EC or SIO device that can be used to determine how to control the fans. This thermal sensor is located near the DMI interface. The on-die thermal sensor is placed as close as possible to the hottest on-die location to reduce thermal gradients and to reduce the error on the sensor trip thresholds. The thermal Sensor trip points may be programmed to generate various interrupts including SCI, Intel SMI, PCI and other General Purpose events. 5.23.1.1 Internal Thermal Sensor Operation The internal thermal sensor reports four trip points: Aux2, Aux, Hot and Catastrophic trip points in the order of increasing temperature. Aux, Aux2 Temperature Trip Points These trip points may be set dynamically if desired and provides an interrupt to ACPI (or other software) when it is crossed in either direction. These auxiliary temperature trip points do not automatically cause any hardware throttling but may be used by software to trigger interrupts. This trip point is set below the Hot temperature trip point and responses are separately programmable from the hot temperature settings, in order to provide incrementally more aggressive actions. Aux and Aux2 trip points are fully Software programmable during system run-time. Aux2 trip point is set below the Aux temperature trip point. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 241 Functional Description Hot Temperature Trip Point This trip point may be set dynamically if desired and provides an interrupt to ACPI (or other software) when it is crossed in either direction. Software could optionally set this as an Interrupt when the temperature exceeds this level setting. Hot trip does not provide any default hardware based thermal throttling, and is available only as a customer configurable interrupt when Tj,max has been reached. Catastrophic Trip Point This trip point is set at the temperature at which the PCH must be shut down immediately without any software support. The catastrophic trip point must correspond to a temperature ensured to be functional in order for the interrupt generation and Hardware response. Hardware response using THERMTRIP# would be an unconditional transition to S5. The catastrophic transition to the S5 state does not enforce a minimum time in the S5 state. It is assumed that the S5 residence and the reboot sequence cools down the system. If the catastrophic condition remains when the catastrophic power down enable bit is set by BIOS, then the system will re-enter S5. Thermometer Mode The thermometer is implemented using a counter that starts at 0 and increments during each sample point until the comparator indicates the temperature is above the current value. The value of the counter is loaded into a read-only register (Thermal Sensor Thermometer Read) when the comparator first trips. 5.23.1.1.1 Recommended Programming for Available Trip Points There may be a 2C offset due to thermal gradient between the hot-spot and the location of the thermal sensor. Trip points should be programmed to account for this temperature offset between the hot-spot Tj,max and the thermal sensor. Aux Trip Points should be programmed for software and firmware control using interrupts. Hot Trip Point should be set to throttle at 108C (Tj,max) due to DTS trim accuracy adjustments. Hot trip points should also be programmed for a software response. Catastrophic Trip Point should be set to halt operation to avoid maximum Tj of about 120C. Note: Crossing a trip point in either direction may generate several types of interrupts. Each trip point has a register that can be programmed to select the type of interrupt to be generated. Crossing a trip point is implemented as edge detection on each trip point to generate the interrupts. 5.23.1.1.2 Thermal Sensor Accuracy (Taccuracy) Taccuracy for PCH is 5 C in the temperature range 90C to 120C. Taccuracy is 10 C for temperatures from 45 C - 90 C. PCH may not operate above +108 C. This value is based on product characterization and is not ensured by manufacturing test. Software has the ability to program the Tcat, Thot, and Taux trip points, but these trip points should be selected with consideration for the thermal sensor accuracy and the quality of the platform thermal solution. Overly conservative (unnecessarily low) temperature settings may unnecessarily degrade performance due to frequent throttling, while overly aggressive (dangerously high) temperature settings may fail to protect the part against permanent thermal damage. 242 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.23.2 Thermal Reporting Over System Management Link 1 Interface (SMLink1) SMLink1 interface in the PCH is the SMBus link to an optional external controller. A SMBus protocol is defined on the PCH to allow compatible devices such as Embedded Controller (EC) or SIO to obtain system thermal data from sensors integrated into components on the system using the SMLink1 interface. The sensors that can be monitored using the SMLink1 include those in the processor, PCH, and DIMMs with sensors implemented. This solution allows an external device or controller to use the system thermal data for system thermal management. Note: To enable Thermal Reporting, the Thermal Data Reporting enable and processor/PCH/ DIMM temperature read enables have to be set in the Thermal Reporting Control (TRC) Register (See Section 23.2 for details on Register) There are 2 uses for the PCH's thermal reporting capability: 1. To provide system thermal data to an external controller. The controller can manage the fans and other cooling elements based on this data. In addition, the PCH can be programmed by setting appropriate bits in the Alert Enable (AE) Register (See Section 23.2 for details on this register) to alert the controller when a device has gone outside of its temperature limits. The alert causes the assertion of the PCH's TEMP_ALERT# (SATA5GP/GPIO49/TEMP_ALERT#) signal. See Section 5.23.2.6 for more details. 2. To provide an interface between the external controller and host software. This software interface has no direct affect on the PCH's thermal collection. It is strictly a software interface to pass information or data. The PCH responds to thermal requests only when the system is in S0 or S1. Once the PCH has been programmed, it will start responding to a request while the system is in S0 or S1. To implement this thermal reporting capability, the platform is required to have appropriate Intel ME firmware, BIOS support, and compatible devices that support the SMBus protocol. 5.23.2.1 Supported Addresses The PCH supports 2 addresses: I2C Address for writes and Block Read Address for reads. These addresses need to be distinct. 5.23.2.1.1 I2C* Address This address is used for writes to the PCH. * The address is set by soft straps which are values stored in SPI flash and are defined by the OEM. The address can be set to any value the platform requires. * This address supports all the writes listed in Table 5-60 below. * SMBus reads by the external controller to this address are not allowed and result in indeterminate behavior. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 243 Functional Description 5.23.2.1.2 Block Read Address This address is used for reads from the PCH. * The address is set by soft straps or BIOS. It can be set to any value the platform requires. * This address only supports SMBus Block Read command and not Byte or Word Read. * The Block Read command is supported as defined in the SMBus 2.0 specification, with the command being 40h, and the byte count being provided by the PCH following the block read format in the SMBus spec. * Writes are not allowed to this address, and result in indeterminate behavior. * Packet Error Code (PEC) may be enabled or not, which is set up by BIOS. 5.23.2.2 I2C Write Commands to the Intel(R) Management Engine Table 5-60 lists the write commands supported by the Intel ME. All bits in the write commands must be written to the PCH or the operation will be aborted. For example, for 6-bytes write commands, all 48 bits must be written or the operation will be aborted. The command format follows the Block Write format of the SMBus specification. Table 5-60. I2C Write Commands to the Intel(R) Management Engine Transaction Slave Addr Data Byte0 (Commd) Data Byte 1 (Byte Count) Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Write Processor Temp Limits I2 C 42h 4h Lower Limit [15:8] Lower Limit [7:0] Upper Limit [15:8] Upper Limit [7:0] Write PCH Temp Limits I2 C 44h 2h Lower Limit [7:0] Upper Limit [7:0] Write DIMM Temp Limits I2 C 45h 2h Lower Limit [7:0] Upper Limit [7:0] 244 Data Byte 6 Data Byte 7 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.23.2.3 Block Read Command The external controller may read thermal information from the PCH using the SMBus Block Read Command. Byte-read and Word-read SMBus commands are not supported. Note that the reads use a different address than the writes. The command format follows the Block Read format of the SMBus spec. The PCH and external controller are set up by BIOS with the length of the read that is supported by the platform. The device must always do reads of the lengths set up by BIOS. The PCH supports any one of the following lengths: 2, 4, 5, 9, 10, 14 or 20 bytes. The data always comes in the order described in Table 5-61, where 0 is the first byte received in time on the SMBus. Table 5-61. Block Read Command - Byte Definition Byte Description Byte 0 Processor Package temperature, in absolute degrees Celsius (C) It is a single byte for the highest temperature between the 2 components. This is not relative to some max or limit, but is the maximum in absolute degrees. If the processor temperature collection has errors, this field will be FFh. Read value represents bits [7:0] of PTV (Processor Temperature Value) Byte 1 The PCH temp in degrees C. FFh indicates error condition. Read value represents bits [7:0] of ITV (Internal Temperature Values) Register described in Section 23.2. Note: Requires TRC (Thermal Reporting Control) Register bit [5] to be enabled. Please see Section 23.2. Byte 4:2 Reserved Byte 5 Thermal Sensor (TS) on DIMM 0 If DIMM not populated, or if there is no TS on DIMM, value will be 0h Read value represents bits[7:0] of DTV (DIMM Temperature Values) Register described in Section 23.2. Note: Requires TRC (Thermal Reporting Control) Register bit [0] to be enabled. Please see Section 23.2. Byte 6 Thermal Sensor (TS) on DIMM 1 If DIMM not populated, or if there is no TS on DIMM, value will be 0h Read value represents bits[15:8] of DTV (DIMM Temperature Values) Register described in Section 23.2. Note: Requires TRC (Thermal Reporting Control) Register bit [1] to be enabled. Please see Section 23.2. Byte 7 Thermal Sensor (TS) on DIMM 2 If DIMM not populated, or if there is no TS on DIMM, value will be 0h Read value represents bits[23:16] of DTV (DIMM Temperature Values) Register described in Section 23.2. Note: Requires TRC (Thermal Reporting Control) Register bit [2] to be enabled. Please see Section 23.2. Byte 8 Thermal Sensor (TS) on DIMM 3 If DIMM not populated, or if there is no TS on DIMM, value will be 0h Read value represents bits[31:24] of DTV (DIMM Temperature Values) Register described in Section 23.2. Note: Requires TRC (Thermal Reporting Control) Register bit [3] to be enabled. Byte 9 Sequence number. Can be used to check if PCH's FW or HW is hung. See Section 5.23.2.9 for usage. This byte is updated every time the collected data is updated Note: Read value represents bits[23:16] of ITV (Internal Temperature Values) Register described in Section 23.2. Byte 19:10 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 245 Functional Description A 2-byte read would provide both the PCH and processor temperature. A device that wants DIMM information would read 9 bytes. 5.23.2.4 Read Data Format For each of the data fields an ERROR Code is listed below. This code indicates that the PCH failed in its access to the device. This would be for the case where the read returned no data, or some illegal value. In general that would mean the device is broken. The EC can treat the device that failed the read as broken or with some failsafe mechanism. 5.23.2.4.1 PCH and DIMM Temperature The temperature readings for the PCH, DIMM are 8-bit unsigned values from 0-255. The minimum granularity supported by the internal thermal sensor is 1C. Thus, there are no fractional values for the PCH or DIMM temperatures. Note the sensors used within the components do not support values below 0 degrees, so this field is treated as 8 bits (0-255) absolute and not 2's complement (-128 to 127). Devices that are not present or that are disabled will be set to 0h. Devices that have a failed reading (that is, the read from the device did not return any legal value) will be set to FFh. A failed reading means that the attempt to read that device returned a failure. The failure could have been from a bus failure or that the device itself had an internal failure. For instance, a system may only have one DIMM and it would report only that one value, and the values for the other DIMM's would all be 00h. 5.23.2.5 Thermal Data Update Rate The temperature values are updated every 200 ms in the PCH, so reading more often than that simply returns the same data multiple times. Also, the data may be up to 200 ms old if the external controller reads the data right before the next update window. 5.23.2.6 Temperature Comparator and Alert The PCH has the ability to alert the external controller when temperatures are out of range. This is done using the PCH's TEMP_ALERT# signal. The alert is a simple comparator. If any device's temperature is outside the limit range for that device, then the signal is asserted (electrical low). Note that this alert does not use the SML1ALERT#. The PCH supports 3 ranges: 1. Processor Package range - upper and lower limit (8 bits each, in degrees C). 2. PCH range - upper and lower limit (8 bits each, in degrees C) for PCH temperature. 3. DIMM range - upper and lower limit (8 bits each, in degrees C), applies to all DIMM's (up to 4 supported) that are enabled. Disabled (unpopulated) DIMMs do not participate in the thermal compares. The comparator checks if the device is within the specified range, including the limits. For example, a device that is at 100 degrees when the upper limit is 100 will not trigger the alert. Likewise, a device that is at 70 degrees when the lower limit is 70 will not trigger the alert. The compares are done only on devices that have been enabled by BIOS for checking. Since BIOS knows how many DIMM's and processors are in the system, it enables the checking only for those devices that are physically present. 246 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description The compares are done in firmware, so all the compares are executed in one software loop and at the end, if there is any out of bound temperature, the PCH's TEMP_ALERT# signal is asserted. When the external controller sees the TEMP_ALERT# signal low, it knows some device is out of range. It can read the temperatures and then change the limits for the devices. Note that it may take up to 250 ms before the actual writes cause the signal to change state. For instance if the PCH is at 105 degrees and the limit is 100, the alert is triggered. If the controller changes the limits to 110, the TEMP_ALERT# signal may remain low until the next thermal sampling window (every 200 ms) occurs and only then go high, assuming the PCH was still within its limits. At boot, the controller can monitor the TEMP_ALERT# signal state. When BIOS has finished all the initialization and enabled the temperature comparators, the TEMP_ALERT# signal will be asserted since the default state of the limit registers is 0h; hence, when the PCH first reads temperatures, they will be out of range. This is the positive indication that the external controller may now read thermal information and get valid data. If the TEMP_ALERT# signal is enabled and not asserted within 30 seconds after PLTRST#, the external controller should assume there is a fatal error and handle accordingly. In general the TEMP_ALERT# signal will assert within 1-4 seconds, depending on the actual BIOS implementation and flow. Note: The TEMP_ALERT# assertion is only valid when PLTRST# is deasserted. The controller should mask the state of this signal when PLTRST# is asserted. Since the controller may be powered even when the PCH and the rest of the platform are not, the signal may glitch as power is being asserted, thus the controller should wait until PLTRST# has deasserted before monitoring the signal. 5.23.2.6.1 Special Conditions The external controller should have a graceful means of handling the following: 1. TEMP_ALERT# asserts, and the controller reads PCH, but all temperature values are within limits. In this case, the controller should assume that by the time the controller could read the data, it had changed and moved back within the limits. 2. External controller writes new values to temperature limits, but TEMP_ALERT# is still asserted after several hundred msecs. When read, the values are back within limits. In this case, the controller should treat this as case where the temperature changed and caused TEMP_ALERT# assertion, and then changed again to be back within limits. 3. There is the case where the external controller writes an update to the limit register, while the PCH is collecting the thermal information and updating the thermal registers. The limit change will only take affect when the write completes and the Intel ME can process this change. If the Intel ME is already in the process of collecting data and doing the compares, then it will continue to use the old limits during this round of compares, and then use the new limits in the next compare window. 4. Each SMBus write to change the limits is an atomic operation, but is distinct in itself. Therefore the external controller could write PCH limit, and then write DIMM limit. In the middle of those 2 writes, the thermal collecting procedure could be called by the Intel ME, so that the comparisons for the limits are done with the new PCH limits but the old DIMM limits. Note: The limit writes are done when the SMBus write is complete; therefore, the limits are updated atomically with respect to the thermal updates and compares. There is never a case where the compares and the thermal update are interrupted in the middle by the write of new limits. The thermal updates and compares are done as one noninterruptible routine, and then the limit writes would change the limit value outside of that routine. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 247 Functional Description 5.23.2.7 BIOS Set Up In order for the PCH to properly report temperature and enable alerts, the BIOS must configure the PCH at boot or from suspend/resume state by writing the following information to the PCH MMIO space. This information is NOT configurable using the external controller. * Enables for each of the possible thermal alerts (PCH and DIMM). Note that each DIMM is enabled individually. * Enables for reading DIMM and PCH temperatures. Note that each can be enabled individually. * SMBus address to use for each DIMM. Setting up the temperature calculation equations. 5.23.2.8 SMBus Rules The PCH may NACK an incoming SMBus transaction. In certain cases the PCH will NACK the address, and in other cases it will NACK the command depending on internal conditions (for example, errors, busy conditions). Given that most of the cases are due to internal conditions, the external controller must alias a NACK of the command and a NACK of the address to the same behavior. The controller must not try to make any determination of the reason for the NACK, based on the type of NACK (command vs. address). The PCH will NACK when it is enabled but busy. The external controller is required to retry up to 3 times when they are NACK'ed to determine if the FW is busy with a data update. When the data values are being updated by the Intel ME, it will force this NACK to occur so that the data is atomically updated to the external controller. In reality if there is a NACK because of the PCH being busy, in almost all cases the next read will succeed since the update internally takes very little time. The only long delay where there can be a NACK is if the internal Intel ME engine is reset. This is due to some extreme error condition and is therefore rare. In this case the NACK may occur for up to 30 seconds. After that, the external controller must assume that the PCH will never return good data. Even in the best of cases, when this internal reset occurs, it will always be a second or 2 to re-enable responding. 5.23.2.8.1 During Block Read On the Block Read, the PCH will respect the NACK and Stop indications from the external controller, but will consider this an error case. It will recover from this case and correctly handle the next SMBus request. The PCH will honor STOP during the block read command and cease providing data. On the next Block Read, the data will start with byte 0 again. However, this is not a recommended usage except for 'emergency cases'. In general the external controller should read the entire length of data that was originally programmed. 5.23.2.8.2 Block Read Special Handling On the Block Read, the PCH will respect the NACK and Stop indications from the external controller, but will consider this an error case. It will recover from this case and correctly handle the next SMBus request. The PCH will honor STOP during the block read command and cease providing data. On the next Block Read, the data will start with byte 0 again. However, this is not a recommended usage except for 'emergency cases'. In general the external controller should read the entire length of data that was originally programmed. 248 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.23.2.9 Case for Considerations Below are some corner cases and some possible actions that the external controller could take. Note that a 1-byte sequence number is available to the data read by the external controller. Each time the PCH updates the thermal information it will increment the sequence number. The external controller can use this value as an indication that the thermal FW is actually operating. Note that the sequence number will roll over to 00h when it reaches FFh. 1. Power on: The PCH will not respond to any SMBus activity (on SMLink1 interface) until it has loaded the thermal Firmware (FW), which in general would take 1-4 seconds. During this period the PCH will NACK any SMBus transaction from the external controller. The load should take 1-4 seconds, but the external controller should design for 30 seconds based on long delays for S4 resume which takes longer than normal power up. This would be an extreme case, but for larger memory footprints and nonoptimized recovery times, 30 seconds is a safe number to use for the timeout. Recover/Failsafe: if PCH has not responded within 30 seconds, the external controller can assume that the system has had a major error and the external controller should ramp the fans to some reasonably high value. The only recover from this is an internal reset on the PCH, which is not visible to the external controller. Therefore the external controller might choose to poll every 10-60 seconds (some fairly long period) hereafter to see if the PCH's thermal reporting has come alive. 2. PCH's Thermal FW hangs and requires an internal reset which is not visible to the external controller. The PCH will NACK any SMBus transaction from the external controller. The PCH may not be able to respond for up to 30 seconds while the FW is being reset and reconfigured. The external controller could choose to poll every 1-10 seconds to see if the thermal FW has been successfully reset and is now providing data. General recovery for this case is about 1 second, but 30 seconds should be used by the external controller at the timeout. Recovery/Failsafe: same as in case #1. 3. Fatal PCH error, causes a global reset of all components. When there is a fatal PCH error, a global reset may occur, and then case #1 applies. The external controller can observe, if desired, PLTRST# assertion as an indication of this event. 4. PCH thermal FW fails or is hung, but no reset occurs The sequence number will not be updated, so the external controller knows to go to failsafe after some number of reads (8 or so) return the same sequence number. The external controller could choose to poll every 1-10 seconds to see if the thermal FW has been successfully reset and working again. In the absence of other errors, the updates for the sequence number should never be longer than 400 ms, so the number of reads needed to indicate that there is a hang should be at around 2 seconds. But when there is an error, the sequence number may not get updated for seconds. In the case that the external controller sees a NACK from the PCH, then it should restart its sequence counter, or otherwise be aware that the NACK condition needs to be factored into the sequence number usage. The use of sequence numbers is not required, but is provided as a means to ensure correct PCH FW operation. 5. When PCH updates the Block Read data structure, the external controller gets a NACK during this period. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 249 Functional Description To ensure atomicity of the SMBus data read with respect to the data itself, when the data buffer is being updated, the PCH will NACK the Block Read transaction. The update is only a few micro-seconds, so very short in terms of SMBus polling time; therefore, the next read should be successful. The external controller should attempt 3 reads to handle this condition before moving on. If the Block read has started (that is, the address is ACK'ed) then the entire read will complete successfully, and the PCH will update the data only after the SMBus read has completed. 6. System is going from S0 to S3/4/5. Note that the thermal monitoring FW is fully operational if the system is in S0/S1, so the following only applies to S3/4/5. When the PCH detects the OS request to go to S3/4/5, it will take the SMLink1 controller offline as part of the system preparation. The external controller will see a period where its transactions are getting NACK'ed, and then see SLP_S3# assert. This period is relatively short (a couple of seconds depending on how long all the devices take to place themselves into the D3 state), and would be far less than the 30 second limit mentioned above. 7. TEMP_ALERT# - Since there can be an internal reset, the TEMP_ALERT# may get asserted after the reset. The external controller must accept this assertion and handle it. 5.23.2.9.1 Example Algorithm for Handling Transaction One algorithm for the transaction handling could be summarized as follows. This is just an example to illustrate the above rules. There could be other algorithms that can achieve the same results. 1. Perform SMBus transaction. 2. If ACK, then continue 3. If NACK 250 a. Try again for 2 more times, in case the PCH is busy updating data. b. If 3 successive transactions receive NACK, then * Ramp fans, assuming some general long reset or failure * Try every 1-10 seconds to see if SMBus transactions are now working * If they start then return to step 1 * If they continue to fail, then stay in this step and poll, but keep the fans ramped up or implement some other failure recovery mechanism. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.24 Intel(R) High Definition Audio (Intel(R) HD Audio) Overview (D27:F0) The PCH's Intel(R) High Definition Audio (Intel(R) HD Audio) controller communicates with the external codec(s) over the Intel High Definition Audio serial link. The controller consists of a set of DMA engines that are used to move samples of digitally encoded data between system memory and an external codec(s). The PCH implements four output DMA engines and 4 input DMA engines. The output DMA engines move digital data from system memory to a D-A converter in a codec. PCH implements a single Serial Data Output signal (HDA_SDOUT) that is connected to all external codecs. The input DMA engines move digital data from the A-D converter in the codec to system memory. The PCH implements four Serial Digital Input signals (HDA_SDI[3:0]) supporting up to four codecs. Audio software renders outbound and processes inbound data to/from buffers in system memory. The location of individual buffers is described by a Buffer Descriptor List (BDL) that is fetched and processed by the controller. The data in the buffers is arranged in a predefined format. The output DMA engines fetch the digital data from memory and reformat it based on the programmed sample rate, bit/sample and number of channels. The data from the output DMA engines is then combined and serially sent to the external codecs over the Intel High Definition Audio link. The input DMA engines receive data from the codecs over the Intel High Definition Audio link and format the data based on the programmable attributes for that stream. The data is then written to memory in the predefined format for software to process. Each DMA engine moves one stream of data. A single codec can accept or generate multiple streams of data, one for each A-D or D-A converter in the codec. Multiple codecs can accept the same output stream processed by a single DMA engine. Codec commands and responses are also transported to and from the codecs using DMA engines. The PCH HD audio controller supports the Function Level Reset (FLR). 5.25 PCH Intel(R) Management Engine Firmware The PCH offers different firmware options depending on the design (server or workstation) and platform usage models. In all cases, SPI Flash is required to connect to PCH to load the Intel ME FW. Please also see platform specific PDG for detailed HW requirements. 5.25.1 Intel(R) Server Platform Services Firmware Intel(R) Server Platform Services FW is for server platforms. It comes in four flavors. 5.25.1.1 Silicon Enabling This option provides the fundamental Intel ME FW functions required to boot a server design. In addition it provides following functions: * Power management controller (PMC) patching to provide a way of applying future enhancements or fixes to PMC Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 251 Functional Description 5.25.1.2 Intel(R) Intelligent Power Node Manager 2.0 Intel(R) Intelligent Power Node Manager 2.0 is a platform power reporting and capping technology, which provides an enhanced set of features, as compared to its previous version. -- Intel Intelligent Power Node Manager 2.0 supports multiple power policies for multiple power domains, including thermal policies. -- The enhanced algorithms provide shorter response times, enhanced dynamic range of power control, and reliable and uninterrupted power capping even during OS or BMC failure. -- By using an intelligent algorithm system, system performance is improved for a given power limit. -- Power supply optimization technology reduces cost or improve efficiency of power supplies. -- Server platform services is an accompanying function that provides access to PECI information by the BMC - critical selected information is available for efficient aggregated access by the BMC without losing the access to any other information available in a raw format. 5.25.1.3 Manageability Controller (MC) Compliant with Data Center Management Interface (DCMI) Specification This option provides a building block infrastructure for OEMs to configure and adopt the manageability controller according to their platform design needs without spending development or engineering time for server manageability. MC also provides an ability to interface with external Service Processors for advanced manageability requirements. Hardware features supported: * Four PWM and Eight TACHS providing maximum of four Thermal zones with two TACHS per zone * 12 GPIO dedicated for the Manageability Controller for LED and other controls * Three SMBus Transports, two dedicated and one shared with Host * SST, PECI and MEI transports * Either Side-band SMBus Intel LOMs or Integrated MAC to external PHY * LM75/TMP75 Thermal Sensors * PMBus for Power Instrumentation and Control Manageability Features supported: * 128 Sensors capable to be configurable as I2C, PECI, SST, GPIO, PMBus and Virtual Sensors. * Up to 32 individually configurable actions based on the Sensors such as Fan Speed Control, LED Controls and any other custom build control mechanisms derived from the sensors. * Piece-wise, Clamped algorithms for Fan Speed Control configurable through PIA. * All commands of DCMI 1.5 including all DCMI 1.0 features. * Additional IPMI commands for Chassis, Sensor, Storage, and Transport for Provisioning and Configuration for OEMs. * IPMB communication to external Server Processors for Platform Events and Alerts. * Well documented BIOS to MC interaction. * Both the simple DCMI-compliant power management interface as well as the full Intel Intelligent Power Node Manager 2.0 interface for provisioning and data security. 252 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description Security Features: * Security is provided for manufacturing data, user configuration and provisioning data through encryption using CBC-128 and xRC4. * RMCP+ authentication and integrity algorithms support includes MD5, SHA1, and SHA-256. * Capable of providing PSK and RSA certificate verification 5.25.1.4 Combined Intel(R) Intelligent Power Node Manager 2.0 and Management Controller Compliant with DCMI A fourth SPS FW option combines both Intel Intelligent Power Node Manager 2.0 and DCMI features. 5.25.2 Intel(R) AMT 7.0 (SRV/WS SKUs Only) Intel Active Management Technology is a set of advanced manageability features developed to meet the evolving demands placed on IT to manage a network infrastructure. Intel AMT reduces the Total Cost of Ownership (TCO) for IT management through features such as asset tracking, remote manageability, and robust policybased security, resulting in fewer desk-side visits and reduced incident support durations. Intel AMT extends the manageability capability for IT through Out Of Band (OOB), allowing asset information, remote diagnostics, recovery, and contain capabilities to be available on client systems even when they are in a low power, or "off" state, or in situations when the operating system is hung. In 2005, Intel developed a set of manageability services called Intel Active Management Technology (Intel AMT). To increase features and reduce cost in 2006 Intel integrated the operating environment for AMT to run on all Intel chipsets: * A microcontroller and support HW was integrated in the MCH (North Bridge) * Additional support HW resided in ICH (South Bridge) This embedded operating environment is called the Intel Management Engine (Intel ME). In 2008 Intel integrated an additional microcontroller called the Virtualization Engine (VE). In 2009 with platform repartitioning, Intel ME and VE HW was designed to reside in PCH. Key properties of Intel ME: * Connectivity -- Integration into I/O subsystem of PCH -- Delivers advanced I/O functions * Security -- More secure (Intel root of trust) and isolated execution -- Increased security of flash file system * Modularity and Partitioning -- OSV, VMM and SW Independence -- Respond rapidly to competitive changes * Power -- Always On Always Connected -- Advanced functions in low power S3-S4-S5 operation -- OS independent PM & thermal heuristics Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 253 Functional Description Intel ME FW provides a variety of services that range from low-level hardware initialization and provisioning to high-level end-user software based IT manageability services. One of Intel ME FW's most established and recognizable features is Intel Active Management Technology. Figure 5-30. PCH Intel(R) Management Engine (Intel(R) ME) High-Level Block Diagram Intel(R) Q PI 5.25.3 Intel(R) Management Engine Requirements Intel ME is a platform-level solution that utilizes multiple system components including: * The Intel ME is the general purpose controller that resides in PCH. It operates in parallel to and is resource-isolated from the host processor. * The flash device stores Intel ME firmware (FW) code that is executed by the Intel ME for its operations. In M0, the highest power state for Intel ME, this code is loaded from flash into DRAM and cached in secure and isolated SRAM. Code that resides in DRAM is stored in 16 MB of unified memory architecture (UMA) memory taken off the highest order rank in channel 0. PCH controls the flash device through the SPI interface and internal logic. * In order to interface with DRAM, the Intel ME utilizes the integrated memory controller (IMC) present in the processor. DMI serves as the interface for communication between the IMC and Intel ME. This interfacing occurs in only M0 power state. In the lower Intel ME power state, M3, code is executed exclusively from secure and isolated Intel ME local RAM. * The LAN controller embedded in PCH as well as Intel Gigabit Platform LAN Connect device are required for Intel AMT network connectivity. (SRV/WS SKUs Only) * BIOS to provide asset detection and POST diagnostics (BIOS and Intel ME FW can optionally share same flash memory device). * An ISV software package - such as LANDesk*, Altiris, or Microsoft SMS* can be used to take advantage of Intel AMT's platform manageability capabilities. (SRV/ WS SKUs Only) 254 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.26 Serial Peripheral Interface (SPI) The Serial Peripheral Interface (SPI) is a 4-pin interface that provides a lower-cost alternative for system flash versus the Firmware Hub on the LPC bus. The 4-pin SPI interface consists of clock (CLK), master data out (Master Out Slave In (MOSI)), master data in (Master In Slave Out (MISO)) and an active low chip select (SPI_CS[1:0]#). The PCH supports up to two SPI flash devices using two separate Chip Select pins. Each SPI flash device can be up to 16 MB. The PCH SPI interface supports 20 MHz, 33 MHz and 50 MHz SPI devices. A SPI Flash device on with Chip Select 0 with a valid descriptor MUST be attached directly to the PCH. Communication on the SPI bus is done with a Master - Slave protocol. The Slave is connected to the PCH and is implemented as a tri-state bus. Note: If Boot BIOS Strap placed on LPC, but PCH's SPI bus with to Section 2.26 for ="00" LPC is selected as the location for BIOS. BIOS may still be all platforms with PCH requires SPI flash connected directly to the a valid descriptor connected to Chip Select 0 in order to boot. Refer details of Boot BIOS strap settings. Note: When SPI is selected by the Boot BIOS Destination Strap and a SPI device is detected by the PCH, LPC based BIOS flash is disabled. 5.26.1 SPI Supported Feature Overview SPI Flash on the PCH has two operational modes, descriptor and non-descriptor. 5.26.1.1 Non-Descriptor Mode Non-Descriptor Mode is not supported as a valid flash descriptor is required for all PCH Platforms. 5.26.1.2 Descriptor Mode Descriptor Mode is required for all SKUs of PCH. It enables many new features of the chipset: * * * * * * * * * * Integrated Gigabit Ethernet and Host processor for Gigabit Ethernet Software Intel Active Management Technology (SRV/WS SKUs Only) Intel ME Firmware PCI Express* root port configuration Supports up to two SPI components using two separate chip select pins -- 1 SPI Flash and 1 user authentication device. Hardware enforced security restricting master accesses to different regions Chipset Soft Strap regions provides the ability to use Flash NVM as an alternative to hardware pull-up/pull-down resistors for PCH and Processor Supports the SPI Fast Read instruction and frequencies of up to 50 MHz Support Single Input, Dual Output Fast read Uses standardized Flash Instruction Set Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 255 Functional Description 5.26.1.2.1 SPI Flash Regions In Descriptor Mode the Flash is divided into five separate regions: Region Content 0 Flash Descriptor 1 BIOS 2 Intel ME 3 Gigabit Ethernet 4 Platform Data Only three masters can access the four regions: Host processor running BIOS code, Integrated Gigabit Ethernet and Host processor running Gigabit Ethernet Software, and Intel Management Engine. The Flash Descriptor and Intel ME region are the only required regions. The Flash Descriptor has to be in Region 0 and Region 0 must be located in the first sector of Device 0 (offset 10). Flash Region Sizes SPI flash space requirements differ by platform and configuration. The Flash Descriptor requires one 4 KB or larger block. GbE requires two 4 KB or larger blocks. The amount of flash space consumed is dependent on the erase granularity of the flash part and the platform requirements for the Intel ME and BIOS regions. The Intel ME region contains firmware to support Intel Active Management Technology, and other Intel ME capabilities. Table 5-62. Region Size versus Erase Granularity of Flash Components 5.26.2 Region Size with 4 KB Blocks Size with 8 KB Blocks Size with 64 KB Blocks Descriptor 4 KB 8 KB 64 KB GbE 8 KB 16 KB 128 KB BIOS Varies by Platform Varies by Platform Varies by Platform ME Varies by Platform Varies by Platform Varies by Platform Flash Descriptor The maximum size of the Flash Descriptor is 4 KB. If the block/sector size of the SPI flash device is greater than 4 KB, the flash descriptor will only use the first 4 KB of the first block. The flash descriptor requires its own block at the bottom of memory (00h). The information stored in the Flash Descriptor can only be written during the manufacturing process as its read/write permissions must be set to Read only when the computer leaves the manufacturing floor. The Flash Descriptor is made up of eleven sections (see Figure 5-31). 256 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description Figure 5-31. Flash Descriptor Sections 4KB OEM Section Descriptor Upper MAP Intel Management Engine VSCC Table Reserved PCH Soft Straps Master Region Component Descriptor MAP Signature 10h 1. The Flash signature selects Descriptor Mode as well as verifies if the flash is programmed and functioning. The data at the bottom of the flash (offset 10h) must be 0FF0A55Ah in order to be in Descriptor mode. 2. The Descriptor map has pointers to the other five descriptor sections as well as the size of each. 3. The component section has information about the SPI flash in the system including: the number of components, density of each, illegal instructions (such as chip erase), and frequencies for read, fast read and write/erase instructions. 4. The Region section points to the three other regions as well as the size of each region. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 257 Functional Description 5. The master region contains the security settings for the flash, granting read/write permissions for each region and identifying each master by a requestor ID. See Section 5.26.2.1 for more information. 6 & 7. The Processor and PCH chipset soft strap sections contain Processor and PCH configurable parameters. 8. The Reserved region between the top of the Processor strap section and the bottom of the OEM Section is reserved for future chipset usages. 9.The Descriptor Upper MAP determines the length and base address of the Intel ME VSCC Table. 10.The Intel ME VSCC Table holds the JEDEC ID and the VSCC information of the entire SPI Flash supported by the NVM image. 11.OEM Section is 256 Bytes reserved at the top of the Flash Descriptor for use by OEM. 5.26.2.1 Descriptor Master Region The master region defines read and write access setting for each region of the SPI device. The master region recognizes three masters: BIOS, Gigabit Ethernet, and Intel ME. Each master is only allowed to do direct reads of its primary regions. Table 5-63. Region Access Control Table Master Read/Write Access 5.26.3 Region Processor and BIOS Intel(R) ME GbE Controller Descriptor N/A N/A N/A BIOS Processor and BIOS can always read from and write to BIOS Region Read / Write Read / Write Intel ME Read / Write Intel ME can always read from and write to Intel ME Region Read / Write Gigabit Ethernet Read / Write Read / Write GbE software can always read from and write to GbE region Platform Data Region N/A N/A N/A Flash Access There are two types of flash accesses: Direct Access: * Masters are allowed to do direct read only of their primary region. -- Gigabit Ethernet region can only be directly accessed by the Gigabit Ethernet controller. Gigabit Ethernet software must use Program Registers to access the Gigabit Ethernet region. * Master's Host or Intel ME virtual read address is converted into the SPI Flash Linear Address (FLA) using the Flash Descriptor Region Base/Limit registers. Program Register Access: * Program Register Accesses are not allowed to cross a 4 KB boundary and can not issue a command that might extend across two components. * Software programs the FLA corresponding to the region desired. -- Software must read the devices Primary Region Base/Limit address to create a FLA. 258 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.26.3.1 Direct Access Security * Requester ID of the device must match that of the primary Requester ID in the Master Section * Calculated Flash Linear Address must fall between primary region base/limit * Direct Write not allowed * Direct Read Cache contents are reset to 0's on a read from a different master -- Supports the same cache flush mechanism in ICH7 which includes Program Register Writes 5.26.3.2 Register Access Security * Only primary region masters can access the registers. Note: Processor running Gigabit Ethernet software can access Gigabit Ethernet registers. * Masters are only allowed to read or write those regions they have read/write permission. * Using the Flash Region Access Permissions, one master can give another master read/write permissions to their area. * Using the five Protected Range registers, each master can add separate read/write protection above that granted in the Flash Descriptor for their own accesses. -- Example: BIOS may want to protect different regions of BIOS from being erased. -- Ranges can extend across region boundaries. 5.26.4 Serial Flash Device Compatibility Requirements A variety of serial flash devices exist in the market. For a serial flash device to be compatible with the PCH SPI bus, it must meet the minimum requirements detailed in the following sections. Note: Depending on the SKU, PCH platforms require Intel ME firmware. Note: The HEDT SKU only supports the fundamental Intel ME function. 5.26.4.1 PCH SPI Based BIOS Requirements A serial flash device must meet the following minimum requirements when used explicitly for system BIOS storage. * Erase size capability of at least one of the following: 64 Kbytes, 8 Kbytes, 4 Kbytes, or 256 bytes. * Device must support multiple writes to a page without requiring a preceding erase cycle (Refer to Section 5.26.5) * Serial flash device must ignore the upper address bits such that an address of FFFFFFh aliases to the top of the flash memory. * SPI Compatible Mode 0 support (clock phase is 0 and data is latched on the rising edge of the clock). * If the device receives a command that is not supported or incomplete (less than 8 bits), the device must complete the cycle gracefully without any impact on the flash content. * An erase command (page, sector, block, chip, etc.) must set all bits inside the designated area (page, sector, block, chip, and so forth) to 1 (Fh). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 259 Functional Description * Status Register bit 0 must be set to 1 when a write, erase or write to status register is in progress and cleared to 0 when a write or erase is NOT in progress. * Devices requiring the Write Enable command must automatically clear the Write Enable Latch at the end of Data Program instructions. * Byte write must be supported. The flexibility to perform a write between 1 byte to 64 bytes is recommended. * Hardware Sequencing requirements are optional in BIOS only platforms. * SPI flash parts that do not meet Hardware sequencing command set requirements may work in BIOS only platforms using software sequencing. 5.26.4.2 Integrated LAN Firmware SPI Flash Requirements A serial flash device that will be used for system BIOS and Integrated LAN or Integrated LAN only must meet all the SPI Based BIOS Requirements plus: * Hardware sequencing. * 4, 8, or 64 KB erase capability must be supported. 5.26.4.2.1 SPI Flash Unlocking Requirements for Integrated LAN BIOS must ensure there is no SPI flash based read/write/erase protection on the GbE region. GbE firmware and drivers for the integrated LAN need to be able to read, write and erase the GbE region at all times. 5.26.4.3 Intel(R) Management Engine (Intel(R) ME) Firmware SPI Flash Requirements Intel ME Firmware must meet the SPI flash based BIOS Requirements plus: * Hardware sequencing. * Flash part must be uniform 4 KB erasable block throughout the entire device or have 64 KB blocks with the first block (lowest address) divided into 4 KB or 8 KB blocks. * Write protection scheme must meet SPI flash unlocking requirements for Intel ME. 5.26.4.3.1 SPI Flash Unlocking Requirements for Intel(R) ME Flash devices must be globally unlocked (read, write and erase access on the Intel ME region) from power on by writing 00h to the flash's status register to disable write protection. If the status register must be unprotected, it must use the enable write status register command 50h or write enable 06h. Opcode 01h (write to status register) must then be used to write a single byte of 00h into the status register. This must unlock the entire part. If the SPI flash's status register has non-volatile bits that must be written to, bits [5:2] of the flash's status register must be all 0h to indicate that the flash is unlocked. If bits [5:2] return a non zero values, the Intel ME firmware will send a write of 00h to the status register. This must keep the flash part unlocked. If there is no need to execute a write enable on the status register, then opcodes 06h and 50h must be ignored. After global unlock, BIOS has the ability to lock down small sections of the flash as long as they do not involve the Intel ME or GbE region. 260 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.26.4.4 Hardware Sequencing Requirements Table 5-64 contains a list of commands and the associated opcodes that a SPI-based serial flash device must support in order to be compatible with hardware sequencing. Table 5-64. Hardware Sequencing Commands and Opcode Requirements Commands Notes Write to Status Register 01h Writes a byte to SPI flash's status register. Enable Write to Status Register command must be run prior to this command. Program Data 02h Single byte or 64 byte write as determined by flash part capabilities and software. Read Data 03h Write Disable 04h Read Status 05h Write Enable 06h Fast Read 0Bh Enable Write to Status Register Erase 5.26.4.4.1 Opcode 06h or 50h Programmable Full Chip Erase C7h JEDEC ID 9Fh Outputs contents of SPI flash's status register Enables a bit in the status register to allow an update to the status register 256B, 4 Kbyte, 8 Kbyte or 64 Kbyte See Section 5.26.4.4.1. Single Input, Dual Output Fast Read The PCH now supports the functionality of a single input, dual output fast read. Opcode and address phase are shifted in serially to the serial flash SI (Serial In) pin. Data is read out after 8 clocks (dummy bits or wait states) from the both the SI and SO pin effectively doubling the through put of each fast read output. In order to enable this functionality, both Single Input Dual Output Fast Read Supported and Fast Read supported must be enabled. 5.26.4.4.2 JEDEC ID Since each serial flash device may have unique capabilities and commands, the JEDEC ID is the necessary mechanism for identifying the device so the uniqueness of the device can be comprehended by the controller (master). The JEDEC ID uses the opcode 9Fh and a specified implementation and usage model. This JEDEC Standard Manufacturer and Device ID read method is defined in Standard JESD21-C, PRN03-NV. 5.26.5 Multiple Page Write Usage Model The system BIOS and Intel ME firmware usage models require that the serial flash device support multiple writes to a page (minimum of 512 writes) without requiring a preceding erase command. BIOS commonly uses capabilities such as counters that are used for error logging and system boot progress logging. These counters are typically implemented by using byte-writes to `increment' the bits within a page that have been designated as the counter. The Intel ME firmware usage model requires the capability for multiple data updates within any given page. These data updates occur using bytewrites without executing a preceding erase to the given page. Both the BIOS and Intel ME firmware multiple page write usage models apply to sequential and non-sequential data writes. Note: This usage model requirement is based on any given bit only being written once from a `1' to a `0'without requiring the preceding erase. An erase would be required to change bits back to the 1 state. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 261 Functional Description 5.26.5.1 Soft Flash Protection There are two types of flash protection that are not defined in the flash descriptor supported by PCH: 1. BIOS Range Write Protection 2. SMI#-Based Global Write Protection Both mechanisms are logically OR'd together such that if any of the mechanisms indicate that the access should be blocked, then it is blocked. Table 5-65 provides a summary of the mechanisms. Table 5-65. Flash Protection Mechanism Summary Mechanism Accesses Blocked Reset-Override or SMI#Override? Range Specific? Equivalent Function on FWH BIOS Range Write Protection Writes Yes Reset Override FWH Sector Protection Write Protect Writes No SMI# Override Same as Write Protect in Intel ICHs for FWH A blocked command will appear to software to finish, except that the Blocked Access status bit is set in this case. 5.26.5.2 BIOS Range Write Protection The PCH provides a method for blocking writes to specific ranges in the SPI flash when the Protected BIOS Ranges are enabled. This is achieved by checking the Opcode type information (which can be locked down by the initial Boot BIOS) and the address of the requested command against the base and limit fields of a Write Protected BIOS range. Note: Once BIOS has locked down the Protected BIOS Range registers, this mechanism remains in place until the next system reset. 5.26.5.3 SMI# Based Global Write Protection The PCH provides a method for blocking writes to the SPI flash when the Write Protected bit is cleared (that is, protected). This is achieved by checking the Opcode type information (which can be locked down by the initial Boot BIOS) of the requested command. The Write Protect and Lock Enable bits interact in the same manner for SPI BIOS as they do for the FWH BIOS. 5.26.6 Flash Device Configurations The PCH-based platform must have a SPI flash connected directly to the PCH with a valid descriptor and Intel ME Firmware. BIOS may be stored in other locations such as Firmware Hub. Note this will not avoid the direct SPI flash connected to PCH requirement. 262 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.26.7 SPI Flash Device Recommended Pinout The table below contains the recommended serial flash device pin-out for an 8-pin device. Use of the recommended pin-out on an 8-pin device reduces complexities involved with designing the serial flash device onto a motherboard and allows for support of a common footprint usage model (refer to Section 5.26.8.1). Table 5-66. Recommended Pinout for 8-Pin Serial Flash Device Pin # Signal 1 Chips Select 2 Data Output 3 Write Protect 4 Ground 5 Data Input 6 Serial Clock 7 Hold / Reset 8 Supply Voltage Although an 8-pin device is preferred over a 16-pin device due to footprint compatibility, the following table contains the recommended serial flash device pin-out for a 16-pin SOIC. 5.26.8 Serial Flash Device Package Table 5-67. Recommended Pinout for 16-Pin Serial Flash Device 5.26.8.1 Pin # Signal Pin # Signal 1 Hold / Reset 9 Write Protect 2 Supply Voltage 10 Ground 3 No Connect 11 No Connect 4 No Connect 12 No Connect 5 No Connect 13 No Connect 6 No Connect 14 No Connect 7 Chip Select 15 Serial Data In 8 Serial Data Out 16 Serial Clock Common Footprint Usage Model In order to minimize platform motherboard redesign and to enable platform Bill of Material (BOM) selectability, many PC System OEM's design their motherboard with a single common footprint. This common footprint allows population of a soldered down device or a socket that accepts a leadless device. This enables the board manufacturer to support, using selection of the appropriate BOM, either of these solutions on the same system without requiring any board redesign. The common footprint usage model is desirable during system debug and by flash content developers since the leadless device can be easily removed and reprogrammed without damage to device leads. When the board and flash content is mature for highvolume production, both the socketed leadless solution and the soldered down leaded solution are available through BOM selection. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 263 Functional Description 5.26.8.2 Serial Flash Device Package Recommendations It is highly recommended that the common footprint usage model be supported. An example of how this can be accomplished is as follows: * The recommended pinout for 8-pin serial flash devices is used (refer to Section 5.26.7). * The 8-pin device is supported in either an 8-contact VDFPN (6x5 mm MLP) package or an 8-contact WSON (5x6 mm) package. These packages can fit into a socket that is land pattern compatible with the wide body SO8 package. * The 8-pin device is supported in the SO8 (150 mil) and in the wide-body SO8 (200 mil) packages. The 16-pin device is supported in the SO16 (300 mil) package. 5.27 Fan Control/Thermal Management The PCH implements 4 PWM and 8 TACH signals for integrated fan speed control. Note: Integrated fan speed control functionality requires a correctly configured system, including an appropriate processor, PCH with Intel(R) ME, Intel(R) ME Firmware, and system BIOS support. (SRV/WS SKUs only) 5.27.1 PWM Outputs This signal is driven as open-drain. An external pull-up resistor is integrated into the fan to provide the rising edge of the PWM output signal. The PWM output is driven low during reset, which represents 0% duty cycle to the fans. After reset de-assertion, the PWM output will continue to be driven low until one of the following occurs: * The internal PWM control register is programmed to a non-zero value by the appropriate firmware. * The watchdog timer expires (enabled and set at 4 seconds by default). * The polarity of the signal is inverted by firmware. Note that if a PWM output will be programmed to inverted polarity for a particular fan, then the low voltage driven during reset represents 100% duty cycle to the fan. 5.27.2 TACH Inputs This signal is driven as an open-collector or open-drain output from the fan. An external pull-up is expected to be implemented on the motherboard to provide the rising edge of the TACH input. This signal has analog hysteresis and digital filtering due to the potentially slow rise and fall times. This signal has a weak internal pull-up resistor to keep the input buffer from floating if the TACH input is not connected to a fan. 264 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Functional Description 5.28 Feature Capability Mechanism A set of registers is included in the PCH LPC Interface (Device 31, Function 0, offset E0h - EBh) that allows the system software or BIOS to easily determine the features supported by PCH. These registers can be accessed through LPC PCI configuration space, thus allowing for convenient single point access mechanism for chipset feature detection. This set of registers consists of: Capability ID (FDCAP) Capability Length (FDLEN) Capability Version and Vendor-Specific Capability ID (FDVER) Feature Vector (FVECT) 5.29 Intel(R) Virtualization Technology (SRV/WS SKUs Only) Intel(R) Virtualization Technology (Intel(R) VT) makes a single system appear as multiple independent systems to software. This allows for multiple, independent operating systems to be running simultaneously on a single system. Intel VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets. The first revision of this technology (Intel VT for IA-32 Intel(R) Architecture [Intel VT-x]) added hardware support in the processor to improve the virtualization performance and robustness. The second revision of this specification (Intel VT for Directed I/O [Intel VT-d]) adds chipset hardware implementation to improve I/O performance and robustness. The Intel VT-d spec and other Intel VT documents can be referenced here: http:// www.intel.com/technology/platform-technology/virtualization/index.htm 5.29.1 Intel(R) Virtualization Technology (Intel(R) VT) for Directed I/O (Intel(R) VT-d) Objectives The key Intel VT-d objectives are domain based isolation and hardware based virtualization. A domain can be abstractly defined as an isolated environment in a platform to which a subset of host physical memory is allocated. Virtualization allows for the creation of one or more partitions on a single system. This could be multiple partitions in the same OS or there can be multiple operating system instances running on the same system offering benefits such as system consolidation, legacy migration, activity partitioning or security. 5.29.2 Intel(R) VT-d features supported on PCH * The following devices and functions support FLR in PCH: -- High Definition Audio (Device 27: Function 0) -- SATA Host Controller #1 (Device 31: Function 2) -- SATA Host Controller #2 (Device 31: Function 5) -- USB2 (EHCI) Host Controller #1(Device 29: Function 0) -- USB2 (EHCI) Host Controller #2(Device 26: Function 0) -- GbE Lan Host Controller (Device 25: Function 0) * Interrupt virtualization support for IOxAPIC * Virtualization Support for HPETs Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 265 Functional Description 5.29.3 Support for Function Level Reset (FLR) in PCH Intel VT-d allows system software (VMM/OS) to assign I/O devices to multiple domains. The system software, then, requires ways to reset I/O devices or their functions within, as it assigns/re-assigns I/O devices from one domain to another. The reset capability is required to ensure the devices have undergone proper re-initialization and are not keeping the stale state. A standard ability to reset I/O devices is also useful for the VMM in case where a guest domain with assigned devices has become unresponsive or has crashed. PCI Express* defines a form of device hot reset which can be initiated through the Bridge Control register of the root/switch port to which the device is attached. However, the hot reset cannot be applied selectively to specific device functions. Also, no similar standard functionality exists for resetting root-complex integrated devices. Current reset limitations can be addressed through a function level reset (FLR) mechanism that allows software to independently reset specific device functions. 5.29.4 Virtualization Support for PCH's IOxAPIC The Intel VT-d architecture extension requires Interrupt Messages to go through the similar Address Remapping as any other memory requests. This is to allow domain isolation for interrupts such that a device assigned in one domain is not allowed to generate interrupts to another domain. The Address Remapping for Intel VT-d is based on the Bus:Device:Function field associated with the requests. Hence, it is required for the internal IOxAPIC to initiate the Interrupt Messages using a unique Bus:Device:Function. PCH supports BIOS programmable unique Bus:Device:Function for the internal IOxAPIC. The Bus:Device:Function field does not change the IOxAPIC functionality in anyway, nor promoting IOxAPIC as a stand-alone PCI device. The field is only used by the IOxAPIC in the following: * As the Requestor ID when initiating Interrupt Messages to the CPU * As the Completer ID when responding to the reads targeting the IOxAPIC's Memory-Mapped I/O registers 5.29.5 Virtualization Support for High Precision Event Timer (HPET) The Intel VT-d architecture extension requires Interrupt Messages to go through the similar Address Remapping as any other memory requests. This is to allow domain isolation for interrupts such that a device assigned in one domain is not allowed to generate interrupts to another domain. The Address Remapping for Intel VT-d is based on the Bus:Device:Function field associated with the requests. Hence, it is required for the HPET to initiate processor message interrupts using unique Bus:Device:Function. PCH supports BIOS programmable unique Bus:Device:Function for each of the HPET timers. The Bus:Device:Function field does not change the HPET functionality in anyway, nor promoting it as a stand-alone PCI device. The field is only used by the HPET timer in the following: * As the Requestor ID when initiating processor message interrupts to the Processor * As the Completer ID when responding to the reads targeting its Memory-Mapped registers The registers for the programmable Bus:Device:Function for HPET timer 7:0 reside under the Device 31:Function 0 LPC Bridge's configuration space. 266 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCH Ballout Definition 6 PCH Ballout Definition This chapter contains the PCH ballout information. Note: Not all listed signals are used on all PCH SKUs. See Chapter 2, "Signal Description" for details. Figure 6-1 shows the ballout from a top of the package view. Figure 6-2, Figure 6-3, Figure 6-4, Figure 6-5 show the ballout zoomed in from a top of package quadrant view. Figure 6-1. PCH Ballout (Top View) 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 AW VSS VSS AV NC_3 VSS CL KIN_ SAS1 P VSS TP15 CL KIN_ SAS1 N SAS3TXN SAS2TXP TP17 VSS SAS3TXP VSS SAS2TXN VSS VSS SAS0TXN SAS1TXN SAS0TXP CL KIN_ SAS0 P SAS_ RBIASN_ 0 VSS VSS HDA _RS T# GPIO13 LAD_1 PWM1 SAS_ RBIASP_0 AD_11 TACH0 /GPIO1 7 VSS PWM0 STOP# PIRQC# HDA _S Y NC VSS LAD_3 VSS AD_0 VSS AD_9 VSS LAD_0 AD_5 AD_25 REFCL K1 4 IN SAS_ L OAD2 VSS AD_7 VSS SAS_ DATAIN2 AU TP14 TP13 AT TP16 GPIO33 AR AP VSS AN SAS5TXN SAS4TXN SAS4TXP VSS AD_20 GNT 0# VSS VSS SAS5RXN SAS4RXN VSS VSS SAS1RXP SAS0RXP VSS VSS SERR# AM SAS5TXP TACH7 /GPIO7 1 VSS VSS C/BE0# AD_15 VSS VSS AD_16 AD_24 VSS VSS PERR# AD_12 VSS VSS SASSM BDATA2 AD_27 C/BE2# AD_14 AD_30 TP11 REQ0# C/BE1# GPIO64 GPIO66 SASSM BCL K2 PAR AD_23 TP18 LDRQ 1#/ G PI O 23 VSS AJ VSS SAS7TXP VSS HDA_ SDIN_ 2 HDA_ SDIN_ 3 HDA_ SDIN_ 0 AF VSS USBP_7 AE USBP_6 AD VSS AH AG SAS6TXN SAS7TXN AD_3 REQ 1#/ G PI O 50/ G SXCLK HDA_ SDIN_ 1 VSS AD_28 SAS7RXP SAS6RXP SAS5RXP SAS4RXP LAD_2 REQ TACH3 /GPIO7 2 # / G PI O 5 2 / G SXSL O A G NT2#/ G PI O 53/ G SXDI N AD_21 VSS DEVSEL# PIRQB# PWM3 TACH4 /GPIO6 8 VSS AD_19 AD_29 AD_18 LFRAME# TACH6 /GPIO7 0 VSS PIRQE# /GPIO2 VSS USBP_5 USBP_3 Y USBP_1 W VSS USBN_1 VSS C/BE3# VSS G NT 1 # / G PI O 5 1 / G SXDO UT SAS3RXP SAS2RXP FRAME# SAS1RXN SAS0RXN PIRQA# PIRQD# SAS_ RBIASP_ 1 PIRQH# /GPIO5 PWM2 TRDY# PLOCK# SAS_ RBIASN_ 1 AD_22 PIRQF# /GPIO3 CLK IN_P CI EQ 3 # / G PI O 5 4 / G TACH1 /GPIO1 VSS VCCXUS VCCXUS VCCRBIAS_ PU SASSM BCL K0 VSS PERN8 PERP8 VSS PERN4 PERP4 VSS PETP7 VSS VSS VCCXUS VCCXUS SASSM BCL K1 SASSM BDATA1 VSS PERP7 PERN7 VSS PERN3 PERP3 PETP6 PETN6 PETN5 VccIO VccIO VccIO VccIO Vc c PL L SAS1 V ccS A S1_5 VccRBI AS_SAS0 VSS VSS VSS VccIO VSS VSS VSS VSS VSS VSS VSS VSS PETP5 GNT3 # /GPIO5 5 VSS VSS VCCXUS VCCXUS Vc c PL L EXPU VCCXUS VCCXUS VSS PERP6 PERN6 VSS PERN2 PERP2 VSS VCCXUS VccIO VSS PERP5 PERN5 VSS PERP1 PERN1 PETP4 VSS V5REF Vcc ASW Vc c ASW Vc c ASW Vc c SCUS Vc cSCUS Vc c SCUS vccCore vccCore vccCore vccCore vccCore VCCXUS Vcc ASW Vc c ASW Vc c ASW Vc c SCUS Vc cSCUS Vc c SCUS vccCore vccCore vccCore vccCore vccCore VCCXUS VccIO VccIO VSS VccIO VccIO VSS Reserved Reserved VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VccIO VccIO VSS VccIO VccIO VSS Reserved Reserved TACH5 /GPIO6 9 VSS AD_6 VccIO VSS Vc c ASW Vcc ASW Vc c ASW vccCore vccCore vccCore vccCore vccCore VccIO VccIO VccIO VSS VccIO vccsus3_3 Vc c ASW Vcc ASW Vc c ASW vccCore vccCore vccCore vccCore vccCore VccIO VccIO VccIO VSS VSS VSS VccIO VccIO vccsus3_3 vccsus3_3 Vc c ASW VSS VSS VSS VSS VSS VSS VSS VSS Vc c ASW Vcc ASW Vc c ASW vccCore vccCore vccCore vccCore DcpSus DcpSus DMI_ZCOMP T VSS Vcc ASW Vc c ASW vccsus3_3 Vc c ASW Vcc ASW Vc c ASW vccCore vccCore vccCore vccCore VccIO vccsus3_3 VccIO VccIO R DSWODVREN VSS VSS vccsus3_3 VSS VSS vcc3_3 V ccDS W3_3 DcpSus vccSPI VccIO VccIO vcc3_3 DcpRTC VSS V ccA UP LL VccIO vccRTC DcpS usB yp DcpSST vcc3_3 VSS J RTCX2 L AN_ PHY_ PW R_ CT RL / G PI O S MB DA TA E 1 GPIO27 GPIO8 OC3 # /GPIO4 2 INTV RME N OC0 # /GPIO5 9 SST WAKE# ADR_CO M PLETE CL KIN_ DOT9 6 N CL KIN_ DOT9 6 P VSS RS MRS T# SM L0ALERT#/ G PI O 60 G PI O 31/ M G PI O 2 P WRB TN# OC6 # /GPIO1 0 SM L1ALERT#/ G PI O 74 SM BALERT#/ G PI O 11 OC4 # /GPIO4 3 DM I_ RCOM P VSS SDATAO UT0/ G PI O 39 SUSACK# DRAM PWROK GPIO57 SLP_LAN#/ G PI O 29 GPIO56 GPIO44 VSS VSS VccIO VSS V ccDFTE RM V ccDFTE RM Vc c APL L SATA VccIO V ccDFTE RM VSS VSS VSS Vc c VRM V _P ROC_IO VccDMI Vc c VRM SPI_MOSI SATA0G P/ G PI O 21 SPI_MISO SPI_CS1# SATA4G P/ G PI O 16 VccIO V ccDFTE RM SPI_CS0# SATAICOM PI TP21 SATAICOM PO SATA5G P/ G PI O 49 SATA3 COM PO vccCore TS_VSS4 Reserved Y VSS W DMIRB IA S TP3 VSS DMI_RX P _0 DMI_RX N_0 DMI_TX P _0 VSS VSS Vcc3_3 VSS DMI_RX N_1 DMI_RX P _1 VSS TP4 VSS TP5 Reserved Reserved Reserved Reserved Reserved Reserved VSS NC_6 VSS Reserved DMI_TX N_2 VSS VSS VSS N VSS M Reserved THRMTRIP B P M_S Y NC VSS L K VSS H NC_22 G VSS NC_8 VSS F P M_S YNC2 VSS VSS NC_18 NC_19 VSS VSS VSS VSS VSS VSS S A TA 5RX P S A TA 4RX P S ATA 3RX P S A TA2RX P S A TA 1RX P S A TA 0RX P Reserved Reserved Reserved Reserved Reserved Reserved Reserved PLTRST# PCIRST# SLP_S4# SDATAO UT1/ G PI O 48 GPIO45 BM BUSY#/ G PI O 0 S A TA 5RX N S A TA 4RX N S ATA 3RX N S A TA2RX N S A TA 1RX N S A TA 0RX N TS_VSS1 TS_VSS3 Reserved Reserved Reserved Reserved PECI NC_11 NC_7 NC_2 GPIO73 GPIO47 SLP_S5#/ G PI O 63 JTA G_TCK VSS SYS_ PWROK JTA G_TDO GPIO28 INIT3_3V # SYS_ RESET# SL OAD/GPIO3 8 VSS SATA3G P/ G PI O 37 GPIO18 RCIN# NM I# /GPIO3 5 VSS VSS VSS SPKR S A TA LE D# SATA2G P/ G PI O 36 A20GATE VSS SATA1G P/ G PI O 19 VSS SERIRQ VSS GPIO32 SPI_CLK S A TA 5TX P S A TA 4TX N VSS S A TA 5TX N VSS S A TA 4TX P VSS S ATA 3TX P S A TA 3TX N VSS S A TA 2TXP S A TA2TX N VSS SATA3 COM PI CL KIN_ SATA_ N TP22 CL KIN_ SATA_ P VSS TP20 SATA3 RRBIAS VSS S A TA 1TX P S A TA 1TX N S A TA 0TX P VSS S A TA 0TX N VSS TP19 VSS VSS VSS 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet VSS Reserved 9 DF_TVS Reserved VSS Reserved Reserved Reserved VSS Reserved VSS 8 7 6 J NC_15 Reserved VSS VSS CL KIN_ DM I_ N NC_24 NC_5 NC_14 VSS NC_12 NC_16 Reserved SM I# /GPIO2 0 VSS VSS VSS VSS CL KIN_ DM I_ P GPIO34 SUSCLK/ G PI O 62 P DMI_TX P _3 DMI_RX N_3 DMI_RXP _3 VSS VSS PME# R DMI_RX P _2 DMI_RXN_2 SCLO CK/ G PI O 22 JTA G_TMS T DMI_TX N_3 VSS VSS VSS C U VSS VSS TP12 GPIO46 V DMI_TX N_1 Vc c APL L EXP VSS VSS VSS VSS VSS PROCPWRGD Reserved DMI_TX P _1 NC_17 NC_20 NC_9 Reserved AB AA Reserved Reserved GPIO26 SLP_S3# JTA G_TDI AC VSS GPIO24 APWROK GPIO15 AD Reserved VSS VSS GPIO72 SLP_A# GPIO61 VSS VSS SMBCLK S ML0DA TA SML0CLK AE PETN1 VSS NC_10 NC_21 vccCore vccCore TS_VSS2 AF PETN3 PETP1 DMI_TX P _2 VccIO VSS AJ AH AG VSS DMI_TX N_0 VSS TP23 TP24 VSS VSS TP6 CL KIN_ GND0 _ N CL KIN_ GND0 _ P AL AK PETP2 VSS TP2 TP1 VSS VSS VSS VSS VSS VSS VSS VccIO PETP3 VSS D B A INTRUDE R# VSS VSS GPIO25 VSS PCH_ PWROK VSS G RI# F DPWROK RTCX1 VSS VCCAPL L DM I2 PETN4 PETN2 AD_31 AD_1 TACH2 /GPIO6 PETN7 vcc3_3 vcc3_3 vcc3_3 VSS VSS vcc3_3 AD_10 USBN_13 PETN8 VSS AD_26 USBN_3 USBP_13 VSS VSS VSS PIRQG# /GPIO4 PEG0 _ RBIASP AN AM Vc c PL L SAS0 Vc c ASW V ccS usHDA H PEG0 _ RBIASN VSS VSS SM L1CLK/ G PI O 58 VSS SAS_ CL OCK1 CLKI N_SPCI E0N CLKI N_SPCI E0P Vc c PL L SAS0 VSS VSS OC7 # /GPIO1 4 SAS_ DATAIN1 TP7 V ccS A S1_5 VSS SM L1DATA/ G PI O 75 P E G0_TP _1 P E G0_TP _0 VSS V ccS A S1_5 HDA _B CLK OC5#/GP IO9 VSS TP9 AP VccRBI AS_SAS1 Vc c AUBG V 5RE F_S us L VSS VSS VCCXUS AR VCCXUS VccRBI AS_SAS1 HDA _S DO K SAS_ L OAD1 VSS P E G0_TN_0 USBP_11 USBN_11 USBN_12 OC1 # /GPIO4 0 P E G0_TN_1 AU TP8 AT VSS VSS OC2 # /GPIO4 1 P E G0_TN_3 P E G0_TP _2 AV TP10 P E G0_RN_0 VSS USBRBIASp S LP _S US # P E G0_RP _1 VccIO VccIO USBRBIASn M AW NC_4 VccIO VccIO VSS PI O S A S _LE D# 1 VccIO VSS RDNACK/ G VSS 2 PETP8 USBP_9 USBN_9 ARN# / SUSPW P E G0_RN_2 USBP_10 USBN_10 USBP_12 S RTCRS T# 3 P E G0_RP _2 P E G0_RN_1 P E G0_TP _3 P E G0_TN_2 SASSM BDATA0 USBP_8 USBN_8 W VSS 4 VSS VSS GPIO65 GPIO67 S X S R E SE T USBP_2 VSS P E G0_RN_3 5 VSS VSS USBP_0 USBN_0 USBN_2 N SAS_DATAO UT2 VSS VSS AD_2 V P 6 VSS NC_1 AD_13 LDRQ0# IRDY# U RTCRS T# 7 P E G0_RP _3 VSS VccIO USBP_4 USBN_4 USBN_5 VSS VSS AD_17 SAS3RXN SAS2RXN USBN_7 USBN_6 VSS AD_8 VSS CLKIN_ SAS0 N SAS7RXN SAS6RXN SAS6TXP AC AB AA VSS VSS SAS_DATAO UT1 8 VSS P E G0_RP _0 VSS AD_4 AL AK SAS1TXP 9 SAS_ CL OCK2 E NC_13 VSS D NC_23 VSS C B A CHIP_ DETECT# VSS VSS 5 4 3 2 1 267 PCH Ballout Definition Figure 6-2. PCH Ballout (Top View - Upper Left) 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 AW VSS VSS AV NC_3 AU TP14 TP13 AT TP16 GPIO33 VSS CL KIN_ SAS1 P VSS TP15 CL KIN_ SAS1 N SAS3TXN SAS2TXP TP17 VSS SAS3TXP VSS AD_28 SAS7R XP SAS6RXP SAS2TXN VSS SAS1TXN SAS0TXP SAS1TXP VSS VSS SAS0TXN CL KIN_ SAS0 P SAS_ RBIASN_ 0 VSS GPIO13 LAD_1 PWM1 SAS_ RBIASP_ 0 VSS AD_8 VSS CL KIN_ SAS0 N VSS HDA_RS T# TACH0 /GPIO1 7 VSS AD_17 AR AP VSS AN SAS5TXN SAS4TXN SAS4TXP VSS AD_20 GNT 0# VSS VSS SAS5R XN SAS4RXN VSS VSS SAS1R XP SAS0RXP AM SAS5TXP TACH7 /GPIO7 1 VSS VSS C/BE0# AD_15 VSS VSS AD_16 AD_24 VSS VSS LAD_2 AD_27 C/BE2# AD_14 AD_30 TP11 REQ0# PAR AD_23 TP18 LDRQ 1#/ G PI O 23 VSS AJ VSS SAS7TXP VSS HDA_ SDIN_ 2 HDA_ SDIN_ 3 HDA_ SDIN_ 0 VSS AE USBP_6 AD VSS AC USBP_7 VSS SAS5RXP SAS4R XP REQ TACH3 /GPIO7 2 # / G PI O 5 2 / G SXSL O A G NT2#/ G PI O 53/ G SXDI N AD_21 VSS D EVSEL# PIRQB# PWM3 TACH4 /GPIO6 8 VSS AD_19 AD_29 AD_18 LFR AME# TACH6 /GPIO7 0 VSS PIRQE# /GPIO2 FR AME# VSS USBP_5 Y USBP_1 W VSS USBP_3 USBN_1 VSS SAS_ RBIASP_ 1 SAS_ RBIASN_ 1 CLK IN_P CI EQ 3 # / G PI O 5 4 / G SXSRESET VccIO VccIO VSS VccRBI AS_SAS1 V ccS A S 1_5 VccP VccIO VccIO VccIO VSS VccRBI AS_SAS1 V ccS A S 1_5 VccP VccIO VccIO VccIO VccIO Vc c PL L SAS1 V ccS A S 1_5 VSS VSS VSS VccIO VSS VSS GNT3 # /GPIO5 5 ccRB V USBP_10 USBN_10 VSS AD_26 VSS V5REF Vc c ASW Vc c ASW Vc c ASW Vc c SCUS Vc c SCU S Vc c SCUS vc USBP_11 USBN_11 VSS AD_10 vcc3_3 vcc3_3 Vc c ASW Vc c ASW Vc c ASW Vc c SCUS Vc c SCU S Vc c SCUS vc VSS VSS VSS VSS VSS VSS VccIO VccIO VccIO USBP_12 USBN_12 VSS PIRQG# /GPIO4 USBN_3 USBP_13 USBN_13 VSS TACH5 /GPIO6 9 V AD_31 AD_1 TACH2 /GPIO6 AD_6 VSS vccsus3_3 vccsus3_3 Vc c ASW Vc c ASW Vc c ASW vc vccsus3_3 Vc c ASW Vc c ASW Vc c ASW vc V USBP_2 USBP_9 USBN_9 VSS USBRBIASn HDA _S DO HDA_BCLK VSS VSS VSS Vc c ASW VSS VSS U USBP_0 USBN_0 USBN_2 USBP_8 USBN_8 VSS USBRBIASp VSS Vc c AUBG V5RE F_Sus Vc c ASW Vc c ASW Vc c ASW 268 AD_22 PIRQF# /GPIO3 VSS VccIO USBP_4 USBN_4 USBN_5 VSS SAS1RXN SAS0R XN SAS3RXN SAS2RXN USBN_7 USBN_6 SAS3RXP SAS2R XP SAS7RXN SAS6RXN SAS6TXP HDA_ SDIN_ 1 VSS AB AA SAS6TXN SAS7TXN AF REQ 1#/ G PI O 50/ G SXCLK VSS AD_4 AL AK AH AG AD_3 V ccS usHDA Vc c ASW V vc Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCH Ballout Definition Figure 6-3. PCH Ballout (Top View - Upper Right) 20 19 18 17 16 15 14 13 12 11 10 AD_11 C/BE3# VSS PW M0 STO P# PIRQ C# HDA _S Y NC VSS LAD_3 VSS VSS AD_0 LAD_0 AD_5 AD_25 VSS G NT 1 # / G PI O 5 1 / G SXDO UT VSS AD_9 VSS REFCL K1 4 IN AD_7 SAS_ CL OCK2 SAS_ L OAD2 VSS 9 SAS_DATAO UT1 8 7 6 VSS P E G0_RP _3 VSS P E G0_RN_3 VSS SAS_ DAT AIN2 5 4 3 VSS AW PIRQH# /GPIO5 PLOC K# LDRQ 0# IRDY# VSS VSS SERR# AD_2 PERR# AD_12 VSS VSS T ACH1 /GPIO1 C/BE1# G PIO 64 GPIO 66 PW M2 T RDY# SAS_DATAO UT2 S A S _LE D# P E G0_TN_3 P E G0_RP _1 P E G0_TP _2 NC_1 AD_13 P E G0_TP _3 VSS VSS VSS VSS SAS_ L OAD1 VC C XU S TP10 P E G0_RN_0 P E G0_TN_1 P E G0_TN_2 SASSM BCL K2 SASSM BDATA0 VSS SAS_ DAT AIN1 P E G0_TP _1 Vc c PL L SAS0 VSS Vc c PL L SAS0 VSS vc c 3_3 VSS VC C XU S VC C XU S VCCRBIAS_ PU SASSM BCL K0 VSS PERN8 vc c 3_3 VSS VC C XU S VC C XU S SASSM BCL K1 SASSM BDAT A1 VSS PERP7 P E G0_TP _0 VSS VSS SAS_ CL OCK1 PEG0 _ RBIASN PEG0 _ RBIASP G PIO 65 GPIO 67 # VSS AR VC C XU S TP9 AP TP7 CLKI N_SPCI E0N VSS VSS PETN8 VSS PETP8 PET N7 AL AK PETP7 VSS AJ PETN6 PET N5 VSS PERP8 VSS PERN4 PERP4 VSS PERN7 VSS PERN3 PERP3 PETP6 Vc c PL L EXPU VC C XU S VC C XU S VSS PERP6 PERN6 VSS PERN2 PERP2 VSS VSS VSS VSS VSS VSS VC C XU S VccIO VSS PERP5 PERN5 VSS PERP1 PERN1 VC C XU S VC C XU S vccCore vccCore vccCore vccCore vccCore VC C XU S vccCore vccCore vccCore vccCore vccCore VC C XU S VccIO VccIO VSS VccIO VccIO VSS Reserved Reserved VSS VSS VSS VSS VSS VSS VccIO VccIO VSS VccIO VccIO VSS Reserved Reserved VccIO VccIO VccIO VSS vccCore vccCore vccCore vccCore vccCore VccIO VccIO VccIO VSS VSS VSS VccIO VCCAPL L DM I2 VSS CL KIN_ GND0 _ N VSS AF PETP4 PET N3 AE VSS PETP3 VSS AD PETP2 DcpSus DcpSus PETP1 PET N1 Reserved VSS AB AA Reserved Y VSS W Reserved VSS TP2 TP1 VSS VSS VSS VSS VSS VSS VSS vccCore vccCore vccCore vccCore AC PETN2 CL KIN_ GND0 _ P Reserved V DMI_TX N_0 DMI_ZCOMP DM I_ RCOM P VSS Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet DMIRB IA S TP3 VSS DMI_RX P _0 DMI_RX N_0 AH AG PETN4 VSS VSS vccCore vccCore vccCore vccCore vccCore AN AM CLKI N_SPCI E0P PETP5 VccRBI AS_SAS0 AU TP8 AT P E G0_TN_0 VSS VSS SASSM BDAT A2 AV NC_4 P E G0_RP _0 PIRQA# PIRQ D# 1 VSS VSS P E G0_RP _2 P E G0_RN_1 P E G0_RN_2 2 DMI_TX P _0 DMI_TX P _1 DMI_TX N_1 U 269 PCH Ballout Definition Figure 6-4. PCH Ballout (Top View - Lower Left) U USBP_0 USBN_0 USBN_2 T VSS R DSWODVREN RTCRST# VSS M SLP_SUS# L OC5#/GPIO9 W A RN # / S U S P W RD NA CK / G PI O OC2#/GPIO41 VSS SMBDATA G RI# PI O E 1 RTCX1 PCH_PWROK RTCX2 INTRUDER# GPIO27 OC1#/GPIO40 SM L1CLK/ G PI O 58 INTVRMEN VSS CLKIN_DOT96N CLKIN_DOT96P VSS VSS TP6 RSMRST# GPIO8 PWRBTN# OC6#/GPIO10 SST SM L1ALERT#/ G PI O 74 SM BALERT#/ G PI O 11 OC4#/GPIO43 SM L0ALERT#/ G PI O 60 SUSACK# OC0#/GPIO59 WAKE# V5REF_Sus VccASW VccSusHDA VccASW VccASW VccASW vc VccASW VccASW vccsus3_3 VccASW VccASW VccASW vc VSS VSS vccsus3_3 VSS VSS vcc3_3 VccDSW3_3 DcpSus vccSPI VccIO VccIO vcc3_3 DcpRTC VSS VccAUPLL VccIO vccRTC DcpSusByp DcpSST vcc3_3 V VSS TP23 TP24 VSS G PI O 31/ M G PI O 2 OC3#/GPIO42 ADR_CO M PLETE VSS SDATAO UT0/ G PI O 39 DRAMPWROK GPIO57 SLP_LAN#/ G PI O 29 GPIO56 GPIO44 V VSS VSSVccA VccIO VSS Vc SPI_MOSI SATA0G P/ G PI O 21 SPI_MISO SPI_CS1# SATA4G P/ G PI O 16 SATA5G P/ G PI O 49 SMBCLK SML0DATA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SML0CLK GPIO24 APWROK GPIO26 SLP_S3# TP12 SCLO CK/ G PI O 22 GPIO34 SMI#/GPIO20 SATA5RXP SATA4RXP PLTRST# PCIRST# SLP_S4# GPIO15 JTAG_TDI SDATAO UT1/ G PI O 48 GPIO45 BM BUSY#/ G PI O 0 SATA5RXN SATA4RXN INIT3_3V# SYS_RESET# GPIO72 SLP_A# GPIO61 D VSS GPIO46 C JTAG_TMS PME# B A VccAUBG VSS GPIO25 L A N_ P H Y _ P W R _ C T R L / G VSS USBRBIASp VSS OC7#/GPIO14 SM L1DATA/ G PI O 75 J F DPWROK SRTCRST# N H VSS VSS P K USBP_8 USBN_8 SUSCLK/ G PI O 62 NC_2 VSS GPIO73 GPIO47 SLP_S5#/ G PI O 63 JTAG_TCK VSS SYS_PWROK JTAG_TDO GPIO28 SLOAD/GPIO38 VSS VSS SATA3G P/ G PI O 37 GPIO18 RCIN# NM I#/GPIO35 VSS VSS SPKR SATALED# SATA2G P/ G PI O 36 A20GATE VSS SATA1G P/ G PI O 19 VSS SERIRQ VSS GPIO32 SPI_CLK SATA5TXP SATA4TXN VSS SATA5TXN VSS 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 270 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCH Ballout Definition Figure 6-5. PCH Ballout (Top View - Lower Right) DMI_ZCOMP vccCore vccCore vccCore vccCore DcpSus DcpSus vccCore vccCore vccCore vccCore VccIO DMI_RCOMP VccIO VccIO vccsus3_3 VSS DMIRBIAS TP3 VSS DMI_RXP_0 DMI_RXN_0 DMI_TXP_0 DMI_TXP_1 DMI_TXN_1 U VSS VSS Vcc3_3 VSS DMI_RXN_1 DMI_RXP_1 VSS VSS T DMI_TXP_2 DMI_TXN_2 DMI_TXN_3 R VSS VSS VSS VSS VSS VSS VccIO VccIO VSS VccAPLLSATA VccIO VccDFTERM VSS VSS VSS VccVRM VccIO VccDFTERM VccVRM VccDFTERM VccDFTERM SPI_CS0# SATAICOMPI TP21 SATAICOMPO NC_10 NC_21 vccCore vccCore V_PROC_IO SATA3COMPO TP4 VSS TP5 VccDMI vccCore Reserved Reserved Reserved Reserved Reserved Reserved VSS TS_VSS2 TS_VSS4 SATA4TXP SATA3TXN VSS VSS VSS VSS SATA3RXP SATA2RXP SATA1RXP SATA0RXP SATA3RXN SATA2RXN SATA1RXN SATA0RXN VSS SATA2TXP VSS SATA3TXP SATA2TXN CLKIN_SATA_N TP22 VSS CLKIN_SATA_P VSS TP20 VSS VSS Reserved VSS Reserved SATA3RRBIAS SATA1TXP VSS SATA0TXN NC_20 NC_9 Reserved PROCPWRGD Reserved Reserved DMI_RXP_2 DMI_RXN_2 DMI_TXP_3 P VSS DMI_RXN_3 DMI_RXP_3 VSS VSS VSS N VSS CLKIN_DMI_N M VSS L NC_24 NC_5 NC_14 K NC_15 J VSS NC_12 NC_16 Reserved Reserved THRMTRIPB PM_SYNC Reserved VSS VSS CLKIN_DMI_P PM_SYNC2 VSS VSS NC_18 VSS NC_19 NC_8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PECI NC_11 NC_7 Reserved VSS VSS 20 19 18 17 16 15 14 13 12 11 10 9 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet VSS VSS Reserved TP19 VSS SATA1TXN SATA0TXP VSS NC_6 NC_17 VSS VSS TS_VSS1 TS_VSS3 SATA3COMPI VSS VccAPLLEXP VSS DF_TVS VSS Reserved Reserved VSS Reserved VSS 8 7 6 Reserved VSS H NC_22 G VSS F E NC_13 VSS D NC_23 VSS C Reserved B A CHIP_DETECT# VSS VSS 5 4 3 2 1 271 PCH Ballout Definition Table 6-1. PCH Ballout by Signal Name (Sheet 1 of 25) PCH Ball Name Ball # Table 6-1. PCH Ballout by Signal Name (Sheet 2 of 25) PCH Ball Name Ball # Table 6-1. PCH Ballout by Signal Name (Sheet 3 of 25) PCH Ball Name Ball # C/BE0# AM31 DMI_TXN_0 V2 B26 C/BE1# AL18 DMI_TXN_1 U1 AD0 AW15 C/BE2# AL33 DMI_TXN_2 R2 AD1 AA30 C/BE3# AU20 DMI_TXN_3 R1 AD10 AC32 CHIP_DETECT# B2 DMI_TXP_0 U3 AD11 AW20 CLKIN_DMI_N M1 DMI_TXP_1 U2 AD12 AM18 CLKIN_DMI_P M2 DMI_TXP_2 R3 AD13 AP12 CLKIN_DOT_96N R32 DMI_TXP_3 P2 AD14 AL31 CLKIN_DOT_96P R31 DMI_ZCOMP U13 AD15 AM30 CLKIN_GND0_N Y5 DMIRBIAS AD16 AM25 CLKIN_GND0_P Y4 DPWROK R37 AD17 AU22 CLKIN_PCI AK22 DRAMPWROK J28 AD18 AG30 CLKIN_SAS0_N AU28 DSWODVREN R39 AD19 AG32 CLKIN_SAS0_P AV27 FRAME# AF31 AD2 AN15 CLKIN_SAS1_N AV33 GNT0# AN33 AD20 AN34 CLKIN_SAS1_P AW33 AK33 CLKIN_SATA_N B17 GNT1# / GPIO51 / GSXDOUT AU15 AD21 AD22 AL21 CLKIN_SATA_P A17 AJ34 AD23 AK27 GNT2# / GPIO53 / GSXDIN CLKIN_SPCIE0_N AN1 AD24 AM24 GNT3# / GPIO55 AF30 CLKIN_SPCIE0_P AM2 AD25 AV13 GPIO13 AV24 DcpRTC M28 AD26 AD32 GPIO15 E30 DcpSST L25 AD27 AL34 GPIO18 B29 DcpSus U15 AD28 AR33 GPIO24 F34 DcpSus U16 AD29 AG31 GPIO25 J38 DcpSus N26 AD3 AR36 GPIO26 F31 DcpSusByp L26 AD30 AL30 GPIO27 M35 DEVSEL# AJ32 AD31 AA31 GPIO28 A33 DF_TVS C7 AD4 AP36 GPIO31/MGPIO2 K33 DMI_IRCOMP U12 AD5 AV14 GPIO32 B24 DMI_RXN_0 U5 AD6 Y30 GPIO33 AT37 DMI_RXN_1 T6 AD7 AU12 GPIO34 F25 DMI_RXN_2 P4 AD8 AU25 GPIO44 J25 DMI_RXN_3 N5 AD9 AW12 GPIO45 E25 DMI_RXP_0 U6 ADR_COMPLETE H37 GPIO46 D37 DMI_RXP_1 T5 APWROK F33 GPIO47 B32 DMI_RXP_2 P5 BMBUSY#/ GPIO0 E24 GPIO56 H27 DMI_RXP_3 N4 A20GATE 272 U9 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCH Ballout Definition Table 6-1. PCH Ballout by Signal Name (Sheet 4 of 25) PCH Ball Name Ball # GPIO57 J27 GPIO64 AL16 GPIO65 GPIO66 Table 6-1. PCH Ballout by Signal Name (Sheet 5 of 25) PCH Ball Name PCH Ball Name Ball # B31 PEG0_RN1 AV5 NC_5 K2 PEG0_RN2 AU7 AK16 NC_6 N9 PEG0_RN3 AV8 AL15 NC_7 E2 PEG0_RP0 AT3 GPIO67 AK15 NC_8 F2 PEG0_RP1 AU5 GPIO72 E38 NC_9 L8 PEG0_RP2 AV6 GPIO73 B33 NC_10 N12 PEG0_RP3 AW7 GPIO8 F38 NC_11 E3 PEG0_TN0 AP3 HDA_BCLK V29 NC_12 L6 PEG0_TN1 AR4 HDA_RST# AW22 NC_13 D3 PEG0_TN2 AP6 HDA_SDIN0 AH37 NC_14 K1 PEG0_TN3 AR7 HDA_SDIN1 AG38 NC_15 J2 PEG0_TP0 AN3 HDA_SDIN2 AH39 NC_16 L5 PEG0_TP1 AN4 HDA_SDIN3 AH38 NC_17 N8 PEG0_TP2 AR6 HDA_SDO V30 NC_18 G3 PEG0_TP3 AP7 HDA_SYNC AV17 NC_19 H2 PERn1 AE4 INIT3_3V# C31 NC_20 L9 PERn2 AF5 INTRUDER# P34 NC_21 N11 PERn3 AH6 INTVRMEN M34 NC_22 G1 PERn4 AJ6 IRDY# AP18 NC_23 C3 PERn5 AE8 JTAG_TCK A37 NC_24 K3 PERn6 AF8 JTAG_TDI E28 OC0# / GPIO59 K34 PERn7 AH8 JTAG_TDO A34 OC1# / GPIO40 M37 PERn8 AJ9 JTAG_TMS C39 OC2# / GPIO41 M38 PERp1 AE5 LAD0 AV15 OC3# / GPIO42 K36 PERp2 AF4 LAD1 AV23 OC4# / GPIO43 J30 PERp3 AH5 LAD2 AL36 OC5# / GPIO9 L39 PERp4 AJ5 LAD3 AU17 OC6# / GPIO10 K30 PERp5 AE9 F39 OC7# / GPIO14 K38 PERp6 AF9 AK28 PERp7 AH9 PCH_PWROK R34 PERp8 AJ8 PCIRST# E33 PERR# AM19 E4 PETn1 AB1 AL5 PETn2 AC2 PEG0_RBIASP AL4 PETn3 AE1 PEG0_RN0 AU3 PETn4 AF2 LAN_PHY_PWR_CT RL / GPIO12 NMI#/GPIO35 Ball # Table 6-1. PCH Ballout by Signal Name (Sheet 6 of 25) PAR LDRQ0# AP19 LDRQ1# / GPIO23 AR37 LFRAME# AF36 NC_1 AP13 NC_2 B38 NC_3 AV38 NC_4 AV2 PECI PEG0_RBIASN Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 273 PCH Ballout Definition Table 6-1. PCH Ballout by Signal Name (Sheet 7 of 25) PCH Ball Name Table 6-1. PCH Ballout by Signal Name (Sheet 8 of 25) Ball # PCH Ball Name Ball # PETn5 AH1 AH2 REQ2# / GPIO52 / GSXSLOAD AK34 PETn6 REQ3# / GPIO54 / GSXSRESET# AK21 PETn7 AK1 PETn8 AL2 PETp1 AB2 PETp2 AB3 PETp3 AD2 PETp4 AE3 PETp5 AG2 PETp6 AH3 PETp7 AJ2 PETp8 AK3 PIRQA# AR19 PIRQB# AJ30 PIRQC# AV18 PIRQD# AR18 PIRQE# / GPIO2 AF32 PIRQF# / GPIO3 AL22 PIRQG# / GPIO4 AA32 PIRQH# / GPIO5 AR16 PLOCK# AR15 PLTRST# E34 PM_SYNC J6 PM_SYNC2 H4 PME# PROCPWRGD C37 J9 PWM0 AW17 PWM1 AV22 PWM2 AR13 PWM3 AG36 PWRBTN# K31 RCIN# B28 REFCLK14IN AV12 REQ0# AL27 REQ1# / GPIO50 / GSXCLK AR34 274 Reserved A7 Reserved AA2 Reserved AB5 Reserved AB6 Reserved AC5 Reserved AC6 Reserved B5 Reserved B6 Reserved B8 Reserved C10 Reserved C5 Reserved E10 Reserved E6 Reserved E7 Reserved E9 Reserved F10 Reserved F12 Reserved F13 Reserved F4 Reserved F6 Reserved F7 Reserved F9 Reserved H10 Reserved H9 Reserved J10 Reserved J12 Reserved J13 Reserved J4 Reserved K12 Reserved K13 Reserved K6 Reserved K7 Reserved L12 Table 6-1. PCH Ballout by Signal Name (Sheet 9 of 25) PCH Ball Name Ball # Reserved L13 Reserved W2 Reserved Y1 Reserved Y3 RI# G39 RSMRST# M30 RTCRST# R38 RTCX1 R36 RTCX2 P36 SAS0RXN AR21 SAS1RXN AR22 SAS2RXN AP24 SAS3RXN AP25 SAS4RXN AN27 SAS5RXN AN28 SAS6RXN AP30 SAS7RXN AP31 SAS0RXP AN21 SAS1RXP AN22 SAS2RXP AR24 SAS3RXP AR25 SAS4RXP AR27 SAS5RXP AR28 SAS6RXP AR30 SAS7RXP AR31 SAS0TXN AW28 SAS1TXN AV29 SAS2TXN AW30 SAS3TXN AV32 SAS4TXN AN38 SAS5TXN AN39 SAS6TXN AL38 SAS7TXN AK39 SAS0TXP AV28 SAS1TXP AU30 SAS2TXP AV31 SAS3TXP AU33 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCH Ballout Definition Table 6-1. PCH Ballout by Signal Name (Sheet 10 of 25) PCH Ball Name Ball # Table 6-1. PCH Ballout by Signal Name (Sheet 11 of 25) PCH Ball Name Ball # Table 6-1. PCH Ballout by Signal Name (Sheet 12 of 25) PCH Ball Name Ball # SAS4TXP AN37 SATA1TXN B13 SLP_SUS# M39 SAS5TXP AM38 SATA2TXN B18 J31 SAS6TXP AK37 SATA3TXN A20 SMBALERT# / GPIO11 SAS7TXP AJ38 SATA4TXN B21 SMBCLK G37 SAS_CLOCK1 AL8 SATA5TXN A22 SMBDATA H38 AN10 SATA0TXP B12 SAS_LOAD1 SAS_DATAIN1 AL9 SATA1TXP C12 SAS_DATAOUT1 AV9 SATA2TXP C17 SAS_CLOCK2 AW10 SATA3TXP B19 SAS_LOAD2 AV10 SATA4TXP C20 SAS_DATAIN2 AU10 SATA5TXP SAS_DATAOUT2 AR10 SMI# / GPIO20 F24 SML0ALERT# / GPIO60 H34 SML0CLK F36 SML0DATA G36 SML1ALERT# / GPIO74 J33 B22 SATA0GP / GPIO21 J24 SML1CLK / GPIO58 K37 AR9 SATA1GP / GPIO19 A25 K39 SAS_RBIASN0 AW25 SATA2GP / GPIO36 C25 SML1DATA / GPIO75 SAS_RBIASN1 AL24 SATA3GP / GPIO37 C28 SPI_CLK B23 SAS_RBIASP0 AV26 SATA4GP / GPIO16 H22 SPI_CS0# K19 SAS_RBIASP1 AL25 H21 SPI_CS1# J21 SASSMBCLK0 AJ12 SATA5GP / GPIO49 / TEMP_ALERT# SPI_MISO J22 SATAICOMPI K18 SPI_MOSI K24 SATAICOMPO J18 SPKR A28 SATALED# B27 SRTCRST# P38 SCLOCK / GPIO22 F27 SST SDATAOUT0 / GPIO39 K25 STOP# AV19 SUSACK# H33 E27 SUSWARN# / GPIO30 N38 GPIO61 E36 SUSCLK / GPIO62 C35 SAS_LED# SASSMBCLK1 AH13 SASSMBCLK2 AL13 SASSMBDATA0 AL11 SASSMBDATA1 AH12 SASSMBDATA2 AM13 SATA0RXN E15 SATA1RXN E16 SDATAOUT1 / GPIO48 SATA2RXN E18 SATA3RBIAS B14 SATA3RXN E19 SATA3COMPI C15 SATA4RXN E21 SATA3COMPO J16 SATA5RXN E22 SERIRQ C22 SATA0RXP F15 SERR# AN16 SATA1RXP F16 SLOAD / GPIO38 A30 SATA2RXP F18 SLP_A# E37 SATA3RXP F19 H28 SATA4RXP F21 SLP_LAN# / GPIO29 SATA5RXP F22 SLP_S3# F30 SATA0TXN A12 SLP_S4# E31 SLP_S5# / GPIO63 B35 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet J34 SYS_PWROK C33 SYS_RESET# C30 TACH0 / GPIO17 AV21 TACH1 / GPIO1 AL19 TACH2 / GPIO6 Y31 TACH3 / GPIO7 AJ35 TACH4 / GPIO68 AG34 TACH5 / GPIO69 Y32 TACH6 / GPIO70 AF34 275 PCH Ballout Definition Table 6-1. PCH Ballout by Signal Name (Sheet 13 of 25) PCH Ball Name Ball # TACH7 / GPIO71 Table 6-1. PCH Ballout by Signal Name (Sheet 14 of 25) PCH Ball Name Ball # Table 6-1. PCH Ballout by Signal Name (Sheet 15 of 25) PCH Ball Name Ball # AM36 USBP12N AA34 VccCore AD18 THRMTRIP# J7 USBP12P AA36 VccCore AD17 TP1 W4 USBP13N Y34 VccCore AD16 TP10 AU1 USBP13P Y36 VccCore AC20 TP11 AL28 USBP1N W38 VccCore AC19 TP12 F28 USBP1P Y39 VccCore AC18 TP13 AU37 USBP2N U37 VccCore AC17 TP14 AU39 USBP2P V38 VccCore AC16 TP15 AV35 USBP3N Y37 VccCore Y20 TP16 AT39 USBP3P AA38 VccCore Y19 TP17 AU35 USBP4N AB38 VccCore Y18 TP18 AR38 USBP4P AB39 VccCore Y17 TP19 B10 USBP5N AB37 VccCore Y16 TP2 W5 USBP5P AC38 VccCore W20 TP20 A15 USBP6N AD38 VccCore W19 TP21 J19 USBP6P AE39 VccCore W18 TP22 B15 USBP7N AE37 VccCore W17 TP23 P32 USBP7P AF38 VccCore W16 TP24 P31 USBP8N U34 VccCore U20 TP3 U8 USBP8P U35 VccCore U19 TP4 P11 USBP9N V34 VccCore U18 TP5 P9 USBP9P V35 VccCore U17 TP6 M32 USBRBIAS U32 VccCore T20 TP7 AN2 USBRBIAS# V32 VccCore T19 TP8 AT1 V_PROC_IO TP9 AP1 V5REF TRDY# AR12 L16 VccCore T18 AD29 VccCore T17 V5REF_Sus U28 VccCore N16 R22 VccCore N15 TS_VSS1 E13 Vcc3_3 TS_VSS2 H16 Vcc3_3 N22 VccCore J15 TS_VSS3 E12 Vcc3_3 AJ18 VccDFTERM N18 TS_VSS4 H15 Vcc3_3 AH18 VccDFTERM N17 USBP0N U38 Vcc3_3 AC30 VccDFTERM M18 USBP0P U39 Vcc3_3 AC29 VccDFTERM L18 USBP10N AD34 Vcc3_3 T8 VccDMI L15 USBP10P AD35 Vcc3_3 L24 VccDSW3_3 N28 USBP11N AC34 VccCore AD20 VccIO AE11 USBP11P AC35 VccCore AD19 VccIO AC13 276 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCH Ballout Definition Table 6-1. PCH Ballout by Signal Name (Sheet 16 of 25) PCH Ball Name Ball # Table 6-1. PCH Ballout by Signal Name (Sheet 17 of 25) PCH Ball Name Ball # Table 6-1. PCH Ballout by Signal Name (Sheet 18 of 25) PCH Ball Name Ball # VccIO AC12 VccIO AH26 VccASW W24 VccIO AC9 VccIO AH25 VccASW W23 VccIO AC8 VccIO AF28 VccASW W22 VccIO AB13 VccIO AF26 VccASW V24 VccIO AB12 VccIO AF25 VccASW U24 VccIO AB9 VccIO AF24 VccASW U23 VccIO AB8 VccIO AE24 VccASW U22 VccIO Y15 VccSCUS AC22 VccASW T24 VccIO Y12 VccSCUS AC23 VccASW T23 VccIO Y11 VccSCUS AC24 VccASW T22 VccIO Y9 VccSCUS AD22 VccASW U26 VccIO W15 VccSCUS AD23 VccASW T28 VccIO W12 VccSCUS AD24 VccASW T26 VccIO W11 VccXUS VccIO T13 VccIO T12 VccIO AR2 VccAPLLDMI2 VccXUS AN9 VccAPLLEXP VccRBIAS_PU AJ13 VccAPLLSATA M20 T16 VccXUS AJ16 VccPLLSAS0 AJ20 VccIO P12 VccXUS AJ15 VccPLLSAS0 AH20 VccIO N24 VccXUS AH16 VccPLLSAS1 AF23 VccIO N23 VccXUS AH15 VccPLLEXPU AF15 VccIO M24 VccXUS AF17 VccRTC L28 VccIO L23 VccXUS AF16 VccSAS1_5 AJ22 VccIO Y28 VccXUS AF12 VccSAS1_5 AH22 VccIO Y26 VccXUS AF11 VccSAS1_5 AF22 VccIO Y25 VccXUS AC15 VccSPI N25 VccIO N20 VccXUS AD15 VccSus3_3 T25 VccIO M19 VccXUS AE12 VccSus3_3 R25 VccIO L19 VccASW AD28 VccSus3_3 W28 VccAUPLL M25 VccASW AD26 VccSus3_3 W26 VccRBIAS_SAS0 AF20 VccASW AD25 VccSus3_3 W25 VccRBIAS_SAS1 AJ23 VccASW AC28 VccAUBG U29 VccRBIAS_SAS1 AH23 VccASW AC26 VccSus3_3 T15 VccIO AJ28 VccASW AC25 VccSusHDA U25 VccIO AJ26 VccASW Y24 VccVRM L17 VccIO AJ25 VccASW Y23 VccVRM L20 VccIO AH28 VccASW Y22 Vss (0) AW37 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Y8 P8 277 PCH Ballout Definition Table 6-1. PCH Ballout by Signal Name (Sheet 19 of 25) PCH Ball Name Ball # Table 6-1. PCH Ballout by Signal Name (Sheet 20 of 25) PCH Ball Name Ball # Table 6-1. PCH Ballout by Signal Name (Sheet 21 of 25) PCH Ball Name Ball # Vss AW36 Vss AN13 Vss AG33 Vss AW34 Vss AN12 Vss AF39 Vss AW31 Vss (40) AN7 Vss AF37 Vss AW29 Vss AN6 Vss AF33 Vss AW26 Vss AM34 Vss AF19 Vss AW24 Vss AM33 Vss (80) AF18 Vss AW21 Vss AM28 Vss AF10 Vss AW19 Vss AM27 Vss AF6 Vss AW16 Vss AM22 Vss AF3 Vss (10) AW13 Vss AM21 Vss AF1 Vss AW11 Vss AM16 Vss AE28 Vss AW8 Vss AM15 Vss AE26 Vss AW6 Vss (50) AM10 Vss AE25 Vss AW4 Vss AM9 Vss AE23 Vss AW3 Vss AM4 Vss AE22 Vss AU34 Vss AL39 Vss (90) AE20 Vss AU31 Vss AL37 Vss AE19 Vss AU29 Vss AL10 Vss AE18 Vss AU26 Vss AL6 Vss AE17 Vss (20) AU24 Vss AL3 Vss AE16 Vss AU21 Vss AL1 Vss AE15 Vss AU19 Vss AJ39 Vss AE10 Vss AU16 Vss (60) AJ37 Vss AE6 Vss AU13 Vss AJ33 Vss AD39 Vss AU11 Vss AJ29 Vss AD37 Vss AU8 Vss AJ24 Vss (100) AD33 Vss AU6 Vss AJ19 Vss AD30 Vss AR3 Vss AJ17 Vss AD3 Vss AP39 Vss AJ11 Vss AD1 Vss (30) AP37 Vss AJ7 Vss AC33 Vss AN36 Vss AJ3 Vss AC11 Vss AN31 Vss AJ1 Vss AC7 Vss AN30 Vss (70) AH24 Vss AB28 Vss AN25 Vss AH19 Vss AB26 Vss AN24 Vss AH17 Vss AB25 Vss AN19 Vss AH11 Vss (110) AB24 Vss AN18 Vss AH7 Vss AB23 278 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCH Ballout Definition Table 6-1. PCH Ballout by Signal Name (Sheet 22 of 25) PCH Ball Name Ball # Table 6-1. PCH Ballout by Signal Name (Sheet 23 of 25) PCH Ball Name Ball # Table 6-1. PCH Ballout by Signal Name (Sheet 24 of 25) PCH Ball Name Ball # Vss AB22 Vss U11 Vss M16 Vss AB20 Vss U7 Vss M15 Vss AB19 Vss (150) T39 Vss L37 Vss AB18 Vss T37 Vss L22 Vss AB17 Vss T11 Vss L11 Vss AB16 Vss T7 Vss L7 Vss AB15 Vss T3 Vss (190) L3 Vss AB11 Vss T1 Vss L1 AB7 Vss R33 Vss H39 Vss AA39 Vss R30 Vss H3 Vss AA37 Vss R28 Vss H1 Vss AA33 Vss R26 Vss G34 Vss AA3 Vss (160) R24 Vss G33 Vss AA1 Vss R23 Vss G31 Vss Y33 Vss R20 Vss G30 Vss Y10 Vss R19 Vss G28 Vss Y6 Vss R18 Vss (200) G27 Vss W39 Vss R17 Vss G25 Vss (130) W37 Vss R16 Vss G24 Vss W10 Vss R15 Vss G22 Vss W6 Vss P33 Vss G21 Vss W3 Vss P30 Vss G19 Vss W1 Vss (170) P10 Vss G18 Vss V33 Vss P6 Vss G16 Vss V28 Vss N39 Vss G15 Vss V26 Vss N37 Vss G13 Vss V25 Vss N19 Vss (210) G12 Vss V23 Vss N10 Vss G10 Vss (140) V22 Vss N6 Vss G9 Vss V20 Vss N3 Vss G7 Vss V19 Vss N1 Vss G6 Vss V18 Vss M33 Vss G4 Vss V17 Vss (180) M29 Vss F37 Vss V16 Vss M26 Vss F3 Vss V15 Vss M22 Vss F1 Vss U33 Vss M17 Vss D39 Vss (120) Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 279 PCH Ballout Definition Table 6-1. PCH Ballout by Signal Name (Sheet 25 of 25) PCH Ball Name Ball # Vss (220) D1 Vss C34 Vss C29 Vss C26 Vss C24 Vss C21 Vss C19 Vss C16 Vss C13 Vss C11 Vss (230) C8 Vss C1 Vss A36 Vss A31 Vss A29 Vss A26 Vss A24 Vss A21 Vss A19 Vss (240) A16 Vss A13 Vss A11 Vss A8 Vss A6 Vss A4 Vss A3 Vss T9 Vss U30 Vss M23 Vss (250) W9 Vss W8 Vss N2 Vss M3 Vss B9 Vss A10 WAKE# J36 280 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Package Information 7 Package Information Refer to the Intel(R) C600 Series Chipset Thermal and Mechanical Design Guidelines or Intel(R) X79 Express Chipset Thermal and Mechanical Design Guidelines document for PCH package information. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 281 Package Information 282 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Electrical Characteristics 8 Electrical Characteristics This chapter contains the DC and AC characteristics for the PCH. AC timing diagrams are included. 8.1 Thermal Specifications Refer to the Intel(R) C600 Series Chipset Thermal and Mechanical Design Guidelines or Intel(R) X79 Express Chipset Thermal and Mechanical Design Guidelines document for PCH package information. 8.2 Absolute Maximum Ratings Table 8-1. PCH Absolute Maximum Ratings Parameter Maximum Limits Voltage on any 5 V Tolerant Pin with respect to Ground (V5REF = 5 V) -0.5 to V5REF + 0.5 V Voltage on any 3.3 V Pin with respect to Ground -0.5 to Vcc3_3 + 0.4 V Voltage on any 1.8 V Tolerant Pin with respect to Ground -0.5 to VccVRM + 0.5 V Voltage on any 1.5 V Pin with respect to Ground -0.5 to VccVRM + 0.5 V Voltage on any 1.1 V Tolerant Pin with respect to Ground -0.5 to VccIO + 0.5 V 1.1 V Supply Voltage with respect to VSS -0.5 to 1.3 V 1.8 V Supply Voltage with respect to VSS -0.5 to 1.98 V 3.3 V Supply Voltage with respect to VSS -0.5 to 3.7 V 5.0 V Supply Voltage with respect to VSS -0.5 to 5.5 V V_PROC_IO Supply Voltage with respect to VSS -0.5 to 1.3 V 1.1 V Supply Voltage for the analog PLL with respect to VSS -0.5 to 1.3 V 1.5 V Supply Voltage for the analog PLL with respect to VSS -0.5 to 1.65 V 1.8 V Supply Voltage for the analog PLL with respect to VSS -0.5 to 1.98 V Table 8-1 specifies absolute maximum and minimum ratings. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits (but within the absolute maximum and minimum ratings) the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits. At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time, it will either not function or its reliability will be severely degraded when returned to conditions within the functional operating condition limits. Although the PCH contains protective circuitry to resist damage from Electrostatic Discharge (ESD), precautions should always be taken to avoid high static voltages or electric fields. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 283 Electrical Characteristics 8.3 PCH Power Supply Range Table 8-2. PCH Power Supply Range Power Supply 1.0 V 1.05 V 1.1 V 8.4 Minimum Nominal Maximum 0.95 V 1.00 V 1.05 V 0.998 V 1.05 V 1.10 V 1.05 V 1.10 V 1.16 V 1.5 V 1.43 V 1.50 V 1.58 V 1.8 V 1.71 V 1.80 V 1.89 V 3.3 V 3.14 V 3.30 V 3.47 V 5V 4.75 V 5.00 V 5.25 V General DC Characteristics ICC values in Table 8-3 and Table 8-4 specifications have been validated using postsilicon measurements. These values are provided primarily for sizing platform VR solutions. Table 8-3. Voltage Rail V5REF V5REF_Sus Power Supply ICC Specifications by Domain (Intel(R) C602, C602J, C604 Chipset and Intel(R) X79 Express Chipset SKUs) Voltage (V) S0 Iccmax Current3 (A) TDC MAX4 (A) TDC Typical5 (A) Sx Iccmax Current3 (A) Sx Idle Current6 (A) G3 5 1 (mA) 1 (mA) 1 (mA) - - - 5 1 (mA) 1 (mA) 1 (mA) < 1 (mA) < 1 (mA) - Vcc3_3 3.3 0.17 0.02 0.02 - - - VccSus3_3 3.3 0.08 0.04 0.03 0.15 0.05 - Vcc1 1.1 7.95 5.55 4.05 - - - VccASW 1.1 1.5 1.0 0.5 0.8 0.4 - VccDSW 3.3 0.002 < 1 (mA) < 1 (mA) < 1 (mA) < 1 (mA) - VccSAS 1.5 0.15 0.13 0.13 - - - VccVRM2 1.5 0.2 0.12 0.11 - - - - - - V_PROC_IO 1.0 - 1.1 1(mA) 1(mA) 1(mA) VccDMI 1.0 - 1.1 0.057 0.057 0.045 VccRTC - - - - - - 6 uA 7,8 Notes: 1. Vcc includes VccIO, VccCORE, and so forth, that are in the 1.1 V core well and typically supplied by a common VR source. 2. VccVRM can optionally be used in 1.8 V mode. 3. Iccmax currents define the operational maximums which must be provided by platform power delivery VR and traces (activity on worst-case 3-sigma manufacturing units). 4. TDC currents represent steady-state consumption, by supply rail, for Full Feature TDP specifications. (Max) defines platform thermal solution necessary to support 3-sigma manufacturing variance, 5. TDC (Typ) is representative consumption of volume units at Full-Feature TDP configuration. 6. Sx Idle current is representative consumption of volume units at full idle (including Intel ME) 7. G3 state shown to provide an estimate of battery life 8. Icc (RTC) data is taken with VccRTC at 3.0 V while the system in a mechanical off (G3) state at room temperature. 284 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Electrical Characteristics Table 8-4. Voltage Rail V5REF V5REF_Sus Vcc3_3 Power Supply ICC Specifications by Domain (Intel(R) C606, C608 Chipset SKUs) Voltage S0 Iccmax Current3 (A) TDC MAX4 (A) TDC Typical5 (A) Sx Iccmax Current3 (A) Sx Idle Current6 (A) G3 5 1 (mA) 1 (mA) 1 (mA) - - - 5 1 (mA) 1 (mA) 1 (mA) < 1 (mA) < 1 (mA) - 3.3 0.17 0.02 0.02 - - - VccSus3_3 3.3 0.08 0.04 0.03 0.15 0.05 - Vcc1 1.1 11.55 8.7 6.7 - - - VccASW 1.1 1.5 1.0 0.46 0.8 0.4 - VccDSW 3.3 0.002 < 1 (mA) < 1 (mA) < 1 (mA) < 1 (mA) - VccSAS 1.5 0.28 0.26 0.26 - - - VccVRM2 1.5 0.16 0.12 0.11 - - - - - - V_PROC_IO 1.0 - 1.1 1(mA) 1(mA) 1(mA) VccDMI 1.0 - 1.1 0.057 0.057 0.045 VccRTC - - - - - - 6 uA 7,8 Notes: 1. Vcc includes VccIO, VccCORE, and so forth, that are in the 1.1 V core well & typically supplied by a common VR source. 2. VccVRM can optionally be used in 1.8 V mode. 3. Iccmax currents define the operational maximums which must be provided by platform power delivery VR and traces (peak activity on worst-case 3-sigma manufacturing units). 4. TDC currents represent steady-state consumption, by supply rail, for Full Feature TDP specifications. (Max) defines platform thermal solution necessary to support 3-sigma manufacturing variance, 5. TDC (Typ) is representative consumption of volume units at Full-Feature TDP configuration. 6. Sx Idle current is representative consumption of volume units at full idle (includes Intel Management Engine) 7. G3 state shown to provide an estimate of battery life 8. Icc (RTC) data is taken with VccRTC at 3.0 V while the system in a mechanical off (G3) state at room temperature. Table 8-5. DC Characteristic Input Signal Association (Sheet 1 of 3) Symbol VIH1/VIL1 (5 V Tolerant) VIMIN2-Gen3i/ VIMAX2-Gen3i Associated Signals PCI Signals: AD[31:0], C/BE[3:0]#, DEVSEL#, FRAME#, IRDY#, PAR, PERR#, PLOCK#, REQ[3:0]#, SERR#, STOP#, TRDY# Interrupt Signals: PIRQ[D:A]#, PIRQ[H:E]# GPIO Signals: GPIO[54, 52, 50, 5:2] GSX Signals:GSXDIN SATA Signals: SATA[1:0]RX[P,N] (6.0 Gb/s internal SATA) VIH3/VIL3 Clock Signals: REFCLK14IN Power Management Signals: PWRBTN#, RI#, SYS_RESET#, WAKE#, SUSACK#. GPIO Signals: GPIO[71:68, 63:61, 57, 48, 39, 38, 34, 32, 31, 30, 29, 24, 22, 17, 7, 6, 1] Thermal/Fan Control Signals: TACH[7:0] VIH4/VIL4 Clock Signals: CLKIN_PCI Processor Signals:A20GATE PCI Signals: PME# Interrupt Signals: SERIRQ SATA Signals: SATA[5:0]GP SPI Signals: SPI_MISO Strap Signals: SPKR, GNT[3:1]#, (Strap purposes only) LPC Signals: LAD[3:0], LDRQ0#, LDRQ1#, GPIO Signals: GPIO[73, 72, 67:64, 59, 56, 55, 53, 51, 49, 47:40, 37, 36, 35, 33, 28, 27, 26, 25, 23, 21, 20, 19, 18, 16, 15, 14, 12, 10, 9, 8, 0] USB Signals: OC[7:0]# Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 285 Electrical Characteristics Table 8-5. DC Characteristic Input Signal Association (Sheet 2 of 3) Symbol Associated Signals VIH5/VIL5 SMBus Signals: SMBCLK, SMBDATA, SMBALERT# SAS SMBus Signals (SRV/WS SKUs Only): SASSMBCLK0, SASSMBDATA0, SASSMBCLK1, SASSMBDATA1, SASSMBCLK2, SASSMBDATA2, System Management Signals: SML[1:0]CLK, SML[1:0]DATA GPIO Signals: GPIO[75, 74, 60, 58, 11] VIH6/VIL6 JTAG Signals: JTAG_TDI, JTAG_TMS, JTAG_TCK VIH7/VIL7 Processor Signals: THRMTRIP# VIMIN8Gen1/ VIMAX8Gen1, VIMIN8Gen2/ VIMAX8Gen2, VIH9/VIL9 PCI Express* Data RX Signals: PER[p,n][8:1] (2.5 GT/s and 5.0 GT/s) Real Time Clock Signals: RTCX1 VIMIN10 -Gen1i/ VIMAX10-Gen1i SATA Signals: SATA[5:0]RX[P,N] (1.5 Gb/s internal SATA) VIMIN10 -Gen1m/ VIMAX10-Gen1m SATA Signals: SATA[5:0]RX[P,N] (1.5 Gb/s external SATA) VIMIN10 -Gen2i/ VIMAX10-Gen2i SATA Signals: SATA[5:0]RX[P,N] (3.0 Gb/s internal SATA) VIMIN10 -Gen2m/ VIMAX10-Gen2m SATA Signals: SATA[5:0]RX[P,N] (3.0 Gb/s external SATA) VIH11/VIL11 Intel(R) High Definition Audio Signals: HDA_SDIN[3:0] (3.3V Mode) Strap Signals: HDA_SDOUT, HDA_SYNC (Strap purposes only) GPIO Signals: GPIO13 Note: VIH12 (Absolute Maximum) / VIL12 (Absolute Minimum) / Vclk_in_cross(abs) Clock Signals: CLKIN_DMI_[P,N], CLKIN_DOT96[P,N], CLKIN_SATA_[P,N] VIH13/VIL13 Miscellaneous Signals: RTCRST# VIH14/VIL14 Power Management Signals: PCH_PWROK, RSMRST#, DPWROK System Management Signals: INTRUDER# Miscellaneous Signals: INTVRMEN, SRTCRST# VIH15/VIL15 Processor Interface: RCIN# Power management Signals: SYS_PWROK, APWROK VIMIN16/VIMAX16 (SRV/WS SKUs Only) SAS Signals: SAS[7:0]RX[P,N] (1.5 Gb/s) VIMIN17/VIMAX17 (SRV/WS SKUs Only) SAS Signals: SAS[7:0]RX[P,N] (3.0 Gb/s) VIMIN18/VIMAX18 (Intel(R) C606, C608 Chipset SKUs Only) PCI Express* Uplink RX Signals: PEG0_R[p,n][3:0] VDI / VCM / VSE (5V Tolerant) VHSSQ / VHSDSC / VHSCM (5 V Tolerant) 286 See VIL_HDA/VIH_HDA for High Definition Audio Low Voltage Mode USB Signals: USBP[13:0][P,N] (Low-speed and Full-speed) USB Signals: USBP[13:0][P,N] (in High-speed Mode) Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Electrical Characteristics Table 8-5. DC Characteristic Input Signal Association (Sheet 3 of 3) Symbol Associated Signals VIH_HDA / VIL_HDA Table 8-6. Symbol Intel High Definition Audio Signals: HDA_SDIN[3:0] Strap Signals: HDA_SDOUT, HDA_SYNC (Strap purposes only) Note: Only applies when running in Low Voltage Mode (1.5 V) VIH_SST/VIL_SST Thermal Reporting Signals: SST VIH_PECI/VIL_PECI Thermal Reporting Signals: PECI VIH_SASCLK/ VIL_SASCLK Vcm_sas (SRV/WS SKUs Only) SAS Clocks:CLKIN_SAS0[P,N], CLKIN_SAS1[P,N] VIH_UPCLK/ VIL_UPCLK Vcm_up (SRV/WS SKUs Only) PCIe* Uplink Clock:CLKIN_SPCIE0[P,N] DC Input Characteristics (Sheet 1 of 3) Parameter Min Max Unit Notes VIL1 Input Low Voltage -0.5 0.3 x 3.3 V V 9 VIH1 Input High Voltage 0.5 x 3.3 V V5REF + 0.5 V 9 VIMIN2-Gen3i Minimum Input Voltage - 6.0 Gb/s SATA 240 -- mVdiffp-p 5 VIMAX2Gen3i Maximum Input Voltage - 6.0 Gb/s SATA -- 1000 mVdiffp-p 5 VIL3 Input Low Voltage -0.5 0.8 V VIH3 Input High Voltage 2.0 3.3 V + 0.5 V 9 VIL4 Input Low Voltage -0.5 0.3 x 3.3 V V 9 VIH4 Input High Voltage 0.5 x 3.3 V) 3.3 V + 0.5 V 9 VIL5 Input Low Voltage -0.5 0.8 V VIH5 Input High Voltage 2.1 3.3 V + 0.5 V 9 VIL6 Input Low Voltage -0.5 0.35 V 10 VIH6 Input High Voltage 0.75 1.1 V + 0.5 V 10 VIL7 Input Low Voltage 0 0.51 x V_PROC_IO V VIH7 Input High Voltage 0.81 x V_PROC_IO V_PROC_IO V VIMIN8Gen1 Minimum Input Voltage 175 -- mVdiffp-p 4 VIMAX8Gen1 Maximum Input Voltage -- 1200 mVdiffp-p 4 VIMIN8Gen2 Minimum Input Voltage 100 -- mVdiffp-p 4 VIMAX8Gen2 Maximum Input Voltage 4 VIL9 VIH9 -- 1200 mVdiffp-p Input Low Voltage -0.5 0.10 V Input High Voltage 0.50 1.2 V VIMIN10- Gen1i Minimum Input Voltage - 1.5 Gb/s internal SATA 325 -- mVdiffp-p 5 VIMAX10-Gen1i Maximum Input Voltage - 1.5 Gb/s internal SATA -- 600 mVdiffp-p 5 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 287 Electrical Characteristics Table 8-6. DC Input Characteristics (Sheet 2 of 3) Symbol Parameter Min Max Unit Notes VIMIN10Gen1m Minimum Input Voltage - 1.5 Gb/s eSATA 240 -- mVdiffp-p 5 VIMAX10Gen1m Maximum Input Voltage - 1.5 Gb/s eSATA -- 600 mVdiffp-p 5 VIMIN10-Gen2i Minimum Input Voltage - 3.0 Gb/s internal SATA 275 -- mVdiffp-p 5 VIMAX10-Gen2i Maximum Input Voltage - 3.0 Gb/s internal SATA -- 750 mVdiffp-p 5 240 -- mVdiffp-p 5 -- 750 mVdiffp-p 5 VIMIN10Gen2m Minimum Input Voltage - 3.0 Gb/s eSATA VIMAX10Gen2m Maximum Input Voltage - 3.0 Gb/s eSATA VIL11 Input Low Voltage -0.5 0.35 x 3.3 V V 9 VIH11 Input High Voltage 0.65 x 3.3 V 3.3 + 0.5 V V 9 VIL12 (Absolute Minimum) Input Low Voltage -0.3 VIH12 (Absolute Maximum) Input High Voltage V 1.150 V VIL13 Input Low Voltage -0.5 0.78 V VIH13 Input High Voltage 2.3 VccRTC + 0.5 V 6 VIL14 Input Low Voltage -0.5 0.78 V VIH14 Input High Voltage 2.0 VccRTC + 0.5 V 6 VIL15 Input Low Voltage -0.5 0.8 V 9 VIH15 Input High Voltage 2.1 3.3 V + 0.5 V 9 VIMIN16 (SRV/WS SKUs Only) Minimum Input Voltage - 1.5 Gb/s SAS 325 -- mVdiffp-p VIMAX16 (SRV/WS SKUs Only) Maximum Input Voltage - 1.5 Gb/s SAS -- 1600 mVdiffp-p VIMIN17 (SRV/WS SKUs Only) Minimum Input Voltage - 3.0 Gb/s SAS 275 -- mVdiffp-p VIMAX17 (SRV/WS SKUs Only) Maximum Input Voltage - 3.0 Gb/s SAS -- 1600 mVdiffp-p VIMIN18 (SRV/WS SKUs Only) Minimum Input Voltage - PCIe Uplink 15 -- mVdiffp-p VIMAX18 (SRV/WS SKUs Only) Maximum Input Voltage - PCIe Uplink -- 1200 mVdiffp-p Vclk_in_cross(a bs) Absolute Crossing Point 0.250 0.550 V 11 Vcross-delta Vcross variation 140 mV 11 VDI Differential Input Sensitivity 0.2 -- V 1,3 VCM Differential Common Mode Range 0.8 2.5 V 2,3 3 VSE Single-Ended Receiver Threshold 0.8 2.0 V VHSSQ HS Squelch Detection Threshold 100 150 mV HS Disconnect Detection Threshold 525 625 mV VHSDSC 288 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Electrical Characteristics Table 8-6. Symbol DC Input Characteristics (Sheet 3 of 3) Min Max Unit -50 500 mV Input Low Voltage 0 0.4 x Vcc_HDA V VIH_HDA Input High Voltage 0.6 x Vcc_HDA) 1.5 V -0.3 0.4 V VHSCM VIL_HDA Parameter HS Data Signaling Common Mode Voltage Range VIL_SST Input Low Voltage VIH_SST Input High Voltage 1.1 1.5 V VIL_PECI Input Low Voltage -0.15 0.275 x V_PROC_IO V VIH_PECI Input High Voltage 0.725 x V_PROC_IO V_PROC_IO + 0.15 V VIH_SASCLK (SRV/WS SKUs Only) Differential Input High Voltage - SAS Clocks 150 -- mV VIH_SASCLK (SRV/WS SKUs Only) Differential Input Low Voltage - SAS Clocks -- -150 mV Differential Rising and falling edge rates 1 4 V/ns ERRefclkdiffRrise, ERRefclk-diffFall Differential ringback voltage -100 100 mV VIL_UPCLK (SRV/WS SKUs Only) VRB-diff Differential Input High Voltage - SAS Clocks 150 -- mV VIL_UPCLK (SRV/WS SKUs Only) Differential Input Low Voltage - SAS Clocks -- -150 mV Differential Rising and falling edge rates 1 4 V/ns -100 100 mV ERRefclkdiffRrise, ERRefclk-diffFall VRB-diff Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Differential ringback voltage Notes 12,13 12,13 VDI = | USBPx[P] - USBPx[N] Includes VDI range Applies to Low-Speed/Full-Speed USB PCI Express* mVdiff p-p = 2*|PETp[x] - PETn[x]| SATA Vdiff, RX (VIMAX10/MIN10) is measured at the SATA connector on the receiver side (generally, the motherboard connector), where SATA mVdiff p-p = 2*|SATA[x]RXP - SATA[x]RXN| VccRTC is the voltage applied to the VccRTC well of the PCH. When the system is in a G3 state, this is generally supplied by the coin cell battery, but for S5 and greater, this is generally VccSus3_3. This is an AC Characteristic that represents transient values for these signals Applies to Hogh-Speed USB 2.0. 3.3 V refers to VccSus3_3 for signals in the suspend well and to Vcc3_3 for signals in the core well. See Table 3-2, or Table 3-3 for signal and power well association. 1.1 V refers to VccIO or VccCore for signals in the core well and to VccASW for signals in the Active Sleep well. See Table 3-2 or Table 3-3 for signal and power well association. The Vcross and Vcross delta spec are not applicable to SAS and PCIE Uplink due to the presence of AC coupling capacitor. OEM's are encouraged to use vendor parts that meet Vcross and Vcross delta spec specified in the vendor datasheet on their respective test boards. The SAS and Uplink receivers are more sensitive to the low end edge rate value 1 V/ns. Failures of edge rate spec on the higher side i.e failures of edge rate reported more than 4V/ns are acceptable up to 6V/ns and these high side failures up to 6V/ns are not required to be reported. The rising edge of CLKIN_SAS[0/1]_DN is equal to the falling edge of CLKIN_SAS[0/1]_DP. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 289 Electrical Characteristics Table 8-7. DC Characteristic Output Signal Association (Sheet 1 of 2) Symbol VOH1/VOL1 Processor Signal: PM_SYNC, PM_SYNC2, PROCPWRGD VOH2/VOL2 LPC Signals: LAD[3:0], LFRAME#, INIT3_3V# Power Management Signal: LAN_PHY_PWR_CTRL PCI Signals: AD[31:0], C/BE[3:0], DEVSEL#, FRAME#, IRDY#, PAR, PCIRST#, GNT[3:0]#, PME#(1) Interrupt Signals: PIRQ[D:A], PIRQ[H:E]#(1) GPIO Signals: GPIO[73, 72, 59, 56, 55:50, 49, 47:44 43:40, 37, 36, 35, 33, 28, 27, 26, 25, 23, 21, 20, 19, 18, 16, 15, 14, 13, 12, 10, 9, 8, 5:2, 0] SPI Signals: SPI_CS0#, SPI_CS1#, SPI_MOSI, SPI_CLK GSX Signals: GSCLK, GSXSLOAD, GSXSRESET#, GSXDOUT Miscellaneous Signals: SPKR VOH3/VOL3 SMBus Signals: SMBCLK(1), SMBDATA(1) System Management Signals: SML[1:0]CLK(1), SML[1:0]DATA(1), SML0ALERT#, SML1ALERT# GPIO Signals: GPIO[75, 74, 60, 58, 11] VOH4/VOL4 Power Management Signals: SLP_S3#, SLP_S4#, SLP_S5#, SLP_A#, SLP_LAN#, SUSCLK, DRAMPWROK, SLP_SUS# SATA Signals: SATALED#, SCLOCK, SLOAD, SDATAOUT0, SDATAOUT1 SAS SGPIO Signals (SRV/WS SKUs Only): SAS_LED#, SAS_CLOCK1, SAS_LOAD1, SAS_DATAIN1, SAS_DATAOUT1, SAS_CLOCK2, SAS_LOAD2, SAS_DATAIN2, SAS_DATAOUT2 GPIO Signals: GPIO[71:68, 63:61, 57, 48, 39, 38, 34, 32, 31, 30, 29, 24, 22, 17, 7, 6, 1] Interrupt Signals: SERIRQ ADR Signal: ADR_COMPLETE VOH5/VOL5 USB Signals: USBP[13:0][P,N] in Low-speed and Full-speed Modes VOMIN6 -Gen3i/ VOMAX6-Gen3i SATA Signals: SATA[1:0]TX[P,N] (6.0 Gb/s Internal SATA) VOMIN7 -Gen1i,m/ VOMAX7-Gen1i,m SATA Signals: SATA[5:0]TX[P,N] (1.5 Gb/s Internal and External SATA) VOMIN7 -Gen2i,m/ VOMAX7-Gen2i,m SATA Signals: SATA[5:0]TX[P,N] (3.0 Gb/s Internal and External SATA) VOMIN8-PCIeGen12/ VOMAX8-PCIeGen12 VOH9/VOL9 PCI Express* Data TX Signals: PET[p,n][8:1] (Gen 1 and Gen 2) Power Management Signal: PLTRST# VOMIN10/VOMAX10 (SRV/WS SKUs Only) SAS Signals: SAS[7:0]TX[P,N] (SAS-1.1) VOMIN11/VOMAX11 (SRV/WS SKUs Only) SAS Signals: SAS[7:0]TX[P,N] (SAS-2.0) VOMIN12/VOMAX12 (Intel(R) C606, C608 Chipset SKUs Only) PCI Express* Uplink TX Signals:PEG0_T[p,n][3:0] VHSOI VHSOH VHSOL VCHIRPJ VCHIRPK USB Signals: USBP[13:0][P:N] in High-speed Mode VOH_HDA/VOL_HDA VOL_JTAG VOH_PCICLK/ VOL_PCICLK VOL_SGPIO 290 Associated Signals Intel High Definition Audio Signals: HDA_RST#, HDA_SDOUT, HDA_SYNC, HDA_BCLK JTAG Signals: JTAG_TDO GPIO Signals: [67:64] SGPIO Signals: SCLOCK, SLOAD, SDATAOUT0, SDATAOUT1 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Electrical Characteristics Table 8-7. DC Characteristic Output Signal Association (Sheet 2 of 2) Symbol VOH_PWM/ VOL_PWM VOH_SST/VOL_SST VOH_PECI/VOL_PECI Note: 1. Table 8-8. Associated Signals Thermal Control Signals: PWM[3:0]1 SST signal: SST PECI signal: PECI These signals are open-drain. DC Output Characteristics (Sheet 1 of 2) Symbol Parameter Min Max Unit IOL / IOH 3 mA Notes VOL1 Output Low Voltage -- 0.255 V VOH1 Output High Voltage V_PROC_IO - 0.3 V_PROC_IO V -3 mA VOL2 Output Low Voltage -- 0.1 x 3.3 V V 1.5 mA 7 VOH2 Output High Voltage 0.9 x 3.3 V 3.3 V -0.5 mA 7 1, 7 VOL3 Output Low Voltage 0 0.4 V VOH3 Output High Voltage 3.3 V - 0.5 -- V 4 mA VOL4 Output Low Voltage -- 0.4 V 6 mA VOH4 Output High Voltage 3.3 V- 0.5 3.3 V V -2 mA VOL5 Output Low Voltage -- 0.4 V 5 mA VOH5 Output High Voltage 3.3 V - 0.5 -- V -2 mA 200 -- mVdiff p-p 3 -- 900 mVdiff p-p 3 400 -- mVdiff p-p 3 -- 600 mVdiff p-p 3 400 -- mVdiff p-p 3 -- 700 mVdiff p-p 3 VOMIN6-Gen3i Minimum Output Voltage VOMAX6-Gen3i Maximum Output Voltage VOMIN7-Gen1i,m Minimum Output Voltage VOMAX7-Gen1i,m Maximum Output Voltage VOMIN7-Gen2i,m Minimum Output Voltage VOMAX7-Gen2i,m Maximum Output Voltage 7 7 VOMIN8-PCIeGen12 Output Low Voltage 800 -- mVdiff p-p 2 VOMAX8-PCIeGen12 Output High Voltage -- 1200 mVdiff p-p 2 VOL9 Output Low Voltage -- 0.1 x 3.3 V V 1.5 mA 7 VOH9 Output High Voltage 0.9 x 3.3 V 3.3 V -2.0 mA 7 800 -- mVdiff p-p -- 1600 mVdiff p-p 850 -- mVdiff p-p -- 1200 mVdiff p-p 250 -- mVdiff p-p VOMIN10 Minimum Output Voltage VOMAX10 Maximum Output Voltage VOMIN11 Minimum Output Voltage VOMAX11 Maximum Output Voltage VOMIN12 Minimum Output Voltage Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 291 Electrical Characteristics Table 8-8. DC Output Characteristics (Sheet 2 of 2) Symbol Parameter Min Max Unit -- 1200 mVdiff p-p -10.0 10.0 mV Maximum Output Voltage VOMAX12 VHSOI HS Idle Level VHSOH HS Data Signaling High 360 440 mV VHSOL HS Data Signaling Low -10.0 10.0 mV IOL / IOH VCHIRPJ Chirp J Level 700 1100 mV VCHIRPK Chirp K Level -900 -500 mV VOL_HDA Output Low Voltage -- 0.1 x VccSusHDA V 1.5 mA VOH_HDA Output High Voltage 0.9 x VccSusHDA -- V -0.5 mA VOL_PWM Output Low Voltage -- 0.4 V 8 mA VOH_PWM Output High Voltage -- -- VOL_SGPIO Output Low Voltage -- 0.4 V VOL_PCICLK Output Low Voltage 0.4 V V 1 mA 0.3 V 0.5 mA Notes 1 -1 mA VOH_PCICLK Output High Voltage 2.4 VOL_SST Output Low Voltage 0 VOH_SST Output High Voltage 1.1 1.5 V -6 mA VOL_PECI Output Low Voltage -- 0.25 x V_PROC_IO V 0.5 mA VOH_PECI Output High Voltage 0.75 x V_PROC_IO V_PROC_IO VOL_HDA Output Low Voltage -- 0.1 x VccHDA V 1.5 mA VOL_JTAG Output Low Voltage 0 0.1 x 1.05 V V 1.5 mA -6 mA Notes: 1. The SERR#, PIRQ[H:A], SMBDATA, SMBCLK, SML[1:0]CLK, SML[1:0]DATA, SML[1:0]'ALERT# and PWM[3:0] signal has an open-drain driver and SATALED# has an open-collector driver, and the VOH spec does not apply. This signal must have external pull up resistor. 2. PCI Express* mVdiff p-p = 2*|PETp[x] - PETn[x]| 3. SATA Vdiff, tx (VOMIN7/VOMAX7) is measured at the SATA connector on the transmit side (generally, the motherboard connector), where SATA mVdiff p-p = 2*|SATA[x]TXP - SATA[x]TXN| 4. Maximum Iol for PROCPWRGD is 12mA for short durations (<500 mS per 1.5 s) and 9 mA for long durations. 5. For INIT3_3V only, for low current devices, the following applies: VOL5 Max is 0.15 V at an IOL5 of 2 mA. 6. 3.3 V refers to VccSus3_3 for signals in the suspend well, to Vcc3_3 for signals in the core well and to VccDSW3_3 for those signals in the Deep Sleep well. See Table 3-2 or Table 3-3 for signal and power well association. 7. 3.3 V refers to VccSus3_3 for signals in the suspend well and to Vcc3_3 for signals in the core well and to VccDSW3_3 for signals in the ME well. See Table 3-2, or Table 3-3 for signal and power well association. Table 8-9. Other DC Characteristics (Sheet 1 of 2) Symbol V_PROC_IO 292 Parameter Processor I/F Min Nom Max Unit Notes .95 1.0 - 1.1 1.16 V 1 V5REF PCH Core Well Reference Voltage 4.75 5 5.25 V 1 Vcc3_3 I/O Buffer Voltage 3.14 3.3 3.47 V 1 VccVRM 1.5 V Internal PLL and VRMs 1.455 1.5 1.545 V 1, 3 VccVRM 1.8 V Internal PLL and VRMs 1.746 1.8 1.854 V 1, 3 V5REF_Sus Suspend Well Reference Voltage 4.75 5 5.25 V 1 VccSus3_3 Suspend Well I/O Buffer Voltage 3.14 3.3 3.47 V 1 VccCore Internal Logic Voltage 1.05 1.1 1.16 V 1 VccIO Core Well I/O buffers 1.05 1.1 1.16 V 1 .95 1.0 - 1.1 1.16 V 1 3.14 3.3 3.47 V 1 VccDMI DMI Buffer Voltage VccSPI 3.3 V Supply for SPI Controller Logic Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Electrical Characteristics Table 8-9. Other DC Characteristics (Sheet 2 of 2) Symbol VccASW VccRTC (G3-S0) Parameter 1.1 V Supply for Intel ME and Interated LAN Nom Max Unit Notes 1.05 1.1 1.16 V 1 2 -- 3.47 V 1 High Definition Audio Controller Suspend Voltage 3.14 3.3 3.47 V 1 High Definition Audio Controller Low Voltage Mode Suspend Voltage 1.43 1.5 1.58 V 1 VccDFTERM 1.8V supply power supply for DF_TVS 1.71 1.8 1.89 V 1 VccDSW3_3 3.3v supply for Deep S4/S5 wells 3.14 3.3 3.47 V 1 VccSusHDA VccSusHDA (low voltage) VccRBIAS_PU (Intel(R) C606, C608 Chipset SKUs Only) Battery Voltage Min PCIe Uplink RBIAS Voltage 1.05 1.1 1.15 V 4 VccRBIAS_SAS0 (SRV/WS SKUs Only) SAS0 RBIAS Voltage 1.05 1.1 1.15 V 4 VccRBIAS_SAS1 (SRV/WS SKUs Only) SAS1 RBIAS Voltage 1.05 1.1 1.15 V 4 PCIe Uplink PLL Voltage 1.05 1.1 1.15 V 4 VccPLLSAS0 (SRV/WS SKUs Only) SAS0 PLL Voltage 1.05 1.1 1.15 V 4 VccPLLSAS1 (SRV/WS SKUs Only) SAS1 PLL Voltage 1.05 1.1 1.15 V 4 VccPLLEXPU (Intel(R) C606, C608 Chipset SKUs Only) ILI1 PCI_3V Hi-Z State Data Line Leakage -10 -- 10 A (0 V < VIN < Vcc3_3) ILI2 PCI_5V Hi-Z State Data Line Leakage -70 -- 70 A Max VIN = 2.7 V Min VIN = 0.5 V ILI3 Input Leakage Current - All Other -10 -- 10 A 2 CIN Input Capacitance - All Other -- -- TBD pF FC = 1 MHz COUT Output Capacitance -- -- TBD pF FC = 1 MHz CI/O I/O Capacitance -- -- 10 pF FC = 1 MHz Typical Value CL XTAL25_IN 3 pF CL RTCX1 6 pF CL RTCX2 6 pF Notes: 1. The I/O buffer supply voltage is measured at the PCH package pins. The tolerances shown in Table 8-9 are inclusive of all noise from DC up to 20 MHz. In testing, the voltage rails should be measured with a bandwidth limited oscilloscope that has a rolloff of 3 dB/decade above 20 MHz. 2. Includes Single Ended clocks REFCLK14IN, and CLKIN_PCI. 3. Includes only DC tolerance. AC tolerance will be 2% in addition to this range. 4. Includes both DC and AC tolerance. For optimal effect, Min/Max value should be within 3% of the nominal value. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 293 Electrical Characteristics 8.5 AC Characteristics Table 8-10. PCI Express* and DMI Interface Timings Symbol Parameter Min Max Unit Figures Notes Transmitter and Receiver Timings UI Unit Interval - PCI Express* Gen 1 (2.5 GT/s) UI Unit Interval - PCI Express Gen 2 (5.0 GT/s) UI Unit Interval - DMI TTX-EYE Minimum Transmission Eye Width 399.88 400.12 ps 5 199.9 200.1 ps 5 399.88 400.12 ps 0.7 -- UI 5 8-25 1,2 TTX-RISE/ Fall (Gen1) D+/D- TX Out put Rise/Fall time -0.125 UI 1,2 TTX-RISE/ Fall (Gen2) D+/D- TX Out put Rise/Fall time -0.15 UI 1,2 Minimum Receiver Eye Width 0.40 TRX-EYE -- UI 8-26 3,4 Notes: 1. Specified at the measurement point into a timing and voltage compliance test load and measured over any 250 consecutive TX UIs. (Also refer to the Transmitter compliance eye diagram) 2. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTXJITTER-MAX = 0.30 UI for the Transmitter collected over any 250 consecutive TX UIs. The TTXEYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. 3. Specified at the measurement point and measured over any 250 consecutive UIs. The test load documented in the PCI Express* specification 2.0 should be used as the RX device when taking measurements (also refer to the Receiver compliance eye diagram). If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram. 4. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to--MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total 0.6 UI jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram. 5. Nominal Unit Interval is 400 ps for 2.5 GT/s and 200 ps for 5 GT/s. Table 8-11. PCI Express* Uplink Interface Timings (Intel(R) C606, C608 Chipset SKUs Only) Symbol Parameter Min Max Unit Figures Notes Transmitter and Receiver Timings UI Unit Interval TRX-EYE Note: 1. 294 Minimum Receiver Eye Width 124.96 0.3 125.04 ps 1 UI The specified UI is equivalent to a tolerance of 300 ppm for each reference clock source. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Electrical Characteristics Table 8-12. SAS Interface Timings (SRV/WS SKUs Only) Sym UI UI-2 UI-OOB Parameter Min Max Units Gen I Operating Data Period 666.43 670.23 ps Gen II Operating Data Period (3Gb/s) 333.21 335.11 ps OOB Operating Data period 665.07 668.27 ns t120 Rise Time 0.15 0.41 UI t121 Fall Time 0.15 0.41 UI t122 TX differential skew -- 20 ps t123 COMRESET 310.4 329.6 ns t124 COMWAKE transmit spacing 103.5 109.9 ns t125 COMSAS transmit spacing 931.2 988.8 ns Notes Figure Table 8-13. Clock Timings (Sheet 1 of 2) Sym Parameter Min Max Unit Notes Figure REFCLK14IN t6 Period 69.820 69.862 ns t7 High time 29.975 38.467 ns Low time 29.975 38.467 ns 40 60 % t8 Duty Cycle Rising Edge Rate 1.0 4 V/ns Falling Edge Rate 1.0 4 V/ns -- 800 ps Jitter SMBus/SMLink Clock (SMBCLK, SML[1:0]CLK) fsmb Operating Frequency 10 100 KHz 5 High time 4.0 50 s 1 t23 Low time 4.7 -- s 8-20 t24 Rise time -- 1000 ns 8-20 t25 Fall time -- 300 ns 8-20 t22 8-20 SMLink0 Clock (SML0CLK) (See note 7) fsmb 0 400 KHz High time 0.6 50 ms t23_SML Low time 1.3 -- ms 8-20 t24_SML Rise time -- 300 ns 8-20 t25_SML Fall time -- 300 ns 8-20 t22_SML Operating Frequency 2 8-20 HDA_BCLK (Intel High Definition Audio) fHDA Operating Frequency 24.0 MHz Frequency Tolerance -- 100 ppm t26a C2C Jitter (refer to Clock Chip Specification) -- 300 ppm t27a High Time (Measured at 0.75 Vcc) 18.75 22.91 ns 8-11 t28a Low Time (Measured at 0.35 Vcc) 18.75 22.91 ns 8-11 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 295 Electrical Characteristics Table 8-13. Clock Timings (Sheet 2 of 2) Sym Parameter Min Max Unit Notes Figure SATA Clock (CLKIN_SATA_[P:N]) from a Clock Chip t36(ssc-on) Period 9.999 10.05 t36(ssc-off) Period 9.999 10.001 ns 1 8 V/ns 50 ps Slew rate C2C Jitter (refer to Clock Chip Specification) ns 3 DMI Clock (CLKIN_DMI_[P:N]) from a Clock Chip tDMI(ssc-on) Period 9.999 10.05 ns tDMI(ssc-off) Period 9.999 10.001 ns Slew rate clock duty cycle VRB-Diff Tstable 1 4 V/ns 45 55 % -100 100 mV 500 ps PCIe* Uplink and SAS Clock (CLKIN_SPCIE0_[P:N], CLKIN_SAS[1:0]_[P:N]) from a Clock Chip ((PCIe* Uplink is Intel(R) C606, C608 Chipset SKUs Only and SAS Clock is SRV/WS Only)) tUplink(ssc-on) Period 9.999 10.05 ns tUplink(ssc-off) Period 9.999 10.001 ns tSAS(ssc-off only) Period 9.999 10.001 ns 1 4 V/ns 45 55 % slew rate clock duty cycle Tstable 500 7 ps DOT 96 MHz (CLKIN_DOT96[P,N]) from a clock chip t36 Period Slew rate 10.066 10.768 ns 1 8 V/ns 250 ps C2C Jitter (refer to Clock Chip Specification) 3 Suspend Clock (SUSCLK) fsusclk Operating Frequency t39 High Time t39a Low Time kHz 2 10 32 -- s 2 10 -- s 2 SPI_CLK Slew_Rise Output Rise Slew Rate (0.2Vcc - 0.6Vcc) 1 4 V/ns 4 8-22 Slew_Fall Output Fall Slew Rate (0.6Vcc - 0.2Vcc) 1 4 V/ns 4 8-22 Notes: 1. The maximum high time (t18 Max) provide a simple ensured method for devices to detect bus idle conditions. 2. SUSCLK duty cycle can range from 30% minimum to 70% maximum. 3. Jitter is specified as cycle to cycle measured in pico seconds. Period min and max includes cycle to cycle jitter 4. Testing condition: 1 kohm pull up to Vcc, 1 kohm pull down and 10 pF pull down and 1/2 inch trace See Figure 8-28 for more detail. 5. When the PCH communicates to BMC using SMLINK signal, up to 400 kHz clock frequency can be supported. 6. When SMLink0 is configured to run in Fast Mode using a soft strap, the operating frequency is in the range of 300 KHz-400 KHz. 296 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Electrical Characteristics 7. The SAS and Uplink receivers are more sensitive to the low end edge rate value 1 V/ns. Failures of edge rate spec on the higher side i.e failures of edge rate reported more than 4 V/ns are acceptable up to 6 V/ns and these high side failures up to 6V/ns are not required to be reported. Table 8-14. PCI Interface Timing Sym Parameter Min Max Units Notes Figure 1 8-12 t40 AD[31:0] Valid Delay 2 11 ns t41 AD[31:0] Setup Time to PCICLK Rising 7 -- ns 8-13 t42 AD[31:0] Hold Time from PCICLK Rising 0 -- ns 8-13 t43 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, PAR, PERR#, PLOCK#, DEVSEL# Valid Delay from PCICLK Rising 2 11 ns t44 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, PAR, PERR#, PLOCK#, IDSEL, DEVSEL# Output Enable Delay from PCICLK Rising 2 t45 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, PERR#, PLOCK#, DEVSEL#, GNT[A:B]# Float Delay from PCICLK Rising 2 t46 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, SERR#, PERR#, DEVSEL#, Setup Time to PCICLK Rising 7 t47 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, SERR#, PERR#, DEVSEL#, REQ[A:B]# Hold Time from PCLKIN Rising 0 t48 PCIRST# Low Pulse Width 1 t49 GNT[3:0]# Valid Delay from PCICLK Rising t50 REQ[3:0]# Setup Time to PCICLK Rising Note: 1. 28 -- 1 8-12 ns 8-16 ns 8-14 ns 8-13 ns 8-13 ms 8-15 2 12 ns 12 -- ns Refer to note 3 of table 4-4 in Section 4.2.2.2 and note 2 of table 4-6 in Section 4.2.3.2 of the PCI Local Bus Specification, Revision 2.3, for measurement details. Table 8-15. Universal Serial Bus Timing (Sheet 1 of 2) Sym Parameter Min Max Units Notes Fig Full-speed Source (Note 7) t100 USBPx+, USBPx- Driver Rise Time 4 20 ns 1, 6 CL = 50 pF 8-17 t101 USBPx+, USBPx- Driver Fall Time 4 20 ns 1, 6 CL = 50 pF 8-17 t102 Source Differential Driver Jitter - To Next Transition - For Paired Transitions -3.5 -4 3.5 4 ns ns 2, 3 8-18 t103 Source SE0 interval of EOP 160 175 ns 4 8-19 t104 Source Jitter for Differential Transition to SE0 Transition -2 5 ns 5 t105 Receiver Data Jitter Tolerance - T o Next Transition - For Paired Transitions -18.5 -9 18.5 9 ns ns 3 8-18 t106 EOP Width: Must accept as EOP 82 -- ns 4 8-19 t107 Width of SE0 interval during differential transition -- 14 ns Low-speed Source (Note 8) Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 297 Electrical Characteristics Table 8-15. Universal Serial Bus Timing (Sheet 2 of 2) Sym Parameter Min Max Units Notes Fig Full-speed Source (Note 7) t108 USBPx+, USBPx - Driver Rise Time 75 300 ns 6 CL = 200pF CL = 600pF 8-17 t109 USBPx+, USBPx - Driver Fall Time 75 300 ns 6 CL = 200pF CL = 600pF 8-17 t110 Source Differential Driver Jitter To Next Transition For Paired Transitions -25 -14 25 14 ns ns 2, 3 8-18 t111 Source SE0 interval of EOP 1.25 1.50 s 4 8-19 t112 Source Jitter for Differential Transition to SE0 Transition -40 100 ns 5 t113 Receiver Data Jitter Tolerance - To Next Transition- For Paired Transitions -152 -200 152 200 ns ns 3 8-18 t114 EOP Width: Must accept as EOP 670 -- ns 4 8-19 t115 Width of SE0 interval during differential transition -- 210 ns Notes: 1. Driver output resistance under steady state drive is specified at 28 at minimum and 43 at maximum. 2. Timing difference between the differential data signals. 3. Measured at crossover point of differential data signals. 4. Measured at 50% swing point of data signals. 5. Measured from last crossover point to 50% swing point of data line at leading edge of EOP. 6. Measured from 10% to 90% of the data signal. 7. Full-speed Data Rate has minimum of 11.97 Mb/s and maximum of 12.03 Mb/s. 8. Low-speed Data Rate has a minimum of 1.48 Mb/s and a maximum of 1.52 Mb/s. Table 8-16. SATA Interface Timings Sym Parameter UI Max Units Gen I Operating Data Period 666.43 670.23 ps UI-2 Gen II Operating Data Period (3Gb/s) 333.21 335.11 ps UI-3 Gen III Operating Data Period (6Gb/s) Notes 166.6667 166.6083 ps t120gen1 Rise Time 0.15 0.41 UI 1 t120gen2 Rise Time 0.2 0.41 UI 1 t120gen3 Rise Time 0.2 0.41 UI 1 t121gen1 Fall Time 0.15 0.41 UI 2 t121gen2 Fall Time 0.2 0.41 UI 2 Fall Time 0.2 0.48 UI 2 -- 20 ps t121gen3 t122 TX differential skew t123 COMRESET 310.4 329.6 ns 3 t124 COMWAKE transmit spacing 103.5 109.9 ns 3 t125 OOB Operating Data period 646.67 686.67 ns 4 Notes: 1. 2. 3. 4. 298 Min Figure 20% - 80% at transmitter 80% - 20% at transmitter As measured from 100 mV differential crosspoints of last and first edges of burst. Operating data period during Out-Of-Band burst transmissions. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Electrical Characteristics Table 8-17. SMBus and SMLink Timing Sym Parameter Min Max Units t130 Bus Free Time Between Stop and Start Condition 4.7 -- s t130SMLFM Bus Free Time Between Stop and Start Condition 1.3 -- s t131 Hold Time after (repeated) Start Condition. After this period, the first clock is generated. 4.0 -- s t131SMLFM Hold Time after (repeated) Start Condition. After this period, the first clock is generated. 0.6 -- s t132 Repeated Start Condition Setup Time 4.7 -- s t132SMLFM Repeated Start Condition Setup Time 0.6 -- s t133 Stop Condition Setup Time 4.0 -- s t133SMLFM Stop Condition Setup Time 0.6 -- s Notes Fig 5 8-20 8-20 8-20 5 8-20 8-20 5 8-20 5 8-20 8-20 t134 Data Hold Time 0 -- ns 4 8-20 t134SMLFM Data Hold Time 0 -- ns 4, 5 8-20 t135 Data Setup Time 250 -- ns t135SMLFM Data Setup Time 100 -- ns 8-20 t136 Device Time Out 25 35 ms 1 t137 Cumulative Clock Low Extend Time (slave device) -- 25 ms 2 8-21 t138 Cumulative Clock Low Extend Time (master device) -- 10 ms 3 8-21 5 8-20 Notes: 1. A device will timeout when any clock low exceeds this value. 2. t137 is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to stop. If a slave device exceeds this time, it is expected to release both its clock and data lines and reset itself. 3. t138 is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, ack-to-ack or ack-to-stop. 4. t134 has a minimum timing for I2C of 0 ns, while the minimum timing for SMBus is 300 ns. 5. Timings with the SMLFM designator apply only to SMLink0 and only when SMLink0 is operating in Fast Mode. Table 8-18. Intel(R) High Definition Audio Timing Sym Parameter Min Max Units Notes Fig t143 Time duration for which HDA_SDO is valid before HDA_BCLK edge. 7 -- ns 8-23 t144 Time duration for which HDA_SDO is valid after HDA_BCLK edge. 7 -- ns 8-23 t145 Setup time for HDA_SDIN[3:0] at rising edge of HDA_BCLK 15 -- ns 8-23 t146 Hold time for HDA_SDIN[3:0] at rising edge of HDA_BCLK 0 -- ns 8-23 Min Max Units 2 11 ns 8-12 Table 8-19. LPC Timing (Sheet 1 of 2) Sym Parameter t150 LAD[3:0] Valid Delay from PCICLK Rising Notes Fig t151 LAD[3:0] Output Enable Delay from PCICLK Rising 2 ns 8-16 t152 LAD[3:0] Float Delay from PCICLK Rising -- 28 ns 8-14 t153 LAD[3:0] Setup Time to PCICLK Rising 7 -- ns 8-13 t154 LAD[3:0] Hold Time from PCICLK Rising 0 -- ns 8-13 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 299 Electrical Characteristics Table 8-19. LPC Timing (Sheet 2 of 2) Sym Parameter Min Max Units Notes Fig t155 LDRQ[1:0]# Setup Time to PCICLK Rising 12 -- ns 8-13 t156 LDRQ[1:0]# Hold Time from PCICLK Rising 0 -- ns 8-13 t157 eE# Valid Delay from PCICLK Rising 2 12 ns 8-12 Min Max Units Table 8-20. Miscellaneous Timings Sym Parameter Notes Fig t160 SERIRQ Setup Time to PCICLK Rising 7 -- ns 8-13 t161 SERIRQ Hold Time from PCICLK Rising 0 -- ns 8-13 t162 RI#, GPIO, USB Resume Pulse Width 2 -- RTCCLK 8-15 t163 SPKR Valid Delay from OSC Rising -- 200 ns 8-12 t164 SERR# Active to NMI Active -- 200 ns Table 8-21. SPI Timings (20 MHz) Sym Parameter Min Max Units Notes 1 Fig t180a Serial Clock Frequency - 20M Hz Operation 17.06 18.73 MHz t183a Tco of SPI_MOSI with respect to serial clock falling edge at the host -5 13 ns 8-22 t184a Setup of SPI_MISO with respect to serial clock falling edge at the host 16 -- ns 8-22 t185a Hold of SPI_MISO with respect to serial clock falling edge at the host 0 -- ns 8-22 t186a Setup of SPI_CS[1:0]# assertion with respect to serial clock rising at the host 30 -- ns 8-22 t187a Hold of SPI_CS[1:0]# deassertion with respect to serial clock falling at the host 30 -- ns 8-22 t188a SPI_CLK high time 26.37 -- ns 8-22 t189a SPI_CLK low time 26.82 -- ns 8-22 Notes: 1. The typical clock frequency driven by the PCH is 17.86 MHz. 2. Measurement point for low time and high time is taken at 0.5 (VccSUS3_3). Table 8-22. SPI Timings (33 MHz) (Sheet 1 of 2) Sym 300 Parameter Min Max Units Notes 1 Fig t180b Serial Clock Frequency - 33 MHz Operation 29.83 32.81 MHz t183b Tco of SPI_MOSI with respect to serial clock falling edge at the host -5 5 ns 8-22 t184b Setup of SPI_MISO with respect to serial clock falling edge at the host 8 -- ns 8-22 t185b Hold of SPI_MISO with respect to serial clock falling edge at the host 0 -- ns 8-22 t186b Setup of SPI_CS[1:0]# assertion with respect to serial clock rising at the host 30 -- ns 8-22 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Electrical Characteristics Table 8-22. SPI Timings (33 MHz) (Sheet 2 of 2) Sym Parameter Min Max Units Notes Fig t187b Hold of SPI_CS[1:0]# deassertion with respect to serial clock falling at the host 30 -- ns 8-22 t188b SPI_CLK High time 14.88 - ns 8-22 t189b SPI_CLK Low time 15.18 - ns 8-22 Notes: 1. The typical clock frequency driven by the PCH is 31.25 MHz. 2. Measurement point for low time and high time is taken at 0.5 (VccSUS3_3). Table 8-23. SPI Timings (50 MHz) Sym Parameter Min Max Units Notes Fig 1 8-22 t180c Serial Clock Frequency - 50 MHz Operation 46.99 53.40 MHz t183c Tco of SPI_MOSI with respect to serial clock falling edge at the host -3 3 ns 8-22 t184c Setup of SPI_MISO with respect to serial clock falling edge at the host 8 - ns 8-22 t185c Hold of SPI_MISO with respect to serial clock falling edge at the host 0 - ns 8-22 t186c Setup of SPI_CS[1:0]# assertion with respect to serial clock rising edge at the host 30 - ns 8-22 t187c Hold of SPI_CS[1:0]# assertion with respect to serial clock rising edge at the host 30 - ns 8-22 t188c SPI_CLK High time 7.1 - ns 2, 3 8-22 t189c SPI_CLK Low time 11.17 - ns 2, 3 8-22 Notes: 1. Typical clock frequency driven by the PCH is 50 MHz. This frequency is not available for ES1 samples. 2. When using 50 MHz mode ensure target flash component can meet t188c and t189c specifications. 3. Measurement point for low time and high time is taken at 0.5 (VccSUS3_3). Table 8-24. SST Timings Sym Parameter Min Max Units Notes 0.495 0.495 500 250 s s 1 tBIT Bit time (overall time evident on SST) Bit time driven by an originator tBIT,jitter Bit time jitter between adjacent bits in an SST message header or data bytes after timing has been negotiated -- -- % tBIT,drift Change in bit time across a SST address or SST message bits as driven by the originator. This limit only applies across tBIT-A bit drift and tBIT-M drift. -- -- % tH1 High level time for logic '1' 0.6 0.8 x tBIT tH0 High level time for logic '0' 0.2 0.4 x tBIT tSSTR Rise time (measured from VOL = 0.3V to VIH,min) -- 25 + 5 ns/ node tSSTF Fall time (measured from VOH = 1.1V to VIL,max) -- 33 ns/ node Fig - 2 Notes: 1. The originator must drive a more restrictive time to allow for quantized sampling errors by a client yet still attain the minimum time less than 500 s. tBIT limits apply equally to tBIT-A and tBIT-M. PCH is targeted on 1 Mbps which is 1 s bit time. 2. The minimum and maximum bit times are relative to tBIT defined in the Timing Negotiation pulse. 3. tBIT-A is the negotiated address bit time and tBIT-M is the negotiated message bit time. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 301 Electrical Characteristics Table 8-25. PECI Timings Sym Parameter Bit time (overall time evident on PECI) Bit time driven by an originator tBIT Min Max Units Notes 0.495 0.495 500 250 s s 1 tBIT,jitter Bit time jitter between adjacent bits in an PECI message header or data bytes after timing has been negotiated -- -- % tBIT,drift Change in bit time across a PECI address or PECI message bits as driven by the originator. This limit only applies across tBIT-A bit drift and tBIT-M drift. -- -- % 0.8 x tBIT tH1 High level time for logic '1' 0.6 tH0 High level time for logic '0' Fig 2 0.2 0.4 x tBIT tPECIR Rise time (measured from VOL to VIH,min, Vtt(nom) -5%) -- 30 + (5 x NNODES) ns 3 tPECIF Fall time (measured from VOH to VIL,max, Vtt(nom) +5%) -- 30 x NNODES ns 3 Notes: 1. The originator must drive a more restrictive time to allow for quantized sampling errors by a client yet still attain the minimum time less than 500 s. tBIT limits apply equally to tBIT-A and tBIT-M. PCH is targeted on 2 MHz which is 500 ns bit time. 2. The minimum and maximum bit times are relative to tBIT defined in the Timing Negotiation pulse. 3. Extended trace lengths may appear as additional nodes. 4. tBIT-A is the negotiated address bit time and tBIT-M is the negotiated message bit time. 8.6 Power Sequencing and Reset Signal Timings Table 8-26. Power Sequencing and Reset Signal Timings (Sheet 1 of 3) Sym Min Max Units Notes Fig 23 8-1, 8-2 t200 VccRTC active to RTCRST# deassertion 9 -- ms t200a RTCRST# deassertion to DPWROK high 1 -- ms 8-1, 8-2 t200b VccDSW3_3 active to DPWROK high 10 -- ms 8-1, 8-2 t200c VccDSW3_3 active to VccSus3_3 active 0 -- ms 8-1, 8-2 t201 VccSUS active to RSMRST# deassertion 10 -- ms 1 8-1, 8-2 t202 DPWROK high to SLP_SUS# deassertion 95 -- ms 2, 3 8-1, 8-2 t202a RSMRST# and SLP_SUS# deassertion to SUSCLK toggling 5 -- ms 3, 4 8-1, 8-2 t203 SLP_S5# high to SLP_S4# high 30 us 5. 24 8-3 t204 SLP_S4# high to SLP_S3# high 30 us 6 8-3 t205 Vcc active to PCH_PWROK active 10 ms 7, 14 8-3, 8-4 t206 PCH_PWROK deglitch time 1 ms 8 8-3, 8-4 t207 VccASW active to APWROK high 1 ms 8-3 ms 8-3, 8-4 t208 302 Parameter Clock chip clock outputs to PCH_PWROK high 1 -- Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Electrical Characteristics Table 8-26. Power Sequencing and Reset Signal Timings (Sheet 2 of 3) Sym Parameter Min t209 PCH_PWROK active to PROCPWRGD active 1 ms 8-3, 8-4 PROCPWRGD and SYS_PWROK high to PLTRST# deassertion 1.06 ms 8-3, 8-4 t212 APWROK high to SPI Soft-Strap Reads 500 t214 DMI message and all PCI Express* ports and DMI in L2/L3 state to PLTRST# active 270 t210 Max -- Units s Notes 22 Fig 8-5 us 8-6 t217 PLTRST# active to PROCPWRGD inactive 30 us 8-6 t218 PROCPWRGD inactive to SLP_S3# assertion 11 us 8-6 t220 SLP_S3# low to SLP_S4# low 30 us 8-6 t221 SLP_S4# low to SLP_S5# low 30 us 8-6 t222 SLP_S3# active to PCH_PWROK deasserted 0 t223 PCH_PWROK rising to DRAMPWRGD rising 0 t224 DRAMPWRGD falling to SLP_S4# falling t225 VccRTC active to VccDSW3_3 active 0 t227 VccSUS active to VccASW active t229 VccASW active to Vcc active t230 APWROK high to PCH_PWROK high t231 8-6 us ns 12 8-8 ms 1, 13 8-2 0 ms 1 0 ms 0 ms PCH_PWROK low to Vcc falling 40 ns t232 APWROK falling to VccASW falling 40 ns 16 t233 SLP_S3# assertion to VccCore rail falling 5 us 14, 15 t234 DPWROK falling to VccDSW rail falling 40 ns t235 RSMRST# assertion to VccSUS falling 40 ns t236 RTCRST# assertion to VccRTC falling 0 ms t237 SLP_LAN# (or LANPHYPC) rising to Intel LAN Phy power high and stable t238 DPWROK falling to any of VccDSW, VccSUS, VccASW, or Vcc falling t239 V5REF_Sus active to VccSus3_3 active t240 V5REF active to Vcc3_3 active -100 8-8 -- 20 40 14, 15, 16 8-7 1, 15, 16 8-7 ms ns 1, 14, 15, 16 0 -- ms 17 See Note 15 -- ms 17 1, 14 t241 VccSus supplies active to Vcc supplies active 0 -- ms t242 HDA_RST# active low pulse width 1 -- s t244 VccSus active to SLP_S5#, SLP_S4#, SLP_S3#, PLTRST# and PCIRST# valid -- 50 ns t246 S4 Wake Event to SLP_S4# inactive (S4 Wake) See Note Below 5 t247 S3 Wake Event to SLP_S3# inactive (S3 Wake) See Note Below 6 t251 RSMRST# deassertion to APWROK assertion Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 0 8-7 21 ms 303 Electrical Characteristics Table 8-26. Power Sequencing and Reset Signal Timings (Sheet 3 of 3) Sym Parameter Min Max Units 175 ns t252 THRMTRIP# active to SLP_S3#, SLP_S4#, SLP_S5# active t253 RSMRST# rising edge transition from 20% to 80% 50 s t254 RSMRST# falling edge transition 50 s Notes Fig 19, 20 Notes: 1. VccSus supplies include VccSus3_3, V5REF_Sus, VccSusHDA. 2. This timing is a nominal value counted using RTC clock. If RTC clock isn't already stable at the rising edge of RSMRST#, this timing could be longer than the specified value. 3. Platforms not supporting Deep S4/S5 will typically have SLP_SUS# left as no connect. Hence DPWROK high and RSMRST# deassertion to SUSCLK toggling would be t202+t202a=100ms minimum 4. Platforms supporting Deep S4/S5 will have SLP_SUS# deassert prior to RSMRST#. Platforms not supporting Deep S4/S5 will have RSMRST# deassert prior to SLP_SUS#. 5. Dependency on SLP_S4# and SLP_A# stretching 6. Dependency on SLP_S3# and SLP_A# stretching 7. It is required that the power rails associated with PCI/PCIe (typically the 3.3 V, 5 V, and 12 V core well rails) have been valid for 99 ms prior to PCH_PWROK assertion in order to comply with the 100 ms PCI/ PCIe 2.0 specification on PLTRST# deassertion. System designers must ensure the requirement is met on the platforms. 8. Ensure PCH_PWROK is a solid logic '1' before proceeding with the boot sequence. Note: If PCH_PWROK drops after t206 it will be considered a power failure. 9. Not Applicable for PCH. 10. Not Applicable for PCH. 11. Requires SPI messaging to be completed. 12. The negative min timing implies that DRAMPWRGD must either fall before SLP_S4# or within 100 ns after it. 13. The VccDSW3_3 supplies must never be active while the VccRTC supply is inactive. 14. Vcc includes VccIO, VccCORE, Vcc3_3, Vcc1_1, V5REF, V_PROC_IO, VccDMI and VccASW (if Intel(R) ME only powered in S0). 15. A Power rail is considered to be inactive when the rail is at its nominal voltage minus 5% or less. 16. Board design may meet (t231 AND t232 AND t235) OR (t238). 17. V5REF must be powered up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must power down after Vcc3_3, or before Vcc3_3 within 0.7 V. V5REF_Sus must be powered up before VccSus3_3, or after VccSus3_3 within 0.7 V. Also, V5REF_Sus must power down after VccSus3_3, or before VccSus3_3 within 0.7 V. 18. If RTC clock is not already stable at RSMRST# rising edge, this time may be longer. 19. RSMRST# falling edge must transition to 0.8 V or less before VccSus3_3 drops to 2.9 V 20. The 50 s should be measured from Vih to Vil (2 V to 0.78 V). 21. This is an internal timing showing when the signals (SLP_S5#, SLP_S4#, SLP_S3#, PLTRST# and PCIRST#) are valid after VccSus rail is Active. 22. APWROK high to SPI Soft-Start Read is an internal PCH timing. The timing cannot be measured externally and included here for general power sequencing reference. 23. Measured from VccRTC-10% to RTCRST# reaching 55%*VccRTC. VccRTC is defined as the final settling voltage that the rail ramps. 24. Timing does not apply after Deep S3/S4 exit when Intel ME has configured SLP_S5# and/or SLP_S4# to rise with SLP_A#. 304 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Electrical Characteristics 8.7 Power Management Timing Diagrams Figure 8-1. G3 w/RTC Loss to S4/S5 (With Deep S4/S5 Support) Timing Diagram S o u rc e D e s t in a tio n B o a rd PCH S ig n a l N a m e V ccR TC B o a rd PCH RTCRST# B o a rd PCH V ccD S W 3_3 B o a rd PCH DPW ROK PCH B o a rd B o a rd PCH V ccS us B o a rd PCH RSMRST# D e e p S 4 /S 5 G3 S 5 /S 4 t2 2 5 t2 0 0 t2 0 0 a t2 0 0 b t2 0 0 c SLP_SUS# t2 0 2 t2 0 1 PCH B o a rd SUSCLK PCH B o a rd SLP_S5# t2 2 6 v a lid t2 0 2 a Figure 8-2. O n ly fo r S 4 a fte r G 3 o r D e e p S x G3 w/RTC Loss to S4/S5 (Without Deep S4/S5 Support) Timing Diagram S o u rc e D e s tin a tio n S ig n a l N a m e B o a rd PCH V ccR TC B o a rd PCH RTCRST# B o a rd PCH V ccD S W 3_3 B o a rd PCH DPWROK PCH B o a rd S LP_SU S# B o a rd PCH V ccS us B o a rd PCH RSM RST# PCH B o a rd G3 S 5 /S 4 t2 2 5 t2 0 0 t2 0 0 a t2 0 0 b t2 0 0 c t2 0 2 t2 0 1 SUSCLK v a lid t2 0 2 a PCH Note: B o a rd S LP_S 5# O n ly fo r S 4 a fte r G 3 VccSus rail ramps up later in comparison to VccDSW due to assumption that SLP_SUS# is used to control power to VccSus. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 305 Electrical Characteristics Figure 8-3. S5 to S0 Timing Diagram Source Dest Signal Name PCH Board SLP_S5# PCH Board SLP_S4# PCH Board SLP_S3# PCH Board SLP_A# PCH Board SLP_LAN# Board PCH VccASW Board PCH Vcc t203 t204 Could already be high before this sequence begins(to support M3), but will never go high later than SLP_S3# Could already be high before this sequence begins(to support WOL), but will never go high later than SLP_S3# or SLP_A# t229 PROCPWRGD CPU CPU VRM Board CPU VccCore_CPU CPU VRM PCH SYS_PWROK Board PCH PCH_PWROK Board PCH APWROK PCH CPU DRAMPWROK Clock Chip PCH Clocks PCH CPU PROCPWRGD CPU PCH THRMTRIP# Serial VID Load CPU SVID V_vid t205 t206 t207 APWROK may come up earlier than PCH_PWROK, but no later t230 stable t208 t209 Assumes soft strap programmed to start at PROCPWRGD - expected setting for SNB PLTRST# honored t210 CK Tr ain ST ing RA P_ SE CP T U Fle _RE x S CP SK ET U_ U _ RE V DO SE DM N E T_ DO wr NE ite _A s PCH CPU/Board ignored PCH 306 CPU DMI Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Electrical Characteristics Figure 8-4. S3/M3 to S0 Timing Diagram PCH Board PCH Board SLP_S5# SLP_S4# PCH Board SLP_S3# PCH Board SLP_A# PCH Board SLP_LAN# Board PCH VccASW Board PCH Vcc CPU CPU VRM Board CPU CPU VRM PCH SYS_PWROK Board PCH PCH_PWROK Board PCH APWROK PCH CPU DRAMPWROK Clock Chip PROCPWRGD Serial VID Load CPU SVID Note: V_PROC_IO may go to Vboot at this time, but can also stay at 0V (default) VccCore_CPU PCH V_vid t205 t206 Clocks stable t208 t209 PCH CPU PROCPWRGD CPU PCH THRMTRIP# PCH CPU/Board PCH CPU Assumes soft strap programmed to start at CPUPWRGD - expected setting for SNB honored PLTRST# A t210 Tr ai n ST ing R A P _S ET C P U Fl _R ex E S S E C T_ PU K _R U D ES VD O ET M NE _D w r O N ite E s ignored Figure 8-5. DMI S5/Moff - S5/M3 Timing Diagram S o u rc e D est S ig n a l N a m e PCH B o a rd S L P _S 5# PCH B o a rd S L P _S 4# PCH B o a rd S L P _S 3# PCH B o a rd SLP_A# PCH B o a rd SLP_LAN# B o a rd PCH V ccA S W B o a rd PCH APW ROK C o uld a lre a d y be hig h be fo re th is se q ue n ce be g in s (to sup p o rt W O L), b u t w ill n e ver g o h ig h la ter th a n S L P_A # t20 7 t2 12 PCH S P I F la sh Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SPI 307 Electrical Characteristics Figure 8-6. S0 to S5 Timing Diagram Source Dest Signal Name PCH PCIe* Devices PCIe Ports PCH Board PLTRST# PCH Board PROCPWRGD CPU PCH DMI L2/L3 DMI Message normal operation L2/L3 t214 THRMTRIP# PCH Board SLP_S3# PCH Board SLP_S4# PCH Board SLP_S5# t217 honored ignored t218 t220 t221 t222 Board PCH PCH_PWROK Board PCH SYS_PWROK PCH CPU DRAMPWROK May drop before or after SLP_S4/5# and DRAMPWRGD Only switch if going to MOFF 308 Source of LANPHYPC value PCH GbE PHY PCH Board Board PCH APWROK PCH Board SLP_LAN# SLP_A# Live value from GbE MAC Value from MAC latched in SUS well If appropriate, save MAC PMCSR context here SLP_LAN# could stay high for M3 or W OL Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Electrical Characteristics Figure 8-7. S4/S5 to Deep S4/S5 to G3 w/ RTC Loss Timing Diagram S o u rce D e s tin a t io n S ig n a l N a m e D e e p S 4 /S 5 S 4 /S 5 PCH B o a rd (E C ) G3 SUSW ARN# u n d r iv e n u n d r iv e n B o a rd (E C ) PCH SUSACK# PCH B o a rd SLP_SU S # PCH B o a rd SLP_S3# / SLP_S4# / SLP_A# PCH B o a rd SLP_S5# u n d r iv e n u n d r iv e n S L P _ S 5 # d r o p s h e r e if n o t a lr e a d y a s s e r te d B o a rd PCH RSMRST# B o a rd PCH V ccS us B o a rd PCH DPW ROK B o a rd PCH VccD SW B o a rd PCH RTCRST# B o a rd PCH V ccR TC t2 3 5 t2 3 4 t2 3 6 Figure 8-8. DRAMPWROK Timing Diagram S o u rc e D estin atio n S ig n al N am e PCH B oard S LP_S4# B oa rd PCH PW ROK PCH CPU DRAM PW ROK 8.8 AC Timing Diagrams Figure 8-9. Clock Cycle Time Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet t22 3 t2 24 309 Electrical Characteristics Figure 8-10. Transmitting Position (Data to Strobe) CLKA/ CLKB Tppos0 YA/YB Tppos1 Tppos2 Tppos3 Tppos4 Tppos5 Tppos6 Figure 8-11. Clock Timing Period High Time 2.0V 0.8V Low Time Fall Time Rise Time Figure 8-12. Valid Delay from Rising Clock Edge Clock 1.5V Valid Delay Output 310 VT Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Electrical Characteristics Figure 8-13. Setup and Hold Times 1.5V Clock Setup Time Input Hold Time VT VT Figure 8-14. Float Delay Input VT Float Delay Output Figure 8-15. Pulse Width Pulse Width VT VT Figure 8-16. Output Enable Delay Clock 1.5V Output Enable Delay Output Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet VT 311 Electrical Characteristics Figure 8-17. USB Rise and Fall Times 312 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Electrical Characteristics Figure 8-18. USB Jitter T period Crossover Points Differential Data Lines Jitter Consecutive Transitions Paired Transitions Figure 8-19. USB EOP Width Tperiod Data Crossover Level Differential Data Lines EOP Width Figure 8-20. SMBus/SMLink Transaction t19 t20 t21 SMBCLK t135 t131 t134 t133 t132 t18 SMBDATA t130 Note: txx also refers to txx_SM, txxx also refers to txxxSMLFM, SMBCLK also refers to SML[1:0]CLK, and SMBDATA also refers to SML[1:0]DATA in Figure 8-20. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 313 Electrical Characteristics Figure 8-21. SMBus/SMLink Timeout Start Stop t137 CLKack CLKack t138 t138 SMBCLK SMBDATA Note: SMBCLK also refers to SML[1:0]CLK and SMBDATA also refers to SML[1:0]DATA in Figure 8-21. Figure 8-22. SPI Timings t188 t189 SPI_CLK t183 SPI_MOSI t184 t185 SPI_MISO t186 t187 SPI_CS# 314 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Electrical Characteristics Figure 8-23. Intel(R) High Definition Audio Input and Output Timings HDA_BIT_CLK HDA_SDOUT t144 t143 t143 t144 HDA_SDIN[3:0] t145 t146 Figure 8-24. Transmitting Position (Data to Strobe) CLKA/ CLKB Tppos0 YA/YB Tppos1 Tppos2 Tppos3 Tppos4 Tppos5 Tppos6 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 315 Electrical Characteristics Figure 8-25. PCI Express* Transmitter Eye Figure 8-26. PCI Express* Receiver Eye VTS-Diff = 0mV D+/D- Crossing point VRS-Diffp-p-Min>175mV .4 UI =TRX-EYE min 316 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Electrical Characteristics Figure 8-27. Measurement Points for Differential Waveforms. Differential Clock - Single Ended Measurements V max = 1.15V V max = 1.15V Clock# Vcross max = 550mV Vcross max = 550mV Vcross min = 300 mV Vcross min = 300 mV Clock V min = -0.30V V min = -0.30V Clock# Vcross delta = 140mV Vcross delta = 140mV Clock Clock# Vcross median ll fa Vcross median T Vcross median +75mV Tr is e Clock# Vcross median -75mV Clock Clock Differential Clock - Differential Measurements Clock Period (Differential ) Positive Duty Cycle (Differential ) Negative Duty Cycle (Differential ) .0V Clock-Clock# Rise Edge Rate Fall Edge Rate Vih_min = +150 mV 0.0V Vil_max = -150 mV Clock-Clock# Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 317 Electrical Characteristics Figure 8-28. PCH Test Load VccSPI 318 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Register and Memory Mapping 9 Register and Memory Mapping The PCH contains registers that are located in the processor's I/O space and memory space and sets of PCI configuration registers that are located in PCI configuration space. This chapter describes the PCH I/O and memory maps at the register-set level. Register access is also described. Register-level address maps and Individual register bit descriptions are provided in the following chapters. The following notations and definitions are used in the register/instruction description chapters. RO Read Only. In some cases, if a register is read only, writes to this register location have no effect. However, in other cases, two separate registers are located at the same location where a read accesses one of the registers and a write accesses the other register. See the I/O and memory map tables for details. WO Write Only. In some cases, if a register is write only, reads to this register location have no effect. However, in other cases, two separate registers are located at the same location where a read accesses one of the registers and a write accesses the other register. See the I/O and memory map tables for details. R/W Read/Write. A register with this attribute can be read and written. R/WC Read/Write Clear. A register bit with this attribute can be read and written. However, a write of 1 clears (sets to 0) the corresponding bit and a write of 0 has no effect. R/WL Read/Write Lockable. A register bit with the attribute can be read at any time but writes may only occur if the associated lock bit is set to unlock. If the associated lock bit is set to lock, this register bit becomes RO unless otherwise indicated. R/WO Read/Write-Once. A register bit with this attribute can be written only once after power up. After the first write, the bit becomes read only. R/WLO Read/Write, Lock-Once. A register bit with this attribute can be written to the non-locked value multiple times, but to the locked value only once. After the locked value has been written, the bit becomes read only. R/W/SN Read/Write register initial value loaded from NVM Reserved The value of reserved bits must never be changed. For details see Section 9.2. Default When the PCH is reset, it sets its registers to predetermined default states. It is the responsibility of the system initialization software to determine configuration, operating parameters, and optional system features that are applicable, and to program the PCH registers accordingly. Bold Register bits that are highlighted in bold text indicate that the bit is implemented in the PCH. Register bits that are not implemented or are hardwired will remain in plain text. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 319 Register and Memory Mapping 9.1 PCI Devices and Functions The PCH incorporates a variety of PCI devices and functions, as shown in Table 9-1. The first is the PCI-To-PCI bridge (Device 30). The second device (Device 31) contains most of the standard PCI functions that always existed in the PCI-to-ISA bridges (South Bridges), such as the Intel(R) 82371AB PIIX4. The third and fourth (Device 29 and Device 26) are the USB and USB2 host controller devices. The fifth (Device 28) is PCI Express* device. The sixth (Device 27) is HD Audio controller device. The seventh (Device 25) is the Gigabit Ethernet controller device. The eighth device i(Device 22) is the Intel(R) Management Engine Interface (Intel(R) MEI). The ninth device (Device 17) is the Virtual Root Port. If for some reason, the particular system platform does not want to support any one of the Device Functions, with the exception of D30:F0 can individually be disabled. The integrated Gigabit Ethernet controller will be disabled if no Platform LAN Connect component is detected (See Chapter 5.4). When a function is disabled, it does not appear at all to the software. A disabled function will not respond to any register reads or writes, insuring that these devices appear hidden to software. Note: In the normal platform, M will equal 0. For some server platforms, it may be desirable to have multiple PCH's in the system which means some PCH's may reside on a bus greater than 0. Table 9-1. PCI Devices and Functions for all PCH SKUs Bus:Device:Function 320 Function Description Bus M:Device 30:Function 0 PCI-to-PCI Bridge Bus M:Device 31:Function 0 LPC Controller1 Bus M:Device 31:Function 2 SATA Controller #1 Bus M:Device 31:Function 3 SMBus Controller Bus M:Device 31:Function 5 SATA Controller #22 Bus M:Device 31:Function 6 Thermal Subsystem Bus M:Device 29:Function 0 USB EHCI Controller #13 Bus M:Device 26:Function 0 USB EHCI Controller #23 Bus M:Device 28:Function 0 PCI Express* Port 14 Bus M:Device 28:Function 1 PCI Express* Port 24 Bus M:Device 28:Function 2 PCI Express* Port 34 Bus M:Device 28:Function 3 PCI Express* Port 44 Bus M:Device 28:Function 4 PCI Express* Port 54 Bus M:Device 28:Function 5 PCI Express* Port 64 Bus M:Device 28:Function 6 PCI Express* Port 74 Bus M:Device 28:Function 7 PCI Express* Port 84 Bus M:Device 27:Function 0 Intel HD Audio Controller Bus M:Device 25:Function 0 Gigabit Ethernet Controller Bus M:Device 22:Function 0 Host Embedded Controller Interface #1 Bus M:Device 22:Function 1 Host Embedded Controller Interface #2 Bus M:Device 22:Function 2 IDE-R Bus M:Device 22:Function 3 KT Bus X:Device 0:Function 0 SCU 0 Bus X:Device 0:Function 1 IDF Bus X:Device 0:Function 3 SMB 0 (Associate with SCU0) Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Register and Memory Mapping Notes: 1. The PCI-to-LPC bridge contains registers that control LPC, Power Management, System Management, GPIO, Processor Interface, RTC, Interrupts, Timers, and DMA. 2. SATA controller 2 (D31:F5) is only visible when D31:F2 CC.SCC=01h. 3. Prior to BIOS initialization of the PCH USB subsystem, the EHCI controllers will appear as Function 7. After BIOS initialization, the EHCI controllers will be Function 0. 4. This section assumes the default PCI Express* Function Number-to-Root Port mapping is used. Function numbers for a given root port are assignable through the "Root Port Function Number and Hide for PCI Express* Root Ports" registers (RCBA+0404h). Table 9-2. PCI Devices and Functions for PCH Intel(R) C602, C602J, C604 Chipset and Intel(R) X79 Express Chipset SKUs Bus:Device:Function Bus M: Device 17: Function 0 Table 9-3. Function Description PCIe Virtual Root Port Additional PCI Devices and Functions for Intel(R) C606, C608 Chipset SKUs Bus:Device:Function Function Description Bus N: Device 0: Function 0 PCIe Upstream Port Bus N+1: Device 8: Function 0 PCIe Virtual Switch Port Bus X:Device 0:Function 4 SMB 1(Associate with SCU1) Notes: 1. X is a value greater than N+1 assigned by the BIOS. 2. Intel(R) C606, C608 Chipset SKU can be configured using soft strap to route SCU traffic to DMI link. In such case, virtual root port (D17:F0) will be used in place of PCIe Upstream port and virtual switch port. Table 9-4. Additional PCI Devices and Functions for Intel(R) C608 Chipset SKU Bus:Device:Function Bus X:Device 0:Function 5 9.2 Function Description SMB 2 PCI Configuration Map Each PCI function on the PCH has a set of PCI configuration registers. The register address map tables for these register sets are included at the beginning of the chapter for the particular function. Configuration Space registers are accessed through configuration cycles on the PCI bus by the Host bridge using configuration mechanism #1 detailed in the PCI Local Bus Specification. Some of the PCI registers contain reserved bits. Software must deal correctly with fields that are reserved. On reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On writes, software must ensure that the values of reserved bit positions are preserved. That is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. Note the software does not need to perform read, merge, write operation for the configuration address register. In addition to reserved bits within a register, the configuration space contains reserved locations. Software should not write to reserved PCI configuration locations in the device-specific region (above address offset 3Fh). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 321 Register and Memory Mapping 9.3 I/O Map The I/O map is divided into Fixed and Variable address ranges. Fixed ranges cannot be moved, but in some cases can be disabled. Variable ranges can be moved and can also be disabled. 9.3.1 Fixed I/O Address Ranges Table 9-5 shows the Fixed I/O decode ranges from the processor perspective. Note that for each I/O range, there may be separate behavior for reads and writes. DMI (Direct Media Interface) cycles that go to target ranges that are marked as "Reserved" will not be decoded by the PCH, and will be passed to PCI unless the Subtractive Decode Policy bit is set (D31:F0:Offset 42h, bit 0). If a PCI master targets one of the fixed I/O target ranges, it will be positively decoded by the PCH in medium speed. Address ranges that are not listed or marked "Reserved" are not decoded by the PCH (unless assigned to one of the variable ranges). Table 9-5. 322 Fixed I/O Ranges Decoded by PCH (Sheet 1 of 2) I/O Address Read Target Write Target Internal Unit 00h-08h DMA Controller DMA Controller DMA 09h-0Eh RESERVED DMA Controller DMA 0Fh DMA Controller DMA Controller DMA 10h-18h DMA Controller DMA Controller DMA 19h-1Eh RESERVED DMA Controller DMA 1Fh DMA Controller DMA Controller DMA 20h-21h Interrupt Controller Interrupt Controller Interrupt 24h-25h Interrupt Controller Interrupt Controller Interrupt 28h-29h Interrupt Controller Interrupt Controller Interrupt 2Ch-2Dh Interrupt Controller Interrupt Controller Interrupt 2E-2F LPC SIO LPC SIO Forwarded to LPC 30h-31h Interrupt Controller Interrupt Controller Interrupt 34h-35h Interrupt Controller Interrupt Controller Interrupt 38h-39h Interrupt Controller Interrupt Controller Interrupt 3Ch-3Dh Interrupt Controller Interrupt Controller Interrupt 40h-42h Timer/Counter Timer/Counter PIT (8254) 43h RESERVED Timer/Counter PIT 4E-4F LPC SIO LPC SIO Forwarded to LPC 50h-52h Timer/Counter Timer/Counter PIT 53h RESERVED Timer/Counter PIT 60h Microcontroller Microcontroller Forwarded to LPC 61h NMI Controller NMI Controller Processor I/F 62h Microcontroller Microcontroller Forwarded to LPC 64h Microcontroller Microcontroller Forwarded to LPC 66h Microcontroller Microcontroller Forwarded to LPC 70h RESERVED1 NMI and RTC Controller RTC 71h RTC Controller RTC Controller RTC 72h RTC Controller NMI and RTC Controller RTC Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Register and Memory Mapping Table 9-5. Fixed I/O Ranges Decoded by PCH (Sheet 2 of 2) I/O Address Read Target Write Target Internal Unit 73h 74h RTC Controller RTC Controller RTC RTC Controller NMI and RTC Controller RTC 75h 76h RTC Controller RTC Controller RTC RTC Controller NMI and RTC Controller RTC 77h RTC Controller RTC Controller RTC 80h DMA Controller, LPC, PCI, or PCIe DMA Controller and LPC, PCI, or PCIe DMA 81h-83h DMA Controller DMA Controller DMA 84h-86h DMA Controller DMA Controller and LPC, PCI, or PCIe DMA 87h DMA Controller DMA Controller DMA 88h DMA Controller DMA Controller and LPC or PCI, or PCIe DMA 89h-8Bh DMA Controller DMA Controller DMA 8Ch-8Eh DMA Controller DMA Controller and LPC or PCI, or PCIe DMA 08Fh DMA Controller DMA Controller DMA 90h-91h DMA Controller DMA Controller DMA 92h Reset Generator Reset Generator Processor I/F 93h-9Fh DMA Controller DMA Controller DMA A0h-A1h Interrupt Controller Interrupt Controller Interrupt A4h-A5h Interrupt Controller Interrupt Controller Interrupt A8h-A9h Interrupt Controller Interrupt Controller Interrupt ACh-ADh Interrupt Controller Interrupt Controller Interrupt B0h-B1h Interrupt Controller Interrupt Controller Interrupt B2h-B3h Power Management Power Management Power Management B4h-B5h Interrupt Controller Interrupt Controller Interrupt B8h-B9h Interrupt Controller Interrupt Controller Interrupt BCh-BDh Interrupt Controller Interrupt Controller Interrupt C0h-D1h DMA Controller DMA Controller DMA D2h-DDh RESERVED DMA Controller DMA DEh-DFh DMA Controller DMA Controller DMA F0h FERR# / Interrupt Controller FERR# / Interrupt Controller Processor I/F 170h-177h SATA Controller, PCI, or PCIe SATA Controller, PCI, or PCIe Forwarded to SATA 1F0h-1F7h SATA Controller, PCI, or PCIe SATA Controller, PCI, or PCIe Forwarded to SATA 200h-207h Gameport Low Gameport Low Forwarded to LPC 208h-20Fh Gameport High Gameport High 376h SATA Controller, PCI, or PCIe SATA Controller, PCI, or PCIe Forwarded to SATA Forwarded to LPC Forwarded to SATA 3F6h SATA Controller, PCI, or PCIe SATA Controller, PCI, or PCIeI 4D0h-4D1h Interrupt Controller Interrupt Controller Interrupt CF9h Reset Generator Reset Generator Processor I/F Note: 1. See Section 13.7.2. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 323 Register and Memory Mapping 9.3.2 Variable I/O Decode Ranges Table 9-6 shows the Variable I/O Decode Ranges. They are set using Base Address Registers (BARs) or other configuration bits in the various PCI configuration spaces. The PNP software (PCI or ACPI) can use their configuration mechanisms to set and adjust these values. Warning: The Variable I/O Ranges should not be set to conflict with the Fixed I/O Ranges. Unpredictable results if the configuration software allows conflicts to occur. The PCH does not perform any checks for conflicts. Table 9-6. Variable I/O Decode Ranges Range Name ACPI Size (Bytes) Mappable Target Anywhere in 64 KB I/O Space 64 Power Management Anywhere in 64 KB I/O Space 1. 16 or 32 2. 16 1. SATA Host Controller #1, #2 2. IDE-R (SRV/WS SKUs Only) Native IDE Command Anywhere in 64 KB I/O Space1 8 1. SATA Host Controller #1, #2 2. IDE-R (SRV/WS SKUs Only) Native IDE Control Anywhere in 64 KB I/O Space1 4 1. SATA Host Controller #1, #2 2. IDE-R (SRV/WS SKUs Only) Anywhere in 64 KB I/O Space 32 SMB Unit 96 Bytes above ACPI Base 32 TCO Unit SATA Index/Data Pair Anywhere in 64 KB I/O Space 16 SATA Host Controller #1, #2 GPIO Anywhere in 64 KB I/O Space 128 GPIO Unit Parallel Port 3 Ranges in 64 KB I/O Space 83 LPC Peripheral Serial Port 1 8 Ranges in 64 KB I/O Space 8 LPC Peripheral Serial Port 2 8 Ranges in 64 KB I/O Space 8 LPC Peripheral IDE Bus Master SMBus TCO Floppy Disk Controller 2 Ranges in 64 KB I/O Space 8 LPC Peripheral LAN Anywhere in 64 KB I/O Space 322 LAN Unit LPC Generic 1 Anywhere in 64 KB I/O Space 4 to 256 LPC Peripheral LPC Generic 2 Anywhere in 64 KB I/O Space 4 to 256 LPC Peripheral LPC Generic 3 Anywhere in 64 KB I/O Space 4 to 256 LPC Peripheral LPC Generic 4 Anywhere in 64 KB I/O Space 4 to 256 LPC Peripheral I/O Trapping Ranges Anywhere in 64 KB I/O Space 1 to 256 Trap on Backbone PCI Bridge Anywhere in 64 KB I/O Space I/O Base/ Limit PCI Bridge PCI Express* Root Ports Anywhere in 64 KB I/O Space I/O Base/ Limit PCI Express* Root Ports 1-8 KT Anywhere in 64 KB I/O Space 8 KT Notes: 1. All ranges are decoded directly from DMI. The I/O cycles will not be seen on PCI, except the range associated with PCI bridge. 2. The LAN range is typically not used, as the registers can also be accessed using a memory space. 3. There is also an alias 400h above the parallel port range that is used for ECP parallel ports. 324 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Register and Memory Mapping 9.4 Memory Map Table 9-7 shows (from the processor perspective) the memory ranges that the PCH decodes. Cycles that arrive from DMI that are not directed to any of the internal memory targets that decode directly from DMI will be driven out on PCI unless the Subtractive Decode Policy bit is set (D31:F0:Offset 42h, bit 0). PCI cycles generated by external PCI masters will be positively decoded unless they fall in the PCI-to-PCI bridge memory forwarding ranges (those addresses are reserved for PCI peer-to-peer traffic). If the cycle is not in the internal LAN controller's range, it will be forwarded up to DMI. Software must not attempt locks to the PCH's memorymapped I/O ranges for EHCI and HPET. If attempted, the lock is not honored which means potential deadlock conditions may occur. Table 9-7. Memory Decode Ranges from Processor Perspective (Sheet 1 of 2) Memory Range Target 0000 0000h-000D FFFFh 0010 0000h-TOM (Top of Memory) Main Memory Dependency/Comments TOM registers in Host controller 000E 0000h-000E FFFFh LPC or SPI Bit 6 in BIOS Decode Enable register is set 000F 0000h-000F FFFFh LPC or SPI Bit 7 in BIOS Decode Enable register is set FEC_ _000h-FEC_ _040h IO(x) APIC inside PCH FEC1 0000h-FEC1 7FFF PCI Express* Port 1 _ _is controlled using APIC Range Select (ASEL) field and APIC Enable (AEN) bit PCI Express* Root Port 1 I/OxAPIC Enable (PAE) set FEC1 8000h-FEC1 FFFFh PCI Express* Port 2 PCI Express* Root Port 2 I/OxAPIC Enable (PAE) set FEC2 0000h-FEC2 7FFFh PCI Express* Port 3 PCI Express* Root Port 3 I/OxAPIC Enable (PAE) set FEC2 8000h-FEC2 FFFFh PCI Express* Port 4 PCI Express* Root Port 4 I/OxAPIC Enable (PAE) set FEC3 0000h-FEC3 7FFFh PCI Express* Port 5 PCI Express* Root Port 5 I/OxAPIC Enable (PAE) set FEC3 8000h-FEC3 FFFFh PCI Express* Port 6 PCI Express* Root Port 6 I/OxAPIC Enable (PAE) set FEC4 0000 - FEC4 7FFF PCI Express* Port 7 PCI Express* Root Port 7I/OxAPIC Enable (PAE) set FEC4 8000 - FEC4 FFFF PCI Express* Port 8 PCI Express* Root Port 8I/OxAPIC Enable (PAE) set If Intel TPM is enabled, FED4_0000h - FED4_7FFFh goes to Intel TPM. If disabled, the entire range goes to LPC. FED4 0000h-FED4 BFFFh TPM on LPC FFC0 0000h-FFC7 FFFFh FF80 0000h-FF87 FFFFh LPC or SPI (or PCI)2 Bit 8 in BIOS Decode Enable register is set FFC8 0000h-FFCF FFFFh FF88 0000h-FF8F FFFFh LPC or SPI (or PCI)2 Bit 9 in BIOS Decode Enable register is set FFD0 0000h-FFD7 FFFFh FF90 0000h-FF97 FFFFh LPC or SPI (or PCI)2 Bit 10 in BIOS Decode Enable register is set FFD8 0000h-FFDF FFFFh FF98 0000h-FF9F FFFFh LPC or SPI (or PCI)2 Bit 11 in BIOS Decode Enable register is set FFE0 000h-FFE7 FFFFh FFA0 0000h-FFA7 FFFFh LPC or SPI (or PCI)2 Bit 12 in BIOS Decode Enable register is set FFE8 0000h-FFEF FFFFh FFA8 0000h-FFAF FFFFh LPC or SPI (or PCI)3 Bit 13 in BIOS Decode Enable register is set FFF0 0000h-FFF7 FFFFh FFB0 0000h-FFB7 FFFFh LPC or SPI (or PCI)2 Bit 14 in BIOS Decode Enable register is set FFF8 0000h-FFFF FFFFh FFB8 0000h-FFBF FFFFh LPC or SPI (or PCI)2 Always enabled. The top two, 64 KB blocks of this range can be swapped, as described in Section 9.4.1. FF70 0000h-FF7F FFFFh FF30 0000h-FF3F FFFFh LPC or SPI (or PCI)2 Bit 3 in BIOS Decode Enable register is set FF60 0000h-FF6F FFFFh FF20 0000h-FF2F FFFFh LPC or SPI (or PCI)2 Bit 2 in BIOS Decode Enable register is set Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 325 Register and Memory Mapping Table 9-7. Memory Decode Ranges from Processor Perspective (Sheet 2 of 2) Memory Range Target FF50 0000h-FF5F FFFFh FF10 0000h-FF1F FFFFh Dependency/Comments LPC or SPI (or PCI)2 Bit 1 in BIOS Decode Enable register is set FF40 0000h-FF4F FFFFh FF00 0000h-FF0F FFFFh LPC or SPI (or PCI)2 Bit 0 in BIOS Decode Enable register is set 128 KB anywhere in 4-GB range Integrated LAN Controller Enable using BAR in Device 25:Function 0 (Integrated LAN Controller MBARA) 4 KB anywhere in 4 GB range Integrated LAN Controller Enable using BAR in Device 25:Function 0 (Integrated LAN Controller MBARB) 1 KB anywhere in 4-GB range USB EHCI Controller #11 Enable using standard PCI mechanism (Device 29, Function 0) 1 KB anywhere in 4-GB range USB EHCI Controller #21 Enable using standard PCI mechanism (Device 26, Function 0) FED4 0000h-FED4 FFFFh TPM on LPC None Memory Base/Limit anywhere in 4 GB range PCI Bridge Enable using standard PCI mechanism (Device 30: Function 0) Prefetchable Memory Base/ Limit anywhere in 64-bit address range PCI Bridge Enable using standard PCI mechanism (Device 30: Function 0) 64 KB anywhere in 4 GB range LPC LPC Generic Memory Range. Enable using setting bit[0] of the LPC Generic Memory Range register (D31:F0:offset 98h). 32 Bytes anywhere in 64-bit address range SMBus Enable using standard PCI mechanism (Device 31: Function 3) 2 KB anywhere above 64 KB to 4 GB range SATA Host Controller #1 AHCI memory-mapped registers. Enable using standard PCI mechanism (Device 31: Function 2) Memory Base/Limit anywhere in 4 GB range PCI Express* Root Ports 1-8 Enable using standard PCI mechanism (Device 28: Function 0-7) Prefetchable Memory Base/ Limit anywhere in 64-bit address range PCI Express* Root Ports 1-8 Enable using standard PCI mechanism (Device 28: Function 0-7) 4 KB anywhere in 64-bit address range Thermal Reporting Enable using standard PCI mechanism (Device 31: Function 6 TBAR/TBARH) 4 KB anywhere in 64-bit address range Thermal Reporting Enable using standard PCI mechanism (Device 31: Function 6 TBARB/TBARBH) 16 Bytes anywhere in 64-bit address range Intel(R) Management Engine Interface (Intel(R) MEI) #1, #2 Enable using standard PCI mechanism (Device 22: Function 1:0) 4 KB anywhere in 4 GB range KT Enable using standard PCI mechanism (Device 22: Function 3) 16 KB anywhere in 4 GB range Root Complex Register Block (RCRB) 512 B anywhere in 64-bit addressing space Enable using setting bit[0] of the Root Complex Base Address register (D31:F0:offset F0h). Intel HD Audio Host Controller Enable using standard PCI mechanism (Device 27, Function 0) FED0 X000h-FED0 X3FFh High Precision Event Timers 1 BIOS determines the "fixed" location which is one of four, 1KB ranges where X (in the first column) is 0h, 1h, 2h, or 3h. All other PCI None Notes: 1. Software must not attempt locks to memory mapped I/O ranges for USB EHCI or High Precision Event Timers. If attempted, the lock is not honored, which means potential deadlock conditions may occur. 2. PCI is the target when the Boot BIOS Destination selection bits are set to 10b (Chipset Config Registers:Offset 3401 bits 11:10). When PCI selected, the Firmware Hub Decode Enable bits have no effect. 326 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Register and Memory Mapping 9.4.1 Boot-Block Update Scheme The PCH supports a "top-block swap" mode that has the PCH swap the top block in the FWH or SPI flash (the boot block) with another location. This allows for safe update of the Boot Block (even if a power failure occurs). When the "TOP_SWAP" Enable bit is set, the PCH will invert A16 for cycles going to the upper two 64 KB blocks in the FWH or appropriate address lines as selected in Boot Block Size (BIOS Boot-Block size) soft strap for SPI. Specifically for FHW, in this mode accesses to FFFF_0000h-FFFF_FFFFh are directed to FFFE_0000h-FFFE_FFFFh and vice versa. When the Top Swap Enable bit is 0, the PCH will not invert A16. Specifically for SPI, in this mode the "Top-Block Swap" behavior is as described below. When the Top Swap Enable bit is 0, the PCH will not invert any address bit. Table 9-8. SPI Mode Address Swapping BIOS Boot-Block Size Value 000 (64 KB) Accesses to FFFF_0000h - FFFF_FFFFh Being Directed to FFFE_0000h - FFFE_FFFFh and vice versa 001 (128 KB) FFFE_0000h - FFFF_FFFFh FFFC_0000h - FFFD_FFFFh and vice versa 010 (256 KB) FFFC_0000h - FFFF_FFFFh FFF8_0000h - FFFB_FFFFh and vice versa 011 (512 KB) FFF8_0000h - FFFF_FFFFh FFF0_0000h - FFF7_FFFFh and vice versa 100 (1 MB) FFF0_0000h - FFFF_FFFFh FFE0_0000h - FFEF_FFFFh and vice versa 101 - 111 Reserved Reserved This bit is automatically set to 0 by RTCRST#, but not by PLTRST#. The scheme is based on the concept that the top block is reserved as the "boot" block, and the block immediately below the top block is reserved for doing boot-block updates. The algorithm is: 1. Software copies the top block to the block immediately below the top. 2. Software checks that the copied block is correct. This could be done by performing a checksum calculation. 3. Software sets the TOP_SWAP bit. This will invert the appropriate address bits for the cycles going to the FWH or SPI. 4. Software erases the top block. 5. Software writes the new top block. 6. Software checks the new top block. 7. Software clears the TOP_SWAP bit. 8. Software sets the Top_Swap Lock-Down bit. If a power failure occurs at any point after step 3, the system will be able to boot from the copy of the boot block that is stored in the block below the top. This is because the TOP_SWAP bit is backed in the RTC well. Note: The top-block swap mode may be forced by an external strapping option. When topblock swap mode is forced in this manner, the TOP_SWAP bit cannot be cleared by software. A re-boot with the strap removed will be required to exit a forced top-block swap mode. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 327 Register and Memory Mapping Note: Top-block swap mode only affects accesses to the Firmware Hub space, not feature space for FWH. Note: The top-block swap mode has no effect on accesses below FFFE_0000h for FWH. 328 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Chipset Configuration Registers 10 Chipset Configuration Registers This section describes all registers and base functionality that is related to chipset configuration and not a specific interface (such as LPC, PCI, or PCI Express). It contains the root complex register block, which describes the behavior of the upstream internal link. This block is mapped into memory space, using the Root Complex Base Address (RCBA) register of the PCI-to-LPC bridge. Accesses in this space must be limited to 32-(DW) bit quantities. Burst accesses are not allowed. All chipset configuration registers are located in the core well unless otherwise indicated. 10.1 Chipset Configuration Registers (Memory Space) Note: Address locations that are not shown should be treated as Reserved (see Section 9.2 for details). Table 10-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 1 of 2) Offset Mnemonic Register Name 0050-0053h CIR0 Chipset Initialization Register 0 00000000h R/WL 0400-0403h RPC Root Port Configuration 0000000yh R/W, RO 0404-0407h RPFN Root Port Function Number for PCI Express* Root Ports 76543210h R/WO, RO 0408-040Bh FLRSTAT Function Level Reset Pending Status Summary 00000000h RO 00000000h R/WC, RO 0000000000000000h RO 1E00-1E03h TRSR Trap Status Register 1E10-1E17h TRCR Trapped Cycle Register Default Type 1E18-1E1Fh TWDR Trapped Write Data Register 0000000000000000h RO 1E80-1E87h IOTR0 I/O Trap Register 0 0000000000000000h R/W 1E88-1E8Fh IOTR1 I/O Trap Register 1 0000000000000000h R/W 1E90-1E97h IOTR2 I/O Trap Register 2 0000000000000000h R/W 1E98-1E9Fh IOTR3 I/O Trap Register 3 0000000000000000h R/W 2014-2017h V0CTL VC 0 Resource Control 800000FFh R/WL, RO 201A-201Bh V0STS VC 0 Resource Status 0000h RO 00000000h R/W, RO, R/WL 2020-2023h V1CTL VC 1 Resource Control 2026-2027h V1STS VC 1 Resource Status 0000h RO 20AC-20AFh REC Root Error Command 0000h R/W 21A4-21A7h LCAP Link Capabilities 00012C42h RO, R/ WO 21A8-21A9h LCTL Link Control 0000h R/W Link Status 0042h RO DMI Link Control 2 0000h R/W, RO 21AA-21ABh LSTS 21B0-21B1h DLCTL2 2234-2237h DMIC DMI Control 00000000h R/W, RO 3000-3000h TCTL TCO Control 00h R/W 3100-3103h D31IP 03243200h R/W, RO Device 31 Interrupt Pin Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 329 Chipset Configuration Registers Table 10-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 2 of 2) Offset 330 Mnemonic Register Name Default Type 3104-3107h D30IP Device 30 Interrupt Pin 00000000h RO 3108-310Bh D29IP Device 29 Interrupt Pin 10004321h R/W 310C-310Fh D28IP Device 28 Interrupt Pin 00214321h R/W 3110-3113h D27IP Device 27 Interrupt Pin 00000001h R/W 3114-3117h D26IP Device 26 Interrupt Pin 30000321h R/W 3118-311Bh D25IP Device 25 Interrupt Pin 00000001h R/W 311C-311Fh D24IP Device 24 Interrupt Pin 00000001h R/W 3124-3127h D22IP Device 22 Interrupt Pin 00004321h R/W 3140-3141h D31IR Device 31 Interrupt Route 3210h R/W 3144-3145h D29IR Device 29 Interrupt Route 3210h R/W 3146-3147h D28IR Device 28 Interrupt Route 3210h R/W 3148-3149h D27IR Device 27 Interrupt Route 3210h R/W 314C-314Fh D26IR Device 26 Interrupt Route 3210h R/W 3150-3153h D25IR Device 25 Interrupt Route 3210h R/W 3154-3157h D24IR Device 24 Interrupt Route 3210h R/W 315C-316Fh D22IR Device 22 Interrupt Route 3210h R/W 31FE-31FFh OIC Other Interrupt Control 0000h R/W 3310-3313h PRSTS Power and Reset Status 03000000h RO, R/WC 3318-331Bh PM_CFG Power Management Configuration 00000000h R/W 332C-332Fh DEEP_S4_POL Deep S4 Power Policies 00000000h R/W 3330-3333h DEEP_S5_POL Deep S5 Power Policies 00000000h R/W R/W, R/WLO 3400-3403h RC RTC Configuration 00000000h 3404-3407h HPTC High Precision Timer Configuration 00000000h R/W 000000yy0h R/W, R/WLO 3410-3413h GCS General Control and Status 3414-3414h BUC Backed Up Control 00h R/W 3418-341Bh FD Function Disable 00000000h R/W 341C-341Fh CG Clock Gating 00000000h R/W 3420-3420h FDSW Function Disable SUS Well 00h R/W 3428-342Bh FD2 Function Disable 2 00000000h R/W 3450-3453h GSXBAR GPIO Serial Expander Base Address 00000000h R/W, RO 3454-3457h GSXCTRL GPIO Serial Expander Control Register 0000000h R/W, RO 3590-3593h MISCCTL Miscellaneous Control Register 00000000h R/W 3598-3599h USBIRE USB Initialization Register E 0000h R/W 35A4-35A7h USBOCM2 USB Overcurrent MAP Register 2 00000000h R/WO 35B0-35B3h RMHWKCTL USB Remap Control 00000000h R/WO Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Chipset Configuration Registers 10.1.1 CIR0--Chipset Initialization Register 0 Offset Address: 0050-0053h Default Value: 00000000h Bit R/WL 32-bit Description 31 30:0 10.1.2 Attribute: Size: TC Lock-Down (TCLOCKDN)-- R/WL. When set to 1, certain DMI configuration registers are locked down by this and cannot be written. Once set to 1, this bit can only be cleared by a PLTRST#. CIR0 Field 0-- R/WL. BIOS must set this field. Bits locked by TCLOCKDN. RPC--Root Port Configuration Register Offset Address: 0400-0403h Default Value: 0000000yh (y = 00xxb) Bit 31:12 11 10:8 Attribute: Size: R/W, RO 32-bit Description Reserved GbE Over PCIe Root Port Enable (GBEPCIERPEN) -- R/W. 0 = GbE MAC/PHY communication is not enabled over PCI Express. 1 = The PCI Express* port selected by the GBEPCIEPORTSEL register will be used for GbE MAC/ PHY over PCI Express* communication The default value for this register is set by the GBE_PCIE_EN soft strap. Note: GbE and PCIe will use the output of this register and not the soft strap. GbE Over PCIe Root Port Select (GBEPCIERPSEL) -- R/W. If the GBEPCIERPEN is a `1', then this register determines which port is used for GbE MAC/PHY communication over PCI Express. This register is set by soft strap and is writable to support separate PHY on motherboard and docking station. 111 = Port 8 (Lane 7) 110 = Port 7 (Lane 6) 101 = Port 6 (Lane 5) 100 = Port 5 (Lane 4) 011 = Port 4 (Lane 3) 010 = Port 3 (Lane 2) 001 = Port 2 (Lane 1) 000 = Port 1 (Lane 0) The default value for this register is set by the GBE_PCIEPORTSEL[2:0] soft strap. Note: GbE and PCIe will use the output of this register and not the soft strap. 7:4 Reserved 3:2 Port Configuration2 (PC2) -- RO. This controls how the PCI bridges are organized in various modes of operation for Ports 5-8. For the following mappings, if a port is not shown, it is considered a x1 port with no connection. This bit is set by the PCIEPCS2[1:0] soft strap. 11 = 1 x4, Port 5(x4) 10 = 2x2, Port 5 (x2) Port 7 (x7) 01 = 1x2 and 2x1s, Port 5 (x2), Port 7(x1) and Port 8(x1) 00 = 4 x1s, Port 5(x1), Port 6(x1), Port 7(x1) and Port 8(x1) 1:0 Port Configuration (PC) -- RO. This controls how the PCI bridges are organized in various modes of operation for Ports 1-4. For the following mappings, if a port is not shown, it is considered a x1 port with no connection. These bits are set by the PCIEPCS1[1:0] soft strap. 11 = 1 x4, Port 1 (x4) 10 = 2x2, Port 1 (x2, Port 3 (x2) 01 = 1x2 and 2x1s, Port 1 (x2), Port 3 (x1) and Port 4 (x1) 00 = 4 x1s, Port 1 (x1), Port 2 (x1), Port 3 (x1) and Port 4 (x1) Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 331 Chipset Configuration Registers 10.1.3 RPFN--Root Port Function Number and Hide for PCI Express* Root Ports Offset Address: 0404-0407h Default Value: 76543210h Attribute: Size: R/WO, RO 32-bit For the PCI Express* root ports, the assignment of a function number to a root port is not fixed. BIOS may re-assign the function numbers on a port by port basis. This capability will allow BIOS to disable/hide any root port and still have functions 0 through N-1 where N is the total number of enabled root ports. Port numbers will remain fixed to a physical root port. The existing root port Function Disable registers operate on physical ports (not functions). Port Configuration (1x4, 4x1, and so forth) is not affected by the logical function number assignment and is associated with physical ports. Bit 31 30:28 27 26:24 23 22:20 19 18:16 15 14:12 11 10:8 7 332 Description Root Port 8 Config Hide (RP8CH) -- R/W. This bit is used to hide the root port and any devices behind it from being discovered by the OS. When set to `1' the root port will not claim any downstream configuration transactions. Root Port 8 Function Number (RP8FN) -- R/WO. These bits set the function number for PCI Express* Root Port 8. This root port function number must be a unique value from the other root port function numbers Root Port 7 Config Hide (RP7CH) -- R/W. This bit is used to hide the root port and any devices behind it from being discovered by the OS. When set to `1' the root port will not claim any downstream configuration transactions. Root Port 7 Function Number (RP7FN) -- R/WO. These bits set the function number for PCI Express* Root Port 7. This root port function number must be a unique value from the other root port function numbers Root Port 6 Config Hide (RP6CH) -- R/W. This bit is used to hide the root port and any devices behind it from being discovered by the OS. When set to `1' the root port will not claim any downstream configuration transactions. Root Port 6 Function Number (RP6FN) -- R/WO. These bits set the function number for PCI Express* Root Port 6. This root port function number must be a unique value from the other root port function numbers Root Port 5 Config Hide (RP5CH) -- R/W. This bit is used to hide the root port and any devices behind it from being discovered by the OS. When set to `1' the root port will not claim any downstream configuration transactions. Root Port 5 Function Number (RP5FN) -- R/WO. These bits set the function number for PCI Express* Root Port 5. This root port function number must be a unique value from the other root port function numbers Root Port 4 Config Hide (RP4CH) -- R/W. This bit is used to hide the root port and any devices behind it from being discovered by the OS. When set to `1' the root port will not claim any downstream configuration transactions. Root Port 4 Function Number (RP4FN) -- R/WO. These bits set the function number for PCI Express* Root Port 4. This root port function number must be a unique value from the other root port function numbers Root Port 3 Config Hide (RP3CH) -- R/W. This bit is used to hide the root port and any devices behind it from being discovered by the OS. When set to `1' the root port will not claim any downstream configuration transactions. Root Port 3 Function Number (RP3FN) -- R/WO. These bits set the function number for PCI Express* Root Port 3. This root port function number must be a unique value from the other root port function numbers Root Port 2 Config Hide (RP2CH) -- R/W. This bit is used to hide the root port and any devices behind it from being discovered by the OS. When set to `1' the root port will not claim any downstream configuration transactions. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Chipset Configuration Registers Bit Description 6:4 Root Port 2 Function Number (RP2FN) -- R/WO. These bits set the function number for PCI Express* Root Port 2. This root port function number must be a unique value from the other root port function numbers 3 2:0 10.1.4 Root Port 1 Config Hide (RP1CH) -- R/W. This bit is used to hide the root port and any devices behind it from being discovered by the OS. When set to `1' the root port will not claim any downstream configuration transactions. Root Port 1 Function Number (RP1FN) -- R/WO. These bits set the function number for PCI Express* Root Port 1. This root port function number must be a unique value from the other root port function numbers FLRSTAT--FLR Pending Status Register Offset Address: 0408-040Bh Default Value: 00000000h Bit 31:24 23 22:16 15 14:0 Attribute: Size: RO 32-bit Description Reserved. FLR Pending Status for D29:F0, EHCI #1 -- R0. 0 = Function Level Reset is not pending. 1 = Function Level Reset is pending. Reserved FLR Pending Status for D26:F0, EHCI#2 -- R0. 0 = Function Level Reset is not pending. 1 = Function Level Reset is pending. Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 333 Chipset Configuration Registers 10.1.5 TRSR--Trap Status Register Offset Address: 1E00-1E03h Default Value: 00000000h Bit 31:4 3:0 10.1.6 Attribute: Size: R/WC, RO 32-bit Description Reserved Cycle Trap SMI# Status (CTSS) -- R/WC. These bits are set by hardware when the corresponding Cycle Trap register is enabled and a matching cycle is received (and trapped). These bits are OR'ed together to create a single status bit in the Power Management register space. Note that the SMI# and trapping must be enabled in order to set these bits. These bits are set before the completion is generated for the trapped cycle, thereby ensuring that the processor can enter the SMI# handler when the instruction completes. Each status bit is cleared by writing a 1 to the corresponding bit location in this register. TRCR--Trapped Cycle Register Offset Address: 1E10-1E17h Default Value: 0000000000000000h Attribute: Size: RO 64-bit This register saves information about the I/O Cycle that was trapped and generated the SMI# for software to read. Bit 63:25 24 Reserved Read/Write# (RWI) -- RO. Trapped cycle was a write cycle. Trapped cycle was a read cycle. 23:20 Reserved 19:16 Active-high Byte Enables (AHBE) -- RO. This is the DWord-aligned byte enables associated with the trapped cycle. A 1 in any bit location indicates that the corresponding byte is enabled in the cycle. 15:2 1:0 10.1.7 Description Trapped I/O Address (TIOA) -- RO. This is the DWord-aligned address of the trapped cycle. Reserved TWDR--Trapped Write Data Register Offset Address: 1E18-1E1Fh Default Value: 0000000000000000h Attribute: Size: RO 64-bit This register saves the data from I/O write cycles that are trapped for software to read. Bit 63:32 31:0 334 Description Reserved Trapped I/O Data (TIOD) -- RO. DWord of I/O write data. This field is undefined after trapping a read cycle. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Chipset Configuration Registers 10.1.8 IOTRn--I/O Trap Register (0-3) Offset Address: 1E80-1E87h Register 0 1E88-1E8Fh Register 1 1E90-1E97h Register 2 1E98-1E9Fh Register 3 Default Value: 0000000000000000h Attribute: R/W Size: 64-bit These registers are used to specify the set of I/O cycles to be trapped and to enable this functionality. Bit 63:50 Description Reserved 49 Read/Write Mask (RWM) -- R/W. The cycle must match the type specified in bit 48. Trapping logic will operate on both read and write cycles. 48 Read/Write# (RWIO) -- R/W. 0 = Write 1 = Read Note: The value in this field does not matter if bit 49 is set. 47:40 Reserved 39:36 Byte Enable Mask (BEM) -- R/W. A 1 in any bit position indicates that any value in the corresponding byte enable bit in a received cycle will be treated as a match. The corresponding bit in the Byte Enables field, below, is ignored. 35:32 Byte Enables (TBE) -- R/W. Active-high DWord-aligned byte enables. 31:24 Reserved 23:18 Address[7:2] Mask (ADMA) -- R/W. A 1 in any bit position indicates that any value in the corresponding address bit in a received cycle will be treated as a match. The corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6 bits of the DWord address, allowing for traps on address ranges up to 256 bytes in size. 17:16 15:2 Reserved I/O Address[15:2] (IOAD) -- R/W. DWord-aligned address 1 Reserved 0 Trap and SMI# Enable (TRSE) -- R/W. 0 = Trapping and SMI# logic disabled. 1 = The trapping logic specified in this register is enabled. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 335 Chipset Configuration Registers 10.1.9 V0CTL--Virtual Channel 0 Resource Control Register Offset Address: 2014-2017h Default Value: 80000011h Bit 31 Description Virtual Channel Enable (EN) -- RO. Always set to 1. VC0 is always enabled and cannot be disabled. Reserved 26:24 Virtual Channel Identifier (ID) -- RO. Indicates the ID to use for this virtual channel. 23:16 Reserved 15:10 Extended TC/VC Map (ETVM): R/WL. Defines the upper 8-bits of the VC0 16-bit TC/VC mapping registers. These registers use the PCI Express* reserved TC[3] traffic class bit. These bits are locked if the TCLOCKDN bit (RCBA+0050h:bit 31) is set. 9:7 Reserved 6:1 Transaction Class / Virtual Channel Map (TVM) -- R/WL. Indicates which transaction classes are mapped to this virtual channel. When a bit is set, this transaction class is mapped to the virtual channel.hese bits are locked if the TCLOCKDN bit (RCBA+0050h:bit 31) is set. Reserved V0STS--Virtual Channel 0 Resource Status Register Offset Address: 201A-201Bh Default Value: 0000h Bit 15:2 10.1.11 Attribute: Size: RO 16-bit Description Reserved 1 VC Negotiation Pending (NP) -- RO. When set, indicates the virtual channel is still being negotiated with ingress ports. 0 Reserved V1CTL--Virtual Channel 1 Resource Control Register Offset Address: 2020-2023h Default Value: 00000000h Attribute: Size: R/W, RO, R/WL 32-bit Bit Description 31 Virtual Channel Enable (EN) -- R/W. Enables the VC when set. Disables the VC when cleared. 30:28 Reserved 27:24 Virtual Channel Identifier (ID) -- R/W. Indicates the ID to use for this virtual channel. 23:16 Reserved 15:10 Extended TC/VC Map (ETVM): R/WL. Defines the upper 8-bits of the VC0 16-bit TC/VC mapping registers. These registers use the PCI Express* reserved TC[3] traffic class bit. These bits are locked if the TCLOCKDN bit (RCBA+0050h:bit 31) is set. 9:8 Reserved 7:1 Transaction Class / Virtual Channel Map (TVM) -- R/WL. Indicates which transaction classes are mapped to this virtual channel. When a bit is set, this transaction class is mapped to the virtual channel. These bits are locked if the TCLOCKDN bit (RCBA+0050h:bit 31) is set. 0 336 R/WL, RO 32-bit 30:27 0 10.1.10 Attribute: Size: Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Chipset Configuration Registers 10.1.12 V1STS--Virtual Channel 1 Resource Status Register Offset Address: 2026-2027h Default Value: 0000h Bit 15:2 10.1.13 RO 16-bit Description Reserved 1 VC Negotiation Pending (NP) -- RO. When set, indicates the virtual channel is still being negotiated with ingress ports. 0 Reserved REC--Root Error Command Register Offset Address: 20AC-20AFh Default Value: 0000h Attribute: Size: R/W 32-bit Bit Description 31 Drop Poisoned Downstream Packets (DPDP) -- R/W. Determines how downstream packets on DMI are handled that are received with the EP field set, indicating poisoned data: 0 = Packets are forwarded downstream without forcing the UT field set. 1 = This packet and all subsequent packets with data received on DMI for any VC will have their Unsupported Transaction (UT) field set causing them to master Abort downstream. Packets without data such as memory, IO and config read requests are allowed to proceed. 30:0 10.1.14 Attribute: Size: Reserved LCAP--Link Capabilities Register Offset Address: 21A4-21A7h Default Value: 00012C42h Bit Attribute: Size: R/WO, RO 32-bit Description 31:18 Reserved 17:15 L1 Exit Latency (EL1) -- R/WO. 000b - Less than 1 s 001b - 1 s to less than 2 s 010b - 2 s to less than 4 s 011b - 4 s to less than 8 s 100b - 8 s to less than 16 s 101b - 16 s to less than 32 s 110b - 32 s to 64 s 111b - More than 64 s 14:12 L0s Exit Latency (EL0) -- R/W. This field indicates that exit latency is 128 ns to less than 256 ns. 11:10 Active State Link PM Support (APMS) -- R/W. Indicates the level of ASPM support on DMI. 00 = Disabled 01 = L0s entry supported 10 = Reserved 11 = L0s and L1 entry supported 9:4 Maximum Link Width (MLW) -- RO. Indicates the maximum link width is 4 ports. 3:0 Supported Link Speed (MLS) -- RO. Indicates the supported links speeds is 5.0 GT/s. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 337 Chipset Configuration Registers 10.1.15 LCTL--Link Control Register Offset Address: 21A8-21A9h Default Value: 0000h Attribute: Size: Bit 15:8 7 10.1.16 Description Reserved Extended Synch (ES) -- R/W. When set, forces extended transmission of FTS ordered sets when exiting L0s prior to entering L0 and extra TS1 sequences at exit from L1 prior to entering L0. 6:2 Reserved 1:0 Active State Link PM Control (ASPM) -- R/W. Indicates whether DMI should enter L0s, L1, or both. 00 = Disabled 01 = L0s entry enabled 10 = L1 entry enabled 11 = L0s and L1 entry enabled LLSTS--Link Status Register Offset Address: 21AA-21ABh Default Value: 0042h Attribute: Size: Bit 15:10 10.1.17 Reserved 9:4 Negotiated Link Width (NLW) -- RO. Negotiated link width is x4 (000100b). 3:0 Current Link Speed (LS) -- RO. 0001b = 2.5 Gb/s 0010b = 5.0 Gb/s DLCTL2--DMI Link Control 2 Register Attribute: Size: Bit 31:4 3:0 R/W, RO 16-bit Description Reserved DLCTL2 Field 1 -- R/W. BIOS must set these bits. DMIC--DMI Control Register Offset Address: 2234-2237h Default Value: 00000000h Bit 31:2 1:0 338 RO 16-bit Description Offset Address: 21B0-21B1h Default Value: 0001h 10.1.18 R/W 16-bit Attribute: Size: R/W 32-bit Description Reserved DMI Clock Gate Enable (DMICGEN) -- R/W. BIOS must program this field to 11b. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Chipset Configuration Registers 10.1.19 TCTL--TCO Configuration Register Offset Address: 3000-3000h Default Value: 00h Bit 7 10.1.20 Attribute: Size: R/W 8-bit Description TCO IRQ Enable (IE) -- R/W. 0 = TCO IRQ is disabled. 1 = TCO IRQ is enabled, as selected by the TCO_IRQ_SEL field. 6:3 Reserved 2:0 TCO IRQ Select (IS) -- R/W. Specifies on which IRQ the TCO will internally appear. If not using the APIC, the TCO interrupt must be routed to IRQ9-11, and that interrupt is not sharable with the SERIRQ stream, but is shareable with other PCI interrupts. If using the APIC, the TCO interrupt can also be mapped to IRQ20-23, and can be shared with other interrupt. 000 = IRQ 9 001 = IRQ 10 010 = IRQ 11 011 = Reserved 100 = IRQ 20 (only if APIC enabled) 101 = IRQ 21 (only if APIC enabled) 110 = IRQ 22 (only if APIC enabled) 111 = IRQ 23 (only if APIC enabled) When setting the these bits, the IE bit should be cleared to prevent glitching. When the interrupt is mapped to APIC interrupts 9, 10 or 11, the APIC should be programmed for active-high reception. When the interrupt is mapped to APIC interrupts 20 through 23, the APIC should be programmed for active-low reception. D31IP--Device 31 Interrupt Pin Register Offset Address: 3100-3103h Default Value: 03243200h Bit Attribute: Size: R/W, RO 32-bit Description 31:28 Reserved 27:24 Thermal Sensor Pin (TSIP) -- R/W. Indicates which pin the Thermal Sensor controller drives as its interrupt 0h = No interrupt 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h-Fh = Reserved 23:20 SATA Pin 2 (SIP2) -- R/W. Indicates which pin the SATA controller 2 drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h-Fh = Reserved 19:16 Reserved 15:12 SMBus Pin (SMIP) -- R/W. Indicates which pin the SMBus controller drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h-Fh = Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 339 Chipset Configuration Registers Bit 11:8 10.1.21 Description SATA Pin (SIP) -- R/W. Indicates which pin the SATA controller drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h-Fh = Reserved 7:4 Reserved 3:0 LPC Bridge Pin (LIP) -- RO. Currently, the LPC bridge does not generate an interrupt, so this field is read-only and 0. D30IP--Device 30 Interrupt Pin Register Offset Address: 3104-3107h Default Value: 00000000h Bit 31:4 3:0 10.1.22 Reserved PCI Bridge Pin (PIP) -- RO. Currently, the PCI bridge does not generate an interrupt, so this field is read-only and 0. D29IP--Device 29 Interrupt Pin Register Bit 31:4 3:0 Attribute: Size: R/W 32-bit Description Reserved EHCI #1 Pin (E1P) -- R/W. Indicates which pin the EHCI controller #1 drives as its interrupt, if controller exists. 0h = No interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h-7h = Reserved Note: EHCI Controller #1 is mapped to Device 29 Function 0. D28IP--Device 28 Interrupt Pin Register Offset Address: 310C-310Fh Default Value: 00214321h 340 RO 32-bit Description Offset Address: 3108-310Bh Default Value: 10004321h 10.1.23 Attribute: Size: Attribute: Size: R/W 32-bit Bit Description 31:28 PCI Express* #8 Pin (P8IP) -- R/W. Indicates which pin the PCI Express* port #8 drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h-7h = Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Chipset Configuration Registers Bit Description 27:24 PCI Express* #7 Pin (P7IP) -- R/W. Indicates which pin the PCI Express* port #7 drives as its interrupt. 0h = No interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h-7h = Reserved 23:20 PCI Express* #6 Pin (P6IP) -- R/W. Indicates which pin the PCI Express* port #6 drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h-7h = Reserved 19:16 PCI Express* #5 Pin (P5IP) -- R/W. Indicates which pin the PCI Express* port #5 drives as its interrupt. 0h = No interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h-7h = Reserved 15:12 PCI Express* #4 Pin (P4IP) -- R/W. Indicates which pin the PCI Express* port #4 drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# 3h = INTC# 4h = INTD# (Default) 5h-7h = Reserved 11:8 PCI Express* #3 Pin (P3IP) -- R/W. Indicates which pin the PCI Express* port #3 drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# 3h = INTC# (Default) 4h = INTD# 5h-7h = Reserved 7:4 PCI Express* #2 Pin (P2IP) -- R/W. Indicates which pin the PCI Express* port #2 drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h-7h = Reserved 3:0 PCI Express* #1 Pin (P1IP) -- R/W. Indicates which pin the PCI Express* port #1 drives as its interrupt. 0h = No interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h-7h = Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 341 Chipset Configuration Registers 10.1.24 D27IP--Device 27 Interrupt Pin Register Offset Address: 3110-3113h Default Value: 00000001h Bit 31:4 3:0 10.1.25 Reserved Intel HD Audio Pin (ZIP) -- R/W. Indicates which pin the Intel HD Audio controller drives as its interrupt. 0h = No interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h-Fh = Reserved D26IP--Device 26 Interrupt Pin Register Bit 31:4 3:0 Attribute: Size: R/W 32-bit Description Reserved EHCI #2 Pin (E2P) -- R/W. Indicates which pin EHCI controller #2 drives as its interrupt, if controller exists. 0h = No Interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h-Fh = Reserved Note: EHCI Controller #2 is mapped to Device 26 Function 0. D25IP--Device 25 Interrupt Pin Register Offset Address: 3118-311Bh Default Value: 00000001h Bit 31:4 3:0 342 R/W 32-bit Description Offset Address: 3114-3117h Default Value: 30000321h 10.1.26 Attribute: Size: Attribute: Size: R/W 32-bit Description Reserved GbE LAN Pin (LIP) -- R/W. Indicates which pin the internal GbE LAN controller drives as its interrupt 0h = No Interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h-Fh = Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Chipset Configuration Registers 10.1.27 D22IP--Device 22 Interrupt Pin Register Offset Address: 3124-3127h Default Value: 00004321h Bit Attribute: Size: R/W 32-bit Description 31:16 Reserved 15:12 KT Pin (KTIP) -- R/W. Indicates which pin the Keyboard text PCI functionality drives as its interrupt 0h = No Interrupt 1h = INTA# 2h = INTB# 3h = INTC# 4h = INTD# 5h-Fh = Reserved 11:8 (HEDT SKU Only) Reserved 11:8 (SRV/WS SKUs Only) IDE-R Pin (IDERIP) -- R/W. Indicates which pin the IDE Redirect PCI functionality drives as its interrupt 0h = No Interrupt 1h = INTA# 2h = INTB# 3h = INTC# 4h = INTD# 5h-Fh = Reserved Intel MEI #2 Pin (MEI2IP) -- R/W. Indicates which pin the Intel MEI #2 drives as its 7:4 interrupt 0h = No Interrupt 1h = INTA# 2h = INTB# 3h = INTC# 4h = INTD# 5h-Fh = Reserved Intel MEI #1 Pin (MEI1IP) -- R/W. Indicates which pin the Intel MEI #1 drives as its 3:0 interrupt 0h = No Interrupt 1h = INTA# 2h = INTB# 3h = INTC# 4h = INTD# 5h-Fh = Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 343 Chipset Configuration Registers 10.1.28 D31IR--Device 31 Interrupt Route Register Offset Address: 3140-3141h Default Value: 3210h Bit 15 14:12 11 10:8 7 6:4 3 2:0 10.1.29 R/W 16-bit Description Reserved Interrupt D Pin Route (IDR) -- R/W. Indicates which physical pin on the PCH is connected to the INTD# pin reported for device 31 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt C Pin Route (ICR) -- R/W. Indicates which physical pin on the PCH is connected to the INTC# pin reported for device 31 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# (Default) 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt B Pin Route (IBR) -- R/W. Indicates which physical pin on the PCH is connected to the INTB# pin reported for device 31 functions. 0h = PIRQA# 1h = PIRQB# (Default) 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt A Pin Route (IAR) -- R/W. Indicates which physical pin on the PCH is connected to the INTA# pin reported for device 31 functions. 0h = PIRQA# (Default) 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# D30IR--Device 30 Interrupt Route Register Offset Address: 3142-3143h Default Value: 0000h Bit 15:0 344 Attribute: Size: Attribute: Size: RO 16-bit Description Reserved. No interrupts generated from Device 30. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Chipset Configuration Registers 10.1.30 D29IR--Device 29 Interrupt Route Register Offset Address: 3144-3145h Default Value: 3210h Bit 15 14:12 11 10:8 7 6:4 3 2:0 Attribute: Size: R/W 16-bit Description Reserved Interrupt D Pin Route (IDR) -- R/W. Indicates which physical pin on the PCH is connected to the INTD# pin reported for device 29 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt C Pin Route (ICR) -- R/W. Indicates which physical pin on the PCH is connected to the INTC# pin reported for device 29 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# (Default) 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt B Pin Route (IBR) -- R/W. Indicates which physical pin on the PCH is connected to the INTB# pin reported for device 29 functions. 0h = PIRQA# 1h = PIRQB# (Default) 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt A Pin Route (IAR) -- R/W. Indicates which physical pin on the PCH is connected to the INTA# pin reported for device 29 functions. 0h = PIRQA# (Default) 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 345 Chipset Configuration Registers 10.1.31 D28IR--Device 28 Interrupt Route Register Offset Address: 3146-3147h Default Value: 3210h Bit 15 14:12 11 10:8 7 6:4 3 2:0 346 Attribute: Size: R/W 16-bit Description Reserved Interrupt D Pin Route (IDR) -- R/W. Indicates which physical pin on the PCH is connected to the INTD# pin reported for device 28 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt C Pin Route (ICR) -- R/W. Indicates which physical pin on the PCH is connected to the INTC# pin reported for device 28 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# (Default) 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt B Pin Route (IBR) -- R/W. Indicates which physical pin on the PCH is connected to the INTB# pin reported for device 28 functions. 0h = PIRQA# 1h = PIRQB# (Default) 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt A Pin Route (IAR) -- R/W. Indicates which physical pin on the PCH is connected to the INTA# pin reported for device 28 functions. 0h = PIRQA# (Default) 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Chipset Configuration Registers 10.1.32 D27IR--Device 27 Interrupt Route Register Offset Address: 3148-3149h Default Value: 3210h Bit 15 14:12 11 10:8 7 6:4 3 2:0 Attribute: Size: R/W 16-bit Description Reserved Interrupt D Pin Route (IDR) -- R/W. Indicates which physical pin on the PCH is connected to the INTD# pin reported for device 27 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt C Pin Route (ICR) -- R/W. Indicates which physical pin on the PCH is connected to the INTC# pin reported for device 27 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# (Default) 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt B Pin Route (IBR) -- R/W. Indicates which physical pin on the PCH is connected to the INTB# pin reported for device 27 functions. 0h = PIRQA# 1h = PIRQB# (Default) 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt A Pin Route (IAR) -- R/W. Indicates which physical pin on the PCH is connected to the INTA# pin reported for device 27 functions. 0h = PIRQA# (Default) 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 347 Chipset Configuration Registers 10.1.33 D26IR--Device 26 Interrupt Route Register Offset Address: 314C-314Dh Default Value: 3210h Bit 15 14:12 11 10:8 7 6:4 3 2:0 348 Attribute: Size: R/W 16-bit Description Reserved Interrupt D Pin Route (IDR) -- R/W. Indicates which physical pin on the PCH is connected to the INTD# pin reported for device 26 functions: 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt C Pin Route (ICR) -- R/W. Indicates which physical pin on the PCH is connected to the INTC# pin reported for device 26 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# (Default) 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt B Pin Route (IBR) -- R/W. Indicates which physical pin on the PCH is connected to the INTB# pin reported for device 26 functions. 0h = PIRQA# 1h = PIRQB# (Default) 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt A Pin Route (IAR) -- R/W. Indicates which physical pin on the PCH is connected to the INTA# pin reported for device 26 functions. 0h = PIRQA# (Default) 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Chipset Configuration Registers 10.1.34 D25IR--Device 25 Interrupt Route Register Offset Address: 3150-3151h Default Value: 3210h Bit 15 14:12 11 10:8 7 6:4 3 2:0 Attribute: Size: R/W 16-bit Description Reserved Interrupt D Pin Route (IDR): -- R/W. Indicates which physical pin on the PCH is connected to the INTD# pin reported for device 25 functions: 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt C Pin Route (ICR) -- R/W. Indicates which physical pin on the PCH is connected to the INTC# pin reported for device 25 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# (Default) 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt B Pin Route (IBR) -- R/W. Indicates which physical pin on the PCH is connected to the INTB# pin reported for device 25 functions. 0h = PIRQA# 1h = PIRQB# (Default) 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt A Pin Route (IAR) -- R/W. Indicates which physical pin on the PCH is connected to the INTA# pin reported for device 25 functions. 0h = PIRQA# (Default) 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 349 Chipset Configuration Registers 10.1.35 D22IR--Device 22 Interrupt Route Register Offset Address: 315C-315Dh Default Value: 3210h Bit 15 14:12 11 10:8 7 6:4 3 2:0 350 Attribute: Size: R/W 16-bit Description Reserved Interrupt D Pin Route (IDR): -- R/W. Indicates which physical pin on the PCH is connected to the INTD# pin reported for device 22 functions: 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt C Pin Route (ICR) -- R/W. Indicates which physical pin on the PCH is connected to the INTC# pin reported for device 22 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# (Default) 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt B Pin Route (IBR) -- R/W. Indicates which physical pin on the PCH is connected to the INTB# pin reported for device 22 functions. 0h = PIRQA# 1h = PIRQB# (Default) 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt A Pin Route (IAR) -- R/W. Indicates which physical pin on the PCH is connected to the INTA# pin reported for device 22 functions. 0h = PIRQA# (Default) 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Chipset Configuration Registers 10.1.36 OIC--Other Interrupt Control Register Offset Address: 31FE-31FFh Default Value: 0000h Bit R/W 16-bit Description 15:10 Reserved 9 Coprocessor Error Enable (CEN) -- R/W. 0 = FERR# will not generate IRQ13 nor IGNNE#. 1 = If FERR# is low, the PCH generates IRQ13 internally and holds it until an I/O port F0h write. It will also drive IGNNE# active. 8 APIC Enable (AEN) -- R/W. 0 = The internal IOxAPIC is disabled. 1 = Enables the internal IOxAPIC and its address decode. Note: Software should read this register after modifying APIC enable bit prior to access to the IOxAPIC address range. 7:0 APIC Range Select (ASEL) -- R/W.These bits define address bits 19:12 for the IOxAPIC range. The default value of 00h enables compatibility with prior PCH products as an initial value. This value must not be changed unless the IOxAPIC Enable bit is cleared. Note: 10.1.37 Attribute: Size: FEC1_0000h-FEC4_FFFFh is allocated to PCIe when I/OxApic Enable (PAE) bit is set. PRSTS--Power and Reset Status Register Offset Address: 3310-3313h Default Value: 03000000h Bit Attribute: Size: RO, R/WC 32-bit Description 31:16 15 14:7 Reserved Power Management Watchdog Timer -- R/WC. This bit is set when the Power Management watchdog timer causes a global reset. Reserved 6 Intel ME Watchdog Timer Status -- R/WC. This bit is set when the Intel ME watchdog timer causes a global reset. 5 Wake On LAN Override Wake Status (WOL_OVR_WK_STS) -- R/WC. This bit gets set when all of the following conditions are met: * Integrated LAN Signals a Power Management Event * The system is not in S0 * The "WOL Enable Override" bit is set in configuration space. BIOS can read this status bit to determine this wake source. Software clears this bit by writing a 1 to it. 4 PRSTS Field 1 -- R/W. BIOS may write to this bit field. 3 Intel ME Host Power Down (ME_HOST_PWRDN) -- R/WC.This bit is set when the Intel ME generates a host reset with power down. 2 Intel ME Host Reset Warm Status (ME_HRST_WARM_STS) -- R/WC. This bit is set when the Intel ME generates a Host reset without power cycling. Software clears this bit by writing a 1 to this bit position. 1 Intel ME Host Reset Cold Status (ME_HRST_COLD_STS) -- R/WC. This bit is set when the Intel ME generates a Host reset with power cycling. Software clears this bit by writing a 1 to this bit position. 0 Intel ME WAKE STATUS (ME_WAKE_STS) -- R/WC. This bit is set when the Intel ME generates a Non-Maskable wake event, and is not affected by any other enable bit. When this bit is set, the Host Power Management logic wakes to S0. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 351 Chipset Configuration Registers 10.1.38 PM_CFG--Power Management Configuration Offset Address: 3318-331Bh Default Value: 00000000h Bit Attribute: Size: R/W 32-bit Description 31:27 Reserved. 26:24 PM_CFG Field 1 -- R/W. BIOS must program this field to `101'. 23:22 Reserved. 21 20 19:18 RTC Wake from Deep S4/S5 Disable (RTC_DS_WAKE_DIS)-- R/W. When set, this bit disables RTC wakes from waking the system from Deep S4/S5. This bit is reset by RTCRST#. Reserved. SLP_SUS# Minimum Assertion Width (SLP_SUS_MIN_ASST_WDTH)-- R/W. This field indicates the minimum assertion width of the SLP_SUS# signal to ensure that the SUS power supplies have been fully power cycled. This value may be modified per platform depending on power supply capacitance, board capacitance, power circuits, etc. Valid values are: 11 = 4 seconds 10 = 1 second 01 = 500 ms 00 = 0 ms (that is, stretching disabled - default) These bits are cleared by RTCRST# assertion. This field is RO when the SLP Stretching Policy Lock-Down bit is set. This field is ignored when exiting G3 or Deep S4/S5 states if the "Disable SLP Stretching After SUS Well Power Up" bit is set. Note that unlike with all other SLP_* pin stretching, this disable bit only impacts SLP_SUS# stretching during G3 exit rather than both G3 and Deep S4/S5 exit. SLP_SUS# stretching always applies to Deep S4/S5 regardless of the disable bit. For platforms that enable Deep S4/S5, BIOS must program SLP_SUS# stretching to be greater than or equal to the largest stretching value on any other SLP_* pin (SLP_S3#, SLP_S4#, or SLP_A#). 17:16 15:0 352 SLP_A# Minimum Assertion Width (SLP_A_MIN_ASST_WDTH) -- R/W. This field indicates the minimum assertion width of the SLP_A# signal to ensure that the ASW power supplies have been fully power cycled. This value may be modified per platform depending on power supply capacitance, board capacitance, power circuits, etc. Valid values are: 11 = 2 seconds 10 = 98 ms 01 = 4 seconds 00 = 0 ms (that is, stretching disabled - default) These bits are cleared by RTCRST# assertion. Notes: 1. This field is RO when the SLP Stretching Policy Lock-Down bit is set. 2. This field is ignored when exiting G3 or Deep S4/S5 states if the "Disable SLP Stretching After SUS Well Power Up" bit is set. Reserved. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Chipset Configuration Registers 10.1.39 DEEP_S4_POL--Deep S4/S5 From S4 Power Policies Offset Address: 332C-332Fh Attribute: R/W Default Value: 00000000h Size: 32-bit This register is in the RTC power well and is reset by RTCRST# assertion. Bit Description 31:2 1 0 10.1.40 Reserved. Deep S4/S5 From S4 Enable in DC Mode (DPS4_EN_DC) -- R/W. A '1' in this bit enables the platform to enter Deep S4/S5 while operating in S4 on DC power (based on the AC_PRESENT pin value). Deep S4/S5 From S4 Enable in AC Mode (DPS4_EN_AC) -- R/W. A '1' in this bit enables the platform to enter Deep S4 while operating in S4 on AC power (based on the AC_PRESENT pin value). DEEP_S5_POL--Deep S4/S5 From S5 Power Policies Offset Address: 3330-3333h Attribute: R/W Default Value: 00000000h Size: 32-bit This register is in the RTC power well and is reset by RTCRST# assertion. Bit 31:16 15 14 13:0 10.1.41 Description Reserved. Deep S4/S5 From S5 Enable in DC Mode (DPS5_EN_DC) -- R/W. A '1' in this bit enables the platform to enter Deep S4/S5 while operating in S5 on DC power. Deep S4/S5 From S5 Enable in AC Mode (DPS5_EN_AC) -- R/W. A '1' in this bit enables the platform to enter Deep S4/S5 while operating in S5 on AC power. Reserved. RC--RTC Configuration Register Offset Address: 3400-3403h Default Value: 00000000h Bit Attribute: Size: R/W, R/WLO 32-bit Description 31:5 Reserved 4 Upper 128 Byte Lock (UL) -- R/WLO. 0 = Bytes not locked. 1 = Bytes 38h-3Fh in the upper 128-byte bank of RTC RAM are locked and cannot be accessed. Writes will be dropped and reads will not return any ensured data. Bit reset on system reset. 3 Lower 128 Byte Lock (LL) -- R/WLO. 0 = Bytes not locked. 1 = Bytes 38h-3Fh in the lower 128-byte bank of RTC RAM are locked and cannot be accessed. Writes will be dropped and reads will not return any ensured data. Bit reset on system reset. 2 Upper 128 Byte Enable (UE) -- R/W. 0 = Bytes locked. 1 = The upper 128-byte bank of RTC RAM can be accessed. 1:0 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 353 Chipset Configuration Registers 10.1.42 HPTC--High Precision Timer Configuration Register Offset Address: 3404-3407h Default Value: 00000000h Attribute: Size: Bit 31:8 7 10.1.43 R/W 32-bit Description Reserved Address Enable (AE) -- R/W. 0 = Address disabled. 1 = The PCH will decode the High Precision Timer memory address range selected by bits 1:0 below. 6:2 Reserved 1:0 Address Select (AS) -- R/W. This 2-bit field selects 1 of 4 possible memory address ranges for the High Precision Timer functionality. The encodings are: 00 = FED0_0000h - FED0_03FFh 01 = FED0_1000h - FED0_13FFh 10 = FED0_2000h - FED0_23FFh 11 = FED0_3000h - FED0_33FFh GCS--General Control and Status Register Offset Address: 3410-3413h Attribute:R/W, R/WLO Default Value: 00000yy0h (yy = xx0000x0b)Size:32-bit Bit 31:13 12 Description Reserved. Function Level Reset Capability Structure Select (FLRCSSEL) -- R/W. 0 = Function Level Reset (FLR) will utilize the standard capability structure with unique capability ID assigned by PCISIG. 1 = Vendor Specific Capability Structure is selected for FLR. Boot BIOS Straps (BBS) -- R/W. This field determines the destination of accesses to the BIOS memory range. The default values for these bits represent the strap values of GNT1# /GPIO51 (bit 11) at the rising edge of PCH_PWROK and SATA1GP/GPIO19 (bit 10) at the rising edge of PCH_PWROK. Bits 11:10 00b 11:10 01b RESERVED 10b PCI 11b SPI When PCI is selected, the top 16 MB of memory below 4 GB (FF00_0000h to FFFF_FFFFh) is accepted by the primary side of the PCI P2P bridge and forwarded to the PCI bus. This allows systems with corrupted or unprogrammed flash to boot from a PCI device. The PCI-to-PCI bridge Memory Space Enable bit does not need to be set (nor any other bits) in order for these cycles to go to PCI. Note that BIOS decode range bits and the other BIOS protection bits have no effect when PCI is selected. This functionality is intended for debug/testing only. When SPI or LPC is selected, the range that is decoded is further qualified by other configuration bits described in the respective sections. The value in this field can be overwritten by software as long as the BIOS Interface Lock-Down (bit 0) is not set. Note: 354 Description LPC Booting to PCI is intended for debug/testing only. Boot BIOS Destination Select to LPC/ PCI by functional strap or using Boot BIOS Destination Bit will not affect SPI accesses initiated by Intel ME or Integrated GbE LAN. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Chipset Configuration Registers Bit Description 9 Server Error Reporting Mode (SERM) -- R/W. 0 = The PCH is the final target of all errors. The Processor sends a messages to the PCH for the purpose of generating NMI. 1 = The Processor is the final target of all errors from PCI Express* and DMI. In this mode, if the PCH detects a fatal, non-fatal, or correctable error on DMI or its downstream ports, it sends a message to the Processor. If the PCH receives an ERR_* message from the downstream port, it sends that message to the Processor. 8:6 Reserved 5 No Reboot (NR) -- R/W. This bit is set when the "No Reboot" strap (SPKR pin on the PCH) is sampled high on PCH_PWROK. This bit may be set or cleared by software if the strap is sampled low but may not override the strap when it indicates "No Reboot". 0 = System will reboot upon the second timeout of the TCO timer. 1 = The TCO timer will count down and generate the SMI# on the first timeout, but will not reboot on the second timeout. 4 Alternate Access Mode Enable (AME) -- R/W. 0 = Disabled. 1 = Alternate access read only registers can be written, and write only registers can be read. Before entering a low power state, several registers from powered down parts may need to be saved. In the majority of cases, this is not an issue, as registers have read and write paths. However, several of the ISA compatible registers are either read only or write only. To get data out of write-only registers, and to restore data into read-only registers, the PCH implements an alternate access mode. For a list of these registers see Section 5.14.9. 3 Shutdown Policy Select (SPS) -- R/W. 0 = PCH will drive INIT# in response to the shutdown Vendor Defined Message (VDM). (Default) 1 = PCH will treat the shutdown VDM similar to receiving a CF9h I/O write with data value 06h, and will drive PLTRST# active. 2 Reserved Page Route (RPR) -- R/W. Determines where to send the reserved page registers. These addresses are sent to PCI or LPC for the purpose of generating POST codes. The I/O addresses modified by this field are: 80h, 84h, 85h, 86h, 88h, 8Ch, 8Dh, and 8Eh. 0 = Writes will be forwarded to LPC, shadowed within the PCH, and reads will be returned from the internal shadow 1 = Writes will be forwarded to PCI, shadowed within the PCH, and reads will be returned from the internal shadow. Note: If some writes are done to LPC/PCI to these I/O ranges, and then this bit is flipped, such that writes will now go to the other interface, the reads will not return what was last written. Shadowing is performed on each interface. The aliases for these registers, at 90h, 94h, 95h, 96h, 98h, 9Ch, 9Dh, and 9Eh, are always decoded to LPC. 1 Reserved 0 BIOS Interface Lock-Down (BILD) -- R/WLO. 0 = Disabled. 1 = Prevents BUC.TS (offset 3414, bit 0) and GCS.BBS (offset 3410h, bits 11:10) from being changed. This bit can only be written from 0 to 1 once. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 355 Chipset Configuration Registers 10.1.44 BUC--Backed Up Control Register Offset Address: 3414-3414h Default Value: 0000000xb Attribute: Size: R/W 8-bit All bits in this register are in the RTC well and only cleared by RTCRST# Bit 7:6 Description Reserved LAN Disable -- R/W. 0 = LAN is Enabled 1 = LAN is Disabled. 5 Changing the internal GbE controller from disabled to enabled requires a system reset (write of 0Eh to CF9h (RST_CNT Register)) immediately after clearing the LAN disable bit. A reset is not required if changing the bit from enabled to disabled. This bit is locked by the Function Disable SUS Well Lockdown register. Once locked this bit can not be changed by software. 4 3:1 Daylight Savings Override (SDO) -- R/W. 0 = Daylight Savings is Enabled. 1 = The DSE bit in RTC Register B is set to Read-only with a value of 0 to disable daylight savings. Reserved Top Swap (TS) -- R/W. 0 = PCH will not invert A16. 1 = PCH will invert A16, A17, or A18 for cycles going to the BIOS space in the FWH. 0 If booting from LPC (FWH), then the boot-block size is 64 KB and A16 is inverted if Top Swap is enabled. If booting from SPI, then the BIOS Boot-Block size soft strap determines if A16, A17, or A18 should be inverted if Top Swap is enabled. If PCH is strapped for Top-Swap (GNT3#/GPIO55 is low at rising edge of PCH_PWROK), then this bit cannot be cleared by software. The strap jumper should be removed and the system rebooted. 10.1.45 FD--Function Disable Register Offset Address: 3418-341Bh Default Value: See bit description Attribute: Size: R/W 32-bit When disabling a function, only the configuration space is disabled. Software must ensure that all functionality within a controller that is not desired (such as memory spaces, I/O spaces, and DMA engines) is disabled prior to disabling the function. When a function is disabled, software must not attempt to re-enable it. A disabled function can only be re-enabled by a platform reset. Bit 31:26 356 Description Reserved 25 Serial ATA Disable 2 (SAD2) -- R/W. Default is 0. 0 = The SATA controller #2 (D31:F5) is enabled. 1 = The SATA controller #2 (D31:F5) is disabled. 24 Thermal Sensor Registers Disable (TTD) -- R/W. Default is 0. 0 = Thermal Sensor Registers (D31:F6) are is enabled. 1 = Thermal Sensor Registers (D31:F6) are is disabled. 23 PCI Express* 8 Disable (PE8D) -- R/W. Default is 0. When disabled, the link for this port is put into the "link down" state. 0 = PCI Express* port #8 is enabled. 1 = PCI Express* port #8 is disabled. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Chipset Configuration Registers Bit Description 22 PCI Express* 7 Disable (PE7D) -- R/W. Default is 0. When disabled, the link for this port is put into the link down state. 0 = PCI Express* port #7 is enabled. 1 = PCI Express* port #7 is disabled. 21 PCI Express* 6 Disable (PE6D) -- R/W. Default is 0. When disabled, the link for this port is put into the "link down" state. 0 = PCI Express* port #6 is enabled. 1 = PCI Express* port #6 is disabled. 20 PCI Express* 5 Disable (PE5D) -- R/W. Default is 0. When disabled, the link for this port is put into the link down state. 0 = PCI Express* port #5 is enabled. 1 = PCI Express* port #5 is disabled. 19 PCI Express* 4 Disable (PE4D) -- R/W. Default is 0. When disabled, the link for this port is put into the "link down" state. 0 = PCI Express* port #4 is enabled. 1 = PCI Express* port #4 is disabled. Note: This bit must be set when Port 1 is configured as a x4. 18 PCI Express* 3 Disable (PE3D) -- R/W. Default is 0. When disabled, the link for this port is put into the link down state. 0 = PCI Express* port #3 is enabled. 1 = PCI Express* port #3 is disabled. Note: This bit must be set when Port 1 is configured as a x4. 17 PCI Express* 2 Disable (PE2D) -- R/W. Default is 0. When disabled, the link for this port is put into the link down state. 0 = PCI Express* port #2 is enabled. 1 = PCI Express* port #2 is disabled. Note: This bit must be set when Port 1 is configured as a x4 or a x2. 16 PCI Express* 1 Disable (PE1D) -- R/W. Default is 0. When disabled, the link for this port is put into the link down state. 0 = PCI Express* port #1 is enabled. 1 = PCI Express* port #1 is disabled. 15 EHCI #1 Disable (EHCI1D) -- R/W. Default is 0. 0 = The EHCI #1 is enabled. 1 = The EHCI #1 is disabled. 14 LPC Bridge Disable (LBD) -- R/W. Default is 0. 0 = The LPC bridge is enabled. 1 = The LPC bridge is disabled. Unlike the other disables in this register, the following additional spaces will no longer be decoded by the LPC bridge: * Memory cycles below 16 MB (1000000h) * I/O cycles below 64 KB (10000h) * The Internal I/OxAPIC at FEC0_0000 to FECF_FFFF Memory cycles in the LPC BIOS range below 4 GB will still be decoded when this bit is set, but the aliases at the top of 1 MB (the E and F segment) no longer will be decoded. 13 EHCI #2 Disable (EHCI2D) -- R/W. Default is 0. 0 = The EHCI #2 is enabled. 1 = The EHCI #2 is disabled. 12:5 Reserved 4 Intel HD Audio Disable (HDAD) -- R/W. Default is 0. 0 = The Intel HD Audio controller is enabled. 1 = The Intel HD Audio controller is disabled and its PCI configuration space is not accessible. 3 SMBus Disable (SD) -- R/W. Default is 0. 0 = The SMBus controller is enabled. 1 = The SMBus controller is disabled. In ICH5 and previous, this also disabled the I/O space. In the PCH, it only disables the configuration space. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 357 Chipset Configuration Registers Bit Description 22 PCI Express* 7 Disable (PE7D) -- R/W. Default is 0. When disabled, the link for this port is put into the link down state. 0 = PCI Express* port #7 is enabled. 1 = PCI Express* port #7 is disabled. 21 PCI Express* 6 Disable (PE6D) -- R/W. Default is 0. When disabled, the link for this port is put into the "link down" state. 0 = PCI Express* port #6 is enabled. 1 = PCI Express* port #6 is disabled. 20 PCI Express* 5 Disable (PE5D) -- R/W. Default is 0. When disabled, the link for this port is put into the link down state. 0 = PCI Express* port #5 is enabled. 1 = PCI Express* port #5 is disabled. 19 PCI Express* 4 Disable (PE4D) -- R/W. Default is 0. When disabled, the link for this port is put into the "link down" state. 0 = PCI Express* port #4 is enabled. 1 = PCI Express* port #4 is disabled. Note: This bit must be set when Port 1 is configured as a x4. 18 PCI Express* 3 Disable (PE3D) -- R/W. Default is 0. When disabled, the link for this port is put into the link down state. 0 = PCI Express* port #3 is enabled. 1 = PCI Express* port #3 is disabled. Note: This bit must be set when Port 1 is configured as a x4. 17 PCI Express* 2 Disable (PE2D) -- R/W. Default is 0. When disabled, the link for this port is put into the link down state. 0 = PCI Express* port #2 is enabled. 1 = PCI Express* port #2 is disabled. Note: This bit must be set when Port 1 is configured as a x4 or a x2. 16 PCI Express* 1 Disable (PE1D) -- R/W. Default is 0. When disabled, the link for this port is put into the link down state. 0 = PCI Express* port #1 is enabled. 1 = PCI Express* port #1 is disabled. 15 EHCI #1 Disable (EHCI1D) -- R/W. Default is 0. 0 = The EHCI #1 is enabled. 1 = The EHCI #1 is disabled. 14 LPC Bridge Disable (LBD) -- R/W. Default is 0. 0 = The LPC bridge is enabled. 1 = The LPC bridge is disabled. Unlike the other disables in this register, the following additional spaces will no longer be decoded by the LPC bridge: * Memory cycles below 16 MB (1000000h) * I/O cycles below 64 KB (10000h) * The Internal I/OxAPIC at FEC0_0000 to FECF_FFFF Memory cycles in the LPC BIOS range below 4 GB will still be decoded when this bit is set, but the aliases at the top of 1 MB (the E and F segment) no longer will be decoded. 13 EHCI #2 Disable (EHCI2D) -- R/W. Default is 0. 0 = The EHCI #2 is enabled. 1 = The EHCI #2 is disabled. 12:5 358 Reserved 4 Intel HD Audio Disable (HDAD) -- R/W. Default is 0. 0 = The Intel HD Audio controller is enabled. 1 = The Intel HD Audio controller is disabled and its PCI configuration space is not accessible. 3 SMBus Disable (SD) -- R/W. Default is 0. 0 = The SMBus controller is enabled. 1 = The SMBus controller is disabled. In ICH5 and previous, this also disabled the I/O space. In the PCH, it only disables the configuration space. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Chipset Configuration Registers Bit 10.1.46 Description 2 Serial ATA Disable 1 (SAD1) -- R/W. Default is 0. 0 = The SATA controller #1 (D31:F2) is enabled. 1 = The SATA controller #1 (D31:F2) is disabled. 1 PCI Bridge Disable -- R/W. Default is 0. 0 = The PCI-to-PCI bridge (D30:F0) is enabled. 1 = The PCI-to-PCI bridge (D30:F0) is disabled. 0 BIOS must set this bit to 1b. CG--Clock Gating Offset Address: 341C-341Fh Default Value: 00000000h Bit 31 30 29:28 Attribute: Size: R/W 32-bit Description Legacy (LPC) Dynamic Clock Gate Enable -- R/W. 0 = Legacy Dynamic Clock Gating is Disabled 1 = Legacy Dynamic Clock Gating is Enabled Reserved CG Field 1 -- R/W. BIOS must program this field to 11b. 27 SATA Port 3 Dynamic Clock Gate Enable -- R/W. 0 = SATA Port 3 Dynamic Clock Gating is Disabled 1 = SATA Port 3 Dynamic Clock Gating is Enabled 26 SATA Port 2 Dynamic Clock Gate Enable -- R/W. 0 = SATA Port 2 Dynamic Clock Gating is Disabled 1 = SATA Port 2 Dynamic Clock Gating is Enabled 25 SATA Port 1 Dynamic Clock Gate Enable -- R/W. 0 = SATA Port 1 Dynamic Clock Gating is Disabled 1 = SATA Port 1 Dynamic Clock Gating is Enabled 24 SATA Port 0 Dynamic Clock Gate Enable -- R/W. 0 = SATA Port 0 Dynamic Clock Gating is Disabled 1 = SATA Port 0 Dynamic Clock Gating is Enabled 23 LAN Static Clock Gating Enable (LANSCGE) -- R/W. 0 = LAN Static Clock Gating is Disabled 1 = LAN Static Clock Gating is Enabled when the LAN Disable bit is set in the Backed Up Control RTC register. 22 Intel HD Audio Dynamic Clock Gate Enable -- R/W. 0 = Intel HD Audio Dynamic Clock Gating is Disabled 1 = Intel HD Audio Dynamic Clock Gating is Enabled 21 Intel HD Audio Static Clock Gate Enable -- R/W. 0 = Intel HD Audio Static Clock Gating is Disabled 1 = Intel HD Audio Static Clock Gating is Enabled 20 USB EHCI Static Clock Gate Enable -- R/W. 0 = USB EHCI Static Clock Gating is Disabled 1 = USB EHCI Static Clock Gating is Enabled 19 USB EHCI Dynamic Clock Gate Enable -- R/W. 0 = USB EHCI Dynamic Clock Gating is Disabled 1 = USB EHCI Dynamic Clock Gating is Enabled 18 SATA Port 5 Dynamic Clock Gate Enable -- R/W. 0 = SATA Port 5 Dynamic Clock Gating is Disabled 1 = SATA Port 5 Dynamic Clock Gating is Enabled 17 SATA Port 4 Dynamic Clock Gate Enable -- R/W. 0 = SATA Port 4 Dynamic Clock Gating is Disabled 1 = SATA Port 4 Dynamic Clock Gating is Enabled 16 PCI Dynamic Gate Enable -- R/W. 0 = PCI Dynamic Gating is Disabled 1 = PCI Dynamic Gating is Enabled Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 359 Chipset Configuration Registers Bit 15:6 5 4:1 0 10.1.47 Description Reserved SMBus Clock Gating Enable (SMBCGEN) -- R/W. 0 = SMBus Clock Gating is Disabled. 1 = SMBus Clock Gating is Enabled. Reserved PCI Express* Root Port Static Clock Gate Enable -- R/W. 0 = PCI Express* root port Static Clock Gating is Disabled 1 = PCI Express* root port Static Clock Gating is Enabled FDSW--Function Disable SUS Well Offset Address: 3420h Default Value: 00h Bit 7 6:0 10.1.48 R/W 8-bit Description Function Disable SUS Well Lockdown (FDSWL)-- R/W03 0 = FDSW registers are not locked down 1 = FDSW registers are locked down and this bit will remain set until a global reset occurs. Note: This bit must be set when Intel(R) Active Management Technology is enabled. Reserved FD2--Function Disable 2 Offset Address: 3428-342Bh Default Value: 00000000h Bit 31:5 360 Attribute: Size: Attribute: Size: R/W 32-bit Description Reserved 4 KT Disable (KTD) --R/W. Default is 0. 0 = Keyboard Text controller (D22:F3) is enabled. 1 = Keyboard Text controller (D22:F3) is Disabled 3 IDE-R Disable (IRERD) --R/W. Default is 0. 0 = IDE Redirect controller (D22:F2) is Enabled. 1 = IDE Redirect controller (D22:F2) is Disabled. 2 Intel MEI #2 Disable (MEI2D) --R/W. Default is 0. 0 = Intel MEI controller #2 (D22:F1) is enabled. 1 = Intel MEI controller #2 (D22:F1) is disabled. 1 Intel MEI #1 Disable (MEI1D) --R/W. Default is 0. 0 = Intel MEI controller #1 (D22:F0) is enabled. 1 = Intel MEI controller #1 (D22:F0) is disabled. 0 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Chipset Configuration Registers 10.1.49 GSXBAR--GPIO Serial Expander Base Address Offset Address: 3450-3453h Default Value: FED04000h Bit 31:10 9:4 3 2:1 0 10.1.50 R/W, RO 32-bit Description Base Address (BA) --R/W. Base Address of GPIO Serial Expander logic. Reserved Prefetchable Memory (PF) --RO. Default is 0. Indicate the memory space is not prefetchable. Memory Type (TP) --RO. Set to 00b indicating a 32-bit BAR. Resource Type (RTE) --RO. Set to 0 indicating a Memory Space BAR. GSXCTRL--GPIO Serial Expander Control Register Offset Address: 3454-3457h Default Value: 00000000h Bit 31:5 4 3:0 10.1.51 Attribute: Size: Attribute: Size: R/W, RO 32-bit Description Reserved GSX BAR Enable (GSXBAREN) --R/W. Default is 0. 0 = GSXBAR is disabled. 1 = GSXBAR is enabled. Note: If GSX is disabled using soft strap, this bit will always read 0. Reserved MISCCTL--Miscellaneous Control Register Offset Address: 3590-3593h Default Value: 00000000h Attribute: Size: R/W 32-bit This register is in the suspend well. This register is not reset on D3-to-D0, HCRESET nor core well reset. Bit 31:2 Description Reserved. 1 EHCI 2 USBR Enable -- R/W. When set, this bit enables support for the USB-r redirect device on the EHCI controller in Device 26. SW must complete programming the following registers before this bit is set: 1. Enable RMH 2. HCSPARAMS (N_CC, N_Ports) 0 EHCI 1 USBR Enable -- R/W. When set, this bit enables support for the USB-r redirect device on the EHCI controller in Device 29. SW must complete programming the following registers before this bit is set: 1. Enable RMH 2. HCSPARAMS (N_CC, N_Ports) Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 361 Chipset Configuration Registers 10.1.52 USBOCM1--Overcurrent MAP Register 1 Offset Address: 35A0-35A3h Default Value: C0300C03h Attribute: Size: R/W0 32-bit All bits in this register are in the Resume Well and is only cleared by RSMRST#. Bit 31:24 23:16 15:8 7:0 362 Description OC3 Mapping Each bit position maps OC3# to a set of ports as follows: The OC3# pin is ganged to the overcurrent signal of each port that has its corresponding bit set. It is SW`s responsibility to ensure that a given port`s bit map is set only for one OC pin. Bit 31 30 29 28 27 26 25 24 Port 7 6 5 4 3 2 1 0 OC2 Mapping Each bit position maps OC2# to a set of ports as follows: The OC2# pin is ganged to the overcurrent signal of each port that has its corresponding bit set. It is SW`s responsibility to ensure that a given port`s bit map is set only for one OC pin. Bit 23 22 21 20 19 18 17 16 Port 7 6 5 4 3 2 1 0 OC1 Mapping Each bit position maps OC1# to a set of ports as follows: The OC1# pin is ganged to the overcurrent signal of each port that has its corresponding bit set. It is SW`s responsibility to ensure that a given port`s bit map is set only for one OC pin. Bit 15 14 13 12 11 10 9 8 Port 7 6 5 4 3 2 1 0 OC0 Mapping Each bit position maps OC0# to a set of ports as follows: The OC0# pin is ganged to the overcurrent signal of each port that has its corresponding bit set. It is SW`s responsibility to ensure that a given port`s bit map is set only for one OC pin. Bit 7 6 5 4 3 2 1 0 Port 7 6 5 4 3 2 1 0 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Chipset Configuration Registers 10.1.53 USBOCM2--Overcurrent MAP Register 2 Offset Address: 35A4-35A7h Default Value: 00h Attribute: Size: R/W0 32-bit All bits in this register are in the Resume Well and is only cleared by RSMRST#. Bit 31:30 29:24 23:22 21:16 15:14 13:8 7:6 5:0 10.1.54 Description Reserved OC7 Mapping Each bit position maps OC7# to a set of ports as follows: The OC7# pin is ganged to the overcurrent signal of each port that has its corresponding bit set. It is SW`s responsibility to ensure that a given port`s bit map is set only for one OC pin. Bit 29 28 27 26 25 24 Port 13 12 11 10 9 8 Reserved OC6 Mapping Each bit position maps OC6# to a set of ports as follows: The OC6# pin is ganged to the overcurrent signal of each port that has its corresponding bit set. It is SW`s responsibility to ensure that a given port`s bit map is set only for one OC pin. Bit 21 20 19 18 17 16 Port 13 12 11 10 9 8 Reserved OC5 Mapping Each bit position maps OC5# to a set of ports as follows: The OC5# pin is ganged to the overcurrent signal of each port that has its corresponding bit set. It is SW`s responsibility to ensure that a given port`s bit map is set only for one OC pin. Bit 13 12 11 10 9 8 Port 13 12 11 10 9 8 Reserved OC4 Mapping Each bit position maps OC4# to a set of ports as follows: The OC4# pin is ganged to the overcurrent signal of each port that has its corresponding bit set. It is SW`s responsibility to ensure that a given port`s bit map is set only for one OC pin. Bit 5 4 3 2 1 0 Port 13 12 11 10 9 8 RMHWKCTL- Rate Matching Hub Wake Control Register Offset Address: 35B0-35B3h Default Value: 00000000h Attribute: Size: R/W 32-bit All bits in this register are in the Resume Well and is only cleared by RSMRST# Bit 31:10 Description Reserved 9 RMH 2 Inherit EHCI2 Wake Control Settings: When this bit is set, the RMH behaves as if bits 6:4 of this register reflect the appropriate bits of EHCI PORTSC0 bits 22:20. 8 RMH 1 Inherit EHCI1 Wake Control Settings: When this bit is set, the RMH behaves as if bits 2:0 of this register reflect the appropriate bits of EHCI PORTSC0 bits 22:20. 7 RMH 2 Upstream Wake on Device Resume This bit governs the hub behavior when globally suspended and the system is in Sx. 0 = Enables the port to be sensitive to device initiated resume events as system wake-up events. that is, the hub will initiate a resume on its upstream port and cause a wake from Sx when a device resume occurs on an enabled DS port 1 = Device resume event is seen on a downstream port, the hub does not initiate a wake upstream and does not cause a wake from Sx Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 363 Chipset Configuration Registers Bit Description 6 RMH 2 Upstream Wake on OC Disable This bit governs the hub behavior when globally suspended and the system is in Sx. 0 = Enables the port to be sensitive to over-current conditions as system wake-up events. i.e, the hub will initiate a resume on its upstream port and cause a wake from Sx when an OC condition occurs on an enabled DS port 1 = Over-current event does not initiate a wake upstream and does not cause a wake from Sx 5 RMH 2 Upstream Wake on Disconnect Disable This bit governs the hub behavior when globally suspended and the system is in Sx 0 = Enables disconnect events on downstream port to be treated as resume events to be propagated upstream. In this case, it is allowed to initiate a wake on its upstream port and cause a system wake from Sx in response to a disconnect event on a downstream port 1 = Downstream disconnect events do not initiate a resume on its upstream port or cause a resume from Sx. 4 RMH 2 Upstream Wake on Connect Enable This bit governs the hub behavior when globally suspended and the system is in Sx. 0 = Enables connect events on a downstream port to be treated as resume events to be propagated upstream. As well as waking up the system from Sx. 1 = Downstream connect events do not wake the system from Sx nor does it initiate a resume on its upstream port. 3 RMH 1 Upstream Wake on Device Resume This bit governs the hub behavior when globally suspended and the system is in Sx. 0 = Enables the port to be sensitive to device initiated resume events as system wake-up events. i.e, the hub will initiate a resume on its upstream port and cause a wake from Sx when a device resume occurs on an enabled DS port 1 = Device resume event is seen on a downstream port, the hub does not initiate a wake upstream and does not cause a wake from Sx 2 RMH 1 Upstream Wake on OC Disable This bit governs the hub behavior when globally suspended and the system is in Sx. 0 = Enables the port to be sensitive to over-current conditions as system wake-up events. i.e, the hub will initiate a resume on its upstream port and cause a wake from Sx when an OC condition occurs on an enabled DS port 1 = Over-current event does not initiate a wake upstream and does not cause a wake from Sx 1 RMH 1 Upstream Wake on Disconnect Disable This bit governs the hub behavior when globally suspended and the system is in Sx 0 = Enables disconnect events on downstream port to be treated as resume events to be propagated upstream. In this case, it is allowed to initiate a wake on its upstream port and cause a system wake from Sx in response to a disconnect event on a downstream port 1 = Downstream disconnect events do not initiate a resume on its upstream port or cause a resume from Sx. 0 RMH 1 Upstream Wake on Connect Enable This bit governs the hub behavior when globally suspended and the system is in Sx. 0 = Enables connect events on a downstream port to be treated as resume events to be propagated upstream. As well as waking up the system from Sx. 1 = Downstream connect events do not wake the system from Sx nor does it initiate a resume on its upstream port. 364 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI-to-PCI Bridge Registers (D30:F0) 11 PCI-to-PCI Bridge Registers (D30:F0) The PCH PCI bridge resides in PCI Device 30, Function 0 on bus #0. This implements the buffering and control logic between PCI and the backbone. The arbitration for the PCI bus is handled by this PCI device. 11.1 PCI Configuration Registers (D30:F0) Note: Address locations that are not shown should be treated as Reserved (see Section 9.2 for details). . Table 11-1. PCI Bridge Register Address Map (PCI-PCI--D30:F0) Offset Mnemonic Register Name Default Type 00h-01h VID Vendor Identification 8086h RO 02h-03h DID Device Identification See register description RO 04h-05h PCICMD PCI Command 0000h R/W, RO 06h-07h PSTS PCI Status 0010h R/WC, RO See register description RO 08h 09h-0Bh RID Revision Identification CC Class Code 0Dh PMLT Primary Master Latency Timer 0Eh HEADTYP BNUM 18h-1Ah 1Bh 060401h RO 00h RO Header Type 01h RO Bus Number 000000h RO SMLT Secondary Master Latency Timer IOBASE_LIMIT I/O Base and Limit 1Eh-1Fh SECSTS Secondary Status 20h-23h MEMBASE_LIMIT Memory Base and Limit 1Ch-1Dh 00h R/W 0000h R/W, RO 0280h R/WC, RO 00000000h R/W 24h-27h PREF_MEM_BASE_LIMIT Prefetchable Memory Base and Limit 00010001h R/W, RO 28h-2Bh PMBU32 Prefetchable Memory Upper 32 Bits 00000000h R/W 2Ch-2Fh PMLU32 Prefetchable Memory Limit Upper 32 Bits 00000000h R/W 34h CAPP Capability List Pointer 50h RO 3Ch-3Dh INTR Interrupt Information 0000h R/W, RO 0000h R/WC, RO, R/W 3Eh-3Fh BCTRL Bridge Control 40h-41h SPDH Secondary PCI Device Hiding 0000h R/W, RO 44h-47h DTC Delayed Transaction Control 00000000h R/W 48h-4Bh BPS Bridge Proprietary Status 00000000h R/WC, RO 4Ch-4Fh BPC Bridge Policy Configuration 00001200h R/W RO SVCAP Subsystem Vendor Capability Pointer SVID Subsystem Vendor IDs 50-51h 54h-57h Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 000Dh RO 00000000 R/WO 365 PCI-to-PCI Bridge Registers (D30:F0) 11.1.1 VID--Vendor Identification Register (PCI-PCI--D30:F0) Offset Address: 00h-01h Default Value: 8086h Bit 15:0 11.1.2 Vendor ID -- RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h. DID--Device Identification Register (PCI-PCI--D30:F0) Bit 15:0 Attribute: Size: RO 16 bits Description Device ID -- RO. This is a 16-bit value assigned to the PCI bridge. Refer to the Intel(R) C600 Series Chipset Specification Update for the value of the Device ID Register. PCICMD--PCI Command (PCI-PCI--D30:F0) Offset Address: 04h-05h Default Value: 0000h Bit 15:11 10 366 RO 16 bits Description Offset Address: 02h-03h Default Value: See bit description 11.1.3 Attribute: Size: Attribute: Size: R/W, RO 16 bits Description Reserved Interrupt Disable (ID) -- RO. Hardwired to 0. The PCI bridge has no interrupts to disable 9 Fast Back to Back Enable (FBE) -- RO. Hardwired to 0, per the PCI Express* Base Specification, Revision 1.0a. 8 SERR# Enable (SERR_EN) -- R/W. 0 = Disable. 1 = Enable the PCH to generate an NMI (or SMI# if NMI routed to SMI#) when the D30:F0 SSE bit (offset 06h, bit 14) is set. 7 Wait Cycle Control (WCC) -- RO. Hardwired to 0, per the PCI Express* Base Specification, Revision 1.0a. 6 Parity Error Response (PER) -- R/W. 0 = The PCH ignores parity errors on the PCI bridge. 1 = The PCH will set the SSE bit (D30:F0, offset 06h, bit 14) when parity errors are detected on the PCI bridge. 5 VGA Palette Snoop (VPS) -- RO. Hardwired to 0, per the PCI Express* Base Specification, Revision 1.0a. 4 Memory Write and Invalidate Enable (MWE) -- RO. Hardwired to 0, per the PCI Express* Base Specification, Revision 1.0a 3 Special Cycle Enable (SCE) -- RO. Hardwired to 0, per the PCI Express* Base Specification, Revision 1.0a and the PCI- to-PCI Bridge Specification. 2 Bus Master Enable (BME) -- R/W. 0 = Disable 1 = Enable. Allows the PCI-to-PCI bridge to accept cycles from PCI. 1 Memory Space Enable (MSE) -- R/W. Controls the response as a target for memory cycles targeting PCI. 0 = Disable 1 = Enable 0 I/O Space Enable (IOSE) -- R/W. Controls the response as a target for I/O cycles targeting PCI. 0 = Disable 1 = Enable Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI-to-PCI Bridge Registers (D30:F0) 11.1.4 PSTS--PCI Status Register (PCI-PCI--D30:F0) Offset Address: 06h-07h Default Value: 0010h Note: Attribute: Size: R/WC, RO 16 bits For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit Description 15 Detected Parity Error (DPE) -- R/WC. 0 = Parity error Not detected. 1 = Indicates that the PCH detected a parity error on the internal backbone. This bit gets set even if the Parity Error Response bit (D30:F0:04 bit 6) is not set. Signaled System Error (SSE) -- R/WC. Several internal and external sources of the bridge can cause SERR#. The first class of errors is parity errors related to the backbone. The PCI bridge captures generic data parity errors (errors it finds on the backbone) as well as errors returned on backbone cycles where the bridge was the master. If either of these two conditions is met, and the primary side of the bridge is enabled for parity error response, SERR# will be captured as shown below. As with the backbone, the PCI bus captures the same sets of errors. The PCI bridge captures generic data parity errors (errors it finds on PCI) as well as errors returned on PCI cycles where the bridge was the master. If either of these two conditions is met, and the secondary side of the bridge is enabled for parity error response, SERR# will be captured as shown below. 14 The final class of errors is system bus errors. There are three status bits associated with system bus errors, each with a corresponding enable. The diagram capturing this is shown below. After checking for the three above classes of errors, an SERR# is generated, and PSTS.SSE logs the generation of SERR#, if CMD.SEE (D30:F0:04, bit 8) is set, as shown below. 13 Received Master Abort (RMA) -- R/WC. 0 = No master abort received. 1 = Set when the bridge receives a master abort status from the backbone. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 367 PCI-to-PCI Bridge Registers (D30:F0) Bit 12 Received Target Abort (RTA) -- R/WC. 0 = No target abort received. 1 = Set when the bridge receives a target abort status from the backbone. 11 Signaled Target Abort (STA) -- R/WC. 0 = No signaled target abort 1 = Set when the bridge generates a completion packet with target abort status on the backbone. 10:9 8 7:5 Reserved. Data Parity Error Detected (DPD) -- R/WC. 0 = Data parity error Not detected. 1 = Set when the bridge receives a completion packet from the backbone from a previous request, and detects a parity error, and CMD.PERE is set (D30:F0:04 bit 6). Reserved. 4 Capabilities List (CLIST) -- RO. Hardwired to 1. Capability list exist on the PCI bridge. 3 Interrupt Status (IS) -- RO. Hardwired to 0. The PCI bridge does not generate interrupts. 2:0 11.1.5 Description Reserved RID--Revision Identification Register (PCI-PCI--D30:F0) Offset Address: 08h Default Value: See bit description Attribute: Size: Bit 7:0 11.1.6 Description (R) Revision ID -- RO. Refer to the Intel C600 Series Chipset and Intel(R) X79 Express Chipset Specification Update for the value of the Revision ID Register CC--Class Code Register (PCI-PCI--D30:F0) Offset Address: 09h-0Bh Default Value: 060401h Bit 23:16 15:8 7:0 11.1.7 Attribute: Size: RO 24 bits Description Base Class Code (BCC) -- RO. Hardwired to 06h. Indicates this is a bridge device. Sub Class Code (SCC) -- RO. Hardwired to 04h. Indicates this device is a PCI-to-PCI bridge. Programming Interface (PI) -- RO. Hardwired to 01h. Indicates the bridge is subtractive decode PMLT--Primary Master Latency Timer Register (PCI-PCI--D30:F0) Offset Address: 0Dh Default Value: 00h Bit 368 RO 8 bits Attribute: Size: RO 8 bits Description 7:3 Master Latency Timer Count (MLTC) -- RO. Reserved per the PCI Express* Base Specification, Revision 1.0a. 2:0 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI-to-PCI Bridge Registers (D30:F0) 11.1.8 HEADTYP--Header Type Register (PCI-PCI--D30:F0) Offset Address: 0Eh Default Value: 01h Bit 7 6:0 11.1.9 RO 8 bits Description Multi-Function Device (MFD) -- RO. `0' indicates a single function device Header Type (HTYPE) -- RO. This 7-bit field identifies the header layout of the configuration space, which is a PCI-to-PCI bridge in this case. BNUM--Bus Number Register (PCI-PCI--D30:F0) Offset Address: 18h-1Ah Default Value: 000000h Bit 23:16 15:8 7:0 11.1.10 Attribute: Size: Attribute: Size: R/W 24 bits Description Subordinate Bus Number (SBBN) -- R/W. Indicates the highest PCI bus number below the bridge. Secondary Bus Number (SCBN) -- R/W. Indicates the bus number of PCI. Primary Bus Number (PBN) -- R/W. This field is default to 00h. In a multiple-PCH system, programmable PBN allows an PCH to be located on any bus. System configuration software is responsible for initializing these registers to appropriate values. PBN is not used by hardware in determining its bus number. SMLT--Secondary Master Latency Timer Register (PCI-PCI--D30:F0) Offset Address: 1Bh Default Value: 00h Attribute: Size: R/W 8 bits This timer controls the amount of time the PCH PCI-to-PCI bridge will burst data on its secondary interface. The counter starts counting down from the assertion of FRAME#. If the grant is removed, then the expiration of this counter will result in the deassertion of FRAME#. If the grant has not been removed, then the PCH PCI-to-PCI bridge may continue ownership of the bus. Bit Description 7:3 Master Latency Timer Count (MLTC) -- R/W. This 5-bit field indicates the number of PCI clocks, in 8-clock increments, that the PCH remains as master of the bus. 2:0 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 369 PCI-to-PCI Bridge Registers (D30:F0) 11.1.11 IOBASE_LIMIT--I/O Base and Limit Register (PCI-PCI--D30:F0) Offset Address: 1Ch-1Dh Default Value: 0000h Attribute: Size: Bit 15:12 11.1.12 Description I/O Limit Address Limit bits[15:12] -- R/W. I/O Base bits corresponding to address lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to FFFh. 11:8 I/O Limit Address Capability (IOLC) -- RO. Indicates that the bridge does not support 32-bit I/O addressing. 7:4 I/O Base Address (IOBA) -- R/W. I/O Base bits corresponding to address lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to 000h. 3:0 I/O Base Address Capability (IOBC) -- RO. Indicates that the bridge does not support 32-bit I/O addressing. SECSTS--Secondary Status Register (PCI-PCI--D30:F0) Offset Address: 1Eh-1Fh Default Value: 0280h Note: Attribute: Size: R/WC, RO 16 bits For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit Description 15 Detected Parity Error (DPE) -- R/WC. 0 = Parity error not detected. 1 = PCH PCI bridge detected an address or data parity error on the PCI bus 14 Received System Error (RSE) -- R/WC. 0 = SERR# assertion not received 1 = SERR# assertion is received on PCI. 13 Received Master Abort (RMA) -- R/WC. 0 = No master abort. 1 = This bit is set whenever the bridge is acting as an initiator on the PCI bus and the cycle is master-aborted. For Processor/PCH interface packets that have completion required, this must also cause a target abort to be returned and sets PSTS.STA. (D30:F0:06 bit 11) 12 Received Target Abort (RTA) -- R/WC. 0 = No target abort. 1 = This bit is set whenever the bridge is acting as an initiator on PCI and a cycle is target-aborted on PCI. For Processor/PCH interface packets that have completion required, this event must also cause a target abort to be returned, and sets PSTS.STA. (D30:F0:06 bit 11). 11 Signaled Target Abort (STA) -- R/WC. 0 = No target abort. 1 = This bit is set when the bridge is acting as a target on the PCI Bus and signals a target abort. 10:9 DEVSEL# Timing (DEVT) -- RO. 01h = Medium decode timing. 8 Data Parity Error Detected (DPD) -- R/WC. 0 = Conditions described below not met. 1 = The PCH sets this bit when all of the following three conditions are met: * The bridge is the initiator on PCI. * PERR# is detected asserted or a parity error is detected internally * BCTRL.PERE (D30:F0:3E bit 0) is set. 7 Fast Back to Back Capable (FBC) -- RO. Hardwired to 1 to indicate that the PCI to PCI target logic is capable of receiving fast back-to-back cycles. 6 Reserved 5 66 MHz Capable (66MHZ_CAP) -- RO. Hardwired to 0. This bridge is 33 MHz capable only. 4:0 370 R/W, RO 16 bits Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI-to-PCI Bridge Registers (D30:F0) 11.1.13 MEMBASE_LIMIT--Memory Base and Limit Register (PCI-PCI--D30:F0) Offset Address: 20h-23h Default Value: 00000000h Attribute: Size: R/W 32 bits This register defines the base and limit, aligned to a 1-MB boundary, of the nonprefetchable memory area of the bridge. Accesses that are within the ranges specified in this register will be sent to PCI if CMD.MSE is set. Accesses from PCI that are outside the ranges specified will be accepted by the bridge if CMD.BME is set. Bit 31:20 Memory Limit (ML) -- R/W. These bits are compared with bits 31:20 of the incoming address to determine the upper 1-MB aligned value (exclusive) of the range. The incoming address must be less than this value. 19:16 Reserved 15:4 3:0 11.1.14 Description Memory Base (MB) -- R/W. These bits are compared with bits 31:20 of the incoming address to determine the lower 1-MB aligned value (inclusive) of the range. The incoming address must be greater than or equal to this value. Reserved PREF_MEM_BASE_LIMIT--Prefetchable Memory Base and Limit Register (PCI-PCI--D30:F0) Offset Address: 24h-27h Default Value: 00010001h Attribute: Size: R/W, RO 32-bit Defines the base and limit, aligned to a 1-MB boundary, of the prefetchable memory area of the bridge. Accesses that are within the ranges specified in this register will be sent to PCI if CMD.MSE is set. Accesses from PCI that are outside the ranges specified will be accepted by the bridge if CMD.BME is set. Bit Description 31:20 Prefetchable Memory Limit (PML) -- R/W. These bits are compared with bits 31:20 of the incoming address to determine the upper 1-MB aligned value (exclusive) of the range. The incoming address must be less than this value. 19:16 64-bit Indicator (I64L) 15:4 3:0 11.1.15 -- RO. Indicates support for 64-bit addressing. Prefetchable Memory Base (PMB) -- R/W. These bits are compared with bits 31:20 of the incoming address to determine the lower 1-MB aligned value (inclusive) of the range. The incoming address must be greater than or equal to this value. 64-bit Indicator (I64B) -- RO. Indicates support for 64-bit addressing. PMBU32--Prefetchable Memory Base Upper 32 Bits Register (PCI-PCI--D30:F0) Offset Address: 28h-2Bh Default Value: 00000000h Bit 31:0 Attribute: Size: R/W 32 bits Description Prefetchable Memory Base Upper Portion (PMBU) -- R/W. Upper 32-bits of the prefetchable address base. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 371 PCI-to-PCI Bridge Registers (D30:F0) 11.1.16 PMLU32--Prefetchable Memory Limit Upper 32 Bits Register (PCI-PCI--D30:F0) Offset Address: 2C-2Fh Default Value: 00000000h Bit 31:0 11.1.17 Prefetchable Memory Limit Upper Portion (PMLU) -- R/W. Upper 32-bits of the prefetchable address limit. CAPP--Capability List Pointer Register (PCI-PCI--D30:F0) Bit 7:0 RO 8 bits Capabilities Pointer (PTR) -- RO. Indicates that the pointer for the first entry in the capabilities list is at 50h in configuration space. INTR--Interrupt Information Register (PCI-PCI--D30:F0) Bit 15:8 7:0 Attribute: Size: R/W, RO 16 bits Description Interrupt Pin (IPIN) -- RO. The PCI bridge does not assert an interrupt. Interrupt Line (ILINE) -- R/W. Software written value to indicate which interrupt line (vector) the interrupt is connected to. No hardware action is taken on this register. Since the bridge does not generate an interrupt, BIOS should program this value to FFh as per the PCI bridge specification. BCTRL--Bridge Control Register (PCI-PCI--D30:F0) Offset Address: 3Eh-3Fh Default Value: 0000h Bit 15:12 372 Attribute: Size: Description Offset Address: 3Ch-3Dh Default Value: 0000h 11.1.19 R/W 32 bits Description Offset Address: 34h Default Value: 50h 11.1.18 Attribute: Size: Attribute: Size: R/WC, RO, R/W 16 bits Description Reserved 11 Discard Timer SERR# Enable (DTE) -- R/W. Controls the generation of SERR# on the primary interface in response to the DTS bit being set: 0 = Do not generate SERR# on a secondary timer discard 1 = Generate SERR# in response to a secondary timer discard 10 Discard Timer Status (DTS) -- R/WC. This bit is set to 1 when the secondary discard timer (see the SDT bit below) expires for a delayed transaction in the hard state. 9 Secondary Discard Timer (SDT) -- R/W. This bit sets the maximum number of PCI clock cycles that the PCH waits for an initiator on PCI to repeat a delayed transaction request. The counter starts once the delayed transaction data is has been returned by the system and is in a buffer in the PCH PCI bridge. If the master has not repeated the transaction at least once before the counter expires, the PCH PCI bridge discards the transaction from its queue. 0 = The PCI master timeout value is between 215 and 216 PCI clocks 1 = The PCI master timeout value is between 210 and 211 PCI clocks 8 Primary Discard Timer (PDT) -- R/W. This bit is R/W for software compatibility only. 7 Fast Back to Back Enable (FBE) -- RO. Hardwired to 0. The PCI logic will not generate fast backto-back cycles on the PCI bus. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI-to-PCI Bridge Registers (D30:F0) Bit Description 6 Secondary Bus Reset (SBR) -- R/W. Controls PCIRST# assertion on PCI. 0 = Bridge deasserts PCIRST# 1 = Bridge asserts PCIRST#. When PCIRST# is asserted, the delayed transaction buffers, posting buffers, and the PCI bus are initialized back to reset conditions. The rest of the part and the configuration registers are not affected. 5 Master Abort Mode (MAM) -- R/W. Controls the PCH PCI bridge's behavior when a master abort occurs: Master Abort on Processor /PCH Interconnect (DMI): 0 = Bridge asserts TRDY# on PCI. It drives all 1s for reads, and discards data on writes. 1 = Bridge returns a target abort on PCI. Master Abort PCI (non-locked cycles): 0 = Normal completion status will be returned on the Processor/PCH interconnect. 1 = Target abort completion status will be returned on the Processor/PCH interconnect. Note: All locked reads will return a completer abort completion status on the Processor/PCH interconnect. 4 VGA 16-Bit Decode (V16D) -- R/W. Enables the PCH PCI bridge to provide 16-bits decoding of VGA I/O address precluding the decode of VGA alias addresses every 1 KB. This bit requires the VGAE bit in this register be set. 3 VGA Enable (VGAE) -- R/W. When set to a 1, the PCH PCI bridge forwards the following transactions to PCI regardless of the value of the I/O base and limit registers. The transactions are qualified by CMD.MSE (D30:F0:04 bit 1) and CMD.IOSE (D30:F0:04 bit 0) being set. * Memory addresses: 000A0000h-000BFFFFh * I/O addresses: 3B0h-3BBh and 3C0h-3DFh. For the I/O addresses, bits [63:16] of the address must be 0, and bits [15:10] of the address are ignored (that is, aliased). The same holds true from secondary accesses to the primary interface in reverse. That is, when the bit is 0, memory and I/O addresses on the secondary interface between the above ranges will be claimed. 2 ISA Enable (IE) -- R/W. This bit only applies to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of PCI I/O space. If this bit is set, the PCH PCI bridge will block any forwarding from primary to secondary of I/O transactions addressing the last 768 bytes in each 1-KB block (offsets 100h to 3FFh). 1 SERR# Enable (SEE) -- R/W. Controls the forwarding of secondary interface SERR# assertions on the primary interface. When set, the PCI bridge will forward SERR# pin. * SERR# is asserted on the secondary interface. * This bit is set. * CMD.SEE (D30:F0:04 bit 8) is set. 0 Parity Error Response Enable (PERE) -- R/W. 0 = Disable 1 = The PCH PCI bridge is enabled for parity error reporting based on parity errors on the PCI bus. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 373 PCI-to-PCI Bridge Registers (D30:F0) 11.1.20 SPDH--Secondary PCI Device Hiding Register (PCI-PCI--D30:F0) Offset Address: 40h-41h Default Value: 0000h Attribute: Size: R/W, RO 16 bits This register allows software to hide the PCI devices, either plugged into slots or on the motherboard. Bit 15:4 11.1.21 Description Reserved 3 Hide Device 3 (HD3) -- R/W, RO. Same as bit 0 of this register, except for device 3 (AD[19]) 2 Hide Device 2 (HD2) -- R/W, RO. Same as bit 0 of this register, except for device 2 (AD[18]) 1 Hide Device 1 (HD1) -- R/W, RO. Same as bit 0 of this register, except for device 1 (AD[17]) 0 Hide Device 0 (HD0) -- R/W, RO. 0 = The PCI configuration cycles for this slot are not affected. 1 = The PCH hides device 0 on the PCI bus. This is done by masking the IDSEL (keeping it low) for configuration cycles to that device. Since the device will not see its IDSEL go active, it will not respond to PCI configuration cycles and the processor will think the device is not present. AD[16] is used as IDSEL for device 0. DTC--Delayed Transaction Control Register (PCI-PCI--D30:F0) Offset Address: 44h-47h Default Value: 00000000h R/W 32 bits Bit Description 31 Discard Delayed Transactions (DDT) -- R/W. 0 = Logged delayed transactions are kept. 1 = The PCH PCI bridge will discard any delayed transactions it has logged. This includes transactions in the pending queue, and any transactions in the active queue, whether in the hard or soft DT state. The prefetchers will be disabled and return to an idle state. Note: If a transaction is running on PCI at the time this bit is set, that transaction will continue until either the PCI master disconnects (by deasserting FRAME#) or the PCI bridge disconnects (by asserting STOP#). This bit is cleared by the PCI bridge when the delayed transaction queues are empty and have returned to an idle state. Software sets this bit and polls for its completion 30 Block Delayed Transactions (BDT) -- R/W. 0 = Delayed transactions accepted 1 = The PCH PCI bridge will not accept incoming transactions which will result in delayed transactions. It will blindly retry these cycles by asserting STOP#. All postable cycles (memory writes) will still be accepted. 29:8 7:6 374 Attribute: Size: Reserved Maximum Delayed Transactions (MDT) -- R/W. Controls the maximum number of delayed transactions that the PCH PCI bridge will run. Encodings are: 00 =) 2 Active, 5 pending 01 =) 2 active, no pending 10 =) 1 active, no pending 11 =) Reserved 5 Reserved 4 Auto Flush After Disconnect Enable (AFADE) -- R/W. 0 = The PCI bridge will retain any fetched data until required to discard by producer/consumer rules. 1 = The PCI bridge will flush any prefetched data after either the PCI master (by deasserting FRAME#) or the PCI bridge (by asserting STOP#) disconnects the PCI transfer. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI-to-PCI Bridge Registers (D30:F0) 11.1.22 Bit Description 3 Never Prefetch (NP) -- R/W. 0 = Prefetch enabled 1 = The PCH will only fetch a single DW and will not enable prefetching, regardless of the command being an Memory read (MR), Memory read line (MRL), or Memory read multiple (MRM). 2 Memory Read Multiple Prefetch Disable (MRMPD) -- R/W. 0 = MRM commands will fetch multiple cache lines as defined by the prefetch algorithm. 1 = Memory read multiple (MRM) commands will fetch only up to a single, 64-byte aligned cache line. 1 Memory Read Line Prefetch Disable (MRLPD) -- R/W. 0 = MRL commands will fetch multiple cache lines as defined by the prefetch algorithm. 1 = Memory read line (MRL) commands will fetch only up to a single, 64-byte aligned cache line. 0 Memory Read Prefetch Disable (MRPD) -- R/W. 0 = MR commands will fetch up to a 64-byte aligned cache line. 1 = Memory read (MR) commands will fetch only a single DW. BPS--Bridge Proprietary Status Register (PCI-PCI--D30:F0) Offset Address: 48h-4Bh Default Value: 00000000h Bit 31:17 16 15:7 Attribute: Size: R/WC, RO 32 bits Description Reserved PERR# Assertion Detected (PAD) -- R/WC. This bit is set by hardware whenever the PERR# pin is asserted on the rising edge of PCI clock. This includes cases in which the chipset is the agent driving PERR#. It remains asserted until cleared by software writing a 1 to this location. When enabled by the PERR#-to-SERR# Enable bit (in the Bridge Policy Configuration register), a 1 in this bit can generate an internal SERR# and be a source for the NMI logic. This bit can be used by software to determine the source of a system problem. Reserved 6:4 Number of Pending Transactions (NPT) -- RO. This read-only indicator tells debug software how many transactions are in the pending queue. Possible values are: 000 = No pending transaction 001 = 1 pending transaction 010 = 2 pending transactions 011 = 3 pending transactions 100 = 4 pending transactions 101 = 5 pending transactions 110-111 = Reserved Note: This field is not valid if DTC.MDT (offset 44h:bits 7:6) is any value other than `00'. 3:2 Reserved 1:0 Number of Active Transactions (NAT) -- RO. This read-only indicator tells debug software how many transactions are in the active queue. Possible values are: 00 = No active transactions 01 = 1 active transaction 10 = 2 active transactions 11 = Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 375 PCI-to-PCI Bridge Registers (D30:F0) 11.1.23 BPC--Bridge Policy Configuration Register (PCI-PCI--D30:F0) Offset Address: 4Ch-4Fh Default Value: 00001200h Attribute: Size: Bit 31:30 R/W 32 bits Description Reserved 29 Subtractive Decode Compatibility Device ID (SDCDID) -- R/W: When '0', this function shall report a Device ID of 244Eh. When set to '1', this function shall report the device Device ID value assigned to the PCI-to-PCI Bridge in the Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Specification Update. If subtractive decode (SDE) is enabled, having this bit as '0' allows the function to present a Device ID that is recognized by the OS. 28 Subtractive Decode Enable (SDE) -- R/W: 0 = Subtractive decode is disabled this function and will only claim transactions positively. 1 = The subtractive decode policy as listed in SDP below applies. Software must ensure that only one PCH device is enabled for Subtractive decode at a time. 27:14 13:8 Reserved Upstream Read Latency Threshold (URLT) -- R/W: This field specifies the number of PCI clocks after internally enqueuing an upstream memory read request at which point the PCI target logic should insert wait states in order to optimize lead-off latency. When the master returns after this threshold has been reached and data has not arrived in the Delayed Transaction completion queue, then the PCI target logic will insert wait states instead of immediately retrying the cycle. The PCI target logic will insert up to 16 clocks of target initial latency (from FRAME# assertion to TRDY# or STOP# assertion) before retrying the PCI read cycle (if the read data has not arrived yet). Note that the starting event for this Read Latency Timer is not explicitly visible externally. A value of 0h disables this policy completely such that wait states will never be inserted on the read lead-off data phase. The default value (12h) specifies 18 PCI clocks (540 ns) and is approximately 4 clocks less than the typical idle lead-off latency expected for desktop PCH systems. This value may need to be changed by BIOS, depending on the platform. Subtractive Decode Policy (SDP) -- R/W. 0 = The PCI bridge always forwards memory and I/O cycles that are not claimed by any other device on the backbone (primary interface) to the PCI bus (secondary interface). 1 = The PCI bridge will not claim and forward memory or I/O cycles at all unless the corresponding Space Enable bit is set in the Command register. Note: The Boot BIOS Destination Selection strap can force the BIOS accesses to PCI. 7 BPC.SDP Range Forwarding Policy 0 0 Don't Care Forward unclaimed cycles 0 1 Don't Care Forwarding Prohibited 1 X Within range Positive decode and forward 1 X Outside Subtractive decode & forward 6 PERR#-to-SERR# Enable (PSE) -- R/W. When this bit is set, a 1 in the PERR# Assertion status bit (in the Bridge Proprietary Status register) will result in an internal SERR# assertion on the primary side of the bridge (if also enabled by the SERR# Enable bit in the primary Command register). SERR# is a source of NMI. 5 Secondary Discard Timer Testmode (SDTT) -- R/W. 0 = The secondary discard timer expiration will be defined in BCTRL.SDT (D30:F0:3E, bit 9) 1 = The secondary discard timer will expire after 128 PCI clocks. 4:3 2 376 CMD.MSE Reserved Peer Decode Enable (PDE) -- R/W. 0 = The PCI bridge assumes that all memory cycles target main memory, and all I/O cycles are not claimed. 1 = The PCI bridge will perform peer decode on any memory or I/O cycle from PCI that falls outside of the memory and I/O window registers 1 Reserved 0 Received Target Abort SERR# Enable (RTAE) -- R/W. When set, the PCI bridge will report SERR# when PSTS.RTA (D30:F0:06 bit 12) or SSTS.RTA (D30:F0:1E bit 12) are set, and CMD.SEE (D30:F0:04 bit 8) is set. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI-to-PCI Bridge Registers (D30:F0) 11.1.24 SVCAP--Subsystem Vendor Capability Register (PCI-PCI--D30:F0) Offset Address: 50h-51h Default Value: 000Dh Bit 15:8 7:0 11.1.25 Attribute: Size: RO 16 bits Description Next Capability (NEXT) -- RO. Value of 00h indicates this is the last item in the list. Capability Identifier (CID) -- RO. Value of 0Dh indicates this is a PCI bridge subsystem vendor capability. SVID--Subsystem Vendor IDs Register (PCI-PCI--D30:F0) Offset Address: 54h-57h Default Value: 00000000h Bit Attribute: Size: R/WO 32 bits Description 31:16 Subsystem Identifier (SID) -- R/WO. Indicates the subsystem as identified by the vendor. This field is write once and is locked down until a bridge reset occurs (not the PCI bus reset). 15:0 Subsystem Vendor Identifier (SVID) -- R/WO. Indicates the manufacturer of the subsystem. This field is write once and is locked down until a bridge reset occurs (not the PCI bus reset). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 377 PCI-to-PCI Bridge Registers (D30:F0) 378 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Gigabit LAN Configuration Registers 12 Gigabit LAN Configuration Registers 12.1 Gigabit LAN Configuration Registers (Gigabit LAN -- D25:F0) Note: Refer to the Intel 82579 datasheet for additional LAN Configuration Status Register information. Note: Register address locations that are not shown in Table 12-1 should be treated as Reserved. Table 12-1. Gigabit LAN Configuration Registers Address Map (Gigabit LAN --D25:F0) (Sheet 1 of 2) Offset Mnemonic 00h-01h VID 02h-03h DID 04h-05h PCICMD PCI Command 06h-07h PCISTS PCI Status 08h RID Register Name Default Type Vendor Identification 8086h RO Device Identification See register description RO 0000h R/W, RO 0010h R/WC, RO See register description RO Revision Identification 09h-0Bh CC Class Code 020000h RO 0Ch CLS Cache Line Size 00h R/W Primary Latency Timer 00h RO Header Type 00h RO 0Dh PLT 0Eh HEADTYP 10h-13h MBARA Memory Base Address A 00000000h R/W, RO 14h-17h MBARB Memory Base Address B 00000000h R/W, RO 18h-1Bh MBARC Memory Base Address C 00000001h R/W, RO Subsystem Vendor ID See register description RO Subsystem ID See register description RO See register description RO 2Ch-2Dh SVID 2Eh-2Fh SID 30h-33h ERBA Expansion ROM Base Address 34h CAPP Capabilities List Pointer 3Ch-3Dh INTR Interrupt Information 3Eh MLMG Maximum Latency/Minimum Grant C8h-C9h CLIST1 Capabilities List 1 CAh-CBh PMC CCh-CDh PMCS CFh DR D0h-D1h CLIST2 C8h RO See register description R/W, RO 00h RO D001h RO PCI Power Management Capability See register description RO PCI Power Management Control and Status See register description R/WC, R/W, RO Data Register See register description RO E005h R/WO, RO Capabilities List 2 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 379 Gigabit LAN Configuration Registers Table 12-1. Gigabit LAN Configuration Registers Address Map (Gigabit LAN --D25:F0) (Sheet 2 of 2) 12.1.1 Offset Mnemonic Register Name Default Type D2h-D3h MCTL 0080h R/W, RO D4h-D7h MADDL Message Address Low See register description R/W D8h-DBh MADDH Message Address High See register description R/W DCh-DDh MDAT Message Data See register description R/W E0h-E1h FLRCAP Function Level Reset Capability 0009h RO E2h-E3h FLRCLV Function Level Reset Capability Length and Value See register description R/WO, RO E4h-E5h DEVCTRL 0000h R/W, RO Message Control Device Control VID--Vendor Identification Register (Gigabit LAN--D25:F0) Address Offset: 00h-01h Default Value: 8086h Bit 15:0 12.1.2 RO 16 bits Description Vendor ID -- RO. This is a 16-bit value assigned to Intel. The field may be auto-loaded from the NVM at address 0Dh during init time depending on the "Load Vendor/Device ID" bit field in NVM word 0Ah with a default value of 8086h. DID--Device Identification Register (Gigabit LAN--D25:F0) Address Offset: 02h-03h Default Value: See bit description 380 Attribute: Size: Attribute: Size: RO 16 bits Bit Description 15:0 Device ID -- RO. This is a 16-bit value assigned to the PCH Gigabit LAN controller. The field may be auto-loaded from the NVM word 0Dh during initialization time depending on the "Load Vendor/ Device ID" bit field in NVM word 0Ah. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Gigabit LAN Configuration Registers 12.1.3 PCICMD--PCI Command Register (Gigabit LAN--D25:F0) Address Offset: 04h-05h Default Value: 0000h Bit 15:11 10 Attribute: Size: R/W, RO 16 bits Description Reserved Interrupt Disable -- R/W. This disables pin-based INTx# interrupts on enabled Hot-Plug and power management events. This bit has no effect on MSI operation. 0 = Internal INTx# messages are generated if there is an interrupt for Hot-Plug or power management and MSI is not enabled. 1 = Internal INTx# messages will not be generated. This bit does not affect interrupt forwarding from devices connected to the root port. Assert_INTx and Deassert_INTx messages will still be forwarded to the internal interrupt controllers if this bit is set. 9 Fast Back to Back Enable (FBE) -- RO. Hardwired to 0. 8 SERR# Enable (SEE) -- R/W. 0 = Disable 1 = Enables the Gb LAN controller to generate an SERR# message when PSTS.SSE is set. 7 Wait Cycle Control (WCC) -- RO. Hardwired to 0. 6 Parity Error Response (PER) -- R/W. 0 = Disable. 1 = Indicates that the device is capable of reporting parity errors as a master on the backbone. 5 Palette Snoop Enable (PSE) -- RO. Hardwired to 0. 4 Postable Memory Write Enable (PMWE) -- RO. Hardwired to 0. 3 Special Cycle Enable (SCE) -- RO. Hardwired to 0. 2 Bus Master Enable (BME) -- R/W. 0 = Disable. All cycles from the device are master aborted 1 = Enable. Allows the root port to forward cycles onto the backbone from a Gigabit LAN* device. 1 Memory Space Enable (MSE) -- R/W. 0 = Disable. Memory cycles within the range specified by the memory base and limit registers are master aborted on the backbone. 1 = Enable. Allows memory cycles within the range specified by the memory base and limit registers can be forwarded to the Gigabit LAN device. 0 I/O Space Enable (IOSE) -- R/W. This bit controls access to the I/O space registers. 0 = Disable. I/O cycles within the range specified by the I/O base and limit registers are master aborted on the backbone. 1 = Enable. Allows I/O cycles within the range specified by the I/O base and limit registers can be forwarded to the Gigabit LAN device. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 381 Gigabit LAN Configuration Registers 12.1.4 PCISTS--PCI Status Register (Gigabit LAN--D25:F0) Address Offset: 06h-07h Default Value: 0010h Bit Description 15 14 Signaled System Error (SSE) -- R/WC. 0 = No system error signaled. 1 = Set when the Gb LAN controller signals a system error to the internal SERR# logic. 13 Received Master Abort (RMA) -- R/WC. 0 = Root port has not received a completion with unsupported request status from the backbone. 1 = Set when the GbE LAN controller receives a completion with unsupported request status from the backbone. 12 Received Target Abort (RTA) -- R/WC. 0 = Root port has not received a completion with completer abort from the backbone. 1 = Set when the Gb LAN controller receives a completion with completer abort from the backbone. 11 Signaled Target Abort (STA) -- R/WC. 0 = No target abort received. 1 = Set whenever the Gb LAN controller forwards a target abort received from the downstream device onto the backbone. DEVSEL# Timing Status (DEV_STS) -- RO. Hardwired to `0'. 8 Master Data Parity Error Detected (DPED) -- R/WC. 0 = No data parity error received. 1 = Set when the Gb LAN Controller receives a completion with a data parity error on the backbone and PCIMD.PER (D25:F0, bit 6) is set. 7 Fast Back to Back Capable (FB2BC) -- RO. Hardwired to `0'. 6 Reserved 5 66 MHz Capable -- RO. Hardwired to 0. 4 Capabilities List -- RO. Hardwired to 1. Indicates the presence of a capabilities list. 3 Interrupt Status -- RO. Indicates status of Hot-Plug and power management interrupts on the root port that result in INTx# message generation. 0 = Interrupt is de-asserted. 1 = Interrupt is asserted. This bit is not set if MSI is enabled. If MSI is not enabled, this bit is set regardless of the state of PCICMD.Interrupt Disable bit (D25:F0:04h:bit 10). 2:0 Reserved RID--Revision Identification Register (Gigabit LAN--D25:F0) Offset Address: 08h Default Value: See bit description Bit 7:0 382 R/WC, RO 16 bits Detected Parity Error (DPE) -- R/WC. 0 = No parity error detected. 1 = Set when the Gb LAN controller receives a command or data from the backbone with a parity error. This is set even if PCIMD.PER (D25:F0, bit 6) is not set. 10:9 12.1.5 Attribute: Size: Attribute: Size: RO 8 bits Description Revision ID -- RO. Refer to the Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Specification Update for the value of the Revision ID Register Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Gigabit LAN Configuration Registers 12.1.6 CC--Class Code Register (Gigabit LAN--D25:F0) Address Offset: 09h-0Bh Default Value: 020000h Bit 23:0 12.1.7 Class Code-- RO. Identifies the device as an Ethernet Adapter. 020000h = Ethernet Adapter. CLS--Cache Line Size Register (Gigabit LAN--D25:F0) Bit 7:0 Attribute: Size: R/W 8 bits Description Cache Line Size -- R/W. This field is implemented by PCI devices as a read write field for legacy compatibility purposes but has no impact on any device functionality. PLT--Primary Latency Timer Register (Gigabit LAN--D25:F0) Address Offset: 0Dh Default Value: 00h Bit 7:0 12.1.9 RO 24 bits Description Address Offset: 0Ch Default Value: 00h 12.1.8 Attribute: Size: Attribute: Size: RO 8 bits Description Latency Timer (LT) -- RO. Hardwired to 0. HEADTYP--Header Type Register (Gigabit LAN--D25:F0) Address Offset: 0Eh Default Value: 00h Bit 7:0 Attribute: Size: RO 8 bits Description Header Type (HT) -- RO. 00h = Indicates this is a single function device. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 383 Gigabit LAN Configuration Registers 12.1.10 MBARA--Memory Base Address Register A (Gigabit LAN--D25:F0) Address Offset: 10h-13h Default Value: 00000000h Attribute: Size: R/W, RO 32 bits The internal CSR registers and memories are accessed as direct memory mapped offsets from the base address register. SW may only access whole DWord at a time. Bit 31:17 16:4 3 2:1 0 12.1.11 Description Base Address (BA) -- R/W. Software programs this field with the base address of this region. Memory Size (MSIZE) -- R/W. Memory size is 128 KB. Prefetchable Memory (PM) -- RO. The GbE LAN controller does not implement prefetchable memory. Memory Type (MT) -- RO. Set to 00b indicating a 32 bit BAR. Memory / IO Space (MIOS) -- RO. Set to 0 indicating a Memory Space BAR. MBARB--Memory Base Address Register B (Gigabit LAN--D25:F0) Address Offset: 14h-17h Default Value: 00000000h Attribute: Size: R/W, RO 32 bits The internal registers that are used to access the LAN Space in the External FLASH device. Access to these registers are direct memory mapped offsets from the base address register. Software may only access a DWord at a time. Bit 31:12 11:4 3 2:1 0 384 Description Base Address (BA) -- R/W. Software programs this field with the base address of this region. Memory Size (MSIZE) -- R/W. Memory size is 4 KB. Prefetchable Memory (PM) -- RO. The Gb LAN controller does not implement prefetchable memory. Memory Type (MT) -- RO. Set to 00b indicating a 32 bit BAR. Memory / IO Space (MIOS) -- RO. Set to 0 indicating a Memory Space BAR. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Gigabit LAN Configuration Registers 12.1.12 MBARC--Memory Base Address Register C (Gigabit LAN--D25:F0) Address Offset: 18h-1Bh Default Value: 00000001h Attribute: Size: R/W, RO 32 bits Internal registers, and memories, can be accessed using I/O operations. There are two 4B registers in the I/O mapping window: Addr Reg and Data Reg. Software may only access a DWord at a time. Bit 31:5 4:1 0 12.1.13 Description Base Address (BA) -- R/W. Software programs this field with the base address of this region. I/O Size (IOSIZE) -- RO. I/O space size is 32 Bytes. Memory / I/O Space (MIOS) -- RO. Set to 1 indicating an I/O Space BAR. SVID--Subsystem Vendor ID Register (Gigabit LAN--D25:F0) Address Offset: 2Ch-2Dh Default Value: See bit description 12.1.14 RO 16 bits Bit Description 15:0 Subsystem Vendor ID (SVID) -- RO. This value may be loaded automatically from the NVM Word 0Ch upon power up depending on the "Load Subsystem ID" bit field in NVM word 0Ah. A value of 8086h is default for this field upon power up if the NVM does not respond or is not programmed. All functions are initialized to the same value. SID--Subsystem ID Register (Gigabit LAN--D25:F0) Address Offset: 2Eh-2Fh Default Value: See bit description 12.1.15 Attribute: Size: Attribute: Size: RO 16 bits Bit Description 15:0 Subsystem ID (SID) -- RO. This value may be loaded automatically from the NVM Word 0Bh upon power up or reset depending on the "Load Subsystem ID" bit field in NVM word 0Ah with a default value of 0000h. This value is loadable from NVM word location 0Ah. ERBA--Expansion ROM Base Address Register (Gigabit LAN--D25:F0) Address Offset: 30h-33h Default Value: See bit description Attribute: Size: RO 32 bits Bit Description 31:0 Expansion ROM Base Address (ERBA) -- RO. This register is used to define the address and size information for boot-time access to the optional FLASH memory. If no Flash memory exists, this register reports 00000000h. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 385 Gigabit LAN Configuration Registers 12.1.16 CAPP--Capabilities List Pointer Register (Gigabit LAN--D25:F0) Address Offset: 34h Default Value: C8h Bit 7:0 12.1.17 Capabilities Pointer (PTR) -- RO. Indicates that the pointer for the first entry in the capabilities list is at C8h in configuration space. INTR--Interrupt Information Register (Gigabit LAN--D25:F0) Bit 15:8 7:0 R/W, RO 16 bits Interrupt Pin (IPIN) -- RO. Indicates the interrupt pin driven by the GbE LAN controller. 01h = The GbE LAN controller implements legacy interrupts on INTA. Interrupt Line (ILINE) -- R/W. Default = 00h. Software written value to indicate which interrupt line (vector) the interrupt is connected to. No hardware action is taken on this register. MLMG--Maximum Latency/Minimum Grant Register (Gigabit LAN--D25:F0) Bit 7:0 Attribute: Size: RO 8 bits Description Maximum Latency/Minimum Grant (MLMG) -- RO. Not used. Hardwired to 00h. CLIST 1--Capabilities List Register 1 (Gigabit LAN--D25:F0) Address Offset: C8h-C9h Default Value: D001h Bit 15:8 7:0 386 Attribute: Size: Description Address Offset: 3Eh Default Value: 00h 12.1.19 R0 8 bits Description Address Offset: 3Ch-3Dh Default Value: 0100h Function Level Reset: No 12.1.18 Attribute: Size: Attribute: Size: RO 16 bits Description Next Capability (NEXT) -- RO. Value of D0h indicates the location of the next pointer. Capability ID (CID) -- RO. Indicates the linked list item is a PCI Power Management Register. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Gigabit LAN Configuration Registers 12.1.20 PMC--PCI Power Management Capabilities Register (Gigabit LAN--D25:F0) Address Offset: CAh-CBh Default Value: See bit descriptions Function Level Reset: No (Bits 15:11 only) Bit Attribute: Size: RO 16 bits Description PME_Support (PMES) -- RO. This five-bit field indicates the power states in which the function may assert PME#. It depend on PM Ena and AUX-PWR bits in word 0Ah in the NVM: Condition 15:11 Function Value PM Ena=0 No PME at all states 0000b PM Ena & AUX-PWR=0 PME at D0 and D3hot 01001b PM Ena & AUX-PWR=1 PME at D0, D3hot and D3cold 11001b These bits are not reset by Function Level Reset. 10 D2_Support (D2S) -- RO. The D2 state is not supported. 9 D1_Support (D1S) -- RO. The D1 state is not supported. 8:6 Aux_Current (AC) -- RO. Required current defined in the Data Register. 5 Device Specific Initialization (DSI) -- RO. Set to 1. The GbE LAN Controller requires its device driver to be executed following transition to the D0 un-initialized state. 4 Reserved 3 2:0 PME Clock (PMEC) -- RO. Hardwired to 0. Version (VS) -- RO. Hardwired to 010b to indicate support for Revision 1.1 of the PCI Power Management Specification. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 387 Gigabit LAN Configuration Registers 12.1.21 PMCS--PCI Power Management Control and Status Register (Gigabit LAN--D25:F0) Address Offset: CCh-CDh Default Value: See bit description Function Level Reset:No (Bit 8 only) Bit 15 Description PME Status (PMES) -- R/WC. This bit is set to 1 when the function detects a wake-up event independent of the state of the PMEE bit. Writing a 1 will clear this bit. 14:13 12:9 Data Select (DSL) -- R/W. This four-bit field is used to select which data is to be reported through the Data register (offset CFh) and Data_Scale field. These bits are writeable only when the Power Management is enabled using NVM. 0h = D0 Power Consumption 3h = D3 Power Consumption 4h = D0 Power Dissipation 7h = D3 Power Dissipation 8h = Common Power All other values are reserved. 8 PME Enable (PMEE) -- R/W. If Power Management is enabled in the NVM, writing a 1 to this register will enable Wakeup. If Power Management is disabled in the NVM, writing a 1 to this bit has no affect, and will not set the bit to 1. This bit is not reset by Function Level Reset. 3 2 1:0 Reserved - Returns a value of 0000. No Soft Reset (NSR) -- RO. Defines if the device executed internal reset on the transition to D0. the LAN controller always reports 0 in this field. Reserved - Returns a value of 0b. Power State (PS) -- R/W. This field is used both to determine the current power state of the GbE LAN Controller and to set a new power state. The values are: 00 = D0 state (default) 01 = Ignored 10 = Ignored 11 = D3 state (Power Management must be enables in the NVM or this cycle will be ignored). DR--Data Register (Gigabit LAN--D25:F0) Address Offset: CFh Default Value: See bit description 388 R/WC, R/W, RO 16 bits Data Scale (DSC) -- R/W. This field indicates the scaling factor to be used when interpreting the value of the Data register. For the GbE LAN and common functions this field equals 01b (indicating 0.1 watt units) if the PM is enabled in the NVM, and the Data_Select field is set to 0, 3, 4, 7, (or 8 for Function 0). Else it equals 00b. For the manageability functions this field equals 10b (indicating 0.01 watt units) if the PM is enabled in the NVM, and the Data_Select field is set to 0, 3, 4, 7. Else it equals 00b. 7:4 12.1.22 Attribute: Size: Attribute: Size: RO 8 bits Bit Description 7:0 Reported Data (RD) -- RO. This register is used to report power consumption and heat dissipation. This register is controlled by the Data_Select field in the PMCS (Offset CCh, bits 12:9), and the power scale is reported in the Data_Scale field in the PMCS (Offset CCh, bits 14:13). The data of this field is loaded from the NVM if PM is enabled in the NVM or with a default value of 00h otherwise. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Gigabit LAN Configuration Registers 12.1.23 CLIST 2--Capabilities List Register 2 (Gigabit LAN--D25:F0) Address Offset: D0h-D1h Default Value: E005h Function Level Reset: No (Bits 15:8 only) Bit 15:8 7:0 12.1.24 Next Capability (NEXT) -- R/WO. Value of E0h points to the Function Level Reset capability structure. These bits are not reset by Function Level Reset. Capability ID (CID) -- RO. Indicates the linked list item is a Message Signaled Interrupt Register. MCTL--Message Control Register (Gigabit LAN--D25:F0) Bit 15:8 7 Attribute: Size: R/W, RO 16 bits Description Reserved 64-bit Capable (CID) -- RO. Set to 1 to indicate that the GbE LAN Controller is capable of generating 64-bit message addresses. 6:4 Multiple Message Enable (MME) -- RO. Returns 000b to indicate that the GbE LAN controller only supports a single message. 3:1 Multiple Message Capable (MMC) -- RO. The GbE LAN controller does not support multiple messages. 0 MSI Enable (MSIE) -- R/W. 0 = MSI generation is disabled. 1 = The Gb LAN controller will generate MSI for interrupt assertion instead of INTx signaling. MADDL--Message Address Low Register (Gigabit LAN--D25:F0) Address Offset: D4h-D7h Default Value: See bit description Bit 31:0 12.1.26 R/WO, RO 16 bits Description Address Offset: D2h-D3h Default Value: 0080h 12.1.25 Attribute: Size: Attribute: Size: R/W 32 bits Description Message Address Low (MADDL) -- R/W. Written by the system to indicate the lower 32 bits of the address to use for the MSI memory write transaction. The lower two bits will always return 0 regardless of the write operation. MADDH--Message Address High Register (Gigabit LAN--D25:F0) Address Offset: D8h-DBh Default Value: See bit description Attribute: Size: R/W 32 bits Bit Description 31:0 Message Address High (MADDH) -- R/W. Written by the system to indicate the upper 32 bits of the address to use for the MSI memory write transaction. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 389 Gigabit LAN Configuration Registers 12.1.27 MDAT--Message Data Register (Gigabit LAN--D25:F0) Address Offset: DCh-DDh Default Value: See bit description Bit 31:0 12.1.28 Attribute: Size: Description Message Data (MDAT) -- R/W. Written by the system to indicate the lower 16 bits of the data written in the MSI memory write DWORD transaction. The upper 16 bits of the transaction are written as 0000h. FLRCAP--Function Level Reset Capability (Gigabit LAN--D25:F0) Address Offset: E0h-E1h Default Value: 0009h Bit 15:8 7:0 12.1.29 R/W 16 bits Attribute: Size: RO 16 bits Description Next Pointer -- RO. This field provides an offset to the next capability item in the capability list. The value of 00h indicates the last item in the list. Capability ID -- RO. The value of this field depends on the FLRCSSEL bit. 13h = If FLRCSSEL = 0 09h = If FLRCSSEL = 1, indicating vendor specific capability. FLRCLV--Function Level Reset Capability Length and Version (Gigabit LAN--D25:F0) Address Offset: E2h-E3h Attribute: R/WO, RO Default Value: See Description. Size: 16 bits Function Level Reset: No (Bits 9:8 Only When FLRCSSEL = 0) When FLRCSSEL = 0, this register is defined as follows: Bit 15:10 Description Reserved. 9 Function Level Reset Capability -- R/WO. 1 = Support for Function Level Reset. This bit is not reset by Function Level Reset. 8 TXP Capability -- R/WO. 1 = Indicates support for the Transactions Pending (TXP) bit. TXP must be supported if FLR is supported. 7:0 Capability Length -- RO. The value of this field indicates the number of bytes of the vendor specific capability as require by the PCI spec. It has the value of 06h for the Function Level Reset capability. When FLRCSSEL = 1, this register is defined as follows: Bit 15:12 390 Description Vendor Specific Capability ID -- RO. A value of 2h in this field identifies this capability as Function Level Reset. 11:8 Capability Version-- RO. The value of this field indicates the version of the Function Level Reset Capability. Default is 0h. 7:0 Capability Length -- RO. The value of this field indicates the number of bytes of the vendor specific capability as require by the PCI spec. It has the value of 06h for the Function Level Reset capability. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Gigabit LAN Configuration Registers 12.1.30 1 DEVCTRL--Device Control (Gigabit LAN--D25:F0) Address Offset: E4-E5h Default Value: 0000h Attribute: Size: Bit 15:9 8 7:1 0 12.2 R/W, RO 16 bits Description Reserved. Transactions Pending (TXP) -- R/W. 1 = Indicates the controller has issued Non-Posted requests which have not been completed. 0 = Indicates that completions for all Non-Posted requests have been received. Reserved Initiate Function Level Reset -- RO. This bit is used to initiate an FLT transition. A write of 1 initiates the transition. Since hardware must not respond to any cycles until Function Level Reset completion, the value read by software from this bit is 0. Gigabit LAN Capabilities and Status Registers (CSR) The internal CSR registers and memories are accessed as direct memory mapped offsets from the base address register in Section 12.1.10. Software may only access whole DWord at a time. Note: Register address locations that are not shown in Table 12-2 should be treated as Reserved. Table 12-2. Gigabit LAN Capabilities and Status Registers Address Map (Gigabit LAN --MBARA) 12.2.1 MBARA + Offset Mnemonic 00h-03h GBECSR1 18h-1Bh Register Name Default Attribute Gigabit Ethernet Capabilities and Status Register 1 00100241h R/W GBECSR2 Gigabit Ethernet Capabilities and Status Register 2 01501000h R/W/SN 20h-23h GBECSR3 Gigabit Ethernet Capabilities and Status Register 3 1000XXXXh R/W/V 2Ch-2Fh GBECSR4 Gigabit Ethernet Capabilities and Status Register 4 00000000h R/W F00h-F03h GBECSR5 Gigabit Ethernet Capabilities and Status Register 5 00010008h R/W/V F10h-F13h GBECSR6 Gigabit Ethernet Capabilities and Status Register 6 0004000Ch R/W/SN 5400h-5403h GBECSR7 Gigabit Ethernet Capabilities and Status Register 7 XXXXXXXXh R/W 5404h-5407h GBECSR8 Gigabit Ethernet Capabilities and Status Register 8 XXXXXXXXh R/W 5800h-5803h GBECSR9 Gigabit Ethernet Capabilities and Status Register 9 00000008h R/W/SN GBECSR1--Gigabit Ethernet Capabilities and Status Register 1 Address Offset: MBARA + 00h Default Value: 00100241h Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Attribute: Size: R/W 32 bit 391 Gigabit LAN Configuration Registers Bit 31:25 24 23:0 12.2.2 Description Reserved PHY Power Down (PHYPDN) -- R/W. When cleared (0b), the PHY power down setting is controlled by the internal logic of PCH. Reserved GBECSR2--Gigabit Ethernet Capabilities and Status Register 2 Address Offset: MBARA + 18h Default Value: 01501000h Bit 31:21 20 19:0 12.2.3 Reserved PHY Power Down Enable (PHYPDEN) -- R/W/SN. When set, this bit enables the PHY to enter a low-power state when the LAN controller is at the DMoff/D3 or with no WOL. Reserved GBECSR3--Gigabit Ethernet Capabilities and Status Register 3 Bit 31:29 28 Attribute: Size: Reserved Ready Bit (RB) -- R/W/V. Set to 1 by the Gigabit Ethernet Controller at the end of the MDI transaction. This bit should be reset to 0 by software at the same time the command is written. 27:26 25:21 LAN Connected Device Address (PHYADD) -- R/W/V. 15:0 R/W/V 32 bit Description MDI Type -- R/W/V. 01 = MDI Write 10 = MDI Read All other values are reserved. 20:16 LAN Connected Device Register Address (PHYREGADD) -- R/W/V. DATA -- R/W/V. GBECSR4--Gigabit Ethernet Capabilities and Status Register 4 Address Offset: MBARA + 2Ch Default Value: 00000000h 392 R/W/SN 32 bit Description Address Offset: MBARA + 20h Default Value: 1000XXXXh 12.2.4 Attribute: Size: Attribute: Size: R/W 32 bit Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Gigabit LAN Configuration Registers Bit 31 WOL Indication Valid (WIV) -- R/W. Set to 1 by BIOS to indicate that the WOL indication setting in bit 30 of this register is valid. 30 WOL Enable Setting by BIOS (WESB) -- R/W. 1 = WOL Enabled in BIOS. 0 = WOL Disabled in BIOS. 29:0 12.2.5 Description Reserved GBECSR5--Gigabit Ethernet Capabilities and Status Register 5 Address Offset: MBARA + F00h Default Value: 00010008h Bit 31:6 5 4:0 12.2.6 R/W/V 32 bit Description Reserved SW Semaphore FLAG (SWFLAG) -- R/W/V. This bit is set by the device driver to gain access permission to shared CSR registers with the firmware and hardware. Reserved GBECSR6--Gigabit Ethernet Capabilities and Status Register 6 Address Offset: MBARA + F10h Default Value: 0004000Ch Bit 31:7 6 5:4 12.2.7 Attribute: Size: Attribute: Size: R/W/SN 32 bit Description Reserved Global GbE Disable (GGD)-- R/W/SN. Prevents the PHY from autonegotiating 1000Mb/s link in all power states. Reserved 3 GbE Disable at non D0a -- R/W/SN. Prevents the PHY from autonegotiating 1000Mb/s link in all power states except D0a. This bit must be set since GbE is not supported in Sx states. 2 LPLU in non D0a (LPLUND) -- R/W/SN. Enables the PHY to negotiate for the slowest possible link in all power states except D0a. 1 LPLU in D0a (LPLUD) -- R/W/SN. Enables the PHY to negotiate for the slowest possible link in all power states. This bit overrides bit 2. 0 Reserved GBECSR7--Gigabit Ethernet Capabilities and Status Register 7 Address Offset: MBARA + 5400h Default Value: XXXXXXXXh Bit 31:0 Attribute: Size: R/W 32 bit Description Receive Address Low (RAL)-- R/W. The lower 32 bits of the 48 bit Ethernet Address. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 393 Gigabit LAN Configuration Registers 12.2.8 GBECSR8--Gigabit Ethernet Capabilities and Status Register 8 Address Offset: MBARA + 5404h Default Value: XXXXXXXXh Bit 31 30:16 15:0 12.2.9 Attribute: Size: R/W 32 bit Description Address Valid-- R/W. Reserved Receive Address High (RAH)-- R/W. The lower 16 bits of the 48 bit Ethernet Address. GBECSR9--Gigabit Ethernet Capabilities and Status Register 9 Address Offset: MBARA + 5800h Default Value: 00000008h Bit 31:1 0 Attribute: Size: R/W/SN 32 bit Description Reserved Advanced Power Management Enable (APME) -- R/W/SN. 1 = APM Wakeup is enabled 0 = APM Wakeup is disabled 394 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13 LPC Interface Bridge Registers (D31:F0) The LPC bridge function of the PCH resides in PCI Device 31:Function 0. This function contains many other functional units, such as DMA and Interrupt controllers, Timers, Power Management, System Management, GPIO, RTC, and LPC Configuration Registers. Registers and functions associated with other functional units are described in their respective sections. 13.1 PCI Configuration Registers (LPC I/F--D31:F0) Note: Address locations that are not shown should be treated as Reserved. . Table 13-1. LPC Interface PCI Register Address Map (LPC I/F--D31:F0) (Sheet 1 of 2) Offset Mnemonic 00h-01h VID 02h-03h DID 04h-05h PCICMD PCI Command 06h-07h PCISTS PCI Status 08h RID 09h PI 0Ah SCC Register Name Default Type Vendor Identification 8086h RO Device Identification See register description RO 0007h R/W, RO 0210h R/WC, RO Revision Identification See register description RO Programming Interface 00h RO Sub Class Code 01h RO 0Bh BCC Base Class Code 06h RO 0Dh PLT Primary Latency Timer 00h RO 0Eh HEADTYP 2Ch-2Fh SS Sub System Identifiers Capability List Pointer Header Type 34h CAPP 40h-43h PMBASE 44h ACPI_CNTL ACPI Control 48h-4Bh GPIOBASE GPIO Base Address 4C GC 60h-63h PIRQ[n]_ROUT 64h SIRQ_CNTL 68h-6Bh PIRQ[n]_ROUT ACPI Base Address GPIO Control PIRQ[A-D] Routing Control Serial IRQ Control PIRQ[E-H] Routing Control 80h RO 00000000h R/WO E0h RO 00000001h R/W, RO 00h R/W 00000001h R/W, RO 00h R/W 80808080h R/W 10h R/W, RO 80808080h R/W 6Ch-6Dh LPC_IBDF IOxAPIC Bus:Device:Function 00F8h R/W 70h-7F LPC_HnBDF HPET Configuration 00F8h R/W 80h LPC_I/O_DEC I/O Decode Ranges 0000h R/W 82h-83h LPC_EN LPC I/F Enables 0000h R/W 84h-87h GEN1_DEC LPC I/F Generic Decode Range 1 00000000h R/W 88h-8Bh GEN2_DEC LPC I/F Generic Decode Range 2 00000000h R/W 8Ch-8Eh GEN3_DEC LPC I/F Generic Decode Range 3 00000000h R/W Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 395 LPC Interface Bridge Registers (D31:F0) Table 13-1. LPC Interface PCI Register Address Map (LPC I/F--D31:F0) (Sheet 2 of 2) Offset Mnemonic 90h-93h GEN4_DEC 94h-97h ULKMC 98h-9Bh LGMR LPC I/F Generic Decode Range 4 LPC Generic Memory Range 00000000h R/W 00000000h R/W D0h-D3h BIOS_SEL1 BIOS Select 1 00112233h R/W, RO D4h-D5h BIOS_SEL2 BIOS Select 2 4567h R/W D8h-D9h BIOS_DEC_EN1 BIOS Decode Enable 1 FFCFh R/W, RO 20h R/WLO, R/W, RO DCh BIOS_CNTL BIOS Control E0h-E1h FDCAP Feature Detection Capability ID E2h FDLEN Feature Detection Capability Length E3h FDVER Feature Detection Version E4h-EBh FDVCT Feature Vector F0h-F3h RCBA Root Complex Base Address 0009h RO 0Ch RO 10h RO See Description RO 00000000h R/W VID--Vendor Identification Register (LPC I/F--D31:F0) Bit 15:0 Attribute: Size: Power Well: RO 16-bit Core Description Vendor ID -- RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h DID--Device Identification Register (LPC I/F--D31:F0) Offset Address: 02h-03h Default Value: See bit description Lockable: No 396 Type USB Legacy Keyboard / Mouse Control Offset Address: 00h-01h Default Value: 8086h Lockable: No 13.1.2 Default Power Management (See Section 13.8.1) A0h-CFh 13.1.1 Register Name Attribute: Size: Power Well: RO 16-bit Core Bit Description 15:0 Device ID -- RO. This is a 16-bit value assigned to the PCH LPC bridge. Refer to the Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Specification Update for the value of the Device ID Register. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.1.3 PCICMD--PCI COMMAND Register (LPC I/F--D31:F0) Offset Address: 04h-05h Default Value: 0007h Lockable: No Bit 15:10 13.1.4 R/W, RO 16-bit Core Description Reserved 9 Fast Back to Back Enable (FBE) -- RO. Hardwired to 0. 8 SERR# Enable (SERR_EN) -- R/W. The LPC bridge generates SERR# if this bit is set. 7 Wait Cycle Control (WCC) -- RO. Hardwired to 0. 6 Parity Error Response Enable (PERE) -- R/W. 0 = No action is taken when detecting a parity error. 1 = Enables the PCH LPC bridge to respond to parity errors detected on backbone interface. 5 VGA Palette Snoop (VPS) -- RO. Hardwired to 0. 4 Memory Write and Invalidate Enable (MWIE) -- RO. Hardwired to 0. 3 Special Cycle Enable (SCE) -- RO. Hardwired to 0. 2 Bus Master Enable (BME) -- RO. Bus Masters cannot be disabled. 1 Memory Space Enable (MSE) -- RO. Memory space cannot be disabled on LPC. 0 I/O Space Enable (IOSE) -- RO. I/O space cannot be disabled on LPC. PCISTS--PCI Status Register (LPC I/F--D31:F0) Offset Address: 06h-07h Default Value: 0210h Lockable: No Note: Attribute: Size: Power Well: Attribute: Size: Power Well: RO, R/WC 16-bit Core For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit Description 15 Detected Parity Error (DPE) -- R/WC. Set when the LPC bridge detects a parity error on the internal backbone. Set even if the PCICMD.PERE bit (D31:F0:04, bit 6) is 0. 0 = Parity Error Not detected. 1 = Parity Error detected. 14 Signaled System Error (SSE)-- R/WC. Set when the LPC bridge signals a system error to the internal SERR# logic. 13 Master Abort Status (RMA) -- R/WC. 0 = Unsupported request status not received. 1 = The bridge received a completion with unsupported request status from the backbone. 12 Received Target Abort (RTA) -- R/WC. 0 = Completion abort not received. 1 = Completion with completion abort received from the backbone. 11 Signaled Target Abort (STA) -- R/WC. 0 = Target abort Not generated on the backbone. 1 = LPC bridge generated a completion packet with target abort status on the backbone. 10:9 8 DEVSEL# Timing Status (DEV_STS) -- RO. 01 = Medium Timing. Data Parity Error Detected (DPED) -- R/WC. 0 = All conditions listed below Not met. 1 = Set when all three of the following conditions are met: * LPC bridge receives a completion packet from the backbone from a previous request, * Parity error has been detected (D31:F0:06, bit 15) * PCICMD.PERE bit (D31:F0:04, bit 6) is set. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 397 LPC Interface Bridge Registers (D31:F0) Bit 7 Fast Back to Back Capable (FBC): Reserved - bit has no meaning on the internal backbone. 6 Reserved. 5 66 MHz Capable (66MHZ_CAP) -- Reserved - bit has no meaning on the internal backbone. 4 Capabilities List (CLIST) -- RO. Capability list exists on the LPC bridge. 3 2:0 13.1.5 Description Interrupt Status (IS) -- RO. The LPC bridge does not generate interrupts. Reserved. RID--Revision Identification Register (LPC I/F--D31:F0) Offset Address: 08h Default Value: See bit description Bit 7:0 13.1.6 Revision ID (RID) -- R/WO. Refer to the Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Specification Update for the value of the Revision ID Register PI--Programming Interface Register (LPC I/F--D31:F0) Bit 7:0 RO 8 bits Programming Interface -- RO. SCC--Sub Class Code Register (LPC I/F--D31:F0) Bit 7:0 Attribute: Size: RO 8 bits Description Sub Class Code -- RO. 8-bit value that indicates the category of bridge for the LPC bridge. 01h = PCI-to-ISA bridge. BCC--Base Class Code Register (LPC I/F--D31:F0) Offset Address: 0Bh Default Value: 06h Bit 7:0 398 Attribute: Size: Description Offset Address: 0Ah Default Value: 01h 13.1.8 R/WO 8 bits Description Offset Address: 09h Default Value: 00h 13.1.7 Attribute: Size: Attribute: Size: RO 8 bits Description Base Class Code -- RO. 8-bit value that indicates the type of device for the LPC bridge. 06h = Bridge device. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.1.9 PLT--Primary Latency Timer Register (LPC I/F--D31:F0) Offset Address: 0Dh Default Value: 00h Bit 13.1.10 RO 8 bits Description 7:3 Master Latency Count (MLC) -- Reserved. 2:0 Reserved. HEADTYP--Header Type Register (LPC I/F--D31:F0) Offset Address: 0Eh Default Value: 80h Bit 7 6:0 13.1.11 Attribute: Size: Attribute: Size: RO 8 bits Description Multi-Function Device -- RO. This bit is 1 to indicate a multi-function device. Header Type -- RO. This 7-bit field identifies the header layout of the configuration space. SS--Sub System Identifiers Register (LPC I/F--D31:F0) Offset Address: 2Ch-2Fh Default Value: 00000000h Attribute: Size: R/WO 32 bits This register is initialized to logic 0 by the assertion of PLTRST#. This register can be written only once after PLTRST# deassertion. 13.1.12 Bit Description 31:16 Subsystem ID (SSID) -- R/WO. This is written by BIOS. No hardware action taken on this value. 15:0 Subsystem Vendor ID (SSVID) -- R/WO. This is written by BIOS. No hardware action taken on this value. CAPP--Capability List Pointer Register (LPC I/F--D31:F0) Offset Address: 34h Default Value: E0h Bit 7:0 Attribute: Size: RO 8 bits Description Capability Pointer (CP) -- RO. Indicates the offset of the first Capability item. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 399 LPC Interface Bridge Registers (D31:F0) 13.1.13 PMBASE--ACPI Base Address Register (LPC I/F--D31:F0) Offset Address: 40h-43h Default Value: 00000001h Lockable: No Attribute: Size: Usage: Power Well: R/W, RO 32 bit ACPI, Legacy Core Sets base address for ACPI I/O registers, GPIO registers and TCO I/O registers. These registers can be mapped anywhere in the 64-K I/O space on 128-byte boundaries. Bit 31:16 15:7 6:1 0 13.1.14 Description Reserved Base Address -- R/W. This field provides 128 bytes of I/O space for ACPI, GPIO, and TCO logic. This is placed on a 128-byte boundary. Reserved Resource Type Indicator (RTE) -- RO. Hardwired to 1 to indicate I/O space. ACPI_CNTL--ACPI Control Register (LPC I/F -- D31:F0) Offset Address: 44h Default Value: 00h Lockable: No Attribute: Size: Usage: Power Well: R/W 8 bit ACPI, Legacy Core Bit Description 7 ACPI Enable (ACPI_EN) -- R/W. 0 = Disable. 1 = Decode of the I/O range pointed to by the ACPI base register is enabled, and the ACPI power management function is enabled. Note that the APM power management ranges (B2/B3h) are always enabled and are not affected by this bit. 6:3 Reserved SCI IRQ Select (SCI_IRQ_SEL) -- R/W. Specifies on which IRQ the SCI will internally appear. If not using the APIC, the SCI must be routed to IRQ9-11, and that interrupt is not sharable with the SERIRQ stream, but is shareable with other PCI interrupts. If using the APIC, the SCI can also be mapped to IRQ20-23, and can be shared with other interrupts. Bits 2:0 SCI Map 000b IRQ9 001b IRQ10 010b IRQ11 011b Reserved 100b IRQ20 (Only available if APIC enabled) 101b IRQ21 (Only available if APIC enabled) 110b IRQ22 (Only available if APIC enabled) When the interrupt is mapped to APIC interrupts 9, 10 or 11, the APIC should be programmed for active-high reception. When the interrupt is mapped to APIC interrupts 20 through 23, the APIC should be programmed for active-low reception. 400 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.1.15 GPIOBASE--GPIO Base Address Register (LPC I/F -- D31:F0) Offset Address: 48h-4Bh Default Value: 00000001h Attribute: Size: Bit 31:16 15:7 6:1 0 13.1.16 R/W, RO 32 bit Description Reserved. Always 0. Base Address (BA) -- R/W. Provides the 128 bytes of I/O space for GPIO. Reserved. Always 0. RO. Hardwired to 1 to indicate I/O space. GC--GPIO Control Register (LPC I/F -- D31:F0) Offset Address: 4Ch Default Value: 00h Bit 7:5 4 3:1 0 Attribute: Size: R/W 8 bit Description Reserved. GPIO Enable (EN) -- R/W. This bit enables/disables decode of the I/O range pointed to by the GPIO Base Address register (D31:F0:48h) and enables the GPIO function. 0 = Disable. 1 = Enable. Reserved. GPIO Lockdown Enable (GLE) -- R/W. This bit enables lockdown of the following GPIO registers: * Offset 00h: GPIO_USE_SEL * Offset 04h: GP_IO_SEL * Offset 0Ch: GP_LVL * Offset 30h: GPIO_USE_SEL2 * Offset 34h: GP_IO_SEL2 * Offset 38h: GP_LVL2 * Offset 40h: GPIO_USE_SEL3 * Offset 44h: GP_IO_SEL3 * Offset 48h: GP_LVL3 * Offset 60h: GP_RST_SEL 0 = Disable. 1 = Enable. When this bit is written from a 1-to-0, an SMI# is generated, if enabled. This ensures that only SMM code can change the above GPIO registers after they are locked down. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 401 LPC Interface Bridge Registers (D31:F0) 13.1.17 PIRQ[n]_ROUT--PIRQ[A,B,C,D] Routing Control Register (LPC I/F--D31:F0) Offset Address: PIRQA - 60h, PIRQB - 61h, Attribute:R/W PIRQC - 62h, PIRQD - 63h Default Value: 80h Size:8 bit Lockable: No Power Well:Core Bit 7 Description Interrupt Routing Enable (IRQEN) -- R/W. 0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in bits[3:0]. 1 = The PIRQ is not routed to the 8259. Note: 6:4 BIOS must program this bit to 0 during POST for any of the PIRQs that are being used. The value of this bit may subsequently be changed by the OS when setting up for I/O APIC interrupt delivery mode. Reserved IRQ Routing -- R/W. (ISA compatible.) 3:0 402 Value IRQ Value IRQ 0000b Reserved 1000b Reserved 0001b Reserved 1001b IRQ9 0010b Reserved 1010b IRQ10 0011b IRQ3 1011b IRQ11 0100b IRQ4 1100b IRQ12 0101b IRQ5 1101b Reserved 0110b IRQ6 1110b IRQ14 0111b IRQ7 1111b IRQ15 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.1.18 SIRQ_CNTL--Serial IRQ Control Register (LPC I/F--D31:F0) Offset Address: 64h Default Value: 10h Lockable: No Bit 7 6 Attribute: Size: Power Well: R/W, RO 8 bit Core Description Serial IRQ Enable (SIRQEN) -- R/W. 0 = The buffer is input only and internally SERIRQ will be a 1. 1 = Serial IRQs will be recognized. The SERIRQ pin will be configured as SERIRQ. Serial IRQ Mode Select (SIRQMD) -- R/W. 0 = The serial IRQ machine will be in quiet mode. 1 = The serial IRQ machine will be in continuous mode. Note: For systems using Quiet Mode, this bit should be set to 1 (Continuous Mode) for at least one frame after coming out of reset before switching back to Quiet Mode. Failure to do so will result in the PCH not recognizing SERIRQ interrupts. 5:2 Serial IRQ Frame Size (SIRQSZ) -- RO. Fixed field that indicates the size of the SERIRQ frame as 21 frames. 1:0 Start Frame Pulse Width (SFPW) -- R/W. This is the number of PCI clocks that the SERIRQ pin will be driven low by the serial IRQ machine to signal a start frame. In continuous mode, the PCH will drive the start frame for the number of clocks specified. In quiet mode, the PCH will drive the start frame for the number of clocks specified minus one, as the first clock was driven by the peripheral. 00 = 4 clocks 01 = 6 clocks 10 = 8 clocks 11 = Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 403 LPC Interface Bridge Registers (D31:F0) 13.1.19 PIRQ[n]_ROUT--PIRQ[E,F,G,H] Routing Control Register (LPC I/F--D31:F0) Offset Address: PIRQE - 68h, PIRQF - 69h, Attribute: PIRQG - 6Ah, PIRQH - 6Bh Default Value: 80h Size: Lockable: No Power Well: Bit R/W 8 bit Core Description Interrupt Routing Enable (IRQEN) -- R/W. 0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in bits[3:0]. 1 = The PIRQ is not routed to the 8259. 7 Note: 6:4 BIOS must program this bit to 0 during POST for any of the PIRQs that are being used. The value of this bit may subsequently be changed by the OS when setting up for I/O APIC interrupt delivery mode. Reserved IRQ Routing -- R/W. (ISA compatible.) 3:0 13.1.20 Value IRQ Value IRQ 0000b Reserved 1000b Reserved 0001b Reserved 1001b IRQ9 0010b Reserved 1010b IRQ10 0011b IRQ3 1011b IRQ11 0100b IRQ4 1100b IRQ12 0101b IRQ5 1101b Reserved 0110b IRQ6 1110b IRQ14 0111b IRQ7 1111b IRQ15 LPC_IBDF--IOxAPIC Bus:Device:Function (LPC I/F--D31:F0) Offset Address: 6Ch-6Dh Default Value: 00F8h Attribute: Size: Bit R/W 16 bit Description IOxAPIC Bus:Device:Function (IBDF)-- R/W. this field specifies the bus:device:function that PCH's IOxAPIC will be using for the following: * As the Requester ID when initiating Interrupt Messages to the processor. * As the Completer ID when responding to the reads targeting the IOxAPIC's Memory-Mapped I/O registers. The 16-bit field comprises the following: 15:0 Bits 15:8 Description Bus Number 7:3 Device Number 2:0 Function Number This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS can program this field to provide a unique bus:device:function number for the internal IOxAPIC. 404 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.1.21 LPC_HnBDF - HPET n Bus:Device:Function(LPC I/F-- D31:F0) Address Offset Default Value: H0BDF H1BDF H2BDF H3BDF H4BDF H5BDF H6BDF H7BDF 00F8h 70h-71h 72h-73h 74h-75h 76h-77h 78h-79h 7Ah-7Bh 7Ch-7Dh 7Eh-7Fh Attribute: Size: Bit R/W 16 bit Description HPET n Bus:Device:Function (HnBDF)-- R/W. This field specifies the bus:device:function that the PCH's HPET n will be using in the following: * As the Requester ID when initiating Interrupt Messages to the processor * As the Completer ID when responding to the reads targeting the corresponding HPET's Memory-Mapped I/O registers The 16-bit field comprises the following: Bits 15:0 15:8 Description Bus Number 7:3 Device Number 2:0 Function Number This field is default to Bus 0: Device 31: Function 0 after reset. BIOS shall program this field accordingly if unique bus:device:function number is required for the corresponding HPET. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 405 LPC Interface Bridge Registers (D31:F0) 13.1.22 LPC_I/O_DEC--I/O Decode Ranges Register (LPC I/F--D31:F0) Offset Address: 80h Default Value: 0000h Bit 15:13 12 11:10 9:8 7 6:4 3 2:0 406 Attribute: Size: R/W 16 bit Description Reserved FDD Decode Range -- R/W. Determines which range to decode for the FDD Port 0 = 3F0h - 3F5h, 3F7h (Primary) 1 = 370h - 375h, 377h (Secondary) Reserved LPT Decode Range -- R/W. This field determines which range to decode for the LPT Port. 00 = 378h - 37Fh and 778h - 77Fh 01 = 278h - 27Fh (port 279h is read only) and 678h - 67Fh 10 = 3BCh -3BEh and 7BCh - 7BEh 11 = Reserved Reserved COMB Decode Range -- R/W. This field determines which range to decode for the COMB Port. 000 = 3F8h - 3FFh (COM1) 001 = 2F8h - 2FFh (COM2) 010 = 220h - 227h 011 = 228h - 22Fh 100 = 238h - 23Fh 101 = 2E8h - 2EFh (COM4) 110 = 338h - 33Fh 111 = 3E8h - 3EFh (COM3) Reserved COMA Decode Range -- R/W. This field determines which range to decode for the COMA Port. 000 = 3F8h - 3FFh (COM1) 001 = 2F8h - 2FFh (COM2) 010 = 220h - 227h 011 = 228h - 22Fh 100 = 238h - 23Fh 101 = 2E8h - 2EFh (COM4) 110 = 338h - 33Fh 111 = 3E8h - 3EFh (COM3) Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.1.23 LPC_EN--LPC I/F Enables Register (LPC I/F--D31:F0) Offset Address: 82h - 83h Default Value: 0000h Bit 15:14 Attribute: Size: Power Well: R/W 16 bit Core Description Reserved 13 CNF2_LPC_EN -- R/W. Microcontroller Enable # 2. 0 = Disable. 1 = Enables the decoding of the I/O locations 4Eh and 4Fh to the LPC interface. This range is used for a microcontroller. 12 CNF1_LPC_EN -- R/W. Super I/O Enable. 0 = Disable. 1 = Enables the decoding of the I/O locations 2Eh and 2Fh to the LPC interface. This range is used for Super I/O devices. 11 MC_LPC_EN -- R/W. Microcontroller Enable # 1. 0 = Disable. 1 = Enables the decoding of the I/O locations 62h and 66h to the LPC interface. This range is used for a microcontroller. 10 KBC_LPC_EN -- R/W. Keyboard Enable. 0 = Disable. 1 = Enables the decoding of the I/O locations 60h and 64h to the LPC interface. This range is used for a microcontroller. 9 GAMEH_LPC_EN -- R/W. High Gameport Enable 0 = Disable. 1 = Enables the decoding of the I/O locations 208h to 20Fh to the LPC interface. This range is used for a gameport. 8 GAMEL_LPC_EN -- R/W. Low Gameport Enable 0 = Disable. 1 = Enables the decoding of the I/O locations 200h to 207h to the LPC interface. This range is used for a gameport. 7:4 Reserved 3 FDD_LPC_EN -- R/W. Floppy Drive Enable 0 = Disable. 1 = Enables the decoding of the FDD range to the LPC interface. This range is selected in the LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 12). 2 LPT_LPC_EN -- R/W. Parallel Port Enable 0 = Disable. 1 = Enables the decoding of the LPTrange to the LPC interface. This range is selected in the LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 9:8). 1 COMB_LPC_EN -- R/W. Com Port B Enable 0 = Disable. 1 = Enables the decoding of the COMB range to the LPC interface. This range is selected in the LPC_COM Decode Range Register (D31:F0:80h, bits 6:4). 0 COMA_LPC_EN -- R/W. Com Port A Enable 0 = Disable. 1 = Enables the decoding of the COMA range to the LPC interface. This range is selected in the LPC_COM Decode Range Register (D31:F0:80h, bits 3:2). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 407 LPC Interface Bridge Registers (D31:F0) 13.1.24 GEN1_DEC--LPC I/F Generic Decode Range 1 Register (LPC I/F--D31:F0) Offset Address: 84h - 87h Default Value: 00000000h Bit Description Reserved 23:18 Generic I/O Decode Range Address[7:2] Mask -- R/W. A 1 in any bit position indicates that any value in the corresponding address bit in a received cycle will be treated as a match. The corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to 256 bytes in size. 15:2 Reserved Generic I/O Decode Range 1 Base Address (GEN1_BASE) -- R/W. Note: The PCH Does not provide decode down to the word or byte level 1 Reserved 0 Generic Decode Range 1 Enable (GEN1_EN) -- R/W. 0 = Disable. 1 = Enable the GEN1 I/O range to be forwarded to the LPC I/F GEN2_DEC--LPC I/F Generic Decode Range 2 Register (LPC I/F--D31:F0) Offset Address: 88h - 8Bh Default Value: 00000000h Bit Attribute: Size: Power Well: R/W 32 bit Core Description 31:24 Reserved 23:18 Generic I/O Decode Range Address[7:2] Mask -- R/W. A 1 in any bit position indicates that any value in the corresponding address bit in a received cycle will be treated as a match. The corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to 256 bytes in size. 17:16 15:2 408 R/W 32 bit Core 31:24 17:16 13.1.25 Attribute: Size: Power Well: Reserved Generic I/O Decode Range 2 Base Address (GEN1_BASE) -- R/W. Note: The PCH does not provide decode down to the word or byte level 1 Reserved 0 Generic Decode Range 2 Enable (GEN2_EN) -- R/W. 0 = Disable. 1 = Enable the GEN2 I/O range to be forwarded to the LPC I/F Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.1.26 GEN3_DEC--LPC I/F Generic Decode Range 3 Register (LPC I/F--D31:F0) Offset Address: 8Ch - 8Eh Default Value: 00000000h Bit R/W 32 bit Core Description 31:24 Reserved 23:18 Generic I/O Decode Range Address[7:2] Mask -- R/W. A 1 in any bit position indicates that any value in the corresponding address bit in a received cycle will be treated as a match. The corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to 256 bytes in size. 17:16 15:2 13.1.27 Attribute: Size: Power Well: Reserved Generic I/O Decode Range 3 Base Address (GEN3_BASE) -- R/W. Note: The PCH Does not provide decode down to the word or byte level 1 Reserved 0 Generic Decode Range 3 Enable (GEN3_EN) -- R/W. 0 = Disable. 1 = Enable the GEN3 I/O range to be forwarded to the LPC I/F GEN4_DEC--LPC I/F Generic Decode Range 4 Register (LPC I/F--D31:F0) Offset Address: 90h - 93h Default Value: 00000000h Bit Attribute: Size: Power Well: R/W 32 bit Core Description 31:24 Reserved 23:18 Generic I/O Decode Range Address[7:2] Mask -- R/W. A 1 in any bit position indicates that any value in the corresponding address bit in a received cycle will be treated as a match. The corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to 256 bytes in size. 17:16 15:2 Reserved Generic I/O Decode Range 4 Base Address (GEN4_BASE) -- R/W. Note: The PCH Does not provide decode down to the word or byte level 1 Reserved 0 Generic Decode Range 4 Enable (GEN4_EN) -- R/W. 0 = Disable. 1 = Enable the GEN4 I/O range to be forwarded to the LPC I/F Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 409 LPC Interface Bridge Registers (D31:F0) 13.1.28 ULKMC--USB Legacy Keyboard / Mouse Control (LPC I/F--D31:F0) Offset Address: 94h - 97h Default Value: 00002000h Bit 31:16 15 14:12 410 Attribute: Size: Power Well: RO, R/WC, R/W 32 bit Core Description Reserved Intel SMI Caused by End of Pass-Through (SMIBYENDPS) -- R/WC. This bit indicates if the event occurred. Note that even if the corresponding enable bit is not set in bit 7, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 = Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = Event Occurred Reserved 11 Intel SMI Caused by Port 64 Write (TRAPBY64W) -- R/WC. This bit indicates if the event occurred. Note that even if the corresponding enable bit is not set in bit 3, this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h writes to complete without setting this bit. 0 = Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = Event Occurred. 10 Intel SMI Caused by Port 64 Read (TRAPBY64R) -- R/WC. This bit indicates if the event occurred. Note that even if the corresponding enable bit is not set in bit 2, this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 = Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = Event Occurred. 9 Intel SMI Caused by Port 60 Write (TRAPBY60W) -- R/WC. This bit indicates if the event occurred. Note that even if the corresponding enable bit is not set in bit 1, this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h writes to complete without setting this bit. 0 = Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = Event Occurred. 8 Intel SMI Caused by Port 60 Read (TRAPBY60R) -- R/WC. This bit indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 0, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 = Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = Event Occurred. 7 Intel SMI at End of Pass-Through Enable (SMIATENDPS) -- R/W. This bit enables Intel SMI at the end of a pass-through. This can occur if an Intel SMI is generated in the middle of a passthrough, and needs to be serviced later. 0 = Disable 1 = Enable 6 Pass Through State (PSTATE) -- RO. 0 = If software needs to reset this bit, it should set bit 5 in all of the host controllers to 0. 1 = Indicates that the state machine is in the middle of an A20GATE pass-through sequence. 5 A20Gate Pass-Through Enable (A20PASSEN) -- R/W. 0 = Disable. 1 = Enable. Allows A20GATE sequence Pass-Through function. A specific cycle sequence involving writes to port 60h and 64h does not result in the setting of the Intel SMI status bits. Note: A20M# functionality is not supported. 4 Intel SMI on USB IRQ Enable (USBSMIEN) -- R/W. 0 = Disable 1 = Enable. USB interrupt will cause an Intel SMI event. 3 Intel SMI on Port 64 Writes Enable (64WEN) -- R/W. 0 = Disable 1 = Enable. A 1 in bit 11 will cause an Intel SMI event. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) Bit 13.1.29 Description 2 Intel SMI on Port 64 Reads Enable (64REN) -- R/W. 0 = Disable 1 = Enable. A 1 in bit 10 will cause an Intel SMI event. 1 Intel SMI on Port 60 Writes Enable (60WEN) -- R/W. 0 = Disable 1 = Enable. A 1 in bit 9 will cause an Intel SMI event. 0 Intel SMI on Port 60 Reads Enable (60REN) -- R/W. 0 = Disable 1 = Enable. A 1 in bit 8 will cause an Intel SMI event. LGMR -- LPC I/F Generic Memory Range (LPC I/F--D31:F0) Offset Address: 98h - 9Bh Default Value: 00000000h Bit 31:16 15:1 0 13.1.30 Attribute: Size: Power Well: R/W 32 bit Core Description Memory Address[31:16] -- R/W. This field specifies a 64 KB memory block anywhere in the 4 GB memory space that will be decoded to LPC as standard LPC memory cycle if enabled. Reserved LPC Memory Range Decode Enable -- R/W. When this bit is set to `1', then the range specified in bits 31:16 of this register is enabled for decoding to LPC BIOS_SEL1--BIOS Select 1 Register (LPC I/F--D31:F0) Offset Address: D0h-D3h Default Value: 00112233h Bit Attribute: Size: R/W, RO 32 bits Description 31:28 BIOS_F8_IDSEL -- RO. IDSEL for two 512-KB BIOS memory ranges and one 128-KB memory range. This field is fixed at 0000. The IDSEL programmed in this field addresses the following memory ranges: FFF8 0000h - FFFF FFFFh FFB8 0000h - FFBF FFFFh 000E 0000h - 000F FFFFh 27:24 BIOS_F0_IDSEL -- R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFF0 0000h - FFF7 FFFFh FFB0 0000h - FFB7 FFFFh 23:20 BIOS_E8_IDSEL -- R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFE8 0000h - FFEF FFFFh FFA8 0000h - FFAF FFFFh 19:16 BIOS_E0_IDSEL -- R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFE0 0000h - FFE7 FFFFh FFA0 0000h - FFA7 FFFFh 15:12 BIOS_D8_IDSEL -- R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFD8 0000h - FFDF FFFFh FF98 0000h - FF9F FFFFh Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 411 LPC Interface Bridge Registers (D31:F0) 13.1.31 Bit Description 11:8 BIOS_D0_IDSEL -- R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFD0 0000h - FFD7 FFFFh FF90 0000h - FF97 FFFFh 7:4 BIOS_C8_IDSEL -- R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFC8 0000h - FFCF FFFFh FF88 0000h - FF8F FFFFh 3:0 BIOS_C0_IDSEL -- R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFC0 0000h - FFC7 FFFFh FF80 0000h - FF87 FFFFh BIOS_SEL2--BIOS Select 2 Register (LPC I/F--D31:F0) Offset Address: D4h-D5h Default Value: 4567h Bit 13.1.32 R/W 16 bits Description 15:12 BIOS_70_IDSEL -- R/W. IDSEL for two, 1-M BIOS memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FF70 0000h - FF7F FFFFh FF30 0000h - FF3F FFFFh 11:8 BIOS_60_IDSEL -- R/W. IDSEL for two, 1-M BIOS memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FF60 0000h - FF6F FFFFh FF20 0000h - FF2F FFFFh 7:4 BIOS_50_IDSEL -- R/W. IDSEL for two, 1-M BIOS memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FF50 0000h - FF5F FFFFh FF10 0000h - FF1F FFFFh 3:0 BIOS_40_IDSEL -- R/W. IDSEL for two, 1-M BIOS memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FF40 0000h - FF4F FFFFh FF00 0000h - FF0F FFFFh BIOS_DEC_EN1--BIOS Decode Enable Register (LPC I/F--D31:F0) Offset Address: D8h-D9h Default Value: FFCFh 412 Attribute: Size: Attribute: Size: R/W, RO 16 bits Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) Bit Description 15 BIOS_F8_EN -- RO. This bit enables decoding two 512-KB BIOS memory ranges, and one 128-KB memory range. 0 = Disable 1 = Enable the following ranges for the BIOS FFF80000h - FFFFFFFFh FFB80000h - FFBFFFFFh 14 BIOS_F0_EN -- R/W. This bit enables decoding two 512-KB BIOS memory ranges. 0 = Disable. 1 = Enable the following ranges for the BIOS: FFF00000h - FFF7FFFFh FFB00000h - FFB7FFFFh 13 BIOS_E8_EN -- R/W. This bit enables decoding two 512-KB BIOS memory ranges. 0 = Disable. 1 = Enable the following ranges for the BIOS: FFE80000h - FFEFFFFh FFA80000h - FFAFFFFFh 12 BIOS_E0_EN -- R/W. This bit enables decoding two 512-KB BIOS memory ranges. 0 = Disable. 1 = Enable the following ranges for the BIOS: FFE00000h - FFE7FFFFh FFA00000h - FFA7FFFFh 11 BIOS_D8_EN -- R/W. This bit enables decoding two 512-KB BIOS memory ranges. 0 = Disable. 1 = Enable the following ranges for the BIOS FFD80000h - FFDFFFFFh FF980000h - FF9FFFFFh 10 BIOS_D0_EN -- R/W. This bit enables decoding two 512-KB BIOS memory ranges. 0 = Disable. 1 = Enable the following ranges for the BIOS FFD00000h - FFD7FFFFh FF900000h - FF97FFFFh 9 BIOS_C8_EN -- R/W. This bit enables decoding two 512-KB BIOS memory ranges. 0 = Disable. 1 = Enable the following ranges for the BIOS FFC80000h - FFCFFFFFh FF880000h - FF8FFFFFh 8 BIOS_C0_EN -- R/W. This bit enables decoding two 512-KB BIOS memory ranges. 0 = Disable. 1 = Enable the following ranges for the BIOS FFC00000h - FFC7FFFFh FF800000h - FF87FFFFh 7 BIOS_Legacy_F_EN -- R/W. This enables the decoding of the legacy 64 KB range at F0000h - FFFFFh. 0 = Disable. 1 = Enable the following legacy ranges for the BIOS F0000h - FFFFFh Note: The decode for the BIOS legacy F segment is enabled only by this bit and is not affected by the GEN_PMCON_1.iA64_EN bit. 6 BIOS_Legacy_E_EN -- R/W. This enables the decoding of the legacy 64 KB range at E0000h - EFFFFh. 0 = Disable. 1 = Enable the following legacy ranges for the BIOS E0000h - EFFFFh Note: The decode for the BIOS legacy E segment is enabled only by this bit and is not affected by the GEN_PMCON_1.iA64_EN bit. 5:4 3 Reserved BIOS_70_EN -- R/W. Enables decoding two 1-M BIOS memory ranges. 0 = Disable. 1 = Enable the following ranges for the BIOS FF700000h - FF7FFFFFh FF300000h - FF3FFFFFh Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 413 LPC Interface Bridge Registers (D31:F0) Bit 2 BIOS_60_EN -- R/W. Enables decoding two 1-M BIOS memory ranges. 0 = Disable. 1 = Enable the following ranges for the BIOS FF600000h - FF6FFFFFh FF200000h - FF2FFFFFh 1 BIOS_50_EN -- R/W. Enables decoding two 1-M BIOS memory ranges. 0 = Disable. 1 = Enable the following ranges for the BIOS FF500000h - FF5FFFFFh FF100000h - FF1FFFFFh 0 BIOS_40_EN -- R/W. Enables decoding two 1-M BIOS memory ranges. 0 = Disable. 1 = Enable the following ranges for the BIOS FF400000h - FF4FFFFFh FF000000h - FF0FFFFFh Note: 13.1.33 Description This register effects the BIOS decode regardless of whether the BIOS is resident on LPC or SPI. The concept of Feature Space does not apply to SPI-based flash. The PCH simply decodes these ranges as memory accesses when enabled for the SPI flash interface. BIOS_CNTL--BIOS Control Register (LPC I/F--D31:F0) Offset Address: DCh Default Value: 20h Lockable: No Attribute: Size: Power Well: Bit 7:6 R/WLO, R/W, RO 8 bit Core Description Reserved 5 SMM BIOS Write Protect Disable (SMM_BWP)-- R/WLO. This bit set defines when the BIOS region can be written by the host. 0 = BIOS region SMM protection is disabled. The BIOS Region is writable regardless if Processors are in SMM or not. (Set this field to 0 for legacy behavior) 1 = BIOS region SMM protection is enabled. The BIOS Region is not writable unless all Processors are in SMM. 4 Top Swap Status (TSS) -- RO. This bit provides a read-only path to view the state of the Top Swap bit that is at offset 3414h, bit 0. SPI Read Configuration (SRC) -- R/W. This 2-bit field controls two policies related to BIOS reads on the SPI interface: Bit 3- Prefetch Enable Bit 2- Cache Disable Settings are summarized below: Bits 3:2 3:2 1 414 Description 00b No prefetching, but caching enabled. 64B demand reads load the read buffer cache with "valid" data, allowing repeated code fetches to the same line to complete quickly 01b No prefetching and no caching. One-to-one correspondence of host BIOS reads to SPI cycles. This value can be used to invalidate the cache. 10b Prefetching and Caching enabled. This mode is used for long sequences of short reads to consecutive addresses (that is, shadowing). 11b Reserved. This is an invalid configuration, caching must be enabled when prefetching is enabled. BIOS Lock Enable (BLE) -- R/WLO. 0 = Setting the BIOSWE will not cause SMIs. 1 = Enables setting the BIOSWE bit to cause SMIs. Once set, this bit can only be cleared by a PLTRST# Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.1.34 Bit Description 0 BIOS Write Enable (BIOSWE) -- R/W. 0 = Only read cycles result in BIOS I/F cycles. 1 = Access to the BIOS space is enabled for both read and write cycles. When this bit is written from a 0 to a 1 and BIOS Lock Enable (BLE) is also set, an SMI# is generated. This ensures that only Intel SMI code can update BIOS. FDCAP--Feature Detection Capability ID (LPC I/F--D31:F0) Offset Address: E0h-E1h Default Value: 0009h Bit 13.1.35 RO 16 bit Core Description 15:8 Next Item Pointer (NEXT) -- RO. Configuration offset of the next Capability Item. 00h indicates the last item in the Capability List. 7:0 Capability ID -- RO. Indicates a Vendor Specific Capability FDLEN--Feature Detection Capability Length (LPC I/F--D31:F0) Offset Address: E2h Default Value: 0Ch Bit 7:0 13.1.36 Attribute: Size: Power Well: Attribute: Size: Power Well: RO 8 bit Core Description Capability Length -- RO. Indicates the length of this Vendor Specific capability, as required by PCI Specification. FDVER--Feature Detection Version (LPC I/F--D31:F0) Offset Address: E3h Default Value: 10h Bit Attribute: Size: Power Well: RO 8 bit Core Description 7:4 Vendor-Specific Capability ID -- RO. A value of 1h in this 4-bit field identifies this Capability as Feature Detection Type. This field allows software to differentiate the Feature Detection Capability from other Vendor-Specific capabilities 3:0 Capability Version -- RO. This field indicates the version of the Feature Detection capability Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 415 LPC Interface Bridge Registers (D31:F0) 13.1.37 FVECIDX--Feature Vector Index (LPC I/F--D31:F0) Offset Address: E4h-E7h Default Value: 00000000h Attribute: Size: Power Well: Bit 31:6 13.1.38 Description Reserved 5:2 Index (IDX) -- R/W. 4-bit index pointer into the 64-byte Feature Vector space. Data is read from the FVECD register. This points to a DWord register. 1:0 Reserved FVECD--Feature Vector Data (LPC I/F--D31:F0) Offset Address: E8h-EBh Default Value: See Description Attribute: Size: Power Well: Bit 31:0 Data (DATA) -- RO. 32-bit data value that is read from the Feature Vector offset pointed to by FVECIDX. Feature Vector Space 13.1.39.1 FVEC0--Feature Vector Register 0 FVECIDX.IDX: Default Value: 0000b See Description Bit Reserved 11:10 USB Port Count Capability -- RO 00 = 14 ports 01 = 12 ports 10 = 10 ports 11 = Reserved RAID Capability -- RO Disabled Capable 6 SATA Ports 2 and 3 -- RO Capable Disabled 3 RO 32 bit Core Reserved 7 5:4 Attribute: Size: Power Well: Description 31:12 9:8 RO 32 bit Core Description 13.1.39 416 R/W 32 bit Core Reserved SATA Port 1 6 Gb/s Capability-- RO Capable Disabled Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) Bit 13.1.39.2 Description 2 SATA Port 0 6 Gb/s Capability-- RO Capable Disabled 1 PCI Interface Capability -- RO Capable Disabled 0 Reserved FVEC1--Feature Vector Register 1 FVECIDX.IDX: Default Value: 0001b See Description Bit 31:23 22 21:0 13.1.39.3 RO 32 bit Core Description Reserved USB Redirect (USBr) Capability-- RO 0 = Capable 1 = Disabled Reserved FVEC2--Feature Vector Register 2 FVECIDX.IDX: Default Value: 0010b See Description Bit 31:23 Attribute: Size: Power Well: RO 32 bit Core Description Reserved 22 Intel(R) Anti-Theft Technology Capability -- RO 0 = Disabled 1 = Capable 21 PCI Express* Ports 7 and 8-- RO 0 = Capable 1 = Disabled 20:0 13.1.39.4 Attribute: Size: Power Well: Reserved FVEC3--Feature Vector Register 3 FVECIDX.IDX: Default Value: 0011b See Description Bit 31:14 Attribute: Size: Power Well: Description Reserved 13 Data Center Manageability Interface (DCMI) Capability -- RO 0 = Capable 1 = Disabled 12 Node Manager Capability -- RO 0 = Capable 1 = Disabled 11:0 RO 32 bit Core Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 417 LPC Interface Bridge Registers (D31:F0) 13.1.40 RCBA--Root Complex Base Address Register (LPC I/F--D31:F0) Offset Address: F0-F3h Default Value: 00000000h Bit 31:14 13:1 R/W 32 bit Description Base Address (BA) -- R/W. Base Address for the root complex register block decode range. This address is aligned on a 16-KB boundary. Reserved Enable (EN) -- R/W. When set, this bit enables the range specified in BA to be claimed as the Root Complex Register Block. 0 13.2 Attribute: Size: DMA I/O Registers Table 13-2. DMA Registers (Sheet 1 of 2) 418 Port Alias Register Name Default Type 00h 10h Channel 0 DMA Base & Current Address Undefined R/W 01h 11h Channel 0 DMA Base & Current Count Undefined R/W 02h 12h Channel 1 DMA Base & Current Address Undefined R/W 03h 13h Channel 1 DMA Base & Current Count Undefined R/W 04h 14h Channel 2 DMA Base & Current Address Undefined R/W 05h 15h Channel 2 DMA Base & Current Count Undefined R/W 06h 16h Channel 3 DMA Base & Current Address Undefined R/W 07h 17h Channel 3 DMA Base & Current Count Undefined R/W 08h 18h Channel 0-3 DMA Command Undefined WO Channel 0-3 DMA Status Undefined RO 0Ah 1Ah Channel 0-3 DMA Write Single Mask 000001XXb WO 0Bh 1Bh Channel 0-3 DMA Channel Mode 000000XXb WO 0Ch 1Ch Channel 0-3 DMA Clear Byte Pointer Undefined WO 0Dh 1Dh Channel 0-3 DMA Master Clear Undefined WO 0Eh 1Eh Channel 0-3 DMA Clear Mask Undefined WO 0Fh 1Fh Channel 0-3 DMA Write All Mask 0Fh R/W 80h 90h Reserved Page Undefined R/W 81h 91h Channel 2 DMA Memory Low Page Undefined R/W 82h -- Channel 3 DMA Memory Low Page Undefined R/W 83h 93h Channel 1 DMA Memory Low Page Undefined R/W 84h-86h 94h-96h Reserved Pages Undefined R/W 87h 97h Channel 0 DMA Memory Low Page Undefined R/W 88h 98h Reserved Page Undefined R/W 89h 99h Channel 6 DMA Memory Low Page Undefined R/W 8Ah 9Ah Channel 7 DMA Memory Low Page Undefined R/W 8Bh 9Bh Channel 5 DMA Memory Low Page Undefined R/W 8Ch-8Eh 9Ch-9Eh Reserved Page Undefined R/W 8Fh 9Fh Refresh Low Page Undefined R/W Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) Table 13-2. DMA Registers (Sheet 2 of 2) 13.2.1 Port Alias Register Name Default Type C0h C1h Channel 4 DMA Base & Current Address Undefined R/W C2h C3h Channel 4 DMA Base & Current Count Undefined R/W C4h C5h Channel 5 DMA Base & Current Address Undefined R/W C6h C7h Channel 5 DMA Base & Current Count Undefined R/W C8h C9h Channel 6 DMA Base & Current Address Undefined R/W CAh CBh Channel 6 DMA Base & Current Count Undefined R/W CCh CDh Channel 7 DMA Base & Current Address Undefined R/W CEh CFh Channel 7 DMA Base & Current Count Undefined R/W D0h D1h Channel 4-7 DMA Command Undefined WO Channel 4-7 DMA Status Undefined RO D4h D5h Channel 4-7 DMA Write Single Mask 000001XXb WO D6h D7h Channel 4-7 DMA Channel Mode 000000XXb WO D8h D9h Channel 4-7 DMA Clear Byte Pointer Undefined WO DAh DBh Channel 4-7 DMA Master Clear Undefined WO DCh DDh Channel 4-7 DMA Clear Mask Undefined WO DEh DFh Channel 4-7 DMA Write All Mask 0Fh R/W DMABASE_CA--DMA Base and Current Address Registers I/O Address: Default Value: Lockable: Ch. #0 = 00h; Ch. #1 = 02hAttribute: Ch. #2 = 04h; Ch. #3 = 06hSize: Ch. #5 = C4h Ch. #6 = C8h Ch. #7 = CCh; Undefined No Power Well: R/W 16 bit (per channel), but accessed in two 8-bit quantities Core Bit Description 15:0 Base and Current Address -- R/W. This register determines the address for the transfers to be performed. The address specified points to two separate registers. On writes, the value is stored in the Base Address register and copied to the Current Address register. On reads, the value is returned from the Current Address register. The address increments/decrements in the Current Address register after each transfer, depending on the mode of the transfer. If the channel is in auto-initialize mode, the Current Address register will be reloaded from the Base Address register after a terminal count is generated. For transfers to/from a 16-bit slave (channels 5-7), the address is shifted left one bit location. Bit 15 will be shifted into Bit 16. The register is accessed in 8 bit quantities. The byte is pointed to by the current byte pointer flip/ flop. Before accessing an address register, the byte pointer flip/flop should be cleared to ensure that the low byte is accessed first Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 419 LPC Interface Bridge Registers (D31:F0) 13.2.2 DMABASE_CC--DMA Base and Current Count Registers I/O Address: Default Value: Lockable: 13.2.3 Core Description 15:0 Base and Current Count -- R/W. This register determines the number of transfers to be performed. The address specified points to two separate registers. On writes, the value is stored in the Base Count register and copied to the Current Count register. On reads, the value is returned from the Current Count register. The actual number of transfers is one more than the number programmed in the Base Count Register (that is, programming a count of 4h results in 5 transfers). The count is decrements in the Current Count register after each transfer. When the value in the register rolls from 0 to FFFFh, a terminal count is generated. If the channel is in auto-initialize mode, the Current Count register will be reloaded from the Base Count register after a terminal count is generated. For transfers to/from an 8-bit slave (channels 0-3), the count register indicates the number of bytes to be transferred. For transfers to/from a 16-bit slave (channels 5-7), the count register indicates the number of words to be transferred. The register is accessed in 8 bit quantities. The byte is pointed to by the current byte pointer flip/ flop. Before accessing a count register, the byte pointer flip/flop should be cleared to ensure that the low byte is accessed first. DMAMEM_LP--DMA Memory Low Page Registers Default Value: Lockable: Ch. #0 = 87h; Ch. #1 = 83h Ch. #2 = 81h; Ch. #3 = 82h Ch. #5 = 8Bh; Ch. #6 = 89h Ch. #7 = 8Ah; Attribute: Undefined Size: No Power Well: R/W 8-bit Core Bit Description 7:0 DMA Low Page (ISA Address bits [23:16]) -- R/W. This register works in conjunction with the DMA controller's Current Address Register to define the complete 24-bit address for the DMA channel. This register remains static throughout the DMA transfer. Bit 16 of this register is ignored when in 16 bit I/O count by words mode as it is replaced by the bit 15 shifted out from the current address register. DMACMD--DMA Command Register I/O Address: Default Value: Lockable: Ch. #0-3 = 08h; Ch. #4-7 = D0h Undefined No Bit 7:5 4 420 R/W 16-bit (per channel), but accessed in two 8-bit quantities Bit I/O Address: 13.2.4 Ch. #0 = 01h; Ch. #1 = 03hAttribute: Ch. #2 = 05h; Ch. #3 = 07hSize: Ch. #5 = C6h; Ch. #6 = CAh Ch. #7 = CEh; Undefined No Power Well: Attribute: Size: Power Well: WO 8-bit Core Description Reserved. Must be 0. DMA Group Arbitration Priority -- WO. Each channel group is individually assigned either fixed or rotating arbitration priority. At part reset, each group is initialized in fixed priority. 0 = Fixed priority to the channel group 1 = Rotating priority to the group. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) Bit 3 Reserved. Must be 0. 2 DMA Channel Group Enable -- WO. Both channel groups are enabled following part reset. 0 = Enable the DMA channel group. 1 = Disable. Disabling channel group 4-7 also disables channel group 0-3, which is cascaded through channel 4. 1:0 13.2.5 Description Reserved. Must be 0. DMASTA--DMA Status Register I/O Address: Default Value: Lockable: 13.2.6 Ch. #0-3 = 08h; Ch. #4-7 = D0h Undefined No Attribute: Size: Power Well: RO 8-bit Core Bit Description 7:4 Channel Request Status -- RO. When a valid DMA request is pending for a channel, the corresponding bit is set to 1. When a DMA request is not pending for a particular channel, the corresponding bit is set to 0. The source of the DREQ may be hardware or a software request. Note that channel 4 is the cascade channel, so the request status of channel 4 is a logical OR of the request status for channels 0 through 3. 4 = Channel 0 5 = Channel 1 (5) 6 = Channel 2 (6) 7 = Channel 3 (7) 3:0 Channel Terminal Count Status -- RO. When a channel reaches terminal count (TC), its status bit is set to 1. If TC has not been reached, the status bit is set to 0. Channel 4 is programmed for cascade, so the TC bit response for channel 4 is irrelevant: 0 = Channel 0 1 = Channel 1 (5) 2 = Channel 2 (6) 3 = Channel 3 (7) DMA_WRSMSK--DMA Write Single Mask Register I/O Address: Default Value: Lockable: Ch. #0-3 = 0Ah; Ch. #4-7 = D4h 0000 01xx No Bit 7:3 2 1:0 Attribute: Size: Power Well: WO 8-bit Core Description Reserved. Must be 0. Channel Mask Select -- WO. 0 = Enable DREQ for the selected channel. The channel is selected through bits [1:0]. Therefore, only one channel can be masked / unmasked at a time. 1 = Disable DREQ for the selected channel. DMA Channel Select -- WO. These bits select the DMA Channel Mode Register to program. 00 = Channel 0 (4) 01 = Channel 1 (5) 10 = Channel 2 (6) 11 = Channel 3 (7) Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 421 LPC Interface Bridge Registers (D31:F0) 13.2.7 DMACH_MODE--DMA Channel Mode Register I/O Address: Default Value: Lockable: 13.2.8 Attribute: Size: Power Well: WO 8-bit Core Bit Description 7:6 DMA Transfer Mode -- WO. Each DMA channel can be programmed in one of four different modes: 00 = Demand mode 01 = Single mode 10 = Reserved 11 = Cascade mode 5 Address Increment/Decrement Select -- WO. This bit controls address increment/decrement during DMA transfers. 0 = Address increment. (default after part reset or Master Clear) 1 = Address decrement. 4 Autoinitialize Enable -- WO. 0 = Autoinitialize feature is disabled and DMA transfers terminate on a terminal count. A part reset or Master Clear disables autoinitialization. 1 = DMA restores the Base Address and Count registers to the current registers following a terminal count (TC). 3:2 DMA Transfer Type -- WO. These bits represent the direction of the DMA transfer. When the channel is programmed for cascade mode, (bits[7:6] = 11) the transfer type is irrelevant. 00 = Verify - No I/O or memory strobes generated 01 = Write - Data transferred from the I/O devices to memory 10 = Read - Data transferred from memory to the I/O device 11 = Invalid 1:0 DMA Channel Select -- WO. These bits select the DMA Channel Mode Register that will be written by bits [7:2]. 00 = Channel 0 (4) 01 = Channel 1 (5) 10 = Channel 2 (6) 11 = Channel 3 (7) DMA Clear Byte Pointer Register I/O Address: Default Value: Lockable: 422 Ch. #0-3 = 0Bh; Ch. #4-7 = D6h 0000 00xx No Ch. #0-3 = 0Ch; Ch. #4-7 = D8h xxxx xxxx No Attribute: Size: Power Well: WO 8-bit Core Bit Description 7:0 Clear Byte Pointer -- WO. No specific pattern. Command enabled with a write to the I/O port address. Writing to this register initializes the byte pointer flip/flop to a known state. It clears the internal latch used to address the upper or lower byte of the 16-bit Address and Word Count Registers. The latch is also cleared by part reset and by the Master Clear command. This command precedes the first access to a 16-bit DMA controller register. The first access to a 16-bit register will then access the significant byte, and the second access automatically accesses the most significant byte. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.2.9 DMA Master Clear Register I/O Address: Default Value: 13.2.10 Ch. #0-3 = 0Dh; Ch. #4-7 = DAh xxxx xxxx WO 8-bit Bit Description 7:0 Master Clear -- WO. No specific pattern. Enabled with a write to the port. This has the same effect as the hardware Reset. The Command, Status, Request, and Byte Pointer flip/flop registers are cleared and the Mask Register is set. DMA_CLMSK--DMA Clear Mask Register I/O Address: Default Value: Lockable: Ch. #0-3 = 0Eh; Ch. #4-7 = DCh xxxx xxxx No Bit 7:0 13.2.11 Attribute: Size: Attribute: Size: Power Well: WO 8-bit Core Description Clear Mask Register -- WO. No specific pattern. Command enabled with a write to the port. DMA_WRMSK--DMA Write All Mask Register I/O Address: Default Value: Lockable: Ch. #0-3 = 0Fh; Ch. #4-7 = DEh 0000 1111 No Bit 7:4 3:0 Attribute: Size: Power Well: R/W 8-bit Core Description Reserved. Must be 0. Channel Mask Bits -- R/W. This register permits all four channels to be simultaneously enabled/ disabled instead of enabling/disabling each channel individually, as is the case with the Mask Register - Write Single Mask Bit. In addition, this register has a read path to allow the status of the channel mask bits to be read. A channel's mask bit is automatically set to 1 when the Current Byte/ Word Count Register reaches terminal count (unless the channel is in auto-initialization mode). Setting the bit(s) to a 1 disables the corresponding DREQ(s). Setting the bit(s) to a 0 enables the corresponding DREQ(s). Bits [3:0] are set to 1 upon part reset or Master Clear. When read, bits [3:0] indicate the DMA channel [3:0] ([7:4]) mask status. Bit 0 = Channel 0 (4)1 = Masked, 0 = Not Masked Bit 1 = Channel 1 (5)1 = Masked, 0 = Not Masked Bit 2 = Channel 2 (6)1 = Masked, 0 = Not Masked Bit 3 = Channel 3 (7)1 = Masked, 0 = Not Masked Note: Disabling channel 4 also disables channels 0-3 due to the cascade of channels 0 - 3 through channel 4. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 423 LPC Interface Bridge Registers (D31:F0) 13.3 Timer I/O Registers Port Aliases 40h 50h 41h 51h 42h 52h 43h 53h Register Name Counter 0 Interval Time Status Byte Format Counter 0 Counter Access Port Counter 1 Interval Time Status Byte Format Counter 1 Counter Access Port Counter 2 Interval Time Status Byte Format Counter 2 Counter Access Port Timer Control Word Timer Control Word Register Default Value 0XXXXXXXb RO Undefined R/W 0XXXXXXXb RO Undefined R/W 0XXXXXXXb RO Undefined R/W Undefined WO XXXXXXX0b WO X0h WO Counter Latch Command 13.3.1 Type TCW--Timer Control Word Register I/O Address: Default Value: 43h All bits undefined Attribute: Size: WO 8 bits This register is programmed prior to any counter being accessed to specify counter modes. Following part reset, the control words for each register are undefined and each counter output is 0. Each timer must be programmed to bring it into a known state. Bit Description 7:6 Counter Select -- WO. The Counter Selection bits select the counter the control word acts upon as shown below. The Read Back Command is selected when bits[7:6] are both 1. 00 = Counter 0 select 01 = Counter 1 select 10 = Counter 2 select 11 = Read Back Command 5:4 Read/Write Select -- WO. These bits are the read/write control bits. The actual counter programming is done through the counter port (40h for counter 0, 41h for counter 1, and 42h for counter 2). 00 = Counter Latch Command 01 = Read/Write Least Significant Byte (LSB) 10 = Read/Write Most Significant Byte (MSB) 11 = Read/Write LSB then MSB Counter Mode Selection -- WO. These bits select one of six possible modes of operation for the selected counter. Bit Value 3:1 0 424 Mode 000b Mode 0 Out signal on end of count (=0) 001b Mode 1 Hardware retriggerable one-shot x10b Mode 2 Rate generator (divide by n counter) x11b Mode 3 Square wave output 100b Mode 4 Software triggered strobe 101b Mode 5 Hardware triggered strobe Binary/BCD Countdown Select -- WO. 0 = Binary countdown is used. The largest possible binary count is 216 1 = Binary coded decimal (BCD) count is used. The largest possible BCD count is 104 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) There are two special commands that can be issued to the counters through this register, the Read Back Command and the Counter Latch Command. When these commands are chosen, several bits within this register are redefined. These register formats are described below: RDBK_CMD--Read Back Command The Read Back Command is used to determine the count value, programmed mode, and current states of the OUT pin and Null count flag of the selected counter or counters. Status and/or count may be latched in any or all of the counters by selecting the counter during the register write. The count and status remain latched until read, and further latch commands are ignored until the count is read. Both count and status of the selected counters may be latched simultaneously by setting both bit 5 and bit 4 to 0. If both are latched, the first read operation from that counter returns the latched status. The next one or two reads, depending on whether the counter is programmed for one or two byte counts, returns the latched count. Subsequent reads return an unlatched count. Bit 7:6 Description Read Back Command. Must be 11 to select the Read Back Command 5 Latch Count of Selected Counters. 0 = Current count value of the selected counters will be latched 1 = Current count will not be latched 4 Latch Status of Selected Counters. 0 = Status of the selected counters will be latched 1 = Status will not be latched 3 Counter 2 Select. 1 = Counter 2 count and/or status will be latched 2 Counter 1 Select. 1 = Counter 1 count and/or status will be latched 1 Counter 0 Select. 1 = Counter 0 count and/or status will be latched. 0 Reserved. Must be 0. LTCH_CMD--Counter Latch Command The Counter Latch Command latches the current count value. This command is used to insure that the count read from the counter is accurate. The count value is then read from each counter's count register through the Counter Ports Access Ports Register (40h for counter 0, 41h for counter 1, and 42h for counter 2). The count must be read according to the programmed format, that is, if the counter is programmed for two byte counts, two bytes must be read. The two bytes do not have to be read one right after the other (read, write, or programming operations for other counters may be inserted between the reads). If a counter is latched once and then latched again before the count is read, the second Counter Latch Command is ignored. Bit Description 7:6 Counter Selection. These bits select the counter for latching. If "11" is written, then the write is interpreted as a read back command. 00 = Counter 0 01 = Counter 1 10 = Counter 2 5:4 Counter Latch Command. 00 = Selects the Counter Latch Command. 3:0 Reserved. Must be 0. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 425 LPC Interface Bridge Registers (D31:F0) 13.3.2 SBYTE_FMT--Interval Timer Status Byte Format Register I/O Address: Default Value: Counter 0 = 40h, Counter 1 = 41h, Attribute: Counter 2 = 42h Size: Bits[6:0] undefined, Bit 7=0 RO 8 bits per counter Each counter's status byte can be read following a Read Back Command. If latch status is chosen (bit 4=0, Read Back Command) as a read back option for a given counter, the next read from the counter's Counter Access Ports Register (40h for counter 0, 41h for counter 1, and 42h for counter 2) returns the status byte. The status byte returns the following: Bit 7 Counter OUT Pin State -- RO. 0 = OUT pin of the counter is also a 0 1 = OUT pin of the counter is also a 1 6 Count Register Status -- RO. This bit indicates when the last count written to the Count Register (CR) has been loaded into the counting element (CE). The exact time this happens depends on the counter mode, but until the count is loaded into the counting element (CE), the count value will be incorrect. 0 = Count has been transferred from CR to CE and is available for reading. 1 = Null Count. Count has not been transferred from CR to CE and is not yet available for reading. 5:4 Read/Write Selection Status -- RO. These reflect the read/write selection made through bits[5:4] of the control register. The binary codes returned during the status read match the codes used to program the counter read/write selection. 00 = Counter Latch Command 01 = Read/Write Least Significant Byte (LSB) 10 = Read/Write Most Significant Byte (MSB) 11 = Read/Write LSB then MSB 3:1 Mode Selection Status -- RO. These bits return the counter mode programming. The binary code returned matches the code used to program the counter mode, as listed under the bit function above. 000 = Mode 0 -- Out signal on end of count (=0) 001 = Mode 1 -- Hardware retriggerable one-shot x10 = Mode 2 -- Rate generator (divide by n counter) x11 = Mode 3 -- Square wave output 100 = Mode 4 -- Software triggered strobe 101 = Mode 5 -- Hardware triggered strobe 0 13.3.3 Description Countdown Type Status -- RO. This bit reflects the current countdown type. 0 = Binary countdown 1 = Binary Coded Decimal (BCD) countdown. Counter Access Ports Register I/O Address: Default Value: 426 Counter 0 - 40h, Counter 1 - 41h, Counter 2 - 42h All bits undefined Attribute: R/W Size: 8 bit Bit Description 7:0 Counter Port -- R/W. Each counter port address is used to program the 16-bit Count Register. The order of programming, either LSB only, MSB only, or LSB then MSB, is defined with the Interval Counter Control Register at port 43h. The counter port is also used to read the current count from the Count Register, and return the status of the counter programming following a Read Back Command. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.4 8259 Interrupt Controller (PIC) Registers 13.4.1 Interrupt Controller I/O MAP The interrupt controller registers are located at 20h and 21h for the master controller (IRQ 0-7), and at A0h and A1h for the slave controller (IRQ 8-13). These registers have multiple functions, depending upon the data written to them. Table 13-3 shows the different register possibilities for each address. Table 13-3. PIC Registers Port Aliases 20h 24h, 28h, 2Ch, 30h, 34h, 38h, 3Ch 21h A0h A1h 25h, 29h, 2Dh, 31h, 35h, 39h, 3Dh A4h, A8h, ACh, B0h, B4h, B8h, BCh A5h, A9h, ADh, B1h, B5h, B9h, BDh Register Name Default Value Master PIC ICW1 Init. Cmd Word 1 Type Undefined WO Master PIC OCW2 Op Ctrl Word 2 001XXXXXb WO Master PIC OCW3 Op Ctrl Word 3 X01XXX10b WO Master PIC ICW2 Init. Cmd Word 2 Undefined WO Master PIC ICW3 Init. Cmd Word 3 Undefined WO Master PIC ICW4 Init. Cmd Word 4 01h WO Master PIC OCW1 Op Ctrl Word 1 00h R/W Slave PIC ICW1 Init. Cmd Word 1 Undefined WO Slave PIC OCW2 Op Ctrl Word 2 001XXXXXb WO Slave PIC OCW3 Op Ctrl Word 3 X01XXX10b WO Slave PIC ICW2 Init. Cmd Word 2 Undefined WO Slave PIC ICW3 Init. Cmd Word 3 Undefined WO Slave PIC ICW4 Init. Cmd Word 4 01h WO Slave PIC OCW1 Op Ctrl Word 1 00h R/W 4D0h - Master PIC Edge/Level Triggered 00h R/W 4D1h - Slave PIC Edge/Level Triggered 00h R/W Note: Refer to note addressing active-low interrupt sources in 8259 Interrupt Controllers section (Chapter 5.9). 13.4.2 ICW1--Initialization Command Word 1 Register Offset Address: Master Controller - 20h Slave Controller - A0h Default Value: All bits undefined Attribute: Size: WO 8 bit /controller A write to Initialization Command Word 1 starts the interrupt controller initialization sequence, during which the following occurs: 1. The Interrupt Mask register is cleared. 2. IRQ7 input is assigned priority 7. 3. The slave mode address is set to 7. 4. Special mask mode is cleared and Status Read is set to IRR. Once this write occurs, the controller expects writes to ICW2, ICW3, and ICW4 to complete the initialization sequence. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 427 LPC Interface Bridge Registers (D31:F0) Bit 7:5 13.4.3 Description ICW/OCW Select -- WO. These bits are MCS-85 specific, and not needed. 000 = Should be programmed to "000" 4 ICW/OCW Select -- WO. 1 = This bit must be a 1 to select ICW1 and enable the ICW2, ICW3, and ICW4 sequence. 3 Edge/Level Bank Select (LTIM) -- WO. Disabled. Replaced by the edge/level triggered control registers (ELCR, D31:F0:4D0h, D31:F0:4D1h). 2 ADI -- WO. 0 = Ignored for the PCH. Should be programmed to 0. 1 Single or Cascade (SNGL) -- WO. 0 = Must be programmed to a 0 to indicate two controllers operating in cascade mode. 0 ICW4 Write Required (IC4) -- WO. 1 = This bit must be programmed to a 1 to indicate that ICW4 needs to be programmed. ICW2--Initialization Command Word 2 Register Offset Address: Master Controller - 21h Slave Controller - A1h Default Value: All bits undefined Attribute: Size: WO 8 bit /controller ICW2 is used to initialize the interrupt controller with the five most significant bits of the interrupt vector address. The value programmed for bits[7:3] is used by the processor to define the base address in the interrupt vector table for the interrupt routines associated with each IRQ on the controller. Typical ISA ICW2 values are 08h for the master controller and 70h for the slave controller. Bit Description 7:3 Interrupt Vector Base Address -- WO. Bits [7:3] define the base address in the interrupt vector table for the interrupt routines associated with each interrupt request level input. Interrupt Request Level -- WO. When writing ICW2, these bits should all be 0. During an interrupt acknowledge cycle, these bits are programmed by the interrupt controller with the interrupt to be serviced. This is combined with bits [7:3] to form the interrupt vector driven onto the data bus during the second INTA# cycle. The code is a three bit binary code: 2:0 428 Code Master Interrupt Slave Interrupt 000b IRQ0 IRQ8 001b IRQ1 IRQ9 010b IRQ2 IRQ10 011b IRQ3 IRQ11 100b IRQ4 IRQ12 101b IRQ5 IRQ13 110b IRQ6 IRQ14 111b IRQ7 IRQ15 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.4.4 ICW3--Master Controller Initialization Command Word 3 Register Offset Address: 21h Default Value: All bits undefined Bit 7:3 2 1:0 13.4.5 WO 8 bits Description 0 = These bits must be programmed to 0. Cascaded Interrupt Controller IRQ Connection -- WO. This bit indicates that the slave controller is cascaded on IRQ2. When IRQ8#-IRQ15 is asserted, it goes through the slave controller's priority resolver. The slave controller's INTR output onto IRQ2. IRQ2 then goes through the master controller's priority solver. If it wins, the INTR signal is asserted to the processor, and the returning interrupt acknowledge returns the interrupt vector for the slave controller. 1 = This bit must always be programmed to a 1. 0 = These bits must be programmed to 0. ICW3--Slave Controller Initialization Command Word 3 Register Offset Address: A1h Default Value: All bits undefined Bit 13.4.6 Attribute: Size: Attribute: Size: WO 8 bits Description 7:3 0 = These bits must be programmed to 0. 2:0 Slave Identification Code -- WO. These bits are compared against the slave identification code broadcast by the master controller from the trailing edge of the first internal INTA# pulse to the trailing edge of the second internal INTA# pulse. These bits must be programmed to 02h to match the code broadcast by the master controller. When 02h is broadcast by the master controller during the INTA# sequence, the slave controller assumes responsibility for broadcasting the interrupt vector. ICW4--Initialization Command Word 4 Register Offset Address: Master Controller - 021h Slave Controller - 0A1h Default Value: 01h Bit 7:5 Attribute: Size: WO 8 bits Description 0 = These bits must be programmed to 0. 4 Special Fully Nested Mode (SFNM) -- WO. 0 = Should normally be disabled by writing a 0 to this bit. 1 = Special fully nested mode is programmed. 3 Buffered Mode (BUF) -- WO. 0 = Must be programmed to 0 for the PCH. This is non-buffered mode. 2 Master/Slave in Buffered Mode -- WO. Not used. 0 = Should always be programmed to 0. 1 Automatic End of Interrupt (AEOI) -- WO. 0 = This bit should normally be programmed to 0. This is the normal end of interrupt. 1 = Automatic End of Interrupt (AEOI) mode is programmed. 0 Microprocessor Mode -- WO. 1 = Must be programmed to 1 to indicate that the controller is operating in an Intel Architecture-based system. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 429 LPC Interface Bridge Registers (D31:F0) 13.4.7 OCW1--Operational Control Word 1 (Interrupt Mask) Register Offset Address: Master Controller - 021h Slave Controller - 0A1h Default Value: 00h 13.4.8 Attribute: Size: R/W 8 bits Bit Description 7:0 Interrupt Request Mask -- R/W. When a 1 is written to any bit in this register, the corresponding IRQ line is masked. When a 0 is written to any bit in this register, the corresponding IRQ mask bit is cleared, and interrupt requests will again be accepted by the controller. Masking IRQ2 on the master controller will also mask the interrupt requests from the slave controller. OCW2--Operational Control Word 2 Register Offset Address: Master Controller - 020h Attribute: Size: Slave Controller - 0A0h Default Value: Bit[4:0]=undefined, Bit[7:5]=001 WO 8 bits Following a part reset or ICW initialization, the controller enters the fully nested mode of operation. Non-specific EOI without rotation is the default. Both rotation mode and specific EOI mode are disabled following initialization. Bit Description 7:5 Rotate and EOI Codes (R, SL, EOI) -- WO. These three bits control the Rotate and End of Interrupt modes and combinations of the two. 000 = Rotate in Auto EOI Mode (Clear) 001 = Non-specific EOI command 010 = No Operation 011 = *Specific EOI Command 100 = Rotate in Auto EOI Mode (Set) 101 = Rotate on Non-Specific EOI Command 110 = *Set Priority Command 111 = *Rotate on Specific EOI Command *L0 - L2 Are Used 4:3 OCW2 Select -- WO. When selecting OCW2, bits 4:3 = 00 Interrupt Level Select (L2, L1, L0) -- WO. L2, L1, and L0 determine the interrupt level acted upon when the SL bit is active. A simple binary code, outlined below, selects the channel for the command to act upon. When the SL bit is inactive, these bits do not have a defined function; programming L2, L1 and L0 to 0 is sufficient in this case. 2:0 430 Code Interrupt Level Code Interrupt Level 000b IRQ0/8 000b IRQ4/12 001b IRQ1/9 001b IRQ5/13 010b IRQ2/10 010b IRQ6/14 011b IRQ3/11 011b IRQ7/15 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.4.9 OCW3--Operational Control Word 3 Register Offset Address: Master Controller - 020h Attribute: Size: Slave Controller - 0A0h Default Value: Bit[6,0]=0, Bit[7,4:2]=undefined, Bit[5,1]=1 Bit Description 7 Reserved. Must be 0. 6 Special Mask Mode (SMM) -- WO. 1 = The Special Mask Mode can be used by an interrupt service routine to dynamically alter the system priority structure while the routine is executing, through selective enabling/disabling of the other channel's mask bits. Bit 5, the ESMM bit, must be set for this bit to have any meaning. 5 Enable Special Mask Mode (ESMM) -- WO. 0 = Disable. The SMM bit becomes a "don't care". 1 = Enable the SMM bit to set or reset the Special Mask Mode. 4:3 13.4.10 WO 8 bits OCW3 Select -- WO. When selecting OCW3, bits 4:3 = 01 2 Poll Mode Command -- WO. 0 = Disable. Poll Command is not issued. 1 = Enable. The next I/O read to the interrupt controller is treated as an interrupt acknowledge cycle. An encoded byte is driven onto the data bus, representing the highest priority level requesting service. 1:0 Register Read Command -- WO. These bits provide control for reading the In-Service Register (ISR) and the Interrupt Request Register (IRR). When bit 1=0, bit 0 will not affect the register read selection. When bit 1=1, bit 0 selects the register status returned following an OCW3 read. If bit 0=0, the IRR will be read. If bit 0=1, the ISR will be read. Following ICW initialization, the default OCW3 port address read will be "read IRR". To retain the current selection (read ISR or read IRR), always write a 0 to bit 1 when programming this register. The selected register can be read repeatedly without reprogramming OCW3. To select a new status register, OCW3 must be reprogrammed prior to attempting the read. 00 = No Action 01 = No Action 10 = Read IRQ Register 11 = Read IS Register ELCR1--Master Controller Edge/Level Triggered Register Offset Address: 4D0h Default Value: 00h Attribute: Size: R/W 8 bits In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In level mode (bit[x] = 1), the interrupt is recognized by a high level. The cascade channel, IRQ2, the heart beat timer (IRQ0), and the keyboard controller (IRQ1), cannot be put into level mode. Bit Description 7 IRQ7 ECL -- R/W. 0 = Edge 1 = Level 6 IRQ6 ECL -- R/W. 0 = Edge 1 = Level 5 IRQ5 ECL -- R/W. 0 = Edge 1 = Level Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 431 LPC Interface Bridge Registers (D31:F0) Bit 4 IRQ4 ECL -- R/W. 0 = Edge 1 = Level 3 IRQ3 ECL -- R/W. 0 = Edge 1 = Level 2:0 13.4.11 Description Reserved. Must be 0. ELCR2--Slave Controller Edge/Level Triggered Register Offset Address: 4D1h Default Value: 00h Attribute: Size: R/W 8 bits In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In level mode (bit[x] = 1), the interrupt is recognized by a high level. The real time clock, IRQ8#, and the floating point error interrupt, IRQ13, cannot be programmed for level mode. Bit Description 7 IRQ15 ECL -- R/W. 0 = Edge 1 = Level 6 IRQ14 ECL -- R/W. 0 = Edge 1 = Level 5 Reserved. Must be 0. 4 IRQ12 ECL -- R/W. 0 = Edge 1 = Level 3 IRQ11 ECL -- R/W. 0 = Edge 1 = Level 2 IRQ10 ECL -- R/W. 0 = Edge 1 = Level 1 IRQ9 ECL -- R/W. 0 = Edge 1 = Level 0 Reserved. Must be 0. 13.5 Advanced Programmable Interrupt Controller (APIC) 13.5.1 APIC Register Map The APIC is accessed using an indirect addressing scheme. Two registers are visible by software for manipulation of most of the APIC registers. These registers are mapped into memory space. The address bits 19:12 of the address range are programmable through bits 7:0 of OIC register (Chipset Config Registers:Offset 31FEh) The registers are shown in Table 13-4. 432 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) Table 13-4. APIC Direct Registers Address Mnemonic Register Name Size Type FEC_ _0000h IND FEC_ _0010h DAT Index 8 bits R/W Data 32 bits R/W FEC_ _0040h EOIR EOI 32 bits WO Table 13-5 lists the registers which can be accessed within the APIC using the Index Register. When accessing these registers, accesses must be done one DWord at a time. For example, software should never access byte 2 from the Data register before accessing bytes 0 and 1. The hardware will not attempt to recover from a bad programming model in this case. Table 13-5. APIC Indirect Registers 13.5.2 Index Mnemonic 00 ID Register Name Size Type Identification 32 bits R/W Version 32 bits RO -- RO 01 VER 02-0F -- 10-11 REDIR_TBL0 Redirection Table 0 64 bits R/W, RO 12-13 REDIR_TBL1 Redirection Table 1 64 bits R/W, RO ... ... 3E-3F REDIR_TBL23 40-FF -- Reserved ... Redirection Table 23 ... ... 64 bits R/W, RO -- RO Reserved IND--Index Register Memory Address FEC_ _0000h Default Value: 00h Attribute: Size: R/W 8 bits The Index Register will select which APIC indirect register to be manipulated by software. The selector values for the indirect registers are listed in Table 13-5. Software will program this register to select the desired APIC internal register. Bit 7:0 Description APIC Index -- R/W. This is an 8-bit pointer into the I/O APIC register table. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 433 LPC Interface Bridge Registers (D31:F0) 13.5.3 DAT--Data Register Memory Address FEC_ _0000h Default Value: 00000000h Attribute: Size: R/W 32 bits This is a 32-bit register specifying the data to be read or written to the register pointed to by the Index register. This register can only be accessed in dword quantities. Bit 7:0 13.5.4 Description APIC Data -- R/W. This is a 32-bit register for the data to be read or written to the APIC indirect register (Figure 13-5) pointed to by the Index register (Memory Address FEC0_0000h). EOIR--EOI Register Memory Address FEC_ _0000h Default Value: N/A Attribute: Size: R/W 32 bits The EOI register is present to provide a mechanism to maintain the level triggered semantics for level-triggered interrupts issued on the parallel bus. When a write is issued to this register, the I/O APIC will check the lower 8 bits written to this register, and compare it with the vector field for each entry in the I/O Redirection Table. When a match is found, the Remote_IRR bit (Index Offset 10h, bit 14) for that I/O Redirection Entry will be cleared. Note: If multiple I/O Redirection entries, for any reason, assign the same vector for more than one interrupt input, each of those entries will have the Remote_IRR bit reset to 0. The interrupt which was prematurely reset will not be lost because if its input remained active when the Remote_IRR bit is cleared, the interrupt will be reissued and serviced at a later time. Note that only bits 7:0 are actually used. Bits 31:8 are ignored by the PCH. Note: To provide for future expansion, the processor should always write a value of 0 to Bits 31:8. Bit 31:8 7:0 13.5.5 Description Reserved. To provide for future expansion, the processor should always write a value of 0 to Bits 31:8. Redirection Entry Clear -- WO. When a write is issued to this register, the I/O APIC will check this field, and compare it with the vector field for each entry in the I/O Redirection Table. When a match is found, the Remote_IRR bit for that I/O Redirection Entry will be cleared. ID--Identification Register Index Offset: Default Value: 00h 00000000h Attribute: Size: R/W 32 bits The APIC ID serves as a physical name of the APIC. The APIC bus arbitration ID for the APIC is derived from its I/O APIC ID. This register is reset to 0 on power-up reset. Bit 31:28 Reserved 27:24 APIC ID -- R/W. Software must program this value before using the APIC. 23:16 Reserved 15 14:0 434 Description Scratchpad Bit. Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.5.6 VER--Version Register Index Offset: Default Value: 01h 00170020h Attribute: Size: RO, R/WO 32 bits Each I/O APIC contains a hardwired Version Register that identifies different implementation of APIC and their versions. The maximum redirection entry information also is in this register, to let software know how many interrupt are supported by this APIC. Bit 31:24 Reserved 23:16 Maximum Redirection Entries (MRE) -- R/WO. This is the entry number (0 being the lowest entry) of the highest entry in the redirection table. It is equal to the number of interrupt input pins minus one and is in the range 0 through 239. In the PCH this field is hardwired to 17h to indicate 24 interrupts. BIOS must write to this field after PLTRST# to lockdown the value. this allows BIOS to utilize some of the entries for its own purpose and thus advertising fewer IOxAPIC Redirection Entries to the OS. 15 14:8 7:0 13.5.7 Description Pin Assertion Register Supported (PRQ) -- RO. Indicate that the IOxAPIC does not implement the Pin Assertion Register. Reserved Version (VS) -- RO. This is a version number that identifies the implementation version. REDIR_TBL--Redirection Table Index Offset: 10h-11h (vector 0) through 3E-3Fh (vector 23) Default Value: Bit 16 = 1. All other bits undefined Attribute: R/W, RO Size: 64 bits each, (accessed as two 32 bit quantities) The Redirection Table has a dedicated entry for each interrupt input pin. The information in the Redirection Table is used to translate the interrupt manifestation on the corresponding interrupt pin into an APIC message. The APIC will respond to an edge triggered interrupt as long as the interrupt is held until after the acknowledge cycle has begun. Once the interrupt is detected, a delivery status bit internally to the I/O APIC is set. The state machine will step ahead and wait for an acknowledgment from the APIC unit that the interrupt message was sent. Only then will the I/O APIC be able to recognize a new edge on that interrupt pin. That new edge will only result in a new invocation of the handler if its acceptance by the destination APIC causes the Interrupt Request Register bit to go from 0 to 1. (In other words, if the interrupt was not already pending at the destination.) Bit Description 63:56 Destination -- R/W. If bit 11 of this entry is 0 (Physical), then bits 59:56 specifies an APIC ID. In this case, bits 63:59 should be programmed by software to 0. If bit 11 of this entry is 1 (Logical), then bits 63:56 specify the logical destination address of a set of processors. 55:48 Extended Destination ID (EDID) -- RO. These bits are sent to a local APIC only when in Processor System Bus mode. They become bits 11:4 of the address. 47:17 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 435 LPC Interface Bridge Registers (D31:F0) Bit Description 16 Mask -- R/W. 0 = Not masked: An edge or level on this interrupt pin results in the delivery of the interrupt to the destination. 1 = Masked: Interrupts are not delivered nor held pending. Setting this bit after the interrupt is accepted by a local APIC has no effect on that interrupt. This behavior is identical to the device withdrawing the interrupt before it is posted to the processor. It is software's responsibility to deal with the case where the mask bit is set after the interrupt message has been accepted by a local APIC unit but before the interrupt is dispensed to the processor. 15 Trigger Mode -- R/W. This field indicates the type of signal on the interrupt pin that triggers an interrupt. 0 = Edge triggered. 1 = Level triggered. 14 Remote IRR -- R/W. This bit is used for level triggered interrupts; its meaning is undefined for edge triggered interrupts. 0 = Reset when an EOI message is received from a local APIC. 1 = Set when Local APIC/s accept the level interrupt sent by the I/O APIC. 13 Interrupt Input Pin Polarity -- R/W. This bit specifies the polarity of each interrupt signal connected to the interrupt pins. 0 = Active high. 1 = Active low. 12 Delivery Status -- RO. This field contains the current status of the delivery of this interrupt. Writes to this bit have no effect. 0 = Idle. No activity for this interrupt. 1 = Pending. Interrupt has been injected, but delivery is not complete. 11 Destination Mode -- R/W. This field determines the interpretation of the Destination field. 0 = Physical. Destination APIC ID is identified by bits 59:56. 1 = Logical. Destinations are identified by matching bit 63:56 with the Logical Destination in the Destination Format Register and Logical Destination Register in each Local APIC. 10:8 Delivery Mode -- R/W. This field specifies how the APICs listed in the destination field should act upon reception of this signal. Certain Delivery Modes will only operate as intended when used in conjunction with a specific trigger mode. These encodings are listed in the note below: 7:0 Vector -- R/W. This field contains the interrupt vector for this interrupt. Values range between 10h and FEh. Note: Delivery Mode encoding: 000 = Fixed. Deliver the signal on the INTR signal of all processor cores listed in the destination. Trigger Mode can be edge or level. 001 = Lowest Priority. Deliver the signal on the INTR signal of the processor core that is executing at the lowest priority among all the processors listed in the specified destination. Trigger Mode can be edge or level. 010 = SMI (System Management Interrupt). Requires the interrupt to be programmed as edge triggered. The vector information is ignored but must be programmed to all 0s for future compatibility: not supported 011 = Reserved 100 = NMI. Deliver the signal on the NMI signal of all processor cores listed in the destination. Vector information is ignored. NMI is treated as an edge triggered interrupt even if it is programmed as level triggered. For proper operation this redirection table entry must be programmed to edge triggered. The NMI delivery mode does not set the RIRR bit. If the redirection table is incorrectly set to level, the loop count will continue counting through the redirection table addresses. Once the count for the NMI pin is reached again, the interrupt will be sent again: not supported 101 = INIT. Deliver the signal to all processor cores listed in the destination by asserting the INIT signal. All addressed local APICs will assume their INIT state. INIT is always treated as an edge triggered interrupt even if programmed as level triggered. For proper operation this redirection table entry must be programmed to edge triggered. The INIT delivery mode does not set the RIRR bit. If the redirection table is incorrectly set to level, the loop count will continue counting through the redirection table addresses. Once the count for the INIT pin is reached again, the interrupt will be sent again: not supported 110 = Reserved 111 = ExtINT. Deliver the signal to the INTR signal of all processor cores listed in the destination as an interrupt that originated in an externally connected 8259A compatible interrupt controller. The INTA cycle that corresponds to this ExtINT delivery will be routed to the external controller that is expected to supply the vector. Requires the interrupt to be programmed as edge triggered. 436 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.6 Real Time Clock Registers 13.6.1 I/O Register Address Map The RTC internal registers and RAM are organized as two banks of 128 bytes each, called the standard and extended banks. The first 14 bytes of the standard bank contain the RTC time and date information along with four registers, A-D, that are used for configuration of the RTC. The extended bank contains a full 128 bytes of battery backed SRAM, and will be accessible even when the RTC module is disabled (using the RTC configuration register). Registers A-D do not physically exist in the RAM. All data movement between the host processor and the real-time clock is done through registers mapped to the standard I/O space. The register map appears in Table 13-6. Table 13-6. RTC I/O Registers I/O Locations If U128E bit = 0 70h and 74h Also alias to 72h and 76h Real-Time Clock (Standard RAM) Index Register 71h and 75h Also alias to 73h and 77h Real-Time Clock (Standard RAM) Target Register Function 72h and 76h Extended RAM Index Register (if enabled) 73h and 77h Extended RAM Target Register (if enabled) Notes: 1. I/O locations 70h and 71h are the standard legacy location for the real-time clock. The map for this bank is shown in Table 13-7. Locations 72h and 73h are for accessing the extended RAM. The extended RAM bank is also accessed using an indexed scheme. I/O address 72h is used as the address pointer and I/O address 73h is used as the data register. Index addresses above 127h are not valid. If the extended RAM is not needed, it may be disabled. 2. Software must preserve the value of bit 7 at I/O addresses 70h and 74h. When writing to this address, software must first read the value, and then write the same value for bit 7 during the sequential address write. Note that port 70h is not directly readable. The only way to read this register is through Alt Access mode. Although RTC Index bits 6:0 are readable from port 74h, bit 7 will always return 0. If the NMI# enable is not changed during normal operation, software can alternatively read this bit once and then retain the value for all subsequent writes to port 70h. 13.6.2 Indexed Registers The RTC contains two sets of indexed registers that are accessed using the two separate Index and Target registers (70/71h or 72/73h), as shown in Table 13-7. Table 13-7. RTC (Standard) RAM Bank Index Name 00h Seconds 01h Seconds Alarm 02h Minutes 03h Minutes Alarm 04h Hours 05h Hours Alarm 06h Day of Week 07h Day of Month 08h Month 09h Year 0Ah Register A 0Bh Register B 0Ch Register C 0Dh Register D 0Eh-7Fh 114 Bytes of User RAM Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 437 LPC Interface Bridge Registers (D31:F0) 13.6.2.1 RTC_REGA--Register A RTC Index: Default Value: Lockable: 0A Undefined No Attribute: Size: Power Well: R/W 8-bit RTC This register is used for general configuration of the RTC functions. None of the bits are affected by RSMRST# or any other PCH reset signal. 438 Bit Description 7 Update In Progress (UIP) -- R/W. This bit may be monitored as a status flag. 0 = The update cycle will not start for at least 488 s. The time, calendar, and alarm information in RAM is always available when the UIP bit is 0. 1 = The update is soon to occur or is in progress. 6:4 Division Chain Select (DV[2:0]) -- R/W. These three bits control the divider chain for the oscillator, and are not affected by RSMRST# or any other reset signal. 010 = Normal Operation 11X = Divider Reset 101 = Bypass 15 stages (test mode only) 100 = Bypass 10 stages (test mode only) 011 = Bypass 5 stages (test mode only) 001 = Invalid 000 = Invalid 3:0 Rate Select (RS[3:0]) -- R/W. Selects one of 13 taps of the 15 stage divider chain. The selected tap can generate a periodic interrupt if the PIE bit is set in Register B. Otherwise this tap will set the PF flag of Register C. If the periodic interrupt is not to be used, these bits should all be set to 0. RS3 corresponds to bit 3. 0000 = Interrupt never toggles 0001 = 3.90625 ms 0010 = 7.8125 ms 0011 = 122.070 s 0100 = 244.141 s 0101 = 488.281 s 0110 = 976.5625 s 0111 = 1.953125 ms 1000 = 3.90625 ms 1001 = 7.8125 ms 1010 = 15.625 ms 1011 = 31.25 ms 1100 = 62.5 ms 1101 = 125 ms 1110 = 250 ms 1111= 500 ms Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.6.2.2 RTC_REGB--Register B (General Configuration) RTC Index: Default Value: Lockable: 0Bh Attribute: U0U00UUU (U: Undefined) Size: No Power Well: Bit 7 R/W 8-bit RTC Description Update Cycle Inhibit (SET) -- R/W. Enables/Inhibits the update cycles. This bit is not affected by RSMRST# nor any other reset signal. 0 = Update cycle occurs normally once each second. 1 = A current update cycle will abort and subsequent update cycles will not occur until SET is returned to 0. When set is one, the BIOS may initialize time and calendar bytes safely. Note: This bit should be set then cleared early in BIOS POST after each powerup directly after coin-cell battery insertion. 6 Periodic Interrupt Enable (PIE) -- R/W. This bit is cleared by RSMRST#, but not on any other reset. 0 = Disable. 1 = Enable. Allows an interrupt to occur with a time base set with the RS bits of register A. 5 Alarm Interrupt Enable (AIE) -- R/W. This bit is cleared by RTCRST#, but not on any other reset. 0 = Disable. 1 = Enable. Allows an interrupt to occur when the AF is set by an alarm match from the update cycle. An alarm can occur once a second, one an hour, once a day, or one a month. 4 Update-Ended Interrupt Enable (UIE) -- R/W. This bit is cleared by RSMRST#, but not on any other reset. 0 = Disable. 1 = Enable. Allows an interrupt to occur when the update cycle ends. 3 Square Wave Enable (SQWE) -- R/W. This bit serves no function in the PCH. It is left in this register bank to provide compatibility with the Motorola 146818B. The PCH has no SQW pin. This bit is cleared by RSMRST#, but not on any other reset. 2 Data Mode (DM) -- R/W. This bit specifies either binary or BCD data representation. This bit is not affected by RSMRST# nor any other reset signal. 0 = BCD 1 = Binary 1 Hour Format (HOURFORM) -- R/W. This bit indicates the hour byte format. This bit is not affected by RSMRST# nor any other reset signal. 0 = Twelve-hour mode. In twelve-hour mode, the seventh bit represents AM as 0 and PM as one. 1 = Twenty-four hour mode. 0 Daylight Savings Legacy Software Support (DSLSWS) -- R/W. Daylight savings functionality is no longer supported. This bit is used to maintain legacy software support and has no associated functionality. If BUC.DSO bit is set, the DSLSWS bit continues to be R/W. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 439 LPC Interface Bridge Registers (D31:F0) 13.6.2.3 RTC_REGC--Register C (Flag Register) RTC Index: Default Value: Lockable: 0Ch Attribute: 00U00000 (U: Undefined) Size: No Power Well: RO 8-bit RTC Writes to Register C have no effect. Bit Description 7 Interrupt Request Flag (IRQF) -- RO. IRQF = (PF * PIE) + (AF * AIE) + (UF *UFE). This bit also causes the RTC Interrupt to be asserted. This bit is cleared upon RSMRST# or a read of Register C. 6 Periodic Interrupt Flag (PF) -- RO. This bit is cleared upon RSMRST# or a read of Register C. 0 = If no taps are specified using the RS bits in Register A, this flag will not be set. 1 = Periodic interrupt Flag will be 1 when the tap specified by the RS bits of register A is 1. 5 Alarm Flag (AF) -- RO. 0 = This bit is cleared upon RTCRST# or a read of Register C. 1 = Alarm Flag will be set after all Alarm values match the current time. 4 Update-Ended Flag (UF) -- RO. 0 = The bit is cleared upon RSMRST# or a read of Register C. 1 = Set immediately following an update cycle for each second. 3:0 13.6.2.4 Reserved. RTC_REGD--Register D (Flag Register) RTC Index: Default Value: Lockable: Bit 7 6 5:0 440 Will always report 0. 0Dh Attribute: 10UUUUUU (U: Undefined) Size: No Power Well: R/W 8-bit RTC Description Valid RAM and Time Bit (VRT) -- R/W. 0 = This bit should always be written as a 0 for write cycle, however it will return a 1 for read cycles. 1 = This bit is hardwired to 1 in the RTC power well. Reserved. This bit always returns a 0 and should be set to 0 for write cycles. Date Alarm -- R/W. These bits store the date of month alarm value. If set to 000000b, then a don't care state is assumed. The host must configure the date alarm for these bits to do anything, yet they can be written at any time. If the date alarm is not enabled, these bits will return 0s to mimic the functionality of the Motorola 146818B. These bits are not affected by any reset assertion. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.7 Processor Interface Registers Table 13-8 is the register address map for the processor interface registers. Table 13-8. Processor Interface PCI Register Address Map Offset 13.7.1 Mnemonic Register Name Default Type 61h NMI_SC NMI Status and Control 00h R/W, RO 70h NMI_EN NMI Enable 80h R/W (special) 92h PORT92 Fast A20 and Init 00h R/W F0h COPROC_ERR Coprocessor Error 00h WO CF9h RST_CNT Reset Control 00h R/W NMI_SC--NMI Status and Control Register I/O Address: Default Value: Lockable: 61h 00h No Bit Attribute: Size: Power Well: R/W, RO 8-bit Core Description 7 SERR# NMI Source Status (SERR#_NMI_STS) -- RO. 1 = Bit is set if a PCI agent detected a system error and pulses the PCI SERR# line and if bit 2 (PCI_SERR_EN) is cleared. This interrupt source is enabled by setting bit 2 to 0. To reset the interrupt, set bit 2 to 1 and then set it to 0. When writing to port 61h, this bit must be 0. Note: This bit is set by any of the PCH internal sources of SERR; this includes SERR assertions forwarded from the secondary PCI bus, errors on a PCI Express* port, or other internal functions that generate SERR#. 6 IOCHK# NMI Source Status (IOCHK_NMI_STS) -- RO. 1 = Bit is set if an LPC agent (using SERIRQ) asserted IOCHK# and if bit 3 (IOCHK_NMI_EN) is cleared. This interrupt source is enabled by setting bit 3 to 0. To reset the interrupt, set bit 3 to 1 and then set it to 0. When writing to port 61h, this bit must be a 0. 5 Timer Counter 2 OUT Status (TMR2_OUT_STS) -- RO. This bit reflects the current state of the 8254 counter 2 output. Counter 2 must be programmed following any PCI reset for this bit to have a determinate value. When writing to port 61h, this bit must be a 0. 4 Refresh Cycle Toggle (REF_TOGGLE) -- RO. This signal toggles from either 0 to 1 or 1 to 0 at a rate that is equivalent to when refresh cycles would occur. When writing to port 61h, this bit must be a 0. 3 IOCHK# NMI Enable (IOCHK_NMI_EN) -- R/W. 0 = Enabled. 1 = Disabled and cleared. 2 PCI SERR# Enable (PCI_SERR_EN) -- R/W. 0 = SERR# NMIs are enabled. 1 = SERR# NMIs are disabled and cleared. 1 Speaker Data Enable (SPKR_DAT_EN) -- R/W. 0 = SPKR output is a 0. 1 = SPKR output is equivalent to the Counter 2 OUT signal value. 0 Timer Counter 2 Enable (TIM_CNT2_EN) -- R/W. 0 = Disable 1 = Enable Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 441 LPC Interface Bridge Registers (D31:F0) 13.7.2 NMI_EN--NMI Enable (and Real Time Clock Index) Register I/O Address: Default Value: Lockable: Note: 70h 80h No Attribute: Size: Power Well: The RTC Index field is write-only for normal operation. This field can only be read in AltAccess Mode. Note, however, that this register is aliased to Port 74h (documented in), and all bits are readable at that address. Bits 7 6:0 13.7.3 Description NMI Enable (NMI_EN) -- R/W (special). 0 = Enable NMI sources. 1 = Disable All NMI sources. Real Time Clock Index Address (RTC_INDX) -- R/W (special). This data goes to the RTC to select which register or CMOS RAM address is being accessed. PORT92-- Init Register I/O Address: Default Value: Lockable: 92h 00h No Bit 7:2 1 0 13.7.4 Attribute: Size: Power Well: R/W 8-bit Core Description Reserved Alternate A20 Gate (ALT_A20_GATE) -- R/W. Functionality reserved. A20M# functionality is not supported. INIT_NOW -- R/W. When this bit transitions from a 0 to a 1, the PCH will force INIT# active for 16 PCI clocks. COPROC_ERR--Coprocessor Error Register I/O Address: Default Value: Lockable: 442 R/W (special) 8-bit Core F0h 00h No Attribute: Size: Power Well: WO 8-bits Core Bits Description 7:0 Coprocessor Error (COPROC_ERR) -- WO. Any value written to this register will cause IGNNE# to go active, if FERR# had generated an internal IRQ13. For FERR# to generate an internal IRQ13, the CEN bit must be 1. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.7.5 RST_CNT--Reset Control Register I/O Address: Default Value: Lockable: CF9h 00h No Attribute: Size: Power Well: Bit 7:4 3 Description Reserved Full Reset (FULL_RST) -- R/W. This bit is used to determine the states of SLP_S3#, SLP_S4#, and SLP_S5# after a CF9 hard reset (SYS_RST =1 and RST_CPU is set to 1), after PCH_PWROK going low (with RSMRST# high), or after two TCO timeouts. 0 = PCH will keep SLP_S3#, SLP_S4# and SLP_S5# high. 1 = PCH will drive SLP_S3#, SLP_S4# and SLP_S5# low for 3 - 5 seconds. Note: 13.8 R/W 8-bit Core When this bit is set, it also causes the full power cycle (SLP_S3/4/5# assertion) in response to SYS_RESET#, PCH_PWROK#, and Watchdog timer reset sources. 2 Reset Processor(RST_CPU) -- R/W. When this bit transitions from a 0 to a 1, it initiates a hard or soft reset, as determined by the SYS_RST bit (bit 1 of this register). 1 System Reset (SYS_RST) -- R/W. This bit is used to determine a hard or soft reset to the processor. 0 = When RST_CPU bit goes from 0 to 1, the PCH performs a soft reset by activating INIT# for 16 PCI clocks. 1 = When RST_CPU bit goes from 0 to 1, the PCH performs a hard reset by activating PLTRST# 0active for a minimum of about 1 milliseconds. In this case, SLP_S3#, SLP_S4# and SLP_S5# state (assertion or deassertion) depends on FULL_RST bit setting. The PCH main power well is reset when this bit is 1. It also resets the resume well bits (except for those noted throughout the datasheet). 0 Reserved Power Management Registers The power management registers are distributed within the PCI Device 31: Function 0 space, as well as a separate I/O range. Each register is described below. Unless otherwise indicated, bits are in the main (core) power well. Bits not explicitly defined in each register are assumed to be reserved. When writing to a reserved bit, the value should always be 0. Software should not attempt to use the value read from a reserved bit, as it may not be consistently 1 or 0. 13.8.1 Power Management PCI Configuration Registers (PM--D31:F0) Table 13-9 shows a small part of the configuration space for PCI Device 31: Function 0. It includes only those registers dedicated for power management. Some of the registers are only used for Legacy Power management schemes. Table 13-9. Power Management PCI Register Address Map (PM--D31:F0) (Sheet 1 of 2) Offset Mnemonic A0h-A1h GEN_PMCON_1 A2h Register Name Default Type General Power Management Configuration 1 0000h R/W, R/WO, RO GEN_PMCON_2 General Power Management Configuration 2 00h RO, R/WC, R/W A4h-A5h GEN_PMCON_3 General Power Management Configuration 3 4206h R/W, R/WL A6h GEN_PMCON_LOCK General Power Management Configuration Lock 00h RO, R/WL, R/WS A9h CIR4 Chipset Initialization Register 4 03h R/W Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 443 LPC Interface Bridge Registers (D31:F0) Table 13-9. Power Management PCI Register Address Map (PM--D31:F0) (Sheet 2 of 2) 13.8.1.1 Offset Mnemonic AAh BM_BREAK_EN_2 ABh BM_BREAK_EN B8-BBh GPI_ROUT Default Type BM_BREAK_EN Register #2 00h R/W, RO BM_BREAK_EN 00h R/W, RO 00000000h R/W GPI Route Control GEN_PMCON_1--General PM Configuration 1 Register (PM--D31:F0) Offset Address: A0h Default Value: 0000h Lockable: No Bit 15:12 Attribute: Size: Usage: Power Well: R/W, RO, R/WO 16-bit ACPI, Legacy Core Description Reserved 11 GEN_PMCON_1 Field 1 -- R/W. BIOS must program this field to 1b. 10 BIOS_PCI_EXP_EN -- R/W. This bit acts as a global enable for the SCI associated with the PCI Express* ports. 0 = The various PCI Express* ports and processor cannot cause the PCI_EXP_STS bit to go active. 1 = The various PCI Express* ports and processor can cause the PCI_EXP_STS bit to go active. 9 8:5 4 444 Register Name PWRBTN_LVL -- RO. This bit indicates the current state of the PWRBTN# signal. 0 = Low. 1 = High. Reserved SMI_LOCK -- R/WS. When this bit is set, writes to the GLB_SMI_EN bit (PMBASE + 30h, bit 0) will have no effect. Once the SMI_LOCK bit is set, writes of 0 to SMI_LOCK bit will have no effect (that is, once set, this bit can only be cleared by PLTRST#). 3:2 Reserved 1:0 Periodic SMI# Rate Select (PER_SMI_SEL) -- R/W. Set by software to control the rate at which periodic SMI# is generated. 00 = 64 seconds 01 = 32 seconds 10 = 16 seconds 11 = 8 seconds Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.8.1.2 GEN_PMCON_2--General PM Configuration 2 Register (PM--D31:F0) Offset Address: A2h Default Value: 00h Lockable: No Attribute: Size: Usage: Power Well: RO, R/WC, R/W 8-bit ACPI, Legacy Resume Bit Description 7 DRAM Initialization Bit -- R/W. This bit does not affect hardware functionality in any way. BIOS is expected to set this bit prior to starting the DRAM initialization sequence and to clear this bit after completing the DRAM initialization sequence. BIOS can detect that a DRAM initialization sequence was interrupted by a reset by reading this bit during the boot sequence. * If the bit is 1, then the DRAM initialization was interrupted. * This bit is reset by the assertion of the RSMRST# pin. 6 Reserved 5 Memory Placed in Self-Refresh (MEM_SR) -- RO. * If the bit is 1, DRAM should have remained powered and held in Self-Refresh through the last power state transition (that is, the last time the system left S0). * This bit is reset by the assertion of the RSMRST# pin. 4 System Reset Status (SRS) -- R/WC. Software clears this bit by writing a 1 to it. 0 = SYS_RESET# button Not pressed. 1 = PCH sets this bit when the SYS_RESET# button is pressed. BIOS is expected to read this bit and clear it, if it is set. Notes: 1. This bit is also reset by RSMRST# and CF9h resets. 2. The SYS_RESET# is implemented in the Main power well. This pin must be properly isolated and masked to prevent incorrectly setting this Suspend well status bit. Processor Thermal Trip Status (CTS) -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set when PLTRST# is inactive and THRMTRIP# goes active while the system is in an S0 or S1 state. 3 2 Notes: 1. This bit is also reset by RSMRST#, and CF9h resets. It is not reset by the shutdown and reboot associated with the Processor THRMTRIP# event. 2. The CF9h reset in the description refers to CF9h type core well reset which includes SYS_RESET#, PCH_PWROK/SYS_PWROK low, SMBus hard reset, TCO Timeout. This type of reset will clear CTS bit. Minimum SLP_S4# Assertion Width Violation Status -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Hardware sets this bit when the SLP_S4# assertion width is less than the time programmed in the SLP_S4# Minimum Assertion Width field (D31:F0:Offset A4h:bits 5:4). The PCH begins the timer when SLP_S4# is asserted during S4/S5 entry or when the RSMRST# input is deasserted during SUS well power-up. Note that this bit is functional regardless of the values in the SLP_S4# Assertion Stretch Enable (D31:F0:Offset A4h:bit 3) and in the Disable SLP Stretching after SUS Well Power Up (D31:F0:Offset A4h:bit 12). Note: This bit is reset by the assertion of the RSMRST# pin, but can be set in some cases before the default value is readable. 1 SYS_PWROK Failure (SYSPWR_FLR) -- R/WC. 0 = This bit will be cleared only be software writing a 1 back to the bit or by SUS well power loss. Note: This bit will be set any time SYS_PWROK drops unexpectedly when the system was in S0 or S1 state. 0 PCH_PWROK Failure (PWROK_FLR) -- R/WC. 0 = This bit will be cleared only be software writing a 1 back to the bit or by SUS well power loss. 1 = This bit will be set any time PCH_PWROK goes low when the system was in S0 or S1 state. Note: See Chapter 5.14.9.3 for more details about the PCH_PWROK pin functionality. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 445 LPC Interface Bridge Registers (D31:F0) 13.8.1.3 GEN_PMCON_3--General PM Configuration 3 Register (PM--D31:F0) Offset Address: A4h Default Value: 4206h Lockable: No Attribute: Size: Usage: Power Well: Bit R/W, R/WC 16-bit ACPI, Legacy RTC, SUS Description PME B0 S5 Disable (PME_B0_S5_DIS)-- R/W. When set to '1', this bit blocks wake events from PME_B0_STS in S5, regardless of the state of PME_B0_EN. When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = '1'. Wakes from power states other than S5 are not affected by this policy bit. The net effect of setting PME_B0_S5_DIS = '1' is described by the truth table below: Y = Wake; N = Don't wake; B0 = PME_B0_EN; OV = WOL Enable Override B0/OV 15 S1/S3/S4 S5 00 N N 01 N Y (LAN only) 11 Y (all PME B0 sources) Y (LAN only) 01 Y (all PME B0 sources) N This bit is cleared by the RTCRST# pin. 14 SUS Well Power Failure (SUS_PWR_FLR) -- R/WC. 0 = Software writes a 1 to this bit to clear it. 1 = This bit is set to `1' whenever SUS well power is lost, as indicated by RSMRST# assertion. Note: This bit is in the SUS well, and defaults to `1' based on RSMRST# assertion (not cleared by any type of reset). 13 WOL Enable Override(WOL_EN_OVRD) -- R/W. 0 = WOL policies are determined by PMEB0 enable bit and appropriate LAN status bits 1 = Enable appropriately configured integrated LAN to wake the system in S5 only regardless of the value in the PME_B0_EN bit in the GPE0_EN register. Note: This bit is cleared by the RTCRST# pin. Disable SLP Stretching After SUS Well Power Up (DIS_SLP_STRCH_SUS_UP): R/W 0 = Enables stretching on SLP signals after SUS power failure as enabled and configured in other fields. 1 = Disables stretching on SLP signals when powering up after a SUS well power loss. regardless of the state of the SLP_S4# Assertion Stretch Enable (bit 3). This bit is cleared by the RTCRST# pin. 12 11:10 Notes: 1. This field is RO when the SLP Stretching Policy Lock-Down bit is set. 2. If this bit is cleared, SLP stretch timers start on SUS well power up (the PCH has no ability to count stretch time while the SUS well is powered down). 3. This policy bit has a different effect on SLP_SUS# stretching than on the other SLP_* pins since SLP_SUS# is the control signal for one of the scenarios where SUS well power is lost (Deep S4/S5). The effect of setting this bit to '1' on: -- SLP_S3# and SLP_S4# stretching: disabled after any SUS power loss. -- SLP_SUS# stretching: disabled after G3, but no impact on Deep S4/S5. SLP_S3# Minimum Assertion Width: R/W This 2-bit value indicates the minimum assertion width of the SLP_S3# signal to ensure that the Main power supplies have been fully powercycled. Valid Settings are: 00 = 60 us 01 = 1 ms 10 = 50 ms 11 = 2 s This bit is cleared by the RSMRST# pin. Note: 446 This field is RO when the SLP Stretching Policy Lock-Down bit is set. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) Bit 9 Description General Reset Status (GEN_RST_STS) -- R/WC. This bit is set by hardware whenever PLTRST# asserts for any reason other than going into a software-entered sleep state (using PM1CNT.SLP_EN write) or a suspend well power failure (RSMRST# pin assertion). BIOS is expected to consult and then write a 1 to clear this bit during the boot flow before determining what action to take based on PM1_STS.WAK_STS = 1. If GEN_RST_STS = `1', the cold reset boot path should be followed rather than the resume path, regardless of the setting of WAK_STS. This bit is cleared by the RSMRST# pin. SLP_LAN# Default Value (SLP_LAN_DEFAULT) -- R/W. This bit specifies the value to drive on the SLP_LAN# pin when in Sx/Moff and Intel ME FW nor host BIOS has configured SLP_LAN# as an output. When this bit is set to 1 SLP_LAN# will default to be driven high, when set to 0 SLP_LAN# will default to be driven low. 8 This bit will always determine SLP_LAN# behavior when in S4/S5/Moff after SUS power loss, in S5/Moff after a host partition reset with power down and when in S5/Moff due to an unconditional power down. This bit is cleared by RTCRST#. 7:6 5:4 SWSMI_RATE_SEL -- R/W. This field indicates when the SWSMI timer will time out. Valid values are: 00 = 1.5 ms 0.6 ms 01 = 16 ms 4 ms 10 = 32 ms 4 ms 11 = 64 ms 4 ms These bits are not cleared by any type of reset except RTCRST#. SLP_S4# Minimum Assertion Width -- R/W. This field indicates the minimum assertion width of the SLP_S4# signal to ensure that the DRAM modules have been safely power-cycled. Valid values are: 11 = 1 second 10 = 2 seconds 01 = 3 seconds 00 = 4 seconds This value is used in two ways: 1. If the SLP_S4# assertion width is ever shorter than this time, a status bit is set for BIOS to read when S0 is entered. 2. If enabled by bit 3 in this register, the hardware will prevent the SLP_S4# signal from deasserting within this minimum time period after asserting. RTCRST# forces this field to the conservative default state (00b). Notes: 1. This field is RO when the SLP Stretching Policy Lock-Down bit is set. 2. Note that the logic that measures this time is in the suspend power well. Therefore, when leaving a G3 or Deep S4/S5 state, the minimum time is measured from the deassertion of the internal suspend well reset (unless the "Disable SLP Stretching After SUS Well Power Up" bit is set). 3 SLP_S4# Assertion Stretch Enable -- R/W. 0 = The SLP_S4# minimum assertion time is defined in Power Sequencing and Reset Signal Timings table. 1 = The SLP_S4# signal minimally assert for the time specified in bits 5:4 of this register. This bit is cleared by RTCRST#. Note: This bit is RO when the SLP Stretching Policy Lock-Down bit is set. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 447 LPC Interface Bridge Registers (D31:F0) Bit Description 2 RTC Power Status (RTC_PWR_STS) -- R/W. This bit is set when RTCRST# indicates a weak or missing battery. The bit is not cleared by any type of reset. The bit will remain set until the software clears it by writing a 0 back to this bit position. Power Failure (PWR_FLR) -- R/WC. This bit is in the DeepS4/S5 well and defaults to 1 based on DPWROK deassertion (not cleared by any type of reset). 0 = Indicates that the trickle current has not failed since the last time the bit was cleared. Software clears this bit by writing a 1 to it. 1 = Indicates that the trickle current (from the main battery or trickle supply) was removed or failed. 1 Note: AFTERG3_EN -- R/W. This bit determines what state to go to when power is re-applied after a power failure (G3 state). This bit is in the RTC well and is only cleared by RTCRST# assertion. 0 = System will return to S0 state (boot) after power is re-applied. 1 = System will return to the S5 state (except if it was in S4, in which case it will return to S4). In the S5 state, the only enabled wake event is the Power Button or any enabled wake event that was preserved through the power failure. 0 Note: 13.8.1.4 Clearing CMOS in a PCH-based platform can be done by using a jumper on RTCRST# or GPI. Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. RSMRST# is sampled using the RTC clock. Therefore, low times that are less than one RTC clock period may not be detected by the PCH. GEN_PMCON_LOCK- General Power Management Configuration Lock Register Offset Address: Default Value: Lockable: Power Well: A6h 00h No Core Bit 7:3 13.8.1.5 RO, R/WLO 8-bit ACPI Description Reserved 2 SLP Stretching Policy Lock-Down(SLP_STR_POL_LOCK) -- R/WLO. R/WLO. When set to 1, this bit locks down the Disable SLP Stretching After SUS Well Power Up, SLP_S3# Minimum Assertion Width, SLP_S4# Minimum Assertion Width, SLP_S4# Assertion Stretch Enable bits in the GEN_PMCON_3 register, making them read-only. This bit becomes locked when a value of 1b is written to it. Writes of 0 to this bit are always ignored. This bit is cleared by platform reset. 1 ACPI_BASE_LOCK -- R/WLO. When set to 1, this bit locks down the ACPI Base Address Register (ABASE) at offset 40h. The Base Address Field becomes read-only. This bit becomes locked when a value of 1b is written to it. Writes of 0 to this bit are always ignored. Once locked by writing 1, the only way to clear this bit is to perform a platform reset. 0 Reserved Chipset Initialization Register 4 (PM--D31:F0) Offset Address: Default Value: Lockable: Power Well: Bit 7:0 448 Attribute: Size: Usage: A9h 03h No Core Attribute: Size: Usage: R/W 8-bit ACPI, Legacy Description CIR4 Field 1 -- R/W. BIOS must program this field to 47h. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.8.1.6 BM_BREAK_EN Register #2(PM--D31:F0) Offset Address: Default Value: Lockable: Power Well: AAh 00h No Core Bit 7:1 0 13.8.1.7 R/W, RO 8-bit ACPI, Legacy Description Reserved SATA3 Break Enable (SATA3_BREAK_EN) -- R/W 0 = SATA3 traffic will not cause BM_STS to be set. 1 = SATA3 traffic will cause BM_STS to be set. BM_BREAK_EN Register (PM--D31:F0) Offset Address: Default Value: Lockable: Power Well: ABh 00h No Core Bit Attribute: Size: Usage: Storage Breka Enable (STORAGE_BREAK_EN) -- R/W. 0 = Serial ATA traffic will not cause BM_STS to be set.. 1 = Serial ATA traffic will cause BM_STS to be set. 6 PCIE_BREAK_EN -- R/W. 0 = PCI Express* traffic will not cause BM_STS to be set.. 1 = PCI Express* traffic will cause BM_STS to be set. 5 PCI_BREAK_EN -- R/W. 0 = PCI traffic will not cause BM_STS to be set.. 1 = PCI traffic will cause BM_STS to be set. 2 R/W 8-bit ACPI, Legacy Description 7 4:3 13.8.1.8 Attribute: Size: Usage: Reserved EHCI_BREAK_EN -- R/W. 0 = EHCI traffic will not cause BM_STS to be set.. 1 = EHCI traffic will cause BM_STS to be set. 1 Reserved 0 HDA_BREAK_EN -- R/W. 0 = Intel(R) High Definition Audio traffic will not cause BM_STS to be set. 1 = Intel(R) High Definition Audio traffic will cause BM_STS to be set. GPIO_ROUT--GPIO Routing Control Register (PM--D31:F0) Offset Address: B8h - BBh Default Value: 00000000h Lockable: No Bit 31:30 Attribute: Size: Power Well: R/W 32-bit Resume Description GPIO15 Route -- R/W. See bits 1:0 for description. Same pattern for GPIO14 through GPIO3 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 449 LPC Interface Bridge Registers (D31:F0) Bit Description 5:4 GPIO2 Route -- R/W. See bits 1:0 for description. 3:2 GPIO1 Route -- R/W. See bits 1:0 for description. 1:0 GPIO0 Route -- R/W. GPIO can be routed to cause an NMI, SMI# or SCI when the GPIO[n]_STS bit is set. If the GPIO0 is not set to an input, this field has no effect. If the system is in an S1-S5 state and if the GPE0_EN bit is also set, then the GPIO can cause a Wake event, even if the GPIO is NOT routed to cause an NMI, SMI# or SCI. 00 = No effect. 01 = SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) 10 = SCI (if corresponding GPE0_EN bit is also set) 11 = NMI (If corresponding GPI_NMI_EN is also set) Note: GPIOs that are not implemented will not have the corresponding bits implemented in this register. 13.8.2 APM I/O Decode Table 13-10 shows the I/O registers associated with APM support. This register space is enabled in the PCI Device 31: Function 0 space (APMDEC_EN), and cannot be moved (fixed I/O location). Table 13-10. APM Register Map 13.8.2.1 Address Mnemonic B2h APM_CNT Advanced Power Management Control Port 00h R/W B3h APM_STS Advanced Power Management Status Port 00h R/W B2h 00h No Core Bit 7:0 Type Attribute: Size: Usage: R/W 8-bit Legacy Only Description Used to pass an APM command between the OS and the SMI handler. Writes to this port not only store data in the APMC register, but also generates an SMI# when the APMC_EN bit is set. APM_STS--Advanced Power Management Status Port Register I/O Address: Default Value: Lockable: Power Well: 450 Default APM_CNT--Advanced Power Management Control Port Register I/O Address: Default Value: Lockable: Power Well: 13.8.2.2 Register Name B3h 00h No Core Attribute: Size: Usage: R/W 8-bit Legacy Only Bit Description 7:0 Used to pass data between the OS and the SMI handler. Basically, this is a scratchpad register and is not affected by any other register or function (other than a PCI reset). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.8.3 Power Management I/O Registers Table 13-11 shows the registers associated with ACPI and Legacy power management support. These registers locations are all offsets from the ACPI base address defined in the PCI Device 31: Function 0 space (PMBASE), and can be moved to any 128-byte aligned I/O location. In order to access these registers, the ACPI Enable bit(ACPI_EN) must be set. The registers are defined to be compliant with the ACPI 3.0b specification, and generally use the same bit names. Note: All reserved bits and registers will always return 0 when read, and will have no effect when written. Table 13-11. ACPI and Legacy I/O Register Map PMBASE + Offset Mnemonic 00h-01h PM1_STS Register Name PM1 Status Default Type 0000h R/WC 02h-03h PM1_EN PM1 Enable 0000h R/W 04h-07h PM1_CNT PM1 Control 00000000h R/W, WO 08h-0Bh PM1_TMR PM1 Timer xx000000h RO 20-27h GPE0_STS General Purpose Event 0 Status 00000000 00000000h R/WC 28-2Fh GPE0_EN General Purpose Event 0a Enables 00000000 00000000h R/W 30h-33h SMI_EN SMI# Control and Enable 00000002h R/W, WO, R/WO 34h-37h SMI_STS SMI Status 00000000h R/WC, RO 38h-39h ALT_GP_SMI_EN Alternate GPI SMI Enable 0000h R/W 3Ah-3Bh ALT_GP_SMI_STS Alternate GPI SMI Status 0000h R/WC 3Ch-3Dh UPRWC USB Per-Port Registers Write Control 0000h R/WC, R/W, R/WO 42h GPE_CNTL 00h R/W 44h-45h DEVTRAP_STS 0000h R/WC 50h PM2_CNT 00h R/W 60h-7Fh -- -- -- General Purpose Event Control Device Trap Status Status Power Management 2 Control Reserved for TCO Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 451 LPC Interface Bridge Registers (D31:F0) 13.8.3.1 PM1_STS--Power Management 1 Status Register I/O Address: Default Value: Lockable: Power Well: PMBASE + 00h Attribute: 0000h No Bits 0-7: Core, Bits 12-15: Resume Bit 11: RTC, Bits 8 and 10: DSW R/WC Size: Usage: 16-bit ACPI or Legacy If bit 10 or 8 in this register is set, and the corresponding _EN bit is set in the PM1_EN register, then the PCH will generate a Wake Event. Once back in an S0 state (or if already in an S0 state when the event occurs), the PCH will also generate an SCI if the SCI_EN bit is set, or an SMI# if the SCI_EN bit is not set. Note: Bit 5 does not cause an SMI# or a wake event. Bit 0 does not cause a wake event but can cause an SMI# or SCI. Bit Description 15 Wake Status (WAK_STS) -- R/WC. This bit is not affected by hard resets caused by a CF9 write, but is reset by RSMRST#. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the system is in one of the sleep states (using the SLP_EN bit) and an enabled wake event occurs. Upon setting this bit, the PCH will transition the system to the ON state. If the AFTERG3_EN bit is not set and a power failure (such as removed batteries) occurs without the SLP_EN bit set, the system will return to an S0 state when power returns, and the WAK_STS bit will not be set. If the AFTERG3_EN bit is set and a power failure occurs without the SLP_EN bit having been set, the system will go into an S5 state when power returns, and a subsequent wake event will cause the WAK_STS bit to be set. Note that any subsequent wake event would have to be caused by either a Power Button press, or an enabled wake event that was preserved through the power failure (enable bit in the RTC well). 14 PCI Express* Wake Status (PCIEXPWAK_STS) -- R/WC. 0 = Software clears this bit by writing a 1 to it. If the WAKE# pin is still active during the write or the PME message received indication has not been cleared in the root port, then the bit will remain active (that is, all inputs to this bit are level-sensitive). 1 = This bit is set by hardware to indicate that the system woke due to a PCI Express* wakeup event. This wakeup event can be caused by the PCI Express* WAKE# pin being active or receipt of a PCI Express* PME message at a root port. This bit is set only when one of these events causes the system to transition from a non-S0 system power state to the S0 system power state. This bit is set independent of the state of the PCIEXP_WAKE_DIS bit. Note: This bit does not itself cause a wake event or prevent entry to a sleeping state. Thus, if the bit is 1 and the system is put into a sleeping state, the system will not automatically wake. 13:12 11 Power Button Override Status (PWRBTNOR_STS) -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set any time a Power Button Override occurs (that is, the power button is pressed for at least 4 consecutive seconds), due to the corresponding bit in the SMBus slave message, Intel ME Initiated Power Button Override, Intel ME Initiated Host Reset with Power down or due to an internal thermal sensor catastrophic condition. The power button override causes an unconditional transition to the S5 state. The BIOS or SCI handler clears this bit by writing a 1 to it. This bit is not affected by hard resets using CF9h writes, and is not reset by RSMRST#. Thus, this bit is preserved through power failures. Note that if this bit is still asserted when the global SCI_EN is set then an SCI will be generated. Note: Upon entry to S5 due to an event described above, if Deep S4/S5 is enabled and conditions are met per Section 5.14.6.6, the system will transition to Deep S4/S5. 10 RTC Status (RTC_STS) -- R/WC. This bit is not affected by hard resets caused by a CF9 write, but is reset by DPWROK. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the RTC generates an alarm (assertion of the IRQ8# signal). Additionally if the RTC_EN bit (PMBASE + 02h, bit 10) is set, the setting of the RTC_STS bit will generate a wake event. 9 452 Reserved Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) Bit Description Power Button Status (PWRBTN__STS) -- R/WC. This bit is not affected by hard resets caused by a CF9 write but is reset by DPWROK 0 = If the PWRBTN# signal is held low for more than 4 seconds, the hardware clears the PWRBTN_STS bit, sets the PWRBTNOR_STS bit, and the system transitions to the S5 state with only PWRBTN# enabled as a wake event. This bit can be cleared by software by writing a one to the bit position. 1 = This bit is set by hardware when the PWRBTN# signal is asserted Low, independent of any other enable bit. 8 In the S0 state, while PWRBTN_EN and PWRBTN_STS are both set, an SCI (or SMI# if SCI_EN is not set) will be generated. In any sleeping state S1-S5, while PWRBTN_EN (PMBASE + 02h, bit 8) and PWRBTN_STS are both set, a wake event is generated. Notes: 1. If the PWRBTN_STS bit is cleared by software while the PWRBTN# signal is sell asserted, this will not cause the PWRBN_STS bit to be set. The PWRBTN# signal must go inactive and active again to set the PWRBTN_STS bit. 2. Upon entry to S5 due to a power button override, if Deep S4/S5 is enabled and conditions are met per Section 5.14.6.6, the system will transition to Deep S4/S5. 7:6 Reserved 5 Global Status (GBL _STS) -- R/WC. 0 = The SCI handler should then clear this bit by writing a 1 to the bit location. 1 = Set when an SCI is generated due to BIOS wanting the attention of the SCI handler. BIOS has a corresponding bit, BIOS_RLS, which will cause an SCI and set this bit. 4 Bus Master Status (BM_STS) -- R/WC. This bit will not cause a wake event, SCI or SMI#. 0 = Software clears this bit by writing a 1 to it. 1 = Set by the PCH when a PCH-visible bus master requests access to memory or the BM_BUSY# signal is active. 3:1 0 Reserved Timer Overflow Status (TMROF_STS) -- R/WC. 0 = The SCI or SMI# handler clears this bit by writing a 1 to the bit location. 1 = This bit gets set any time bit 22 of the 24-bit timer goes high (bits are numbered from 0 to 23). This will occur every 2.3435 seconds. When the TMROF_EN bit (PMBASE + 02h, bit 0) is set, then the setting of the TMROF_STS bit will additionally generate an SCI or SMI# (depending on the SCI_EN). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 453 LPC Interface Bridge Registers (D31:F0) 13.8.3.2 PM1_EN--Power Management 1 Enable Register I/O Address: PMBASE + 02h Default Value: Lockable: Power Well: 0000h No Bits 0-7: Core, Bits 8-9, 11-15: Resume, Bit 10: RTC Bit Attribute: Size: Usage: RO; R/W 16-bit ACPI or Legacy Description 15 Reserved 14 PCI Express* Wake Disable(PCIEXPWAK_DIS) -- R/W. Modification of this bit has no impact on the value of the PCIEXP_WAKE_STS bit. 0 = Inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register enabled to wake the system. 1 = Inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register disabled from waking the system. 13:11 10 Reserved RTC Alarm Enable (RTC_EN) -- R/W. This bit is in the RTC well to allow an RTC event to wake after a power failure. In addition to being cleared by RTCRST# assertion, the PCH also clears this bit due to a Power Button Override event, Intel ME Initiated Power Button Override, Intel ME Initiated Host Reset with Power down, SMBus unconditional power down, Processor thermal trip event, or due to an internal thermal sensor catastrophic condition. 0 = No SCI (or SMI#) or wake event is generated then RTC_STS (PMBASE + 00h, bit 10) goes active. 1 = An SCI (or SMI#) or wake event will occur when this bit is set and the RTC_STS bit goes active. 9 Reserved. 8 Power Button Enable (PWRBTN_EN) -- R/W. This bit is used to enable the setting of the PWRBTN_STS bit to generate a power management event (SMI#, SCI). PWRBTN_EN has no effect on the PWRBTN_STS bit (PMBASE + 00h, bit 8) being set by the assertion of the power button. The Power Button is always enabled as a Wake event. 0 = Disable. 1 = Enable. 7:6 5 4:1 Reserved. Global Enable (GBL_EN) -- R/W. When both the GBL_EN and the GBL_STS bit (PMBASE + 00h, bit 5) are set, an SCI is raised. 0 = Disable. 1 = Enable SCI on GBL_STS going active. Reserved. Timer Overflow Interrupt Enable (TMROF_EN) -- R/W. Works in conjunction with the SCI_EN bit (PMBASE + 04h, bit 0) as described below: 0 454 TMROF_EN SCI_EN Effect when TMROF_STS is set 0 X No SMI# or SCI 1 0 SMI# 1 1 SCI Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.8.3.3 PM1_CNT--Power Management 1 Control I/O Address: PMBASE + 04h Default Value: Lockable: Power Well: 00000000h No Bits 0-7: Core, Bits 8-12: RTC, Bits 13-15: Resume Bit 31:14 13 Attribute: Size: Usage: R/W, WO 32-bit ACPI or Legacy Description Reserved. Sleep Enable (SLP_EN) -- WO. Setting this bit causes the system to sequence into the Sleep state defined by the SLP_TYP field. Sleep Type (SLP_TYP) -- R/W. This 3-bit field defines the type of Sleep the system should enter when the SLP_EN bit is set to 1. These bits are only reset by RTCRST#. Code 12:10 9:3 Master Interrupt 000b ON: Typically maps to S0 state. 001b Puts CPU in S1 state. 010b Reserved 011b Reserved 100b Reserved 101b Suspend-To-RAM. Assert SLP_S3#: Typically maps to S3 state. 110b Suspend-To-Disk. Assert SLP_S3#, and SLP_S4#: Typically maps to S4 state. 111b Soft Off. Assert SLP_S3#, SLP_S4#, and SLP_S5#: Typically maps to S5 state. Reserved. 2 Global Release (GBL_RLS) -- WO. 0 = This bit always reads as 0. 1 = ACPI software writes a 1 to this bit to raise an event to the BIOS. BIOS software has a corresponding enable and status bits to control its ability to receive ACPI events. 1 Bus Master Reload (BM_RLD) -- R/W. This bit is treated as a scratchpad bit. his bit is reset to 0 by PLTRST# 0 = Bus master requests will not cause a break from the C3 state. 1 = Enables Bus Master requests (internal or external) to cause a break from the C3 state. If software fails to set this bit before going to C3 state, the PCH will still return to a snoopable state from C3 or C4 states due to bus master activity. 0 SCI Enable (SCI_EN) -- R/W. Selects the SCI interrupt or the SMI# interrupt for various events including the bits in the PM1_STS register (bit 10, 8, 0), and bits in GPE0_STS. 0 = These events will generate an SMI#. 1 = These events will generate an SCI. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 455 LPC Interface Bridge Registers (D31:F0) 13.8.3.4 PM1_TMR--Power Management 1 Timer Register I/O Address: PMBASE + 08h Default Value: Lockable: Power Well: xx000000h No Core Bit 31:24 23:0 13.8.3.5 Attribute: Size: Usage: RO 32-bit ACPI Description Reserved Timer Value (TMR_VAL) -- RO. Returns the running count of the PM timer. This counter runs off a 3.579545 MHz clock (14.31818 MHz divided by 4). It is reset to 0 during a PCI reset, and then continues counting as long as the system is in the S0 state. After an S1 state, the counter will not be reset (it will continue counting from the last value in S0 state. Anytime bit 22 of the timer goes HIGH to LOW (bits referenced from 0 to 23), the TMROF_STS bit (PMBASE + 00h, bit 0) is set. The High-to-Low transition will occur every 2.3435 seconds. If the TMROF_EN bit (PMBASE + 02h, bit 0) is set, an SCI interrupt is also generated. GPE0_STS--General Purpose Event 0a Status Register I/O Address: PMBASE + 20h Default Value: Lockable: Power Well: 0000000000000000h Size: No Usage: Bits 0-34, 56-63: Resume, Bit 35: DSW Attribute: R/WC; RO 64-bit ACPI This register is symmetrical to the General Purpose Event 0a Enable Register. Unless indicated otherwise below, if the corresponding _EN bit is set, then when the _STS bit get set, the PCH will generate a Wake Event. Once back in an S0 state (or if already in an S0 state when the event occurs), the PCH will also generate an SCI if the SCI_EN bit is set, or an SMI# if the SCI_EN bit (PMBASE + 04h, bit 0) is not set. Bits 15:0 should not be reset by CF9 write. Bits 31:16 are reset by CF9h full resets. Bit 63:36 35 34:32 31:16 Description Reserved. GPIO27_STS-- R/WC. 0 = Disable. 1 = Set by hardware and can be reset by writing a one to this bit position or a resume well reset. This bit is set at the level specified in GP27IO_POL. Note that GPIO27 is always monitored as an input for the purpose of setting this bit, regardless of the actual GPIO configuration. Reserved. GPIOn_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = These bits are set any time the corresponding GPIO is set up as an input and the corresponding GPIO signal is high (or low if the corresponding GP_INV bit is set). If the corresponding enable bit is set in the GPE0_EN register, then when the GPIO[n]_STS bit is set: * If the system is in an S1-S5 state, the event will also wake the system. * If the system is in an S0 state (or upon waking back to an S0 state), a SCI will be caused depending on the GPIO_ROUT bits (D31:F0:B8h, bits 31:30) for the corresponding GPI. Note: 15:14 456 Mapping is as follows: bit 31 corresponds to GPIO[15]... and bit 16 corresponds to GPIO[0]. Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) Bit Description Power Management Event Bus 0 Status (PME_B0_STS) -- R/WC This bit will be set to 1 by the Intel PCH when any internal device with PCI Power Management capabilities on bus 0 asserts the equivalent of the PME# signal. Additionally, if the PME_B0_EN and SCI_EN bits are set, and the system is in an S0 state, then the setting of the PME_B0_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the PME_B0_EN bit is set, and the system is in an S1-S4 state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the PME_B0_STS bit will generate a wake event, If the system is in an S5 state due to power button override, then the PME_B0_STS bit will not cause a wake event or SCI. 13 The The * * * * * default for this bit is 0. This bit is cleared by a software write of '1'. following are internal devices which can set this bit: Intel HD Audio Intel ME "maskable" wake events Integrated LAN SATA EHCI 12 Reserved 11 PME_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the PME# signal goes active. Additionally, if the PME_EN and SCI_EN bits are set, and the system is in an S0 state, then the setting of the PME_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the PME_EN bit is set, and the system is in an S1-S4 state (or S5 state due to setting SLP_TYP and SLP_EN), then the setting of the PME_STS bit will generate a wake event. If the system is in an S5 state due to power button override or a power failure, then PME_STS will not cause a wake event or SCI. 10 Reserved. PCI_EXP_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware to indicate that: * The PME event message was received on one or more of the PCI Express* ports * An Assert PMEGPE message received from the Processor using DMI 9 Notes: 1. The PCI WAKE# pin has no impact on this bit. 2. If the PCI_EXP_STS bit went active due to an Assert PMEGPE message, then a Deassert PMEGPE message must be received prior to the software write in order for the bit to be cleared. 3. If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the level-triggered SCI will remain active. 4. A race condition exists where the PCI Express* device sends another PME message because the PCI Express* device was not serviced within the time when it must resend the message. This may result in a spurious interrupt, and this is comprehended and approved by the PCI Express* specification. The window for this race condition is approximately 95-105 milliseconds. 8 RI_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the RI# input signal goes active. 7 SMBus Wake Status (SMB_WAK_STS) -- R/WC. The SMBus controller can independently cause an SMI#, so this bit does not need to do so (unlike the other bits in this register). Software clears this bit by writing a 1 to it. 0 = Wake event Not caused by the PCH's SMBus logic. 1 = Set by hardware to indicate that the wake event was caused by the PCH's SMBus logic.This bit will be set by the WAKE/SMI# command type, even if the system is already awake. The SMI handler should then clear this bit. Notes: 1. The SMBus controller will independently cause an SMI# so this bit does not need to do so (unlike the other bits in this register). 2. This bit is set by the SMBus slave command 01h (Wake/SMI#) even when the system is in the S0 state. Therefore, to avoid an instant wake on subsequent transitions to sleep states, software must clear this bit after each reception of the Wake/SMI# command or just prior to entering the sleep state. 3. The SMBALERT_STS bit (D31:F3:I/O Offset 00h:Bit 5) should be cleared by software before the SMB_WAK_STS bit is cleared. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 457 LPC Interface Bridge Registers (D31:F0) Bit Description Power Management Event Bus 0 Status (PME_B0_STS) -- R/WC This bit will be set to 1 by the Intel PCH when any internal device with PCI Power Management capabilities on bus 0 asserts the equivalent of the PME# signal. Additionally, if the PME_B0_EN and SCI_EN bits are set, and the system is in an S0 state, then the setting of the PME_B0_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the PME_B0_EN bit is set, and the system is in an S1-S4 state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the PME_B0_STS bit will generate a wake event, If the system is in an S5 state due to power button override, then the PME_B0_STS bit will not cause a wake event or SCI. 13 The The * * * * * default for this bit is 0. This bit is cleared by a software write of '1'. following are internal devices which can set this bit: Intel HD Audio Intel ME "maskable" wake events Integrated LAN SATA EHCI 12 Reserved 11 PME_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the PME# signal goes active. Additionally, if the PME_EN and SCI_EN bits are set, and the system is in an S0 state, then the setting of the PME_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the PME_EN bit is set, and the system is in an S1-S4 state (or S5 state due to setting SLP_TYP and SLP_EN), then the setting of the PME_STS bit will generate a wake event. If the system is in an S5 state due to power button override or a power failure, then PME_STS will not cause a wake event or SCI. 10 Reserved. PCI_EXP_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware to indicate that: * The PME event message was received on one or more of the PCI Express* ports * An Assert PMEGPE message received from the Processor using DMI 9 458 Notes: 1. The PCI WAKE# pin has no impact on this bit. 2. If the PCI_EXP_STS bit went active due to an Assert PMEGPE message, then a Deassert PMEGPE message must be received prior to the software write in order for the bit to be cleared. 3. If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the level-triggered SCI will remain active. 4. A race condition exists where the PCI Express* device sends another PME message because the PCI Express* device was not serviced within the time when it must resend the message. This may result in a spurious interrupt, and this is comprehended and approved by the PCI Express* specification. The window for this race condition is approximately 95-105 milliseconds. 8 RI_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the RI# input signal goes active. 7 SMBus Wake Status (SMB_WAK_STS) -- R/WC. The SMBus controller can independently cause an SMI#, so this bit does not need to do so (unlike the other bits in this register). Software clears this bit by writing a 1 to it. 0 = Wake event Not caused by the PCH's SMBus logic. 1 = Set by hardware to indicate that the wake event was caused by the PCH's SMBus logic.This bit will be set by the WAKE/SMI# command type, even if the system is already awake. The SMI handler should then clear this bit. Notes: 1. The SMBus controller will independently cause an SMI# so this bit does not need to do so (unlike the other bits in this register). 2. This bit is set by the SMBus slave command 01h (Wake/SMI#) even when the system is in the S0 state. Therefore, to avoid an instant wake on subsequent transitions to sleep states, software must clear this bit after each reception of the Wake/SMI# command or just prior to entering the sleep state. 3. The SMBALERT_STS bit (D31:F3:I/O Offset 00h:Bit 5) should be cleared by software before the SMB_WAK_STS bit is cleared. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) Bit Description Power Management Event Bus 0 Status (PME_B0_STS) -- R/WC This bit will be set to 1 by the Intel PCH when any internal device with PCI Power Management capabilities on bus 0 asserts the equivalent of the PME# signal. Additionally, if the PME_B0_EN and SCI_EN bits are set, and the system is in an S0 state, then the setting of the PME_B0_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the PME_B0_EN bit is set, and the system is in an S1-S4 state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the PME_B0_STS bit will generate a wake event, If the system is in an S5 state due to power button override, then the PME_B0_STS bit will not cause a wake event or SCI. 13 The The * * * * * default for this bit is 0. This bit is cleared by a software write of '1'. following are internal devices which can set this bit: Intel HD Audio Intel ME "maskable" wake events Integrated LAN SATA EHCI 12 Reserved 11 PME_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the PME# signal goes active. Additionally, if the PME_EN and SCI_EN bits are set, and the system is in an S0 state, then the setting of the PME_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the PME_EN bit is set, and the system is in an S1-S4 state (or S5 state due to setting SLP_TYP and SLP_EN), then the setting of the PME_STS bit will generate a wake event. If the system is in an S5 state due to power button override or a power failure, then PME_STS will not cause a wake event or SCI. 10 Reserved. PCI_EXP_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware to indicate that: * The PME event message was received on one or more of the PCI Express* ports * An Assert PMEGPE message received from the Processor using DMI 9 Notes: 1. The PCI WAKE# pin has no impact on this bit. 2. If the PCI_EXP_STS bit went active due to an Assert PMEGPE message, then a Deassert PMEGPE message must be received prior to the software write in order for the bit to be cleared. 3. If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the level-triggered SCI will remain active. 4. A race condition exists where the PCI Express* device sends another PME message because the PCI Express* device was not serviced within the time when it must resend the message. This may result in a spurious interrupt, and this is comprehended and approved by the PCI Express* specification. The window for this race condition is approximately 95-105 milliseconds. 8 RI_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the RI# input signal goes active. 7 SMBus Wake Status (SMB_WAK_STS) -- R/WC. The SMBus controller can independently cause an SMI#, so this bit does not need to do so (unlike the other bits in this register). Software clears this bit by writing a 1 to it. 0 = Wake event Not caused by the PCH's SMBus logic. 1 = Set by hardware to indicate that the wake event was caused by the PCH's SMBus logic.This bit will be set by the WAKE/SMI# command type, even if the system is already awake. The SMI handler should then clear this bit. Notes: 1. The SMBus controller will independently cause an SMI# so this bit does not need to do so (unlike the other bits in this register). 2. This bit is set by the SMBus slave command 01h (Wake/SMI#) even when the system is in the S0 state. Therefore, to avoid an instant wake on subsequent transitions to sleep states, software must clear this bit after each reception of the Wake/SMI# command or just prior to entering the sleep state. 3. The SMBALERT_STS bit (D31:F3:I/O Offset 00h:Bit 5) should be cleared by software before the SMB_WAK_STS bit is cleared. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 459 LPC Interface Bridge Registers (D31:F0) Bit Description Power Management Event Bus 0 Status (PME_B0_STS) -- R/WC This bit will be set to 1 by the Intel PCH when any internal device with PCI Power Management capabilities on bus 0 asserts the equivalent of the PME# signal. Additionally, if the PME_B0_EN and SCI_EN bits are set, and the system is in an S0 state, then the setting of the PME_B0_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the PME_B0_EN bit is set, and the system is in an S1-S4 state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the PME_B0_STS bit will generate a wake event, If the system is in an S5 state due to power button override, then the PME_B0_STS bit will not cause a wake event or SCI. 13 The The * * * * * default for this bit is 0. This bit is cleared by a software write of '1'. following are internal devices which can set this bit: Intel HD Audio Intel ME "maskable" wake events Integrated LAN SATA EHCI 12 Reserved 11 PME_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the PME# signal goes active. Additionally, if the PME_EN and SCI_EN bits are set, and the system is in an S0 state, then the setting of the PME_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the PME_EN bit is set, and the system is in an S1-S4 state (or S5 state due to setting SLP_TYP and SLP_EN), then the setting of the PME_STS bit will generate a wake event. If the system is in an S5 state due to power button override or a power failure, then PME_STS will not cause a wake event or SCI. 10 Reserved. PCI_EXP_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware to indicate that: * The PME event message was received on one or more of the PCI Express* ports * An Assert PMEGPE message received from the Processor using DMI 9 460 Notes: 1. The PCI WAKE# pin has no impact on this bit. 2. If the PCI_EXP_STS bit went active due to an Assert PMEGPE message, then a Deassert PMEGPE message must be received prior to the software write in order for the bit to be cleared. 3. If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the level-triggered SCI will remain active. 4. A race condition exists where the PCI Express* device sends another PME message because the PCI Express* device was not serviced within the time when it must resend the message. This may result in a spurious interrupt, and this is comprehended and approved by the PCI Express* specification. The window for this race condition is approximately 95-105 milliseconds. 8 RI_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the RI# input signal goes active. 7 SMBus Wake Status (SMB_WAK_STS) -- R/WC. The SMBus controller can independently cause an SMI#, so this bit does not need to do so (unlike the other bits in this register). Software clears this bit by writing a 1 to it. 0 = Wake event Not caused by the PCH's SMBus logic. 1 = Set by hardware to indicate that the wake event was caused by the PCH's SMBus logic.This bit will be set by the WAKE/SMI# command type, even if the system is already awake. The SMI handler should then clear this bit. Notes: 1. The SMBus controller will independently cause an SMI# so this bit does not need to do so (unlike the other bits in this register). 2. This bit is set by the SMBus slave command 01h (Wake/SMI#) even when the system is in the S0 state. Therefore, to avoid an instant wake on subsequent transitions to sleep states, software must clear this bit after each reception of the Wake/SMI# command or just prior to entering the sleep state. 3. The SMBALERT_STS bit (D31:F3:I/O Offset 00h:Bit 5) should be cleared by software before the SMB_WAK_STS bit is cleared. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) Bit 6 5:3 13.8.3.6 Description TCOSCI_STS -- R/WC. Software clears this bit by writing a 1 to it. 0 = TOC logic or thermal sensor logic did Not cause SCI. 1 = Set by hardware when the TCO logic or thermal sensor logic causes an SCI. Reserved. 2 SWGPE_STS -- R/WC. The SWGPE_CTRL bit (bit 1 of GPE_CTRL reg) acts as a level input to this bit. 1 HOT_PLUG_STS -- R/WC. 0 = This bit is cleared by writing a 1 to this bit position. 1 = When a PCI Express* Hot-Plug event occurs. This will cause an SCI if the HOT_PLUG_EN and SCI_EN bits are set. 0 Reserved. GPE0_EN--General Purpose Event 0 Enables Register I/O Address: Default Value: Lockable: Power Well: PMBASE + 28h Attribute: 0000000000000000h Size: No Usage: Bits 0-7, 9, 12, 14-34, 36-63: Resume, Bits 8, 10-11, 13, 35: RTC R/W 64-bit ACPI This register is symmetrical to the General Purpose Event 0Status Register. Bit 63:36 35 Description Reserved. GPIO27_EN -- R/W. 0 = Disable. 1 = Enable the setting of the GPIO27_STS bit to generate a wake event/SCI/SMI#. GPIO27 is a valid host wake event from Deep S4/S5. The wake enable configuration persists after a G3 state. Note: In the Deep S4/S5 state, GPIO27 has no GPIO functionality other than wake enable capability, which is enabled when this bit is set. 34:32 Reserved. 31:16 GPIn_EN -- R/W. These bits enable the corresponding GPI[n]_STS bits being set to cause a SCI, and/or wake event. These bits are cleared by RSMRST#. Note: Mapping is as follows: bit 31 corresponds to GPIO15... and bit 16 corresponds to GPIO0. 15:14 13 Reserved PME_B0_EN -- R/W. 0 = Disable 1 = Enables the setting of the PME_B0_STS bit to generate a wake event and/or an SCI or SMI#. PME_B0_STS can be a wake event from the S1-S4 states, or from S5 (if entered using SLP_TYP and SLP_EN) or power failure, but not Power Button Override. This bit defaults to 0. It is only cleared by Software or RTCRST#. It is not cleared by CF9h writes. 12 Reserved 11 Power Management Event Enable (PME_EN) -- R/W. 0 = Disable. 1 = Enables the setting of the PME_STS to generate a wake event and/or an SCI. PME# can be a wake event from the S1 - S4 state or from S5 (if entered using SLP_EN, but not power button override). In addition to being cleared by RTCRST# assertion, the PCH also clears this bit due to a Power Button Override event, Intel ME Initiated Power Button Override, Intel ME Initiated Host Reset with Power down, SMBus unconditional power down, Processor thermal trip event, or due to an internal thermal sensor catastrophic condition. 10 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 461 LPC Interface Bridge Registers (D31:F0) Bit 9 PCI Express* Enable (PCI_EXP_EN) -- R/W. 0 = Disable SCI generation upon PCI_EXP_STS bit being set. 1 = Enables PCH to cause an SCI when PCI_EXP_STS bit is set. This is used to allow the PCI Express* ports, including the link to the Processor, to cause an SCI due to wake/PME events. 8 RI_EN -- R/W. The value of this bit will be maintained through a G3 state and is not affected by a hard reset caused by a CF9h write. 0 = Disable. 1 = Enables the setting of the RI_STS to generate a wake event. In addition to being cleared by RTCRST# assertion, the PCH also clears this bit due to a Power Button Override event, Intel ME Initiated Power Button Override, Intel ME Initiated Host Reset with Power down, SMBus unconditional power down, Processor thermal trip event, or due to an internal thermal sensor catastrophic condition. 7 Reserved 6 TCOSCI_EN -- R/W. 0 = Disable. 1 = Enables the setting of the TCOSCI_STS to generate an SCI. In addition to being cleared by RTCRST# assertion, the PCH also clears this bit due to a Power Button Override event, Intel ME Initiated Power Button Override, Intel ME Initiated Host Reset with Power down, SMBus unconditional power down, Processor thermal trip event, or due to an internal thermal sensor catastrophic condition. 5:3 13.8.3.7 Description Reserved 2 Software GPE Enable (SWGPE_EN) -- R/W. This bit allows software to control the assertion of SWGPE_STS bit. This bit This bit, when set to 1, enables the SW GPE function. If SWGPE_CTRL is written to a 1, hardware will set SWGPE_STS (acts as a level input) If SWGPE_STS, SWGPE_EN, and SCI_EN are all 1's, an SCI will be generated If SWGPE_STS = 1, SWGPE_EN = 1, SCI_EN = 0, and GBL_SMI_EN = 1 then an SMI# will be generated 1 HOT_PLUG_EN -- R/W. 0 = Disables SCI generation upon the HOT_PLUG_STS bit being set. 1 = Enables the PCH to cause an SCI when the HOT_PLUG_STS bit is set. This is used to allow the PCI Express* ports to cause an SCI due to hot-plug events. 0 Reserved. SMI_EN--SMI Control and Enable Register I/O Address: Default Value: Lockable: Power Well: Note: Attribute: Size: Usage: R/W, R/WO, WO 32 bit ACPI or Legacy This register is symmetrical to the SMI status register. Bit 31:28 27 26:19 Description Reserved GPIO_UNLOCK_SMI_EN-- R/WO. Setting this bit will cause the Intel PCH to generate an SMI# when the GPIO_UNLOCK_SMI_STS bit is set in the SMI_STS register. Once written to `1', this bit can only be cleared by PLTRST#. Reserved 18 INTEL_USB2_EN -- R/W. 0 = Disable 1 = Enables Intel-Specific USB2 SMI logic to cause SMI#. 17 LEGACY_USB2_EN -- R/W. 0 = Disable 1 = Enables legacy USB2 logic to cause SMI#. 16:15 462 PMBASE + 30h 00000002h No Core Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) Bit 14 13 Description PERIODIC_EN -- R/W. 0 = Disable. 1 = Enables the PCH to generate an SMI# when the PERIODIC_STS bit is set in the SMI_STS register. TCO_EN -- R/WL. 0 = Disables TCO logic generating an SMI#. Note that if the NMI2SMI_EN bit is set, SMIs that are caused by re-routed NMIs will not be gated by the TCO_EN bit. Even if the TCO_EN bit is 0, NMIs will still be routed to cause SMIs. 1 = Enables the TCO logic to generate SMI#. Note: This bit cannot be written once the TCO_LOCK bit is set. 12 Reserved 11 MCSMI_ENMicrocontroller SMI Enable (MCSMI_EN) -- R/W. 0 = Disable. 1 = Enables PCH to trap accesses to the microcontroller range (62h or 66h) and generate an SMI#. Note that "trapped' cycles will be claimed by the PCH on PCI, but not forwarded to LPC. 10:8 Reserved 7 BIOS Release (BIOS_RLS) -- WO. 0 = This bit will always return 0 on reads. Writes of 0 to this bit have no effect. 1 = Enables the generation of an SCI interrupt for ACPI software when a one is written to this bit position by BIOS software. Note: GBL_STS being set will cause an SCI, even if the SCI_EN bit is not set. Software must take great care not to set the BIOS_RLS bit (which causes GBL_STS to be set) if the SCI handler is not in place. 6 Software SMI# Timer Enable (SWSMI_TMR_EN) -- R/W. 0 = Disable. Clearing the SWSMI_TMR_EN bit before the timer expires will reset the timer and the SMI# will not be generated. 1 = Starts Software SMI# Timer. When the SWSMI timer expires (the timeout period depends upon the SWSMI_RATE_SEL bit setting), SWSMI_TMR_STS is set and an SMI# is generated. SWSMI_TMR_EN stays set until cleared by software. 5 APMC_EN -- R/W. 0 = Disable. Writes to the APM_CNT register will not cause an SMI#. 1 = Enables writes to the APM_CNT register to cause an SMI#. 4 SLP_SMI_EN) -- R/W. 0 = Disables the generation of SMI# on SLP_EN. Note that this bit must be 0 before the software attempts to transition the system into a sleep state by writing a 1 to the SLP_EN bit. 1 = A write of 1 to the SLP_EN bit (bit 13 in PM1_CNT register) will generate an SMI#, and the system will not transition to the sleep state based on that write to the SLP_EN bit. 3 LEGACY_USB_EN -- R/W. 0 = Disable. 1 = Enables legacy USB circuit to cause SMI#. 2 BIOS_EN -- R/W. 0 = Disable. 1 = Enables the generation of SMI# when ACPI software writes a 1 to the GBL_RLS bit. Note that if the BIOS_STS bit, which gets set when software writes 1 to GBL_RLS bit, is already a 1 at the time that BIOS_EN becomes 1, an SMI# will be generated when BIOS_EN gets set. 1 End of SMI (EOS) -- R/W (special). This bit controls the arbitration of the SMI signal to the processor. This bit must be set for the PCH to assert SMI# low to the processor after SMI# has been asserted previously. 0 = Once the PCH asserts SMI# low, the EOS bit is automatically cleared. 1 = When this bit is set to 1, SMI# signal will be deasserted for 4 PCI clocks before its assertion. In the SMI handler, the processor should clear all pending SMIs (by servicing them and then clearing their respective status bits), set the EOS bit, and exit SMM. This will allow the SMI arbiter to re-assert SMI upon detection of an SMI event and the setting of a SMI status bit. Note: 0 PCH is able to generate 1st SMI after reset even though EOS bit is not set. Subsequent SMI require EOS bit is set. GBL_SMI_EN -- R/WL. 0 = No SMI# will be generated by PCH. This bit is reset by a PCI reset event. 1 = Enables the generation of SMI# in the system upon any enabled SMI event. Note: When the SMI_LOCK bit is set, this bit cannot be changed. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 463 LPC Interface Bridge Registers (D31:F0) 13.8.3.8 SMI_STS--SMI Status Register I/O Address: Default Value: Lockable: Power Well: Note: Attribute: Size: Usage: RO, R/WC 32-bit ACPI or Legacy If the corresponding _EN bit is set when the _STS bit is set, the Intel PCH will cause an SMI# (except bits 8-10 and 12, which do not need enable bits since they are logic ORs of other registers that have enable bits). The PCH uses the same GPE0_EN register (I/O address: PMBase+2Ch) to enable/disable both SMI and ACPI SCI general purpose input events. ACPI OS assumes that it owns the entire GPE0_EN register per the ACPI specification. Problems arise when some of the general-purpose inputs are enabled as SMI by BIOS, and some of the general purpose inputs are enabled for SCI. In this case ACPI OS turns off the enabled bit for any GPIx input signals that are not indicated as SCI general-purpose events at boot, and exit from sleeping states. BIOS should define a dummy control method which prevents the ACPI OS from clearing the SMI GPE0_EN bits. Bit 31:28 Description Reserved 27 GPIO_UNLOCK_SMI_STS -- R/WC. This bit will be set if the GPIO registers lockdown logic is requesting an SMI#. Writing a `1' to this bit position clears this bit to `0'. 26 SPI_STS -- RO. This bit will be set if the SPI logic is generating an SMI#. This bit is read only because the sticky status and enable bits associated with this function are located in the SPI registers. 25:22 464 PMBASE + 34h 00000000h No Core Reserved 21 MONITOR_STS -- RO. This bit will be set if the Trap/SMI logic has caused the SMI. This will occur when the processor or a bus master accesses an assigned register (or a sequence of accesses). See Section 10.1.20 through Section 10.1.35 for details on the specific cause of the SMI. 20 PCI_EXP_SMI_STS -- RO. PCI Express* SMI event occurred. This could be due to a PCI Express* PME event or Hot-Plug event. 19 Reserved 18 INTEL_USB2_STS -- RO. This non-sticky read-only bit is a logical OR of each of the SMI status bits in the Intel-Specific USB2 SMI Status Register ANDed with the corresponding enable bits. This bit will not be active if the enable bits are not set. Writes to this bit will have no effect. All integrated EHCIs are represented with this bit. 17 LEGACY_USB2_STS -- RO. This non-sticky read-only bit is a logical OR of each of the SMI status bits in the USB2 Legacy Support Register ANDed with the corresponding enable bits. This bit will not be active if the enable bits are not set. Writes to this bit will have no effect. All integrated EHCIs are represented with this bit. 16 SMBus SMI Status (SMBUS_SMI_STS) -- R/WC. Software clears this bit by writing a 1 to it. 0 = This bit is set from the 64 kHz clock domain used by the SMBus. Software must wait at least 15.63 s after the initial assertion of this bit before clearing it. 1 = Indicates that the SMI# was caused by: 1. The SMBus Slave receiving a message that an SMI# should be caused, or 2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and the SMBALERT_DIS bit is cleared, or 3. The SMBus Slave receiving a Host Notify message and the HOST_NOTIFY_INTREN and the SMB_SMI_EN bits are set, or 4. The PCH detecting the SMLINK_SLAVE_SMI command while in the S0 state. 15 SERIRQ_SMI_STS -- RO. 0 = SMI# was not caused by the SERIRQ decoder. 1 = Indicates that the SMI# was caused by the SERIRQ decoder. Note: This is not a sticky bit 14 PERIODIC_STS -- R/WC. Software clears this bit by writing a 1 to it. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set at the rate determined by the PER_SMI_SEL bits. If the PERIODIC_EN bit (PMBASE + 30h, bit 14) is also set, the PCH generates an SMI#. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) Bit Description 13 TCO_STS -- R/WC. Software clears this bit by writing a 1 to it. 0 = SMI# not caused by TCO logic. 1 = Indicates the SMI# was caused by the TCO logic. Note that this is not a wake event. 12 Device Monitor Status (DEVMON_STS) -- RO. 0 = SMI# not caused by Device Monitor. 1 = Set if bit 0 of the DEVACT_STS register (PMBASE + 44h) is set. The bit is not sticky, so writes to this bit will have no effect. 11 Microcontroller SMI# Status (MCSMI_STS) -- R/WC. Software clears this bit by writing a 1 to it. 0 = Indicates that there has been no access to the power management microcontroller range (62h or 66h). 1 = Set if there has been an access to the power management microcontroller range (62h or 66h) and the Microcontroller Decode Enable #1 bit in the LPC Bridge I/O Enables configuration register is 1 (D31:F0:Offset 82h:bit 11). Note that this implementation assumes that the Microcontroller is on LPC. If this bit is set, and the MCSMI_EN bit is also set, the PCH will generate an SMI#. 10 GPE0_STS -- RO. This bit is a logical OR of the bits in the ALT_GP_SMI_STS register that are also set up to cause an SMI# (as indicated by the GPI_ROUT registers) and have the corresponding bit set in the ALT_GP_SMI_EN register. Bits that are not routed to cause an SMI# will have no effect on this bit. 0 = SMI# was not generated by a GPI assertion. 1 = SMI# was generated by a GPI assertion. 9 GPE0_STS -- RO. This bit is a logical OR of the bits 47:32, 14:10, 8, 6:2, and 0 in the GPE0_STS register (PMBASE + 28h) that also have the corresponding bit set in the GPE0_EN register (PMBASE + 2Ch). 0 = SMI# was not generated by a GPE0 event. 1 = SMI# was generated by a GPE0 event. 8 PM1_STS_REG -- RO. This is an ORs of the bits in the ACPI PM1 Status Register (offset PMBASE+00h) that can cause an SMI#. 0 = SMI# was not generated by a PM1_STS event. 1 = SMI# was generated by a PM1_STS event. 7 Reserved 6 SWSMI_TMR_STS -- R/WC. Software clears this bit by writing a 1 to it. 0 = Software SMI# Timer has Not expired. 1 = Set by the hardware when the Software SMI# Timer expires. 5 APM_STS -- R/WC. Software clears this bit by writing a 1 to it. 0 = No SMI# generated by write access to APM Control register with APMCH_EN bit set. 1 = SMI# was generated by a write access to the APM Control register with the APMC_EN bit set. 4 SLP SMI Status (SLP_SMI_STS) -- R/WC This bit will be set by the Intel PCH when a write access attempts to set the SLP_EN bit. This bit is cleared by writing a 1 to this bit position 3 LEGACY_USB_STS -- RO. This bit is a logical OR of each of the SMI status bits in the USB Legacy Keyboard/Mouse Control Registers ANDed with the corresponding enable bits. This bit will not be active if the enable bits are not set. 0 = SMI# was not generated by USB Legacy event. 1 = SMI# was generated by USB Legacy event. 2 BIOS_STS -- R/WC. 0 = No SMI# generated due to ACPI software requesting attention. 1 = This bit gets set by hardware when a 1 is written by software to the GBL_RLS bit (D31:F0:PMBase + 04h:bit 2). When both the BIOS_EN bit (D31:F0:PMBase + 30h:bit 2) and the BIOS_STS bit are set, an SMI# will be generated. The BIOS_STS bit is cleared when software writes a 1 to its bit position. 1:0 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 465 LPC Interface Bridge Registers (D31:F0) 13.8.3.9 ALT_GP_SMI_EN--Alternate GPI SMI Enable Register I/O Address: Default Value: Lockable: Power Well: 13.8.3.10 PMBASE +38h 0000h No Resume Description 15:0 Alternate GPI Intel SMI Enable -- R/W. These bits are used to enable the corresponding GPIO to cause an SMI#. For these bits to have any effect, the following must be true. * The corresponding bit in the ALT_GP_SMI_EN register is set. * The corresponding GPI must be routed in the GPI_ROUT register to cause an Intel SMI. * The corresponding GPIO must be implemented. Note: Mapping is as follows: bit 15 corresponds to GPIO15... bit 0 corresponds to GPIO0. ALT_GP_SMI_STS--Alternate GPI SMI Status Register PMBASE +3Ah 0000h No Resume Bit 15:0 Attribute: Size: Usage: R/WC 16-bit ACPI or Legacy Description Alternate GPI SMI Status -- R/WC. These bits report the status of the corresponding GPIOs. 0 = Inactive. Software clears this bit by writing a 1 to it. 1 = Active These bits are sticky. If the following conditions are true, then an SMI# will be generated and the GPE0_STS bit set: * The corresponding bit in the ALT_GPI_SMI_EN register (PMBASE + 38h) is set * The corresponding GPIO must be routed in the GPI_ROUT register to cause an SMI. * The corresponding GPIO must be implemented. All bits are in the resume well. Default for these bits is dependent on the state of the GPIO pins. UPRWC--USB Per-Port Registers Write Control Register I/O Address: Default Value: Lockable: Power Well: Bit 15:9 8 7:1 466 R/W 16-bit ACPI or Legacy Bit I/O Address: Default Value: Lockable: Power Well: 13.8.3.11 Attribute: Size: Usage: PMBASE +3Ch 0000h No Resume Attribute: Size: Usage: R/WC, R/W, R/WO 16-bit ACPI or Legacy Description Reserved Write Enable Status -- R/WC 0 = This bit gets set by hardware when the "Per-Port Registers Write Enable" bit is written from 0 to 1 1 = This bit is cleared by software writing a 1b to this bit location The setting condition takes precedence over the clearing condition in the event that both occur at once. When this bit is 1b and bit 0 is 1b, the INTEL_USB2_STS bit is set in the SMI_STS register. Reserved. 1 Reserved 0 Write Enable SMI Enable-- R/WO 0 = Disable 1 = enables the generation of SMI when the Per-Port Registers Write Enable (bit 1) is written from 0 to 1. Once written to 1b, this bit can not be cleared by software. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.8.3.12 GPE_CNTL-- General Purpose Control Register I/O Address: Default Value: Lockable: Power Well: PMBASE +42h 00h No Bits 0-1, 3-7: Resume Bit 2: RTC Bit 7:3 Attribute: Size: Usage: R/W 8-bit ACPI or Legacy Description Reserved 2 GPIO27_POL -- R/W. This bit controls the polarity of the GPIO27 pin needed to set the GPIO27_STS bit. 0 = GPIO27 = 0 will set the GPIO27_STS bit. 1 = GPIO27 = 1 will set the GPIO27_STS bit. Note: This bit is cleared by RTCRST# assertion. 1 SWGPE_CTRL-- R/W. This bit allows software to control the assertion of SWGPE_STS bit. This bit is used by hardware as the level input signal for the SWGPE_STS bit in the GPE0_STS register. When SWGPE_CTRL is 1, SWGPE_STS will be set to 1, and writes to SWGPE_STS with a value of 1 to clear SWGPE_STS will result in SWGPE_STS being set back to 1 by hardware. When SWGPE_CTRL is 0, writes to SWGPE_STS with a value of 1 will clear SWGPE_STS to 0. In addition to being cleared by RSMRST# assertion, the PCH also clears this bit due to a Power Button Override event, Intel ME Initiated Power Button Override, Intel ME Initiated Host Reset with Power down, SMBus unconditional power down, Processor thermal trip event, or due to an internal thermal sensor catastrophic condition. 0 Reserved. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 467 LPC Interface Bridge Registers (D31:F0) 13.8.3.13 DEVACT_STS -- Device Activity Status Register I/O Address: Default Value: Lockable: Power Well: PMBASE +44h 0000h No Core Attribute: Size: Usage: R/WC 16-bit Legacy Only Each bit indicates if an access has occurred to the corresponding device's trap range, or for bits 6:9 if the corresponding PCI interrupt is active. This register is used in conjunction with the Periodic SMI# timer to detect any system activity for legacy power management. The periodic SMI# timer indicates if it is the right time to read the DEVACT_STS register (PMBASE + 44h). Note: Software clears bits that are set in this register by writing a 1 to the bit position. Bit 15:13 12 11:10 Reserved KBC_ACT_STS -- R/WC. KBC (60/64h). 0 = Indicates that there has been no access to this device's I/O range. 1 = This device's I/O range has been accessed. Clear this bit by writing a 1 to the bit location. Reserved 9 PRIQDH_ACT_STS -- R/WC. PIRQ[D or H]. 0 = The corresponding PCI interrupts have not been active. 1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by writing a 1 to the bit location. 8 PIRQCG_ACT_STS -- R/WC. PIRQ[C or G]. 0 = The corresponding PCI interrupts have not been active. 1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by writing a 1 to the bit location. 7 PIRQBF_ACT_STS -- R/WC. PIRQ[B or F]. 0 = The corresponding PCI interrupts have not been active. 1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by writing a 1 to the bit location. 6 PIRQAE_ACT_STS -- R/WC. PIRQ[A or E]. 0 = The corresponding PCI interrupts have not been active. 1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by writing a 1 to the bit location. 5:0 13.8.3.14 Description Reserved PM2_CNT--Power Management 2 Control I/O Address: PMBASE + 50h Default Value: Lockable: Power Well: 00h No Core Bit 7:1 0 468 Attribute: Size: Usage: R/W 8-bit ACPI Description Reserved Arbiter Disable (ARB_DIS) -- R/W This bit is a scratchpad bit for legacy software compatibility. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.9 System Management TCO Registers The TCO logic is accessed using registers mapped to the PCI configuration space (Device 31:Function 0) and the system I/O space. For TCO PCI Configuration registers, see LPC Device 31:Function 0 PCI Configuration registers. TCO Register I/O Map The TCO I/O registers reside in a 32-byte range pointed to by a TCOBASE value, which is, PMBASE + 60h in the PCI config space. The following table shows the mapping of the registers within that 32-byte range. Each register is described in the following sections. Table 13-12. TCO I/O Register Address Map TCOBASE + Offset Mnemonic 00h-01h TCO_RLD 02h TCO_DAT_IN Register Name TCO Timer Reload and Current Value TCO Data In TCO Data Out Default Type 0000h R/W 00h R/W 03h TCO_DAT_OUT 00h R/W 04h-05h TCO1_STS TCO1 Status 0000h R/WC, RO 06h-07h TCO2_STS TCO2 Status 0000h R/WC 08h-09h TCO1_CNT TCO1 Control 0000h R/W, R/WLO, R/WC 0Ah-0Bh TCO2_CNT TCO2 Control 0008h R/W 0Ch-0Dh TCO_MESSAGE1, TCO_MESSAGE2 00h R/W 0Eh TCO_WDCNT 00h R/W 0Fh -- -- -- 10h SW_IRQ_GEN 03h R/W 11h -- -- -- 12h-13h TCO_TMR 0004h R/W 14h-1Fh -- -- -- TCO Message 1 and 2 Watchdog Control Reserved Software IRQ Generation Reserved TCO Timer Initial Value Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 469 LPC Interface Bridge Registers (D31:F0) 13.9.1 TCO_RLD--TCO Timer Reload and Current Value Register I/O Address: Default Value: Lockable: TCOBASE +00h 0000h No Bit 15:10 9:0 13.9.2 Reserved TCO Timer Value -- R/W. Reading this register will return the current count of the TCO timer. Writing any value to this register will reload the timer to prevent the timeout. TCO_DAT_IN--TCO Data In Register TCOBASE +02h 00h No Bit 7:0 R/W 8-bit Core TCO Data In Value -- R/W. This data register field is used for passing commands from the OS to the SMI handler. Writes to this register will cause an SMI and set the SW_TCO_SMI bit in the TCO1_STS register (D31:F0:04h). TCO_DAT_OUT--TCO Data Out Register TCOBASE +03h 00h No Bit 7:0 Attribute: Size: Power Well: R/W 8-bit Core Description TCO Data Out Value -- R/W. This data register field is used for passing commands from the Intel SMI handler to the OS. Writes to this register will set the TCO_INT_STS bit in the TCO1_STS register. It will also cause an interrupt, as selected by the TCO_INT_SEL bits. TCO1_STS--TCO1 Status Register I/O Address: Default Value: Lockable: Bit 15:14 470 Attribute: Size: Power Well: Description I/O Address: Default Value: Lockable: 13.9.4 R/W 16-bit Core Description I/O Address: Default Value: Lockable: 13.9.3 Attribute: Size: Power Well: TCOBASE +04h 2000h `Size: No Attribute: 16-bit Power Well: R/WC, RO Core (Except bit 7, in RTC) Description Reserved 13 TCO_SLVSEL (TCO Slave Select) -- RO. This register bit is Read Only by Host and indicates the value of TCO Slave Select Soft Strap. Refer to the PCH Soft Straps section of the SPI Chapter for details. 12 DMISERR_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = PCH received a DMI special cycle message using DMI indicating that it wants to cause an SERR#. The software must read the Processor to determine the reason for the SERR#. 11 Reserved 10 DMISMI_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = PCH received a DMI special cycle message using DMI indicating that it wants to cause an SMI. The software must read the Processor to determine the reason for the SMI. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) Bit Description 9 DMISCI_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = PCH received a DMI special cycle message using DMI indicating that it wants to cause an SCI. The software must read the Processor to determine the reason for the SCI. 8 BIOSWR_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = PCH sets this bit and generates and SMI# to indicate an invalid attempt to write to the BIOS. This occurs when either: a) The BIOSWP bit is changed from 0 to 1 and the BLD bit is also set, or b) any write is attempted to the BIOS and the BIOSWP bit is also set. Note: On write cycles attempted to the 4 MB lower alias to the BIOS space, the BIOSWR_STS will not be set. NEWCENTURY_STS -- R/WC. This bit is in the RTC well. 0 = Cleared by writing a 1 to the bit position or by RTCRST# going active. 1 = This bit is set when the Year byte (RTC I/O space, index offset 09h) rolls over from 99 to 00. Setting this bit will cause an SMI# (but not a wake event). Note: 7 6:4 The NEWCENTURY_STS bit is not valid when the RTC battery is first installed (or when RTC power has not been maintained). Software can determine if RTC power has not been maintained by checking the RTC_PWR_STS bit (D31:F0:A4h, bit 2), or by other means (such as a checksum on RTC RAM). If RTC power is determined to have not been maintained, BIOS should set the time to a valid value and then clear the NEWCENTURY_STS bit. The NEWCENTURY_STS bit may take up to 3 RTC clocks for the bit to be cleared after a 1 is written to the bit to clear it. After writing a 1 to this bit, software should not exit the SMI handler until verifying that the bit has actually been cleared. This will ensure that the SMI is not re-entered. Reserved 3 TIMEOUT -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by PCH to indicate that the SMI was caused by the TCO timer reaching 0. 2 TCO_INT_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = SMI handler caused the interrupt by writing to the TCO_DAT_OUT register (TCOBASE + 03h). 1 SW_TCO_SMI -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Software caused an SMI# by writing to the TCO_DAT_IN register (TCOBASE + 02h). 0 NMI2SMI_STS -- RO. 0 = Cleared by clearing the associated NMI status bit. 1 = Set by the PCH when an SMI# occurs because an event occurred that would otherwise have caused an NMI (because NMI2SMI_EN is set). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 471 LPC Interface Bridge Registers (D31:F0) 13.9.5 TCO2_STS--TCO2 Status Register I/O Address: Default Value: Lockable: Bit 15:5 472 TCOBASE +06h 0000h No Attribute: Size: Power Well: R/WC 16-bit Resume (Except Bit 0, in RTC) Description Reserved 4 SMLink Slave Intel SMI Status (SMLINK_SLV_SMI_STS) -- R/WC. Allow the software to go directly into a pre-determined sleep state. This avoids race conditions. Software clears this bit by writing a 1 to it. 0 = The bit is reset by RSMRST#, but not due to the PCI Reset associated with exit from S3-S5 states. 1 = PCH sets this bit to 1 when it receives the Intel SMI message on the SMLink Slave Interface. 3 Reserved 2 BOOT_STS -- R/WC. 0 = Cleared by PCH based on RSMRST# or by software writing a 1 to this bit. Note that software should first clear the SECOND_TO_STS bit before writing a 1 to clear the BOOT_STS bit. 1 = Set to 1 when the SECOND_TO_STS bit goes from 0 to 1 and the processor has not fetched the first instruction. If rebooting due to a second TCO timer timeout, and if the BOOT_STS bit is set, the PCH will reboot using the `safe' multiplier (1111). This allows the system to recover from a processor frequency multiplier that is too high, and allows the BIOS to check the BOOT_STS bit at boot. If the bit is set and the frequency multiplier is 1111, then the BIOS knows that the processor has been programmed to an invalid multiplier. 1 SECOND_TO_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it, or by a RSMRST#. 1 = PCH sets this bit to 1 to indicate that the TIMEOUT bit had been (or is currently) set and a second timeout occurred before the TCO_RLD register was written. If this bit is set and the NO_REBOOT config bit is 0, then the PCH will reboot the system after the second timeout. The reboot is done by asserting PLTRST#. 0 Intruder Detect (INTRD_DET) -- R/WC. 0 = Software clears this bit by writing a 1 to it, or by RTCRST# assertion. 1 = Set by PCH to indicate that an intrusion was detected. This bit is set even if the system is in G3 state. Notes: 1. This bit has a recovery time. After writing a 1 to this bit position (to clear it), the bit may be read back as a 1 for up 65 microseconds before it is read as a 0. Software must be aware of this recovery time when reading this bit after clearing it. 2. If the INTRUDER# signal is active when the software attempts to clear the INTRD_DET bit, the bit will remain as a 1, and the SMI# will be generated again immediately. The SMI handler can clear the INTRD_SEL bits (TCOBASE + 0Ah, bits 2:1), to avoid further SMIs. However, if the INTRUDER# signals goes inactive and then active again, there will not be further SMI's (because the INTRD_SEL bits would select that no SMI# be generated). 3. If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written as a 1, then the INTRD_DET signal will go to a 0 when INTRUDER# input signal goes inactive. Note that this is slightly different than a classic sticky bit, since most sticky bits would remain active indefinitely when the signal goes active and would immediately go inactive when a 1 is written to the bit. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.9.6 TCO1_CNT--TCO1 Control Register I/O Address: Default Value: Lockable: TCOBASE +08h 0000h No Attribute: Size: Power Well: Bit 15:13 R/W, R/WLO, R/WC 16-bit Core Description Reserved 12 TCO_LOCK -- R/WLO. When set to 1, this bit prevents writes from changing the TCO_EN bit (in offset 30h of Power Management I/O space). Once this bit is set to 1, it can not be cleared by software writing a 0 to this bit location. A core-well reset is required to change this bit from 1 to 0. This bit defaults to 0. 11 TCO Timer Halt (TCO_TMR_HLT) -- R/W. 0 = The TCO Timer is enabled to count. 1 = The TCO Timer will halt. It will not count, and thus cannot reach a value that will cause an SMI# or set the SECOND_TO_STS bit. When set, this bit will prevent rebooting and prevent Alert On LAN event messages from being transmitted on the SMLink (but not Alert On LAN* heartbeat messages). 10 Reserved NMI2SMI_EN -- R/W. 0 = Normal NMI functionality. 1 = Forces all NMIs to instead cause SMIs. The functionality of this bit is dependent upon the settings of the NMI_EN bit and the GBL_SMI_EN bit as detailed in the following table: 9 8 7:0 13.9.7 NMI_EN GBL_SMI_EN Description 0b 0b No SMI# at all because GBL_SMI_EN = 0 0b 1b SMI# will be caused due to NMI events 1b 0b No SMI# at all because GBL_SMI_EN = 0 1b 1b No SMI# due to NMI because NMI_EN = 1 NMI_NOW -- R/WC. 0 = Software clears this bit by writing a 1 to it. The NMI handler is expected to clear this bit. Another NMI will not be generated until the bit is cleared. 1 = Writing a 1 to this bit causes an NMI. This allows the BIOS or SMI handler to force an entry to the NMI handler. Reserved TCO2_CNT--TCO2 Control Register I/O Address: Default Value: Lockable: TCOBASE +0Ah 0008h No Bit 15:6 5:4 Attribute: Size: Power Well: R/W 16-bit Resume Description Reserved OS_POLICY -- R/W. OS-based software writes to these bits to select the policy that the BIOS will use after the platform resets due the WDT. The following convention is recommended for the BIOS and OS: 00 = Boot normally 01 = Shut down 10 = Do not load OS. Hold in pre-boot state and use LAN to determine next step 11 = Reserved Note: These are just scratchpad bits. They should not be reset when the TCO logic resets the platform due to Watchdog Timer. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 473 LPC Interface Bridge Registers (D31:F0) Bit Description 3 GPIO11_ALERT_DISABLE -- R/W. At reset (using RSMRST# asserted) this bit is set and GPIO[11] alerts are disabled. 0 = Enable. 1 = Disable GPIO11/SMBALERT# as an alert source for the heartbeats and the SMBus slave. 2:1 0 13.9.8 INTRD_SEL -- R/W. This field selects the action to take if the INTRUDER# signal goes active. 00 = No interrupt or SMI# 01 = Interrupt (as selected by TCO_INT_SEL). 10 = Intel SMI 11 = Reserved Reserved TCO_MESSAGE1 and TCO_MESSAGE2 Registers I/O Address: Default Value: Lockable: TCOBASE +0Ch (Message 1)Attribute: TCOBASE +0Dh (Message 2) 00h Size: No Power Well: Bit 7:0 13.9.9 TCO_MESSAGE[n] -- R/W. BIOS can write into these registers to indicate its boot progress. The external microcontroller can read these registers to monitor the boot progress. TCO_WDCNT--TCO Watchdog Control Register Bit 7:0 Attribute: Size: R/W 8 bits Description The BIOS or system management software can write into this register to indicate more details on the boot progress. The register will reset to 00h based on a RSMRST# (but not PLTRST#). The external microcontroller can read this register to monitor boot progress. SW_IRQ_GEN--Software IRQ Generation Register Offset Address: TCOBASE + 10h Default Value: 03h Power Well: Core Bit 7:2 474 8-bit Resume Description Offset Address: TCOBASE + 0Eh Default Value: 00h Power Well: Resume 13.9.10 R/W Attribute: Size: R/W 8 bits Description Reserved 1 IRQ12_CAUSE -- R/W. When software sets this bit to 1, IRQ12 will be asserted. When software sets this bit to 0, IRQ12 will be deasserted. 0 IRQ1_CAUSE -- R/W. When software sets this bit to 1, IRQ1 will be asserted. When software sets this bit to 0, IRQ1 will be deasserted. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.9.11 TCO_TMR--TCO Timer Initial Value Register I/O Address: Default Value: Lockable: TCOBASE +12h 0004h No Bit 15:10 9:0 13.10 Attribute: Size: Power Well: R/W 16-bit Core Description Reserved TCO Timer Initial Value -- R/W. Value that is loaded into the timer each time the TCO_RLD register is written. Values of 0000h or 0001h will be ignored and should not be attempted. The timer is clocked at approximately 0.6 seconds, and thus allows timeouts ranging from 1.2 second to 613.8 seconds. Note: The timer has an error of 1 tick (0.6s). The TCO Timer will only count down in the S0 state. General Purpose I/O Registers (D31:F0) The control for the general purpose I/O signals is handled through a 128-byte I/O space. The base offset for this space is selected by the GPIOBASE register. Table 13-13. Registers to Control GPIO Address Map GPIOBASE + Offset Mnemonic 00h-03h GPIO_USE_SEL 04h-07h GP_IO_SEL 08h-0Bh -- 0Ch-0Fh GP_LVL Register Name Default Access GPIO Use Select BF7FA1FFh R/W GPIO Input/Output Select E8EB6EFFh R/W Reserved GPIO Level for Input or Output 0h -- 02FE0100h R/W 10h-13h -- Reserved 0h -- 14h-17h -- Reserved 0h -- 18h-1Bh GPO_BLINK 1Ch-1Fh GP_SER_BLINK GPIO Blink Enable 00040000h R/W GP Serial Blink 00000000h R/W 20-23h GP_SB_CMDSTS 24-27h GP_SB_DATA GP Serial Blink Command Status 00080000h R/W GP Serial Blink Data 00000000h R/W 28-29h GPI_NMI_EN GPI NMI Enable 0000 R/W 2A-2Bh GPI_NMI_STS GPI NMI Status 0000 R/WC 2C-2Fh GPI_INV GPIO Signal Invert 00000000h R/W 30h-33h GPIO_USE_SEL2 GPIO Use Select 2 020300FFh R/W 34h-37h GP_IO_SEL2 GPIO Input/Output Select 2 1F57FFF4h R/W 38h-3Bh GP_LVL2 GPIO Level for Input or Output 2 A4AA0007h R/W 3Ch-3Fh -- 40h-43h GPIO_USE_SEL3 44h-47h GP_IO_SEL3 48h-4Bh GP_LVL3 Reserved 0h -- 0000033Fh R/W GPIO Input/Output Select 3 00000FF0h R/W GPIO Level for Input or Output 3 000000C0h R/W GPIO Use Select 3 4Ch-5Fh -- 0h -- 60h-63h GP_RST_SEL1 Reserved GPIO Reset Select 1 01000000h R/W 64h-67h GP_RST_SEL2 GPIO Reset Select 2 0h R/W 68h-6Bh GP_RST_SEL3 GPIO Reset Select 3 0h R/W 6Ch-7Fh -- Reserved 0h -- Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 475 LPC Interface Bridge Registers (D31:F0) 13.10.1 GPIO_USE_SEL--GPIO Use Select Register Offset Address: GPIOBASE + 00h Default Value: BF7FA1FFh Lockable: Yes Bit Attribute: Size: Power Well: R/W 32-bit Core for 0:7, 16:23, Resume for 8:15, 24:31 Description GPIO_USE_SEL[31:0] -- R/W. Each bit in this register enables the corresponding GPIO (if it exists) to be used as a GPIO, rather than for the native function. 0 = Signal used as native function. 1 = Signal used as a GPIO. 31:0 13.10.2 Notes: 1. The following bits are always 1 because they are always unMultiplexed: 8, 15, 24, 27, and 28. 2. After a full reset (RSMRST#) all multiplexed signals in the resume and core wells are configured as their default function. After only a PLTRST#, the GPIOs in the core well are configured as their default function. 3. When configured to GPIO mode, the muxing logic will present the inactive state to native logic that uses the pin as an input. 4. By default, all GPIOs are reset to the default state by CF9h reset except GPIO24. Other resume well GPIOs' reset behavior can be programmed using GP_RST_SEL registers. 5. Bit 26 may be overridden by bit 8 in the GEN_PMCON_3 Register. 6. Bit 29 can be configured to GPIO when SLP_LAN#/GPIO29 Select Soft-strap is set to 1 (GPIO usage). GP_IO_SEL--GPIO Input/Output Select Register Offset Address: GPIOBASE +04h Default Value: E8EB6EFFh Lockable: Yes 476 Attribute: Size: Power Well: R/W 32-bit Core for 0:7, 16:23, Resume for 8:15, 24:31 Bit Description 31:0 GP_IO_SEL[31:0] -- R/W. When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits have no effect. The value reported in this register is undefined when programmed as native mode. 0 = Output. The corresponding GPIO signal is an output. 1 = Input. The corresponding GPIO signal is an input. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.10.3 GP_LVL--GPIO Level for Input or Output Register Offset Address: GPIOBASE +0Ch Default Value: 02FE0100h Lockable: Yes Bit Attribute: Size: Power Well: R/W 32-bit Core for 0:7, 16:23, Resume for 8:15, 24:31 Description GP_LVL[31:0]-- R/W. These registers are implemented as dual read/write with dedicated storage each. Write value will be stored in the write register, while read is coming from the read register which will always reflect the value of the pin. 31:0 If GPIO[n] is programmed to be an output (using the corresponding bit in the GP_IO_SEL register), then the corresponding GP_LVL[n] write register value will drive a high or low value on the output pin. 1 = high, 0 = low. When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits are stored but have no effect to the pin value. The value reported in this register is undefined when programmed as native mode. Note: Bit 29 setting will be ignored if Intel ME FW is configuring SLP_LAN# behavior. When GPIO29/SLP_LAN# Select Soft-strap is set to 1 (GPIO usage), bit 29 can be used as regular GP_LVL bit. 13.10.4 GPO_BLINK--GPO Blink Enable Register Offset Address: GPIOBASE +18h Default Value: 00040000h Lockable: No Attribute: Size: Power Well: R/W 32-bit Core for 0:7, 16:23, Resume for 8:15, 24:31 Bit Description 31:0 GP_BLINK[31:0] -- R/W. The setting of this bit has no effect if the corresponding GPIO signal is programmed as an input. 0 = The corresponding GPIO will function normally. 1 = If the corresponding GPIO is programmed as an output, the output signal will blink at a rate of approximately once per second. The high and low times have approximately 0.5 seconds each. The GP_LVL bit is not altered when this bit is set. The value of the corresponding GP_LVL bit remains unchanged during the blink process, and does not effect the blink in any way. The GP_LVL bit is not altered when programmed to blink. It will remain at its previous value. These bits correspond to GPIO in the Resume well. These bits revert to the default value based on RSMRST# or a write to the CF9h register (but not just on PLTRST#). Note: GPIO18 will blink by default immediately after reset. This signal could be connected to an LED to indicate a failed boot (by programming BIOS to clear GP_BLINK18 after successful POST). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 477 LPC Interface Bridge Registers (D31:F0) 13.10.5 GP_SER_BLINK--GP Serial Blink Offset Address: GPIOBASE +1Ch Default Value: 00000000h Lockable: No 13.10.6 R/W 32-bit Core for 0:7, 16:23, Resume for 8:15, 24:31 Bit Description 31:0 GP_SER_BLINK[31:0] -- R/W. The setting of this bit has no effect if the corresponding GPIO is programmed as an input or if the corresponding GPIO has the GPO_BLINK bit set. When set to a `0', the corresponding GPIO will function normally. When using serial blink, this bit should be set to a 1 while the corresponding GP_IO_SEL bit is set to 1. Setting the GP_IO_SEL bit to 0 after the GP_SER_BLINK bit ensures PCH will not drive a 1 on the pin as an output. When this corresponding bit is set to a 1 and the pin is configured to output mode, the serial blink capability is enabled. The PCH will serialize messages through an open-drain buffer configuration. The value of the corresponding GP_LVL bit remains unchanged and does not impact the serial blink capability in any way. Writes to this register have no effect when the corresponding pin is configured in native mode and the read value returned is undefined. GP_SB_CMDSTS--GP Serial Blink Command Status Offset Address: GPIOBASE +20h Default Value: 00080000h Lockable: No Bit Attribute: Size: Power Well: R/W, RO 32-bit Core Description 31:24 Reserved 23:22 Data Length Select (DLS) -- R/W. This field determines the number of bytes to serialize on GPIO 00 = Serialize bits 7:0 of GP_SB_DATA (1 byte) 01 = Serialize bits 15:0 of GP_SB_DATA (2 bytes) 10 = Undefined - Software must not write this value 11 = Serialize bits 31:0 of GP_SB_DATA (4 bytes) Software should not modify the value in this register unless the Busy bit is clear. Writes to this register have no effect when the corresponding pin is configured in native mode and the read value returned is undefined. 21:16 Data Rate Select (DRS) -- R/W. This field selects the number of 120 ns time intervals to count between Manchester data transitions. The default of 8h results in a 960 ns minimum time between transitions. A value of 0h in this register produces undefined behavior. Software should not modify the value in this register unless the Busy bit is clear. 15:9 8 7:1 0 478 Attribute: Size: Power Well: Reserved Busy -- RO. This read-only status bit is the hardware indication that a serialization is in progress. Hardware sets this bit to 1 based on the Go bit being set. Hardware clears this bit when the Go bit is cleared by the hardware. Reserved Go -- R/W. This bit is set to 1 by software to start the serialization process. Hardware clears the bit after the serialized data is sent. Writes of 0 to this register have no effect. Software should not write this bit to 1 unless the Busy status bit is cleared. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.10.7 GP_SB_DATA--GP Serial Blink Data Offset Address: GPIOBASE +24h Default Value: 00000000h Lockable: No 13.10.8 R/W 32-bit Core Bit Description 31:0 GP_SB_DATA[31:0] -- R/W. This register contains the data serialized out. The number of bits shifted out are selected through the DLS field in the GP_SB_CMDSTS register. This register should not be modified by software when the Busy bit is set. GPI_NMI_EN--GPI NMI Enable Offset Address: GPIOBASE +28h Default Value: 00000h Lockable: No 13.10.9 Attribute: Size: Power Well: Attribute: Size: Power Well: R/W 16-bit Core for 0:7 Resume for 8:15 Bit Description 15:0 GPI_NMI_EN[15:0]. GPI NMI Enable: This bit only has effect if the corresponding GPIO is used as an input and its GPI_ROUT register is being programmed to NMI functionality. When set to 1, it used to allow active-low and active-high inputs (depends on inversion bit) to cause NMI. GPI_NMI_STS--GPI NMI Status Offset Address: GPIOBASE +2Ah Default Value: 00000h Lockable: Yes Attribute: Size: Power Well: R/WC 16-bit Core for 0:7 Resume for 8:15 Bit Description 15:0 GPI_NMI_STS[15:0]. GPI NMI Status: GPI_NMI_STS[15:0]. GPI NMI Status: This bit is set if the corresponding GPIO is used as an input, and its GPI_ROUT register is being programmed to NMI functionality and also GPI_NMI_EN bit is set when it detects either: 1) active-high edge when its corresponding GPI_INV is configured with value 0. 2) active-low edge when its corresponding GPI_INV is configured with value 1. Note: Writing value of 1 will clear the bit, while writing value of 0 have no effect. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 479 LPC Interface Bridge Registers (D31:F0) 13.10.10 GPI_INV--GPIO Signal Invert Register Offset Address: GPIOBASE +2Ch Default Value: 00000000h Lockable: No Bit 31:16 31:0 Attribute: Size: Power Well: R/W 32-bit Core for 17, 16, 7:0 Description Reserved Input Inversion (GP_INV[n]) -- R/W. This bit only has effect if the corresponding GPIO is used as an input and used by the GPE logic, where the polarity matters. When set to `1', then the GPI is inverted as it is sent to the GPE logic that is using it. This bit has no effect on the value that is reported in the GP_LVL register. These bits are used to allow both active-low and active-high inputs to cause SMI# or SCI. Note that in the S0 or S1 state, the input signal must be active for at least two PCI clocks to ensure detection by the PCH. In the S3, S4 or S5 states the input signal must be active for at least 2 RTC clocks to ensure detection. The setting of these bits has no effect if the corresponding GPIO is programmed as an output. These bits correspond to GPI that are in the resume well, and will be reset to their default values by RSMRST# or by a write to the CF9h register. 0 = The corresponding GPI_STS bit is set when the PCH detects the state of the input pin to be high. 1 = The corresponding GPI_STS bit is set when the PCH detects the state of the input pin to be low. 13.10.11 GPIO_USE_SEL2--GPIO Use Select 2 Register Offset Address: GPIOBASE +30h Default Value: 020300FFh Dockable: Yes Bit 31:0 Attribute: Size: Power Well: R/W 32-bit Core for 0:7, 16:23, Resume for 8:15, 24:31 Description GPIO_USE_SEL2[63:32]-- R/W. Each bit in this register enables the corresponding GPIO (if it exists) to be used as a GPIO, rather than for the native function. 0 = Signal used as native function. 1 = Signal used as a GPIO. Notes: 1. The following bit are always 1 because it is always unMultiplexed:0, 3, 25. 2. If GPIO[n] does not exist, then, the (n-32) bit in this register will always read as 0 and writes will have no effect. The following bits are always 0: 29, 30 and 31. 3. After a full reset RSMRST# all multiplexed signals in the resume and core wells are configured as their default function. After only a PLTRST#, the GPIOs in the core well are configured as their default function. 4. When configured to GPIO mode, the muxing logic will present the inactive state to native logic that uses the pin as an input. 5. Bit 26 is ignored, functionality is configured by bits 9:8 of FLMAP0 register. This register corresponds to GPIO[63:32]. Bit 0 corresponds to GPIO32 and bit 28 corresponds to GPIO60. 13.10.12 GP_IO_SEL2--GPIO Input/Output Select 2 Register Offset Address: GPIOBASE +34h Default Value: 1F57FFF4h Lockable: Yes Bit 31:0 480 Attribute: R/W Power Well: Core for 0:7, 16:23, Resume for 8:15, 24:31 Description GP_IO_SEL2[63:32] -- R/W. 0 = GPIO signal is programmed as an output. 1 = Corresponding GPIO signal (if enabled in the GPIO_USE_SEL2 register) is programmed as an input. This register corresponds to GPIO[63:32]. Bit 0 corresponds to GPIO32. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.10.13 GP_LVL2--GPIO Level for Input or Output 2 Register Offset Address: GPIOBASE +38h Default Value: A4AA0007h Lockable: Yes Bit 31:0 Attribute: Size: Power Well: R/W 32-bit Core for 0:7, 16:23, Resume for 8:15, 24:31 Description GP_LVL[63:32] -- R/W. These registers are implemented as dual read/write with dedicated storage each. Write value will be stored in the write register, while read is coming from the read register which will always reflect the value of the pin. If GPIO[n] is programmed to be an output (using the corresponding bit in the GP_IO_SEL register), then the corresponding GP_LVL[n] write register value will drive a high or low value on the output pin. 1 = high, 0 = low. When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits are stored but have no effect to the pin value. The value reported in this register is undefined when programmed as native mode. Note: This register corresponds to GPIO[63:32]. Bit 0 corresponds to GPIO32. 13.10.14 GPIO_USE_SEL3--GPIO Use Select 3 Register Offset Address: GPIOBASE +40h Default Value: 0000033Fh Lockable: Yes Bit 31:12 11:0 Attribute: Size: Power Well: R/W 32-bit Core for 0:7, 16:23, Resume for 8:15, 24:31 Description Always 0. No corresponding GPIO. GPIO_USE_SEL3[75:64]-- R/W. Each bit in this register enables the corresponding GPIO (if it exists) to be used as a GPIO, rather than for the native function. 0 = Signal used as native function. 1 = Signal used as a GPIO. Notes: 1. The following bit is always 1 because it is always unMultiplexed: 8 2. If GPIO[n] does not exist, then, the (n-32) bit in this register will always read as 0 and writes will have no effect. 3. After a full reset RSMRST# all multiplexed signals in the resume and core wells are configured as their default function. After only a PLTRST#, the GPIOs in the core well are configured as their default function. 4. When configured to GPIO mode, the muxing logic will present the inactive state to native logic that uses the pin as an input. This register corresponds to GPIO[95:64]. Bit 0 corresponds to GPIO64 and bit 11 corresponds to GPIO75. 13.10.15 GP_IO_SEL3--GPIO Input/Output Select 3 Register Offset Address: GPIOBASE +44h Default Value: 00000FF0h Lockable: Yes Bit 31:12 11:0 Attribute: Size: Power Well: R/W 32-bit Core for 0:7, 16:23, Resume for 8:15, 24:31 Description Always 0. No corresponding GPIO. GPIO_IO_SEL3[75:64]-- R/W. 0 = GPIO signal is programmed as an output. 1 = Corresponding GPIO signal (if enabled in the GPIO_USE_SEL3 register) is programmed as an input. This register corresponds to GPIO[95:64]. Bit 0 corresponds to GPIO64. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 481 LPC Interface Bridge Registers (D31:F0) 13.10.16 GP_LVL3--GPIO Level for Input or Output 3 Register Offset Address: GPIOBASE +48h Default Value: 000000C0h Lockable: Yes Bit 31:12 11:0 Attribute: Size: Power Well: R/W 32-bit Core for 0:7, 16:23, Resume for 8:15, 24:31 Description Always 0. No corresponding GPIO. GP_LVL[75:64]-- R/W. These registers are implemented as dual read/write with dedicated storage each. Write value will be stored in the write register, while read is coming from the read register which will always reflect the value of the pin. If GPIO[n] is programmed to be an output (using the corresponding bit in the GP_IO_SEL register), then the corresponding GP_LVL[n] write register value will drive a high or low value on the output pin. 1 = high, 0 = low. When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits are stored but have no effect to the pin value. The value reported in this register is undefined when programmed as native mode. This register corresponds to GPIO[75:64]. Bit 0 corresponds to GPIO64 and bit 11 corresponds to GPIO75. 13.10.17 GP_RST_SEL1 -- GPIO Reset Select Offset Address: GPIOBASE +60h Default Value: 01000000h Lockable: Yes Bit 31:24 15:8 7:0 482 R/W 32-bit Core for 0:7, 16:23, Resume for 8:15, 24:31 Description GP_RST_SEL[31:24] -- R/W. 0 = Corresponding GPIO registers will be reset by PCH_PWROK deassertion, CF9h reset (06h or 0Eh), or SYS_RST# assertion. 1 = Corresponding GPIO registers will be reset by RSMRST# assertion only. Note: 23:16 Attribute: Size: Power Well: GPIO[24] register bits are not cleared by CF9h reset by default. Reserved GP_RST_SEL[15:8] -- R/W. 0 = Corresponding GPIO registers will be reset by PCH_PWROK deassertion, CF9h reset (06h or 0Eh), or SYS_RST# assertion. 1 = Corresponding GPIO registers will be reset by RSMRST# assertion only. Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.10.18 GP_RST_SEL2 -- GPIO Reset Select Offset Address: GPIOBASE +64h Default Value: 00000000h Lockable: Yes Bit 31:24 23:16 15:8 7:0 Attribute: Size: Power Well: R/W 32-bit Core for 0:7, 16:23, Resume for 8:15, 24:31 Description GP_RST_SEL[63:56] -- R/W. 0 = Corresponding GPIO registers will be reset by PCH_PWROK deassertion, CF9h reset (06h or 0Eh), or SYS_RST# assertion. 1 = Corresponding GPIO registers will be reset by RSMRST# assertion only. Reserved GP_RST_SEL[47:40] -- R/W. 0 = Corresponding GPIO registers will be reset by PCH_PWROK deassertion, CF9h reset (06h or 0Eh), or SYS_RST# assertion. 1 = Corresponding GPIO registers will be reset by RSMRST# assertion only. Reserved 13.10.19 GP_RST_SEL3 -- GPIO Reset Select Offset Address: GPIOBASE +68h Default Value: 00000000h Lockable: Yes Bit 31:12 11:8 7:0 Attribute: Size: Power Well: R/W 32-bit Core for 0:7, 16:23, Resume for 8:15, 24:31 Description Reserved GP_RST_SEL[75:72] -- R/W. 0 = Corresponding GPIO registers will be reset by PCH_PWROK deassertion, CF9h reset (06h or 0Eh), or SYS_RST# assertion. 1 = Corresponding GPIO registers will be reset by RSMRST# assertion only. Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 483 LPC Interface Bridge Registers (D31:F0) 13.11 GPIO Serial Expander MMIO Registers The control for the GSX signals is handled through MMIO space. The base offset for this space is selected by the GSXBAR register in Section 10.1.49. Table 13-14. Registers to Control GSX Address Map 13.11.1 GSXBAR + offset Mnemonic 000h-00Fh -- Reserved Default Access 0h -- 010h-013h GSX_CxCAP GSX Capabilities 1 00000000h R/W, RO 014h-017h GSX_CxCAP2 GSX Capabilities 2 00031250h -- 018h-01Fh -- 020h-023h GSX_CxGPILVL 024h-027h GSX_CxGPILVL_DW1 028h-02Fh -- Reserved 0h -- GSX Input Level DWord 0 00000000h RO GSX Input Level DWord 1 00000000h RO 0h -- Reserved 030h-033h GSX_CxGPOLVL GSX Output Level DWord 0 00000000h R/W 034h-037h GSX_CxGPOLVL_DW1 GSX Output Level DWord 1 00000000h R/W 038h-03Fh -- 0040h-0043h GSX_CxCMD 044h-3FFh -- Reserved GSX Command Register Reserved 0h -- 00000000h R/W, RO 0h -- GSX_CxCAP -- GSX Capabilities Register 1 Offset Address: GSXBAR +10h Default Value: 00000000h Bit 31:10 484 Register Name Attribute: Size: R/W, RO 32-bit Description Reserved 9:5 Number of Output Expanders (NOUT) -- R/W. BIOS programs this field to indicate number of output expander components which corresponds to multiple of CxGPO in byte granularity. 00000b = No output expanders 00001b = 1 output expander 00010b = 2 output expanders ... Note: Total number of NOUT + NIN <= 8 4:0 Number of Input Expanders (NIN) -- R/W. BIOS programs this field to indicate number of output expander components which corresponds to multiple of CxGPI in byte granularity. 00000b = No input expanders 00001b = 1 input expander 00010b = 2 input expanders ... Note: Total number of NOUT + NIN <= 8 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet LPC Interface Bridge Registers (D31:F0) 13.11.2 GSX_CxCAP2 -- GSX Capabilities Register 2 Offset Address: GSXBAR +14h Default Value: 000015625h Bit Attribute: Size: R/W, RO 32-bit Description 31:26 Reserved 25:12 SCLK Rate (SCLKR) -- RO. SCLKR and SCLKRD are BCD (binary-coded decimal) encoded. The SCLKR represent MHz rate as a whole number, and SCLKR_D represent the decimal number. Note: The GSXSCLK is running at 15.625MHZ. SCLK Rate Decimal (SCLKR_D) -- RO. Refer to SCLKR. 11:0 Note: 13.11.3 The GSXSCLK is running at 15.625 MHZ. GSX_CxGPILVL -- GSX Input Level Register DW0 Offset Address: GSXBAR +20h Default Value: 00000000h 13.11.4 RO 32-bit Bit Description 31:0 GPI Level (GPILVL) -- RO. BIOS or software read returns the value of the CxGPI received over the GSX channel. GPILVL[y] corresponds to CxGPI[y] where y falls within [31:0] range. CGPILVL[0] contains the first bit being serially shifted in during an atomic input serialization process. Hardware serialization process shifts in each bit of CxGPI value in ascending order from [bit 0] to [((NIN*8)-1)'s MSB bit]. GSX_CxGPILVL_DW1 -- GSX Input Level Register DW1 Offset Address: GSXBAR +24h Default Value: 00000000h Bit 31:0 13.11.5 Attribute: Size: Attribute: Size: RO 32-bit Description GPI Level (GPILVL_DW1) -- RO. BIOS or software read returns the value of the CxGPI received over the GSX channel. GPILVL[y] corresponds to CxGPI[y] where y falls within [63:32] range. GSX_CxGPOLVL -- GSX Output Level Register DW0 Offset Address: GSXBAR +30h Default Value: 00000000h Attribute: Size: R/W 32-bit Bit Description 31:0 GPO Level (GPOLVL) -- R/W. BIOS or software writes to this field to program the value of each output bit that will be sent in the serialization process. GPOLVL[y] corresponds to CxGPO[y] where y within CxGPO[31:0] range. GPOLVL[0] is the last bit in this register to be shifted out serially. Hardware serialization process shifts out each bit of CxGPOLVL_DW1 & CxGPOLVL in descending order from [((NOUT*8)-1)'s MSB bit] to [bit 0]. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 485 LPC Interface Bridge Registers (D31:F0) 13.11.6 GSX_CxGPOLVL_DW1 -- GSX Output Level Register DW1 Offset Address: GSXBAR +34h Default Value: 00000000h 13.11.7 Attribute: Size: R/W 32-bit Bit Description 31:0 GPO Level (GPOLVL_DW1) -- R/W. BIOS or software writes to this field to program the value of each output bit that will be sent in the serialization process. GPOLVL[y] corresponds to CxGPO[y] where y within CxGPO[63:32] range. GSX_CxCMD -- GSX Command Register Offset Address: GSXBAR +40h Default Value: 00000000h Bit 31:4 3 Attribute: Size: R/W, RO 32-bit Description Reserved. Input and Output Expander Reset Sequence (IOERST) -- R/W. Software writes `1' to this bit to cause a reset sequence that brings both input and output expander into a default state. Serialization process will be able to begin at default bit position again. Note: This bit is cleared once the above reset sequence is completed. 2 Serialization Running (RUN) -- RO. 0 = Serialization is complete. 1 = Serialization is in progress. Note: When software clears the ST bit, software shall poll on RUN bit to be `0' before software can write `1' to ST bit again. 1 Busy (BSY) -- RO. Software reads this field to determine if the serialization of most recently updated GPOLVL_DW1 and/or GPOLVL content has been completely serialized out on the GSX. Hardware will automatically clear the bit to`0' after all of the newly written value of GPOLVL_DW1 and/or GPOLVL bits have been serialized out at least once. 0 Start (ST) -- R/W. 0 = Stop serialization process. 1 = Start serialization process. Notes: 1. Software can only write this bit to `1' when Busy (BSY) status bit is cleared and CxCAP register is programmed. If software write this bit to `0', serialization process will stop at an atomic boundary. 2. 3. Clearing Start (ST) bit does not cause GSXSRESET# to be asserted. 486 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) 14 SATA Controller Registers (D31:F2) 14.1 PCI Configuration Registers (SATA-D31:F2) Note: Address locations that are not shown should be treated as Reserved. All of the SATA registers are in the core well. None of the registers can be locked. Table 14-1. SATA Controller PCI Register Address Map (SATA-D31:F2) (Sheet 1 of 2) Offset Mnemonic 00h-01h VID Register Name Default Type Vendor Identification 8086h RO Device Identification See register description RO 02h-03h DID 04h-05h PCICMD PCI Command 0000h R/W, RO 06h-07h PCISTS PCI Status 02B0h R/WC, RO 08h RID Revision Identification See register description RO 09h PI Programming Interface See register description See register description 0Ah SCC Sub Class Code See register description See register description 0Bh BCC Base Class Code 01h RO 0Dh PMLT 0Eh HTYPE Primary Master Latency Timer 00h RO Header Type 00h RO 10h-13h PCMD_BAR 14h-17h PCNL_BAR Primary Command Block Base Address 00000001h R/W, RO Primary Control Block Base Address 00000001h R/W, RO 18h-1Bh 1Ch-1Fh SCMD_BAR Secondary Command Block Base Address 00000001h R/W, RO SCNL_BAR Secondary Control Block Base Address 00000001h R/W, RO 20h-23h BAR 24h-27h ABAR / SIDPBA 2Ch-2Dh SVID 2Eh-2Fh SID Legacy Bus Master Base Address 00000001h R/W, RO AHCI Base Address / SATA Index Data Pair Base Address See register description See register description Subsystem Vendor Identification 0000h R/WO Subsystem Identification 0000h R/WO 34h CAP Capabilities Pointer 80h RO 3Ch INT_LN Interrupt Line 00h R/W 3Dh INT_PN Interrupt Pin See register description RO 40h-41h IDE_TIM Primary IDE Timing Register 0000h R/W 0000h R/W 00h R/W 42h-43h IDE_TIM Secondary IDE Timing Register 44h SIDETIM Slave IDE Timing 48h SDMA_CNT Synchronous DMA Control 00h R/W 4Ah-4Bh SDMA_TIM Synchronous DMA Timing 0000h R/W 54h-47h IDE_CONFIG IDE I/O Configuration 00000000h R/W PCI Power Management Capability ID See register description RO 70h-71h PID Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 487 SATA Controller Registers (D31:F2) Table 14-1. SATA Controller PCI Register Address Map (SATA-D31:F2) (Sheet 2 of 2) Offset Mnemonic 72h-73h PC 74h-75h Default Type PCI Power Management Capabilities See register description RO PMCS PCI Power Management Control and Status See register description R/W, RO, R/WC 80h-81h MSICI Message Signaled Interrupt Capability ID 7005h RO 82h-83h MSIMC Message Signaled Interrupt Message Control 0000h RO, R/W 84h-87h MSIMA Message Signaled Interrupt Message Address 00000000h RO, R/W 88h-89h MSIMD Message Signaled Interrupt Message Data 0000h R/W 90h MAP Address Map 0000h R/W 92h-93h PCS Port Control and Status 0000h R/W, RO 94h-97h SCLKCG SATA Clock Gating Control 00000000h R/W 9Ch-9Fh SGC SATA General Configuration 00000000h R/W, R/WO A8h-ABh SCAP0 SATA Capability Register 0 0010B012h RO, R/WO ACh-AFh SCAP1 SATA Capability Register 1 00000048h RO B0h-B1h FLRCID FLR Capability ID B2h-B3h FLRCLV B4h-B5h FLRCTRL C0h ATC C4h ATS D0h-D3h SP FLR Capability Length and Version FLR Control APM Trapping Control ATM Trapping Status R/WO, RO 0000h RO, R/W 00h R/W 00h R/WC 00000000h R/W BFCS BIST FIS Control/Status 00000000h R/W, R/WC E4h-E7h BFTD1 BIST FIS Transmit Data, DW1 00000000h R/W E8h-EBh BFTD2 BIST FIS Transmit Data, DW2 00000000h R/W The PCH SATA controller is not arbitrated as a PCI device, therefore it does not need a master latency timer. VID--Vendor Identification Register (SATA--D31:F2) Bit 15:0 Attribute: Size: Power Well: RO 16 bit Core Description Vendor ID -- RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h DID--Device Identification Register (SATA--D31:F2) Offset Address: 02h-03h Default Value: See bit description Lockable: No Bit 15:0 488 RO Scratch Pad Offset Address: 00h-01h Default Value: 8086h Lockable: No 14.1.2 0009h See register description E0h-E3h Note: 14.1.1 Register Name Attribute: Size: Power Well: RO 16 bit Core Description Device ID -- RO. This is a 16-bit value assigned to the PCH SATA controller. Note: The value of this field will change dependent upon the value of the MAP Register. See Section 14.1.34 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) 14.1.3 PCICMD--PCI Command Register (SATA-D31:F2) Address Offset: 04h-05h Default Value: 0000h Bit 15:11 10 9 14.1.4 RO, R/W 16 bits Description Reserved Interrupt Disable -- R/W. This disables pin-based INTx# interrupts. This bit has no effect on MSI operation. 0 = Internal INTx# messages are generated if there is an interrupt and MSI is not enabled. 1 = Internal INTx# messages will not be generated. Fast Back to Back Enable (FBE) -- RO. Reserved as 0. 8 SERR# Enable (SERR_EN) -- RO. Reserved as 0. 7 Wait Cycle Control (WCC) -- RO. Reserved as 0. 6 Parity Error Response (PER) -- R/W. 0 = Disabled. SATA controller will not generate PERR# when a data parity error is detected. 1 = Enabled. SATA controller will generate PERR# when a data parity error is detected. 5 VGA Palette Snoop (VPS) -- RO. Reserved as 0. 4 Postable Memory Write Enable (PMWE) -- RO. Reserved as 0. 3 Special Cycle Enable (SCE) -- RO. Reserved as 0. 2 Bus Master Enable (BME) -- R/W. This bit controls the SATA controller's ability to act as a master for data transfers. This bit does not impact the generation of completions for split transaction commands. 1 Memory Space Enable (MSE) -- R/W / RO. Controls access to the SATA controller's target memory space (for AHCI). This bit is RO `0' when not in AHCI/RAID modes. 0 I/O Space Enable (IOSE) -- R/W. This bit controls access to the I/O space registers. 0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as well as the Bus Master I/O registers. 1 = Enable. Note that the Base Address register for the Bus Master registers should be programmed before this bit is set. PCISTS -- PCI Status Register (SATA-D31:F2) Address Offset: 06h-07h Default Value: 02B0h Note: Attribute: Size: Attribute: Size: R/WC, RO 16 bits For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit Description 15 Detected Parity Error (DPE) -- R/WC. 0 = No parity error detected by SATA controller. 1 = SATA controller detects a parity error on its interface. 14 Signaled System Error (SSE) -- RO. Reserved as 0. 13 Received Master Abort (RMA) -- R/WC. 0 = Master abort Not generated. 1 = SATA controller, as a master, generated a master abort. 12 Reserved -- R/WC. 11 Signaled Target Abort (STA) -- RO. Reserved as 0. 10:9 DEVSEL# Timing Status (DEV_STS) -- RO. 01 = Hardwired; Controls the device select time for the SATA controller's PCI interface. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 489 SATA Controller Registers (D31:F2) Bit Description 8 Data Parity Error Detected (DPED) -- R/WC. For PCH, this bit can only be set on read completions received from the bus when there is a parity error. 0 = No data parity error received. 1 = SATA controller, as a master, either detects a parity error or sees the parity error line asserted, and the parity error response bit (bit 6 of the command register) is set. 7 Fast Back to Back Capable (FB2BC) -- RO. Reserved as 1. 6 Reserved. 5 66 MHz Capable (66MHZ_CAP) -- RO. Reserved as 1. 4 Capabilities List (CAP_LIST) -- RO. This bit indicates the presence of a capabilities list. The minimum requirement for the capabilities list must be PCI power management for the SATA controller. 3 Interrupt Status (INTS) -- RO. Reflects the state of INTx# messages, IRQ14 or IRQ15. 0 = Interrupt is cleared (independent of the state of Interrupt Disable bit in the command register [offset 04h]). 1 = Interrupt is to be asserted 2:0 14.1.5 Reserved RID--Revision Identification Register (SATA--D31:F2) Offset Address: 08h Default Value: See bit description Attribute: Size: Bit 7:0 RO 8 bits Description (R) Revision ID -- RO. Refer to the Intel C600 Series Chipset and Intel(R) X79 Express Chipset Specification Update for the value of the Revision ID Register 14.1.6 PI--Programming Interface Register (SATA-D31:F2) 14.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h Address Offset: 09h Default Value: 8Ah Bit 7 6:4 490 Attribute: Size: R/W, RO 8 bits Description This read-only bit is a 1 to indicate that the PCH supports bus master operation Reserved. Will always return 0. 3 Secondary Mode Native Capable (SNC) -- RO. Hardwired to `1' to indicate secondary controller supports both legacy and native modes. 2 Secondary Mode Native Enable (SNE) -- R/W. Determines the mode that the secondary channel is operating in. 0 = Secondary controller operating in legacy (compatibility) mode 1 = Secondary controller operating in native PCI mode. When MAP.MV (D31:F2:Offset 90:bits 1:0) is any value other than 00b, this bit is read-only (RO). When MAP.MV is 00b, this bit is read/write (R/W). If this bit is set by software, then the PNE bit (bit 0 of this register) must also be set by software. While in theory these bits can be programmed separately, such a configuration is not supported by hardware. 1 Primary Mode Native Capable (PNC) -- RO. Hardwired to `1' to indicate primary controller supports both legacy and native modes. 0 Primary Mode Native Enable (PNE) -- R/W. Determines the mode that the primary channel is operating in. 0 = Primary controller operating in legacy (compatibility) mode. 1 = Primary controller operating in native PCI mode. If this bit is set by software, then the SNE bit (bit 2 of this register) must also be set by software simultaneously. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) 14.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h Address Offset: 09h Default Value: 00h Attribute: Size: Bit 7:0 14.1.6.3 Description Interface (IF) -- RO. When configured as RAID, this register becomes read only 0. When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h Address Offset: 09h Default Value: 01h Attribute: Size: Bit 7:0 14.1.7 RO 8 bits RO 8 bits Description Interface (IF) -- RO. Indicates that the SATA Controller is an AHCI HBA that has a major revision of 1. SCC--Sub Class Code Register (SATA-D31:F2) Address Offset: 0Ah Default Value: See bit description Bit Attribute: Size: RO 8 bits Description Sub Class Code (SCC) This field specifies the sub-class code of the controller, per the table below: MAP.SMS (D31:F2:Offset 90h:bit 7:6) SCC Default Register Value 00b 01h (IDE Controller) 01b 06h (AHCI Controller) 10b 04h (RAID Controller) 7:0 14.1.8 BCC--Base Class Code Register (SATA-D31:F2) Address Offset: 0Bh Default Value: 01h Bit 7:0 Attribute: Size: RO 8 bits Description Base Class Code (BCC) -- RO. 01h = Mass storage device Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 491 SATA Controller Registers (D31:F2) 14.1.9 PMLT--Primary Master Latency Timer Register (SATA-D31:F2) Address Offset: 0Dh Default Value: 00h Bit 7:0 14.1.10 RO 8 bits Description Master Latency Timer Count (MLTC) -- RO. 00h = Hardwired. The SATA controller is implemented internally, and is not arbitrated as a PCI device, so it does not need a Master Latency Timer. HTYPE--Header Type (SATA-D31:F2) Address Offset: 0Eh Default Value: 00h Bit 7 6:0 14.1.11 Attribute: Size: Attribute: Size: RO 8 bits Description Multi-function Device (MFD) -- RO. Indicates this SATA controller is not part of a multifunction device. Header Layout (HL) -- RO. Indicates that the SATA controller uses a target device layout. PCMD_BAR--Primary Command Block Base Address Register (SATA-D31:F2) Address Offset: 10h-13h Default Value: 00000001h Attribute: Size: R/W, RO 32 bits . Bit 31:16 15:3 2:1 0 Note: 14.1.12 Description Reserved Base Address -- R/W. This field provides the base address of the I/O space (8 consecutive I/O locations). Reserved Resource Type Indicator (RTE) -- RO. Hardwired to 1 to indicate a request for I/O space. This 8-byte I/O space is used in native mode for the Primary Controller's Command Block. PCNL_BAR--Primary Control Block Base Address Register (SATA-D31:F2) Address Offset: 14h-17h Default Value: 00000001h Attribute: Size: R/W, RO 32 bits . Bit 31:16 15:2 Reserved Base Address -- R/W. This field provides the base address of the I/O space (4 consecutive I/O locations). 1 Reserved 0 Resource Type Indicator (RTE) -- RO. Hardwired to 1 to indicate a request for I/O space. Note: 492 Description This 4-byte I/O space is used in native mode for the Primary Controller's Control Block. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) 14.1.13 SCMD_BAR--Secondary Command Block Base Address Register (IDE D31:F2) Address Offset: 18h-1Bh Default Value: 00000001h Bit 31:16 15:3 2:1 0 Note: 14.1.14 R/W, RO 32 bits Description Reserved Base Address -- R/W. This field provides the base address of the I/O space (8 consecutive I/O locations). Reserved Resource Type Indicator (RTE) -- RO. Hardwired to 1 to indicate a request for I/O space. This 8-byte I/O space is used in native mode for the Secondary Controller's Command Block. SCNL_BAR--Secondary Control Block Base Address Register (IDE D31:F2) Address Offset: 1Ch-1Fh Default Value: 00000001h Bit 31:16 15:2 Attribute: Size: R/W, RO 32 bits Description Reserved Base Address -- R/W. This field provides the base address of the I/O space (4 consecutive I/O locations). 1 Reserved 0 Resource Type Indicator (RTE) -- RO. Hardwired to 1 to indicate a request for I/O space. Note: 14.1.15 Attribute: Size: This 4-byte I/O space is used in native mode for the Secondary Controller's Control Block. BAR -- Legacy Bus Master Base Address Register (SATA-D31:F2) Address Offset: 20h-23h Default Value: 00000001h Attribute: Size: R/W, RO 32 bits The Bus Master IDE interface function uses Base Address register 5 to request a 16byte I/O space to provide a software interface to the Bus Master functions. Only 12 bytes are actually used (6 bytes for primary, 6 bytes for secondary). Only bits [15:4] are used to decode the address. Bit 31:16 Description Reserved 15:5 Base Address -- R/W. This field provides the base address of the I/O space (16 consecutive I/O locations). 4 Base-- R/W / RO. When SCC is 01h, this bit will be R/W resulting in requesting 16B of I/O space. When SCC is not 01h, this bit will be Read Only 0, resulting in requesting 32B of I/O space. 3:1 0 Reserved Resource Type Indicator (RTE) -- RO. Hardwired to 1 to indicate a request for I/O space. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 493 SATA Controller Registers (D31:F2) 14.1.16 ABAR/SIDPBA1 -- AHCI Base Address Register/Serial ATA Index Data Pair Base Address (SATA-D31:F2) When the programming interface is not IDE (that is, SCC is not 01h), this register is named ABAR. When the programming interface is IDE, this register becomes SIDPBA. Note that hardware does not clear those BA bits when switching from IDE component to non-IDE component or vice versa. BIOS is responsible for clearing those bits to 0 since the number of writable bits changes after component switching (as indicated by a change in SCC). In the case, this register will then have to be re-programmed to a proper value. 14.1.16.1 When SCC is not 01h When the programming interface is not IDE, the register represents a memory BAR allocating space for the AHCI memory registers defined in Section 14.4. Address Offset: 24-27h Default Value: 00000000h Bit 31:11 10:4 3 2:1 0 Note: 1. 14.1.16.2 Attribute: Size: R/W, RO 32 bits Description Base Address (BA) -- R/W. Base address of register memory space (aligned to 2 KB) Reserved Prefetchable (PF) -- RO. Indicates that this range is not pre-fetchable Type (TP) -- RO. Indicates that this range can be mapped anywhere in 32-bit address space. Resource Type Indicator (RTE) -- RO. Hardwired to 0 to indicate a request for register memory space. The ABAR register must be set to a value of 0001_0000h or greater. When SCC is 01h When the programming interface is IDE, the register becomes an I/O BAR allocating 16 bytes of I/O space for the I/O-mapped registers defined in Section 14.2. Note that although 16 bytes of locations are allocated, only 8 bytes are used to as SINDX and SDATA registers; with the remaining 8 bytes preserved for future enhancement. Address Offset: 24h-27h Default Value: 00000001h Bit 31:16 15:4 3:1 0 494 Attribute: Size: R/WO 32 bits Description Reserved Base Address (BA) -- R/W. Base address of the I/O space. Reserved Resource Type Indicator (RTE) -- RO. Indicates a request for I/O space. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) 14.1.17 SVID--Subsystem Vendor Identification Register (SATA-D31:F2) Address Offset: 2Ch-2Dh Default Value: 0000h Lockable: No Function Level Reset: No Bit 15:0 14.1.18 Subsystem Vendor ID (SVID) -- R/WO. Value is written by BIOS. No hardware action taken on this value. SID--Subsystem Identification Register (SATA-D31:F2) R/WO 16 bits Core Description 15:0 Subsystem ID (SID) -- R/WO. Value is written by BIOS. No hardware action taken on this value. CAP--Capabilities Pointer Register (SATA-D31:F2) Attribute: Size: RO 8 bits Bit Description 7:0 Capabilities Pointer (CAP_PTR) -- RO. Indicates that the first capability pointer offset is 80h. This value changes to 70h if the Sub Class Code (SCC) (Dev 31:F2:0Ah) is configure as IDE mode (value of 01). INT_LN--Interrupt Line Register (SATA-D31:F2) Address Offset: 3Ch Default Value: 00h Function Level Reset:No Bit 7:0 14.1.21 Attribute: Size: Power Well: Bit Address Offset: 34h Default Value: 80h 14.1.20 R/WO 16 bits Core Description Address Offset: 2Eh-2Fh Default Value: 0000h Lockable: No Function Level Reset: No 14.1.19 Attribute: Size: Power Well: Attribute: Size: R/W 8 bits Description Interrupt Line -- R/W. This field is used to communicate to software the interrupt line that the interrupt pin is connected to. Interrupt Line register is not reset by FLR INT_PN--Interrupt Pin Register (SATA-D31:F2) Address Offset: 3Dh Default Value: See Register Description Bit 7:0 Attribute: Size: RO 8 bits Description Interrupt Pin -- RO. This reflects the value of D31IP.SIP (Chipset Config Registers:Offset 3100h:bits 11:8). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 495 SATA Controller Registers (D31:F2) 14.1.22 IDE_TIM -- IDE Timing Register (SATA-D31:F2) Address Offset: Primary: 40h-41h Secondary: 42h-43h Default Value: 0000h Attribute: R/W Size: 16 bits Bits 14:12 and 9:0 of this register are R/W to maintain software compatibility. These bits have no effect on hardware. Bit 15 Description IDE Decode Enable (IDE) -- R/W. Individually enable/disable the Primary or Secondary decode. 0 = Disable. 1 = Enables the PCH to decode the associated Command Blocks (1F0-1F7h for primary, 170-177h for secondary, or their native mode BAR equivalents) and Control Block (3F6h for primary, 376h for secondary, or their native mode BAR equivalents). This bit effects the IDE decode ranges for both legacy and native-Mode decoding. 14:12 IDE_TIM Field 2 -- R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. 11:10 Reserved 9:0 14.1.23 IDE_TIM Field 1 -- R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. SIDETIM--Slave IDE Timing Register (SATA-D31:F2) Address Offset: 44h Default Value: 00h Note: 7:0 Description SIDETIM Field 1 -- R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. SDMA_CNT--Synchronous DMA Control Register (SATA-D31:F2) Address Offset: 48h Default Value: 00h Note: Attribute: Size: R/W 8 bits This register is R/W to maintain software compatibility. These bits have no effect on hardware. Bit 496 R/W 8 bits This register is R/W to maintain software compatibility. These bits have no effect on hardware. Bit 14.1.24 Attribute: Size: Description 7:4 Reserved 3:0 SDMA_CNT Field 1 -- R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) 14.1.25 SDMA_TIM--Synchronous DMA Timing Register (SATA-D31:F2) Address Offset: 4Ah-4Bh Default Value: 0000h Note: Description 15:14 Reserved 13:12 SDMA_TIM Field 4-- R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. 11:10 Reserved 9:8 SDMA_TIM Field 3-- R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. 7:6 Reserved 5:4 SDMA_TIM Field 2-- R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. 3:2 Reserved 1:0 SDMA_TIM Field 1 -- R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. IDE_CONFIG--IDE I/O Configuration Register (SATA-D31:F2) Address Offset: 54h-57h Default Value: 00000000h Note: R/W 16 bits This register is R/W to maintain software compatibility. These bits have no effect on hardware. Bit 14.1.26 Attribute: Size: Attribute: Size: R/W 32 bits This register is R/W to maintain software compatibility. These bits have no effect on hardware. Bit Description 31:24 Reserved 23:12 IDE_CONFIG Field 2 -- R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. 11:8 7:0 Reserved IDE_CONFIG Field 1 -- R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 497 SATA Controller Registers (D31:F2) 14.1.27 PID--PCI Power Management Capability Identification Register (SATA-D31:F2) Address Offset: 70h-71h Default Value: See Register Description Bits 15:8 7:0 14.1.28 Attribute: Size: RO 16 bits Description Next Capability (NEXT) -- RO. B0h -- if SCC = 01h (IDE mode) indicating next item is FLR capability pointer. A8h -- for all other values of SCC to point to the next capability structure. Capability ID (CID) -- RO. Hardwired to 01h. Indicates that this pointer is a PCI power management. PC--PCI Power Management Capabilities Register (SATA-D31:F2) Address Offset: 72h-73h Default Value: See Register Description Attribute: Size: RO 16 bits f Bits 15:11 PME Support (PME_SUP) -- RO. 00000 = If SCC = 01h, indicates no PME support in IDE mode. 01000 = If SCC is not 01h, in a non-IDE mode, indicates PME# can be generated from the D3HOT state in the SATA host controller. 10 D2 Support (D2_SUP) -- RO. Hardwired to 0. The D2 state is not supported 9 D1 Support (D1_SUP) -- RO. Hardwired to 0. The D1 state is not supported 8:6 Auxiliary Current (AUX_CUR) -- RO. PME# from D3COLD state is not supported, therefore this field is 000b. 5 Device Specific Initialization (DSI) -- RO. Hardwired to 0 to indicate that no device-specific initialization is required. 4 Reserved 3 PME Clock (PME_CLK) -- RO. Hardwired to 0 to indicate that PCI clock is not required to generate PME#. 2:0 498 Description Version (VER) -- RO. Hardwired to 011 to indicates support for Revision 1.2 of the PCI Power Management Specification. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) 14.1.29 PMCS--PCI Power Management Control and Status Register (SATA-D31:F2) Address Offset: 74h-75h Default Value: 0008h Function Level Reset: No (Bits 8 and 15) Bits 15 14:9 8 7:4 Description PME Status (PMES) -- R/WC. Bit is set when a PME event is to be requested, and if this bit and PMEE is set, a PME# will be generated from the SATA controller Note: Whenever SCC = 01h, hardware will automatically change the attribute of this bit to RO `0'. Software is advised to clear PMEE and PMES together prior to changing SCC thru MAP.SMS. This bit is not reset by Function Level Reset. Reserved PME Enable (PMEE) -- R/W. When set, the SATA controller generates PME# form D3HOT on a wake event. Note: Whenever SCCSCC = 01h, hardware will automatically change the attribute of this bit to RO `0'. Software is advised to clear PMEE and PMES together prior to changing SCC thru MAP.SMS. This bit is not reset by Function Level Reset. Reserved 3 2 Reserved Power State (PS) -- R/W. These bits are used both to determine the current power state of the SATA controller and to set a new power state. 00 = D0 state 11 = D3HOT state When in the D3HOT state, the controller's configuration space is available, but the I/O and memory spaces are not. Additionally, interrupts are blocked. MSICI--Message Signaled Interrupt Capability Identification (SATA-D31:F2) Address Offset: 80h-81h Default Value: 7005h Note: R/W, R/WC 16 bits No Soft Reset (NSFRST) -- RO. These bits are used to indicate whether devices transitioning from D3HOT state to D0 state will perform an internal reset. 0 = Device transitioning from D3HOT state to D0 state perform an internal reset. 1 = Device transitioning from D3HOT state to D0 state do not perform an internal reset. Configuration content is preserved. Upon transition from the D3HOT state to D0 state initialized state, no additional operating system intervention is required to preserve configuration context beyond writing to the PowerState bits. Regardless of this bit, the controller transition from D3HOT state to D0 state by a system or bus segment reset will return to the state D0 uninitialized with only PME context preserved if PME is supported and enabled. 1:0 14.1.30 Attribute: Size: Attribute: Size: RO 16 bits There is no support for MSI when the software is operating in legacy (IDE) mode when AHCI is not enabled. Prior to switching from AHCI to IDE mode, software must make sure that MSI is disabled. Bits 15:8 7:0 Description Next Pointer (NEXT) -- RO. Indicates the next item in the list is the PCI power management pointer. Capability ID (CID) -- RO. Capabilities ID indicates MSI. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 499 SATA Controller Registers (D31:F2) 14.1.31 MSIMC--Message Signaled Interrupt Message Control (SATA-D31:F2) Address Offset: 82h-83h Default Value: 0000h Note: Attribute: Size: R/W, RO 16 bits There is no support for MSI when the software is operating in legacy (IDE) mode when AHCI is not enabled. Prior to switching from AHCI to IDE mode, software must make sure that MSI is disabled. Bits 15:8 7 Description Reserved 64 Bit Address Capable (C64) -- RO. Capable of generating a 32-bit message only. Multiple Message Enable (MME) -- RO. = 000 (and MSIE is set), a single MSI message will be generated for all SATA ports, and bits [15:0] of the message vector will be driven from MD[15:0]. For 6 port components: MME Value Driven on MSI Memory Write Bit[2] Bit[1] Bit[0] MD[2] MD[1] MD[0] Bits[15:3] 000, 001, 010 011 MD[15:3] MD[15:3] Port Port Port Port Port Port 0: 1: 2: 3: 4: 5: 0 0 0 0 1 1 Port Port Port Port Port Port 0: 1: 2: 3: 4: 5: 0 0 1 1 0 0 Port Port Port Port Port Port 0: 1: 2: 3: 4: 5: 0 1 0 1 0 1 6:4 MME Value Driven on MSI Memory Write Bit[2] Bit[1] Bit[0] MD[2] MD[1] MD[0] Bits[15:3] 000, 001, 010 MD[15:3] 011 MD[15:3] Port Port Port Port 0: 1: 4: 5: 0 0 1 1 Port Port Port Port 0: 1: 2: 3: 0 0 0 0 Port Port Port Port 0: 1: 2: 3: 0 1 0 1 All other MME values are reserved. If this field is set to one of these reserved values, the results are undefined. Note: The CCC interrupt is generated on unimplemented port (AHCI PI register bit equal to 0). If CCC interrupt is disabled, no MSI shall be generated for the port dedicated to the CCC interrupt. When CCC interrupt occurs, MD[2:0] is dependant on CCC_CTL.INT (in addition to MME). 3:1 Multiple Message Capable (MMC) -- RO. MMC is not supported. MSI Enable (MSIE) -- R/W /RO. If set, MSI is enabled and traditional interrupt pins are not used to generate interrupts. This bit is R/W when SC.SCC is not 01h and is read-only `0' when SCC is 01h. Note that CMD.ID bit has no effect on MSI. 0 Note: 500 Software must clear this bit to `0' to disable MSI first before changing the number of messages allocated in the MMC field. Software must also make sure this bit is cleared to `0' when operating in legacy mode (when GHC.AE = 0). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) 14.1.32 MSIMA-- Message Signaled Interrupt Message Address (SATA-D31:F2) Address Offset: 84h-87h Default Value: 00000000h Note: 31:2 1:0 Description Address (ADDR) -- R/W. Lower 32 bits of the system specified message address, always DWORD aligned. Reserved MSIMD--Message Signaled Interrupt Message Data (SATA-D31:F2) Address Offset: 88h-89h Default Value: 0000h Note: R/W 32 bits There is no support for MSI when the software is operating in legacy (IDE) mode when AHCI is not enabled. Prior to switching from AHCI to IDE mode, software must make sure that MSI is disabled. Bits 14.1.33 Attribute: Size: Attribute: Size: R/W 16 bits There is no support for MSI when the software is operating in legacy (IDE) mode when AHCI is not enabled. Prior to switching from AHCI to IDE mode, software must make sure that MSI is disabled. Bits Description 15:0 Data (DATA) -- R/W. This 16-bit field is programmed by system software if MSI is enabled. Its content is driven onto the lower word of the data bus of the MSI memory write transaction. Note that when the MME field is set to `001' or `010', bit [0] and bits [1:0] respectively of the MSI memory write transaction will be driven based on the source of the interrupt rather than from MD[2:0]. See the description of the MME field. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 501 SATA Controller Registers (D31:F2) 14.1.34 MAP--Address Map Register (SATA-D31:F2) Address Offset: 90h Attribute: Default Value: 0000h Size: Function Level Reset: No (Bits 7:5 and 13:8 only) Bits R/W, R/WO 16 bits Description 15:8 Reserved 13:8 Reserved SATA Mode Select (SMS) -- R/W. SW programs these bits to control the mode in which the SATA Controller should operate: 00b = IDE mode 01b = AHCI mode 10b = RAID mode 11b = Reserved NOTES: 7:6 1. 2. The SATA Function Device ID will change based on the value of this register. When switching from AHCI or RAID mode to IDE mode, a 2 port SATA controller (Device 31, Function 5) will be enabled. 3. AHCI mode may only be selected when MV = 00 4. RAID mode may only be selected when MV = 00 5. Programming these bits with values that are invalid (such as, selecting RAID when in combined mode) will result in indeterministic behavior by the HW 6. SW shall not manipulate SMS during runtime operation; that is, the OS will not do this. The BIOS may choose to switch from one mode to another during POST. These bits are not reset by Function Level Reset. SATA Port-to-Controller Configuration (SC) -- R/W. This bit changes the number of SATA ports available within each SATA Controller. 5 0 = Up to 4 SATA ports are available for Controller 1 (Device 31 Function 2) with ports [3:0] and up to 2 SATA ports are available for Controller 2 (Device 31 Function 5) with ports [5:4]. 1 = Up to 6 SATA ports are available for Controller 1 (Device 31 Function 2) with ports [5:0] and no SATA ports are available for Controller 2 (Device 31 Function 5). This bit should be set to 1 in AHCI/RAID mode. This bit is not reset by Function Level Reset. 4:0 502 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) 14.1.35 PCS--Port Control and Status Register (SATA-D31:F2) Address Offset: 92h-93h Default Value: 0000h Function Level Reset: No Attribute: Size: R/W, RO 16 bits By default, the SATA ports are set to the disabled state (bits [5:0] = `0'). When enabled by software, the ports can transition between the on, partial, and slumber states and can detect devices. When disabled, the port is in the "off" state and cannot detect any devices. If an AHCI-aware or RAID enabled operating system is being booted, then system BIOS shall insure that all supported SATA ports are enabled prior to passing control to the OS. Once the AHCI aware OS is booted it becomes the enabling/disabling policy owner for the individual SATA ports. This is accomplished by manipulating a port's PxSCTL and PxCMD fields. Because an AHCI or RAID aware OS will typically not have knowledge of the PxE bits and because the PxE bits act as master on/off switches for the ports, preboot software must insure that these bits are set to `1' prior to booting the OS, regardless as to whether or not a device is currently on the port. Bits Description 15 OOB Retry Mode (ORM) -- R/W. 0 = The SATA controller will not retry after an OOB failure 1 = The SATA controller will continue to retry after an OOB failure until successful (infinite retry) 14 Reserved. 13 Port 5 Present (P5P) -- RO. The status of this bit may change at any time. This bit is cleared when the port is disabled using P5E. This bit is not cleared upon surprise removal of a device. 0 = No device detected. 1 = The presence of a device on Port 5 has been detected. 12 Port 4 Present (P4P) -- RO. The status of this bit may change at any time. This bit is cleared when the port is disabled using P4E. This bit is not cleared upon surprise removal of a device. 0 = No device detected. 1 = The presence of a device on Port 4 has been detected. 11 Port 3 Present (P3P) -- RO. The status of this bit may change at any time. This bit is cleared when the port is disabled using P3E. This bit is not cleared upon surprise removal of a device. 0 = No device detected. 1 = The presence of a device on Port 3 has been detected. 10 Port 2 Present (P2P) -- RO. The status of this bit may change at any time. This bit is cleared when the port is disabled using P2E. This bit is not cleared upon surprise removal of a device. 0 = No device detected. 1 = The presence of a device on Port 2 has been detected. 9 Port 1 Present (P1P) -- RO. The status of this bit may change at any time. This bit is cleared when the port is disabled using P1E. This bit is not cleared upon surprise removal of a device. 0 = No device detected. 1 = The presence of a device on Port 1 has been detected. 8 Port 0 Present (P0P) -- RO. The status of this bit may change at any time. This bit is cleared when the port is disabled using P0E. This bit is not cleared upon surprise removal of a device. 0 = No device detected. 1 = The presence of a device on Port 0 has been detected. 7:6 5 Reserved Port 5 Enabled (P5E) -- R/W R/O. 0 = Disabled. The port is in the `off' state and cannot detect any devices. 1 = Enabled. The port can transition between the on, partial, and slumber states and can detect devices. Note: This bit takes precedence over P5CMD.SUD (offset ABAR+398h:bit 1) If MAP.SC is `0', if SCC is `01h' this bit will be read only `0' or if MAP.SPD[5] is `1'. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 503 SATA Controller Registers (D31:F2) Bits 14.1.36 Description 4 Port 4 Enabled (P4E) -- R/W R/O. 0 = Disabled. The port is in the `off' state and cannot detect any devices. 1 = Enabled. The port can transition between the on, partial, and slumber states and can detect devices. Note: This bit takes precedence over P4CMD.SUD (offset ABAR+318h:bit 1) If MAP.SC is `0', if SCC is `01h' this bit will be read only `0' or if MAP.SPD[4] is `1'. 3 Port 3 Enabled (P3E) -- R/W R/O. 0 = Disabled. The port is in the `off' state and cannot detect any devices. 1 = Enabled. The port can transition between the on, partial, and slumber states and can detect devices. Note: This bit takes precedence over P3CMD.SUD (offset ABAR+298h:bit 1). When MAP.SPD[3] is `1' this is reserved and is read-only 0. 2 Port 2 Enabled (P2E) -- R/W R/O. 0 = Disabled. The port is in the `off' state and cannot detect any devices. 1 = Enabled. The port can transition between the on, partial, and slumber states and can detect devices. Note: This bit takes precedence over P2CMD.SUD (offset ABAR+218h:bit 1). When MAP.SPD[2] is `1' this is reserved and is read-only 0. 1 Port 1 Enabled (P1E) -- R/W R/O. 0 = Disabled. The port is in the `off' state and cannot detect any devices. 1 = Enabled. The port can transition between the on, partial, and slumber states and can detect devices. Note: This bit takes precedence over P1CMD.SUD (offset ABAR+198h:bit 1). When MAP.SPD[1] is `1' this is reserved and is read-only 0. 0 Port 0 Enabled (P0E) -- R/W R/O. 0 = Disabled. The port is in the `off' state and cannot detect any devices. 1 = Enabled. The port can transition between the on, partial, and slumber states and can detect devices. Note: This bit takes precedence over P0CMD.SUD (offset ABAR+118h:bit 1). When MAP.SPD[0] is `1' this is reserved and is read-only 0. SCLKCG--SATA Clock Gating Control Register Address Offset: 94h-97h Default Value: 00000000h Attribute: Size: R/W 32 bits . Bit 31:30 Reserved. 29:24 Port Clock Disable (PCD) -- R/W 0 = All clocks to the associated port logic will operate normally. 1 = The backbone clock driven to the associated port logic is gated and will not toggle. Bit 29: Port 5 Bit 28: Port 4 Bit 27: Port 3 BIt 26: Port 2 Bit 25: Port 1 Bit 24: Port 0 If a port is not available, software shall set the corresponding bit to 1. Software can also set the corresponding bits to 1 on ports that are disabled. Software cannot set the PCD [port x]='1' if the corresponding PCS.PxE='1' in either Dev31Func2 or Dev31Func5 (dual controller IDE mode). 23:9 8:0 504 Description Reserved. SCLKCG Field 1 -- R/W. BIOS must program these bits to 183h. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) 14.1.37 SGC--SATA General Configuration Register Address Offset: 9Ch-9Fh Default Value: 00000000h Function Level Reset: No Bit 31:10 Attribute: Size: R/W, R/WO 32 bits Description Reserved 9 BIOS must program this bit to 1b. 8 Reserved 7 (PCH nonRaid Capable SKUs Only) Reserved 7 (PCH Raid Capable SKUs Only) Alternate ID Enable (AIE) -- R/WO. 0 = When in RAID mode the SATA Controller located at Device 31: Function 2 will report the following Device ID 2826h and the Microsoft Windows Vista* and Windows* 7 in-box version of the Intel(R) Rapid Storage Technology will load on the platform. 1 = When in RAID mode the SATA Controller located at Device 31: Function 2 will report the Device ID 1D04h for RAID 0/1/5/10, to prevent the Microsoft Windows Vista or Windows 7 in-box version of the Intel(R) Rapid Storage Technology from loading on the platform and will require the user to perform an `F6' installation of the appropriate Intel(R) Rapid Storage Technology. Note: This field is applicable when the AHCI is configured for RAID mode of operation. It has no impact for AHCI and IDE modes of operation. BIOS is recommended to program this bit prior to programming the MAP.SMS field to reflect RAID. This field is reset by PLTRST#. BIOS is required to reprogram the value of this bit after resuming from S3, S4 and S5. 6:2 SATA Traffic Monitor-- R/W. 00000b = Disable. 00011b = Enable. SATA Traffic Monitor allows for aggressive C2 Pop down by monitoring SATA bus mastering activity. When enabled, BIOS must ensure bit 3 and bit 4 of Cx_STATE_CNF (Cx State Configuration Register) are ones. Note: This field is reset by PLTRST# and BIOS is required to reprogram the value after resuming from S3-S5. All other bit combinations are Reserved. 1 Reserved 0 SATA4-port All Master Configuration Indicator (SATA4PMIND) -- RO. 0 = Normal configuration. 1 = Two IDE Controllers are implemented, each supporting two ports for a Primary Master and a Secondary Master. Note: When set, BIOS must ensure that bit 2 and bit 3 of the AHCI PI registers are zeros. BIOS must also make sure that Port 2 and Port 3 are disabled (using PCS configuration register) and the port clocks are gated (using SCLKCG configuration register). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 505 SATA Controller Registers (D31:F2) 14.1.37.1 SATACR0--SATA Capability Register 0 (SATA-D31:F2) Address Offset: A8h-ABh Default Value: 0010B012h Function Level Reset: No (Bits 15:8 only) Note: Description 31:24 Reserved 23:20 Major Revision (MAJREV) -- RO. Major revision number of the SATA Capability Pointer implemented. 19:16 Minor Revision (MINREV) -- RO. Minor revision number of the SATA Capability Pointer implemented. 15:8 7:0 Next Capability Pointer (NEXT) -- R/WO. Points to the next capability structure. These bits are not reset by Function Level Reset. Capability ID (CAP)-- RO: This value of 12h has been assigned by the PCI SIG to designate the SATA Capability Structure. SATACR1--SATA Capability Register 1 (SATA-D31:F2) Address Offset: ACh-AFh Default Value: 00000048h Note: Attribute: Size: RO 32 bits This register shall be read-only 0 when SCC is 01h. Bit 31:16 506 RO, R/WO 32 bits This register shall be read-only 0 when SCC is 01h. Bit 14.1.37.2 Attribute: Size: Description Reserved 15:4 BAR Offset (BAROFST) -- RO: Indicates the offset into the BAR where the Index/Data pair are located (in DWord granularity). The Index and Data I/O registers are located at offset 10h within the I/O space defined by LBAR. A value of 004h indicates offset 10h. 000h = 0h offset 001h = 4h offset 002h = 8h offset 003h = Bh offset 004h = 10h offset ... FFFh = 3FFFh offset (max 16KB) 3:0 BAR Location (BARLOC) -- RO: Indicates the absolute PCI Configuration Register address of the BAR containing the Index/Data pair (in DWord granularity). The Index and Data I/O registers reside within the space defined by LBAR in the SATA controller. A value of 8h indicates offset 20h, which is LBAR. 0000 - 0011b = reserved 0100b = 10h => BAR0 0101b = 14h => BAR1 0110b = 18h => BAR2 0111b = 1Ch => BAR3 1000b = 20h => LBAR 1001b = 24h => BAR5 1010 - 1110b = reserved 1111b = Index/Data pair in PCI Configuration space. This is not supported in the PCH. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) 14.1.38 FLRCID--FLR Capability ID (SATA-D31:F2) Address Offset: B0-B1h Default Value: 0009h Bit 15:8 7:0 14.1.39 Attribute: Size: RO 16 bits Description Next Capability Pointer -- RO. 00h indicates the final item in the capability list. Capability ID -- RO. The value of this field depends on the FLRCSSEL (RCBA+3410h:bit 12) bit. 13h = If PFLRCSSEL = 0 09h (Vendor Specific) = If PFLRCSSEL = 1 FLRCLV--FLR Capability Length and Version (SATA- D31:F2) Address Offset: B2-B3hAttribute: RO, R/WO Default Value: xx06hSize: 16 bits Function Level Reset: No (Bit 9:8 Only when FLRCSSEL = `0') When FLRCSSEL (RCBA+3410h:bit 12) = `0', this register is defined as follows: Bit 15:10 Description Reserved. 9 FLR Capability -- R/WO. 1 = Support for Function Level reset. This bit is not reset by the Function Level Reset. 8 TXP Capability -- R/WO. 1 = Support for Transactions Pending (TXP) bit. TXP must be supported if FLR is supported. 7:0 Vendor-Specific Capability ID -- RO. This field indicates the # of bytes of this Vendor Specific capability as required by the PCI specification. It has the value of 06h for the FLR capability. When FLRCSSEL = `1', this register is defined as follows: Bit Description 15:12 Vendor-Specific Capability ID -- RO. A value of 2h identifies this capability as the Function Level Reset (FLR). 11:8 7:0 14.1.40 Capability Version -- RO. This field indicates the version of the FLR capability. Vendor-Specific Capability ID -- RO. This field indicates the # of bytes of this Vendor Specific capability as required by the PCI specification. It has the value of 06h for the FLR capability. FLRC--FLR Control (SATA-D31:F2) Address Offset: B4-B5h Default Value: 0000h Bit 15:9 8 7:1 0 Attribute: Size: RO, R/W 16 bits Description Reserved. Transactions Pending (TXP) -- RO. 0 = Controller has received all non-posted requests. 1 = Controller has issued non-posted requests which has not been completed. Reserved. Initiate FLR -- R/W. Used to initiate FLR transition. A write of `1' indicates FLR transition. Since hardware must no t respond to any cycles till FLR completion the value read by software from this bit is `0'. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 507 SATA Controller Registers (D31:F2) 14.1.41 ATC--APM Trapping Control Register (SATA-D31:F2) Address Offset: C0h Default Value: 00h Function Level Reset:No Attribute: Size: R/W 8 bits . Bit 7:4 14.1.42 Description Reserved 3 Secondary Slave Trap (SST) -- R/W. Enables trapping and SMI# assertion on legacy I/O accesses to 170h-177h and 376h. The active device on the secondary interface must be device 1 for the trap and/or SMI# to occur. 2 Secondary Master Trap (SPT) -- R/W. Enables trapping and SMI# assertion on legacy I/O accesses to 170h-177h and 376h. The active device on the secondary interface must be device 0 for the trap and/or SMI# to occur. 1 Primary Slave Trap (PST) -- R/W. Enables trapping and SMI# assertion on legacy I/O accesses to 1F0h-1F7h and 3F6h. The active device on the primary interface must be device 1 for the trap and/ or SMI# to occur. 0 Primary Master Trap (PMT) -- R/W. Enables trapping and SMI# assertion on legacy I/O accesses to 1F0h-1F7h and 3F6h. The active device on the primary interface must be device 0 for the trap and/or SMI# to occur. ATS--APM Trapping Status Register (SATA-D31:F2) Address Offset: C4h Default Value: 00h Function Level Reset:No Attribute: Size: R/WC 8 bits . Bit 7:4 14.1.43 Description Reserved 3 Secondary Slave Trap (SST) -- R/WC. Indicates that a trap occurred to the secondary slave device. 2 Secondary Master Trap (SPT) -- R/WC. Indicates that a trap occurred to the secondary master device. 1 Primary Slave Trap (PST) -- R/WC. Indicates that a trap occurred to the primary slave device. 0 Primary Master Trap (PMT) -- R/WC. Indicates that a trap occurred to the primary master device. SP Scratch Pad Register (SATA-D31:F2) Address Offset: D0h Default Value: 00000000h Attribute: Size: R/W 32 bits . Bit 31:0 508 Description Data (DT) -- R/W. This is a read/write register that is available for software to use. No hardware action is taken on this register. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) 14.1.44 BFCS--BIST FIS Control/Status Register (SATA-D31:F2) Address Offset: E0h-E3h Default Value: 00000000h Bits 31:16 Attribute: Size: R/W, R/WC 32 bits Description Reserved 15 Port 5 BIST FIS Initiate (P5BFI) -- R/W. When a rising edge is detected on this bit field, the PCH initiates a BIST FIS to the device on Port 5, using the parameters specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS will only be initiated if a device on Port 5 is present and ready (not partial/slumber state). After a BIST FIS is successfully completed, software must disable and re-enable the port using the PxE bits at offset 92h prior to attempting additional BIST FISs or to return the PCH to a normal operational mode. If the BIST FIS fails to complete, as indicated by the BFF bit in the register, then software can clear then set the P5BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS eventually completes successfully. 14 Port 4 BIST FIS Initiate (P4BFI) -- R/W. When a rising edge is detected on this bit field, the PCH initiates a BIST FIS to the device on Port 4, using the parameters specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS will only be initiated if a device on Port 4 is present and ready (not partial/slumber state). After a BIST FIS is successfully completed, software must disable and re-enable the port using the PxE bits at offset 92h prior to attempting additional BIST FISs or to return the PCH to a normal operational mode. If the BIST FIS fails to complete, as indicated by the BFF bit in the register, then software can clear then set the P4BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS eventually completes successfully. 13 Port 3 BIST FIS Initiate (P3BFI) -- R/W. When a rising edge is detected on this bit field, the PCH initiates a BIST FIS to the device on Port 3, using the parameters specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS will only be initiated if a device on Port 3 is present and ready (not partial/slumber state). After a BIST FIS is successfully completed, software must disable and re-enable the port using the PxE bits at offset 92h prior to attempting additional BIST FISs or to return the PCH to a normal operational mode. If the BIST FIS fails to complete, as indicated by the BFF bit in the register, then software can clear then set the P3BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS eventually completes successfully. 12 Port 2 BIST FIS Initiate (P2BFI) -- R/W. When a rising edge is detected on this bit field, the PCH initiates a BIST FIS to the device on Port 2, using the parameters specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS will only be initiated if a device on Port 2 is present and ready (not partial/slumber state). After a BIST FIS is successfully completed, software must disable and re-enable the port using the PxE bits at offset 92h prior to attempting additional BIST FISes or to return the PCH to a normal operational mode. If the BIST FIS fails to complete, as indicated by the BFF bit in the register, then software can clear then set the P2BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS eventually completes successfully. 11 BIST FIS Successful (BFS) -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set any time a BIST FIS transmitted by PCH receives an R_OK completion status from the device. Note: 10 Note: 9 This bit must be cleared by software prior to initiating a BIST FIS. BIST FIS Failed (BFF) -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set any time a BIST FIS transmitted by PCH receives an R_ERR completion status from the device. This bit must be cleared by software prior to initiating a BIST FIS. Port 1 BIST FIS Initiate (P1BFI) -- R/W. When a rising edge is detected on this bit field, the PCH initiates a BIST FIS to the device on Port 1, using the parameters specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS will only be initiated if a device on Port 1 is present and ready (not partial/slumber state). After a BIST FIS is successfully completed, software must disable and re-enable the port using the PxE bits at offset 92h prior to attempting additional BIST FISes or to return the PCH to a normal operational mode. If the BIST FIS fails to complete, as indicated by the BFF bit in the register, then software can clear then set the P1BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS eventually completes successfully. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 509 SATA Controller Registers (D31:F2) 14.1.45 Bits Description 8 Port 0 BIST FIS Initiate (P0BFI) -- R/W. When a rising edge is detected on this bit field, the PCH initiates a BIST FIS to the device on Port 0, using the parameters specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS will only be initiated if a device on Port 0 is present and ready (not partial/slumber state). After a BIST FIS is successfully completed, software must disable and re-enable the port using the PxE bits at offset 92h prior to attempting additional BIST FISes or to return the PCH to a normal operational mode. If the BIST FIS fails to complete, as indicated by the BFF bit in the register, then software can clear then set the P0BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS eventually completes successfully. 7:2 BIST FIS Parameters (BFP) -- R/W. These 6 bits form the contents of the upper 6 bits of the BIST FIS Pattern Definition in any BIST FIS transmitted by the PCH. This field is not port specific -- its contents will be used for any BIST FIS initiated on port 0, port 1, port 2 or port 3. The specific bit definitions are: Bit 7: T - Far End Transmit mode Bit 6: A - Align Bypass mode Bit 5: S - Bypass Scrambling Bit 4: L - Far End Retimed Loopback Bit 3: F - Far End Analog Loopback Bit 2: P - Primitive bit for use with Transmit mode 1:0 Reserved BFTD1--BIST FIS Transmit Data1 Register (SATA-D31:F2) Address Offset: E4h-E7h Default Value: 00000000h 14.1.46 R/W 32 bits Bits Description 31:0 BIST FIS Transmit Data 1 -- R/W. The data programmed into this register will form the contents of the second DWord of any BIST FIS initiated by the PCH. This register is not port specific -- its contents will be used for BIST FIS initiated on any port. Although the 2nd and 3rd DWs of the BIST FIS are only meaningful when the "T" bit of the BIST FIS is set to indicate "Far-End Transmit mode", this register's contents will be transmitted as the BIST FIS 2nd DW regardless of whether or not the "T" bit is indicated in the BFCS register (D31:F2:E0h). BFTD2--BIST FIS Transmit Data2 Register (SATA-D31:F2) Address Offset: E8h-EBh Default Value: 00000000h 510 Attribute: Size: Attribute: Size: R/W 32 bits Bits Description 31:0 BIST FIS Transmit Data 2 -- R/W. The data programmed into this register will form the contents of the third DWord of any BIST FIS initiated by the PCH. This register is not port specific -- its contents will be used for BIST FIS initiated on any port. Although the 2nd and 3rd DWs of the BIST FIS are only meaningful when the "T" bit of the BIST FIS is set to indicate "Far-End Transmit mode", this register's contents will be transmitted as the BIST FIS 3rd DW regardless of whether or not the "T" bit is indicated in the BFCS register (D31:F2:E0h). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) 14.2 Bus Master IDE I/O Registers (D31:F2) The bus master IDE function uses 16 bytes of I/O space, allocated using the BAR register, located in Device 31:Function 2 Configuration space, offset 20h. All bus master IDE I/O space registers can be accessed as byte, word, or DWord quantities. Reading reserved bits returns an indeterminate, inconsistent value, and writes to reserved bits have no affect (but should not be attempted). These registers are only used for legacy operation. Software must not use these registers when running AHCI. All I/O registers are reset by Function Level Reset. The description of the I/O registers address map is shown in Table 14-2. Table 14-2. Bus Master IDE I/O Register Address Map BAR+ Offset Mnemonic 00 BMICP 01 -- 02 BMISP 03 -- 04-07 BMIDP 08 BMICS 09 -- 0Ah BMISS 0Bh -- 0Ch-0Fh BMIDS 10h AIR 14h AIDR Register Command Register Primary Reserved Bus Master IDE Status Register Primary Reserved Bus Master IDE Descriptor Table Pointer Primary Command Register Secondary Reserved Bus Master IDE Status Register Secondary Reserved Default Type 00h R/W -- RO 00h R/W, R/WC, RO -- RO xxxxxxxxh R/W 00h R/W -- RO 00h R/W, R/WC, RO -- RO Bus Master IDE Descriptor Table Pointer Secondary xxxxxxxxh R/W AHCI Index Register 00000000h R/W, RO AHCI Index Data Register xxxxxxxxh R/W Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 511 SATA Controller Registers (D31:F2) 14.2.1 BMIC[P,S]--Bus Master IDE Command Register (D31:F2) Address Offset: Primary: BAR + 00h Secondary: BAR + 08h Default Value: 00h Bit 7:4 3 2:1 0 R/W Size: 8 bits Description Reserved. Returns 0. Read / Write Control (R/WC) -- R/W. This bit sets the direction of the bus master transfer. This bit must NOT be changed when the bus master function is active. 0 = Memory reads 1 = Memory writes Reserved. Returns 0. Start/Stop Bus Master (START) -- R/W. 0 = All state information is lost when this bit is cleared. Master mode operation cannot be stopped and then resumed. If this bit is reset while bus master operation is still active (that is, the Bus Master IDE Active bit (D31:F2:BAR + 02h, bit 0) of the Bus Master IDE Status register for that IDE channel is set) and the drive has not yet finished its data transfer (the Interrupt bit in the Bus Master IDE Status register for that IDE channel is not set), the bus master command is said to be aborted and data transferred from the drive may be discarded instead of being written to system memory. 1 = Enables bus master operation of the controller. Bus master operation does not actually start unless the Bus Master Enable bit (D31:F2:04h, bit 2) in PCI configuration space is also set. Bus master operation begins when this bit is detected changing from 0 to 1. The controller will transfer data between the IDE device and memory only when this bit is set. Master operation can be halted by writing a 0 to this bit. Note: 512 Attribute: This bit is intended to be cleared by software after the data transfer is completed, as indicated by either the Bus Master IDE Active bit being cleared or the Interrupt bit of the Bus Master IDE Status register for that IDE channel being set, or both. Hardware does not clear this bit automatically. If this bit is cleared to 0 prior to the DMA data transfer being initiated by the drive in a Device to memory data transfer, then the PCH will not send DMAT to terminate the data transfer. SW intervention (such as sending SRST) is required to reset. the interface in this condition. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) 14.2.2 BMIS[P,S]--Bus Master IDE Status Register (D31:F2) Address Offset: Primary: BAR + 02h Secondary: BAR + 0Ah Default Value: 00h R/W, R/WC, RO Size: 8 bits Bit Description 7 Simplex Only -- RO. 0 = Both bus master channels (primary and secondary) can be operated independently and can be used at the same time. 1 = Only one channel may be used at the same time. 6 Drive 1 DMA Capable -- R/W. 0 = Not Capable. 1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 1 for this channel is capable of DMA transfers, and that the controller has been initialized for optimum performance. The PCH does not use this bit. It is intended for systems that do not attach BMIDE to the PCI bus. 5 Drive 0 DMA Capable -- R/W. 0 = Not Capable 1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 0 for this channel is capable of DMA transfers, and that the controller has been initialized for optimum performance. The PCH does not use this bit. It is intended for systems that do not attach BMIDE to the PCI bus. 4:3 14.2.3 Attribute: Reserved. Returns 0. 2 Interrupt -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set when a device FIS is received with the `I' bit set, provided that software has not disabled interrupts using the IEN bit of the Device Control Register (see chapter 5 of the Serial ATA Specification, Revision 1.0a). 1 Error -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set when the controller encounters a target abort or master abort when transferring data on PCI. 0 Bus Master IDE Active (ACT) -- RO. 0 = This bit is cleared by the PCH when the last transfer for a region is performed, where EOT for that region is set in the region descriptor. It is also cleared by the PCH when the Start Bus Master bit (D31:F2:BAR+ 00h, bit 0) is cleared in the Command register. When this bit is read as a 0, all data transferred from the drive during the previous bus master command is visible in system memory, unless the bus master command was aborted. 1 = Set by the PCH when the Start bit is written to the Command register. BMID[P,S]--Bus Master IDE Descriptor Table Pointer Register (D31:F2) Address Offset: Primary: BAR + 04h-07h Attribute: Secondary: BAR + 0Ch-0Fh Default Value: All bits undefined Size: R/W 32 bits Bit Description 31:2 Address of Descriptor Table (ADDR) -- R/W. The bits in this field correspond to bits [31:2] of the memory location of the Physical Region Descriptor (PRD). The Descriptor Table must be Dwordaligned. The Descriptor Table must not cross a 64-K boundary in memory. 1:0 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 513 SATA Controller Registers (D31:F2) 14.2.4 AIR--AHCI Index Register (D31:F2) Address Offset: Primary: BAR + 10h Default Value: 00000000h Attribute: Size: R/W 32 bits This register is available only when SCC is not 01h. Bit 31:11 10:2 1:0 14.2.5 Description Reserved Index (INDEX)-- R/W: This Index register is used to select the Dword offset of the Memory Mapped AHCI register to be accessed. A Dword, Word or Byte access is specified by the active byte enables of the I/O access to the Data register. Reserved AIDR--AHCI Index Data Register (D31:F2) Address Offset: Primary: BAR + 14h Default Value: All bits undefined Attribute: Size: R/W 32 bits This register is available only when SCC is not 01h. 14.3 Bit Description 31:0 Data (DATA)-- R/W: This Data register is a "window" through which data is read or written to the AHCI memory mapped registers. A read or write to this Data register triggers a corresponding read or write to the memory mapped register pointed to by the Index register. The Index register must be setup prior to the read or write to this Data register. Note that a physical register is not actually implemented as the data is actually stored in the memory mapped registers. Since this is not a physical register, the "default" value is the same as the default value of the register pointed to by Index. Serial ATA Index/Data Pair Superset Registers All of these I/O registers are in the core well. They are exposed only when SCC is 01h (that is, IDE programming interface). These are Index/Data Pair registers that are used to access the SerialATA superset registers (SerialATA Status (PxSSTS), SerialATA Control (PxSCTL) and SerialATA Error (PxSERR)). The I/O space for these registers is allocated through SIDPBA. Locations with offset from 08h to 0Fh are reserved for future expansion. Software-write operations to the reserved locations will have no effect while software-read operations to the reserved locations will return 0. 514 Offset Mnemonic Register 00h-03h SINDEX Serial ATA Index Serial ATA Data 04h-07h SDATA 08h-0Ch -- Reserved 0Ch-0Fh -- Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) 14.3.1 SINDX - Serial ATA Index (D31:F2) Address Offset: SIDPBA + 00h Default Value: 00000000h Bit 31:16 14.3.2 Attribute: Size: R/W 32 bits Description Reserved 15.8 Port Index (PIDX) -- R/W: This Index field is used to specify the port of the SATA controller at which the port-specific SSTS, SCTL, and SERR registers are located. 00h = Primary Master (Port 0) 01h = Primary Slave (Port 2) 02h = Secondary Master (Port 1) 03h = Secondary Slave (Port 3) All other values are Reserved. 7:0 Register Index (RIDX) -- R/W: This index field is used to specify one out of three registers currently being indexed into. These three registers are the Serial ATA superset SStatus, SControl and SError memory registers and are port specific, hence for this SATA controller, there are four sets of these registers. Refer to Section 14.4.2.10, Section 14.4.2.11, and Section 14.4.2.12 for definitions of the SStatus, SControl and SError registers. 00h = SSTS 01h = SCTL 02h = SERR All other values are Reserved. SDATA - Serial ATA Data (D31:F2) Address Offset: SIDPBA + 04h Default Value: 00000000h Attribute: Size: R/W 32 bits Bit Description 31:0 Data (DATA) -- R/W: This Data register is a "window" through which data is read or written to from the register pointed to by the Serial ATA Index (SINDX) register above. Note that a physical register is not actually implemented as the data is actually stored in the memory mapped registers. Since this is not a physical register, the "default" value is the same as the default value of the register pointed to by SINDX.RIDX field. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 515 SATA Controller Registers (D31:F2) 14.3.2.1 PxSSTS--Serial ATA Status Register (D31:F2) Address Offset: Default Value: 00000000h Attribute: Size: RO 32 bits SDATA when SINDX.RIDX is 00h. This is a 32-bit register that conveys the current state of the interface and host. The PCH updates it continuously and asynchronously. When the PCH transmits a COMRESET to the device, this register is updated to its reset values. Bit 31:12 Description Reserved Interface Power Management (IPM) -- RO. Indicates the current interface state: Value 11:8 Description 0h Device not present or communication not established 1h Interface in active state 2h Interface in PARTIAL power management state 6h Interface in SLUMBER power management state All other values reserved. Current Interface Speed (SPD) -- RO. Indicates the negotiated interface communication speed. Value 7:4 Description 0h Device not present or communication not established 1h Generation 1 communication rate negotiated 2h Generation 2 communication rate negotiated 3h Generation 3communication rate negotiated All other values reserved. The PCH Supports Generation 1 communication rates (1.5 Gb/s) and Gen 2 rates (3.0 Gb/s) and Gen 3 rates (6.0Gb/s). Device Detection (DET) -- RO. Indicates the interface device detection and Phy state: Value 3:0 Description 0h No device detected and Phy communication not established 1h Device presence detected but Phy communication not established 3h Device presence detected and Phy communication established 4h Phy in offline mode as a result of the interface being disabled or running in a BIST loopback mode All other values reserved. 516 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) 14.3.2.2 PxSCTL -- Serial ATA Control Register (D31:F2) Address Offset: Default Value: 00000000h Attribute: Size: R/W, RO 32 bits SDATA when SINDX.RIDX is 01h. This is a 32-bit read-write register by which software controls SATA capabilities. Writes to the SControl register result in an action being taken by the PCH or the interface. Reads from the register return the last value written to it. Bit Description 31:20 Reserved 19:16 Port Multiplier Port (PMP) -- R/W. This field is not used by AHCI. 15:12 Select Power Management (SPM) -- R/W. This field is not used by AHCI. Interface Power Management Transitions Allowed (IPM) -- R/W. Indicates which power states the PCH is allowed to transition to: Value 11:8 Description 0h No interface restriction 1h Transitions to the PARTIAL state disabled 2h Transitions to the SLUMBER state disabled 3h Transitions to both PARTIAL and SLUMBER state disabled All other values reserved Speed Allowed (SPD) -- R/W. Indicates the highest allowable speed of the interface. This speed is limited by the CAP.ISS (ABAR+00h:bit 23:20) field. Value 7:4 Description 0h No speed negotiation restriction 1h Limit speed negotiation to Generation 1 communication rate 2h Limit speed negotiation to Generation 2 communication rate 3h Limit speed negotiation to Generation 3 communication rate All other values reserved. The PCH Supports Generation 1 communication rates (1.5 Gb/s), Gen 2 rates (3.0 Gb/s) and Gen 3 rates (6Gb/s). Device Detection Initialization (DET) -- R/W. Controls the PCH's device detection and interface initialization. Value 3:0 Description 0h No device detection or initialization action requested 1h Perform interface communication initialization sequence to establish communication. This is functionally equivalent to a hard reset and results in the interface being reset and communications re-initialized 4h Disable the Serial ATA interface and put Phy in offline mode All other values reserved. When this field is written to a 1h, the PCH initiates COMRESET and starts the initialization process. When the initialization is complete, this field shall remain 1h until set to another value by software. This field may only be changed to 1h or 4h when PxCMD.ST is 0. Changing this field while the PCH is running results in undefined behavior. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 517 SATA Controller Registers (D31:F2) 14.3.2.3 PxSERR--Serial ATA Error Register (D31:F2) Address Offset: Default Value: 00000000h Attribute: Size: R/WC 32 bits SDATA when SINDx.RIDX is 02h. Bits 26:16 of this register contains diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes. Bits 11:0 contain error information used by host software in determining the appropriate response to the error condition. If one or more of bits 11:8 of this register are set, the controller will stop the current transfer. Bit 31:27 Reserved 26 Exchanged (X): When set to `1' this bit indicates that a change in device presence has been detected since the last time this bit was cleared. This bit shall always be set to 1 anytime a COMINIT signal is received. This bit is reflected in the P0IS.PCS bit. 25 Unrecognized FIS Type (F): Indicates that one or more FISs were received by the Transport layer with good CRC, but had a type field that was not recognized. 24 Transport state transition error (T): Indicates that an error has occurred in the transition from one state to another within the Transport layer since the last time this bit was cleared. 23 Link Sequence Error (S): Indicates that one or more Link state machine error conditions was encountered. The Link Layer state machine defines the conditions under which the link layer detects an erroneous transition. 22 Handshake (H): Indicates that one or more R_ERR handshake response was received in response to frame transmission. Such errors may be the result of a CRC error detected by the recipient, a disparity or 8b/10b decoding error, or other error condition leading to a negative handshake on a transmitted frame. 21 CRC Error (C): Indicates that one or more CRC errors occurred with the Link Layer. 20 Disparity Error (D): This field is not used by AHCI. 19 10b to 8b Decode Error (B): Indicates that one or more 10b to 8b decoding errors occurred. 18 Comm Wake (W): Indicates that a Comm Wake signal was detected by the Phy. 17 Phy Internal Error (I): Indicates that the Phy detected some internal error. 16 PhyRdy Change (N): When set to 1 this bit indicates that the internal PhyRdy signal changed state since the last time this bit was cleared. In the PCH, this bit will be set when PhyRdy changes from a 0 -> 1 or a 1 -> 0. The state of this bit is then reflected in the PxIS.PRCS interrupt status bit and an interrupt will be generated if enabled. Software clears this bit by writing a 1 to it. 15:12 Reserved 11 Internal Error (E): The SATA controller failed due to a master or target abort when attempting to access system memory. 10 Protocol Error (P): A violation of the Serial ATA protocol was detected. Note: The PCH does not set this bit for all protocol violations that may occur on the SATA link. 9 Persistent Communication or Data Integrity Error (C): A communication error that was not recovered occurred that is expected to be persistent. Persistent communications errors may arise from faulty interconnect with the device, from a device that has been removed or has failed, or a number of other causes. 8 Transient Data Integrity Error (T): A data integrity error occurred that was not recovered by the interface. 7:2 518 Description Reserved. 1 Recovered Communications Error (M): Communications between the device and host was temporarily lost but was re-established. This can arise from a device temporarily being removed, from a temporary loss of Phy synchronization, or from other causes and may be derived from the PhyNRdy signal between the Phy and Link layers. 0 Recovered Data Integrity Error (I): A data integrity error occurred that was recovered by the interface through a retry operation or other recovery action. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) 14.4 AHCI Registers (D31:F2) Note: These registers are AHCI-specific and available when the PCH is properly configured. The Serial ATA Status, Control, and Error registers are special exceptions and may be accessed on all PCH components if properly configured; see Section 14.3 for details. The memory mapped registers within the SATA controller exist in non-cacheable memory space. Additionally, locked accesses are not supported. If software attempts to perform locked transactions to the registers, indeterminate results may occur. Register accesses shall have a maximum size of 64-bits; 64-bit access must not cross an 8-byte alignment boundary. All memory registers are reset by Function Level Reset unless specified otherwise. The registers are broken into two sections - generic host control and port control. The port control registers are the same for all ports, and there are as many registers banks as there are ports. Table 14-3. AHCI Register Address Map 14.4.1 ABAR + Offset Mnemonic Register 00-1Fh GHC 20h-FFh -- Generic Host Control 100h-17Fh P0PCR Port 0 port control registers 180h-1FFh P1PCR Port 1 port control registers 200h-27Fh P2PCR Port 2 port control registers 280h-2FFh P3PCR Port 3 port control registers 300h-37Fh P4PCR Port 4 port control registers 380h-3FFh P5PCR Port 5 port control registers 400h-47Fh P6PCR Port 6 port control registers Reserved AHCI Generic Host Control Registers (D31:F2) Table 14-4. Generic Host Controller Register Address Map ABAR + Offset Mnemonic Register Default Type 00-03 CAP Host Capabilities FF22FFC2h R/WO, RO 04-07 GHC Global PCH Control 00000000h R/W, RO 08-0Bh IS Interrupt Status 00000000h R/WC 0Ch-0Fh PI Ports Implemented 00000000h R/WO, RO 10h-13h VS AHCI Version 00010300h RO 14h-17h CCC_CTL Command Completion Coalescing Control 00010121h R/W, RO 18h-1Bh CCC_PORTS Command Completion Coalescing Ports 00000000h R/W 1Ch-1Fh EM_LOC Enclosure Management Location 01600002h RO 20h-23h EM_CTRL Enclosure Management Control 07010000h R/W, R/WO, RO 70h-73h VS AHCI Version 00010000h RO Vendor Specific 00000000h RO, R/WO 003Fh R/WO A0h-A3h VSP C8h-C9h RSTF Intel RST Feature Capabilities Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 519 SATA Controller Registers (D31:F2) 14.4.1.1 CAP--Host Capabilities Register (D31:F2) Address Offset: ABAR + 00h-03h Default Value: FF22FFC2h Function Level Reset:No Attribute: Size: R/WO, RO 32 bits All bits in this register that are R/WO are reset only by PLTRST#. Bit Description 31 Supports 64-bit Addressing (S64A) -- RO. Indicates that the SATA controller can access 64bit data structures. The 32-bit upper bits of the port DMA Descriptor, the PRD Base, and each PRD entry are read/write. 30 Supports Command Queue Acceleration (SCQA) -- R/WO. When set to 1, indicates that the SATA controller supports SATA command queuing using the DMA Setup FIS. The PCH handles DMA Setup FISes natively, and can handle auto-activate optimization through that FIS. 29 Supports SNotification Register (SSNTF): -- RO. The PCH SATA Controller does not support the SNotification register. 28 Supports Mechanical Presence Switch (SMPS) -- R/WO. When set to 1, indicates whether the SATA controller supports mechanical presence switches on its ports for use in Hot Plug operations. This value is loaded by platform BIOS prior to OS initialization. If this bit is set, BIOS must also map the SATAGP pins to the SATA controller through GPIO space. 27 Supports Staggered Spin-up (SSS) -- R/WO. Indicates whether the SATA controller supports staggered spin-up on its ports, for use in balancing power spikes. This value is loaded by platform BIOS prior to OS initialization. 0 = Staggered spin-up not supported. 1 = Staggered spin-up supported. 26 Supports Aggressive Link Power Management (SALP) -- R/WO. 0 = Software shall treat the PxCMD.ALPE and PxCMD.ASP bits as reserved. 1 = The SATA controller supports auto-generating link requests to the partial or slumber states when there are no commands to process. 25 Supports Activity LED (SAL) -- RO. Indicates that the SATA controller supports a single output pin (SATALED#) which indicates activity. 24 Supports Command List Override (SCLO) -- R/WO. When set to '1', indicates that the Controller supports the PxCMD.CLO bit and its associated function. When cleared to '0', the Controller is not capable of clearing the BSY and DRQ bits in the Status register in order to issue a software reset if these bits are still set from a previous operation. 23:20 Interface Speed Support (ISS) -- R/WO. Indicates the maximum speed the SATA controller can support on its ports. 1h = 1.5 Gb/s; 2h =3.0 Gb/s; 3h = 6.0 Gb/s. 19 Supports Non-Zero DMA Offsets (SNZO) -- RO. Reserved, as per the AHCI Revision 1.3 specification 18 Supports AHCI Mode Only (SAM) -- RO. The SATA controller may optionally support AHCI access mechanism only. 0 = SATA controller supports both IDE and AHCI Modes 1 = SATA controller supports AHCI Mode Only 17 Supports Port Multiplier (PMS) -- R/WO. The PCH SATA controller does not support Port Multipliers. BIOS must clear this bit by writing a 0 to this field. 16 Reserved 15 PIO Multiple DRQ Block (PMD) -- RO. Hardwired to 1. The SATA controller supports PIO Multiple DRQ Command Block 14 Slumber State Capable (SSC) -- R/WO. When set to 1, the SATA controller supports the slumber state. 13 Partial State Capable (PSC) -- R/WO. When set to 1, the SATA controller supports the partial state. 12:8 7 520 Number of Command Slots (NCS) -- RO. Hardwired to 1Fh to indicate support for 32 slots. Command Completion Coalescing Supported (CCCS) -- R/WO. 0 = Command Completion Coalescing Not Supported 1 = Command Completion Coalescing Supported Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) Bit 6 Enclosure Management Supported (EMS) -- R/WO. 0 = Enclosure Management Not Supported 1 = Enclosure Management Supported 5 Supports External SATA (SXS) -- R/WO. 0 = External SATA is not supported on any ports 1 = External SATA is supported on one or more ports When set, SW can examine each SATA port's Command Register (PxCMD) to determine which port is routed externally. 4:0 14.4.1.2 Description Number of Ports (NPS) -- RO. Indicates number of supported ports. Note that the number of ports indicated in this field may be more than the number of ports indicated in the PI (ABAR + 0Ch) register. GHC--Global PCH Control Register (D31:F2) Address Offset: ABAR + 04h-07h Default Value: 00000000h Attribute: Size: R/W, RO 32 bits Bit Description 31 AHCI Enable (AE) -- R/W. When set, this bit indicates that an AHCI driver is loaded and the controller will be talked to using AHCI mechanisms. This can be used by an PCH that supports both legacy mechanisms (such as SFF-8038i) and AHCI to know when the controller will not be talked to as legacy. 0 = Software will communicate with the PCH using legacy mechanisms. 1 = Software will communicate with the PCH using AHCI. The PCH will not have to allow command processing using both AHCI and legacy mechanisms. Software shall set this bit to 1 before accessing other AHCI registers. 30:3 Reserved 2 MSI Revert to Single Message (MRSM) -- RO: When set to '1' by hardware, this bit indicates that the host controller requested more than one MSI vector but has reverted to using the first vector only. When this bit is cleared to '0', the Controller has not reverted to single MSI mode (that is hardware is already in single MSI mode, software has allocated the number of messages requested, or hardware is sharing interrupt vectors if MC.MME < MC.MMC). "MC.MSIE = '1' (MSI is enabled) "MC.MMC > 0 (multiple messages requested) "MC.MME > 0 (more than one message allocated) "MC.MME!= MC.MMC (messages allocated not equal to number requested) When this bit is set to '1', single MSI mode operation is in use and software is responsible for clearing bits in the IS register to clear interrupts. This bit shall be cleared to '0' by hardware when any of the four conditions stated is false. This bit is also cleared to '0' when MC.MSIE = '1' and MC.MME = 0h. In this case, the hardware has been programmed to use single MSI mode, and is not "reverting" to that mode. For PCH, the Controller shall always revert to single MSI mode when the number of vectors allocated by the host is less than the number requested. This bit is ignored when GHC.HR = 1. 1 Interrupt Enable (IE) -- R/W. This global bit enables interrupts from the PCH. 0 = All interrupt sources from all ports are disabled. 1 = Interrupts are allowed from the AHCI controller. 0 Controller Reset (HR) -- R/W. Resets PCH AHCI controller. 0 = No effect 1 = When set by software, this bit causes an internal reset of the PCH AHCI controller. All state machines that relate to data transfers and queuing return to an idle condition, and all ports are re-initialized using COMRESET. Note: For further details, consult Section 10.4.3 of the Serial ATA Advanced Host Controller Interface specification revision 1.3. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 521 SATA Controller Registers (D31:F2) 14.4.1.3 IS--Interrupt Status Register (D31:F2) Address Offset: ABAR + 08h-0Bh Default Value: 00000000h Attribute: Size: R/WC 32 bits This register indicates which of the ports within the controller have an interrupt pending and require service. Bit 31:6 14.4.1.4 Description Reserved. Returns 0. 5 Interrupt Pending Status Port[5] (IPS[5]) -- R/WC. 0 = No interrupt pending. 1 = Port 5 has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. 4 Interrupt Pending Status Port[4] (IPS[4]) -- R/WC. 0 = No interrupt pending. 1 = Port 4 has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. 3 Interrupt Pending Status Port[3] (IPS[3]) -- R/WC. 0 = No interrupt pending. 1 = Port 3 has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. 2 Interrupt Pending Status Port[2] (IPS[2]) -- R/WC. 0 = No interrupt pending. 1 = Port 2 has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. 1 Interrupt Pending Status Port[1] (IPS[1]) -- R/WC. 0 = No interrupt pending. 1 = Port 1has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. 0 Interrupt Pending Status Port[0] (IPS[0]) -- R/WC. 0 = No interrupt pending. 1 = Port 0 has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. PI--Ports Implemented Register (D31:F2) Address Offset: ABAR + 0Ch-0Fh Default Value: 00000000h Function Level Reset:No Attribute: Size: R/WO, RO 32 bits This register indicates which ports are exposed to the PCH. It is loaded by platform BIOS. It indicates which ports that the device supports are available for software to use. For ports that are not available, software must not read or write to registers within that port. Bit 31:6 522 Description Reserved. Returns 0. 5 Ports Implemented Port 5 (PI5) -- R/WO. 0 = The port is not implemented. 1 = The port is implemented. This bit is read-only `0' if MAP.SC = `0' or SCC = `01h'. 4 Ports Implemented Port 4 (PI4) -- R/WO. 0 = The port is not implemented. 1 = The port is implemented. This bit is read-only `0' if MAP.SC = `0' or SCC = `01h'. 3 Ports Implemented Port 3 (PI3) -- R/WO. 0 = The port is not implemented. 1 = The port is implemented. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) Bit 14.4.1.5 Description 2 Ports Implemented Port 2 (PI2)-- R/WO. 0 = The port is not implemented. 1 = The port is implemented. 1 Ports Implemented Port 1 (PI1) -- R/WO. 0 = The port is not implemented. 1 = The port is implemented. 0 Ports Implemented Port 0 (PI0) -- R/WO. 0 = The port is not implemented. 1 = The port is implemented. VS--AHCI Version (D31:F2) Address Offset: ABAR + 10h-13h Default Value: 00010300h Attribute: Size: RO 32 bits This register indicates the major and minor version of the AHCI specification. It is BCD encoded. The upper two bytes represent the major version number, and the lower two bytes represent the minor version number. Example: Version 3.12 would be represented as 00030102h. The current version of the specification is 1.30 (00010300h). Bit 31:16 15:0 14.4.1.6 Description Major Version Number (MJR) -- RO. Indicates the major version is 1 Minor Version Number (MNR) -- RO. Indicates the minor version is 30. EM_LOC--Enclosure Management Location Register (D31:F2) Address Offset: ABAR + 1Ch-1Fh Default Value: 01600002h Attribute: Size: RO 32 bits This register identifies the location and size of the enclosure management message buffer. This register is reserved if enclosure management is not supported (that is, CAP.EMS = 0). Bit Description 31:16 Offset (OFST) -- RO. The offset of the message buffer in Dwords from the beginning of the ABAR. 15:0 Buffer Size (SZ) -- RO. Specifies the size of the transmit message buffer area in Dwords. The PCH SATA controller only supports transmit buffer. A value of 0 is invalid. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 523 SATA Controller Registers (D31:F2) 14.4.1.7 EM_CTRL--Enclosure Management Control Register (D31:F2) Address Offset: ABAR + 20h-23h Default Value: 07010000h Attribute: Size: R/W, R/WO, RO 32 bits This register is used to control and obtain status for the enclosure management interface. This register includes information on the attributes of the implementation, enclosure management messages supported, the status of the interface, whether any message are pending, and is used to initiate sending messages. This register is reserved if enclosure management is not supported (CAP_EMS = 0). Bit 31:27 26 Reserved Activity LED Hardware Driven (ATTR.ALHD) -- R/WO. 1 = The SATA controller drives the activity LED for the LED message type in hardware and does not utilize software for this LED. The host controller does not begin transmitting the hardware based activity signal until after software has written CTL.TM=1 after a reset condition. 25 Transmit Only (ATTR.XMT) -- RO. 0 = The SATA controller supports transmitting and receiving messages. 1 = The SATA controller only supports transmitting messages and does not support receiving messages. 24 Single Message Buffer (ATTR.SMB) -- RO. 0 = There are separate receive and transmit buffers such that unsolicited messages could be supported. 1 = The SATA controller has one message buffer that is shared for messages to transmit and messages received. Unsolicited receive messages are not supported and it is software's responsibility to manage access to this buffer. 23:20 Reserved 19 SGPIO Enclosure Management Messages (SUPP.SGPIO) -- RO. 1 = The SATA controller supports the SGPIO register interface message type. 18 SES-2 Enclosure Management Messages (SUPP.SES2) -- RO. 1 = The SATA controller supports the SES-2 message type. 17 SAF-TE Enclosure Management Messages (SUPP.SAFTE) -- RO. 1 = The SATA controller supports the SAF-TE message type. 16 LED Message Types (SUPP.LED) -- RO. 1 = The SATA controller supports the LED message type. 15:10 Reserved 9 Reset (RST): -- R/W. 0 = A write of 0 to this bit by software will have no effect. 1 = When set by software, The SATA controller resets all enclosure management message logic and takes all appropriate reset actions to ensure messages can be transmitted / received after the reset. After the SATA controller completes the reset operation, the SATA controller sets the value to 0. 8 Transmit Message (CTL.TM) -- R/W. 0 = A write of 0 to this bit by software will have no effect. 1 = When set by software, The SATA controller transmits the message contained in the message buffer. When the message is completely sent, the SATA controller sets the value to 0. Software must not change the contents of the message buffer while CTL.TM is set to 1. 7:1 0 524 Description Reserved Message Received (STS.MR): -- RO. Message Received is not supported in the PCH. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) 14.4.1.8 CAP2--HBA Capabilities Extended Address Offset: ABAR + 24h-27h Default Value: 00000004h Function Level Reset: No Bit 31:3 14.4.1.9 Attribute: Size: Description Reserved 2 Automatic Partial to Slumber Transitions (APST) 0= Not supported 1= Supported 1 Reserved 0 Reserved VSP--Vendor Specific (D31:F2) Address Offset: ABAR + A0h-A3h Default Value: 00000000h Bit 31:1 0 14.4.1.10 RO 32 bits Attribute: Size: RO, R/WO 32 bits Description Reserved SATA Initialization Field -- R/WO BIOS must clear this bit by writing a 0 to this field. Intel(R) Rapid Storage Technology enterprise (Intel(R) RSTe) Feature Capabilities Address Offset: ABAR + C8h-C9hAttribute: R/WO Default Value: 003FhSize: 16 bits Function Level Reset: No No hardware action is taken on this register. This register is needed for the Intel(R) Rapid Storage Technology enterprise software. These bits are set by BIOS to request the feature from the appropriate Intel Rapid Storage Technology enterprise software. Bit 15:12 11:10 Description Reserved OROM UI Normal Delay (OUD) -- R/WO. The values of these bits specify the delay of the OROM UI Splash Screen in a normal status. 00 = 2 Seconds (Default) 01 = 4 Seconds 10 = 6 Seconds 11 = 8 Seconds If bit 5 = 0b these values will be disregarded. 9 Reserved 8 Intel(R) RRT Only on eSATA (ROES) -- R/WO Indicates the request that only Intel(R) Rapid Recovery Technology (RRT) volumes can can span internal and external SATA (eSATA). If not set, any RAID volume can span internal and external SATA. 0 = Disabled 1 = Enabled Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 525 SATA Controller Registers (D31:F2) 526 Bit Description 7 LED Locate (LEDL) -- R/WO Indicates the request that the LED/SGPIO hardware is attached and ping to locate feature is enabled in the OS. 0 = Disabled Enabled 6 HDD Unlock (HDDLK) -- R/WO Indicates the requested status of HDD password unlock in the OS. 0 = Disabled 1 = Enabled 5 Intel RSTe OROM UI (RSTOROMUI) -- R/WO. Indicates the requested status of the Intel(R) RSTe OROM UI display. 0 = The Intel RSTe OROM UI and banner are not displayed if all disks and RAID volumes have a normal status. 1 = The Intel RSTe OROM UI is displayed during each boot. 4 Intel RSTe -- R/WO Indicates the requested status of the Intel(R) Rapid Recovery Technology Support 0 = The Intel RSTe is disabled 1 = The Intel RSTe is enabled 3 RAID 5 Enable (R5E) -- R/WO Indicates the requested status of RAID 5 Support 0 = Disabled 1 = Enabled 2 RAID 10 Enable (R10E) -- R/WO Indicates the requested status of RAID 10 Support 0 = Disabled 1 = Enabled 1 RAID 1 Enable (R1E) -- R/WO Indicates the requested status of RAID 1 Support 0 = Disabled 1 = Enabled 0 RAID 0 Enable (R0E) -- R/WO Indicates the requested status of RAID 0 Support 0 = Disabled 1 = Enabled Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) 14.4.2 Port Registers (D31:F2) Ports not available will result in the corresponding Port DMA register space being reserved. The controller shall ignore writes to the reserved space on write cycles and shall return `0' on read cycle accesses to the reserved location. SSD Functionality of Integrated NAND Module appears as Port 6(7th SATA port) When the NVMHCI is exposed as a port under AHCI, Port 7 registers will start at ABAR + 480h. Table 14-5. Port [5:0] DMA Register Address Map (Sheet 1 of 3) ABAR + Offset Mnemonic 100h-103h P0CLB 104h-107h P0CLBU Register Port 0 Command List Base Address Port 0 Command List Base Address Upper 32-Bits 108h-10Bh P0FB 10Ch-10Fh P0FBU 110h-113h P0IS Port 0 Interrupt Status 114h-117h P0IE Port 0 Interrupt Enable 118h-11Bh P0CMD 11Ch-11Fh -- 120h-123h P0TFD Port 0 Task File Data 124h-127h P0SIG Port 0 Signature 128h-12Bh P0SSTS Port 0 Serial ATA Status 12Ch-12Fh P0SCTL Port 0 Serial ATA Control 130h-133h P0SERR Port 0 Serial ATA Error 134h-137h P0SACT Port 0 Serial ATA Active 138h-13Bh P0CI 13Ch-17Fh -- 180h-183h P1CLB 184h-187h P1CLBU Port 0 FIS Base Address Port 0 FIS Base Address Upper 32-Bits Port 0 Command Reserved Port 0 Command Issue Reserved Port 1 Command List Base Address Port 1 Command List Base Address Upper 32-Bits 188h-18Bh P1FB 18Ch-18Fh P1FBU 190h-193h P1IS Port 1 Interrupt Status 194h-197h P1IE Port 1 Interrupt Enable 198h-19Bh P1CMD 19Ch-19Fh -- 1A0h-1A3h P1TFD Port 1 Task File Data 1A4h-1A7h P1SIG Port 1 Signature 1A8h-1ABh P1SSTS Port 1 Serial ATA Status 1ACh-1AFh P1SCTL Port 1 Serial ATA Control 1B0h-1B3h P1SERR Port 1 Serial ATA Error 1B4h-1B7h P1SACT Port 1 Serial ATA Active 1B8h-1BBh P1CI 1BCh-1FFh -- 200h-203h P2CLB 204h-207h P2CLBU Port 1 FIS Base Address Port 1 FIS Base Address Upper 32-Bits Port 1 Command Reserved Port 1 Command Issue Reserved Port 2 Command List Base Address Port 2 Command List Base Address Upper 32-Bits Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 527 SATA Controller Registers (D31:F2) Table 14-5. Port [5:0] DMA Register Address Map (Sheet 2 of 3) ABAR + Offset 528 Mnemonic Register 208h-20Bh P2FB 20Ch-20Fh P2FBU 210h-213h P2IS Port 2 Interrupt Status 214h-217h P2IE Port 2 Interrupt Enable 218h-21Bh P2CMD 21Ch-21Fh -- 220h-223h P2TFD Port 2 Task File Data 224h-227h P2SIG Port 2 Signature 228h-22Bh P2SSTS Port 2 Serial ATA Status 22Ch-22Fh P2SCTL Port 2 Serial ATA Control 230h-233h P2SERR Port 2 Serial ATA Error 234h-237h P2SACT Port 2 Serial ATA Active 238h-23Bh P2CI 23Ch-27Fh -- 280h-283h P3CLB 284h-287h P3CLBU Port 2 FIS Base Address Port 2 FIS Base Address Upper 32-Bits Port 2 Command Reserved Port 2 Command Issue Reserved Port 3 Command List Base Address Port 3 Command List Base Address Upper 32-Bits 288h-28Bh P3FB 28Ch-28Fh P3FBU 290h-293h P3IS Port 3 Interrupt Status 294h-297h P3IE Port 3 Interrupt Enable 298h-29Bh P3CMD 29Ch-29Fh -- 2A0h-2A3h P3TFD Port 3 Task File Data 2A4h-2A7h P3SIG Port 3 Signature 2A8h-2ABh P3SSTS Port 3 Serial ATA Status 2ACh-2AFh P3SCTL Port 3 Serial ATA Control 2B0h-2B3h P3SERR Port 3 Serial ATA Error 2B4h-2B7h P3SACT Port 3 Serial ATA Active 2B8h-2BBh P3CI 2BCh-2FFh -- 300h-303h P4CLB 304h-307h P4CLBU Port 3 FIS Base Address Port 3 FIS Base Address Upper 32-Bits Port 3 Command Reserved Port 3 Command Issue Reserved Port 4 Command List Base Address Port 4 Command List Base Address Upper 32-Bits 308h-30Bh P4FB 30Ch-30Fh P4FBU Port 4 FIS Base Address 310h-313h P4IS Port 4 Interrupt Status 314h-317h P4IE Port 4 Interrupt Enable 318h-31Bh P4CMD 31Ch-31Fh -- 320h-323h P4TFD Port 4 Task File Data 324h-327h P4SIG Port 4 Signature 328h-32Bh P4SSTS Port 4 Serial ATA Status 32Ch-32Fh P4SCTL Port 4 Serial ATA Control Port 4 FIS Base Address Upper 32-Bits Port 4 Command Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) Table 14-5. Port [5:0] DMA Register Address Map (Sheet 3 of 3) 14.4.2.1 ABAR + Offset Mnemonic Register 330h-333h P4SERR Port 4 Serial ATA Error 334h-337h P4SACT Port 4 Serial ATA Active 338h-33Bh P4CI 33Ch-37Fh -- Port 4 Command Issue Reserved 380h-383h P5CLB 384h-387h P5CLBU Port 5 Command List Base Address Port 5 Command List Base Address Upper 32-Bits 388h-38Bh P5FB 38Ch-38Fh P5FBU Port 5 FIS Base Address 390h-393h P5IS Port 5 Interrupt Status 394h-397h P5IE Port 5 Interrupt Enable 398h-39Bh P5CMD 39Ch-39Fh -- 3A0h-3A3h P5TFD Port 5 Task File Data 3A4h-3A7h P5SIG Port 5 Signature 3A8h-3ABh P5SSTS Port 5 Serial ATA Status 3ACh-3AFh P5SCTL Port 5 Serial ATA Control 3B0h-3B3h P5SERR Port 5 Serial ATA Error 3B4h-3B7h P5SACT Port 5 Serial ATA Active 3B8h-3BBh P5CI 3BCh-FFFh -- Port 5 FIS Base Address Upper 32-Bits Port 5 Command Reserved Port 5 Command Issue Reserved PxCLB--Port [5:0] Command List Base Address Register (D31:F2) Address Offset: Port Port Port Port Port Port Default Value: 0: 1: 2: 3: 4: 5: ABAR ABAR ABAR ABAR ABAR ABAR + + + + + + Undefined 100h 180h 200h 280h 300h 380h Attribute: R/W Size: 32 bits Bit Description 31:10 Command List Base Address (CLB) -- R/W. Indicates the 32-bit base for the command list for this port. This base is used when fetching commands to execute. The structure pointed to by this address range is 1 KB in length. This address must be 1-KB aligned as indicated by bits 31:10 being read/write. Note that these bits are not reset on a Controller reset. 9:0 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 529 SATA Controller Registers (D31:F2) 14.4.2.2 PxCLBU--Port [5:0] Command List Base Address Upper 32-Bits Register (D31:F2) Address Offset: Port Port Port Port Port Port Default Value: 0: 1: 2: 3: 4: 5: ABAR ABAR ABAR ABAR ABAR ABAR + + + + + + 104h 184h 204h 284h 304h 384h Undefined Bit 31:0 14.4.2.3 Size: 32 bits Command List Base Address Upper (CLBU) -- R/W. Indicates the upper 32-bits for the command list base address for this port. This base is used when fetching commands to execute. Note that these bits are not reset on a Controller reset. PxFB--Port [5:0] FIS Base Address Register (D31:F2) Default Value: 0: 1: 2: 3: 4: 5: ABAR ABAR ABAR ABAR ABAR ABAR + + + + + + 108h 188h 208h 288h 308h 388h Undefined Attribute: R/W Size: 32 bits Bit Description 31:8 FIS Base Address (FB) -- R/W. Indicates the 32-bit base for received FISes. The structure pointed to by this address range is 256 bytes in length. This address must be 256-byte aligned, as indicated by bits 31:3 being read/write. Note that these bits are not reset on a Controller reset. 7:0 Reserved PxFBU--Port [5:0] FIS Base Address Upper 32-Bits Register (D31:F2) Address Offset: Port Port Port Port Port Port Default Value: 530 R/W Description Address Offset: Port Port Port Port Port Port 14.4.2.4 Attribute: 0: 1: 2: 3: 4: 5: ABAR ABAR ABAR ABAR ABAR ABAR Undefined + + + + + + 10Ch 18Ch 20Ch 28Ch 30Ch 38Ch Attribute: R/W Size: 32 bits Bit Description 31:0 FIS Base Address Upper (FBU) -- R/W. Indicates the upper 32-bits for the received FIS base for this port. Note that these bits are not reset on a Controller reset. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) 14.4.2.5 PxIS--Port [5:0] Interrupt Status Register (D31:F2) Address Offset: Port Port Port Port Port Port Default Value: 0: 1: 2: 3: 4: 5: ABAR ABAR ABAR ABAR ABAR ABAR + + + + + + 00000000h Bit 110h 190h 210h 290h 310h 390h Attribute: R/WC, RO Size: 32 bits Description 31 Cold Port Detect Status (CPDS) -- RO. Cold presence detect is not supported. 30 Task File Error Status (TFES) -- R/WC. This bit is set whenever the status register is updated by the device and the error bit (PxTFD.bit 0) is set. 29 Host Bus Fatal Error Status (HBFS) -- R/WC. Indicates that the PCH encountered an error that it cannot recover from due to a bad software pointer. In PCI, such an indication would be a target or master abort. 28 Host Bus Data Error Status (HBDS) -- R/WC. Indicates that the PCH encountered a data error (uncorrectable ECC / parity) when reading from or writing to system memory. 27 Interface Fatal Error Status (IFS) -- R/WC. Indicates that the PCH encountered an error on the SATA interface which caused the transfer to stop. 26 Interface Non-fatal Error Status (INFS) -- R/WC. Indicates that the PCH encountered an error on the SATA interface but was able to continue operation. 25 Reserved 24 Overflow Status (OFS) -- R/WC. Indicates that the PCH received more bytes from a device than was specified in the PRD table for the command. 23 Incorrect Port Multiplier Status (IPMS) -- R/WC. The PCH SATA controller does not support Port Multipliers. 22 PhyRdy Change Status (PRCS) -- RO. When set to `1', this bit indicates the internal PhyRdy signal changed state. This bit reflects the state of PxSERR.DIAG.N. Unlike most of the other bits in the register, this bit is RO and is only cleared when PxSERR.DIAG.N is cleared. Note that the internal PhyRdy signal also transitions when the port interface enters partial or slumber power management states. Partial and slumber must be disabled when Surprise Removal Notification is desired, otherwise the power management state transitions will appear as false insertion and removal events. 21:8 Reserved 7 Device Interlock Status (DIS) -- R/WC. When set, this bit indicates that a platform interlock switch has been opened or closed, which may lead to a change in the connection state of the device. This bit is only valid in systems that support an interlock switch (CAP.SIS [ABAR+00:bit 28] set). For systems that do not support an interlock switch, this bit will always be 0. 6 Port Connect Change Status (PCS) -- RO. This bit reflects the state of PxSERR.DIAG.X. (ABAR+130h/1D0h/230h/2D0h, bit 26) Unlike other bits in this register, this bit is only cleared when PxSERR.DIAG.X is cleared. 0 = No change in Current Connect Status. 1 = Change in Current Connect Status. 5 Descriptor Processed (DPS) -- R/WC. A PRD with the I bit set has transferred all its data. 4 Unknown FIS Interrupt (UFS) -- RO. When set to `1', this bit indicates that an unknown FIS was received and has been copied into system memory. This bit is cleared to `0' by software clearing the PxSERR.DIAG.F bit to `0'. Note that this bit does not directly reflect the PxSERR.DIAG.F bit. PxSERR.DIAG.F is set immediately when an unknown FIS is detected, whereas this bit is set when the FIS is posted to memory. Software should wait to act on an unknown FIS until this bit is set to `1' or the two bits may become out of sync. 3 Set Device Bits Interrupt (SDBS) -- R/WC. A Set Device Bits FIS has been received with the I bit set and has been copied into system memory. 2 DMA Setup FIS Interrupt (DSS) -- R/WC. A DMA Setup FIS has been received with the I bit set and has been copied into system memory. 1 PIO Setup FIS Interrupt (PSS) -- R/WC. A PIO Setup FIS has been received with the I bit set, it has been copied into system memory, and the data related to that FIS has been transferred. 0 Device to Host Register FIS Interrupt (DHRS) -- R/WC. A D2H Register FIS has been received with the I bit set, and has been copied into system memory. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 531 SATA Controller Registers (D31:F2) 14.4.2.6 PxIE--Port [5:0] Interrupt Enable Register (D31:F2) Address Offset: Port Port Port Port Port Port Default Value: 0: 1: 2: 3: 4: 5: ABAR ABAR ABAR ABAR ABAR ABAR 00000000h + + + + + + 114h 194h 214h 294h 314h 394h Attribute: R/W, RO Size: 32 bits This register enables and disables the reporting of the corresponding interrupt to system software. When a bit is set (`1') and the corresponding interrupt condition is active, then an interrupt is generated. Interrupt sources that are disabled (`0') are still reflected in the status registers. Bit 31 Cold Presence Detect Enable (CPDE) -- RO. Cold Presence Detect is not supported. 30 Task File Error Enable (TFEE) -- R/W. When set, and GHC.IE and PxTFD.STS.ERR (due to a reception of the error register from a received FIS) are set, the PCH will generate an interrupt. 29 Host Bus Fatal Error Enable (HBFE) -- R/W. When set, and GHC.IE and PxS.HBFS are set, the PCH will generate an interrupt. 28 Host Bus Data Error Enable (HBDE) -- R/W. When set, and GHC.IE and PxS.HBDS are set, the PCH will generate an interrupt. 27 Host Bus Data Error Enable (HBDE) -- R/W. When set, GHC.IE is set, and PxIS.HBDS is set, the PCH will generate an interrupt. 26 Interface Non-fatal Error Enable (INFE) -- R/W. When set, GHC.IE is set, and PxIS.INFS is set, the PCH will generate an interrupt. 25 Reserved 24 Overflow Error Enable (OFE) -- R/W. When set, and GHC.IE and PxS.OFS are set, the PCH will generate an interrupt. 23 Incorrect Port Multiplier Enable (IPME) -- R/W. The PCH SATA controller does not support Port Multipliers. BIOS and storage software should keep this bit cleared to 0. 22 PhyRdy Change Interrupt Enable (PRCE) -- R/W. When set, and GHC.IE is set, and PxIS.PRCS is set, the PCH shall generate an interrupt. 21:8 532 Description Reserved 7 Device Interlock Enable (DIE) -- R/W. When set, and PxIS.DIS is set, the PCH will generate an interrupt. For systems that do not support an interlock switch, this bit shall be a read-only 0. 6 Port Change Interrupt Enable (PCE) -- R/W. When set, and GHC.IE and PxS.PCS are set, the PCH will generate an interrupt. 5 Descriptor Processed Interrupt Enable (DPE) -- R/W. When set, and GHC.IE and PxS.DPS are set, the PCH will generate an interrupt 4 Unknown FIS Interrupt Enable (UFIE) -- R/W. When set, and GHC.IE is set and an unknown FIS is received, the PCH will generate this interrupt. 3 Set Device Bits FIS Interrupt Enable (SDBE) -- R/W. When set, and GHC.IE and PxS.SDBS are set, the PCH will generate an interrupt. 2 DMA Setup FIS Interrupt Enable (DSE) -- R/W. When set, and GHC.IE and PxS.DSS are set, the PCH will generate an interrupt. 1 PIO Setup FIS Interrupt Enable (PSE) -- R/W. When set, and GHC.IE and PxS.PSS are set, the PCH will generate an interrupt. 0 Device to Host Register FIS Interrupt Enable (DHRE) -- R/W. When set, and GHC.IE and PxS.DHRS are set, the PCH will generate an interrupt. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) 14.4.2.7 PxCMD--Port [5:0] Command Register (D31:F2) Address Offset: Port Port Port Port Port Port 0: 1: 2: 3: 4: 5: ABAR ABAR ABAR ABAR ABAR ABAR + + + + + + 118h 198h 218h 298h 318h 398h Attribute: R/W, RO, R/WO Default Value: 0000w00wh Size: 32 bits where w = 00?0b (for?, see bit description) Function Level Reset:No (Bit 21, 19 and 18 only) Bit Description Interface Communication Control (ICC) -- R/W. This is a four bit field that can be used to control reset and power states of the interface. Writes to this field will cause actions on the interface, either as primitives or an OOB sequence, and the resulting status of the interface will be reported in the PxSSTS register (Address offset Port 0:ABAR+124h, Port 1: ABAR+1A4h, Port 2: ABAR+224h, Port 3: ABAR+2A4h, Port 4: ABAR+224h, Port 5: ABAR+2A4h). Value Fh-7h 6h 5h-3h 31:28 Definition Reserved Slumber: This will cause the PCH to request a transition of the interface to the slumber state. The SATA device may reject the request and the interface will remain in its current state Reserved 2h Partial: This will cause the PCH to request a transition of the interface to the partial state. The SATA device may reject the request and the interface will remain in its current state. 1h Active: This will cause the PCH to request a transition of the interface into the active 0h No-Op / Idle: When software reads this value, it indicates the PCH is not in the process of changing the interface state or sending a device reset, and a new link command may be issued. When system software writes a non-reserved value other than No-Op (0h), the PCH will perform the action and update this field back to Idle (0h). If software writes to this field to change the state to a state the link is already in (such as interface is in the active state and a request is made to go to the active state), the PCH will take no action and return this field to Idle. Note: When the ALPE bit (bit 26) is set, then this register should not be set to 02h or 06h. 27 Aggressive Slumber / Partial (ASP) -- R/W. When set, and the ALPE bit (bit 26) is set, the PCH shall aggressively enter the slumber state when it clears the PxCI register and the PxSACT register is cleared. When cleared, and the ALPE bit is set, the PCH will aggressively enter the partial state when it clears the PxCI register and the PxSACT register is cleared. If CAP.SALP is cleared to '0', software shall treat this bit as reserved. 26 Aggressive Link Power Management Enable (ALPE) -- R/W. When set, the PCH will aggressively enter a lower link power state (partial or slumber) based upon the setting of the ASP bit (bit 27). 25 Drive LED on ATAPI Enable (DLAE) -- R/W. When set to 1, the PCH will drive the LED pin active for ATAPI commands (PxCLB[CHz.A] set) in addition to ATA commands. When cleared, the PCH will only drive the LED pin active for ATA commands. See Section 5.17.10 for details on the activity LED. 24 Device is ATAPI (ATAPI) -- R/W. When set to 1, the connected device is an ATAPI device. This bit is used by the PCH to control whether or not to generate the LED when commands are active. See Section 5.17.10 for details on the activity LED. 23 Automatic Partial Slumber Transitions Enabled (APSTE)-- R/W. 0 = This port will not perform Automatic Partial to Slumber Transitions. 1 = The HBA may perform Automatic Partial to Slumber Transitions. Note: Software should only set this bit to `1' if CAP2.APST is set to `1'. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 533 SATA Controller Registers (D31:F2) Bit Description 22 SATA Initialization Field -- R/WO BIOS must write a 0 to this field. This field is not reset by FLR. 21 External SATA Port (ESP) -- R/WO. 0 = This port supports internal SATA devices only. 1 = This port will be used with an external SATA device and hot plug is supported. When set, CAP.SXS must also be set. This bit is not reset by Function Level Reset. 20 Reserved 19 Mechanical Switch Attached to Port (MPSP) -- R/WO. If set to 1, the PCH supports a mechanical presence switch attached to this port. The PCH takes no action on the state of this bit - it is for system software only. For example, if this bit is cleared, and an interlock switch toggles, the PCH still treats it as a proper interlock switch event. Note: 18 Note: 17:16 This bit is not reset on a Controller reset or by a Function Level Reset. Reserved. 15 Controller Running (CR) -- RO. When this bit is set, the DMA engines for a port are running. See section 5.2.2 of the Serial ATA AHCI Specification for details on when this bit is set and cleared by the PCH. 14 FIS Receive Running (FR) -- RO. When set, the FIS Receive DMA engine for the port is running. See section 12.2.2 of the Serial ATA AHCI Specification for details on when this bit is set and cleared by the PCH. 13 Mechanical Presence Switch State (MPSS) -- RO. The MPSS bit reports the state of a mechanical presence switch attached to this port. If CAP.SMPS is set to 1 and the mechanical presence switch is closed then this bit is cleared to 0. If CAP.SMPS is set to 1 and the mechanical presence switch is open then this bit is set to 1. If CAP.SMPS is set to '0' then this bit is cleared to 0. Software should only use this bit if both CAP.SMPS and PxCMD.MPSP are set to 1. 12:8 Current Command Slot (CCS) -- RO. Indicates the current command slot the PCH is processing. This field is valid when the ST bit is set in this register, and is constantly updated by the PCH. This field can be updated as soon as the PCH recognizes an active command slot, or at some point soon after when it begins processing the command. This field is used by software to determine the current command issue location of the PCH. In queued mode, software shall not use this field, as its value does not represent the current command being executed. Software shall only use PxCI and PxSACT when running queued commands. 7:5 4 534 This bit is not reset on a Controller reset or by a Function Level Reset. Hot-Plug Capable Port (HPCP) -- R/WO. 0 = Port is not capable of Hot-Plug. 1 = Port is Hot-Plug capable. This indicates whether the platform exposes this port to a device which can be Hot-Plugged. SATA by definition is hot-pluggable, but not all platforms are constructed to allow the device to be removed (it may be screwed into the chassis, for example). This bit can be used by system software to indicate a feature such as "eject device" to the end-user. The PCH takes no action on the state of this bit - it is for system software only. For example, if this bit is cleared, and a Hot-Plug event occurs, the PCH still treats it as a proper Hot-Plug event. Reserved FIS Receive Enable (FRE) -- R/W. When set, the PCH may post received FISes into the FIS receive area pointed to by PxFB (ABAR+108h/188h/208h/288h) and PxFBU (ABAR+10Ch/ 18Ch/20Ch/28Ch). When cleared, received FISes are not accepted by the PCH, except for the first D2H (device-to-host) register FIS after the initialization sequence. System software must not set this bit until PxFB (PxFBU) have been programmed with a valid pointer to the FIS receive area, and if software wishes to move the base, this bit must first be cleared, and software must wait for the FR bit (bit 14) in this register to be cleared. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) 14.4.2.8 Bit Description 3 Command List Override (CLO) -- R/W. Setting this bit to '1' causes PxTFD.STS.BSY and PxTFD.STS.DRQ to be cleared to '0'. This allows a software reset to be transmitted to the device regardless of whether the BSY and DRQ bits are still set in the PxTFD.STS register. The Controller sets this bit to '0' when PxTFD.STS.BSY and PxTFD.STS.DRQ have been cleared to '0'. A write to this register with a value of '0' shall have no effect. This bit shall only be set to '1' immediately prior to setting the PxCMD.ST bit to '1' from a previous value of '0'. Setting this bit to '1' at any other time is not supported and will result in indeterminate behavior. Software must wait for CLO to be cleared to '0' before setting PxCMD.ST to '1'. 2 Power On Device (POD) -- RO. Cold presence detect not supported. Defaults to 1. 1 Spin-Up Device (SUD) -- R/W / RO This bit is R/W and defaults to 0 for systems that support staggered spin-up (R/W when CAP.SSS (ABAR+00h:bit 27) is 1). Bit is RO 1 for systems that do not support staggered spinup (when CAP.SSS is 0). 0 = No action. 1 = On an edge detect from 0 to 1, the PCH starts a COMRESET initialization sequence to the device. Clearing this bit to '0' does not cause any OOB signal to be sent on the interface. When this bit is cleared to '0' and PxSCTL.DET=0h, the Controller will enter listen mode. 0 Start (ST) -- R/W. When set, the PCH may process the command list. When cleared, the PCH may not process the command list. Whenever this bit is changed from a 0 to a 1, the PCH starts processing the command list at entry 0. Whenever this bit is changed from a 1 to a 0, the PxCI register is cleared by the PCH upon the PCH putting the controller into an idle state. Refer to section 10.3 of the Serial ATA AHCI Specification for important restrictions on when ST can be set to 1 and cleared to 0. PxTFD--Port [5:0] Task File Data Register (D31:F2) Address Offset: Port Port Port Port Port Port Default Value: 0: 1: 2: 3: 4: 5: ABAR ABAR ABAR ABAR ABAR ABAR + + + + + + 120h 1A0h 220h 2A0h 320h 3A0h 0000007Fh Attribute: RO Size: 32 bits This is a 32-bit register that copies specific fields of the task file when FISes are received. The FISes that contain this information are: D2H Register FIS,PIO Setup FIS and Set Device Bits FIS Bit 31:16 15:8 Description Reserved Error (ERR) -- RO. Contains the latest copy of the task file error register. Status (STS) -- RO. Contains the latest copy of the task file status register. Fields of note in this register that affect AHCI. Bit 7:0 Field Definition 7 BSY Indicates the interface is busy 6:4 N/A Not applicable 3 DRQ Indicates a data transfer is requested 2:1 N/A Not applicable 0 ERR Indicates an error during the transfer Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 535 SATA Controller Registers (D31:F2) 14.4.2.9 PxSIG--Port [5:0] Signature Register (D31:F2) Address Offset: Port Port Port Port Port Port Default Value: 0: 1: 2: 3: 4: 5: ABAR ABAR ABAR ABAR ABAR ABAR + + + + + + 124h 1A4h 224h 2A4h 324h 3A4h FFFFFFFFh Attribute: RO Size: 32 bits This is a 32-bit register which contains the initial signature of an attached device when the first D2H Register FIS is received from that device. It is updated once after a reset sequence. Bit Description Signature (SIG) -- RO. Contains the signature received from a device on the first D2H register FIS. The bit order is as follows: Bit 31:0 Field 31:24 LBA High Register 23:16 LBA Mid Register 15:8 LBA Low Register 7:0 536 Sector Count Register Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) 14.4.2.10 PxSSTS--Port [5:0] Serial ATA Status Register (D31:F2) Address Offset: Port Port Port Port Port Port Default Value: 0: 1: 2: 3: 4: 5: ABAR ABAR ABAR ABAR ABAR ABAR + + + + + + 128h 1A8h 228h 2A8h 328h 3A8h 00000000h Attribute: RO Size: 32 bits This is a 32-bit register that conveys the current state of the interface and host. The PCH updates it continuously and asynchronously. When the PCH transmits a COMRESET to the device, this register is updated to its reset values. Bit 31:12 Description Reserved Interface Power Management (IPM) -- RO. Indicates the current interface state: Value 11:8 Description 0h Device not present or communication not established 1h Interface in active state 2h Interface in PARTIAL power management state 6h Interface in SLUMBER power management state All other values reserved. Current Interface Speed (SPD) -- RO. Indicates the negotiated interface communication speed. Value 7:4 Description 0h Device not present or communication not established 1h Generation 1 communication rate negotiated 2h Generation 2 communication rate negotiated 3h Generation 3 communication rate negotiated All other values reserved. The PCH Supports Gen 1 communication rates (1.5 Gb/s) and Gen 2 rates (3.0 Gb/s) and Gen 3 rates (6.0 Gb/s). Device Detection (DET) -- RO. Indicates the interface device detection and Phy state: Value 3:0 Description 0h No device detected and Phy communication not established 1h Device presence detected but Phy communication not established 3h Device presence detected and Phy communication established 4h Phy in offline mode as a result of the interface being disabled or running in a BIST loopback mode All other values reserved. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 537 SATA Controller Registers (D31:F2) 14.4.2.11 PxSCTL -- Port [5:0] Serial ATA Control Register (D31:F2) Address Offset: Port Port Port Port Port Port Default Value: 0: 1: 2: 3: 4: 5: ABAR ABAR ABAR ABAR ABAR ABAR + + + + + + 12Ch 1ACh 22Ch 2ACh 32Ch 3ACh 00000004h Attribute: R/W, RO Size: 32 bits This is a 32-bit read-write register by which software controls SATA capabilities. Writes to the SControl register result in an action being taken by the PCH or the interface. Reads from the register return the last value written to it. Bit Description 31:20 Reserved 19:16 Port Multiplier Port (PMP) -- R/W. This field is not used by AHCI 15:12 Select Power Management (SPM) -- R/W. This field is not used by AHCI Interface Power Management Transitions Allowed (IPM) -- R/W. Indicates which power states the PCH is allowed to transition to: Value 11:8 Description 0h No interface restrictions 1h Transitions to the PARTIAL state disabled 2h Transitions to the SLUMBER state disabled 3h Transitions to both PARTIAL and SLUMBER states disabled All other values reserved Speed Allowed (SPD) -- R/W. Indicates the highest allowable speed of the interface. This speed is limited by the CAP.ISS (ABAR+00h:bit 23:20) field. Value 7:4 Description 0h No speed negotiation restrictions 1h Limit speed negotiation to Generation 1 communication rate 2h Limit speed negotiation to Generation 2 communication rate 3h Limit speed negotiation to Generation 3 communication rate (Port 0 and Port 1 only) The PCH Supports Gen 1 communication rates (1.5 Gb/s) and Gen 2 rates (3.0 Gb/s) and Gen 3 rates (6 Gb/s). Device Detection Initialization (DET) -- R/W. Controls the PCH's device detection and interface initialization. Value 3:0 Description 0h No device detection or initialization action requested 1h Perform interface communication initialization sequence to establish communication. This is functionally equivalent to a hard reset and results in the interface being reset and communications re-initialized 4h Disable the Serial ATA interface and put Phy in offline mode All other values reserved. When this field is written to a 1h, the PCH initiates COMRESET and starts the initialization process. When the initialization is complete, this field shall remain 1h until set to another value by software. This field may only be changed to 1h or 4h when PxCMD.ST is 0. Changing this field while the PCH is running results in undefined behavior. Note: It is permissible to implement any of the Serial ATA defined behaviors for transmission of COMRESET when DET=1h. 538 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F2) 14.4.2.12 PxSERR--Port [5:0] Serial ATA Error Register (D31:F2) Address Offset: Port Port Port Port Port Port Default Value: 0: 1: 2: 3: 4: 5: ABAR ABAR ABAR ABAR ABAR ABAR + + + + + + 00000000h 130h 1B0h 230h 2B0h 330h 3B0h Attribute: R/WC Size: 32 bits Bits 26:16 of this register contain diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes. Bits 11:0 contain error information used by host software in determining the appropriate response to the error condition. If one or more of bits 11:8 of this register are set, the controller will stop the current transfer. Bit 31:27 Description Reserved 26 Exchanged (X) -- R/WC. When set to `1' this bit indicates that a change in device presence has been detected since the last time this bit was cleared. This bit shall always be set to 1 anytime a COMINIT signal is received. This bit is reflected in the P0IS.PCS bit. 25 Unrecognized FIS Type (F) -- R/WC. Indicates that one or more FISs were received by the Transport layer with good CRC, but had a type field that was not recognized. 24 Transport state transition error (T) -- R/WC. Indicates that an error has occurred in the transition from one state to another within the Transport layer since the last time this bit was cleared. 23 Link Sequence Error (S): Indicates that one or more Link state machine error conditions was encountered. The Link Layer state machine defines the conditions under which the link layer detects an erroneous transition. 22 Handshake (H) -- R/WC. Indicates that one or more R_ERR handshake response was received in response to frame transmission. Such errors may be the result of a CRC error detected by the recipient, a disparity or 8b/10b decoding error, or other error condition leading to a negative handshake on a transmitted frame. 21 CRC Error (C) -- R/WC. Indicates that one or more CRC errors occurred with the Link Layer. 20 Disparity Error (D) -- R/WC. This field is not used by AHCI. 19 10b to 8b Decode Error (B) -- R/WC. Indicates that one or more 10b to 8b decoding errors occurred. 18 Comm Wake (W) -- R/WC. Indicates that a Comm Wake signal was detected by the Phy. 17 Phy Internal Error (I) -- R/WC. Indicates that the Phy detected some internal error. 16 PhyRdy Change (N) -- R/WC. When set to 1 this bit indicates that the internal PhyRdy signal changed state since the last time this bit was cleared. In the PCH, this bit will be set when PhyRdy changes from a 0 -> 1 or a 1 -> 0. The state of this bit is then reflected in the PxIS.PRCS interrupt status bit and an interrupt will be generated if enabled. Software clears this bit by writing a 1 to it. 15:12 Reserved 11 Internal Error (E) -- R/WC. The SATA controller failed due to a master or target abort when attempting to access system memory. 10 Protocol Error (P) -- R/WC. A violation of the Serial ATA protocol was detected. Note: The PCH does not set this bit for all protocol violations that may occur on the SATA link. 9 Persistent Communication or Data Integrity Error (C) -- R/WC. A communication error that was not recovered occurred that is expected to be persistent. Persistent communications errors may arise from faulty interconnect with the device, from a device that has been removed or has failed, or a number of other causes. 8 Transient Data Integrity Error (T) -- R/WC. A data integrity error occurred that was not recovered by the interface. 7:2 Reserved. 1 Recovered Communications Error (M) -- R/WC. Communications between the device and host was temporarily lost but was re-established. This can arise from a device temporarily being removed, from a temporary loss of Phy synchronization, or from other causes and may be derived from the PhyNRdy signal between the Phy and Link layers. 0 Recovered Data Integrity Error (I) -- R/WC. A data integrity error occurred that was recovered by the interface through a retry operation or other recovery action. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 539 SATA Controller Registers (D31:F2) 14.4.2.13 PxSACT--Port [5:0] Serial ATA Active (D31:F2) Address Offset: Port Port Port Port Port Port Default Value: 0: 1: 2: 3: 4: 5: ABAR ABAR ABAR ABAR ABAR ABAR + + + + + + 134h 1B4h 234h 2B4h 334h 3B4h 00000000h Bit 31:0 14.4.2.14 Attribute: R/W Size: 32 bits Description Device Status (DS) -- R/W. System software sets this bit for SATA queuing operations prior to setting the PxCI.CI bit in the same command slot entry. This field is cleared using the Set Device Bits FIS. This field is also cleared when PxCMD.ST (ABAR+118h/198h/218h/298h:bit 0) is cleared by software, and as a result of a COMRESET or SRST. PxCI--Port [5:0] Command Issue Register (D31:F2) Address Offset: Port Port Port Port Port Port Default Value: Bit 31:0 Bit 31:0 0: 1: 2: 3: 4: 5: ABAR ABAR ABAR ABAR ABAR ABAR + + + + + + 138h 1B8h 238h 2B8h 338h 3B8h 00000000h Attribute: R/W Size: 32 bits Description Commands Issued (CI) -- R/W. This field is set by software to indicate to the PCH that a command has been built-in system memory for a command slot and may be sent to the device. When the PCH receives a FIS which clears the BSY and DRQ bits for the command, it clears the corresponding bit in this register for that command slot. Bits in this field shall only be set to '1' by software when PxCMD.ST is set to '1'. This field is also cleared when PxCMD.ST (ABAR+118h/198h/218h/298h:bit 0) is cleared by software. Description Command List Base Address Upper (CLBU) -- R/W. Indicates the upper 32-bits for the command list base address for this port. This base is used when fetching commands to execute. Note that these bits are not reset on a Controller reset. 540 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F5) 15 SATA Controller Registers (D31:F5) 15.1 PCI Configuration Registers (SATA-D31:F5) Note: Address locations that are not shown should be treated as Reserved. All of the SATA registers are in the core well. None of the registers can be locked. Table 15-1. SATA Controller PCI Register Address Map (SATA-D31:F5) (Sheet 1 of 2) Offset Mnemonic 00h-01h VID Register Name Default Type Vendor Identification 8086h RO Device Identification See register description RO 02h-03h DID 04h-05h PCICMD PCI Command 0000h R/W, RO 06h-07h PCISTS PCI Status 02B0h R/WC, RO 08h RID Revision Identification See register description RO 09h PI Programming Interface See register description See register description 0Ah SCC Sub Class Code See register description See register description 0Bh BCC Base Class Code 01h RO 0Dh PMLT Primary Master Latency Timer 10h-13h PCMD_BAR Primary Command Block Base Address 00h RO 00000001h R/W, RO 14h-17h PCNL_BAR Primary Control Block Base Address 00000001h R/W, RO 18h-1Bh SCMD_BAR Secondary Command Block Base Address 00000001h R/W, RO 1Ch-1Fh SCNL_BAR Secondary Control Block Base Address 00000001h R/W, RO 20h-23h BAR Legacy Bus Master Base Address 00000001h R/W, RO 24h-27h SIDPBA Serial ATA Index / Data Pair Base Address 00000000h See register description 2Ch-2Dh SVID Subsystem Vendor Identification 0000h R/WO 0000h R/WO 70h RO Interrupt Line 00h R/W Interrupt Pin See register description RO 2Eh-2Fh SID Subsystem Identification 34h CAP Capabilities Pointer 3Ch INT_LN 3Dh INT_PN 40h-41h IDE_TIM Primary IDE Timing Register 0000h R/W 42h-43h IDE_TIM Secondary IDE Timing Registers 0000h R/W 48h SDMA_CNT Synchronous DMA Control 00h R/W 4Ah-4Bh SDMA_TIM Synchronous DMA Timing 0000h R/W 54h-57h IDE_CONFIG IDE I/O Configuration 00000000h R/W See register description RO 4003h RO 70h-71h PID PCI Power Management Capability ID 72h-73h PC PCI Power Management Capabilities Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 541 SATA Controller Registers (D31:F5) Table 15-1. SATA Controller PCI Register Address Map (SATA-D31:F5) (Sheet 2 of 2) Offset Mnemonic 74h-75h PMCS 90h MAP Address Map 92h-93h PCS Port Control and Status A8h-ABh SATACAP0 ACh-AFh SATACAP1 B0h-B1h FLRCID FLR Capability ID B2h-B3h FLRCLV FLR Capability Length and Value 2006h RO B4h-B5h FLRCTRL FLR Control 0000h R/W, RO C0h ATC APM Trapping Control 00h R/W C4h ATS ATM Trapping Status 00h R/WC Note: 15.1.1 Register Name Default Type 0008h R/W, RO, R/WC 00h R/W 0000h R/W, RO, R/WC SATA Capability Register 0 0010B012h RO SATA Capability Register 1 00000048h RO 0009h RO PCI Power Management Control and Status The PCH SATA controller is not arbitrated as a PCI device; therefore, it does not need a master latency timer. VID--Vendor Identification Register (SATA--D31:F5) Offset Address: 00h-01h Default Value: 8086h Lockable: No Bit 15:0 15.1.2 RO 16 bit Core Description Vendor ID -- RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h DID--Device Identification Register (SATA--D31:F5) Offset Address: 02h-03h Default Value: See bit description Lockable: No Bit 15:0 542 Attribute: Size: Power Well: Attribute: Size: Power Well: RO 16 bit Core Description Device ID -- RO. This is a 16-bit value assigned to the PCH SATA controller. Note: The value of this field will change dependent upon the value of the MAP Register. See Section 15.1.28. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F5) 15.1.3 PCICMD--PCI Command Register (SATA-D31:F5) Address Offset: 04h-05h Default Value: 0000h Bit 15:11 10 9 Attribute: Size: RO, R/W 16 bits Description Reserved Interrupt Disable -- R/W. This disables pin-based INTx# interrupts. This bit has no effect on MSI operation. 0 = Internal INTx# messages are generated if there is an interrupt and MSI is not enabled. 1 = Internal INTx# messages will not be generated. Fast Back to Back Enable (FBE) -- RO. Reserved as `0'. 8 SERR# Enable (SERR_EN) -- RO. Reserved as `0'. 7 Wait Cycle Control (WCC) -- RO. Reserved as `0'. 6 Parity Error Response (PER) -- R/W. 0 = Disabled. SATA controller will not generate PERR# when a data parity error is detected. 1 = Enabled. SATA controller will generate PERR# when a data parity error is detected. 5 VGA Palette Snoop (VPS) -- RO. Reserved as `0'. 4 Postable Memory Write Enable (PMWE) -- RO. Reserved as `0'. 3 Special Cycle Enable (SCE) -- RO. Reserved as `0'. 2 Bus Master Enable (BME) -- R/W. This bit controls the PCH ability to act as a PCI master for IDE Bus Master transfers. This bit does not impact the generation of completions for split transaction commands. 1 Memory Space Enable (MSE) -- RO. This controller does not support AHCI; therefore, no memory space is required. 0 I/O Space Enable (IOSE) -- R/W. This bit controls access to the I/O space registers. 0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as well as the Bus Master I/O registers. 1 = Enable. Note that the Base Address register for the Bus Master registers should be programmed before this bit is set. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 543 SATA Controller Registers (D31:F5) 15.1.4 PCISTS -- PCI Status Register (SATA-D31:F5) Address Offset: 06h-07h Default Value: 02B0h Note: R/WC, RO 16 bits For the writable bits, software must write a `1' to clear bits that are set. Writing a `0' to the bit has no effect. Bit Description 15 Detected Parity Error (DPE) -- R/WC. 0 = No parity error detected by SATA controller. 1 = SATA controller detects a parity error on its interface. 14 Signaled System Error (SSE) -- RO. Reserved as `0'. 13 Received Master Abort (RMA) -- R/WC. 0 = Master abort Not generated. 1 = SATA controller, as a master, generated a master abort. 12 Reserved 11 Signaled Target Abort (STA) -- RO. Reserved as `0'. 10:9 DEVSEL# Timing Status (DEV_STS) -- RO. 01 = Hardwired; Controls the device select time for the SATA controller's PCI interface. 8 Data Parity Error Detected (DPED) -- R/WC. For PCH, this bit can only be set on read completions received from SiBUS where there is a parity error. 1 = SATA controller, as a master, either detects a parity error or sees the parity error line asserted, and the parity error response bit (bit 6 of the command register) is set. 7 Fast Back to Back Capable (FB2BC) -- RO. Reserved as `1'. 6 User Definable Features (UDF) -- RO. Reserved as `0'. 5 66 MHz Capable (66 MHZ_CAP) -- RO. Reserved as `1'. 4 Capabilities List (CAP_LIST) -- RO. This bit indicates the presence of a capabilities list. The minimum requirement for the capabilities list must be PCI power management for the SATA controller. 3 Interrupt Status (INTS) -- RO. Reflects the state of INTx# messages, IRQ14 or IRQ15. 0 = Interrupt is cleared (independent of the state of Interrupt Disable bit in the command register [offset 04h]). 1 = Interrupt is to be asserted 2:0 544 Attribute: Size: Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F5) 15.1.5 RID--Revision Identification Register (SATA--D31:F5) Offset Address: 08h Default Value: See bit description Attribute: Size: Bit 7:0 15.1.6 RO 8 bits Description (R) Revision ID -- RO. Refer to the Intel C600 Series Chipset and Intel(R) X79 Express Chipset Specification Update for the value of the Revision ID Register PI--Programming Interface Register (SATA-D31:F5) Address Offset: 09h Default Value: 85h Attribute: Size: RO 8 bits When SCC = 01h Bit 7 6:4 15.1.7 Description This read-only bit is a `1' to indicate that the PCH supports bus master operation Reserved. 3 Secondary Mode Native Capable (SNC) -- RO. Indicates whether or not the secondary channel has a fixed mode of operation. 0 = Indicates the mode is fixed and is determined by the (read-only) value of bit 2. This bit will always return `0'. 2 Secondary Mode Native Enable (SNE) -- RO. Determines the mode that the secondary channel is operating in. 1 = Secondary controller operating in native PCI mode. This bit will always return `1'. 1 Primary Mode Native Capable (PNC) -- RO. Indicates whether or not the primary channel has a fixed mode of operation. 0 = Indicates the mode is fixed and is determined by the (read-only) value of bit `0'. This bit will always return `0'. 0 Primary Mode Native Enable (PNE) -- RO. Determines the mode that the primary channel is operating in. 1 = Primary controller operating in native PCI mode. This bit will always return `1'. SCC--Sub Class Code Register (SATA-D31:F5) Address Offset: 0Ah Default Value: 01h Bit 7:0 Attribute: Size: RO 8 bits Description Sub Class Code (SCC) -- RO. The value of this field determines whether the controller supports legacy IDE mode. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 545 SATA Controller Registers (D31:F5) 15.1.8 BCC--Base Class Code Register (SATA-D31:F5SATA-D31:F5) Address Offset: 0Bh Default Value: 01h Bit 7:0 15.1.9 RO 8 bits Description Base Class Code (BCC) -- RO. 01h = Mass storage device PMLT--Primary Master Latency Timer Register (SATA-D31:F5) Address Offset: 0Dh Default Value: 00h Bit 7:0 15.1.10 Attribute: Size: Attribute: Size: RO 8 bits Description Master Latency Timer Count (MLTC) -- RO. 00h = Hardwired. The SATA controller is implemented internally, and is not arbitrated as a PCI device, so it does not need a Master Latency Timer. PCMD_BAR--Primary Command Block Base Address Register (SATA-D31:F5) Address Offset: 10h-13h Default Value: 00000001h Attribute: Size: R/W, RO 32 bits . Bit 31:16 15:3 2:1 0 Note: 15.1.11 Description Reserved Base Address -- R/W. This field provides the base address of the I/O space (8 consecutive I/O locations). Reserved Resource Type Indicator (RTE) -- RO. Hardwired to `1' to indicate a request for I/O space. This 8-byte I/O space is used in native mode for the Primary Controller's Command Block. PCNL_BAR--Primary Control Block Base Address Register (SATA-D31:F5) Address Offset: 14h-17h Default Value: 00000001h Attribute: Size: R/W, RO 32 bits . Bit 31:16 15:2 Reserved Base Address -- R/W. This field provides the base address of the I/O space (4 consecutive I/O locations). 1 Reserved 0 Resource Type Indicator (RTE) -- RO. Hardwired to `1' to indicate a request for I/O space. Note: 546 Description This 4-byte I/O space is used in native mode for the Primary Controller's Command Block. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F5) 15.1.12 SCMD_BAR--Secondary Command Block Base Address Register (IDE D31:F1) Address Offset: 18h-1Bh Default Value: 00000001h Bit 31:16 15:3 2:1 0 Note: 15.1.13 R/W, RO 32 bits Description Reserved Base Address -- R/W. This field provides the base address of the I/O space (8 consecutive I/O locations). Reserved Resource Type Indicator (RTE) -- RO. Hardwired to `1' to indicate a request for I/O space. This 8-byte I/O space is used in native mode for the Secondary Controller's Command Block. SCNL_BAR--Secondary Control Block Base Address Register (IDE D31:F1) Address Offset: 1Ch-1Fh Default Value: 00000001h Bit 31:16 15:2 Attribute: Size: R/W, RO 32 bits Description Reserved Base Address -- R/W. This field provides the base address of the I/O space (4 consecutive I/O locations). 1 Reserved 0 Resource Type Indicator (RTE) -- RO. Hardwired to `1' to indicate a request for I/O space. Note: 15.1.14 Attribute: Size: This 4-byte I/O space is used in native mode for the Secondary Controller's Command Block. BAR -- Legacy Bus Master Base Address Register (SATA-D31:F5) Address Offset: 20h-23h Default Value: 00000001h Attribute: Size: R/W, RO 32 bits The Bus Master IDE interface function uses Base Address register 5 to request a 16byte I/O space to provide a software interface to the Bus Master functions. Only 12 bytes are actually used (6 bytes for primary, 6 bytes for secondary). Only bits [15:4] are used to decode the address. Bit 31:16 15:5 4 3:1 0 Description Reserved Base Address -- R/W. This field provides the base address of the I/O space (16 consecutive I/O locations). Base Address 4 (BA4)-- R/W. When SCC is 01h, this bit will be R/W resulting in requesting 16B of I/O space. Reserved Resource Type Indicator (RTE) -- RO. Hardwired to 1 to indicate a request for I/O space. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 547 SATA Controller Registers (D31:F5) 15.1.15 SIDPBA -- SATA Index/Data Pair Base Address Register (SATA-D31:F5) Address Offset: 24h-27h Default Value: 00000000h Attribute: Size: R/W, RO 32 bits When SCC is 01h When the programming interface is IDE, the register represents an I/O BAR allocating 16B of I/O space for the I/O mapped registers defined in Section 15.3. Note that although 16B of locations are allocated, some maybe reserved. Bit 31:16 15:4 3:1 0 15.1.16 Description Reserved Base Address (BA) -- R/W. Base address of register I/O space Reserved Resource Type Indicator (RTE) -- RO. Hardwired to 1 to indicate a request for I/O space. SVID--Subsystem Vendor Identification Register (SATA-D31:F5) Address Offset: 2Ch-2Dh Default Value: 0000h Lockable: No Function Level Reset: No Bit 15:0 15.1.17 Subsystem Vendor ID (SVID) -- R/WO. Value is written by BIOS. No hardware action taken on this value. SID--Subsystem Identification Register (SATA-D31:F5) Attribute: Size: Power Well: R/WO 16 bits Core Bit Description 15:0 Subsystem ID (SID) -- R/WO. Value is written by BIOS. No hardware action taken on this value. CAP--Capabilities Pointer Register (SATA-D31:F5) Address Offset: 34h Default Value: 70h Bit 7:0 548 R/WO 16 bits Core Description Address Offset: 2Eh-2Fh Default Value: 0000h Lockable: No 15.1.18 Attribute: Size: Power Well: Attribute: Size: RO 8 bits Description Capabilities Pointer (CAP_PTR) -- RO. Indicates that the first capability pointer offset is 70h if the Sub Class Code (SCC) (Dev 31:F2:0Ah) is configure as IDE mode (value of 01). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F5) 15.1.19 INT_LN--Interrupt Line Register (SATA-D31:F5) Address Offset: 3Ch Default Value: 00h Function Level Reset: No Bit 7:0 15.1.20 R/W 8 bits Description Interrupt Line -- R/W. This field is used to communicate to software the interrupt line that the interrupt pin is connected to. These bits are not reset by FLR. INT_PN--Interrupt Pin Register (SATA-D31:F5) Address Offset: 3Dh Default Value: See Register Description Bit 7:0 15.1.21 Attribute: Size: Attribute: Size: RO 8 bits Description Interrupt Pin -- RO. This reflects the value of D31IP.SIP1 (Chipset Config Registers:Offset 3100h:bits 11:8). IDE_TIM -- IDE Timing Register (SATA-D31:F5) Address Offset: Primary: 40h-41h Secondary: 42h-43h Default Value: 0000h Attribute: R/W Size: 16 bits Bits 14:12 and 9:0 of this register are R/W to maintain software compatibility. These bits have no effect on hardware. Bit 15 Description IDE Decode Enable (IDE) -- R/W. Individually enable/disable the Primary or Secondary decode. 0 = Disable. 1 = Enables the PCH to decode the associated Command Blocks (1F0-1F7h for primary, 170-177h for secondary) and Control Block (3F6h for primary and 376h for secondary). This bit effects the IDE decode ranges for both legacy and native-Mode decoding. Note: This bit affects SATA operation in both combined and non-combined ATA modes. See Section 5.17 for more on ATA modes of operation. 14:12 IDE_TIM Field 2 -- R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. 11:10 Reserved 9:0 IDE_TIM Field 1 -- R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 549 SATA Controller Registers (D31:F5) 15.1.22 SDMA_CNT--Synchronous DMA Control Register (SATA-D31:F5) Address Offset: 48h Default Value: 00h Note: Description 7:4 Reserved 3:0 SDMA_CNT Field 1 -- R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. SDMA_TIM--Synchronous DMA Timing Register (SATA-D31:F5) Address Offset: 4Ah-4Bh Default Value: 0000h Note: Attribute: Size: R/W 16 bits This register is R/W to maintain software compatibility. These bits have no effect on hardware. Bit 15:10 550 R/W 8 bits This register is R/W to maintain software compatibility. These bits have no effect on hardware. Bit 15.1.23 Attribute: Size: Description Reserved 9:8 SDMA_TIM Field 2-- R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. 7:2 Reserved 1:0 SDMA_TIM Field 1 -- R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F5) 15.1.24 IDE_CONFIG--IDE I/O Configuration Register (SATA-D31:F5) Address Offset: 54h-57h Default Value: 00000000h Note: Description 31:24 Reserved 23:16 IDE_CONFIG Field 6 -- R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. 15 Reserved 14 IDE_CONFIG Field 5 -- R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. 13 Reserved 12 IDE_CONFIG Field 4 -- R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. 11:8 7:4 Reserved IDE_CONFIG Field 3 -- R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. 3 Reserved 2 IDE_CONFIG Field 2 -- R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. 1 Reserved 0 IDE_CONFIG Field 1 -- R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. PID--PCI Power Management Capability Identification Register (SATA-D31:F5) Address Offset: 70h-71h Default Value: B001h Bits 15:8 7:0 15.1.26 R/W 32 bits This register is R/W to maintain software compatibility. These bits have no effect on hardware. Bit 15.1.25 Attribute: Size: Attribute: Size: RO 16 bits Description Next Capability (NEXT) -- RO. When SCC is 01h, this field will be B0h indicating the next item is FLR Capability Pointer in the list. Capability ID (CID) -- RO. Indicates that this pointer is a PCI power management. PC--PCI Power Management Capabilities Register (SATA-D31:F5) Address Offset: 72h-73h Default Value: 4003h Attribute: Size: RO 16 bits f Bits Description 15:11 PME Support (PME_SUP) -- RO. By default with SCC = 01h, the default value of `00000' indicates no PME support in IDE mode. 10 D2 Support (D2_SUP) -- RO. Hardwired to `0'. The D2 state is not supported 9 D1 Support (D1_SUP) -- RO. Hardwired to `0'. The D1 state is not supported Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 551 SATA Controller Registers (D31:F5) Bits Description 8:6 Auxiliary Current (AUX_CUR) -- RO. PME# from D3COLD state is not supported, therefore this field is 000b. 5 4 Reserved 3 PME Clock (PME_CLK) -- RO. Hardwired to `0' to indicate that PCI clock is not required to generate PME#. 2:0 15.1.27 Device Specific Initialization (DSI) -- RO. Hardwired to `0' to indicate that no device-specific initialization is required. Version (VER) -- RO. Hardwired to `011' to indicates support for Revision 1.2 of the PCI Power Management Specification. PMCS--PCI Power Management Control and Status Register (SATA-D31:F5) Address Offset: 74h-75h Attribute: Default Value: 0008h Size: Function Level Reset:No (Bits 8 and 15 only) Bits Description 15 PME Status (PMES) -- R/WC. Bit is set when a PME event is to be requested, and if this bit and PMEE is set, a PME# will be generated from the SATA controller. Note: When SCC=01h this bit will be RO `0'. Software is advised to clear PMEE together with PMES prior to changing SCC through MAP.SMS. This bit is not reset by Function Level Reset. 14:9 8 7:4 Reserved PME Enable (PMEE) -- R/W. When SCC is not 01h, this bit R/W. When set, the SATA controller generates PME# form D3HOT on a wake event. Note: When SCC=01h this bit will be RO `0'. Software is advised to clear PMEE together with PMES prior to changing SCC through MAP.SMS. This bit is not reset by Function Level Reset. Reserved 3 No Soft Reset (NSFRST) -- RO. These bits are used to indicate whether devices transitioning from D3HOT state to D0 state will perform an internal reset. 0 = Device transitioning from D3HOT state to D0 state perform an internal reset. 1 = Device transitioning from D3HOT state to D0 state do not perform an internal reset. Configuration content is preserved. Upon transition from the D3HOT state to D0 state initialized state, no additional operating system intervention is required to preserve configuration context beyond writing to the PowerState bits. Regardless of this bit, the controller transition from D3HOT state to D0 state by a system or bus segment reset will return to the state D0 uninitialized with only PME context preserved if PME is supported and enabled. 2 Reserved 1:0 15.1.28 Power State (PS) -- R/W. These bits are used both to determine the current power state of the SATA controller and to set a new power state. 00 = D0 state 11 = D3HOT state When in the D3HOT state, the controller's configuration space is available, but the I/O and memory spaces are not. Additionally, interrupts are blocked. MAP--Address Map Register (SATA-D31:F5)16 Address Offset: 90h Attribute: Default Value: 00h Size: Function Level Reset: No (Bits 9:8 only) 552 RO, R/W, R/WC 16 bits R/W, R/WO, RO bits Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F5) Bits 15:8 15.1.29 Description Reserved. 7:6 SATA Mode Select (SMS) -- R/W. Software programs these bits to control the mode in which the SATA Controller should operate. 00b = IDE Mode All other combinations are reserved. 5:2 Reserved. 1:0 Map Value (MV)-- Reserved. PCS--Port Control and Status Register (SATA-D31:F5) Address Offset: 92h-93h Default Value: 0000h Function Level Reset: No Attribute: Size: R/W, RO 16 bits By default, the SATA ports are set to the disabled state (bits [5:0] = `0'). When enabled by software, the ports can transition between the on, partial, and slumber states and can detect devices. When disabled, the port is in the "off" state and cannot detect any devices. If an AHCI-aware or RAID enabled operating system is being booted then system BIOS shall insure that all supported SATA ports are enabled prior to passing control to the OS. Once the AHCI aware OS is booted it becomes the enabling/disabling policy owner for the individual SATA ports. This is accomplished by manipulating a port's PxSCTL and PxCMD fields. Because an AHCI or RAID aware OS will typically not have knowledge of the PxE bits and because the PxE bits act as master on/off switches for the ports, preboot software must insure that these bits are set to `1' prior to booting the OS, regardless as to whether or not a device is currently on the port. Bits 15:10 Description Reserved 9 Port 5 Present (P5P) -- RO. The status of this bit may change at any time. This bit is cleared when the port is disabled using P1E. This bit is not cleared upon surprise removal of a device. 0 = No device detected. 1 = The presence of a device on Port 1 has been detected. 8 Port 4 Present (P4P) -- RO. The status of this bit may change at any time. This bit is cleared when the port is disabled using P0E. This bit is not cleared upon surprise removal of a device. 0 = No device detected. 1 = The presence of a device on Port 0 has been detected. 7:2 Reserved 1 Port 5 Enabled (P5E) -- R/W. 0 = Disabled. The port is in the `off' state and cannot detect any devices. 1 = Enabled. The port can transition between the on, partial, and slumber states and can detect devices. This bit is read-only `0' when MAP.SPD[1]= 1. 0 Port 4 Enabled (P4E) -- R/W. 0 = Disabled. The port is in the `off' state and cannot detect any devices. 1 = Enabled. The port can transition between the on, partial, and slumber states and can detect devices. This bit is read-only `0' when MAP.SPD[0]= 1. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 553 SATA Controller Registers (D31:F5) 15.1.30 SATACR0-- SATA Capability Register 0 (SATA-D31:F5) Address Offset: A8h-ABh Default Value: 0010B012h Function Level Reset: No (Bits 15:8 only) Note: Attribute: Size: RO, R/WO 32 bits When SCC is 01h this register is read-only 0. . Bit 31:24 Reserved. 23:20 Major Revision (MAJREV) -- RO. Major revision number of the SATA Capability Pointer implemented. 19:16 Minor Revision (MINREV) -- RO. Minor revision number of the SATA Capability Pointer implemented. 15:8 7:0 15.1.31 Description Next Capability Pointer (NEXT) -- R/WO. Points to the next capability structure. Capability ID (CAP) -- RO. The value of 12h has been assigned by the PCI SIG to designate the SATA capability pointer. SATACR1-- SATA Capability Register 1 (SATA-D31:F5) Address Offset: ACh-AFh Default Value: 00000048h Attribute: Size: RO 32 bits When SCC is 01h this register is read-only 0. . Bit 31:16 15.1.32 Description Reserved. 15:4 BAR Offset (BAROFST) -- RO. Indicates the offset into the BAR where the index/Data pair are located (in DWord granularity). The index and Data I/O registers are located at offset 10h within the I/O space defined by LBAR (BAR4). A value of 004h indicates offset 10h. 3:0 BAR Location (BARLOC) -- RO. Indicates the absolute PCI Configuration Register address of the BAR containing the Index/Data pair (in DWord granularity). The Index and Data I/O registers reside within the space defined by LBAR (BAR4) in the SATA controller. a value of 8h indicates and offset of 20h, which is LBAR (BAR4). FLRCID-- FLR Capability ID (SATA-D31:F5) Address Offset: B0h-B1h Default Value: 0009h Attribute: Size: RO 16 bits . Bit 15:8 7:0 554 Description Next Capability Pointer -- RO. A value of 00h indicates the final item in the Capability List. Capability ID -- RO. The value of this field depends on the FLRCSSECL bit. If FLRCSSEL = 0, this field is 13h If FLRCSSEL = 1, this field is 09h, indicating vendor specific capability. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F5) 15.1.33 FLRCLV-- FLR Capability Length and Value (SATA-D31:F5) Address Offset: B2h-B3h Default Value: 2006h Function Level Reset:No (Bits 9:8 only) Attribute: Size: RO, R/WO 16 bits When FLRCSSEL = `0' , this register is defined as follows. Bit 15:10 Description Reserved. 9 FLR Capability -- R/WO. This field indicates support for Function Level Reset. 8 TXP Capability -- R/WO. This field indicates support for the Transactions Pending (TXP) bit. TXP must be supported if FLR is supported. 7:0 Capability Length -- RO. This field indicates the number of bytes of the Vendor Specific capability as required by the PCI spec. It has the value of 06h for FLR Capability. When FLRCSSEL = `1' , this register is defined as follows. Bit 15:12 11:8 7:0 15.1.34 Description Vendor Specific Capability ID -- RO. A value of 02h identifies this capability as a Function Level Reset. Capability Version -- RO. This field indicates the version of the FLR capability. Capability Length -- RO. This field indicates the number of bytes of the Vendor Specific capability as required by the PCI spec. It has the value of 06h for FLR Capability. FLRCTRL-- FLR Control (SATA-D31:F5) Address Offset: B4h-B5h Default Value: 0000h Bit 15:9 8 7:1 0 15.1.35 R/W, RO 16 bits Description Reserved. Transactions Pending (TXP) -- RO. 0 = Completions for all Non-Posted requests have been received by the controller. 1 = Controller has issued Non-Posted request which has not been completed. Reserved. Initiate FLR -- R/W. Used to initiate FLR transition. A write of `1' indicates FLR transition. ATS--APM Trapping Status Register (SATA-D31:F5) Address Offset: C0h Default Value: 00h Note: Attribute: Size: Attribute: Size: R/W 8 bits This SATA controller does not support legacy I/O access. Therefore, this register is reserved. Software shall not change the default values of the register; otherwise, the result will be undefined. . Bit 7:0 Description Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 555 SATA Controller Registers (D31:F5) 15.1.36 ATC--APM Trapping Control (SATA-D31:F5) Address Offset: C4h Default Value: 00h Note: Attribute: Size: R/WC 8 bits This SATA controller does not support legacy I/O access. Therefore, this register is reserved. Software shall not change the default values of the register; otherwise, the result will be undefined. . Bit 7:0 15.2 Description Reserved Bus Master IDE I/O Registers (D31:F5) The bus master IDE function uses 16 bytes of I/O space, allocated using the BAR register, located in Device 31:Function 2 Configuration space, offset 20h. All bus master IDE I/O space registers can be accessed as byte, word, or DWord quantities. Reading reserved bits returns an indeterminate, inconsistent value, and writes to reserved bits have no affect (but should not be attempted). These registers are only used for legacy operation. Software must not use these registers when running AHCI. The description of the I/O registers is shown in Table 15-2. Table 15-2. Bus Master IDE I/O Register Address Map BAR+ Offset Mnemonic 00 BMICP 01 -- 02 556 BMISP 03 -- 04-07 BMIDP 08 BMICS 09 -- 0Ah BMISS 0Bh -- 0Ch-0Fh BMIDS Register Command Register Primary Reserved Bus Master IDE Status Register Primary Reserved Bus Master IDE Descriptor Table Pointer Primary Command Register Secondary Reserved Bus Master IDE Status Register Secondary Reserved Bus Master IDE Descriptor Table Pointer Secondary Default Type 00h R/W -- RO 00h R/W, R/WC, RO -- RO xxxxxxxxh R/W 00h R/W -- RO 00h R/W, R/WC, RO -- RO xxxxxxxxh R/W Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F5) 15.2.1 BMIC[P,S]--Bus Master IDE Command Register (D31:F5) Address Offset: Primary: BAR + 00h Secondary: BAR + 08h Default Value: 00h Bit 7:4 3 2:1 0 R/W Size: 8 bits Description Reserved. Read / Write Control (R/WC) -- R/W. This bit sets the direction of the bus master transfer: This bit must NOT be changed when the bus master function is active. 0 = Memory reads 1 = Memory writes Reserved. Start/Stop Bus Master (START) -- R/W. 0 = All state information is lost when this bit is cleared. Master mode operation cannot be stopped and then resumed. If this bit is reset while bus master operation is still active (that is, the Bus Master IDE Active bit (D31:F5:BAR + 02h, bit 0) of the Bus Master IDE Status register for that IDE channel is set) and the drive has not yet finished its data transfer (the Interrupt bit in the Bus Master IDE Status register for that IDE channel is not set), the bus master command is said to be aborted and data transferred from the drive may be discarded instead of being written to system memory. 1 = Enables bus master operation of the controller. Bus master operation does not actually start unless the Bus Master Enable bit (D31:F1:04h, bit 2) in PCI configuration space is also set. Bus master operation begins when this bit is detected changing from `0' to `1'. The controller will transfer data between the IDE device and memory only when this bit is set. Master operation can be halted by writing a `0' to this bit. Note: 15.2.2 Attribute: This bit is intended to be cleared by software after the data transfer is completed, as indicated by either the Bus Master IDE Active bit being cleared or the Interrupt bit of the Bus Master IDE Status register for that IDE channel being set, or both. Hardware does not clear this bit automatically. If this bit is cleared to `0' prior to the DMA data transfer being initiated by the drive in a device to memory data transfer, then the PCH will not send DMAT to terminate the data transfer. SW intervention (for example, sending SRST) is required to reset the interface in this condition. BMIS[P,S]--Bus Master IDE Status Register (D31:F5) Address Offset: Primary: BAR + 02h Secondary: BAR + 0Ah Default Value: 00h Bit Attribute: R/W, R/WC, RO Size: 8 bits Description 7 PRD Interrupt Status (PRDIS) -- R/WC. 0 = Software clears this bit by writing a `1' to it. 1 = This bit is set when the host controller execution of a PRD that has its PRD_INT bit set. 6 Reserved. 5 Drive 0 DMA Capable -- R/W. 0 = Not Capable 1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 0 for this channel is capable of DMA transfers, and that the controller has been initialized for optimum performance. The PCH does not use this bit. It is intended for systems that do not attach BMIDE to the PCI bus. 4:3 Reserved. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 557 SATA Controller Registers (D31:F5) Bit 15.2.3 Description 2 Interrupt -- R/WC. 0 = Software clears this bit by writing a `1' to it. 1 = Set when a device FIS is received with the `I' bit set, provided that software has not disabled interrupts using the IEN bit of the Device Control Register (see Chapter 5 of the Serial ATA Specification, Revision 1.0a). 1 Error -- R/WC. 0 = Software clears this bit by writing a `1' to it. 1 = This bit is set when the controller encounters a target abort or master abort when transferring data on PCI. 0 Bus Master IDE Active (ACT) -- RO. 0 = This bit is cleared by the PCH when the last transfer for a region is performed, where EOT for that region is set in the region descriptor. It is also cleared by the PCH when the Start Bus Master bit (D31:F5:BAR+ 00h, bit 0) is cleared in the Command register. When this bit is read as a 0, all data transferred from the drive during the previous bus master command is visible in system memory, unless the bus master command was aborted. 1 = Set by the PCH when the Start bit is written to the Command register. BMID[P,S]--Bus Master IDE Descriptor Table Pointer Register (D31:F5) Address Offset: Primary: BAR + 04h-07h Attribute: Secondary: BAR + 0Ch-0Fh Default Value: All bits undefined Size: 32 bits Bit Description 31:2 Address of Descriptor Table (ADDR) -- R/W. The bits in this field correspond to bits [31:2] of the memory location of the Physical Region Descriptor (PRD). The Descriptor Table must be DWordaligned. The Descriptor Table must not cross a 64-K boundary in memory. 1:0 15.3 R/W Reserved Serial ATA Index/Data Pair Superset Registers All of these I/O registers are in the core well. They are exposed only when SCC is 01h (that is, IDE programming interface) and the controller is not in combined mode. These are Index/Data Pair registers that are used to access the SerialATA superset registers (SerialATA Status, SerialATA Control and SerialATA Error). The I/O space for these registers is allocated through SIDPBA. Locations with offset from 08h to 0Fh are reserved for future expansion. Software-write operations to the reserved locations shall have no effect while software-read operations to the reserved locations shall return `0'. 15.3.1 SINDX--SATA Index Register (D31:F5) Address Offset: SIDPBA + 00h Default Value: 00000000h Note: 558 Attribute: Size: R/W 32 bits These are Index/Data Pair Registers that are used to access the SSTS, SCTL, and SERR. The I/O space for these registers is allocated through SIDPBA. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F5) Bit 31:16 15:8 7:0 15.3.2 Description Reserved Port Index (PIDX)-- R/W: This Index field is used to specify the port of the SATA controller at which the port-specific SSTS, SCTL, and SERR registers are located. 00h = Primary Master (Port 4) 02h = Secondary Master (Port 5) All other values are Reserved. Register Index (RIDX)-- R/W: This Index field is used to specify one out of three registers currently being indexed into. 00h = SSTS 01h = SCTL 02h = SERR All other values are Reserved SDATA--SATA Index Data Register (D31:F5) Address Offset: SIDPBA + 04h Default Value: All bits undefined Note: 15.3.2.1 Attribute: Size: R/W 32 bits These are Index/Data Pair Registers that are used to access the SSTS, SCTL, and SERR. The I/O space for these registers is allocated through SIDPBA. Bit Description 31:0 Data (DATA)-- R/W: This Data register is a "window" through which data is read or written to the memory mapped registers. A read or write to this Data register triggers a corresponding read or write to the memory mapped register pointed to by the Index register. The Index register must be setup prior to the read or write to this Data register. Note that a physical register is not actually implemented as the data is actually stored in the memory mapped registers. Since this is not a physical register, the "default" value is the same as the default value of the register pointed to by Index. PxSSTS--Serial ATA Status Register (D31:F5) Address Offset: Default Value: 00000000h Attribute: Size: RO 32 bits SDATA when SINDX.RIDX is 00h. This is a 32-bit register that conveys the current state of the interface and host. The PCH updates it continuously and asynchronously. When the PCH transmits a COMRESET to the device, this register is updated to its reset values. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 559 SATA Controller Registers (D31:F5) Bit 31:12 Description Reserved Interface Power Management (IPM) -- RO. Indicates the current interface state: Value 11:8 Description 0h Device not present or communication not established 1h Interface in active state 2h Interface in PARTIAL power management state 6h Interface in SLUMBER power management state All other values reserved. Current Interface Speed (SPD) -- RO. Indicates the negotiated interface communication speed. Value 7:4 Description 0h Device not present or communication not established 1h Generation 1 communication rate negotiated 2h Generation 2 communication rate negotiated All other values reserved. The PCH Supports Gen 1 communication rates (1.5 Gb/s) and Gen 2 rates (3.0 Gb/s). Device Detection (DET) -- RO. Indicates the interface device detection and Phy state: Value 3:0 Description 0h No device detected and Phy communication not established 1h Device presence detected but Phy communication not established 3h Device presence detected and Phy communication established 4h Phy in offline mode as a result of the interface being disabled or running in a BIST loopback mode All other values reserved. 15.3.2.2 PxSCTL -- Serial ATA Control Register (D31:F5) Address Offset: Default Value: 00000004h Attribute: Size: R/W, RO 32 bits SDATA when SINDX.RIDX is 01h. This is a 32-bit read-write register by which software controls SATA capabilities. Writes to the SControl register result in an action being taken by the PCH or the interface. Reads from the register return the last value written to it. Bit 560 Description 31:20 Reserved 19:16 Port Multiplier Port (PMP) -- RO. This field is not used by AHCI. 15:12 Select Power Management (SPM) -- RO. This field is not used by AHCI. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SATA Controller Registers (D31:F5) Bit Description Interface Power Management Transitions Allowed (IPM) -- R/W. Indicates which power states the PCH is allowed to transition to: Value 11:8 Description 0h No interface restrictions 1h Transitions to the PARTIAL state disabled 2h Transitions to the SLUMBER state disabled 3h Transitions to both PARTIAL and SLUMBER states disabled All other values reserved Speed Allowed (SPD) -- R/W. Indicates the highest allowable speed of the interface. This speed is limited by the CAP.ISS (ABAR+00h:bit 23:20) field. Value 7:4 Description 0h No speed negotiation restrictions 1h Limit speed negotiation to Generation 1 communication rate 2h Limit speed negotiation to Generation 2 communication rate All other values reserved. The PCH Supports Gen 1 communication rates (1.5 Gb/s) and Gen 2 rates (3.0 Gb/s). Device Detection Initialization (DET) -- R/W. Controls the PCH's device detection and interface initialization. Value Description 0h No device detection or initialization action requested 1h Perform interface communication initialization sequence to establish communication. This is functionally equivalent to a hard reset and results in the interface being reset and communications re-initialized 4h Disable the Serial ATA interface and put Phy in offline mode 3:0 All other values reserved. 15.3.2.3 PxSERR--Serial ATA Error Register (D31:F5) Address Offset: Default Value: 00000000h Attribute: Size: R/WC 32 bits SDATA when SINDx.RIDX is 02h. Bits 26:16 of this register contains diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes. Bits 11:0 contain error information used by host software in determining the appropriate response to the error condition. If one or more of bits 11:8 of this register are set, the controller will stop the current transfer. Bit 31:27 Description Reserved 26 Exchanged (X) -- R/WC. When set to `1' this bit indicates that a change in device presence has been detected since the last time this bit was cleared. This bit shall always be set to 1' anytime a COMINIT signal is received. This bit is reflected in the P0IS.PCS bit. 25 Unrecognized FIS Type (F) -- R/WC. Indicates that one or more FISs were received by the Transport layer with good CRC, but had a type field that was not recognized. 24 Transport state transition error (T) -- R/WC. Indicates that an error has occurred in the transition from one state to another within the Transport layer since the last time this bit was cleared. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 561 SATA Controller Registers (D31:F5) Bit Description 23 Link Sequence Error (S): Indicates that one or more Link state machine error conditions was encountered. The Link Layer state machine defines the conditions under which the link layer detects an erroneous transition. 22 Handshake (H) -- R/WC. Indicates that one or more R_ERR handshake response was received in response to frame transmission. Such errors may be the result of a CRC error detected by the recipient, a disparity or 8b/10b decoding error, or other error condition leading to a negative handshake on a transmitted frame. 21 CRC Error (C) -- R/WC. Indicates that one or more CRC errors occurred with the Link Layer. 20 Disparity Error (D) -- R/WC. This field is not used by AHCI. 19 10b to 8b Decode Error (B) -- R/WC. Indicates that one or more 10b to 8b decoding errors occurred. 18 Comm Wake (W) -- R/WC. Indicates that a Comm Wake signal was detected by the Phy. 17 Phy Internal Error (I) -- R/WC. Indicates that the Phy detected some internal error. 16 PhyRdy Change (N) -- R/WC. When set to `1' this bit indicates that the internal PhyRdy signal changed state since the last time this bit was cleared. In the PCH, this bit will be set when PhyRdy changes from a 0 --> 1 or a 1 --> 0. The state of this bit is then reflected in the PxIS.PRCS interrupt status bit and an interrupt will be generated if enabled. Software clears this bit by writing a `1' to it. 15:12 Reserved 11 Internal Error (E) -- R/WC. The SATA controller failed due to a master or target abort when attempting to access system memory. 10 Protocol Error (P) -- R/WC. A violation of the Serial ATA protocol was detected. Note: The PCH does not set this bit for all protocol violations that may occur on the SATA link. 9 Persistent Communication or Data Integrity Error (C) -- R/WC. A communication error that was not recovered occurred that is expected to be persistent. Persistent communications errors may arise from faulty interconnect with the device, from a device that has been removed or has failed, or a number of other causes. 8 Transient Data Integrity Error (T) -- R/WC. A data integrity error occurred that was not recovered by the interface. 7:2 Reserved. 1 Recovered Communications Error (M) -- R/WC. Communications between the device and host was temporarily lost but was re-established. This can arise from a device temporarily being removed, from a temporary loss of Phy synchronization, or from other causes and may be derived from the PhyNRdy signal between the Phy and Link layers. 0 Recovered Data Integrity Error (I) -- R/WC. A data integrity error occurred that was recovered by the interface through a retry operation or other recovery action. 562 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) The following sections describe the SCU PCI Configuration registers with support for SR-IOV as defined by the Single Root I/O Virtualization and Sharing Specification, Revision 1.1. The SCU includes a single PF configuration space with an SR-IOV extended capability that references up to 31 VF configuration spaces. Regardless of the SCU type (Single-SCU or Dual-SCU) the SCU always appears to SW as a single Physical function with support for SR-IOV as defined by the Single Root I/O Virtualization and Sharing Specification. For Physical and Virtual Function Configuration Register definitions, refer to Section 16.2 and Section 16.3 respectively. 16.1 Register Attribute Definitions Table 16-3. Register Base Attribute Definitions Attr Description RO Read Only: These bits can only be read by software, writes have no effect. The value of the bits is determined by the hardware only. R/W R/W1C Read / Write: These bits can be read and written by software. Read / Write 1 to Clear: These bits can be read and cleared by software. Writing a `1' to a bit clears it, while writing a `0' to a bit has no effect. Hardware sets these bits. WO Write Only: These bits can only be written by software, reads return zero. Note: Use of this attribute type is deprecated and can only be used to describe bits without persistent state. RC Read Clear: These bits can only be read by software, but a read causes the bits to be cleared. Hardware sets these bits. Note: Use of this attribute type is only allowed on legacy functions, as side-effects on reads are not desirable. RCW Read Clear / Write: These bits can be read and written by software, but a read causes the bits to be cleared. Note: Use of this attribute type is only allowed on legacy functions, as side-effects on reads are not desirable. RV Reserved: These bits are reserved for future expansion and their value must not be modified by software. When writing these bits, software must preserve the value read. The bits are read-only must return `0' when read. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 563 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.1.1 Address Attribute Modifier Definitions Following are the definitions of Address Attribute Modifies used in this section Attribute Modifiers specify additional information about the behavior of register bits when used in conjunction with applicable Base Attributes. Bits without a Sticky attribute modifier are set to their default value by a hard reset. Table 16-4. Register Attribute Modifier Definitions Attr Modifier Applicable Attr Description S RO (w/ -V), R/W, R/W1C Sticky: These bits are only re-initialized to their default value by a PWRGD reset. Note: Does not apply to RO (constant) bits. -K R/W, WO Key: These bits control the ability to write other bits (identified with a `Lock' modifier). -L R/W, WO Lock: Hardware can make these bits "Read Only" using a separate configuration bit or other logic. Note: Mutually exclusive with `Once' modifier. Note: BIOS must ensure that all registers having -L attribute are programmed correctly. -O R/W, WO Once: After reset, these bits can only be written by software once, after which the bits becomes "Read Only". Note: Mutually exclusive with `Lock' modifier and does not make sense with `Variant' or `Restricted' modifiers. -R R/W Restricted: On a write, the value of these bits may differ from what is provided by software. Note: The use of this modifier should be limited to only where absolutely necessary. -V RO, R/W Variant: The value of these bits can be updated by hardware. Note: R/W1C and RC bits are variant by definition and therefore do not need to be modified. Modifiers without a leading dash are appended to the end of the Base Attribute for compatibility with industry specs. Modifiers with a leading dash are appended (in alphabetical order) after a single dash when more than one apply. Some Modifiers may be used together to accurately describe the register bit behavior. Table 16-5. Register Domain Definitions Attr S PRST FLR 564 Description Sticky: These bits are only re-initialized to their default value by a PWRGD reset. Primary Reset: These bits are only re-initialized to their default value by a PWRGD or Primary reset signal. These bits are not reset on Secondary bus reset. Function Level Reset: In addition to their "normal" reset behavior, these bits are also reinitialized to their default value by a Function Level Reset (initiated by setting the Initiate Function Level Reset bit in Section 16.2.4.5 for the PF or in Section 16.3.3.5 for the VF. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2 SCU Physical Function Configuration Registers Table 16-6. SCU PF PCI Configuration Registers (Sheet 1 of 2) Configuration Address Offset Mnemonic and Register Name Default Attribute +000H SCUPVID -- SCU PF Vendor ID Register 8086h RO +002H SCUPDID -- SCU PF Device ID Register See bit description RO +004H SCUPCMD -- SCU PF Command Register +006H SCUPSR -- SCU PF Device Status Register 0000h RV, RO,R/W See bit description RV, RO, R/W1C +008H +009H SCUPRID -- SCU PF Revision ID Register 00h RO SCUPCCR -- SCU PF Class Code Register 10700h +00CH RO SCUPCLSR -- SCU PF Cacheline Size Register 00h R/W +00DH SCUPLT -- SCU PF Latency Timer Register 00h RO +00EH SCUPHTR -- SCU PF Header Type Register 00h RO +00FH SCUPBISTR -- SCU PF BIST Register 00h RV,RO See bit description RV, RO, R/W +010H SCUPBAR0 -- SCU PF Base Address Register 0 +014H SCUPUBAR0 -- SCU PF Upper Base Address Register 0 +018H SCUPBAR1 -- SCU PF Base Address Register 1 +01CH SCUPUBAR1 -- SCU PF Upper Base Address Register 1 0h R/W +020H SCUPBAR2 -- SCU PF Base Address Register 2 1h RO, R/W 0h R/W See bit description RV, RO, R/W +02CH SPSVIR -- SCU PF Subsystem Vendor ID Register 0h R/W +02EH SPSIR -- SCU PF Subsystem ID Register 0h R/W +030H PERBAR -- SCU PF Expansion ROM Base Address Register +034H SCU PF Cap Ptr -- SCU PF Capabilities Pointer Register 0h RV 98h R/W +03CH SCUPILR -- SCU PF Interrupt Line Register FFh R/W +03DH SCUPIPR -- SCU PF Interrupt Pin Register 01h R/W +03EH SCUPMGNT -- SCU PF Minimum Grant Register 00h RO +03FH SCUPMLAT -- SCU PF Maximum Latency Register 00h RO +040H SCUDIDOV -- SCU DID Override Register 0h RV, R/W +098H PF PM Cap ID -- PF PM Capability Identifier Register 01h RO +099H PF PM Next Item Ptr -- PF PM Next Item Pointer Register C4h R/W +09AH PAPMCR -- SCU PF Power Management Capabilities Register +09CH PAPMCSR -- SCU PF Power Management Control/Status Register" See bit description RV, RO 0h RO, RV, R/W +0A0H P MSIX CAP -- PF MSI-X Capability Register See bit description RV, RO, R/W +0A4H P MSIX TOR -- PF MSI-X Table Offset Register See bit description RO +0A8H P MSIX PBAOR -- PF MSI-X Pending Bit Array Offset Register See bit description RO +0ACH-0C0H Reserved +0C4H SCU P I EXP CAPID -- SCU PF PCI Express* Capability Identifier Register 10h RO +0C5H SCU P I EXP NXTP -- SCU PF I PCI Express* Next Item Pointer Register A0h R/W +0C6H SCU P I EXP CAP -- SCU PF PCI Express* Capabilities Register See bit description RO, RV +0C8H SCU P I EXP DCAP -- SCU PF PCI Express* Device Capabilities Register See bit description RV, RO +0CCH SCU P I EXP DCTL -- SCU PF PCI Express* Device Control Register See bit description R/W, RO 0h RV, RO, R/W1C +0CEH SCU P I EXP DSTS -- SCU PF PCI Express* Device Status Register +0D0H SCU P I EXP LCAP -- SCU PF PCI Express* Link Capabilities Register +0D4H See bit description RV, RO SCU P I EXP LCTL -- SCU PF PCI Express* Link Control Register 0h RO, RV, R/W +0D6H SCU P I EXP LSTS -- SCU PF PCI Express* Link Status Register See bit description RO, RV +100H SCU P I ADVERR CAPID -- SCU PF PCI Express* Advanced Error Capability Identifier See bit description R/W, RO +104H SCU P I ERRUNC STS -- SCU PF PCI Express* Uncorrectable Error Status 0h RV, R/W1C +108H SCU P I ERRUNC MSK -- SCU PF PCI Express* Uncorrectable Error Mask 0h RV, R/W Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 565 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) Table 16-6. SCU PF PCI Configuration Registers (Sheet 2 of 2) Configuration Address Offset +10CH SCU P I ERRUNC SEV -- SCU PF PCI Express* Uncorrectable Error Severity Default Attribute See bit description RV, R/W, RO +110H SCU P I ERRCOR STS -- SCU PF PCI Express* Correctable Error Status 0h RV, R/W1C +114H SCU P I ERRCOR MSK -- SCU PF PCI Express* Correctable Error Mask See bit description RV, R/W +118H SCU P I ADVERR CTL -- SCU PF Advanced Error Control and Capability Register 0h RV, R/W, RO +11CH PADVERR LOG0 -- SCU PF PCI Express* Advanced Error Header Log 0h RO +120H PADVERR LOG1 -- SCU PF PCI Express* Advanced Error Header Log 0h RO +124H PADVERR LOG2 -- SCU PF PCI Express* Advanced Error Header Log 0h RO +128H PADVERR LOG3 -- SCU PF PCI Express* Advanced Error Header Log 0h RO +138H PARIDHDR -- PF Alternative Routing ID Capability Header See bit description R/W, RO R/W, RV, RO +13CH PARIDCAP -- PF Alternative Routing ID Capability Register 0h +13EH PARIDCTL -- PF Alternative Routing ID Control Register 0h RV, RO +140H SRIOVHDR -- SR-IOV Extended Capability Header See bit description R/W, RO +144H SRIOVCAP -- SR-IOV Extended Capabilities 0h RV, RO +148H SRIOVCTL -- SR-IOV Control Register 0h RV, R/W +14AH SRIOVSTS -- SR-IOV Status Register 0h RV, RO +14CH SRIOVIVF -- SR-IOV InitialVFs Register 001Fh RO +14EH SRIOVTVF -- SR-IOV TotalVFs Register 001Fh RO +150H SRIOVNVF -- SR-IOV NumVFs Register 0h R/W 0h RV, RO +152H SRIOVFDL -- SR-IOV Function Dependency Link +154H SRIOVFVFO -- SR-IOV First VF Offset Register +156H SRIOVSTRIDE -- SR-IOV VF Stride Register See bit description RO 0001h RO 0h RO +15AH SRIOVDID -- SR-IOV Device ID +15CH SRIOVSUPGSR -- SR-IOV Supported Page Size Register See bit description RO +160H SRIOVSYPGSR -- SR-IOV System Page Size Register See bit description R/W +164H SRIOVBAR0 -- SR-IOV Base Address Register 0 See bit description R/W, RV, RO +168H SRIOVUBAR0 -- SR-IOV Upper Base Address Register 0 0h R/W +17CH SRIOVFMIG -- SR-IOV VF Migration State Array Offset 0h RO +180H PTPHRHDR -- PF TPH Requester Capability Header See bit description R/W, RO +1184H PTPHRCAP -- PF TPH Requester Capability Register See bit description RV, RO 0h RV, RO, R/W +188H 566 Mnemonic and Register Name PTPHRCTL -- PF TPH Requester Control Register Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.1 PCI Standard Header Registers 16.2.1.1 SCUPVID--SCU PF Vendor ID Register (SCU - D0:F0) Address Offset: 00h-01h Default Value: 8086h 16.2.1.2 Bit Attr Default 15:00 RO 8086h Attribute: Size: RO 16 bits Description SCU Vendor ID: This is a 16-bit value assigned to Intel SCUPDID--SCU PF Device ID Register (SCU - D0:F0) Address Offset: 02h-03h Default Value: See Bit Description Attribute: Size: RO 16 bits The SCU Device ID Register reports a function of "SCU DID Override Register (SCUDIDOV)", Fuses and Straps. 16.2.1.3 Bit Attr Default 15:04 RO-V 0000h 3:0 RO-V 0h Description SCU Device ID 15to4: Device ID[15:4]. SCU Device ID 3to0: Device ID[3:0] SCUPCMD--SCU PF Command Register (SCU - D0:F0) Address Offset: 04h-05h Default Value: 0000h Attribute: Size: RV, RO, R/W 16 bits SCUPCMD Bus: XDevice: 0Function: 0,2Offset: 04h; Bit Attr Default Description 15:11 RV 00000b 10 R/W FLR 0b Interrupt Disable: Controls the ability of the SCU to generate INTx interrupt messages. When set, the SCU is prevented from generating INTx interrupt messages and will generate a Deassert_INTx message for any emulation interrupts already asserted. 9 RO 0b Fast Back to Back Enable: Does not apply to PCI Express. Hard-wired to 0 Reserved 8 R/W FLR 0b SERR# Enable: When set, the SCU is allowed to report non-fatal and fatal errors detected by the SCU to the Root Complex. Note: Errors are reported either through this bit or through the PCI Express* specific bits in the "SCU P I EXP DCTL--SCU PF PCI Express* Device Control Register (SCU - D0:F0)". 7 RO 0b Address/Data Stepping Control: Does not apply to PCI Express. Hard-wired to 0. 6 R/W FLR 0b Parity Error Response: When set, the SCU takes normal action in response to a poisoned TLP received from PCI Express. When cleared, parity checking is disabled. Note: If the bit is cleared but the Poisoned TLP Mask is cleared in the "SCU P I ERRUNC MSK--SCU PF PCI Express* Uncorrectable Error Mask (SCU - D0:F0)" register, the SCU will still log the error in the Advanced Error Reporting registers and generate an Uncorrectable Error message. 5 RO 0b VGA Palette Snoop Enable: Does not apply to PCI Express. Hard-wired to 0. 4 RO 0b Memory Write and Invalidate Enable: Does not apply to PCI Express. Hardwired to 0. 3 RO 0b Special Cycle Enable: Does not apply to PCI Express. Hard-wired to 0. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 567 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) SCUPCMD Bus: XDevice: 0Function: 0,2Offset: 04h; 16.2.1.4 Bit Attr Default Description 2 R/W FLR 0b Bus Master Enable: When cleared, the SCU is prevented from issuing any memory or I/O read/write requests. Requests other than memory or I/O requests are not controlled by this bit. The SCU will initiate a completion transaction regardless of the setting. 1 R/W FLR 0b Memory Enable: Controls the SCU PF BAR response to memory transactions. When cleared, the SCU PF does not claim memory transactions. If no function in the device claims the transaction, it results in an unaffiliated unsupported request. 0 R/W FLR 0b I/O Space Enable: Controls the SCU PF BAR response to I/O transactions. When cleared, the SCU PF does not claim I/O transactions. If no function in the device claims the transaction, it results in an unaffiliated unsupported request. SCUPSR--SCU PF Device Register (SCU - D0:F0) Address Offset: 06h-07h Default Value: see bit description 568 Attribute: Size: RV, RO, R/W1C 16 bits Bit Attr Default Description 15 R/W1C FLR 0b Detected Parity Error: set when the SCU receives a poisoned TLP regardless of the state of the Parity Error Response in the SCUPCMD register. 14 R/W1C FLR 0b SERR# Asserted: set when the SCU sends an ERR_FATAL or ERR_NONFATAL message, and the SERR Enable bit in the SCUPCMD register is `1'. 13 R/W1C FLR 0b Received Master Abort: set when the SCU receives a completion with Unsupported Request Completion Status. 12 R/W1C FLR 0b Received Target Abort: set when the SCU receives a completion with Completer Abort Completion Status. 11 R/W1C FLR 0b Signaled Target Abort: set when the SCU completes a Request using Completer Abort Completion Status 10:9 RO 00b DEVSEL# Timing: Does not apply to PCI Express. Hard-wired to 0. 8 R/W1C FLR 0b Master Data Parity Error: This bit is set by the SCU if its Parity Error Enable bit is set and either of the following two conditions occurs: This bit is set under the following conditions. * SCU receives a Poisoned Completion for an Outbound Read Request * SCU transmits a Poisoned TLP for an Outbound Write Request. If the Parity Error Response bit is cleared in the Section 16.2.1.3, this bit is never set. 7 RO 0b Fast Back-to-Back: Does not apply to PCI Express. Hard-wired to 0. 6 RV 0b Reserved 5 RO 0b 66 MHz Capable (C66): Does not apply to PCI Express. Hard-wired to 0 4 RO 1b Capabilities List: All PCI Express* devices are required to implement the PCI Express* capability structure. Hard-wired to 1. 3 RO-V FLR 0b Interrupt Status: Indicates that an INTx interrupt is pending internally to the device. Note: Setting the Interrupt Disable bit to a 1 in (bit 10 of SCUPCMD) has no effect on the state of this bit. 2:0 RV 000b Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.1.5 SCUPRID--SCU PF Revision ID Register (SCU - D0:F0) Address Offset: 08h Default Value: 00h 16.2.1.6 Bit Attr Default 7:0 RO-V 00h Attribute: Size: Description SCU Revision: Identifies the SCU's revision number. The default value is a function of fuses. SCUPCCR--SCU PF Class Code Register (SCU - D0:F0) Address Offset: 09h-0Bh Default Value: 010700h 16.2.1.7 Bit Attr Default 23:0 RO 10700h RO 24 bits Class Code: SAS Controller. SCUPCLSR--SCU PF Cacheline Size Register (SCU - D0:F0) Bit Attr Default 7:0 R/W FLR 00h Attribute: Size: R/W 8 bits Description SCU Cacheline Size: For PCI Express, this field has no impact on device functionality. SCUPLT--SCU PF Latency Timer Register (SCU - D0:F0) Address Offset: 0Dh Default Value: 00h 16.2.1.9 Attribute: Size: Description Address Offset: 0Ch Default Value: 00h 16.2.1.8 RO 8 bits Bit Attr Default 7:0 RO 00h Attribute: Size: RO 8 bits Description Programmable Latency Timer: The latency timer does not apply to PCI Express. Hard-wired 0. SCUPHTR--SCU PF Header Type Register (SCU - D0:F0) Address Offset: 0Eh Default Value: 00h Attribute: Size: RO 8 bits Bit Attr Default Description 7 RO-V 0b Multi-Function Device (MFD): Identifies the SCU as a single or multi function device. 6:0 RO 00h PCI Header Type: This bit field indicates the type of PCI header implemented. The SCU interface header conforms to PCI Local Bus Specification, Revision 3.0. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 569 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.1.10 SCUPBISTR--SCU PF BIST Register (SCU - D0:F0) Address Offset: 0Fh Default Value: 00h 16.2.1.11 Attribute: Size: Bit Attr Default 7 RO 0b Intel BIST Capable: The SCU is not Intel BIST capable. Start BIST: 6 RO 0b 5:4 RV 00b 3:0 RO 0000b Description Reserved Intel BIST Completion Code: SCUPBAR0--SCU PF Base Address Register 0 (SCU - D0:F0) Address Offset: 10h-13h Default Value: See Bit Description 16.2.1.12 Bit Attr Default 31:14 R/W-V FLR 00000h 13:4 RV 00h 3 RO 1b 2:1 RO 10b 0 RO 0b Attribute: Size: RV, RO, R/W 32 bits Description SCU Base Address 0: These bits define the actual location of window 0 on the PCI bus. Single SCU: Window size == 16KB (bit[14] behaves as R/W). Dual SCU: Window Size == 32KB (bit[14] behaves as RV). Reserved Prefetchable Indicator: If set, defines the memory space as prefetchable. Type Indicator: Defines the width of the addressability for this memory window: 00 = Memory Window is locatable anywhere in 32 bit address space 10 = Memory Window is locatable anywhere in 64 bit address space Memory Space Indicator: This bit field describes memory or I/O space base address. The SCU does not occupy I/O space, thus this bit must be zero. SCUPUBAR0--SCU PF Upper Base Address Register 0 (SCU - D0:F0) Address Offset: 14h-17h Default Value: 00000000h 570 RV, RO 8 bits Bit Attr Default 31:0 R/W FLR 0 Attribute: Size: R/W 32 bits Description SCU Upper Base Address 0: Together with the SCU Base Address 0 these bits define the actual location the SCU function is to respond Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.1.13 SCUPBAR1--SCU PF Base Address Register 1 (SCU - D0:F0) Address Offset: 18h-1Bh Default Value: See Bit Description 16.2.1.14 Default RV, RO, R/W 32 bits Bit Attr Description 31:22 R/W-V FLR 000h 21:04 RV 00000h 03 RO 1b Prefetchable Indicator: If set, defines the memory space as prefetchable. 02:01 RO 10b Type Indicator: Defines the width of the address for this memory window: 00 = Memory Window is locatable anywhere in 32 bit address space 10 = Memory Window is locatable anywhere in 64 bit address space 00 RO 0b SCU Base Address 1: These bits define the actual location of window 1 on the PCI bus. Single SCU: Window size == 4MB (bit[22] behaves as R/W). Dual SCU: Window Size == 8MB (bit[22] behaves as RV). Reserved Memory Space Indicator: This bit field describes memory or I/O space base address. The SCU window does not occupy I/O space, thus this bit must be zero. SCUPUBAR1--SCU PF Upper Base Address Register 1 (SCU - D0:F0) Address Offset: 1Ch-1Fh Default Value: 00000000h 16.2.1.15 Attribute: Size: Bit Attr Default 31:00 R/W FLR 0 Attribute: Size: R/W 32 bits Description SCU Upper Base Address 1: Together with the SCU PF Base Address 1 these bits define the actual location for this memory window on the PCI bus SCUPBAR2--SCU PF Base Address Register 2 (SCU - D0:F0) Address Offset: 20h-23h Default Value: 00000001h Default Attribute: Size: RO, R/W 32 bits Bit Attr Description 31:8 R/W-V FLR 0h SCU Base Address 2 for I/O Address Space: These bits define the actual location of window 2 on the PCI bus. Window size == 256B Note: Window 2 maps to the SCU[0] SMU register space for the PF. 7:1 RV 0h Reserved 0 RO 1b Memory Space Indicator: 1 = SCUPBAR2 in I/O address space. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 571 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.1.16 SCUPBAR3--SCU PF Base Address Register 3 (SCU - D0:F0) Address Offset: 24h-27h Default Value: 00000001h Note: 16.2.1.17 Bit Attr Default Description 31:8 R/W-V FLR 0h SCU Base Address 3 for I/O Address Space: These bits define the actual location of window 3 on the PCI bus. Window size == 256B Note: Window 3 maps to the SCU[1] SMU register space for the PF. 7:1 RV 0h Reserved 0 RO 1b Memory Space Indicator: 1 = SCUPBAR3 in I/O address space. SPSVIR--SCU PF Subsystem Vendor ID Register (SCU - D0:F0) Bit Attr Default 15:0 R/WL PRST 0000h R/WL 16 bits Subsystem Vendor ID: This register uniquely identifies the add-in board or subsystem vendor. SPSIR--SCU PF Subsystem ID Register (SCU - D0:F0) Bit Attr Default 15:0 R/WL PRST 0000h Attribute: Size: R/WL 16 bits Description Subsystem ID: uniquely identifies the add-in board or subsystem. PERBAR--SCU PF Expansion ROM Base Address Register (SCU - D0:F0) Address Offset: 30h-33h Default Value: 00000000h Attribute: Size: RV 32 bits Bit Attr Default Description 31:12 RV 00000h Expansion ROM Base Address: These bits define the actual location where the Expansion ROM address window resides when addressed from the PCI bus on any 4 Kbyte boundary. 11:1 RV 000h 0 572 Attribute: Size: Description Address Offset: 2Eh-2Fh Default Value: 0000h 16.2.1.19 RO, R/W 32 bits This register is Reserved (RV) in Single SCU configurations Address Offset: 2Ch-2Dh Default Value: 0000h 16.2.1.18 Attribute: Size: RV 0b Reserved Address Decode Enable: This bit field shows the ROM address decoder is enabled or disabled. When cleared, indicates the address decoder is disabled. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.1.20 SCU PF Cap Ptr--SCU PF Capabilities Pointer Register (SCU - D0:F0) Address Offset: 34h Default Value: 98h 16.2.1.21 Bit Attr Default 7:0 R/WL PRST 98h Attribute: Size: Description Capability List Pointer: This provides an offset in this function's configuration space that points to the SCU's PCl Bus Power Management extended capability. SCUPILR--SCU PF Interrupt Line Register (SCU - D0:F0) Address Offset: 3Ch Default Value: FFh 16.2.1.22 Attribute: Size: Attr Default Description 7:0 R/W FLR FFh Interrupt Assigned: system-assigned value identifies which system interrupt controller's interrupt request has the device's PCI interrupt request routed to it (as specified in the interrupt pin register). A value of FFh signifies "no connection" or "unknown". SCUPIPR--SCU PF Interrupt Pin Register (SCU - D0:F0) Attribute: Size: R/W 8 bits Bit Attr Default Description 7:0 R/WL PRST 01h Interrupt Used: Indicates which INTx assert/deassert legacy interrupt messages are used by the SCU. SCUPMGNT--SCU PF Minimum Grant Register (SCU - D0:F0) Address Offset: 3Eh Default Value: 00h 16.2.1.24 R/W 8 bits Bit Address Offset: 3Dh Default Value: 01h 16.2.1.23 R/W 8 bits Bit Attr Default 7:0 RO 00h Attribute: Size: RO 8 bit Description Reserved: This register does not apply to PCI Express. Hard-wired to 0 SCUPMLAT--SCU PF Maximum Latency Register (SCU - D0:F0) Address Offset: 3Fh Default Value: 00h Bit Attr Default 7:0 RO 00h Attribute: Size: RO 8 bit Description Reserved: This register does not apply to PCI Express. Hard-wired to 0 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 573 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.1.25 SCUDIDOV--SCU DID Override Register (SCU - D0:F0) Address Offset: 40-43h Default Value: 00000000h 16.2.2 Attribute: Size: RV, R/W 32 bit Bit Attr Default Description 31:4 RV 0h Reserved 3 R/WL PRST 0b DID 3 Override: This bit OR's into the value of Device ID[3] in ("SCUPDID--SCU PF Device ID Register (SCU - D0:F0)" and "SRIOVDID--SR-IOV Device ID (SCU - D0:F0)"). 2 R/WL PRST 0b DID 2 Override: This bit OR's into the value of Device ID[2] in "SCUPDID--SCU PF Device ID Register (SCU - D0:F0)" and "SRIOVDID--SR-IOV Device ID (SCU - D0:F0)". 1 R/WL PRST 0b DID 1 Override: This bit OR's into the value of Device ID[1] in "SCUPDID--SCU PF Device ID Register (SCU - D0:F0)" and "SRIOVDID--SR-IOV Device ID (SCU - D0:F0)". 0 R/WL PRST 0b DID 0 Override: This bit OR's into the value of Device ID[0] in "SCUPDID--SCU PF Device ID Register (SCU - D0:F0)" and "SRIOVDID--SR-IOV Device ID (SCU - D0:F0)". PF Power Management Capability Structure This section describes the PCI Configuration Space registers that make up the PCI Power Management Capability Structure. 16.2.2.1 PF PM Cap ID--PF PM Capability Identifier Register (SCU - D0:F0) Address Offset: 98h Default Value: 01h 16.2.2.2 Bit Attr Default 07:00 RO 01h RO 8 bit Description Cap Id: This field with its' 01H value identifies this item in the linked list of Extended Capability Headers as being the PCI Power Management Registers. PF PM Next Item Ptr--PF PM Next Item Pointer Register (SCU - D0:F0) Address Offset: 99h Default Value: C4h 574 Attribute: Size: Attribute: Size: R/W 8 bit Bit Attr Default Description 07:00 R/WL PRST C4h Next Item Pointer: This field provides an offset into the function's configuration space pointing to the next item in the function's capability list which in the SCU is the PCI Express* extended capabilities header. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.2.3 PAPMCR--SCU PF Power Management Capabilities Register (SCU - D0:F0) Address Offset: 9A-9Bh Default Value: See bit description 16.2.2.4 Attribute: Size: RO, RV 16 bit Bit Attr Default Description 15:11 RO 00000b 10 RO 0b D2 Support: This bit is set to 0b indicating that the SCU does not support the D2 Power Management State 9 RO 0b D1 Support: This bit is set to 0b indicating that the SCU does not support the D1 Power Management State 8:6 RO 000b Aux Current: This field is set to 000b indicating that the SCU has no current requirements for the 3.3Vaux signal as defined in the PCI Bus Power Management Interface Specification, Revision 1.2 5 RO 0b 4 RV 0b Reserved PME Support: This function is not capable of asserting the PME# signal in any state, since PME# is not supported by the SCU. DSI: This field is set to 0b meaning that this function will not require a device specific initialization sequence following the transition to the D0 un-initialized state. 3 RO 0b PME Clock: Since the SCU does not support PME# signal generation this bit is cleared to 0b. 2:0 RO 011b Version: Setting these bits to 011b means that this function complies with PCI Bus Power Management Interface Specification, Revision 1.2 PAPMCSR--SCU PF Power Management Control/Status Register Address Offset: 9Ch-9Dh Default Value: 00h Bit Attr Default 15 RO 0b 14:9 RV 00h 8 RO 0b 7:4 RV 3 RV 2 RV 1:0 R/W-R FLR Attribute: Size: RO,RV, R/W 16 bit Description PME Status: This function is not capable of asserting the PME# signal in any state, since PME## is not supported by the SCU. Reserved PME En: This bit is hard-wired to read-only 0b since this function does not support PME# generation from any power state. 000000b Reserved 0b No Soft Reset: This bit is set to zero, therefore, the SCU will perform an internal reset on the D3hot to D0 transition and all of the configuration state will return to the default values. 000000b Reserved 00b Power State: This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the values is: 00b = D0 01b = D1 (Unsupported) 10b = D2 (Unsupported) 11b = D3hot The SCU supports only the D0 and D3hot states. The register is designed to discard writes of 01b or 10b, though the write operation should complete on the bus normally. In other words, no state change should occur. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 575 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.3 PF MSI-X Capability Structure This section describes the PCI Configuration Space registers that make up the Message Signaled Interrupts Capability Structure. 16.2.3.1 P MSIX CAP--PF MSI-X Capability Register (SCU - D0:F0) Address Offset: A0-A3h Default Value: See bit description 16.2.3.2 RV, RO, R/W 32 bit Bit Attr Default Description 31 R/W FLR 0b MSI-X Enable: If set, the SMU is able to use MSI-X to request service. 30 R/W FLR 0b Function Mask: If set, all the vectors in the MSI-X Table are globally masked, regardless of the per-vector Mask Bit states in the Vector Control Register of the MSI-X Table entries. 29:27 RV 000b Reserved MSI-X Table Size: This field indicates the MSI-X Table size N. This field is encoded as N-1. Up to two messages can be generated (Single SCU) or 4 messages (Dual SCU). SCU Configuration Default Value Single 001h (2 vectors) Dual 003h (4 vectors) 26:16 RO-V FLR 001h 15:8 RO 00h Next Item Pointer: This field provides an offset into the function's configuration space pointing to the next item in the function's capability list. Since the MSI-X capability is the last in the linked list of extended capabilities in the SCU, this register is set to 00H. 7:0 RO 11h Capability ID: A value of 11H identifies this as the Message Signaled Interrupt (MSI-X) Capability. P MSIX TOR--PF MSI-X Table Offset Register (SCU - D0:F0) Address Offset: A4-A7h Default Value: See bit description Attribute: Size: RO 32 bit Bit Attr Default Description 31:3 RO 400h MSI-X Table Offset: Indicates the starting address of the MSI-X Table relative to the address in the Base Address Register indicated bits [2:0] of this register. This is a 64-bit QWORD aligned offset. The MSI-X Table starts at SCUPBAR0 + 8KB. 000b MSI-X Table BAR Indication Register (BIR): indicates which Base Address Register of the SMU function the MSI-X Table is mapped into. BIR Value Base Address Register 0 SCUPBAR0 2:0 576 Attribute: Size: RO Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.3.3 P MSIX PBAOR--PF MSI-X Pending Bit Array Offset Register (SCU - D0:F0) Address Offset: A8-ABh Default Value: See bit description RO 32 bit Bit Attr Default Description 31:3 RO 600h PBA Offset: Indicates the starting address of the MSI-X Pending Bit Array relative to the address in the Base Address Register indicated bits[2:0] of this register. This is a 64-bit QWORD aligned offset. The MSI-X PBA starts at SCUPBAR0 + 12 KB. 000b PBA BAR Indication Register (BIR): indicates which Base Address Register of the SMU function the Pending Bit Array is mapped into. BIR Value Base Address Register 0 SCUPBAR0 2:0 16.2.4 Attribute: Size: RO PF PCI Express* Capability Structure This section describes the PCI Configuration Space registers that make up the PCI Express* Capability Structure. 16.2.4.1 SCU P I EXP CAPID--SCU PF PCI Express* Capability Identifier Register (SCU - D0:F0) Address Offset: C4h Default Value: 10h 16.2.4.2 Bit Attr Default 7:0 RO 10h Attribute: Size: RO 8 bit Description Cap Id: This field identifies this item in the linked list of Extended Capability Headers as being the PCI Express capability registers. SCU P I EXP NXTP--SCU PF I PCI Express* Next Item Pointer Register (SCU - D0:F0) Address Offset: C5h Default Value: A0h Attribute: Size: R/W 8 bit Bit Attr Default Description 7:0 R/WL PRST A0h Next Item Pointer: This field provides an offset into the function's configuration space pointing to the next item in the function's capability list which in the SCU is the MSI-X extended capabilities header. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 577 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.4.3 SCU P I EXP CAP--SCU PF PCI Express* Capabilities Register (SCU - D0:F0) Address Offset: C6-C7h Default Value: See bit description 16.2.4.4 RO, RV 16 bit Bit Attr Default 15:14 RV 0b 13:9 RO 00000b Interrupt Message Number: This only applies to Root Complex and Switch devices. This register is hardcoded to 0. Slot Implemented: Indicates that the PCI Express* Link associated with this port is connected to a slot. Only valid for root complex and switch downstream ports. Hard-wired to 0 8 RO 0b 7:4 RO 0000b 3:0 RO 2h Description Preserved Device/Port Type: Indicates the type of PCI Express* logical device. 0000b = PCI Express* Endpoint device Capability Version: Indicates PCI-SIG defined PCI Express* capability structure version number SCU supports version 2. SCU P I EXP DCAP--SCU PF PCI Express* Device Capabilities Register (SCU - D0:F0) Address Offset: C8-CBh Default Value: See bit description 578 Attribute: Size: Attribute: Size: RO, RV 32 bit Bit Attr Default Description 31:29 RV 000b 28 RO 1b 27:26 RO 00b Captured Slot Power Limit Scale: Specifies the scale used for the Slot Power Limit Value. This value is set when the Set Slot Power Limit message is received. 25:18 RO 00h Captured Slot Power Limit Value: In combination with the Slot Power Limit Scale value, specifies the upper limit on power supplied by slot. This value is set when the Set Slot Power Limit message is received. 17:16 RV 00b Preserved 15 RO 1b Role-Based Error Reporting: this bit is set to indicate that this device implements the Role Base Error Reporting defined in PCI Express Base Specification, Revision 2.0. 14 RV 0b Reserved 13 RV 0b Reserved 12 RV 0b Reserved 11:9 RO 000b Endpoint L1 Acceptable Latency: Total acceptable latency that the SCU can withstand due to a transition from L1 state. 8:6 RO 111b Endpoint L0 Acceptable Latency: Total acceptable latency that the SCU can withstand due to a transition from L0s to L0 state. 5 RO 0b 4:3 RO 00b 2:0 RO 011b Preserved Function Level Reset Capability (FLR): is required for all VFs and PFs according to the Single Root I/O Virtualization and Sharing Specification, Revision 0.9. Extended Tag Field Supported: The SCU does support generation of 8-bit Tags. Phantom Functions Supported The SCU does not use phantom functions to extend the number of outstanding requests. Max Payload Size Supported: Indicates that the SCU can support a max payload of 1 KB Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.4.5 SCU P I EXP DCTL--SCU PF PCI Express* Device Control Register (SCU - D0:F0) Address Offset: CC-CDh Default Value: See bit description Bit Attr Default 15 R/W-V 0b Attribute: Size: R/W, RO 16 bit Description Initiate Function Level Reset: A write of 1b to this bit initiates Function Level Reset to the function. The value is always read as 0b. Max Read Request Size: This field sets the maximum Read Request size for the Device as a Requester. The Device must not generate read requests with size exceeding the set value. If a read request would exceed Max_Read_Request_Size, the SCU shall break it at an address aligned Max_Read_Request_Size boundary. If a read request would cross an address aligned 4 KB boundary, the SCU shall break it at the address aligned 4KB boundary. Defined encodings for this field are: 000b 128B max read request size 001b 256B max read request size 010b 512B max read request size 011b 1024B max read request size 100b 2048B max read request size 101b 4096B max read request size 110b Reserved 111b Reserved Any unsupported or reserved value may result in undefined behavior. 14:12 R/W FLR 010b 11 R/W FLR 1b Enable No Snoop: 10 RO 0b Aux Power PM Enable: The SCU does not utilize Auxiliary power. Hard-wired to 0. 9 RO 0b Phantom Functions Enable: SCU does not use phantom functions. Hard-wired to 0. Extended Tag Field Enable: When set in the Dual-SCU configuration, enables the use of extended tags (8 bit tags) as an initiator, else standard 5 bit tagging is used: 8 RO 0b SCUExtended Tag ConfigurationField EnableBehavior Single-SCU-5b tags; 32 total Dual-SCU05b tags; 16 per SCU; 32 total Dual-SCU18b tags; 32 per SCU; 64 total Note: Extended tagging should be enabled for best performance in a Dual-SCU. Max Payload Size: This field sets the maximum TLP payload size for the device. As a receiver, the device must handle TLPs as large as the set value; as a transmitter, the device must not generate TLPs exceeding the set value. If a write request would exceed Max_Payload_Size, the SCU shall break it at an address aligned Max_Payload_Size boundary. If a write request would cross an address aligned 4KB boundary, the SCU shall break it at the address aligned 4 KB boundary. Defined encodings for this field are: 000b 128B max payload size 001b 256B max payload size 010b 512B max payload size 011b 1024B max payload size 100b 2048B max payload size (Unsupported) 101b 4096B max payload size (Unsupported) 110b Reserved 111b Reserved Any unsupported or reserved value may result in undefined behavior. 7:5 R/W 000b 4 R/W FLR 1b Enable Relaxed Ordering: 3 R/W FLR 0b Unsupported Request Reporting Enable (URRE): This bit enables reporting of Unsupported Requests. For a multi-function device, this bit controls error reporting from the point-of-view of the respective function. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 579 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.4.6 Bit Attr Default Description 2 R/W FLR 0b Fatal Error Reporting Enable: This bit controls reporting of fatal errors. For a multi-function device, this bit controls error reporting for each function from the point-of-view of the respective function. 1 R/W FLR 0b Non-Fatal Error Reporting Enable: This bit controls reporting of non-fatal errors. For a multi-function device, this bit controls error reporting from the pointof-view of the respective function. 0 R/W FLR 0b Correctable Error Reporting Enable: This bit controls reporting of correctable errors. For a multi-function device, this bit controls error reporting from the pointof-view of the respective function. SCU P I EXP DSTS--SCU PF PCI Express* Device Status Register (SCU - D0:F0) Address Offset: CEh-CFh Default Value: 0000h RV, RO, R/W1C 16 bit Bit Attr Default 15:6 RV 000h 5 RO-V FLR 0b Transactions Pending: This bit when set indicates that a device has issued NonPosted Requests which have not been completed. A device reports this bit cleared only when all Completions for any outstanding Non-Posted Requests have been received. 4 RO 0b AUX Power Detected: SCU does not utilize AUX power. Hard-wired to 0. 3 R/W1C FLR 0b Unsupported Request Detected: This bit indicates that the device received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control Register. For a multi-function device, each function indicates status of errors as perceived by the respective function. 0b Fatal Error Detected: This bit indicates status of fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For devices supporting Advanced Error Handling, errors are logged in this register regardless of the settings of the uncorrectable error mask register. For a multi-function device, each function indicates status of errors as perceived by the respective function. 0b Non-Fatal Error Detected: This bit indicates status of non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For devices supporting Advanced Error Handling, errors are logged in this register regardless of the settings of the uncorrectable error mask register. For a multi-function device, each function indicates status of errors as perceived by the respective function. 0b Correctable Error Detected: This bit indicates status of correctable errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For devices supporting Advanced Error Handling, errors are logged in this register regardless of the settings of the correctable error mask register. For a multi-function device, each function indicates status of errors as perceived by the respective function. 2 1 0 580 Attribute: Size: R/W1C FLR R/W1C FLR R/W1C FLR Description Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.4.7 SCU P I EXP LCAP--SCU PF PCI Express* Link Capabilities Register (SCU - D0:F0) Address Offset: D0-D3h Default Value: See bit description 16.2.4.8 Bit Attr Default 31:24 RO 00h Attribute: Size: RO, RV 32 bit Description Port #: PCI Express* port number. 23:22 RV 0h Reserved 21 RO 0b Link Bandwidth Notification Capability (LBNC): Not supported. 20 RO 0b Data Link Layer Link Active Reporting Capable (DLLLARC): Not supported. 19 RO 0b Surprise Down Error Reporting Capable (SDERC): Not supported. Clock Power Management (CPM): IOSF clock gating. 18 RO 0b 17:15 RO 000b L1 Exit Latency (L1EL): 14:12 RO 000b L0s Exit Latency (L0SEL): 11:10 RO 11b Active State Link PM Support: 9:4 RO 1h Maximum Link Width (MLW): This device supports a maximum width of x8. 3:0 RO 1h Maximum Link Speed (MLS): The PCI Express* Link operates at 2.5 Gb/s. SCU P I EXP LCTL--SCU PF PCI Express* Link Control Register (SCU - D0:F0) Address Offset: D4-D5h Default Value: 0000h Attribute: Size: RO, RV, R/W 16 bit Bit Attr Default Description 15:8 RV 00h 7 R/W 0b Extended Synch: When set forces extended transmissions of FTS ordered sets in FTS and extra TS2 at exit from L1 prior to entering L0. This mode provides external devices monitoring the link time to achieve bit and symbol lock before the link enters L0 state and resumes communication. Reserved 6 R/W 0b Common Clock Configuration: When set indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. This bit used to report the correct L0s and L1 Exit Latencies in the PCIE LCAP register 5 RO 0b Retrain Link: Not Applicable to endpoints. Hard-wired to 0 4 RO 0b Link Disable: Not Applicable to endpoints. Hard-wired to 0 3 R/W 0b Read Completion Boundary (RCB) Control: Indicates the Root Complex's RCB. 2 RV 0b 1:0 R/W 00b Reserved Active State PM Control: This field controls the level of active state PM supported on the given PCI Express* Link. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 581 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.4.9 SCU P I EXP LSTS--SCU PF PCI Express* Link Status Register (SCU - D0:F0) Address Offset: D6-D7h Default Value: See bit description 16.2.5 Attribute: Size: RO, RV 16 bit Bit Attr Default Description 15:13 RV 0h Reserved 12 RO 1b Slot Clock Configuration: Indicates that the component uses the same physical reference clock that the platform provides on the connector. This bit must be cleared if the device uses an independent reference clock. 11 RO 0b Link Training: As an endpoint, this bit is hard-wired to 0 10 RO 0b Link Training Error: As an endpoint, this bit is hard-wired to 0 9:4 RO 1h Negotiated Link Width: Defined encodings are 01H x1 02H x2 04H x4 08H x8 12H x12 (Unsupported) 10H x16 (Unsupported) 20H x32 (Unsupported) All other encodings are reserved Note: Hardwired to x1. 3:0 RO 1h Link Speed: Negotiated Link Speed. 1h indicates 2.5 Gb/s Link speed. Note: Hardwired to report Gen1 speed. PF Advanced Error Reporting Extended Capability Structure This section describes the PCI Express* Extended Configuration Space registers that make up the Advanced Error Reporting Extended Capability Structure. 16.2.5.1 SCU P I ADVERR CAPID--SCU PF PCI Express* Advanced Error Capability Identifier (SCU - D0:F0) Address Offset: 100-103h Default Value: See bit description 582 Attribute: Size: R/W, RO 32 bit Bit Attr Default Description 31:20 R/WL PRST 138h Next Capability Pointer: This filed points to the Alternative Routing ID extended capability. 19:16 RO 1h Capability Version Number: PCI Express Advanced Error Reporting Extended Capability Version Number. 15:0 RO 0001h Advanced Error Capability ID: PCI Express Extended Capability ID indicating Advanced Error Reporting Capability. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.5.2 SCU P I ERRUNC STS--SCU PF PCI Express* Uncorrectable Error Status (SCU - D0:F0) Address Offset: 104-107h Default Value: 00000000h 16.2.5.3 Attribute: Size: RV, R/W1C 32 bit Bit Attr Default Description 31:23 RV 000h 22 R/W1CS 0b Uncorrectable Internal Error Status: As a receiver, set whenever an Internal Bus Command Parity Error is detected. The Header is logged. 21 RV 0b Reserved 20 R/W1CS 0b Unsupported Request Error Status: As a receiver, Set whenever an unsupported request is detected. The Header is logged. 19 RV 0b ECRC Check: As a receiver, set when ECRC check fails. The Header is logged. ECRC checking is not supported. 18 R/W1CS 0b Malformed TLP: As a receiver, set whenever a malformed TLP is detected. The Header is logged. 17 RV 0b Receiver Overflow: Set if PCI Express receive buffers overflow. 16 R/W1CS 0b Unexpected Completion: As a receiver, set whenever a completion is received that does not match the SCU requestor ID or outstanding Tag. The Header is logged. 15 R/W1CS 0b Completer Abort: As a completer, set whenever an internal agent signals a data abort. The header is logged. 14 R/W1CS 0b Completion Timeout: As a requester, set whenever an outbound Non Posted Request does not receive a completion within 16-32 ms. 13 RV 0b Flow Control Protocol Error Status: Set whenever a flow control protocol error is detected. 12 R/W1CS 0b Poisoned TLP Received: As a receiver, set whenever a poisoned TLP is received from PCI Express. The header is logged. Note that internal queue errors are not covered by this bit, they are logged by the target of the transaction. 11:5 RV 00h Reserved Reserved 4 RV 0b Data Link Protocol Error: Set whenever a data link protocol error is detected. 3:0 RV 0h Reserved SCU P I ERRUNC MSK--SCU PF PCI Express* Uncorrectable Error Mask (SCU - D0:F0) Address Offset: 108-10Bh Default Value: 00000000h Bit Attr Default 31:23 RV 000h Attribute: Size: RV, R/W 32 bit Description Reserved 22 R/WS 1b Uncorrectable Internal Error Mask: When `1' error reporting is masked. 21 RV 0b Reserved 20 R/WS 0b Unsupported Request Error Mask: When `1' error reporting is masked. 19 RV 0b ECRC Check Error Mask: When `1' error reporting is masked. 18 R/WS 0b Malformed TLP Error Mask: When `1' error reporting is masked. 17 RV 0b Receiver Overflow Error Mask: When `1' error reporting is masked. 16 R/WS 0b Unexpected Completion Error Mask: When `1' error reporting is masked. 15 R/WS 0b Completer Abort Error Mask: When `1' error reporting is masked. 14 R/WS 0b Completion Time Out Error Mask: When `1' error reporting is masked. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 583 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) Bit 16.2.5.4 Attr Default Description 13 RV 0b Flow Control Protocol Error Mask: When `1' error reporting is masked. 12 R/WS 0b Poisoned TLP Received Error Mask: When `1' error reporting is masked. 11:5 RV 00h 4 RV 0b Data Link Protocol Error Mask: When `1' error reporting is masked. 3:0 RV 0h Reserved Reserved. SCU P I ERRUNC SEV--SCU PF PCI Express* Uncorrectable Error Severity (SCU - D0:F0) Address Offset: 10C-10Fh Default Value: See bit description 16.2.5.5 Bit Attr Default 31:23 RV 000h 22 R/WS 1b Uncorrectable Internal Error Severity (UIES): 21 RV 0b Reserved 20 R/WS 0b Unsupported Request Error Severity: 19 RV 0b ECRC Check Severity: 18 R/WS 1b Malformed TLP Severity: 17 RO 1b Receiver Overflow Severity: 16 R/WS 0b Unexpected Completion Severity: 15 R/WS 0b Completer Abort Severity: 14 R/WS 0b Completion Time Out Severity: 13 RO 1b Flow Control Protocol Error Severity: RV, R/W, RO 32 bit Description Reserved 12 R/WS 0b 11:5 RV 00h Poisoned TLP Received Severity: 4 RO 1b Data Link Protocol Error Severity: 3:0 RV 0h Reserved Reserved SCU P I ERRCOR STS--SCU PF PCI Express* Correctable Error Status (SCU - D0:F0) Address Offset: 110-113h Default Value: 00000000h 584 Attribute: Size: Attribute: Size: RV, R/W1C 32 bit Bit Attr Default Description 31:14 RV 0 13 R/W1CS 0b Advisory Non-Fatal Error Status 12 RV 0b Replay Timer Timeout Status: Set whenever a replay timer timeout occurs. 11:9 RV 000b Reserved Reserved 8 RV 0b REPLAY NUM Rollover Status: Set whenever the replay number rolls over from 11 to 00. 7 RV 0b Bad DLLP Status: Sets this bit on CRC errors on DLLP. 6 RV 0b Bad TLP Status: Sets this bit on CRC errors or sequence number out of range on TLP. 5:1 RV 00h 0 RV 0b Reserved Receiver Error Status: Set whenever the physical layer detects a receiver error. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.5.6 SCU P I ERRCOR MSK--SCU PF PCI Express* Correctable Error Mask (SCU - D0:F0) Address Offset: 114-117h Default Value: See bit description 16.2.5.7 RV, R/W 32 bit Bit Attr Default Description 31:14 RV 0 13 R/WS 1b Advisory Non-Fatal Error Mask: this bit is set by default to enable compatibility with software that does not comprehend Role-Based Error Reporting. 12 RV 0b Replay Timer Timeout Mask: 11:9 RV 000b 8 RV 0b REPLAY NUM Rollover Mask: 7 RV 0b Bad DLLP Mask: 6 RV 0b Bad TLP Mask: 5:1 RV 00h 0 RV 0b Reserved Reserved Reserved Receiver Error Mask: SCU P I ADVERR CTL--SCU PF Advanced Error Control and Capability Register (SCU - D0:F0) Address Offset: 118-11Bh Default Value: 00000000h 16.2.5.8 Attribute: Size: Bit Attr Default 31:9 RV 0 Attribute: Size: RV, R/W, RO 32 bit Description Reserved 8 R/WS 0b ECRC Check Enable: When set enables ECRC checking. 7 RO 0b ECRC Check Capable: Indicates the SCU is not capable of checking ECRC. 6 R/WS 0b ECRC Generation Enable: When set enables ECRC generation. 5 RO 0b ECRC Generation Capable: Indicates the SCU is not capable of generating ECRC. 4:0 ROS-V 00000b The First Error Pointer: Identifies the bit position of the first error reported in the Section 16.2.5.2 register. Note: This register will not update until all bits in the ERRUNC STS register are cleared. PADVERR LOG0--SCU PF PCI Express* Advanced Error Header Log (SCU - D0:F0) Address Offset: 11C-11Fh Default Value: 00000000h Attribute: Size: RO 32 bit Bit Attr Default Description 31:0 ROS-V 0 1st DWord of the Header for the PCIe packet in error (HDRLOGDW0): Once an error is logged in this register, it remains locked for further error logging until the time the software clears the status bit that cause the header log, that is, the error pointer is rearmed to log again. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 585 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.5.9 PADVERR LOG1--SCU PF PCI Express* Advanced Error Header Log (SCU - D0:F0) Address Offset: 120-123h Default Value: 00000000h 16.2.5.10 Attr Default Description 31:0 ROS-V 0 2nd DWord of the Header for the PCIe packet in error (HDRLOGDW1): Once an error is logged in this register, it remains locked for further error logging until the time the software clears the status bit that cause the header log, that is, the error pointer is rearmed to log again. PADVERR LOG2--SCU PF PCI Express* Advanced Error Header Log (SCU - D0:F0) Attribute: Size: RO 32 bit Bit Attr Default Description 31:0 ROS-V 0 3rd DWord of the Header for the PCIe packet in error (HDRLOGDW2): Once an error is logged in this register, it remains locked for further error logging until the time the software clears the status bit that cause the header log, that is, the error pointer is rearmed to log again. PADVERR LOG3--SCU PF PCI Express* Advanced Error Header Log (SCU - D0:F0) Address Offset: 128-12Bh Default Value: 00000000h 16.2.6 RO 32 bit Bit Address Offset: 124-127h Default Value: 00000000h 16.2.5.11 Attribute: Size: Attribute: Size: RO 32 bit Bit Attr Default Description 31:0 ROS-V 0 4th DWord of the Header for the PCIe packet in error (HDRDWLOG3): Once an error is logged in this register, it remains locked for further error logging until the time the software clears the status bit that cause the header log, that is, the error pointer is rearmed to log again. PF Alternative Routing ID Extended Capability Structure This section describes the PCI Express* Extended Configuration Space registers that make up the Alternative Routing ID Extended Capability Structure. 16.2.6.1 PARIDHDR--PF Alternative Routing ID Capability Header (SCU - D0:F0) Address Offset: 138-13Bh Default Value: See bit description 586 Bit Attr Default 31:20 R/WL PRST 180h 19:16 RO 1h 15:0 RO 000Eh Attribute: Size: R/W, RO 32 bit Description Next Capability Offset: This field points to the next item in the extended capabilities list, the TPH requester extended capability. Capability Version: This is set to 1h for the most current version of the specification. PCI Express* Extended Capability ID: The PCI SIG has assigned 000Eh to the ARI extended capability. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.6.2 PARIDCAP--PF Alternative Routing ID Capability Register (SCU - D0:F0) Address Offset: 13C-13Dh Default Value: 0000h 16.2.6.3 R/W, RV, RO 16 bit Bit Attr Default Description 15:8 R/WL PRST 00h Next Function Number: The function number of the next highest numbered PF in a multi-function device. 7:2 RV 00h Reserved 1 RO 0b ACS Functional Groups Capability: SCU does not support. 0 RO 0b MFVC Functional Groups Capability: SCU does not support. PARIDCTL--PF Alternative Routing ID Control Register (SCU - D0:F0) Address Offset: 13E-13Fh Default Value: 0000h Bit 16.2.7 Attribute: Size: Attr Default Attribute: Size: RV, RO 16 bit Description 15:7 RV 00h 6:4 RO 000b Reserved 3:2 RV 00b 1 RO 0b ACS Functional Groups Enable: Hardwired to Zero as SCU does not support. 0 RO 0b MFVC Functional Groups Enable: Hardwired to Zero as SCU does not support. Function Group: Hardwired to Zero as SCU does not support Function Groups. Reserved PF SR-IOV Extended Capability Structure This section describes the PCI Express* Extended Configuration Space registers that make up the SR-IOV Extended Capability Structure. 16.2.7.1 SRIOVHDR--SR-IOV Extended Capability Header (SCU - D0:F0) Address Offset: 140-143h Default Value: See bit description Bit Attr Default 31:20 R/WL PRST 000h 19:16 RO 1h 15:0 RO 0010h Attribute: Size: R/W, RO 32 bit Description Next Capability Offset: This field contains 000h as this is the end of the extended capability list for the SCU. Capability Version: This is set to 1h for the Single Root I/O Virtualization and Sharing Specification, Revision 0.9. PCI Express* Extended Capability ID: The PCI SIG has assigned 0010h to the SR-IOV extended capability. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 587 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.7.2 SRIOVCAP--SR-IOV Extended Capabilities (SCU - D0:F0) Address Offset: 144-147h Default Value: 00000000h Attr Default Description 31:21 RO 000h VF Migration Interrupt Message Number (VMIMN): Hardwired to zero as the SCU does not support Multi-Root I/O Virtualization (MR-IOV). 20:1 RV 00000h RO 0b Reserved VF Migration Capable: The SCU does not support MR-IOV; therefore, does not support VF Migration. SRIOVCTL--SR-IOV Control Register (SCU - D0:F0) Address Offset: 148-149h Default Value: 0000h 16.2.7.4 Bit Attr Default 15:5 RV 000h Attribute: Size: RV, R/W 16 bit Description Reserved 4 R/W FLR 0b ARI Capable Hierarchy: This bit is a hint to the device that it is in an ARI capable hierarchy. It is permitted to use this bit to determine stride and first-VFoffset. This bit is R/W in the lowest numbered physical function, and RV in other functions. This is only a hint, and the SCU does not use this bit. 3 R/W FLR 0b VF MSE: Controls the SCU VF BAR response to memory transactions. When cleared, the SCU VFs do not claim memory transactions. If no function in the device claims the transaction, it results in an unaffiliated unsupported request. 2 R/W FLR 0b VF Migration Interrupt Enable: Enables/Disables VF Migration State Change Interrupt. Note: Not supported by the SCU. 1 R/W FLR 0b VF Migration Enable: Enables/Disables VF Migration Support. Note: Not supported by the SCU. 0 R/W FLR 0b VF Enable: Enables/Disables VFs. When this bit is clear (0b) all VFs are disabled (VFs shall not master transactions and VFs shall not claim configuration, memory or I/O transactions). If no function in the device claims the transaction, it results in an unaffiliated unsupported request. SRIOVSTS--SR-IOV Status Register (SCU - D0:F0) Address Offset: 14A-14Bh Default Value: 0000h Bit Attr Default 15:1 RV 000h 0 588 RV, RO 32 bit Bit 0 16.2.7.3 Attribute: Size: RO 0 Attribute: Size: 16 bit RV, RO Description Reserved VF Migration Status: Note: Since the SCU does not support VF Migration, this bit will be hardwired to zero. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.7.5 SRIOVIVF--SR-IOV InitialVFs Register (SCU - D0:F0) Address Offset: 14C-14Dh Default Value: 001Fh 16.2.7.6 Attr Default Description 15:0 RO 001Fh InitialVFs: Indicates to SR software the number of VFs that are initially associated with the Physical Function (PF). Note: For SR-IOV, this register must always be equal to the Section 16.2.7.6 as VF Migration is not supported. SRIOVTVF--SR-IOV TotalVFs Register (SCU - D0:F0) Bit Attr Default 15:0 RO 001Fh Attribute: Size: RO 16 bit Description TotalVFs: Indicates to SR software the maximum number of VFs that could be associated with the Physical Function (PF). SRIOVNVF--SR-IOV NumVFs Register (SCU - D0:F0) Address Offset: 150-151h Default Value: 0000h Bit 15:0 16.2.7.8 RO 16 bit Bit Address Offset: 14E-14Fh Default Value: 001Fh 16.2.7.7 Attribute: Size: Attr R/W FLR Attribute: Size: R/W 16 bit Default Description 0000h NumVFs: Controls the number of VFs software assigns to the PF. Software sets NumVFs as part of the process of creating VFs. This number of VFs shall be visible in the PCI Express* fabric after both NumVFs is set to a valid value and VF Enable is set to one. Note: NumVFs may only be written while VF Enable is Clear. If NumVFs is written when VF Enable is Set, the results are undefined. If the SMU or SDMA attempt to master a transaction on PCI using an invalid VFi, a Master-Abort is returned to the requester (SMU or SDMA) and the transaction will not be forwarded to the PCI bus. The VFi is invalid under any of the following conditions: 1. VF Enable is Clear, or 1. VFi > TotalVFs, or 1. VFi > NumVFs, or 1. Bus Master Enable for that VFi is Clear. SRIOVFDL--SR-IOV Function Dependency Link (SCU - D0:F0) Address Offset: 152-153h Default Value: 0000h Attribute: Size: RV, RO 16 bit Bit Attr Default Description 15:8 RV 00h Reserved 7:0 RO 00h Function Dependency Link: As the SCU is a single function device, this is set to 00H. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 589 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.7.9 SRIOVFVFO--SR-IOV First VF Offset Register (SCU - D0:F0) Address Offset: 154-155h Default Value: See bit description 16.2.7.10 Attr Default Description 15:0 RO 08h First VF Offset: First VF Offset is a constant and defines the Routing ID (RID) offset of the first VF that is associated with the PF that contains this Capability structure. The first VFs 16-bit RID is calculated by adding the contents of this field to the RID of the PF. SRIOVSTRIDE--SR-IOV VF Stride Register (SCU - D0:F0) Bit 15:0 Attr RO Attribute: Size: Description 0001h VF Stride: VF Stride is a constant and defines the Routing ID (RID) offset from one VF to the next one for all VFs associated with the PF that contains this Capability structure. The next VFs 16-bit RID is calculated by adding the contents of this field to the RID of the current VF. Note: For the SCU, the stride between the RIDs of subsequent VFs is one. SRIOVDID--SR-IOV Device ID (SCU - D0:F0) Bit Attr Default 15:04 RO-V 000h 3:0 RO-V 0h Attribute: Size: RO 16 bit Description Note: VF Device ID 15to4: The Device ID[15:4] that is presented to the OS for every VF. VF Device ID 3to0: The Device ID[3:0] that is presented to the OS for every VF. This field returns the same value as bits[3:0] of Section 16.2.1.2. SRIOVSUPGSR--SR-IOV Supported Page Size Register (SCU - D0:F0) Address Offset: 15C-15Fh Default Value: See bit description Bit 31:0 590 RO 16 bit Default Address Offset: 15A-15Bh Default Value: 0000h 16.2.7.12 RO 16 bit Bit Address Offset: 156-157h Default Value: 0001h 16.2.7.11 Attribute: Size: Attr RO Attribute: Size: RO 32 bit Default Description 553h Supported Page Size: The SCU supports the 4-KB, 8-KB, 64-KB, 256-KB, 1-MB and 4-MB page sizes. Support for these page sizes are required by the Single Root I/O Virtualization and Sharing Specification, Revision 0.9. Note: A given bit n set in this register corresponds to support for a page size of 2^(n+12) bytes. For example, the setting of bit 0 indicates support for a 4-KB page size. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.7.13 SRIOVSYPGSR--SR-IOV System Page Size Register (SCU - D0:F0) Address Offset: 160-163h Default Value: See bit description Bit 31:0 16.2.7.14 Attr R/W FLR Attribute: Size: R/W, RV, RO 32 bit Default Description 1h System Page Size: The SCU supports the 4-KB, 8-KB, 64-KB, 256-KB, 1-MB and 4-MB page sizes. By setting one and only one of these bits, the OS can configure the SCU to one of its' supported page sizes. The default page size is 4-KB. Note: A given bit n set in this register corresponds to support for a page size of 2^(n+12) bytes. For example, the setting of bit 0 indicates support for a 4-KB page size. VF Enable of Section 16.2.7.3 must be zero when this register is written. SRIOVBAR0--SR-IOV Base Address Register 0 (SCU - D0:F0) Address Offset: 164-167h Default Value: See bit description Bit Attr Default Attribute: Size: R/W, RV, RO 32 bit Description SRIOV Base Address 0: These bits are used to define the actual locations that the VFs of the SCU function are to respond to when addressed from the PCI bus. PCI Local Bus Specification, Revision 3.0 compliant scanning of this register, at a minimum reveals a 16KB memory window. However, if the System Page Size is programmed larger than 16KB, the size of the memory window must adjust to two times the System Page Size as described in Section 16.2.7.13, "SRIOVSYPGSR-- SR-IOV System Page Size Register (SCU - D0:F0)" on page 591. This would mean that bits above bit 13 in this register may respond as Reserved (RV) rather than Read/Write (R/W) opening up a window larger than 16KB. In addition, the window size doubles for a Dual-SCU configuration. System Page SizeBits responding as RVWindow Size (per VF) R/W-V FLR 00000h 13:4 RV 00h 3 RO 1b 2:1 RO 10b 31:14 0 RO 0b Single-SCUDual-SCUSingle-SCUDual-SCU 4 KB None 14 16KB 32KB 8 KB None 14 16KB 32KB 64 KB 16:14 17:14128KB 256KB 256 KB 18:14 19:14512KB 1MB 1 MB 20:14 21:142MB 4MB 4 MB 22:14 23:148MB 16MB The reported window size is the window size per VF and may also be given by the following equations: Single-SCU: WindowSizePerVF = Max(16KB, 2*System_Page_Size) Dual-SCU: WindowSizePerVF = 2*Max(16KB, 2*System_Page_Size) The total size of the SRIOVBAR0 window will be this size multiplied by the number of enabled VFs: WindowSizeTotal = VFs * WindowSizePerVF The base address of any VF having VF index of VFi is: VF_Base = SRIOVBAR0 + ((VFi - 1) * WindowSizePerVF) Reserved Prefetchable Indicator: If set, defines the memory space as prefetchable. Type Indicator: Memory Window is locatable anywhere in 64 bit address space Memory Space Indicator: This bit field describes memory or I/O space base address. This bit must be hard-wired to zero as SR-IOV does not support I/O space. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 591 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.7.15 SRIOVUBAR0--SR-IOV Upper Base Address Register 0 (SCU - D0:F0) Address Offset: 168-16Bh Default Value: 00000000h 16.2.7.16 R/W 32 bit Bit Attr Default Description 31:0 R/W FLR 000000 00h SR-IOV Upper Base Address 0: Together with the SR-IOV Base Address 0 these bits define the actual location the VMs will respond to when addressed from the PCI bus SRIOVFMIG--SR-IOV VF Migration State Array Offset (SCU - D0:F0) Address Offset: 17C-17Fh Default Value: 00000000h 16.2.8 Attribute: Size: Attribute: Size: RO 32 bit Bit Attr Default Description 31:0 RO 0h VF Migration State Array Offset: This value is hardwired to zero as the SCU is not VF Migration Capable. PF TPH Requester Extended Capability Structure This section describes the PCI Express* Extended Configuration Space registers that make up the TPH (TLP Processing Hints) Requester Extended Capability Structure. 16.2.8.1 PTPHRHDR--PF TPH Requester Capability Header (SCU - D0:F0) Address Offset: 180-183h Default Value: See bit description 592 Bit Attr Default 31:20 R/WL PRST 140h 19:16 RO 1h 15:0 RO 0017h Attribute: Size: R/W, RO 32 bit Description Next Capability Offset: This field points to the next item in the extended capabilities list, the SR-IOV extended capability. Capability Version: This is set to 1h for the most current version of the specification. PCI Express* Extended Capability ID: The PCI SIG has assigned 0017h to the TPH Requester extended capability. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.2.8.2 PTPHRCAP--PF TPH Requester Capability Register (SCU - D0:F0) Address Offset: 184-187h Default Value: See bit description 16.2.8.3 Bit Attr Default 31:27 RV 00h Attribute: Size: RV, RO 32 bit Description Reserved 26:16 RO 000h 15:11 RV 00h ST Table Size: ST Table is not present. 10:9 RO 0h ST Table Location: ST Table is not present. 8 RO 0b Extended TPH Requester Supported: SCU does not generate requests with the TPH TLP Prefix. 7:3 RV 00h 2 RO 1b Device Specific Mode Supported: SCU supports the Device Specific Mode of operation. 1 RO 0b Interrupt Vector Mode Supported: SCU does not support the Interrupt Vector Mode of operation. 0 RO 1b No ST Mode Supported: SCU supports the No ST Mode of operation. Reserved Reserved PTPHRCTL--PF TPH Requester Control Register (SCU - D0:F0) Address Offset: 188-18Bh Default Value: 00000000h Bit Attr Default 31:10 RV 00h 9 RO 0b 8 R/W FLR 0b 7:3 RV 00h 2:0 R/W FLR 0h Attribute: Size: RV, RO, R/W 32 bit Description Reserved Extended TPH Enable: The SCU is never Extended TPH enabled. TPH Requester Enable: When set, the SCU is permitted to use TPH. Reserved ST Mode Select: Sets the ST mode of operation. 000b = No ST Mode 001b = Interrupt Vector Mode (not supported; behaves as No ST Mode) 010b = Device Specific Mode Others = Reserved (behave as No ST Mode) Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 593 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.3 SCU Virtual Function Configuration Registers The following sections describe the SCU VF configuration registers. Table 16-7. SCU VF PCI Configuration Registers (Sheet 1 of 2) Configuration Address Offset Default Attributes RO +000H SCUVID x--SCU Vendor ID Register x FFFFh +002H SCUVDID x--SCU VF Device ID Register x FFFFh RO +004H SCUVFCMD x--SCU VF Command Register x 0h RO, RV, R/W +006H SCUVSR x--SCU VF Status Register x See bit description RO, R/W1C, RV +008H SCUVRID x--SCU VF Revision ID Register +009H SCUVCCR x--SCU VF Class Code Register x +00CH SCUVCLSR x--SCU VF Cacheline Size Register x 0h RO +00DH SCUVLT x--SCU VF Latency Timer Register x 0h RO 0h RO 10700h RO +00EH SCUVHTR x--SCU VF Header Type Register x 0h RO +02CH SVSVIR x--SCU VF Subsystem Vendor ID Register x 0h RO +02EH SVSIR x--SCU VF Subsystem ID Register x 0h RO +034H SCU VF Cap Ptr x--SCU VF Capabilities Pointer Register x C4h R/W +03CH SCUVILR x--SCU VF Interrupt Line Register x 0h RO +03DH SCUVIPR x--SCU VF Interrupt Pin Register x 0h RO +03EH SCUVMGNT x--SCU VF Minimum Grant Register x 0h RO +03FH SCUVMLAT x--SCU VF Maximum Latency Register x 0h RO V MSIX CAP x--VF MSI-X Capability Register x See bit description R/W, RV, RO +0A4H SV MSIX TOR x--VF MSI-X Table Offset Register x See bit description RO +0A8H V MSIX PBAOR x--VF MSI-X Pending Bit Array Offset Register x See bit description RO +0ACH V MSIX CR x--VF MSI-X Control Register x 0h RV, R/W +0C4H SCU V I EXP CAPID x--SCU VF PCI Express* Capability Identifier Register x 10h RO +0C5H SCU V I EXP NXTP x--SCU VF I PCI Express* Next Item Pointer Register x A0h R/W +0C6H SCU V I EXP CAP x--SCU VF PCI Express* Capabilities Register x See bit description RO, RV +0C8H SCU V I EXP DCAP x--SCU VF PCI Express* Device Capabilities Register x See bit description RV, RO +0CCH SCU V I EXP DCTL x--SCU VF PCI Express* Device Control Register x 0h RO, R/W +0CEH SCU V I EXP DSTS x--SCU VF PCI Express* Device Status Register x 0h RO, R/W1C, RV +0D0H SCU V I EXP LCAP x--SCU VF PCI Express* Link Capabilities Register x See bit description RO, RV +0A0H 594 Register Name and Neumonics +0D4H SCU V I EXP LCTL x--SCU VF PCI Express* Link Control Register x 0h RO, RV +0D6H SCU V I EXP LSTS x--SCU VF PCI Express* Link Status Register x 0h RV +100H SCU V I AERR CAPID x--SCU VF PCI Express* Advanced Error Capability Identifier x See bit description RO, R/W +104H SCU V I ERRUNC STS x--SCU VF PCI Express* Uncorrectable Error Status x 0h RV, R/W1C +108H SCU V I ERRUNC MSK x--SCU VF PCI Express* Uncorrectable Error Mask x 0h RV +10CH SCU V I ERRUNC SEV x--SCU VF PCI Express* Uncorrectable Error Severity x 0h RV +110H SCU V I ERRCOR STS x--SCU VF PCI Express* Correctable Error Status x 0h RV, R/W1C +114H SCU V I ERRCOR MSK x--SCU VF PCI Express* Correctable Error Mask x 0h RV +118H SCU V I ADVERR CTL x--SCU VF Advanced Error Control and Capability Register x) 0h RV, RO +11CH VADVERR LOG0 x--SCU VF PCI Express* Advanced Error Header Log x 0h RO +120H VADVERR LOG1 x--SCU VF PCI Express* Advanced Error Header Log x 0h RO Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) Table 16-7. SCU VF PCI Configuration Registers (Sheet 2 of 2) Configuration Address Offset Register Name and Neumonics Default Attributes +124H VADVERR LOG2 x--SCU VF PCI Express* Advanced Error Header Log x 0h RO +128H VADVERR LOG3 x--SCU VF PCI Express* Advanced Error Header Log x 0h RO See bit description RO, R/W +138H VARIDHDR x--VF Alternative Routing ID Capability Header x +13CH VARIDCAP x--VF Alternative Routing ID Capability Register x 0h RV, RO +13EH VARIDCTL x--VF Alternative Routing ID Control Register x 0h RV, RO +180H VTPHRHDR x--VF TPH Requester Capability Header x See bit description RO +184H VTPHRCAP x--VF TPH Requester Capability Register x See bit description RV, RO +188H VTPHRCTL x--VF TPH Requester Control Register x 0h RV, RO, R/W 16.3.1 PCI Standard Header Registers This section describes the PCI Configuration Space registers that make up the standard Type 0 VF header. 16.3.1.1 SCUVID x--SCU Vendor ID Register x (D1-3 : F0-7, D4 : F0-6) Address Offset: 00-01h Default Value: FFFFh 16.3.1.2 Bit Attr Default 15:00 RO FFFFh Attribute: Size: RO 16 bit Description Vendor ID: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field return FFFFH. SCUVDID x--SCU VF Device ID Register x (D1-3 : F0-7, D4 : F0-6) Address Offset: 02-03h Default Value: FFFFh Attribute: Size: RO 16 bit Bit Attr Default Description 15:00 RO FFFFh Device ID: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field return FFFFH. Note: Software should return the VF Device ID value from the associated PF as the Device ID for the VF. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 595 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.3.1.3 SCUVFCMD x--SCU VF Command Register x (D1-3 : F0-7, D4 : F0-6) Address Offset: 04-05h Default Value: 0000h 596 Attribute: Size: RO, RV, R/W 16 bit Bit Attr Default Description 15:11 RV 00000b 10 RO 0b Interrupt Disable: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field is hardwired to 0b for all VFs. Note: This bit does not apply to VFs. 9 RO 0b Fast Back to Back Enable: Does not apply to PCI Express. Hard-wired to 0 8 RO 0b SERR# Enable: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field is hardwired to 0b for all VFs. In addition the functionality associated with the setting of this bit in the Section 16.2.1.3 will apply to all VFs. 7 RO 0b Address/Data Stepping Control: Does not apply to PCI Express. Hard-wired to 0. 6 RO 0b Parity Error Response: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field is hardwired to 0b for all VFs. In addition the functionality associated with the setting of this bit in the Section 16.2.1.3 will apply to all VFs. 5 RO 0b VGA Palette Snoop Enable: Does not apply to PCI Express. Hard-wired to 0. 4 RO 0b Memory Write and Invalidate Enable: Does not apply to PCI Express. Hardwired to 0. 3 RO 0b Special Cycle Enable: Does not apply to PCI Express. Hard-wired to 0. Reserved 2 R/W FLR 0b Bus Master Enable: When cleared, the SCU is prevented from issuing any memory or I/O read/write requests. Requests other than memory or I/O requests are not controlled by this bit. The SCU will initiate a completion transaction regardless of the setting. Note: Transactions for a VF that has its Bus Master Enable set must not be blocked by transactions for VFs that have their Bus Master Enable cleared. 1 RO 0b Memory Enable: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field is hardwired to 0b for all VFs. 0 RO 0b I/O Space Enable: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field is hardwired to 0b for all VFs. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.3.1.4 SCUVSR x--SCU VF Status Register x (D1-3 : F0-7, D4: F0-6) Address Offset: 06-07h Default Value: See bit description 16.3.1.5 Attribute: Size: RO, R/W1C, RV 16 bit Bit Attr Default Description 15 R/W1C FLR 0b Detected Parity Error: set when the SCU receives a poisoned TLP regardless of the state of the Parity Error Response in the SCUPCMD register. 14 R/W1C FLR 0b SERR# Asserted: set when the SCU sends an ERR FATAL or ERR NONFATAL message, and the SERR Enable bit in the SCUPCMD register is `1'. 13 R/W1C FLR 0b Received Master Abort: set when the SCU receives a completion with Unsupported Request Completion Status. 12 R/W1C FLR 0b Received Target Abort: set when the SCU receives a completion with Completer Abort Completion Status. 11 R/W1C FLR 0b Signaled Target Abort: set when the SCU completes a Request using Completer Abort Completion Status 10:9 RO 00b DEVSEL# Timing: Does not apply to PCI Express. Hard-wired to 0. 8 R/W1C FLR 0b Master Data Parity Error: This bit is set by the SCU if its Parity Error Enable bit is set and either of the following two conditions occurs: * SCU receives a Poisoned Completion for an Outbound Read Request * SCU transmits a Poisoned TLP for an Outbound Write Request. If the Parity Error Response bit is cleared in the "SCUPCMD--SCU PF Command Register (SCU - D0:F0)", this bit is never set. 7 RO 0b Fast Back-to-Back: Does not apply to PCI Express. Hard-wired to 0. 6 RV 0b Reserved 5 RO 0b 66 MHz Capable (C66): Does not apply to PCI Express. Hard-wired to 0 4 RO 1b Capabilities List: All PCI Express* devices are required to implement the PCI Express* capability structure. Hard-wired to 1. 3 RO 0b Interrupt Status: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field is hardwired to 0b for all VFs. Note: This bit does not apply to VFs. 2:0 RV 0b Reserved. SCUVRID x--SCU VF Revision ID Register (D1-3 : F0-7, D4 : F0-6) Address Offset: 08h Default Value: 00h Attribute: Size: RO 8 bit Bit Attr Default Description 07:00 RO-V 00h SCU Revision: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 states that this field should be viewed as a Vendor Defined Extension to the Device ID. In the SCU, this is implemented as a read-only copy of the PF register ("SCUPRID--SCU PF Revision ID Register (SCU - D0:F0)"). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 597 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.3.1.6 SCUVCCR x--SCU VF Class Code Register x (D1-3 : F0-7, D4 : F0-6) Address Offset: 09-0Bh Default Value: 10700h 16.3.1.7 Attr Default Description 23:00 RO 10700h Class Code: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field return the same value as the Section 16.2.1.6 for all VFs. SCUVCLSR x--SCU VF Cacheline Size Register x (D1-3 : F0-7, D4 : F06) Bit Attr Default 07:00 RO 00h Attribute: Size: SCU Cacheline Size: For PCI Express, this field has no impact on device functionality. Furthermore, for all VFs, the Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to 00H. SCUVLT x--SCU VF Latency Timer Register x (D1-3 : F0-7, D4 : F0-6) Bit Attr Default 07:00 RO 00h Attribute: Size: Programmable Latency Timer: The latency timer does not apply to PCI Express. Hard-wired 0. SCUVHTR x--SCU VF Header Type Register x (D1-3 : F0-7, D4 : F0-6) Bit Attr Default 7 RO 0b 06:00 RO 00h Attribute: Size: RO 8 bit Description Multi-Function Device (MFD): The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 states that this field must be 00H for VFs. Header Type: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 states that this field must be 00H for VFs. SVSVIR x--SCU VF Subsystem Vendor ID Register x (D1-3 : F0-7, D4 : F0-6) Address Offset: 2C-2Dh Default Value: 0000h 598 RO 8 bit Description Address Offset: 0Eh Default Value: 00h 16.3.1.10 RO 8 bit Description Address Offset: 0Dh Default Value: 00h 16.3.1.9 RO 24 bit Bit Address Offset: 0Ch Default Value: 00h 16.3.1.8 Attribute: Size: Bit Attr Default 15:0 RO-V 0h Attribute: Size: RO 16 bit Description Subsystem Vendor ID: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that when read, this read only register must return the same value as the Section 16.2.1.16 for all VFs. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.3.1.11 SVSIR x--SCU VF Subsystem ID Register x (D1-3 : F0-7, D4 : F0-6) Address Offset: 2E-2Fh Default Value: 0000h 16.3.1.12 Attr Default Description 15:0 RO-V 0000h Subsystem ID: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this read only register return the same value for all VFs. This register returns the value in the PF (Section 16.2.1.18). SCU VF Cap Ptr x--SCU VF Capabilities Pointer Register x (D1-3 : F0-7, D4 : F0-6) Attribute: Size: Attr Default Description 07:00 R/WL PRST C4h Capability List Pointer: This field provides an offset into the function's configuration space pointing to the first item in the function's capability list which in the SCU VF is the PCI Express* extended capabilities header. SCUVILR x--SCU VF Interrupt Line Register x (D1-3 : F0-7, D4 : F0-6) Bit Attr Default 07:00 RO 00h Attribute: Size: RO 8 bit Description Interrupt Assigned: This field does not apply to VFs and is hardwired to Zero. SCUVIPR x)--SCU VF Interrupt Pin Register x (D1-3 : F0-7, D4 : F0-6) Address Offset: 3Dh Default Value: 00h 16.3.1.15 R/W 8 bit Bit Address Offset: 3Ch Default Value: 00h 16.3.1.14 RO 16 bit Bit Address Offset: 34h Default Value: C4h 16.3.1.13 Attribute: Size: Bit Attr Default 07:00 RO 00h Attribute: Size: RO 8 bit Description Interrupt Used: This field does not apply to VFs and is hardwired to Zero. SCUVMGNT x--SCU VF Minimum Grant Register x (D1-3 : F0-7, D4 : F06) Address Offset: 3Eh Default Value: 00h Bit Attr Default 07:00 RO 00h Attribute: Size: RO 8 bit Description Reserved: This register does not apply to PCI Express. Hard-wired to 0 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 599 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.3.1.16 SCUVMLAT x--SCU VF Maximum Latency Register x (D1-3 : F0-7, D4 : F0-6) Address Offset: 3Fh Default Value: 00h 16.3.2 Bit Attr Default 07:00 RO 00h Attribute: Size: RO 8 bit Description Reserved: This register does not apply to PCI Express. Hard-wired to 0 VF MSI-X Capability Structure This section describes the PCI Configuration Space registers that make up the Message Signaled Interrupts Capability Structure. 16.3.2.1 V MSIX CAP x--VF MSI-X Capability Register x (D1-3 : F0-7, D4 : F0-6) Address Offset: A0-A3h Default Value: See bit description 600 Attribute: Size: R/W, RV, RO 32 bit Bit Attr Default Description 31 R/W FLR 0b MSI-X Enable: If set, the SMU is able to use MSI-X to request service. 30 R/W FLR 0b Function Mask: If set, all the vectors in the MSI-X Table are globally masked, regardless of the per-vector Mask Bit states in the Vector Control Register of the MSI-X Table entries. 29:27 RV 000b Reserved MSI-X Table Size: This field indicates the MSI-X Table size N. This field is encoded as N-1. Up to two messages can be generated (Single SCU) or 4 messages (Dual SCU). SCU Configuration Default Value Single 001h (2 vectors) Dual 003h (4 vectors) 26:16 RO-V FLR 001h 15:8 RO 00h Next Item Pointer: This field provides an offset into the function's configuration space pointing to the next item in the function's capability list. Since the MSI-X capability is the last in the linked list of extended capabilities in the SCU, this register is set to 00H. 7:0 RO 11h Capability ID: A value of 11H identifies this as the Message Signaled Interrupt (MSI-X) Capability. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.3.2.2 SV MSIX TOR x--VF MSI-X Table Offset Register x (D1-3 : F0-7, D4 : F0-6) Address Offset: A4-A7h Default Value: See bit description Bit 31:3 Attr RO-V FLR Default 400h Attribute: Size: RO 32 bit Description MSI-X Table Offset: Indicates the starting QWORD offset of the MSI-X Table relative to the Base Address for the VF (VF_Base). The offset is a function of the System Page Size as follows: System Page SizeValueByte Offset from Base of VF 4 KB 400H 8 KB 8 KB 400H 8 KB 64 KB 2000H 64 KB 256 KB 8000H 256 KB 1 MB 2 0000H 1 MB 4 MB 8 0000H 4 MB The byte offset of the MSI-X table is also given by the following equation: MSIX_Offset = Max(8KB, System_Page_Size) The absolute starting address of the MSI-X table for a VF having VF index of VFi is given by the following equation: MSIX_Addr = VF_Base + MSIX_Offset To determine VF_Base, please refer to "SR-IOV Base Address Register 0 (SRIOVBAR0)" 2:0 RO 000b MSI-X Table BAR Indication Register (BIR): indicates which Base Address Register of the SMU function the MSI-X Table is mapped into. BIR Value Base Address Register 0 SRIOVBAR0 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 601 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.3.2.3 V MSIX PBAOR x--VF MSI-X Pending Bit Array Offset Register x (D1-3 : F0-7, D4 : F0-6) Address Offset: A8-ABh Default Value: See bit description Bit 31:3 2:0 16.3.3 Attr RO-V FLR RO Attribute: Size: RO 32 bit Default Description 600h PBA Offset: Indicates the starting QWORD offset of the Pending Bit Array relative to the Base Address for the VF (VF_Base). The offset is a function of the System Page Size as follows: System Page SizeValueByte Offset from Base of VF 4 KB 600H 8 KB + 4 KB 8 KB 600H 8 KB + 4 KB 64 KB 2200H 64 KB + 4 KB 256 KB 8200H 256 KB + 4 KB 1 MB 2 0200H 1 MB + 4 KB 4 MB 8 0200H 4 MB + 4 KB The byte offset of the PBA is also given by the following equation: PBA_Offset = Max(8KB, System_Page_Size) + 4 KB The absolute starting address of the PBA for a VF having VF index of VFi is given by the following equation: PBA_Addr = VF_Base + PBA_Offset To determine VF_Base, please refer to "SR-IOV Base Address Register 0 (SRIOVBAR0)". 000b PBA BAR Indication Register (BIR): indicates which Base Address Register of the SMU function the Pending Bit Array is mapped into. BIR Value Base Address Register 0 SRIOVBAR0 VF PCI Express* Capability Structure This section describes the PCI Configuration Space registers that make up the PCI Express* Capability Structure. 16.3.3.1 SCU V I EXP CAPID x--SCU VF PCI Express* Capability Identifier Register x (D1-3 : F0-7, D4 : F0-6) Address Offset: C4h Default Value: 10h 602 Bit Attr Default 7:0 RO 10h Attribute: Size: RO 8 bit Description Cap Id: This field identifies this item in the linked list of Extended Capability Headers as being the PCI Express capability registers. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.3.3.2 SCU V I EXP NXTP x--SCU VF I PCI Express* Next Item Pointer Register x (D1-3 : F0-7, D4 : F0-6) Address Offset: C5h Default Value: A0h 16.3.3.3 Attribute: Size: R/W 8 bit Bit Attr Default Description 7:0 R/WL PRST A0h Next Item Pointer: This field provides an offset into the function's configuration space pointing to the next item in the function's capability list which in the SCU is the MSI-X extended capabilities header. SCU V I EXP CAP x--SCU VF PCI Express* Capabilities Register x (D1-3 : F0-7, D4 : F0-6) Address Offset Default Value: : C6-C7h See bit description Attribute Size: RO, RV 16 bit Bit Attr Default 15:14 RV 00b 13:9 RO 00000b Interrupt Message Number: This only applies to Root Complex and Switch devices. This register is hardcoded to 0. Slot Implemented: Indicates that the PCI Express* Link associated with this port is connected to a slot. Only valid for root complex and switch downstream ports. Hard-wired to 0 8 RO 0b 7:4 RO 0000b 3:0 RO 2h Description Preserved Device/Port Type: Indicates the type of PCI Express* logical device. 0000b = PCI Express* Endpoint device Capability Version: Indicates PCI-SIG defined PCI Express* capability structure version number SCU supports version 2h. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 603 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.3.3.4 SCU V I EXP DCAP x--SCU VF PCI Express* Device Capabilities Register x (D1-3 : F0-7, D4 : F0-6) Address Offset: C8-CBh Default Value: See bit description 16.3.3.5 RV, RO 32 bit Bit Attr Default Description 31:29 RV 000b 28 RO 1b 27:26 RO 00b Captured Slot Power Limit Scale: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 states that this field is undefined for all VFs. 25:18 RO 00h Captured Slot Power Limit Value: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 states that this field is undefined for all VFs. 17:16 RV 00b Preserved 15 RO 1b Role-Based Error Reporting: this bit is set to indicate that this device implements the Role Base Error Reporting defined in PCI Express Base Specification, Revision 2.0. 14 RV 0b Reserved: Undefined - Treated as Reserved 13 RV 0b Reserved: Undefined - Treated as Reserved 12 RV 0b Reserved: Undefined - Treated as Reserved 11:9 RO 000b Endpoint L1 Acceptable Latency: Total acceptable latency that the SCU can withstand due to a transition from L1 state. 8:6 RO 111b Endpoint L0 Acceptable Latency: Total acceptable latency that the SCU can withstand due to a transition from L0s to L0 state. 5 RO 0b Extended Tag Field Supported: The SCU does support generation of 8-bit Tags. 4:3 RO 00b Phantom Functions Supported: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field is hardwired to 00b. 2:0 RO 011b Preserved FLR Cap: Function Level Reset Capability is required for all VFs and PFs according to the Single Root I/O Virtualization and Sharing Specification, Revision 0.9. Max Payload Size Supported: Indicates that the SCU can support a max payload of 1 KB SCU V I EXP DCTL x--SCU VF PCI Express* Device Control Register x (D1-3 : F0-7, D4 : F0-6) Address Offset: CC-CDh Default Value: 0000h 604 Attribute: Size: Attribute: Size: RO, R/W 16 bit Bit Attr Default Description 15 R/W-V 0b 14:12 RO 000b 11 RO 0b Enable No Snoop: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field is hardwired to all zeros. 10 RO 0b Aux Power PM Enable: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field is hardwired to all zeros. 9 RO 0b Phantom Functions Enable: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field is hardwired to all zeros. 8 RO 0b Extended Tag Field Enable: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field is hardwired to all zeros. 7:5 RO 000b 4 RO 0b Initiate Function Level Reset: A write of 1b to this bit initiates Function Level Reset to the function. The value is always read as 0b. Max Read Request Size: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field is hardwired to all zeros. Max Payload Size: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field is hardwired to all zeros. Enable Relaxed Ordering: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field is hardwired to all zeros. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.3.3.6 Bit Attr Default Description 3 RO 0b Unsupported Request Reporting Enable (URRE): The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field is hardwired to all zeros. 2 RO 0b Fatal Error Reporting Enable: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field is hardwired to all zeros. 1 RO 0b Non-Fatal Error Reporting Enable: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field is hardwired to all zeros. 0 RO 0b Correctable Error Reporting Enable: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field is hardwired to all zeros. SCU V I EXP DSTS x--SCU VF PCI Express* Device Status Register x (D1-3 : F0-7, D4 : F0-6) Address Offset: CE-CFh Default Value: 0000h Bit Attr Default 15:6 RV 000h RO, R/W1C, RV 16 bit Description Reserved 5 RO-V FLR 0b Transactions Pending: This bit when set indicates that a device has issued NonPosted Requests which have not been completed. A device reports this bit cleared only when all Completions for any outstanding Non-Posted Requests have been received. 4 RO 0b AUX Power Detected: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field is hardwired to all zeros. 3 R/W1C FLR 0b Unsupported Request Detected: This bit indicates that the device received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control Register. For a multi-function device, each function indicates status of errors as perceived by the respective function. 0b Fatal Error Detected: This bit indicates status of fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For devices supporting Advanced Error Handling, errors are logged in this register regardless of the settings of the uncorrectable error mask register. For a multi-function device, each function indicates status of errors as perceived by the respective function. 0b Non-Fatal Error Detected: This bit indicates status of non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For devices supporting Advanced Error Handling, errors are logged in this register regardless of the settings of the uncorrectable error mask register. For a multi-function device, each function indicates status of errors as perceived by the respective function. 0b Correctable Error Detected: This bit indicates status of correctable errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For devices supporting Advanced Error Handling, errors are logged in this register regardless of the settings of the correctable error mask register. For a multi-function device, each function indicates status of errors as perceived by the respective function. 2 1 0 16.3.3.7 Attribute: Size: R/W1C FLR R/W1C FLR R/W1C FLR SCU V I EXP LCAP x--SCU VF PCI Express* Link Capabilities Register x (D1-3 : F0-7, D4 : F0-6) Address Offset: D0-D3h Default Value: See bit description Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Attribute: Size: RO, RV 32 bit 605 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.3.3.8 Bit Attr Default Description 31:24 RO 00h Port #: PCI Express* port number: 23:18 RV 00h Preserved 17:15 RO 000b L1 Exit Latency: 14:12 RO 000b L0s Exit Latency: 11:10 RO 11b 9:4 RO 1h Maximum Link Width: This device supports a maximum width of x8. 3:0 RO 1h Maximum Link Speed: The PCI Express* Link operates at 2.5Gb/s. Active State Link PM Support: SCU V I EXP LCTL x--SCU VF PCI Express* Link Control Register x (D13 : F0-7, D4 : F0-6) Address Offset: D4-D5h Default Value: 0000h 16.3.3.9 RO, RV 16 bit Bit Attr Default Description 15:10 RV 00b Preserved Reserved: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field is hardwired to all zeros. 9:8 RO 00b 7 RO 0b Extended Synch: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field is hardwired to all zeros. 6 RO 0b Common Clock Configuration: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field is hardwired to all zeros.r 5 RO 0b Retrain Link: Not Applicable to endpoints. Hard-wired to 0 4 RO 0b Link Disable: Not Applicable to endpoints. Hard-wired to 0 3 RO 0b Read Completion Boundary (RCB) Control: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field is hardwired to all zeros. 2 RV 0b Preserved 1:0 RO 00b Active State PM Control: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field is hardwired to all zeros. SCU V I EXP LSTS x--SCU VF PCI Express* Link Status Register x (D13 : F0-7, D4 : F0-6) Address Offset: D6-D7h Default Value: 0000h 16.3.4 Attribute: Size: Bit Attr Default 15:0 RV 0000h Attribute: Size: RV 16 bit Description Reserved VF Advanced Error Reporting Extended Capability Structure This section describes the PCI Express* Extended Configuration Space registers that make up the Advanced Error Reporting Extended Capability Structure. 16.3.4.1 SCU V I AERR CAPID x--SCU VF PCI Express* Advanced Error Capability Identifier x (D1-3 : F0-7, D4 : F0-6) Address Offset: 100-103h 606 Attribute: RO, R/W Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) Default Value: 16.3.4.2 See bit description Size: 32 bit Bit Attr Default Description 31:20 R/WL PRST 138h Next Capability Pointer: This field points to the Alternative Routing ID extended capability. 19:16 RO 1h Capability Version Number: PCI Express Advanced Error Reporting Extended Capability Version Number. 15:0 RO 0001h Advanced Error Capability ID: PCI Express Extended Capability ID indicating Advanced Error Reporting Capability. SCU V I ERRUNC STS x--SCU VF PCI Express* Uncorrectable Error Status x (D1-3 : F0-7, D4 : F0-6) Address Offset: 104-107h Default Value: 00000000h Attribute: Size: RV, R/W1CS 32 bit Bit Attr Default Description 31:21 RV 0 20 R/W1CS 0b Unsupported Request Error Status: As a receiver, Set whenever an unsupported request is detected. The Header is logged. 19 RV 0b ECRC Check: As a non-function specific error, the Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros. 18 RV 0b Malformed TLP: As a non-function specific error, the Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros. 17 RV 0b Receiver Overflow: As a non-function specific error, the Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros. 16 R/W1CS 0b Unexpected Completion: As a receiver, set whenever a completion is received that does not match the SCU requestor ID or outstanding Tag. The Header is logged. 15 R/W1CS 0b Completer Abort: As a completer, set whenever an internal agent signals a data abort. The header is logged. 14 R/W1CS 0b Completion Timeout: As a requester, set whenever an outbound Non Posted Request does not receive a completion within 16-32 ms. 13 RV 0b Flow Control Protocol Error Status: As a non-function specific error, the Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros. 12 R/W1CS 0b Poisoned TLP Received: As a receiver, set whenever a poisoned TLP is received from PCI Express. The header is logged. Note that internal queue errors are not covered by this bit, they are logged by the Configuration target of the transaction. 11:6 RV 0b Reserved 5 RV 0b Surprise Down Error: As a non-function specific error, the Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros. 4 RV 0b Data Link Protocol Error: As a non-function specific error, the Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros. 3:0 RV 0h Reserved Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 607 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.3.4.3 SCU V I ERRUNC MSK x--SCU VF PCI Express* Uncorrectable Error Mask x (D1-3 : F0-7, D4 : F0-6) Address Offset: 108-10Bh Default Value: 00000000h 608 Attribute: Size: RV 32 bit Bit Attr Default Description 31:22 RV 0 21 RV 0b ACS Violation Error Mask: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros and that the setting of this mask in Section 16.2.5.3 applies to all of the VFs. 20 RV 0b Unsupported Request Error Mask: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros and that the setting of this mask in Section 16.2.5.3 applies to all of the VFs. 19 RV 0b ECRC Check Error Mask: As a non-function specific error, the Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros. 18 RV 0b Malformed TLP Error Mask: As a non-function specific error, the Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros. 17 RV 0b Receiver Overflow Error Mask: As a non-function specific error, the Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros. 16 RV 0b Unexpected Completion Error Mask: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros and that the setting of this mask in Section 16.2.5.3 applies to all of the VFs. 15 RV 0b Completer Abort Error Mask: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros and that the setting of this mask in Section 16.2.5.3 applies to all of the VFs. 14 RV 0b Completion Time Out Error Mask: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros and that the setting of this mask in Section 16.2.5.3 applies to all of the VFs. 13 RV 0b Flow Control Protocol Error Mask: As a non-function specific error, the Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros. 12 RV 0b Poisoned TLP Received Error Mask: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros and that the setting of this mask in Section 16.2.5.3 applies to all of the VFs. 11:6 RV 00h 5 RV 0b Surprise Down Error Mask: As a non-function specific error, the Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros. 4 RV 0b Data Link Protocol Error Mask: As a non-function specific error, the Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros. 3:0 RV 0h Reserved Reserved Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.3.4.4 SCU V I ERRUNC SEV x--SCU VF PCI Express* Uncorrectable Error Severity x (D1-3 : F0-7, D4 : F0-6) Address Offset: 10C-10Fh Default Value: 00000000h Attribute: Size: RV 32 bit Bit Attr Default Description 31:22 RV 0 21 RV 0b ACS Violation Error Severity: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros and that the setting of this field in Section 16.2.5.4 applies to all of the VFs. 20 RV 0b Unsupported Request Error Severity: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros and that the setting of this field in Section 16.2.5.4 applies to all of the VFs. 19 RV 0b ECRC Check Error Severity: As a non-function specific error, the Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros. 18 RV 0b Malformed TLP Error Severity: As a non-function specific error, the Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros. 17 RV 0b Receiver Overflow Error Severity: As a non-function specific error, the Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros. 16 RV 0b Unexpected Completion Error Severity: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros and that the setting of this field in Section 16.2.5.4 applies to all of the VFs. 15 RV 0b Completer Abort Error Severity: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros and that the setting of this field in Section 16.2.5.4 applies to all of the VFs. 14 RV 0b Completion Time Out Error Severity: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros and that the setting of this field in Section 16.2.5.4 applies to all of the VFs. 13 RV 0b Flow Control Protocol Error Severity: As a non-function specific error, the Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros. 12 RV 0b Poisoned TLP Received Error Field: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros and that the setting of this field in Section 16.2.5.4 applies to all of the VFs. 11:6 RV 00h 5 RV 0b Surprise Down Error Severity: As a non-function specific error, the Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros. 4 RV 0b Data Link Protocol Error Severity: As a non-function specific error, the Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros. 3:0 RV 0h Reserved Reserved Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 609 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.3.4.5 SCU V I ERRCOR STS x--SCU VF PCI Express* Correctable Error Status x (D1-3 : F0-7, D4 : F0-6) Address Offset: 110-113h Default Value: 00000000h 16.3.4.6 RV, R/W1C 32 bit Bit Attr Default Description 31:14 RV 0 13 R/W1CS 0b Advisory Non-Fatal Error Status 12 RV 0b Replay Timer Timeout Status: As a non-function specific error, the Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros. 11:9 RV 000b Reserved Reserved 8 RV 0b REPLAY NUM Rollover Status: As a non-function specific error, the Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros. 7 RV 0b Bad DLLP Status: As a non-function specific error, the Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros. 6 RV 0b Bad TLP Status: As a non-function specific error, the Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros. 5:1 RV 00h 0 RV 0b Reserved Receiver Error Status: As a non-function specific error, the Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros. SCU V I ERRCOR MSK x--SCU VF PCI Express* Correctable Error Mask x (D1-3 : F0-7, D4 : F0-6) Address Offset: 114-117h Default Value: 00000000h 610 Attribute: Size: Attribute: Size: RV 32 bit Bit Attr Default Description 31:14 RV 0 13 RV 0b Advisory Non-Fatal Error Mask: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be treated as Preserved and that the setting of the corresponding bit in Section 16.2.5.6 will apply to the VFs. 12 RV 0b Replay Timer Timeout Mask: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be treated as Preserved and that the setting of the corresponding bit in Section 16.2.5.6 will apply to the VFs. 11:9 RV 000b Reserved Reserved 8 RV 0b REPLAY NUM Rollover Mask: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be treated as Preserved and that the setting of the corresponding bit in Section 16.2.5.6 will apply to the VFs. 7 RV 0b Bad DLLP Mask: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be treated as Preserved and that the setting of the corresponding bit in Section 16.2.5.6 will apply to the VFs. 6 RV 0b Bad TLP Mask: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be treated as Preserved and that the setting of the corresponding bit in Section 16.2.5.6 will apply to the VFs. 5:1 RV 00h 0 RV 0b Reserved Receiver Error Mask: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be treated as Preserved and that the setting of the corresponding bit in Section 16.2.5.6 will apply to the VFs. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.3.4.7 SCU V I ADVERR CTL x--SCU VF Advanced Error Control and Capability Register x) (D1-3 : F0-7, D4 : F0-6) Address Offset: 118-11Bh Default Value: 00000000h Attribute: Size: RV, RO 32 bit Bit Attr Default Description 31:9 RV 0 8 RV 0b ECRC Check Enable: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros and that the setting of this field in Section 16.2.5.7 applies to all of the VFs. 7 RO 0b ECRC Check Capable: Indicates the SCU is not capable of checking ECRC. 6 RV 0b ECRC Generation Enable: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 requires that this field be hardwired to all zeros and that the setting of this field in Section 16.2.5.7 applies to all of the VFs. 5 RO 0b ECRC Generation Capable: Indicates the SCU is not capable of generating ECRC. 4:0 ROS-V 00000b Reserved The First Error Pointer: Identifies the bit position of the first error reported in Section 16.3.4.2 register. Note: This register will not update until all bits in the ERRUNC STS register are cleared. 16.3.5 Advanced Error Header Log Registers 16.3.5.1 VADVERR LOG0 x--SCU VF PCI Express* Advanced Error Header Log x (D1-3 : F0-7, D4 : F0-6) Address Offset: 11C-11Fh Default Value: 00000000h 16.3.5.2 Attribute: Size: RO 32 bit Bit Attr Default Description 31:0 ROS-V 0 1st DWord of the Header for the PCIe packet in error (HDRLOGDW0): Once an error is logged in this register, it remains locked for further error logging until the time the software clears the status bit that cause the header log, that is, the error pointer is rearmed to log again. VADVERR LOG1 x--SCU VF PCI Express* Advanced Error Header Log x (D1-3 : F0-7, D4 : F0-6) Address Offset: 120-123h Default Value: 00000000h Attribute: Size: RO 32 bit Bit Attr Default Description 31:0 ROS-V 0 2nd DWord of the Header for the PCIe packet in error (HDRLOGDW1): Once an error is logged in this register, it remains locked for further error logging until the time the software clears the status bit that cause the header log, that is, the error pointer is rearmed to log again. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 611 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.3.5.3 VADVERR LOG2 x--SCU VF PCI Express* Advanced Error Header Log x (D1-3 : F0-7, D4 : F0-6) Address Offset: 124-127h Default Value: 00000000h 16.3.5.4 RO 32 bit Bit Attr Default Description 31:0 ROS-V 0 3rd DWord of the Header for the PCIe packet in error (HDRLOGDW2): Once an error is logged in this register, it remains locked for further error logging until the time the software clears the status bit that cause the header log, that is, the error pointer is rearmed to log again. VADVERR LOG3 x--SCU VF PCI Express* Advanced Error Header Log x (D1-3 : F0-7, D4 : F0-6) Address Offset: 128-12Bh Default Value: 00000000h 16.3.6 Attribute: Size: Attribute: Size: RO 32 bit Bit Attr Default Description 31:0 ROS-V 0 4th DWord of the Header for the PCIe packet in error (HDRLOGDW3): Once an error is logged in this register, it remains locked for further error logging until the time the software clears the status bit that cause the header log, that is, the error pointer is rearmed to log again. VF Alternative Routing ID Extended Capability Structure This section describes the PCI Express* Extended Configuration Space registers that make up the Alternative Routing ID Extended Capability Structure. 16.3.6.1 VARIDHDR x--VF Alternative Routing ID Capability Header x (D1-3 : F0-7, D4 : F0-6) Address Offset: 138-13Bh Default Value: see bit description 16.3.6.2 RO, R/W 32 bit Bit Attr Default Description 31:20 R/WL PRST 180h Next Capability Offset: This field contains 180h which points to the next item in the extended capabilities list, the TPH requester extended capability. 19:16 RO 1h 15:0 RO 000Eh Capability Version: This is set to 1h for the most current version of the specification. PCI Express* Extended Capability ID: The PCI SIG has assigned 000Eh to the ARI extended capability. VARIDCAP x--VF Alternative Routing ID Capability Register x (D1-3 : F0-7, D4 : F0-6) Address Offset: 13C-13Dh Default Value: 0000h 612 Attribute: Size: Attribute: Size: RV, RO 16 bit Bit Attr Default Description 15:8 RV 00h Next Function Number: The Single Root I/O Virtualization and Sharing Specification, Revision 0.9 states that this field is undefined for VFs. 7:2 RV 00h Reserved 1 RO 0b ACS Functional Groups Capability: SCU does not support. 0 RO 0b MFVC Functional Groups Capability: SCU does not support. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.3.6.3 VARIDCTL x--VF Alternative Routing ID Control Register x (D1-3 : F07, D4 : F0-6) Address Offset: 13E-13Fh Default Value: 0000h Attribute: Size: RV, RO 16 bit Bit Attr Default Description 15:7 RV 000h 6:4 RO 0h 3:2 RV 00b 1 RO 0b ACS Functional Groups Enable: Hardwired to Zero as SCU does not support. 0 RO 0b MFVC Functional Groups Enable: Hardwired to Zero as SCU does not support. Reserved Function Group: Hardwired to Zero as SCU does not support Function Groups. Reserved 16.3.7 VF TPH Requester Extended Capability Structure 16.3.7.1 VTPHRHDR x--VF TPH Requester Capability Header x (D1-3 : F0-7, D4 : F0-6) Address Offset: 180-183h Default Value: See bit description 16.3.7.2 Bit Attr Default 31:20 RO 000h 19:16 RO 1h 15:0 RO 0017h Attribute: Size: RO 32 bit Description Next Capability Offset: This field contains 000h indicating the end of the SCUs VF Extended capability list. Capability Version: This is set to 1h for the most current version of the specification. PCI Express* Extended Capability ID: The PCI SIG has assigned 0017h to the TPH Requester extended capability. VTPHRCAP x--VF TPH Requester Capability Register x (D1-3 : F0-7, D4 : F0-6) Address Offset: 184-187h Default Value: See bit description Bit Attr Default Attribute: Size: RV, RO 32 bit Description 31:27 RV 00h 26:16 RO 000h Reserved 15:11 RV 00h 10:9 RO 0h ST Table Location: ST Table is not present. 8 RO 0b Extended TPH Requester Supported: SCU does not generate requests with the TPH TLP Prefix. 7:3 RV 00h 2 RO 1b Device Specific Mode Supported: SCU supports the Device Specific Mode of operation. 1 RO 0b Interrupt Vector Mode Supported: SCU does not support the Interrupt Vector Mode of operation. 0 RO 1b No ST Mode Supported: SCU supports the No ST Mode of operation. ST Table Size: ST Table is not present. Reserved Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 613 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.3.7.3 VTPHRCTL x--VF TPH Requester Control Register x (D1-3 : F0-7, D4 : F0-6) Address Offset: 188-18Bh Default Value: 0000h RV, RO, R/W 32 bit Bit Attr Default 31:10 RV 00h 9 RO 0b Extended TPH Enable: The SCU is never Extended TPH enabled. 8 R/W FLR 0b TPH Requester Enable: When set, the SCU is permitted to use TPH. 7:3 RV 00h 2:0 Description Reserved Reserved 0h 16.4 Attribute: Size: ST Mode Select: Sets the ST mode of operation. 000b- No ST Mode 001b- Interrupt Vector Mode (not supported; behaves as No ST Mode) 010b- Device Specific Mode Others- Reserved (behave as No ST Mode) R/W FLR SCU SGPIO Memory Mapped Registers The memory mapped registers are accessible using memory transactions on the PCI Express* interface. Their offsets are relative to SCUPBAR1 in Section 16.2.1.13. Table 16-8. SGPIO Memory Mapped Registers SCUPUBAR1 + offset 16.4.1 Mnemonic Register Name Access 1400h-1403h SGICR SGPIO Interface Control Register 00000000h R/W, RO 1404h-1407h SGPBR SGPIO Programmable Blink Register 00000000h R/W, RO 1408h-140Bh SGSDLR SGPIO Start Drive Lower Register 00000000h R/W, RO 140Ch-140Fh SGSDUR SGPIO Start Drive Upper Register 00000000h R/W, RO 1410h-1413h SGSIDLR SGPIO Serial Input Data Lower Register 00000000h RO 1414h-1417h SGSIDUR SGPIO Serial Input Data Upper Register 00000000h RO 1418h-141Bh SGVSCR SGPIO Vendor Specific code Register 00000000h R/W, RO 141Ch-141fh -- 0h -- 1420h-143Fh SGODSR[0-7] 00000000h R/W, RO 1440h-14FFh -- 0h -- Reserved SGPIO Output Data Slect Register Reserved SGICR- SGPIO Interface Control Register Address Offset: SCUPBAR1+1400h Default Value: 00000000h 614 Default Bit Attr Default 31:03 RO 000000 0h 02 R/W 0b Attribute: Size: R/W, RO 32 bit Description Reserved. SGPIO Serial Shift Register Width Select (SSSRWS): This bit selects the width of the SGPIO Serial Shift Register. 0 = The shift register is 12 bits wide. (Default) 1 = The shift register is 24 bits wide. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) Bit Attr Default Description 01 R/W 0b SGPIO Serial Clock Rate Select (SSCRS): This bit selects the frequency of the SGPIO serial clock. 0 = The SGPIO serial clock runs at 99.8 KHz 1 = The SGPIO serial clock runs at 49.9 KHz. 0b SGPIO Functionality Enable (SFE): 1 = The SGPIO bus pins (SCLOCK, SLOAD, SDATAIN and SDATAOUT) are used for SGPIO signaling. 0 = The SGPIO pins are used for Direct LED controls. (Default) 00 16.4.2 R/W SGPBR- SGPIO Programmable Blink Register Address Offset: SCUPBAR1+1404h Default Value: 00000000h Attribute: Size: R/W, RO 32 bit Bit Attr Default 31:16 RO 0000h Reserved. 0000b Programmable Pattern B High Duration Time (PPBHDT): This field is used to program the high duration time in millisecond for pattern B. 0000 = 125 ms 0001 = 250 ms 0010 = 375 ms 0011 = 500 ms 0100 = 625 ms 0101 = 750 ms 0110 = 875 ms 0111 = 1000 ms 1000 = 1125 ms 1001 = 1250 ms 1010 = 1375 ms 1011 = 1500 ms 1100 = 1625 ms 1101 = 1750 ms 1110 = 1875 ms 1111 = 2000 ms 0000b Programmable Pattern B Low Duration Time (PPBLDT): This field is used to program the low duration time in millisecond for pattern B. 0000 = 125 ms 0001 = 250 ms 0010 = 375 ms 0011 = 500 ms 0100 = 625 ms 0101 = 750 ms 0110 = 875 ms 0111 = 1000 ms 1000 = 1125 ms 1001 = 1250 ms 1010 = 1375 ms 1011 = 1500 ms 1100 = 1625 ms 1101 = 1750 ms 1110 = 1875 ms 1111 = 2000 ms 15:12 11:8 R/W R/W Description Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 615 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) Bit 7:4 3:0 16.4.3 Attr R/W R/W Default Description 0000b Programmable Pattern A High Duration Time (PPAHDT): This field is used to program the high duration time in millisecond for pattern A. 0000 = 125 ms 0001 = 250 ms 0010 = 375 ms 0011 = 500 ms 0100 = 625 ms 0101 = 750 ms 0110 = 875 ms 0111 = 1000 ms 1000 = 1125 ms 1001 = 1250 ms 1010 = 1375 ms 1011 = 1500 ms 1100 = 1625 ms 1101 = 1750 ms 1110 = 1875 ms 1111 = 2000 ms 0000b Programmable Pattern A Low Duration Time (PPALDT): This field is used to program the low duration time in millisecond for pattern A. 0000 = 125 ms 0001 = 250 ms 0010 = 375 ms 0011 = 500 ms 0100 = 625 ms 0101 = 750 ms 0110 = 875 ms 0111 = 1000 ms 1000 = 1125 ms 1001 = 1250 ms 1010 = 1375 ms 1011 = 1500 ms 1100 = 1625 ms 1101 = 1750 ms 1110 = 1875 ms 1111 = 2000 ms SGSDLR- SGPIO Start Drive Lower Register Address Offset: SCUPBAR1+1408h Default Value: 00000000h Bit Attr Default 31:15 RO 0000h 14:12 R/W 011b 11 RO 0b 10:08 616 R/W 010b Attribute: Size: R/W, RO 32 bit Description Reserved. Output 3 Select Bits (O3SB): This bit field selects which Input[7:0] of the Multiplexer Block is selected to drive Output 3. 000 = Input[0] 001 = Input[1] 010 = Input[2] 011 = Input[3] 100 = Input[4] 101 = Input[5] 110 = Input[6] 111 = Input[7] Reserved. Output 2 Select Bits (O2SB): This bit field selects which Input[7:0] of the Multiplexer Block is selected to drive Output 2. 000 = Input[0] 001 = Input[1] 010 = Input[2] 011 = Input[3] 100 = Input[4] 101 = Input[5] 110 = Input[6] 111 = Input[7] Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) Bit Attr Default 07 RO 0b 06:04 R/W 001b 03 RO 0b 02:00 16.4.4 R/W 000b Description Reserved. Output 1 Select Bits (O1SB): This bit field selects which Input[7:0] of the Multiplexer Block is selected to drive Output 1. 000 = Input[0] 001 = Input[1] 010 = Input[2] 011 = Input[3] 100 = Input[4] 101 = Input[5] 110 = Input[6] 111 = Input[7] Reserved. Output 0 Select Bits (O0SB): This bit field selects which Input[7:0] of the Multiplexer Block is selected to drive Output 0. 000 = Input[0] 001 = Input[1] 010 = Input[2] 011 = Input[3] 100 = Input[4] 101 = Input[5] 110 = Input[6] 111 = Input[7] SGSDUR- SGPIO Start Drive Upper Register Address Offset: SCUPBAR1+140Ch Default Value: 00000000h Bit Attr Default 31:15 RO 0000h 14:12 R/W 111b 11 RO 0b 10:08 R/W 110b 07 RO 0b 06:04 R/W 101b Attribute: Size: R/W, RO 32 bit Description Reserved. Output 7 Select Bits (O7SB): This bit field selects which Input[7:0] of the Multiplexer Block is selected to drive Output 7. 000 = Input[0] 001 = Input[1] 010 = Input[2] 011 = Input[3] 100 = Input[4] 101 = Input[5] 110 = Input[6] 111 = Input[7] Reserved. Output 6 Select Bits (O6SB): This bit field selects which Input[7:0] of the Multiplexer Block is selected to drive Output 6. 000 = Input[0] 001 = Input[1] 010 = Input[2] 011 = Input[3] 100 = Input[4] 101 = Input[5] 110 = Input[6] 111 = Input[7] Reserved. Output 5 Select Bits (O5SB): This bit field selects which Input[7:0] of the Multiplexer Block is selected to drive Output 5. 000 = Input[0] 001 = Input[1] 010 = Input[2] 011 = Input[3] 100 = Input[4] 101 = Input[5] 110 = Input[6] 111 = Input[7] Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 617 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) Bit Attr Default 03 RO 0b 02:00 16.4.5 R/W 100b Description Reserved. Output 4 Select Bits (O4SB): This bit field selects which Input[7:0] of the Multiplexer Block is selected to drive Output 4. 000 = Input[0] 001 = Input[1] 010 = Input[2] 011 = Input[3] 100 = Input[4] 101 = Input[5] 110 = Input[6] 111 = Input[7] SGSIDLR- SGPIO Input Data Lower Register Address Offset: SCUPBAR1+1410h Default Value: 00000000h Bit 16.4.6 Attr Default 31:15 RO 0000h 14:12 RO 000b 11 RO 0b 10:08 RO 000b 07 RO 0b 06:04 RO 000b 03 RO 0b 02:00 RO 000b Reserved. Drive 3 input data (D3ID):. Reserved. Drive 2 input data (D2ID):. Reserved. Drive 1 input data (D1ID):. Reserved. Drive 0 input data (D0ID):. SGSIDUR- SGPIO Input Data Upper Register Bit Attr Default 31:15 RO 0000h 14:12 RO 000b 11 RO 0b 10:08 RO 000b 07 RO 0b 06:04 RO 000b 03 RO 0b 02:00 RO 000b Attribute: Size: RO 32 bit Description Reserved. Drive 7 input data. (D7ID):. Reserved. Drive 6 input data (D6ID):. Reserved. Drive 5 input data (D5ID):. Reserved. Drive 4 input data (D4ID):. SGVSCR- SGPIO Vendor Specific Code Register Address Offset: SCUPBAR1+1418h Default Value: 00000000h 618 RO 32 bit Description Address Offset: SCUPBAR1+1414h Default Value: 00000000h 16.4.7 Attribute: Size: Bit Attr Default 31:04 RO 0000000h Attribute: Size: R/W, RO 32 bit Description Reserved. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) Bit Attr Default Description 03:00 R/W 0h Vendor Specific data (VSD): The four bits vendor-specific code is the first four bits shifted on the SLoad pin after SLoad is driven high. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 619 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only) 16.4.8 SGODSR[0-7]--SGPIO Output Data Select Register[0-7] Address Offset: SCUPBAR1+1420h SCUPBAR1+1424h SCUPBAR1+1428h SCUPBAR1+142Ch SCUPBAR1+1430h SCUPBAR1+1434h SCUPBAR1+1438h SCUPBAR1+143Ch Default Value: 00000000h Bit Attr Default 31:12 RO 00000h Attribute: Size: R/W, RO 32 bit Description Reserved. 11 R/W 0b OD2 JOG Enable (OD2JE): When set this bit enables the jog mechanism to be applied on the input selected by bits[09:08]. When cleared, the selected input is not altered. 10 R/W 0b Invert OD2 Selected Input (IOD2SI): When set this bit causes the input selected by bits[09:08] to be inverted. When cleared, the selected input is not altered. 09:08 R/W 00b OD2 Input Select (OD2IS): This field selects the input that drives output OD2 of Drive N, where N = 0-7. 00 = Fixed - High 01 = Programmable pattern A 10 = Programmable pattern B 11 = Reserved 07 R/W 0b OD1 JOG Enable (OD1JE): When set this bit enables the jog mechanism to be applied on the input selected by bits[05:04]. When cleared, the selected input is not altered. 06 R/W 0b Invert OD1 Selected Input (IOD1SI): When set this bit causes the input selected by bits[05:04] to be inverted. When cleared, the selected input is not altered. 05:04 R/W 00b OD1 Input Select (OD1IS): This field selects the input that drives output OD1 of Drive N, where N = 0-7. 00 = Fixed - High 01 = Programmable pattern A 10 = Programmable pattern B 11 = FSENG Activity 03 R/W 0b OD0 JOG Enable (OD0JE): When set this bit enables the jog mechanism to be applied on the input selected by bits[01:00]. When cleared, the selected input is not altered. 02 R/W 0b Invert OD0 Selected Input (IOD0SI): When set this bit causes the input selected by bits[01:00] to be inverted. When cleared, the selected input is not altered. 01:00 R/W 00b OD0 Input Select (OD0IS): This field selects the input that drives output OD0 of Drive N, where N = 0-7. 00 = Fixed - High 01 = Programmable pattern A 10 = Programmable pattern B 11 = FSENG Activity 620 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet EHCI Controller Registers (D29:F0, D26:F0) 17 EHCI Controller Registers (D29:F0, D26:F0) 17.1 USB EHCI Configuration Registers (USB EHCI--D29:F0, D26:F0) Note: Register address locations that are not shown in Table 17-1 should be treated as Reserved (see Table 9-3 for details). Note: Prior to BIOS initialization of the PCH USB subsystem, the EHCI controllers will appear as Function 7. After BIOS initialization, the EHCI controllers will be Function 0. Table 17-1. USB EHCI PCI Register Address Map (USB EHCI--D29:F0, D26:F0) (Sheet 1 of 2) Offset Mnemonic 00h-01h VID 02h-03h DID 04h-05h PCICMD PCI Command 06h-07h PCISTS PCI Status 08h RID 09h PI 0Ah SCC Register Name Default Value Attribute Vendor Identification 8086h RO Device Identification See register description RO 0000h R/W, RO 0290h R/WC, RO See register description RO Revision Identification Programming Interface 20h RO Sub Class Code 03h RO 0Bh BCC Base Class Code 0Ch RO 0Dh PMLT Primary Master Latency Timer 00h RO 0Eh HEADTYP 10h-13h MEM_BASE 2Ch-2Dh SVID 2Eh-2Fh SID Header Type 80h RO 00000000h R/W, RO USB EHCI Subsystem Vendor Identification XXXXh R/W USB EHCI Subsystem Identification XXXXh R/W Memory Base Address 34h CAP_PTR Capabilities Pointer 50h RO 3Ch INT_LN Interrupt Line 00h R/W 3Dh INT_PN Interrupt Pin See register description RO 50h PWR_CAPID 01h RO PCI Power Management Capability ID 51h NXT_PTR1 Next Item Pointer 58h R/W 52h-53h PWR_CAP Power Management Capabilities C9C2h R/W 54h-55h PWR_CNTL_STS Power Management Control/Status 0000h R/W, R/WC, RO 58h DEBUG_CAPID 0Ah RO Debug Port Capability ID 59h NXT_PTR2 5Ah-5Bh DEBUG_BASE Next Item Pointer #2 Debug Port Base Offset 60h USB_RELNUM USB Release Number 20h RO 61h FL_ADJ Frame Length Adjustment 20h R/W 62h-63h PWAKE_CAP 01FFh R/W Port Wake Capabilities Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 98h RO 20A0h RO 621 EHCI Controller Registers (D29:F0, D26:F0) Table 17-1. USB EHCI PCI Register Address Map (USB EHCI--D29:F0, D26:F0) (Sheet 2 of 2) Offset Mnemonic 64h-67h -- 68h-6Bh LEG_EXT_CAP 6Ch-6Fh Default Value Attribute -- -- USB EHCI Legacy Support Extended Capability 00000001h R/W, RO LEG_EXT_CS USB EHCI Legacy Extended Support Control/Status 00000000h R/W, R/WC, RO 70h-73h SPECIAL_SMI Intel Specific USB 2.0 Intel SMI 00000000h R/W, R/WC 74h-7Fh -- -- -- 80h ACCESS_CNTL 00h R/W 84-87h EHCIIR1 EHCI Initialization Register 1 83088E01h R/W 88-8Bh EHCIIR2 EHCI Initialization Register 2 04000010h R/W 98h FLR_CID FLR Capability ID 09h RO 99h FLR_NEXT 9Ah-9Bh FLR_CLV 9Ch FLR_CTRL 9Dh FLR_STAT Register Name Reserved Reserved Access Control FLR Next Capability Pointer 00h RO 2006h RO, R/WO FLR Control 00h R/W FLR Status 00h RO FLR Capability Length and Version F4-F7h EHCIIR3 EHCI Initialization Register 3 00408588h R/W FC-FFh EHCIIR4 EHCI Initialization Register 4 20591708h R/W Note: All configuration registers in this section are in the core well and reset by a core well reset and the D3-to-D0 warm reset, except as noted. 17.1.1 VID--Vendor Identification Register (USB EHCI--D29:F0, D26:F0) Offset Address: 00h-01h Default Value: 8086h Bit 15:0 17.1.2 RO 16 bits Description Vendor ID -- RO. This is a 16-bit value assigned to Intel. DID--Device Identification Register (USB EHCI--D29:F0, D26:F0) Offset Address: 02h-03h Default Value: See bit description Bit 15:0 622 Attribute: Size: Attribute: Size: RO 16 bits Description Device ID -- RO. This is a 16-bit value assigned to the PCH USB EHCI controller. Refer to the Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Specification Update for the value of the Device ID Register Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet EHCI Controller Registers (D29:F0, D26:F0) 17.1.3 PCICMD--PCI Command Register (USB EHCI--D29:F0, D26:F0) Address Offset: 04h-05h Default Value: 0000h Bit 15:11 10 Attribute: Size: R/W, RO 16 bits Description Reserved Interrupt Disable -- R/W. 0 = The function is capable of generating interrupts. 1 = The function can not generate its interrupt to the interrupt controller. Note that the corresponding Interrupt Status bit (D29:F0, D26:F0:06h, bit 3) is not affected by the interrupt enable. 9 Fast Back to Back Enable (FBE) -- RO. Hardwired to 0. 8 SERR# Enable (SERR_EN) -- R/W. 0 = Disables EHC's capability to generate an SERR#. 1 = The Enhanced Host controller (EHC) is capable of generating (internally) SERR# in the following cases: * When it receive a completion status other than "successful" for one of its DMA initiated memory reads on DMI (and subsequently on its internal interface). * When it detects an address or command parity error and the Parity Error Response bit is set. * When it detects a data parity error (when the data is going into the EHC) and the Parity Error Response bit is set. 7 Wait Cycle Control (WCC) -- RO. Hardwired to 0. 6 Parity Error Response (PER) -- R/W. 0 = The EHC is not checking for correct parity (on its internal interface). 1 = The EHC is checking for correct parity (on its internal interface) and halt operation when bad parity is detected during the data phase. Note: If the EHC detects bad parity on the address or command phases when the bit is set to 1, the host controller does not take the cycle. It halts the host controller (if currently not halted) and sets the Host System Error bit in the USBSTS register. This applies to both requests and completions from the system interface. This bit must be set in order for the parity errors to generate SERR#. 5 VGA Palette Snoop (VPS) -- RO. Hardwired to 0. 4 Postable Memory Write Enable (PMWE) -- RO. Hardwired to 0. 3 Special Cycle Enable (SCE) -- RO. Hardwired to 0. 2 Bus Master Enable (BME) -- R/W. 0 = Disables this functionality. 1 = Enables the PCH to act as a master on the PCI bus for USB transfers. 1 Memory Space Enable (MSE) -- R/W. This bit controls access to the USB 2.0 Memory Space registers. 0 = Disables this functionality. 1 = Enables accesses to the USB 2.0 registers. The Base Address register (D29:F0, D26:F0:10h) for USB 2.0 should be programmed before this bit is set. 0 I/O Space Enable (IOSE) -- RO. Hardwired to 0. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 623 EHCI Controller Registers (D29:F0, D26:F0) 17.1.4 PCISTS--PCI Status Register (USB EHCI--D29:F0, D26:F0) Address Offset: 06h-07h Default Value: 0290h Note: R/WC, RO 16 bits For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit Description 15 Detected Parity Error (DPE) -- R/WC. 0 = No parity error detected. 1 = This bit is set by the PCH when a parity error is seen by the EHCI controller, regardless of the setting of bit 6 or bit 8 in the Command register or any other conditions. 14 Signaled System Error (SSE) -- R/WC. 0 = No SERR# signaled by the PCH. 1 = This bit is set by the PCH when it signals SERR# (internally). The SER_EN bit (bit 8 of the Command Register) must be 1 for this bit to be set. 13 Received Master Abort (RMA) -- R/WC. 0 = No master abort received by EHC on a memory access. 1 = This bit is set when EHC, as a master, receives a master abort status on a memory access. This is treated as a Host Error and halts the DMA engines. This event can optionally generate an SERR# by setting the SERR# Enable bit. 12 Received Target Abort (RTA) -- R/WC. 0 = No target abort received by EHC on memory access. 1 = This bit is set when EHC, as a master, receives a target abort status on a memory access. This is treated as a Host Error and halts the DMA engines. This event can optionally generate an SERR# by setting the SERR# Enable bit (D29:F0, D26:F0:04h, bit 8). 11 Signaled Target Abort (STA) -- RO. This bit is used to indicate when the EHCI function responds to a cycle with a target abort. There is no reason for this to happen, so this bit is hardwired to 0. 10:9 8 DEVSEL# Timing Status (DEVT_STS) -- RO. This 2-bit field defines the timing for DEVSEL# assertion. Master Data Parity Error Detected (DPED) -- R/WC. 0 = No data parity error detected on USB2.0 read completion packet. 1 = This bit is set by the PCH when a data parity error is detected on a USB 2.0 read completion packet on the internal interface to the EHCI host controller and bit 6 of the Command register is set to 1. 7 Fast Back to Back Capable (FB2BC) -- RO. Hardwired to 1. 6 User Definable Features (UDF) -- RO. Hardwired to 0. 5 66 MHz Capable (66 MHz _CAP) -- RO. Hardwired to 0. 4 Capabilities List (CAP_LIST) -- RO. Hardwired to 1 indicating that offset 34h contains a valid capabilities pointer. 3 Interrupt Status -- RO. This bit reflects the state of this function's interrupt at the input of the enable/disable logic. 0 = This bit will be 0 when the interrupt is deasserted. 1 = This bit is a 1 when the interrupt is asserted. The value reported in this bit is independent of the value in the Interrupt Enable bit. 2:0 624 Attribute: Size: Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet EHCI Controller Registers (D29:F0, D26:F0) 17.1.5 RID--Revision Identification Register (USB EHCI--D29:F0, D26:F0) Offset Address: 08h Default Value: See bit description Bit 7:0 17.1.6 Attribute: Size: Description Revision ID -- RO. Refer to the Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Specification Update for the value of the Revision ID Register PI--Programming Interface Register (USB EHCI--D29:F0, D26:F0) Address Offset: 09h Default Value: 20h 17.1.7 RO 8 bits Description 7:0 Programming Interface -- RO. A value of 20h indicates that this USB 2.0 host controller conforms to the EHCI Specification. SCC--Sub Class Code Register (USB EHCI--D29:F0, D26:F0) Bit 7:0 Attribute: Size: RO 8 bits Description Sub Class Code (SCC) -- RO. 03h = Universal serial bus host controller. BCC--Base Class Code Register (USB EHCI--D29:F0, D26:F0) Address Offset: 0Bh Default Value: 0Ch Bit 7:0 17.1.9 Attribute: Size: Bit Address Offset: 0Ah Default Value: 03h 17.1.8 RO 8 bits Attribute: Size: RO 8 bits Description Base Class Code (BCC) -- RO. 0Ch = Serial bus controller. PMLT--Primary Master Latency Timer Register (USB EHCI--D29:F0, D26:F0) Address Offset: 0Dh Default Value: 00h Bit 7:0 Attribute: Size: RO 8 bits Description Master Latency Timer Count (MLTC) -- RO. Hardwired to 00h. Because the EHCI controller is internally implemented with arbitration on an interface (and not PCI), it does not need a master latency timer. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 625 EHCI Controller Registers (D29:F0, D26:F0) 17.1.10 HEADTYP--Header Type Register (USB EHCI--D29:F0, D26:F0) Address Offset: Default Value: 0Eh 80h Bit 7 6:0 17.1.11 Multi-Function Device -- RO. When set to `1' indicates this is a multifunction device: 0 = Single-function device 1 = Multi-function device. Configuration Layout. Hardwired to 00h, which indicates the standard PCI configuration layout. MEM_BASE--Memory Base Address Register (USB EHCI--D29:F0, D26:F0) Bit 31:10 9:4 3 Attribute: Size: R/W, RO 32 bits Description Base Address -- R/W. Bits [31:10] correspond to memory address signals [31:10], respectively. This gives 1-KB of locatable memory space aligned to 1-KB boundaries. Reserved Prefetchable -- RO. Hardwired to 0 indicating that this range should not be prefetched. 2:1 Type -- RO. Hardwired to 00b indicating that this range can be mapped anywhere within 32-bit address space. 0 Resource Type Indicator (RTE) -- RO. Hardwired to 0 indicating that the base address field in this register maps to memory space. SVID--USB EHCI Subsystem Vendor ID Register (USB EHCI--D29:F0, D26:F0) Address Offset: 2Ch-2Dh Default Value: XXXXh Reset: None 626 RO 8 bits Description Address Offset: 10h-13h Default Value: 00000000h 17.1.12 Attribute: Size: Attribute: Size: R/W 16 bits Bit Description 15:0 Subsystem Vendor ID (SVID) -- R/W. This register, in combination with the USB 2.0 Subsystem ID register, enables the operating system to distinguish each subsystem from the others. Note: Writes to this register are enabled when the WRT_RDONLY bit (D29:F0, D26:F0:80h, bit 0) is set to 1. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet EHCI Controller Registers (D29:F0, D26:F0) 17.1.13 SID--USB EHCI Subsystem ID Register (USB EHCI--D29:F0, D26:F0) Address Offset: 2Eh-2Fh Default Value: XXXXh Reset: None Bit 15:0 Subsystem ID (SID) -- R/W. BIOS sets the value in this register to identify the Subsystem ID. This register, in combination with the Subsystem Vendor ID register, enables the operating system to distinguish each subsystem from other(s). Writes to this register are enabled when the WRT_RDONLY bit (D29:F0, D26:F0:80h, bit 0) is set to 1. CAP_PTR--Capabilities Pointer Register (USB EHCI--D29:F0, D26:F0) Address Offset: 34h Default Value: 50h Bit 7:0 17.1.15 Attribute: Size: RO 8 bits Description Capabilities Pointer (CAP_PTR) -- RO. This register points to the starting offset of the USB 2.0 capabilities ranges. INT_LN--Interrupt Line Register (USB EHCI--D29:F0, D26:F0) Address Offset: 3Ch Default Value: 00h Function Level Reset: No Bit 7:0 17.1.16 R/W 16 bits Description Note: 17.1.14 Attribute: Size: Attribute: Size: R/W 8 bits Description Interrupt Line (INT_LN) -- R/W. This data is not used by the PCH. It is used as a scratchpad register to communicate to software the interrupt line that the interrupt pin is connected to. INT_PN--Interrupt Pin Register (USB EHCI--D29:F0, D26:F0) Address Offset: 3Dh Default Value: See Description Bit 7:0 Attribute: Size: RO 8 bits Description Interrupt Pin -- RO. This reflects the value of D29IP.E1IP (Chipset Config Registers:Offset 3108:bits 3:0) or D26IP.E2IP (Chipset Config Registers:Offset 3114:bits 3:0). Note: Bits 7:4 are always 0h Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 627 EHCI Controller Registers (D29:F0, D26:F0) 17.1.17 PWR_CAPID--PCI Power Management Capability ID Register (USB EHCI--D29:F0, D26:F0) Address Offset: 50h Default Value: 01h Bit 7:0 17.1.18 RO 8 bits Description Power Management Capability ID -- RO. A value of 01h indicates that this is a PCI Power Management capabilities field. NXT_PTR1--Next Item Pointer #1 Register (USB EHCI--D29:F0, D26:F0) Address Offset: 51h Default Value: 58h 17.1.19 Attribute: Size: Attribute: Size: R/W 8 bits Bit Description 7:0 Next Item Pointer 1 Value -- R/W (special). This register defaults to 58h, which indicates that the next capability registers begin at configuration offset 58h. This register is writable when the WRT_RDONLY bit (D29:F0, D26:F0:80h, bit 0) is set. This allows BIOS to effectively hide the Debug Port capability registers, if necessary. This register should only be written during system initialization before the plug-and-play software has enabled any master-initiated traffic. Only values of 58h (Debug Port and FLR capabilities visible) and 98h (Debug Port invisible, next capability is FLR) are expected to be programmed in this register. Note: Register not reset by D3-to-D0 warm reset. PWR_CAP--Power Management Capabilities Register (USB EHCI--D29:F0, D26:F0) Address Offset: 52h-53h Default Value: C9C2h Attribute: Size: R/W, RO 16 bits Bit Description 15:11 PME Support (PME_SUP) -- R/W. This 5-bit field indicates the power states in which the function may assert PME#. The PCH EHC does not support the D1 or D2 states. For all other states, the PCH EHC is capable of generating PME#. Software should never need to modify this field. 10 D2 Support (D2_SUP) -- RO. 0 = D2 State is not supported 9 D1 Support (D1_SUP) -- RO. 0 = D1 State is not supported 8:6 Auxiliary Current (AUX_CUR) -- R/W. The PCH EHC reports 375 mA maximum suspend well current required when in the D3COLD state. 5 Device Specific Initialization (DSI)-- RO. The PCH reports 0, indicating that no device-specific initialization is required. 4 Reserved 3 PME Clock (PME_CLK) -- RO. The PCH reports 0, indicating that no PCI clock is required to generate PME#. 2:0 Version (VER) -- RO. The PCH reports 010b, indicating that it complies with Revision 1.1 of the PCI Power Management Specification. Notes: 1. Normally, this register is read-only to report capabilities to the power management software. To report different power management capabilities, depending on the system in which the PCH is used, bits 15:11 and 8:6 in this register are writable when the WRT_RDONLY bit (D29:F0, D26:F0:80h, bit 0) is set. The value written to this register does not affect the hardware other than changing the value returned during a read. 2. Reset: core well, but not D3-to-D0 warm reset. 628 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet EHCI Controller Registers (D29:F0, D26:F0) 17.1.20 PWR_CNTL_STS--Power Management Control/ Status Register (USB EHCI--D29:F0, D26:F0) Address Offset: 54h-55h Attribute: Default Value: 0000h Size: Function Level Reset: No (Bits 8 and 15 only) Bit 15 R/W, R/WC, RO 16 bits Description PME Status -- R/WC. 0 = Writing a 1 to this bit will clear it and cause the internal PME to deassert (if enabled). 1 = This bit is set when the PCH EHC would normally assert the PME# signal independent of the state of the PME_En bit. Note: This bit must be explicitly cleared by the operating system each time the operating system is loaded. This bit is not reset by Function Level Reset. 14:13 12:9 8 Data Scale -- RO. Hardwired to 00b indicating it does not support the associated Data register. Data Select -- RO. Hardwired to 0000b indicating it does not support the associated Data register. PME Enable -- R/W. 0 = Disable. 1 = Enables the PCH EHC to generate an internal PME signal when PME_Status is 1. Note: This bit must be explicitly cleared by the operating system each time it is initially loaded. This bit is not reset by Function Level Reset. 7:2 Reserved 1:0 Power State -- R/W. This 2-bit field is used both to determine the current power state of EHC function and to set a new power state. The definition of the field values are: 00 = D0 state 11 = D3HOT state If software attempts to write a value of 10b or 01b in to this field, the write operation completes normally; however, the data is discarded and no state change occurs. When in the D3HOT state, the PCH does not accept accesses to the EHC memory range; but the configuration space is still be accessible. When not in the D0 state, the generation of the interrupt output is blocked. Specifically, the EHC interrupt is not asserted by the PCH when not in the D0 state. When software changes this value from the D3HOT state to the D0 state, an internal warm (soft) controller reset is generated, and software must re-initialize the function. Note: 17.1.21 Reset (bits 15, 8): suspend well, and not D3-to-D0 warm reset nor core well reset. DEBUG_CAPID--Debug Port Capability ID Register (USB EHCI--D29:F0, D26:F0) Address Offset: 58h Default Value: 0Ah Attribute: Size: RO 8 bits Bit Description 7:0 Debug Port Capability ID -- RO. Hardwired to 0Ah indicating that this is the start of a Debug Port Capability structure. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 629 EHCI Controller Registers (D29:F0, D26:F0) 17.1.22 NXT_PTR2--Next Item Pointer #2 Register (USB EHCI--D29:F0, D26:F0) Address Offset: 59h Default Value: 98h Function Level Reset: No Bit 7:0 17.1.23 Next Item Pointer 2 Capability -- RO. This register points to the next capability in the Function Level Reset capability structure. DEBUG_BASE--Debug Port Base Offset Register (USB EHCI--D29:F0, D26:F0) Bit Attribute: Size: RO 16 bits Description 15:13 BAR Number -- RO. Hardwired to 001b to indicate the memory BAR begins at offset 10h in the EHCI configuration space. 12:0 Debug Port Offset -- RO. Hardwired to 0A0h to indicate that the Debug Port registers begin at offset A0h in the EHCI memory range. USB_RELNUM--USB Release Number Register (USB EHCI--D29:F0, D26:F0) Address Offset: 60h Default Value: 20h Bit 7:0 17.1.25 RO 8 bits Description Address Offset: 5Ah-5Bh Default Value: 20A0h 17.1.24 Attribute: Size: Attribute: Size: RO 8 bits Description USB Release Number -- RO. A value of 20h indicates that this controller follows Universal Serial Bus (USB) Specification, Revision 2.0. FL_ADJ--Frame Length Adjustment Register (USB EHCI--D29:F0, D26:F0) Address Offset: 61h Default Value: 20h Function Level Reset: No Attribute: Size: R/W 8 bits This feature is used to adjust any offset from the clock source that generates the clock that drives the SOF counter. When a new value is written into these six bits, the length of the frame is adjusted. Its initial programmed value is system dependent based on the accuracy of hardware USB clock and is initialized by system BIOS. This register should only be modified when the HChalted bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 12) in the USB2.0_STS register is a 1. Changing value of this register while the host controller is operating yields undefined results. It should not be reprogrammed by USB system software unless the default or BIOS programmed values are incorrect, or the system is restoring the register while returning from a suspended state. These bits in suspend well and not reset by a D3-to-D0 warm rest or a core well reset. 630 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet EHCI Controller Registers (D29:F0, D26:F0) Bit 7:6 Description Reserved -- RO. These bits are reserved for future use and should read as 00b. Frame Length Timing Value -- R/W. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (20h), which gives a SOF cycle time of 60000. Frame Length (# 480 MHz Clocks) (decimal) Frame Length Timing Value (this register) (decimal) 59488 0 59504 1 59520 2 5:0 17.1.26 -- -- 59984 31 60000 32 -- -- 60480 62 PWAKE_CAP--Port Wake Capability Register (USB EHCI--D29:F0, D26:F0) Address Offset: 62-63h Default Value: 01FFh Default Value: 07FFh Function Level Reset: No Attribute: Size: R/W 16 bits This register is in the suspend power well. The intended use of this register is to establish a policy about which ports are to be used for wake events. Bit positions 1- 8(D29) or 1-6(D26) in the mask correspond to a physical port implemented on the current EHCI controller. A 1 in a bit position indicates that a device connected below the port can be enabled as a wake-up device and the port may be enabled for disconnect/ connect or overcurrent events as wake-up events. This is an information-only mask register. The bits in this register do not affect the actual operation of the EHCI host controller. The system-specific policy can be established by BIOS initializing this register to a system-specific value. System software uses the information in this register when enabling devices and ports for remote wake-up. These bits are not reset by a D3-to-D0 warm rest or a core well reset. Bit Description 15:9 (D29) 15:7 (D26) Reserved. 8:1 (D29) 6:1 (D26) Port Wake Up Capability Mask -- R/W. Bit positions 1 through 8 (Device 29) or 1 through 6(Device 26) correspond to a physical port implemented on this host controller. For example, bit position 1 corresponds to port 1, bit position 2 corresponds to port 2, etc. 0 Port Wake Implemented -- R/W. A 1 in this bit indicates that this register is implemented to software. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 631 EHCI Controller Registers (D29:F0, D26:F0) 17.1.27 LEG_EXT_CAP--USB EHCI Legacy Support Extended Capability Register (USB EHCI--D29:F0, D26:F0) Address Offset: 68-6Bh Default Value: 00000001h Power Well: Suspend Function Level Reset: No Note: 31:25 24 23:17 16 15:8 7:0 Description Reserved -- RO. Hardwired to 00h HC OS Owned Semaphore -- R/W. System software sets this bit to request ownership of the EHCI controller. Ownership is obtained when this bit reads as 1 and the HC BIOS Owned Semaphore bit reads as clear. Reserved -- RO. Hardwired to 00h HC BIOS Owned Semaphore -- R/W. The BIOS sets this bit to establish ownership of the EHCI controller. System BIOS will clear this bit in response to a request for ownership of the EHCI controller by system software. Next EHCI Capability Pointer -- RO. Hardwired to 00h to indicate that there are no EHCI Extended Capability structures in this device. Capability ID -- RO. Hardwired to 01h to indicate that this EHCI Extended Capability is the Legacy Support Capability. LEG_EXT_CS--USB EHCI Legacy Support Extended Control / Status Register (USB EHCI--D29:F0, D26:F0) Address Offset: 6C-6Fh Default Value: 00000000h Power Well: Suspend Function Level Reset: No Note: Attribute: Size: R/W, R/WC, RO 32 bits These bits are not reset by a D3-to-D0 warm rest or a core well reset. Bit Description 31 Intel SMI on BAR -- R/WC. Software clears this bit by writing a 1 to it. 0 = Base Address Register (BAR) not written. 1 = This bit is set to 1 when the Base Address Register (BAR) is written. 30 Intel SMI on PCI Command -- R/WC. Software clears this bit by writing a 1 to it. 0 = PCI Command (PCICMD) Register Not written. 1 = This bit is set to 1 when the PCI Command (PCICMD) Register is written. 29 Intel SMI on OS Ownership Change -- R/WC. Software clears this bit by writing a 1 to it. 0 = No HC OS Owned Semaphore bit change. 1 = This bit is set to 1 when the HC OS Owned Semaphore bit in the LEG_EXT_CAP register (D29:F0, D26:F0:68h, bit 24) transitions from 1 to 0 or 0 to 1. 28:22 21 20 632 R/W, RO 32 bits These bits are not reset by a D3-to-D0 warm rest or a core well reset. Bit 17.1.28 Attribute: Size: Reserved. Intel SMI on Async Advance -- RO. This bit is a shadow bit of the Interrupt on Async Advance bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 5) in the USB2.0_STS register. Note: To clear this bit system software must write a 1 to the Interrupt on Async Advance bit in the USB2.0_STS register. Intel SMI on Host System Error -- RO. This bit is a shadow bit of Host System Error bit in the USB2.0_STS register (D29:F0, D26:F0:CAPLENGTH + 24h, bit 4). Note: To clear this bit system software must write a 1 to the Host System Error bit in the USB2.0_STS register. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet EHCI Controller Registers (D29:F0, D26:F0) Bit 19 18 17 16 Description Intel SMI on Frame List Rollover -- RO. This bit is a shadow bit of Frame List Rollover bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 3) in the USB2.0_STS register. Note: To clear this bit system software must write a 1 to the Frame List Rollover bit in the USB2.0_STS register. Intel SMI on Port Change Detect -- RO. This bit is a shadow bit of Port Change Detect bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 2) in the USB2.0_STS register. Note: To clear this bit system software must write a 1 to the Port Change Detect bit in the USB2.0_STS register. Intel SMI on USB Error -- RO. This bit is a shadow bit of USB Error Interrupt (USBERRINT) bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 1) in the USB2.0_STS register. Note: To clear this bit system software must write a 1 to the USB Error Interrupt bit in the USB2.0_STS register. Intel SMI on USB Complete -- RO. This bit is a shadow bit of USB Interrupt (USBINT) bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 0) in the USB2.0_STS register. Note: To clear this bit system software must write a 1 to the USB Interrupt bit in the USB2.0_STS register. 15 Intel SMI on BAR Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is 1 and Intel SMI on BAR (D29:F0, D26:F0:6Ch, bit 31) is 1, then the host controller will issue an Intel SMI. 14 Intel SMI on PCI Command Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is 1 and Intel SMI on PCI Command (D29:F0, D26:F0:6Ch, bit 30) is 1, then the host controller will issue an Intel SMI. 13 Intel SMI on OS Ownership Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is a 1 AND the OS Ownership Change bit (D29:F0, D26:F0:6Ch, bit 29) is 1, the host controller will issue an Intel SMI. 12:6 Reserved. 5 Intel SMI on Async Advance Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is a 1, and the Intel SMI on Async Advance bit (D29:F0, D26:F0:6Ch, bit 21) is a 1, the host controller will issue an Intel SMI immediately. 4 Intel SMI on Host System Error Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is a 1, and the Intel SMI on Host System Error (D29:F0, D26:F0:6Ch, bit 20) is a 1, the host controller will issue an Intel SMI. 3 Intel SMI on Frame List Rollover Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is a 1, and the Intel SMI on Frame List Rollover bit (D29:F0, D26:F0:6Ch, bit 19) is a 1, the host controller will issue an Intel SMI. 2 Intel SMI on Port Change Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is a 1, and the Intel SMI on Port Change Detect bit (D29:F0, D26:F0:6Ch, bit 18) is a 1, the host controller will issue an Intel SMI. 1 Intel SMI on USB Error Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is a 1, and the Intel SMI on USB Error bit (D29:F0, D26:F0:6Ch, bit 17) is a 1, the host controller will issue an Intel SMI immediately. 0 Intel SMI on USB Complete Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is a 1, and the Intel SMI on USB Complete bit (D29:F0, D26:F0:6Ch, bit 16) is a 1, the host controller will issue an Intel SMI immediately. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 633 EHCI Controller Registers (D29:F0, D26:F0) 17.1.29 SPECIAL_SMI--Intel(R) Specific USB 2.0 Intel(R) SMI Register (USB EHCI--D29:F0, D26:F0) Address Offset: 70h-73h Default Value: 00000000h Power Well: Suspend Function Level Reset: No Note: R/W, R/WC 32 bits These bits are not reset by a D3-to-D0 warm rest or a core well reset. Bit Description 31:25 Reserved. 24:22 Intel SMI on PortOwner -- R/WC. Software clears these bits by writing a 1 to it. 0 = No Port Owner bit change. 1 = Bits 24:22 correspond to the Port Owner bits for ports 0 (22) through 3(24). These bits are set to 1 when the associated Port Owner bits transition from 0 to 1 or 1 to 0. 21 Intel SMI on PMCSR -- R/WC. Software clears these bits by writing a 1 to it. 0 = Power State bits Not modified. 1 = Software modified the Power State bits in the Power Management Control/Status (PMCSR) register (D29:F0, D26:F0:54h). 20 Intel SMI on Async -- R/WC. Software clears these bits by writing a 1 to it. 0 = No Async Schedule Enable bit change 1 = Async Schedule Enable bit transitioned from 1 to 0 or 0 to 1. 19 Intel SMI on Periodic -- R/WC. Software clears this bit by writing a 1 it. 0 = No Periodic Schedule Enable bit change. 1 = Periodic Schedule Enable bit transitions from 1 to 0 or 0 to 1. 18 Intel SMI on CF -- R/WC. Software clears this bit by writing a 1 it. 0 = No Configure Flag (CF) change. 1 = Configure Flag (CF) transitions from 1 to 0 or 0 to 1. 17 Intel SMI on HCHalted -- R/WC. Software clears this bit by writing a 1 it. 0 = HCHalted did Not transition to 1 (as a result of the Run/Stop bit being cleared). 1 = HCHalted transitions to 1 (as a result of the Run/Stop bit being cleared). 16 Intel SMI on HCReset -- R/WC. Software clears this bit by writing a 1 it. 0 = HCRESET did Not transitioned to 1. 1 = HCRESET transitioned to 1. 15:14 13:6 634 Attribute: Size: Reserved. Intel SMI on PortOwner Enable -- R/W. 0 = Disable. 1 = Enable. When any of these bits are 1 and the corresponding Intel SMI on PortOwner bits are 1, then the host controller will issue an SMI. Unused ports should have their corresponding bits cleared. 5 Intel SMI on PMSCR Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is 1 and Intel SMI on PMSCR is 1, then the host controller will issue an Intel SMI. 4 Intel SMI on Async Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is 1 and Intel SMI on Async is 1, then the host controller will issue an Intel SMI 3 Intel SMI on Periodic Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is 1 and Intel SMI on Periodic is 1, then the host controller will issue an Intel SMI. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet EHCI Controller Registers (D29:F0, D26:F0) Bit 17.1.30 Description 2 Intel SMI on CF Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is 1 and Intel SMI on CF is 1, then the host controller will issue an Intel SMI. 1 Intel SMI on HCHalted Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is a 1 and Intel SMI on HCHalted is 1, then the host controller will issue an Intel SMI. 0 Intel SMI on HCReset Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is a 1 and Intel SMI on HCReset is 1, then host controller will issue an Intel SMI. ACCESS_CNTL--Access Control Register (USB EHCI--D29:F0, D26:F0) Address Offset: 80h Default Value: 00h Function Level Reset: No Bit 7:1 0 17.1.31 Attribute: Size: R/W 8 bits Description Reserved WRT_RDONLY -- R/W. When set to 1, this bit enables a select group of normally read-only registers in the EHC function to be written by software. Registers that may only be written when this mode is entered are noted in the summary tables and detailed description as "Read/Write-Special". The registers fall into two categories: 1. System-configured parameters 2. Status bits EHCIIR1--EHCI Initialization Register 1 (USB EHCI--D29:F0, D26:F0) Address Offset: Default Value: 84h-87h 83088E01h Bit 31:29 28 27:19 18 17:11 10:9 8 Attribute: Size: R/W 32 bits Description Reserved EHCI Prefetch Entry Clear -- R/W. 0 = EHC will clear prefetched entries in DMA. 1 = EHC will not clear prefetched entries in DMA Reserved EHCI Initialization Register 1 Field 2-- R/W. BIOS may write to this bit field. Reserved EHCI Initialization Register 1 Field 1-- R/W. BIOS may write to this bit field. Asynchronous Schedule Caching Disable -- R/W. 0 = Caching of Asynchronous Schedule is enabled. (default) 1 = Caching of Asynchronous Schedule is disabled. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 635 EHCI Controller Registers (D29:F0, D26:F0) Bit 7:5 4 3:0 17.1.32 Description Reserved Intel(R) Pre-fetch Based Pause Enable -- R/W. 0 = Intel Pre-fetch Based Pause is disabled. 1 = Intel Pre-fetch Based Pause is enabled. Reserved EHCIIR2--EHCI Initialization Register 2 (USB EHCI-- D29:F0, D26:F0) Offset Address: 88h-8Bh Default Value: 04000010h Bit 31:30 29 28:20 19 18:12 Reserved EHCI Initialization Register 2 Field 6 -- R/W. BIOS may write to this bit field. Reserved EHCI Initialization Register 2 Field 5 -- R/W. BIOS may write to this bit field. Reserved EHCI Initialization Register 2 Field 4 -- R/W. BIOS may write to this bit field. 10 EHCI Initialization Register 2 Field 3 -- R/W. BIOS may write to this bit field. 9 Reserved 8 EHCI Initialization Register 2 Field 2 -- R/W. BIOS may write to this bit field. 5 4:0 Reserved EHCI Initialization Register 2 Field 1 -- R/W. BIOS may write to this bit field. Reserved FLR_CID--Function Level Reset Capability ID (USB EHCI--D29:F0, D26:F0) Address Offset: 98h Default Value: 09h Function Level Reset: No Bit 7:0 636 R/W 32-bit Description 11 7:6 17.1.33 Attribute: Size: Attribute: Size: RO 8 bits Description Capability ID -- R0. 13h = If FLRCSSEL = 0 09h (Vendor Specific Capability) = If FLRCSSEL = 1 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet EHCI Controller Registers (D29:F0, D26:F0) 17.1.34 FLR_NEXT--Function Level Reset Next Capability Pointer (USB EHCI--D29:F0, D26:F0) Address Offset: 99h Default Value: 00h Function Level Reset: No Bit 7:0 17.1.35 Attribute: Size: RO 8 bits Description A value of 00h in this register indicates this is the last capability field. FLR_CLV--Function Level Reset Capability Length and Version (USB EHCI--D29:F0, D26:F0) Address Offset: 9Ah-9Bh Default Value: 2006h Function Level Reset: No Attribute: Size: R/WO, RO 16 bits When FLRCSSEL = `0' this register is defined as follows: Bit 15:10 Description Reserved. 9 FLR Capability -- R/WO. 1 = Support for Function Level Reset (FLR). 8 TXP Capability -- R/WO. 1 = Support for Transactions Pending (TXP) bit. TXP must be supported if FLR is supported. 7:0 Capability Length -- RO. This field indicates the # of bytes of this vendor specific capability as required by the PCI specification. It has the value of 06h for the FLR capability. When FLRCSSEL = `1' this register is defined as follows: Bit 15:12 11:8 7:0 17.1.36 Description Vendor Specific Capability ID -- RO. A value of 2h in this field identifies this capability as Function Level Reset. Capability Version -- RO. This field indicates the version of the FLR capability. Capability Length -- RO. This field indicates the # of bytes of this vendor specific capability as required by the PCI specification. It has the value of 06h for the FLR capability. FLR_CTRL--Function Level Reset Control Register (USB EHCI--D29:F0, D26:F0) Address Offset: 9Ch Default Value: 00h Function Level Reset: No Bit 7:1 0 Attribute: Size: R/W 8 bits Description Reserved Initiate FLR -- R/W. This bit is used to initiate FLR transition. A write of `1' initiates FLR transition. Since hardware must not respond to any cycles until FLR completion, the value read by software from this bit is always `0'. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 637 EHCI Controller Registers (D29:F0, D26:F0) 17.1.37 FLR_STAT--Function Level Reset Status Register (USB EHCI--D29:F0, D26:F0) Address Offset: 9Dh Default Value: 00h Function Level Reset: No Bit 7:1 0 17.1.38 Reserved Transactions Pending (TXP) -- RO. 0 = Completions for all non-posted requests have been received. 1 = Controller has issued non-posted requests which have no bee completed. EHCIIR3--EHCI Initialization Register 3 (USB EHCI-- D29:F0, D26:F0) Bit 31 Attribute: Size: R/W 32-bit Description EHCIIR3 Write Enable -- R/W. 0 = Writes to the EHCIIR3 register are disabled 1 = If set, the values of the EHCIIR3 register may be modified 30:24 Reserved 23:22 EHCI Initialization Register 3 Field 1 -- R/W. BIOS may write to this bit field. 21:0 Reserved EHCIIR4--EHCI Initialization Register 4 (USB EHCI-- D29:F0, D26:F0) Offset Address: FCh-FFh Default Value: 20591708h Bit 31:18 Attribute: Size: R/W 32-bit Description Reserved 17 EHCI Initialization Register 4 Field 2 -- R/W. BIOS may write to this bit field. 16 Reserved 15 EHCI Initialization Register 4 Field 1 -- R/W. BIOS may write to this bit field. 14:0 638 RO 8 bits Description Offset Address: F4h-F7h Default Value: 00408588h 17.1.39 Attribute: Size: Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet EHCI Controller Registers (D29:F0, D26:F0) 17.2 Memory-Mapped I/O Registers The EHCI memory-mapped I/O space is composed of two sets of registers: Capability Registers and Operational Registers. Note: The PCH EHCI controller will not accept memory transactions (neither reads nor writes) as a target that are locked transactions. The locked transactions should not be forwarded to PCI as the address space is known to be allocated to USB. Note: When the EHCI function is in the D3 PCI power state, accesses to the USB 2.0 memory range are ignored and result a master abort. Similarly, if the Memory Space Enable (MSE) bit (D29:F0, D26:F0:04h, bit 1) is not set in the Command register in configuration space, the memory range will not be decoded by the PCH enhanced host controller (EHC). If the MSE bit is not set, the PCH must default to allowing any memory accesses for the range specified in the BAR to go to PCI. This is because the range may not be valid and, therefore, the cycle must be made available to any other targets that may be currently using that range. 17.2.1 Host Controller Capability Registers These registers specify the limits, restrictions and capabilities of the host controller implementation. Within the host controller capability registers, only the structural parameters register is writable. These registers are implemented in the suspend well and is only reset by the standard suspend-well hardware reset, not by HCRESET or the D3-to-D0 reset. Note: Note that the EHCI controller does not support as a target memory transactions that are locked transactions. Attempting to access the EHCI controller Memory-Mapped I/O space using locked memory transactions will result in undefined behavior. Note: Note that when the USB2 function is in the D3 PCI power state, accesses to the USB2 memory range are ignored and will result in a master abort Similarly, if the Memory Space Enable (MSE) bit is not set in the Command register in configuration space, the memory range will not be decoded by the Enhanced Host Controller (EHC). If the MSE bit is not set, the EHC will not claim any memory accesses for the range specified in the BAR. Table 17-2. Enhanced Host Controller Capability Registers MEM_BASE + Offset Mnemonic Register 00h CAPLENGTH Capabilities Registers Length 02h-03h HCIVERSION Host Controller Interface Version Number 04h-07h HCSPARAMS 08h-0Bh HCCPARAMS Note: Default Type 20h RO 0100h RO Host Controller Structural Parameters 00204208h (D29:F0) 00203206 (D26:F0) R/W (special), RO Host Controller Capability Parameters 00006881h RO "Read/Write Special" means that the register is normally read-only, but may be written when the WRT_RDONLY bit is set. Because these registers are expected to be programmed by BIOS during initialization, their contents must not get modified by HCRESET or D3-to-D0 internal reset. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 639 EHCI Controller Registers (D29:F0, D26:F0) 17.2.1.1 CAPLENGTH--Capability Registers Length Register Offset: Default Value: 17.2.1.2 MEM_BASE + 00h 20h Description 7:0 Capability Register Length Value -- RO. This register is used as an offset to add to the Memory Base Register (D29:F0, D26:F0:10h) to find the beginning of the Operational Register Space. This field is hardwired to 20h indicating that the Operation Registers begin at offset 20h. HCIVERSION--Host Controller Interface Version Number Register MEM_BASE + 02h-03h 0100h Bit 15:0 RO 16 bits Host Controller Interface Version Number -- RO. This is a two-byte register containing a BCD encoding of the version number of interface that this host controller interface conforms. HCSPARAMS--Host Controller Structural Parameters MEM_BASE + 04h-07h 00204208h (D29:F0) 00203206h (D26:F0) Function Level Reset: No Attribute: Size: R/W, RO 32 bits This register is reset by a suspend well reset and not a D3-to-D0 reset or HCRESET. Bit Description 31:24 Reserved. 23:20 Debug Port Number (DP_N) -- RO. Hardwired to 2h indicating that the Debug Port is on the second lowest numbered port on the EHCI. EHCI#1: Port 1 EHCI#2: Port 9 19:16 Reserved 15:12 Number of Companion Controllers (N_CC) -- R/W. This field indicates the number of companion controllers associated with this USB EHCI host controller. BIOS must program this field to 0b to indicate companion host controllers are not supported. Portownership hand-off is not supported. Only high-speed devices are supported on the host controller root ports. 11:8 Number of Ports per Companion Controller (N_PCC) -- RO. This field indicates the number of ports supported per companion host controller. This field is 0h indication no other companion controller support. 7:4 Reserved. These bits are reserved and default to 0. 3:0 N_PORTS -- R/W. This field specifies the number of physical downstream ports implemented on this host controller. The value of this field determines how many port registers are addressable in the Operational Register Space. Valid values are in the range of 1h to Fh. A 0 in this field is undefined. For Integrated USB 2.0 Rate Matching Hub Enabled: Each EHCI reports 2 ports by default. Port 0 assigned to the RMH and port 1 assigned as the debug port. When the KVM/USB-R feature is enabled it will show up as Port2 on the EHCI, and BIOS would need to update this field to 3h. Note: 640 Attribute: Size: Description Offset: Default Value: Note: RO 8 bits Bit Offset: Default Value: 17.2.1.3 Attribute: Size: This register is writable when the WRT_RDONLY bit is set. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet EHCI Controller Registers (D29:F0, D26:F0) 17.2.1.4 HCCPARAMS--Host Controller Capability Parameters Register Offset: Default Value: MEM_BASE + 08h-0Bh 00006881h Bit 31:18 Attribute: Size: RO 32 bits Description Reserved 17 Asynchronous Schedule Update Capability (ASUC) -- R/W. There is no functionality associated with this bit. 16 Periodic Schedule Update Capability (PSUC) -- RO. This field is hardwired to 0b to indicate that the EHC hardware supports the Periodic Schedule Update Event Flag in the USB2.0_CMD register. 15:8 EHCI Extended Capabilities Pointer (EECP) -- RO. This field is hardwired to 68h, indicating that the EHCI capabilities list exists and begins at offset 68h in the PCI configuration space. 7:4 Isochronous Scheduling Threshold -- RO. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. When bit 7 is 0, the value of the least significant 3 bits indicates the number of micro-frames a host controller hold a set of isochronous data structures (one or more) before flushing the state. When bit 7 is a 1, then host software assumes the host controller may cache an isochronous data structure for an entire frame. Refer to the EHCI specification for details on how software uses this information for scheduling isochronous transfers. This field is hardwired to 8h. 3 Reserved. 2 Asynchronous Schedule Park Capability -- RO. This bit is hardwired to 0 indicating that the host controller does not support this optional feature 1 Programmable Frame List Flag -- RO. 0 = System software must use a frame list length of 1024 elements with this host controller. The USB2.0_CMD register (D29:F0, D26:F0:CAPLENGTH + 20h, bits 3:2) Frame List Size field is a read-only register and must be set to 0. 1 = System software can specify and use a smaller frame list and configure the host controller using the USB2.0_CMD register Frame List Size field. The frame list must always be aligned on a 4K page boundary. This requirement ensures that the frame list is always physically contiguous. 0 64-bit Addressing Capability -- RO. This field documents the addressing range capability of this implementation. The value of this field determines whether software should use the 32-bit or 64-bit data structures. This bit is hardwired to 1. Note: The PCH supports 64 bit addressing only. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 641 EHCI Controller Registers (D29:F0, D26:F0) 17.2.2 Host Controller Operational Registers This section defines the enhanced host controller operational registers. These registers are located after the capabilities registers. The operational register base must be DWord-aligned and is calculated by adding the value in the first capabilities register (CAPLENGTH) to the base address of the enhanced host controller register address space (MEM_BASE). Since CAPLENGTH is always 20h, Table 17-3 already accounts for this offset. All registers are 32 bits in length. Table 17-3. Enhanced Host Controller Operational Register Address Map Note: MEM_BASE + Offset Mnemonic 20h-23h USB2.0_CMD USB 2.0 Command 00080000h R/W, RO 24h-27h USB2.0_STS USB 2.0 Status 00001000h R/WC, RO 28h-2Bh USB2.0_INTR USB 2.0 Interrupt Enable 00000000h R/W 2Ch-2Fh FRINDEX USB 2.0 Frame Index 00000000h R/W, 00000000h R/W, RO Register Name Default Special Notes Attribute 30h-33h CTRLDSSEGMENT Control Data Structure Segment 34h-37h PERODICLISTBASE Period Frame List Base Address 00000000h R/W 38h-3Bh ASYNCLISTADDR Current Asynchronous List Address 00000000h R/W 3Ch-5Fh -- 60h-63h CONFIGFLAG 64h-67h Reserved 0h RO Configure Flag 00000000h Suspend R/W PORT0SC Port 0 Status and Control 00003000h Suspend R/W, R/WC, RO 68h-6Bh PORT1SC Port 1 Status and Control 00003000h Suspend R/W, R/WC, RO 6Ch-6Fh PORT2SC Port 2 Status and Control 00003000h Suspend R/W, R/WC, RO 70h-73h PORT3SC Port 3 Status and Control 00003000h Suspend R/W, R/WC, RO 74h-77h PORT4SC Port 4 Status and Control 00003000h Suspend R/W, R/WC, RO 78h-7Bh PORT5SC Port 5 Status and Control 00003000h Suspend R/W, R/WC, RO 74h-77h (D29 Only) PORT6SC Port 6 Status and Control 00003000h Suspend R/W, R/WC, RO 78h-7Bh (D29 Only) PORT7SC Port 7 Status and Control 00003000h Suspend R/W, R/WC, RO 7Ch-9Fh -- Reserved Undefined RO A0h-B3h -- Debug Port Registers Undefined See register description B4h-3FFh -- Reserved Undefined RO Software must read and write these registers using only DWord accesses.These registers are divided into two sets. The first set at offsets MEM_BASE + 00:3Bh are implemented in the core power well. Unless otherwise noted, the core well registers are reset by the assertion of any of the following: * Core well hardware reset * HCRESET * D3-to-D0 reset The second set at offsets MEM_BASE + 60h to the end of the implemented register space are implemented in the Suspend power well. Unless otherwise noted, the suspend well registers are reset by the assertion of either of the following: * Suspend well hardware reset * HCRESET 642 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet EHCI Controller Registers (D29:F0, D26:F0) 17.2.2.1 USB2.0_CMD--USB 2.0 Command Register Offset: Default Value: MEM_BASE + 20-23h 00080000h Bit 31:24 Attribute: Size: R/W, RO 32 bits Description Reserved Interrupt Threshold Control -- R/W. System software uses this field to select the maximum rate at which the host controller will issue interrupts. The only valid values are defined below. If software writes an invalid value to this register, the results are undefined. Value 23:16 15:14 Maximum Interrupt Interval 00h Reserved 01h 1 micro-frame 02h 2 micro-frames 04h 4 micro-frames 08h 8 micro-frames (default, equates to 1 ms) 10h 16 micro-frames (2 ms) 20h 32 micro-frames (4 ms) 40h 64 micro-frames (8 ms) Reserved 13 Asynch Schedule Update (ASC) -- R/W. There is no functionality associated with this bit. 12 Periodic Schedule Prefetch Enable -- R/W. This bit is used by software to enable the host controller to prefetch the periodic schedule even in C0. 0 = Prefetch based pause enabled only when not in C0. 1 = Prefetch based pause enable in C0. Once software has written a 1b to this bit to enable periodic schedule prefetching, it must disable prefecthing by writing a 0b to this bit whenever periodic schedule updates are about to begin. Software should continue to dynamically disable and re-enable the prefetcher surrounding any updates to the periodic scheduler (that is until the host controller has been reset using a HCRESET). 11:8 7 6 Unimplemented Asynchronous Park Mode Bits -- RO. Hardwired to 000b indicating the host controller does not support this optional feature. Light Host Controller Reset -- RO. Hardwired to 0. The PCH does not implement this optional reset. Interrupt on Async Advance Doorbell -- R/W. This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. 0 = The host controller sets this bit to a 0 after it has set the Interrupt on Async Advance status bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 5) in the USB2.0_STS register to a 1. 1 = Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Async Advance status bit in the USB2.0_STS register. If the Interrupt on Async Advance Enable bit in the USB2.0_INTR register (D29:F0, D26:F0:CAPLENGTH + 28h, bit 5) is a 1 then the host controller will assert an interrupt at the next interrupt threshold. See the EHCI specification for operational details. Note: Software should not write a 1 to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. 5 Asynchronous Schedule Enable -- R/W. This bit controls whether the host controller skips processing the Asynchronous Schedule. 0 = Do not process the Asynchronous Schedule 1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule. 4 Periodic Schedule Enable -- R/W. This bit controls whether the host controller skips processing the Periodic Schedule. 0 = Do not process the Periodic Schedule 1 = Use the PERIODICLISTBASE register to access the Periodic Schedule. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 643 EHCI Controller Registers (D29:F0, D26:F0) Bit 3:2 Description Frame List Size -- RO. The PCH hardwires this field to 00b because it only supports the 1024element frame list size. Host Controller Reset (HCRESET) -- R/W. This control bit used by software to reset the host controller. The effects of this on root hub registers are similar to a Chip Hardware Reset (that is, RSMRST# assertion and PCH_PWROK deassertion on the PCH). When software writes a 1 to this bit, the host controller resets its internal pipelines, timers, counters, state machines, etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Note: 1 0 PCI configuration registers and Host controller capability registers are not effected by this reset. All operational registers, including port registers and port state machines are set to their initial values. Port ownership reverts to the companion host controller(s), with the side effects described in the EHCI spec. Software must re-initialize the host controller in order to return the host controller to an operational state. This bit is set to 0 by the host controller when the reset process is complete. Software cannot terminate the reset process early by writing a 0 to this register. Software should not set this bit to a 1 when the HCHalted bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 12) in the USB2.0_STS register is a 0. Attempting to reset an actively running host controller will result in undefined behavior. This reset me be used to leave EHCI port test modes. Run/Stop (RS) -- R/W. 0 = Stop (default) 1 = Run. When set to a 1, the Host controller proceeds with execution of the schedule. The Host controller continues execution as long as this bit is set. When this bit is set to 0, the Host controller completes the current transaction on the USB and then halts. The HCHalted bit in the USB2.0_STS register indicates when the Host controller has finished the transaction and has entered the stopped state. Software should not write a 1 to this field unless the host controller is in the Halted state (that is, HCHalted in the USBSTS register is a 1). The Halted bit is cleared immediately when the Run bit is set. The following table explains how the different combinations of Run and Halted should be interpreted: Run/Stop Halted Interpretation 0b 0b In the process of halting 0b 1b Halted 1b 0b Running 1b 1b Invalid - the HCHalted bit clears immediately Memory read cycles initiated by the EHC that receive any status other than Successful will result in this bit being cleared. Note: 644 The Command Register indicates the command to be executed by the serial bus host controller. Writing to the register causes a command to be executed. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet EHCI Controller Registers (D29:F0, D26:F0) 17.2.2.2 USB2.0_STS--USB 2.0 Status Register Offset: Default Value: MEM_BASE + 24h-27h 00001000h Attribute: Size: R/WC, RO 32 bits This register indicates pending interrupts and various states of the Host controller. The status resulting from a transaction on the serial bus is not indicated in this register. See the Interrupts description in section 4 of the EHCI specification for additional information concerning USB 2.0 interrupt conditions. Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 has no effect. Bit 31:16 Description Reserved. Asynchronous Schedule Status RO. This bit reports the current real status of the Asynchronous Schedule. 0 = Disabled. (Default) 1 = Enabled. 15 Note: The Host controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit (D29:F0, D26:F0:CAPLENGTH + 20h, bit 5) in the USB2.0_CMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). Periodic Schedule Status RO. This bit reports the current real status of the Periodic Schedule. 0 = Disabled. (Default) 1 = Enabled. 14 Note: The Host controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit (D29:F0, D26:F0:CAPLENGTH + 20h, bit 4) in the USB2.0_CMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). 13 Reclamation RO. This read-only status bit is used to detect an empty asynchronous schedule. The operational model and valid transitions for this bit are described in Section 4 of the EHCI Specification. 12 HCHalted RO. 0 = This bit is a 0 when the Run/Stop bit is a 1. 1 = The Host controller sets this bit to 1 after it has stopped executing as a result of the Run/Stop bit being set to 0, either by software or by the Host controller hardware (such as, internal error). (Default) 11:6 5 4 Reserved Interrupt on Async Advance -- R/WC. System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a 1 to the Interrupt on Async Advance Doorbell bit (D29:F0, D26:F0:CAPLENGTH + 20h, bit 6) in the USB2.0_CMD register. This bit indicates the assertion of that interrupt source. Host System Error -- R/WC. 0 = No serious error occurred during a host system access involving the Host controller module 1 = The Host controller sets this bit to 1 when a serious error occurs during a host system access involving the Host controller module. A hardware interrupt is generated to the system. Memory read cycles initiated by the EHC that receive any status other than Successful will result in this bit being set. When this error occurs, the Host controller clears the Run/Stop bit in the USB2.0_CMDregister (D29:F0, D26:F0:CAPLENGTH + 20h, bit 0) to prevent further execution of the scheduled TDs. A hardware interrupt is generated to the system (if enabled in the Interrupt Enable Register). 3 Frame List Rollover -- R/WC. 0 = No Frame List Index rollover from its maximum value to 0. 1 = The Host controller sets this bit to a 1 when the Frame List Index rolls over from its maximum value to 0. Since the PCH only supports the 1024-entry Frame List Size, the Frame List Index rolls over every time FRNUM13 toggles. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 645 EHCI Controller Registers (D29:F0, D26:F0) 17.2.2.3 Bit Description 2 Port Change Detect -- R/WC. This bit is allowed to be maintained in the Auxiliary power well. Alternatively, it is also acceptable that on a D3 to D0 transition of the EHCI HC device, this bit is loaded with the OR of all of the PORTSC change bits (including: Force port resume, overcurrent change, enable/disable change and connect status change). Regardless of the implementation, when this bit is readable (that is, in the D0 state), it must provide a valid view of the Port Status registers. 0 = No change bit transition from a 0 to 1 or No Force Port Resume bit transition from 0 to 1 as a result of a J-K transition detected on a suspended port. 1 = The Host controller sets this bit to 1 when any port for which the Port Owner bit is set to 0 has a change bit transition from a 0 to 1 or a Force Port Resume bit transition from 0 to 1 as a result of a J-K transition detected on a suspended port. 1 USB Error Interrupt (USBERRINT) -- R/WC. 0 = No error condition. 1 = The Host controller sets this bit to 1 when completion of a USB transaction results in an error condition (such as DWord, error counter underflow). If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and Bit 0 are set. See the EHCI specification for a list of the USB errors that will result in this interrupt being asserted. 0 USB Interrupt (USBINT) -- R/WC. 0 = No completion of a USB transaction whose Transfer Descriptor had its IOC bit set. No short packet is detected. 1 = The Host controller sets this bit to 1 when the cause of an interrupt is a completion of a USB transaction whose Transfer Descriptor had its IOC bit set. The Host controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes). USB2.0_INTR--USB 2.0 Interrupt Enable Register Offset: Default Value: MEM_BASE + 28h-2Bh 00000000h Attribute: Size: R/W 32 bits This register enables and disables reporting of the corresponding interrupt to the software. When a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. Interrupt sources that are disabled in this register still appear in the USB2.0_STS Register to allow the software to poll for events. Each interrupt enable bit description indicates whether it is dependent on the interrupt threshold mechanism (see Section 4 of the EHCI specification), or not. Bit 31:6 646 Description Reserved. 5 Interrupt on Async Advance Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is a 1, and the Interrupt on Async Advance bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 5) in the USB2.0_STS register is a 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit. 4 Host System Error Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is a 1, and the Host System Error Status bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 4) in the USB2.0_STS register is a 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Host System Error bit. 3 Frame List Rollover Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is a 1, and the Frame List Rollover bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 3) in the USB2.0_STS register is a 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet EHCI Controller Registers (D29:F0, D26:F0) Bit 17.2.2.4 Description 2 Port Change Interrupt Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is a 1, and the Port Change Detect bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 2) in the USB2.0_STS register is a 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit. 1 USB Error Interrupt Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is a 1, and the USBERRINT bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 1) in the USB2.0_STS register is a 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software by clearing the USBERRINT bit in the USB2.0_STS register. 0 USB Interrupt Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is a 1, and the USBINT bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 0) in the USB2.0_STS register is a 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software by clearing the USBINT bit in the USB2.0_STS register. FRINDEX--Frame Index Register Offset: Default Value: MEM_BASE + 2Ch-2Fh 00000000h Attribute: Size: R/W 32 bits The SOF frame number value for the bus SOF token is derived or alternatively managed from this register. Refer to Section 4 of the EHCI specification for a detailed explanation of the SOF value management requirements on the host controller. The value of FRINDEX must be within 125 s (1 micro-frame) ahead of the SOF token value. The SOF value may be implemented as an 11-bit shadow register. For this discussion, this shadow register is 11 bits and is named SOFV. SOFV updates every 8 micro-frames (1 millisecond). An example implementation to achieve this behavior is to increment SOFV each time the FRINDEX[2:0] increments from 0 to 1. Software must use the value of FRINDEX to derive the current micro-frame number, both for high-speed isochronous scheduling purposes and to provide the get microframe number function required to client drivers. Therefore, the value of FRINDEX and the value of SOFV must be kept consistent if chip is reset or software writes to FRINDEX. Writes to FRINDEX must also write-through FRINDEX[13:3] to SOFV[10:0]. In order to keep the update as simple as possible, software should never write a FRINDEX value where the three least significant bits are 111b or 000b. Note: This register is used by the host controller to index into the periodic frame list. The register updates every 125 microseconds (once each micro-frame). Bits [12:3] are used to select a particular entry in the Periodic Frame List during periodic schedule execution. The number of bits used for the index is fixed at 10 for the PCH since it only supports 1024-entry frame lists. This register must be written as a DWord. Word and byte writes produce undefined results. This register cannot be written unless the Host controller is in the Halted state as indicated by the HCHalted bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 12). A write to this register while the Run/Stop bit (D29:F0, D26:F0:CAPLENGTH + 20h, bit 0) is set to a 1 (USB2.0_CMD register) produces undefined results. Writes to this register also effect the SOF value. See Section 4 of the EHCI specification for details. Bit 31:14 13:0 Description Reserved Frame List Current Index/Frame Number -- R/W. The value in this register increments at the end of each time frame (such as, micro-frame). Bits [12:3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 647 EHCI Controller Registers (D29:F0, D26:F0) 17.2.2.5 CTRLDSSEGMENT--Control Data Structure Segment Register Offset: Default Value: MEM_BASE + 30h-33h 00000000h Attribute: Size: R/W, RO 32 bits This 32-bit register corresponds to the most significant address bits [63:32] for all EHCI data structures. Since the PCH hardwires the 64-bit Addressing Capability field in HCCPARAMS to 1, this register is used with the link pointers to construct 64-bit addresses to EHCI control data structures. This register is concatenated with the link pointer from either the PERIODICLISTBASE, ASYNCLISTADDR, or any control data structure link field to construct a 64-bit address. This register allows the host software to locate all control data structures within the same 4 GB memory segment. Bit 31:12 11:0 17.2.2.6 Description Upper Address[63:44] -- RO. Hardwired to 0s. The PCH EHC is only capable of generating addresses up to 16 terabytes (44 bits of address). Upper Address[43:32] -- R/W. This 12-bit field corresponds to address bits 43:32 when forming a control data structure address. PERIODICLISTBASE--Periodic Frame List Base Address Register Offset: Default Value: MEM_BASE + 34h-37h 00000000h Attribute: Size: R/W 32 bits This 32-bit register contains the beginning address of the Periodic Frame List in the system memory. Since the PCH host controller operates in 64-bit mode (as indicated by the 1 in the 64-bit Addressing Capability field in the HCCSPARAMS register) (offset 08h, bit 0), then the most significant 32 bits of every control data structure address comes from the CTRLDSSEGMENT register. HCD loads this register prior to starting the schedule execution by the host controller. The memory structure referenced by this physical memory pointer is assumed to be 4-Kbyte aligned. The contents of this register are combined with the Frame Index Register (FRINDEX) to enable the Host controller to step through the Periodic Frame List in sequence. Bit 31:12 11:0 648 Description Base Address (Low) -- R/W. These bits correspond to memory address signals [31:12], respectively. Reserved. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet EHCI Controller Registers (D29:F0, D26:F0) 17.2.2.7 ASYNCLISTADDR--Current Asynchronous List Address Register Offset: Default Value: MEM_BASE + 38h-3Bh 00000000h Attribute: Size: R/W 32 bits This 32-bit register contains the address of the next asynchronous queue head to be executed. Since the PCH host controller operates in 64-bit mode (as indicated by a 1 in 64-bit Addressing Capability field in the HCCPARAMS register) (offset 08h, bit 0), then the most significant 32 bits of every control data structure address comes from the CTRLDSSEGMENT register (offset 08h). Bits [4:0] of this register cannot be modified by system software and will always return 0s when read. The memory structure referenced by this physical memory pointer is assumed to be 32-byte aligned. Bit 31:5 4:0 17.2.2.8 Description Link Pointer Low (LPL) -- R/W. These bits correspond to memory address signals [31:5], respectively. This field may only reference a Queue Head (QH). Reserved. CONFIGFLAG--Configure Flag Register Offset: Default Value: MEM_BASE + 60h-63h 00000000h Attribute: Size: R/W 32 bits This register is in the suspend power well. It is only reset by hardware when the suspend power is initially applied or in response to a host controller reset. Bit 31:1 0 17.2.2.9 Note: Description Reserved. Configure Flag (CF) -- R/W. Host software sets this bit as the last action in its process of configuring the Host controller. This bit controls the default port-routing control logic. Bit values and side-effects are listed below. See section 4 of the EHCI spec for operation details. 0 = Compatibility debug only (default). 1 = Port routing control logic default-routes all ports to this host controller. PORTSC--Port N Status and Control Register Offset: Port 0 RMH: MEM_BASE + 64h-67h Port 1 Debug Port: MEM_BASE + 68-6Bh Port 2 USB redirect (if enabled): MEM_BASE + 6C-6Fh Attribute: Default Value: R/W, R/WC, RO 00003000h Size: 32 bits This register is associated with the upstream ports of the EHCI controller and does not represent downstream hub ports. USB Hub class commands must be used to determine RMH port status and enable test modes. See Chapter 11 of the USB Specification, Revision 2.0 for more details. Rate Matching Hub wake capabilities can be configured by the RMHWKCTL Register (RCBA+35B0h) located in the Chipset Configuration chapter. A host controller must implement one or more port registers. Software uses the N_Port information from the Structural Parameters Register to determine how many ports need to be serviced. All ports have the structure defined below. Software must not write to unreported Port Status and Control Registers. This register is in the suspend power well. It is only reset by hardware when the suspend power is initially applied or in response to a host controller reset. The initial conditions of a port are: * No device connected * Port disabled. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 649 EHCI Controller Registers (D29:F0, D26:F0) When a device is attached, the port state transitions to the attached state and system software will process this as with any status change notification. Refer to Section 4 of the EHCI specification for operational requirements for how change events interact with port suspend mode. Bit 31:23 Description Reserved. 22 Wake on Overcurrent Enable (WKOC_E) -- R/W. 0 = Disable. (Default) 1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power Management Control/Status Register (offset 54, bit 15) when the overcurrent Active bit (bit 4 of this register) is set. 21 Wake on Disconnect Enable (WKDSCNNT_E) -- R/W. 0 = Disable. (Default) 1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power Management Control/Status Register (offset 54, bit 15) when the Current Connect Status changes from connected to disconnected (that is, bit 0 of this register changes from 1 to 0). 20 Wake on Connect Enable (WKCNNT_E) -- R/W. 0 = Disable. (Default) 1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power Management Control/Status Register (offset 54, bit 15) when the Current Connect Status changes from disconnected to connected (that is, bit 0 of this register changes from 0 to 1). Port Test Control -- R/W. When this field is 0s, the port is NOT operating in a test mode. A nonzero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value. The encoding of the test mode bits are (0110b - 1111b are reserved): 19:16 Value Maximum Interrupt Interval 0000b Test mode not enabled (default) 0001b Test J_STATE 0010b Test K_STATE 0011b Test SE0_NAK 0100b Test Packet 0101b FORCE_ENABLE Refer to the USB Specification Revision 2.0, Chapter 7 for details on each test mode. 15:14 13 Port Owner -- R/W. This bit unconditionally goes to a 0 when the Configured Flag bit in the USB2.0_CMD register makes a 0 to 1 transition. System software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device). Software writes a 1 to this bit when the attached device is not a high-speed device. A 1 in this bit means that a companion host controller owns and controls the port. See Section 4 of the EHCI Specification for operational details. 12 Port Power (PP) -- RO. Read-only with a value of 1. This indicates that the port does have power. 11:10 Line Status-- RO.These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines. These bits are used for detection of low-speed USB devices prior to the port reset and enable sequence. This field is valid only when the port enable bit is 0 and the current connect status bit is set to a 1. 00 = SE0 10 = J-state 01 = K-state 11 = Undefined 9 650 Reserved. Reserved. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet EHCI Controller Registers (D29:F0, D26:F0) Bit Description Port Reset -- R/W. When software writes a 1 to this bit (from a 0), the bus reset sequence as defined in the USB Specification, Revision 2.0 is started. Software writes a 0 to this bit to terminate the bus reset sequence. Software must keep this bit at a 1 long enough to ensure the reset sequence completes as specified in the USB Specification, Revision 2.0. 1 = Port is in Reset. 0 = Port is not in Reset. Note: 8 When software writes a 0 to this bit, there may be a delay before the bit status changes to a 0. The bit status will not read as a 0 until after the reset has completed. If the port is in high-speed mode after reset is complete, the host controller will automatically enable this port (such as, set the Port Enable bit to a 1). A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from 0 to 1. For example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state within 2 ms of software writing this bit to a 0. The HCHalted bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 12) in the USB2.0_STS register should be a 0 before software attempts to use this bit. The host controller may hold Port Reset asserted to a 1 when the HCHalted bit is a 1. This bit is 0 if Port Power is 0 Note: System software should not attempt to reset a port if the HCHalted bit in the USB2.0_STS register is a 1. Doing so will result in undefined behavior. Suspend -- R/W. 0 = Port not in suspend state.(Default) 1 = Port in suspend state. Port Enabled Bit and Suspend bit of this register define the port states as follows: Port Enabled Suspend Port State 0 X Disabled 1 0 Enabled 1 1 Suspend 7 When in suspend state, downstream propagation of data is blocked on this port, except for port reset. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port depending on the activity on the port. The host controller will unconditionally set this bit to a 0 when software sets the Force Port Resume bit to a 0 (from a 1). A write of 0 to this bit is ignored by the host controller. If host software sets this bit to a 1 when the port is not enabled (that is, Port enabled bit is a 0) the results are undefined. 6 Force Port Resume -- R/W. 0 = No resume (K-state) detected/driven on port. (Default) 1 = Resume detected/driven on port. Software sets this bit to a 1 to drive resume signaling. The Host controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a 1 because a J-to-K transition is detected, the Port Change Detect bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 2) in the USB2.0_STS register is also set to a 1. If software sets this bit to a 1, the host controller must not set the Port Change Detect bit. Note: When the EHCI controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification, Revision 2.0. The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a 1. Software must appropriately time the Resume and set this bit to a 0 when the appropriate amount of time has elapsed. Writing a 0 (from 1) causes the port to return to high-speed mode (forcing the bus below the port into a high-speed idle). This bit will remain a 1 until the port has switched to the high-speed idle. 5 Overcurrent Change -- R/WC. The functionality of this bit is not dependent upon the port owner. Software clears this bit by writing a 1 to it. 0 = No change. (Default) 1 = There is a change to Overcurrent Active. 4 Overcurrent Active -- RO. 0 = This port does not have an overcurrent condition. (Default) 1 = This port currently has an overcurrent condition. This bit will automatically transition from 1 to 0 when the over current condition is removed. The PCH automatically disables the port when the overcurrent active bit is 1. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 651 EHCI Controller Registers (D29:F0, D26:F0) 17.2.3 Bit Description 3 Port Enable/Disable Change -- R/WC. For the root hub, this bit gets set to a 1 only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification for the definition of a port error). This bit is not set due to the Disabled-to-Enabled transition, nor due to a disconnect. Software clears this bit by writing a 1 to it. 0 = No change in status. (Default). 1 = Port enabled/disabled status has changed. 2 Port Enabled/Disabled -- R/W. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a 1 to this bit. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. 0 = Disable 1 = Enable (Default) 1 Connect Status Change -- R/WC. This bit indicates a change has occurred in the port's Current Connect Status. Software sets this bit to 0 by writing a 1 to it. 0 = No change (Default). 1 = Change in Current Connect Status. The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be "setting" an already-set bit (that is, the bit will remain set). 0 Current Connect Status -- RO. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. 0 = No device is present. (Default) 1 = Device is present on port. USB 2.0-Based Debug Port Registers The Debug port's registers are located in the same memory area, defined by the Base Address Register (MEM_BASE), as the standard EHCI registers. The base offset for the debug port registers (A0h) is declared in the Debug Port Base Offset Capability Register at Configuration offset 5Ah (D29:F0, D26:F0:offset 5Ah). The specific EHCI port that supports this debug capability (Port 1 for D29:F0 and Port 9 for D26:F0) is indicated by a 4-bit field (bits 20-23) in the HCSPARAMS register of the EHCI controller. The address map of the Debug Port registers is shown in Table 17-4. Table 17-4. Debug Port Register Address Map MEM_BASE + Offset Mnemonic A0-A3h CNTL_STS A4-A7h USBPID A8-AFh DATABUF[7:0] B0-B3h CONFIG Register Name Default Attribute Control/Status 00000000h R/W, R/WC, RO USB PIDs 00000000h R/W, RO Data Buffer (Bytes 7:0) 00000000 00000000h R/W Configuration 00007F01h R/W Notes: 1. All of these registers are implemented in the core well and reset by PLTRST#, EHC HCRESET, and a EHC D3-to-D0 transition. 2. The hardware associated with this register provides no checks to ensure that software programs the interface correctly. How the hardware behaves when programmed improperly is undefined. 652 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet EHCI Controller Registers (D29:F0, D26:F0) 17.2.3.1 CNTL_STS--Control/Status Register Offset: Default Value: MEM_BASE + A0h 00000000h Bit Attribute: Size: R/W, R/WC, RO 32 bits Description 31 Reserved 30 OWNER_CNT -- R/W. 0 = Ownership of the debug port is NOT forced to the EHCI controller (Default) 1 = Ownership of the debug port is forced to the EHCI controller (that is, immediately taken away from the companion Classic USB Host controller) If the port was already owned by the EHCI controller, then setting this bit has no effect. This bit overrides all of the ownership-related bits in the standard EHCI registers. 29 Reserved 28 ENABLED_CNT -- R/W. 0 = Software can clear this by writing a 0 to it. The hardware clears this bit for the same conditions where the Port Enable/Disable Change bit (in the PORTSC register) is set. (Default) 1 = Debug port is enabled for operation. Software can directly set this bit if the port is already enabled in the associated PORTSC register (this is enforced by the hardware). 27:17 16 15:12 Reserved DONE_STS -- R/WC. Software can clear this by writing a 1 to it. 0 = Request Not complete 1 = Set by hardware to indicate that the request is complete. LINK_ID_STS -- RO. This field identifies the link interface. 0h = Hardwired. Indicates that it is a USB Debug Port. 11 Reserved. 10 IN_USE_CNT -- R/W. Set by software to indicate that the port is in use. Cleared by software to indicate that the port is free and may be used by other software. This bit is cleared after reset. (This bit has no affect on hardware.) 9:7 EXCEPTION_STS -- RO. This field indicates the exception when the ERROR_GOOD#_STS bit is set. This field should be ignored if the ERROR_GOOD#_STS bit is 0. 000 =No Error. (Default) Note: This should not be seen since this field should only be checked if there is an error. 001 =Transaction error: Indicates the USB 2.0 transaction had an error (CRC, bad PID, timeout, etc.) 010 =Hardware error. Request was attempted (or in progress) when port was suspended or reset. All Other combinations are reserved 6 5 ERROR_GOOD#_STS -- RO. 0 = Hardware clears this bit to 0 after the proper completion of a read or write. (Default) 1 = Error has occurred. Details on the nature of the error are provided in the Exception field. GO_CNT -- R/W. 0 = Hardware clears this bit when hardware sets the DONE_STS bit. (Default) 1 = Causes hardware to perform a read or write request. Note: 4 3:0 Writing a 1 to this bit when it is already set may result in undefined behavior. WRITE_READ#_CNT -- R/W. Software clears this bit to indicate that the current request is a read. Software sets this bit to indicate that the current request is a write. 0 = Read (Default) 1 = Write DATA_LEN_CNT -- R/W. This field is used to indicate the size of the data to be transferred. default = 0h. For write operations, this field is set by software to indicate to the hardware how many bytes of data in Data Buffer are to be transferred to the console. A value of 0h indicates that a zero-length packet should be sent. A value of 1-8 indicates 1-8 bytes are to be transferred. Values 9-Fh are invalid and how hardware behaves if used is undefined. For read operations, this field is set by hardware to indicate to software how many bytes in Data Buffer are valid in response to a read operation. A value of 0h indicates that a zero length packet was returned and the state of Data Buffer is not defined. A value of 1-8 indicates 1-8 bytes were received. Hardware is not allowed to return values 9-Fh. The transferring of data always starts with byte 0 in the data area and moves toward byte 7 until the transfer size is reached. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 653 EHCI Controller Registers (D29:F0, D26:F0) Notes: 1. Software should do Read-Modify-Write operations to this register to preserve the contents of bits not being modified. This include Reserved bits. 2. To preserve the usage of RESERVED bits in the future, software should always write the same value read from the bit until it is defined. Reserved bits will always return 0 when read. 17.2.3.2 USBPID--USB PIDs Register Offset: Default Value: MEM_BASE + A4h-A7h 00000000h Attribute: Size: R/W, RO 32 bits This Dword register is used to communicate PID information between the USB debug driver and the USB debug port. The debug port uses some of these fields to generate USB packets, and uses other fields to return PID information to the USB debug driver. Bit 31:24 Reserved. 23:16 RECEIVED_PID_STS[23:16] -- RO. Hardware updates this field with the received PID for transactions in either direction. When the controller is writing data, this field is updated with the handshake PID that is received from the device. When the host controller is reading data, this field is updated with the data packet PID (if the device sent data), or the handshake PID (if the device NAKs the request). This field is valid when the hardware clears the GO_DONE#_CNT bit. 15:8 SEND_PID_CNT[15:8] -- R/W. Hardware sends this PID to begin the data packet when sending data to USB (that is, WRITE_READ#_CNT is asserted). Software typically sets this field to either DATA0 or DATA1 PID values. 7:0 17.2.3.3 Description TOKEN_PID_CNT[7:0] -- R/W. Hardware sends this PID as the Token PID for each USB transaction. Software typically sets this field to either IN, OUT, or SETUP PID values. DATABUF[7:0]--Data Buffer Bytes[7:0] Register Offset: Default Value: MEM_BASE + A8h-AFh 0000000000000000h Attribute: Size: R/W 64 bits This register can be accessed as 8 separate 8-bit registers or 2 separate 32-bit register. 17.2.3.4 Bit Description 63:0 DATABUFFER[63:0] -- R/W. This field is the 8 bytes of the data buffer. Bits 7:0 correspond to least significant byte (byte 0). Bits 63:56 correspond to the most significant byte (byte 7). The bytes in the Data Buffer must be written with data before software initiates a write request. For a read request, the Data Buffer contains valid data when DONE_STS bit (offset A0, bit 16) is cleared by the hardware, ERROR_GOOD#_STS (offset A0, bit 6) is cleared by the hardware, and the DATA_LENGTH_CNT field (offset A0, bits 3:0) indicates the number of bytes that are valid. CONFIG--Configuration Register Offset: Default Value: Bit 31:15 14:8 MEM_BASE + B0-B3h 00007F01h Attribute: Size: R/W 32 bits Description Reserved USB_ADDRESS_CNF -- R/W. This 7-bit field identifies the USB device address used by the controller for all Token PID generation. (Default = 7Fh) 7:4 Reserved 3:0 USB_ENDPOINT_CNF -- R/W. This 4-bit field identifies the endpoint used by the controller for all Token PID generation. (Default = 1h) 654 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 18 Intel(R) High Definition Audio Controller Registers (D27:F0) The Intel(R) High Definition Audio (Intel(R) HD Audio) controller resides in PCI Device 27, Function 0 on bus 0. This function contains a set of DMA engines that are used to move samples of digitally encoded data between system memory and external codecs. Note: All registers in this function (including memory-mapped registers) must be addressable in byte, word, and DWord quantities. The software must always make register accesses on natural boundaries (that is, DWord accesses must be on DWord boundaries; word accesses on word boundaries, and so forth) Register access crossing the DWord boundary are ignored. In addition, the memory-mapped register space must not be accessed with the LOCK semantic exclusive-access mechanism. If software attempts exclusive-access mechanisms to the Intel HD Audio memory-mapped space, the results are undefined. Note: Users interested in providing feedback on the Intel HD Audio specification or planning to implement the Intel HD Audio specification into a future product will need to execute the Intel(R) High Definition Audio Specification Developer's Agreement. For more information, contact nextgenaudio@intel.com. 18.1 Intel(R) HD Audio PCI Configuration Space (Intel HD Audio--D27:F0) Note: Address locations that are not shown should be treated as Reserved. Table 18-5. Intel(R) High Definition Audio PCI Register Address Map (Intel HD Audio D27:F0) (Sheet 1 of 2) Offset Mnemonic 00h-01h VID Register Name Default Attribute Vendor Identification 8086h RO Device Identification See register description RO 0000h R/W, RO 0010h R/WC, RO See register description RO 02h-03h DID 04h-05h PCICMD PCI Command 06h-07h PCISTS PCI Status 08h RID Revision Identification 09h PI Programming Interface 00h RO 0Ah SCC Sub Class Code 03h RO 0Bh BCC Base Class Code 04h RO 0Ch CLS Cache Line Size 00h R/W 0Dh LT 0Eh HEADTYP Latency Timer 00h RO Header Type 00h RO R/W, RO 10h-13h HDBARL Intel HD Audio Lower Base Address (Memory) 00000004h 14h-17h HDBARU Intel HD Audio Upper Base Address (Memory) 00000000h R/W 2Ch-2Dh SVID Subsystem Vendor Identification 0000h R/WO 2Eh-2Fh SID Subsystem Identification 0000h R/WO 34h CAPPTR Capability List Pointer 50h RO 3Ch INTLN Interrupt Line 00h R/W 3Dh INTPN Interrupt Pin See Register Description RO Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 655 Intel(R) High Definition Audio Controller Registers (D27:F0) Table 18-5. Intel(R) High Definition Audio PCI Register Address Map (Intel HD Audio D27:F0) (Sheet 2 of 2) Offset Mnemonic 40h HDCTL 43h HDINIT1 4Ch-4Dh 18.1.1 Default Attribute Intel HD Audio Control 01h R/W, RO Intel High Definition Audio Initialization 07h R/W 0000h RO R/WO, RO Reserved 50h-51h PID PCI Power Management Capability ID 6001h 52h-53h PC Power Management Capabilities C842h RO 00000000h R/W, RO, R/WC 7005h RO 54h-57h PCS Power Management Control and Status 60h-61h MID MSI Capability ID 62h-63h MMC MSI Message Control 0080h R/W, RO 64h-67h MMLA MSI Message Lower Address 00000000h R/W, RO 68h-6Bh MMUA MSI Message Upper Address 00000000h R/W 6Ch-6Dh MMD 0000h R/W MSI Message Data 70h-71h PXID PCI Express* Capability Identifiers 0010h RO 72h-73h PXC PCI Express* Capabilities 0091h RO 74h-77h DEVCAP 10000000h RO, R/WO 78h-79h DEVC Device Control 0800h R/W, RO Device Capabilities 7Ah-7Bh DEVS Device Status 0010h RO 100h-103h VCCAP Virtual Channel Enhanced Capability Header 13010002h R/WO 104h-107h PVCCAP1 Port VC Capability Register 1 00000001h RO 108h-10Bh PVCCAP2 Port VC Capability Register 2 00000000h RO 10Ch-10D PVCCTL Port VC Control 0000h RO 10Eh-10Fh PVCSTS Port VC Status 0000h RO 110h-113h VC0CAP VC0 Resource Capability 00000000h RO 114h-117h VC0CTL VC0 Resource Control 800000FFh R/W, RO 11Ah-11Bh VC0STS VC0 Resource Status 0000h RO 11Ch-11Fh VCiCAP VCi Resource Capability 00000000h RO 120h-123h VCiCTL VCi Resource Control 00000000h R/W, RO 126h-127h VCiSTS VCi Resource Status 0000h RO 130h-133h RCCAP Root Complex Link Declaration Enhanced Capability Header 00010005h RO Element Self Description 0F000100h RO Link 1 Description 00000001h RO RO RO 134h-137h ESD 140h-143h L1DESC 148h-14Bh L1ADDL Link 1 Lower Address See Register Description 14Ch-14Fh L1ADDU Link 1 Upper Address 00000000h VID--Vendor Identification Register (Intel(R) HD Audio Controller--D27:F0) Offset: Default Value: Bit 15:0 656 Register Name 00h-01h 8086h Attribute: Size: RO 16 bits Description Vendor ID -- RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 18.1.2 DID--Device Identification Register (Intel(R) High Definition Audio Controller--D27:F0) Offset Address: 02h-03h Default Value: See bit description Bit 15:0 18.1.3 Attribute: Size: RO 16 bits Description Device ID -- RO. This is a 16-bit value assigned to the PCH's Intel High Definition Audio controller. Refer to the Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Specification Update for the value of the Device ID Register PCICMD--PCI Command Register (Intel(R) HD Audio Controller--D27:F0) Offset Address: 04h-05h Default Value: 0000h Bit 15:11 10 Attribute: Size: R/W, RO 16 bits Description Reserved Interrupt Disable (ID) -- R/W. 0= The INTx# signals may be asserted. 1= The Intel HD Audio controller's INTx# signal will be de-asserted. Note: This bit does not affect the generation of MSIs. 9 Fast Back to Back Enable (FBE) -- RO. Not implemented. Hardwired to 0. 8 SERR# Enable (SERR_EN) -- R/W. SERR# is not generated by the PCH's Intel HD Audio Controller. 7 Wait Cycle Control (WCC) -- RO. Not implemented. Hardwired to 0. 6 Parity Error Response (PER) -- R/W. PER functionality not implemented. 5 VGA Palette Snoop (VPS). Not implemented. Hardwired to 0. 4 Memory Write and Invalidate Enable (MWIE) -- RO. Not implemented. Hardwired to 0. 3 Special Cycle Enable (SCE). Not implemented. Hardwired to 0. 2 Bus Master Enable (BME) -- R/W. Controls standard PCI Express* bus mastering capabilities for Memory and I/O, reads and writes. Note that this bit also controls MSI generation since MSI's are essentially Memory writes. 0 = Disable 1 = Enable 1 Memory Space Enable (MSE) -- R/W. Enables memory space addresses to the Intel HD Audio controller. 0 = Disable 1 = Enable 0 I/O Space Enable (IOSE)--RO. Hardwired to 0 since the Intel HD Audio controller does not implement I/O space. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 657 Intel(R) High Definition Audio Controller Registers (D27:F0) 18.1.4 PCISTS--PCI Status Register (Intel(R) HD Audio Controller--D27:F0) Offset Address: 06h-07h Default Value: 0010h Attribute: Size: Bit 15 Description Detected Parity Error (DPE) -- RO. Not implemented. Hardwired to 0. 14 SERR# Status (SERRS) -- RO. Not implemented. Hardwired to 0. 13 Received Master Abort (RMA) -- R/WC. Software clears this bit by writing a 1 to it. 0 = No master abort received. 1 = The Intel High Definition Audio controller sets this bit when, as a bus master, it receives a master abort. When set, the Intel(R) High Definition Audio controller clears the run bit for the channel that received the abort. 12 Received Target Abort (RTA) -- RO. Not implemented. Hardwired to 0. 11 Signaled Target Abort (STA) -- RO. Not implemented. Hardwired to 0. 10:9 DEVSEL# Timing Status (DEV_STS) -- RO. Does not apply. Hardwired to 0. 8 Data Parity Error Detected (DPED) -- RO. Not implemented. Hardwired to 0. 7 Fast Back to Back Capable (FB2BC) -- RO. Does not apply. Hardwired to 0. 6 Reserved. 5 66 MHz Capable (66MHZ_CAP) -- RO. Does not apply. Hardwired to 0. 4 Capabilities List (CAP_LIST) -- RO. Hardwired to 1. Indicates that the controller contains a capabilities pointer list. The first item is pointed to by looking at configuration offset 34h. 3 Interrupt Status (IS) -- RO. 0 = This bit is 0 after the interrupt is cleared. 1 = This bit is 1 when the INTx# is asserted. Note that this bit is not set by an MSI. 2:0 18.1.5 Reserved. RID--Revision Identification Register (Intel(R) HD Audio Controller--D27:F0) Offset: Default Value: 08h See bit description Attribute: Size: Bit 7:0 18.1.6 RO 8 Bits Description (R) Revision ID -- RO. Refer to the Intel C600 Series Chipset and Intel(R) X79 Express Chipset Specification Update for the value of the Revision ID Register PI--Programming Interface Register (Intel(R) HD Audio Controller--D27:F0) Offset: Default Value: 09h 00h Bit 7:0 658 RO, R/WC 16 bits Attribute: Size: RO 8 bits Description Programming Interface -- RO. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 18.1.7 SCC--Sub Class Code Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 0Ah Default Value: 03h Bit 7:0 18.1.8 Sub Class Code (SCC) -- RO. 03h = Audio Device BCC--Base Class Code Register (Intel(R) HD Audio Controller--D27:F0) Bit 7:0 RO 8 bits Base Class Code (BCC) -- RO. 04h = Multimedia device CLS--Cache Line Size Register (Intel(R) HD Audio Controller--D27:F0) Bit 7:0 Attribute: Size: R/W 8 bits Description Cache Line Size -- R/W. Implemented as R/W register, but has no functional impact to the PCH LT--Latency Timer Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 0Dh Default Value: 00h Bit 7:0 18.1.11 Attribute: Size: Description Address Offset: 0Ch Default Value: 00h 18.1.10 RO 8 bits Description Address Offset: 0Bh Default Value: 04h 18.1.9 Attribute: Size: Attribute: Size: RO 8 bits Description Latency Timer -- RO. Hardwired to 00 HEADTYP--Header Type Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 0Eh Default Value: 00h Bit 7:0 Attribute: Size: RO 8 bits Description Header Type -- RO. Hardwired to 00. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 659 Intel(R) High Definition Audio Controller Registers (D27:F0) 18.1.12 HDBARL--Intel(R) HD Audio Lower Base Address Register (Intel(R) HD Audio--D27:F0) Address Offset: 10h-13h Default Value: 00000004h Bit 31:14 13:4 3 18.1.13 R/W, RO 32 bits Description Lower Base Address (LBA) -- R/W. Base address for the Intel HD Audio controller's memory mapped configuration registers. 16 Kbytes are requested by hardwiring bits 13:4 to 0s. Reserved. Prefetchable (PREF) -- RO. Hardwired to 0 to indicate that this BAR is NOT prefetchable 2:1 Address Range (ADDRNG) -- RO. Hardwired to 10b, indicating that this BAR can be located anywhere in 64-bit address space. 0 Space Type (SPTYP) -- RO. Hardwired to 0. Indicates this BAR is located in memory space. HDBARU--Intel(R) HD Audio Upper Base Address Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 14h-17h Default Value: 00000000h 18.1.14 Attribute: Size: Attribute: Size: R/W 32 bits Bit Description 31:0 Upper Base Address (UBA) -- R/W. Upper 32 bits of the Base address for the Intel High Definition Audio controller's memory mapped configuration registers. SVID--Subsystem Vendor Identification Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 2Ch-2Dh Default Value: 0000h Function Level Reset: No Attribute: Size: R/WO 16 bits The SVID register, in combination with the Subsystem ID register (D27:F0:2Eh), enable the operating environment to distinguish one audio subsystem from the other(s). This register is implemented as write-once register. Once a value is written to it, the value can be read back. Any subsequent writes will have no effect. This register is not affected by the D3HOT to D0 transition. Bit 15:0 660 Description Subsystem Vendor ID -- R/WO. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 18.1.15 SID--Subsystem Identification Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 2Eh-2Fh Default Value: 0000h Function Level Reset: No Attribute: Size: R/WO 16 bits The SID register, in combination with the Subsystem Vendor ID register (D27:F0:2Ch) make it possible for the operating environment to distinguish one audio subsystem from the other(s). This register is implemented as write-once register. Once a value is written to it, the value can be read back. Any subsequent writes will have no effect. This register is not affected by the D3HOT to D0 transition. Bit 15:0 18.1.16 Description Subsystem ID -- R/WO. CAPPTR--Capabilities Pointer Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 34h Default Value: 50h Attribute: Size: RO 8 bits This register indicates the offset for the capability pointer. 18.1.17 Bit Description 7:0 Capabilities Pointer (CAP_PTR) -- RO. This field indicates that the first capability pointer offset is offset 50h (Power Management Capability) INTLN--Interrupt Line Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 3Ch Default Value: 00h Bit 7:0 18.1.18 Attribute: Size: R/W 8 bits Description Interrupt Line (INT_LN) -- R/W. This data is not used by the PCH. It is used to communicate to software the interrupt line that the interrupt pin is connected to. INTPN--Interrupt Pin Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 3Dh Default Value: See Description Bit Attribute: Size: RO 8 bits Description 7:4 Reserved. 3:0 Interrupt Pin -- RO. This reflects the value of D27IP.ZIP (Chipset Config Registers:Offset 3110h:bits 3:0). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 661 Intel(R) High Definition Audio Controller Registers (D27:F0) 18.1.19 HDCTL--Intel(R) HD Audio Control Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 40h Default Value: 01h Bit 7:1 0 18.1.20 Reserved. Intel High Definition Signal Mode -- RO. This bit is hardwired to 1 (High Definition Audio mode) HDINIT1--Intel(R) High Definition Audio Initialization Register 1 (Intel(R) High Definition Audio Controller-- D27:F0) Bit R/W 8 bits 7:3 Reserved. 2:0 HDINIT1 Field 1-- R/W. BIOS must program this field to 101b. PID--PCI Power Management Capability ID Register (Intel(R) HD Audio Controller--D27:F0) Bit 15:8 7:0 Attribute: Size: R/WO, RO 16 bits Description Next Capability (Next) -- R/WO. Points to the next capability structure (MSI). Cap ID (CAP) -- RO. Hardwired to 01h. Indicates that this pointer is a PCI power management capability. These bits are not reset by Function Level Reset. PC--Power Management Capabilities Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 52h-53h Default Value: C842h Bit 15:11 Attribute: Size: RO 16 bits Description PME Support -- RO. Hardwired to 11001b. Indicates PME# can be generated from D3 and D0 states. 10 D2 Support -- RO. Hardwired to 0. Indicates that D2 state is not supported. 9 D1 Support --RO. Hardwired to 0. Indicates that D1 state is not supported. 8:6 5 662 Attribute: Size: Description Address Offset: 50h-51h Default Value: 6001h Function Level Reset: No (Bits 7:0 only) 18.1.22 RO 8 bits Description Address Offset: 43h Default Value: 07h 18.1.21 Attribute: Size: Aux Current -- RO. Hardwired to 001b. Reports 55 mA maximum suspend well current required when in the D3COLD state. Device Specific Initialization (DSI) -- RO. Hardwired to 0. Indicates that no device specific initialization is required. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) Bit 4 Reserved 3 PME Clock (PMEC) -- RO. Does not apply. Hardwired to 0. 2:0 18.1.23 Description Version -- RO. Hardwired to 010b. Indicates support for version 1.1 of the PCI Power Management Specification. PCS--Power Management Control and Status Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 54h-57h Default Value: 00000000h Function Level Reset: No Bit 31:24 Attribute: Size: RO, R/W, R/WC 32 bits Description Data -- RO. Does not apply. Hardwired to 0. 23 Bus Power/Clock Control Enable -- RO. Does not apply. Hardwired to 0. 22 B2/B3 Support -- RO. Does not apply. Hardwired to 0. 21:16 15 14:9 8 7:2 Reserved. PME Status (PMES) -- R/WC. 0 = Software clears the bit by writing a 1 to it. 1 = This bit is set when the Intel HD Audio controller would normally assert the PME# signal independent of the state of the PME_EN bit (bit 8 in this register). This bit is in the resume well and is cleared by a power-on reset. Software must not make assumptions about the reset state of this bit and must set it appropriately. Reserved PME Enable (PMEE) -- R/W. 0 = Disable 1 = When set and if corresponding PMES also set, the Intel HD Audio controller sets the PME_B0_STS bit in the GPE0_STS register (PMBASE +28h). This bit in the resume well and is cleared on a power-on reset. Software must not make assumptions about the reset state of this bit and must set it appropriately. Reserved Power State (PS) -- R/W. This field is used both to determine the current power state of the Intel High Definition Audio controller and to set a new power state. 00 = D0 state 11 = D3HOT state Others = reserved 1:0 18.1.24 Notes: 1. If software attempts to write a value of 01b or 10b in to this field, the write operation must complete normally; however, the data is discarded and no state change occurs. 2. When in the D3HOT states, the Intel HD Audio controller's configuration space is available, but the IO and memory space are not. Additionally, interrupts are blocked. 3. When software changes this value from D3HOT state to the D0 state, an internal warm (soft) reset is generated, and software must re-initialize the function. MID--MSI Capability ID Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 60h-61h Default Value: 7005h Bit 15:8 7:0 Attribute: Size: RO 16 bits Description Next Capability (Next) -- RO. Hardwired to 70h. Points to the PCI Express* capability structure. Cap ID (CAP) -- RO. Hardwired to 05h. Indicates that this pointer is a MSI capability Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 663 Intel(R) High Definition Audio Controller Registers (D27:F0) 18.1.25 MMC--MSI Message Control Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 62h-63h Default Value: 0080h Bit 15:8 7 6:4 3:1 0 18.1.26 Reserved 64b Address Capability (64ADD) -- RO. Hardwired to 1. Indicates the ability to generate a 64-bit message address Multiple Message Enable (MME) -- RO. Normally this is a R/W register. However since only 1 message is supported, these bits are hardwired to 000 = 1 message. Multiple Message Capable (MMC) -- RO. Hardwired to 0 indicating request for 1 message. MSI Enable (ME) -- R/W. 0 = an MSI may not be generated 1 = an MSI will be generated instead of an INTx signal. MMLA--MSI Message Lower Address Register (Intel(R) HD Audio Controller--D27:F0) Bit 31:2 1:0 RO, R/W 32 bits Message Lower Address (MLA) -- R/W. Lower address used for MSI message. Reserved. MMUA--MSI Message Upper Address Register (Intel(R) HD Audio Controller--D27:F0) Bit 31:0 Attribute: Size: R/W 32 bits Description Message Upper Address (MUA) -- R/W. Upper 32-bits of address used for MSI message. MMD--MSI Message Data Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 6Ch-6Dh Default Value: 0000h Bit 15:0 664 Attribute: Size: Description Address Offset: 68h-6Bh Default Value: 00000000h 18.1.28 RO, R/W 16 bits Description Address Offset: 64h-67h Default Value: 00000000h 18.1.27 Attribute: Size: Attribute: Size: R/W 16 bits Description Message Data (MD) -- R/W. Data used for MSI message. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 18.1.29 PXID--PCI Express* Capability ID Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 70h-71h Default Value: 0010h Description 15:8 Next Capability (Next) -- RO. Hardwired to 0. Indicates that this is the last capability structure in the list. Cap ID (CAP) -- RO. Hardwired to 10h. Indicates that this pointer is a PCI Express* capability structure. PXC--PCI Express* Capabilities Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 72h-73h Default Value: 0091h Bit 15:14 13:9 8 18.1.31 RO 16 bits Bit 7:0 18.1.30 Attribute: Size: Attribute: Size: RO 16 bits Description Reserved Interrupt Message Number (IMN) -- RO. Hardwired to 0. Slot Implemented (SI) -- RO. Hardwired to 0. 7:4 Device/Port Type (DPT) -- RO. Hardwired to 1001b. Indicates that this is a Root Complex Integrated endpoint device. 3:0 Capability Version (CV) -- RO. Hardwired to 0001b. Indicates version #1 PCI Express* capability DEVCAP--Device Capabilities Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 74h-77h Default Value: 10000000h Function Level Reset: No Bit 31:29 28 Attribute: Size: Description Reserved Function Level Reset (FLR) -- R/WO. A 1 indicates that the PCH Intel HD Audio Controller supports the Function Level Reset Capability. 27:26 Captured Slot Power Limit Scale (SPLS) -- RO. Hardwired to 0. 25:18 Captured Slot Power Limit Value (SPLV) -- RO. Hardwired to 0. 17:15 Reserved 14 Power Indicator Present -- RO. Hardwired to 0. 13 Attention Indicator Present -- RO. Hardwired to 0. 12 Attention Button Present -- RO. Hardwired to 0. 11:9 8:6 5 R/WO, RO 32 bits Endpoint L1 Acceptable Latency -- R/WO. Endpoint L0s Acceptable Latency -- R/WO. Extended Tag Field Support -- RO. Hardwired to 0. Indicates 5-bit tag field support 4:3 Phantom Functions Supported -- RO. Hardwired to 0. Indicates that phantom functions not supported 2:0 Max Payload Size Supported -- RO. Hardwired to 0. Indicates 128-B maximum payload size capability Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 665 Intel(R) High Definition Audio Controller Registers (D27:F0) 18.1.32 DEVC--Device Control Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 78h-79h Default Value: 0800h Function Level Reset: No (Bit 11 Only) Bit 15 14:12 11 Attribute: Size: R/W, RO 16 bits Description Initiate FLR (IF) -- R/W. This bit is used to initiate FLR transition. 1 = A write of 1 initiates FLR transition. Since hardware does not respond to any cycles until FLR completion, the read value by software from this bit is 0. Max Read Request Size -- RO. Hardwired to 0 enabling 128B maximum read request size. No Snoop Enable (NSNPEN) -- R/W. 0 = The Intel HD Audio controller will not set the No Snoop bit. In this case, isochronous transfers will not use VC1 (VCi) even if it is enabled since VC1 is never snooped. Isochronous transfers will use VC0. 1 = The Intel(R) High Definition Audio controller is permitted to set the No Snoop bit in the Requester Attributes of a bus master transaction. In this case, VC0 or VC1 may be used for isochronous transfers. Note: This bit is not reset on D3HOT to D0 transition; however, it is reset by PLTRST#. This bit is not reset by Function Level Reset. 10 9 Phantom Function Enable -- RO. Hardwired to 0 disabling phantom functions. 8 Extended Tag Field Enable -- RO. Hardwired to 0 enabling 5-bit tag. 7:5 18.1.33 Auxiliary Power Enable -- RO. Hardwired to 0, indicating that Intel HD Audio device does not draw AUX power Max Payload Size -- RO. Hardwired to 0 indicating 128B. 4 Enable Relaxed Ordering -- RO. Hardwired to 0 disabling relaxed ordering. 3 Unsupported Request Reporting Enable -- R/W. Not implemented. 2 Fatal Error Reporting Enable -- R/W. Not implemented. 1 Non-Fatal Error Reporting Enable -- R/W. Not implemented. 0 Correctable Error Reporting Enable -- R/W. Not implemented. DEVS--Device Status Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 7Ah-7Bh Default Value: 0010h Bit 15:6 666 Attribute: Size: RO 16 bits Description Reserved 5 Transactions Pending -- RO. 0 = Indicates that completions for all non-posted requests have been received 1 = Indicates that Intel High Definition Audio controller has issued non-posted requests which have not been completed. 4 AUX Power Detected -- RO. Hardwired to 1 indicating the device is connected to resume power 3 Unsupported Request Detected -- RO. Not implemented. Hardwired to 0. 2 Fatal Error Detected -- RO. Not implemented. Hardwired to 0. 1 Non-Fatal Error Detected -- RO. Not implemented. Hardwired to 0. 0 Correctable Error Detected -- RO. Not implemented. Hardwired to 0. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 18.1.34 VCCAP--Virtual Channel Enhanced Capability Header (Intel(R) HD Audio Controller--D27:F0) Address Offset: 100h-103h Default Value: 13010002h Bit 18.1.35 R/WO 32 bits Description 31:20 Next Capability Offset -- R/WO. Points to the next capability header. 130h = Root Complex Link Declaration Enhanced Capability Header 000h = Root Complex Link Declaration Enhanced Capability Header is not supported. 19:16 Capability Version -- R/WO. 0h =PCI Express* Virtual channel capability and the Root Complex Topology Capability structure are not supported. 1h =PCI Express* Virtual channel capability and the Root Complex Topology Capability structure are supported. 15:0 PCI Express* Extended Capability -- R/WO. 0000h =PCI Express* Virtual channel capability and the Root Complex Topology Capability structure are not supported. 0002h =PCI Express* Virtual channel capability and the Root Complex Topology Capability structure are supported. PVCCAP1--Port VC Capability Register 1 (Intel(R) HD Audio Controller--D27:F0) Address Offset: 104h-107h Default Value: 00000001h Bit 31:12 11:10 9:8 7 6:4 3 2:0 18.1.36 Attribute: Size: Attribute: Size: RO 32 bits Description Reserved. Port Arbitration Table Entry Size -- RO. Hardwired to 0 since this is an endpoint device. Reference Clock -- RO. Hardwired to 0 since this is an endpoint device. Reserved. Low Priority Extended VC Count -- RO. Hardwired to 0. Indicates that only VC0 belongs to the low priority VC group Reserved. Extended VC Count -- RO. Hardwired to 001b. Indicates that 1 extended VC (in addition to VC0) is supported by the Intel HD Audio controller. PVCCAP2 -- Port VC Capability Register 2 (Intel(R) HD Audio Controller--D27:F0) Address Offset: 108h-10Bh Default Value: 00000000h Bit 31:24 23:8 7:0 Attribute: Size: RO 32 bits Description VC Arbitration Table Offset -- RO. Hardwired to 0 indicating that a VC arbitration table is not present. Reserved. VC Arbitration Capability -- RO. Hardwired to 0. These bits are not applicable since the Intel HD Audio controller reports a 0 in the Low Priority Extended VC Count bits in the PVCCAP1 register. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 667 Intel(R) High Definition Audio Controller Registers (D27:F0) 18.1.37 PVCCTL -- Port VC Control Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 10Ch-10Dh Default Value: 0000h Bit 15:4 3:1 0 18.1.38 Reserved. VC Arbitration Select -- RO. Hardwired to 0. Normally these bits are R/W. However, these bits are not applicable since the Intel HD Audio controller reports a 0 in the Low Priority Extended VC Count bits in the PVCCAP1 register Load VC Arbitration Table -- RO. Hardwired to 0 since an arbitration table is not present. PVCSTS--Port VC Status Register (Intel(R) HD Audio Controller--D27:F0) Bit 15:1 0 Attribute: Size: RO 16 bits Description Reserved. VC Arbitration Table Status -- RO. Hardwired to 0 since an arbitration table is not present. VC0CAP--VC0 Resource Capability Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 110h-113h Default Value: 00000000h Bit 31:24 23 22:16 Attribute: Size: RO 32 bits Description Port Arbitration Table Offset -- RO. Hardwired to 0 since this field is not valid for endpoint devices Reserved. Maximum Time Slots -- RO. Hardwired to 0 since this field is not valid for endpoint devices 15 Reject Snoop Transactions -- RO. Hardwired to 0 since this field is not valid for endpoint devices. 14 Advanced Packet Switching -- RO. Hardwired to 0 since this field is not valid for endpoint devices 13:8 7:0 668 RO 16 bits Description Address Offset: 10Eh-10Fh Default Value: 0000h 18.1.39 Attribute: Size: Reserved. Port Arbitration Capability -- RO. Hardwired to 0 since this field is not valid for endpoint devices Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 18.1.40 VC0CTL--VC0 Resource Control Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 114h-117h Default Value: 800000FFh Function Level Reset: No Bit 31 Description VC0 Enable -- RO. Hardwired to 1 for VC0. Reserved. 26:24 VC0 ID -- RO. Hardwired to 0 since the first VC is always assigned as VC0 23:20 Reserved. 16 15:8 7:0 Port Arbitration Select -- RO. Hardwired to 0 since this field is not valid for endpoint devices Load Port Arbitration Table -- RO. Hardwired to 0 since this field is not valid for endpoint devices Reserved. TC/VC0 Map -- R/W, RO. Bit 0 is hardwired to 1 since TC0 is always mapped VC0. Bits [7:1] are implemented as R/W bits. VC0STS--VC0 Resource Status Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 11Ah-11Bh Default Value: 0000h Bit 15:2 18.1.42 R/W, RO 32 bits 30:27 19:17 18.1.41 Attribute: Size: Attribute: Size: RO 16 bits Description Reserved. 1 VC0 Negotiation Pending -- RO. Hardwired to 0 since this bit does not apply to the integrated Intel HD Audio device 0 Port Arbitration Table Status -- RO. Hardwired to 0 since this field is not valid for endpoint devices VCiCAP--VCi Resource Capability Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 11Ch-11Fh Default Value: 00000000h Bit 31:24 23 22:16 15 14 13:8 7:0 Attribute: Size: RO 32 bits Description Port Arbitration Table Offset -- RO. Hardwired to 0 since this field is not valid for endpoint devices. Reserved. Maximum Time Slots -- RO. Hardwired to 0 since this field is not valid for endpoint devices Reject Snoop Transactions -- RO. Hardwired to 0 since this field is not valid for endpoint devices Advanced Packet Switching -- RO. Hardwired to 0 since this field is not valid for endpoint devices Reserved Port Arbitration Capability -- RO. Hardwired to 0 since this field is not valid for endpoint devices Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 669 Intel(R) High Definition Audio Controller Registers (D27:F0) 18.1.43 VCiCTL--VCi Resource Control Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 120h-123h Default Value: 00000000h Function Level Reset: No Bit 31 Description VCi Enable -- R/W. 0 = VCi is disabled 1 = VCi is enabled Note: This bit is not reset on D3HOT to D0 transition; however, it is reset by PLTRST#. Reserved. 26:24 VCi ID -- R/W. This field assigns a VC ID to the VCi resource. This field is not used by the PCH hardware, but it is R/W to avoid confusing software. 23:20 Reserved. 19:17 Port Arbitration Select -- RO. Hardwired to 0 since this field is not valid for endpoint devices 16 7:0 Load Port Arbitration Table -- RO. Hardwired to 0 since this field is not valid for endpoint devices Reserved. TC/VCi Map -- R/W, RO. This field indicates the TCs that are mapped to the VCi resource. Bit 0 is hardwired to 0 indicating that it cannot be mapped to VCi. Bits [7:1] are implemented as R/W bits. This field is not used by the PCH hardware, but it is R/W to avoid confusing software. VCiSTS--VCi Resource Status Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 126h-127h Default Value: 0000h Bit 15:2 18.1.45 Attribute: Size: RO 16 bits Description Reserved. 1 VCi Negotiation Pending -- RO. Does not apply. Hardwired to 0. 0 Port Arbitration Table Status -- RO. Hardwired to 0 since this field is not valid for endpoint devices. RCCAP--Root Complex Link Declaration Enhanced Capability Header Register (Intel(R) HD Audio Controller-- D27:F0) Address Offset: 130h Default Value: 00010005h Bit Attribute: Size: RO 32 bits Description 31:20 Next Capability Offset -- RO. Hardwired to 0 indicating this is the last capability. 19:16 Capability Version -- RO. Hardwired to 1h. 15:0 670 R/W, RO 32 bits 30:27 15:8 18.1.44 Attribute: Size: PCI Express* Extended Capability ID -- RO. Hardwired to 0005h. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 18.1.46 ESD--Element Self Description Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 134h-137h Default Value: 0F000100h Bit 18.1.47 31:24 Port Number -- RO. Hardwired to 0Fh indicating that the Intel HD Audio controller is assigned as Port #15d. 23:16 Component ID -- RO. This field returns the value of the ESD.CID field of the chip configuration section. ESD.CID is programmed by BIOS. 15:8 Number of Link Entries -- RO. The Intel HD Audio only connects to one device, the PCH egress port. Therefore this field reports a value of 1h. 7:4 Reserved. 3:0 Element Type (ELTYP) -- RO. The Intel HD Audio controller is an integrated Root Complex Device. Therefore, the field reports a value of 0h. L1DESC--Link 1 Description Register (Intel(R) HD Audio Controller--D27:F0) Bit Attribute: Size: RO 32 bits Description 31:24 Target Port Number -- RO. The Intel HD Audio controller targets the PCH's Port 0. 23:16 Target Component ID -- RO. This field returns the value of the ESD.CID field of the chip configuration section. ESD.CID is programmed by BIOS. 15:2 Reserved. 1 Link Type -- RO. Hardwired to 0 indicating Type 0. 0 Link Valid -- RO. Hardwired to 1. L1ADDL--Link 1 Lower Address Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 148h-14Bh Default Value: See Register Description Bit 31:14 13:0 18.1.49 RO 32 bits Description Address Offset: 140h-143h Default Value: 00000001h 18.1.48 Attribute: Size: Attribute: Size: RO 32 bits Description Link 1 Lower Address -- RO. Hardwired to match the RCBA register value in the PCI-LPC bridge (D31:F0:F0h). Reserved. L1ADDU--Link 1 Upper Address Register (Intel(R) HD Audio Controller--D27:F0) Address Offset: 14Ch-14Fh Default Value: 00000000h Bit 31:0 Attribute: Size: RO 32 bits Description Link 1 Upper Address -- RO. Hardwired to 00000000h. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 671 Intel(R) High Definition Audio Controller Registers (D27:F0) 18.2 Intel(R) HD Audio Memory Mapped Configuration Registers (Intel(R) HD Audio-- D27:F0) The base memory location for these memory mapped configuration registers is specified in the HDBAR register (D27:F0:offset 10h and D27:F0:offset 14h). The individual registers are then accessible at HDBAR + Offset as indicated in the following table. These memory mapped registers must be accessed in byte, word, or DWord quantities. Note: Address locations that are not shown should be treated as Reserved. Table 18-6. Intel(R) HD Audio PCI Register Address Map (Intel(R) HD Audio D27:F0) (Sheet 1 of 4) 672 HDBAR + Offset Mnemonic 00h-01h GCAP Global Capabilities 02h VMIN 03h VMAJ 04h-05h OUTPAY 06h-07h INPAY 08h-0Bh GCTL 0Ch-0Dh WAKEEN 0Eh-0Fh STATESTS 10h-11h GSTS Register Name Default Attribute 4401h RO Minor Version 00h RO Major Version 01h RO Output Payload Capability 003Ch RO Input Payload Capability 001Dh RO 00000000h R/W Wake Enable Global Control 0000h R/W State Change Status 0000h R/WC Global Status 0000h R/WC 12h-13h Rsv Reserved 0000h RO 14h-17h Rsv Reserved 00000000h RO 18h-19h OUTSTRMPAY 1Ah-1Bh INSTRMPAY 1Ch-1Fh Rsv 20h-23h INTCTL Output Stream Payload Capability 0030h RO Input Stream Payload Capability 0018h RO Reserved 00000000h RO Interrupt Control 00000000h R/W 24h-27h INTSTS Interrupt Status 00000000h RO 30h-33h WALCLK Wall Clock Counter 00000000h RO 34-37h Rsv 38h-3Bh SSYNC Reserved 00000000h RO Stream Synchronization 00000000h R/W 40h-43h CORBLBASE CORB Lower Base Address 00000000h R/W, RO 44h-47h CORBUBASE CORB Upper Base Address 00000000h R/W 48h-49h CORBWP CORB Write Pointer 0000h R/W 4Ah-4Bh CORBRP CORB Read Pointer 0000h R/W, RO 4Ch CORBCTL CORB Control 00h R/W 4Dh CORBST CORB Status 00h R/WC 4Eh CORBSIZE CORB Size 42h RO 50h-53h RIRBLBASE RIRB Lower Base Address 00000000h R/W, RO 54h-57h RIRBUBASE RIRB Upper Base Address 58h-59h RIRBWP 5Ah-5Bh 5Ch 00000000h R/W RIRB Write Pointer 0000h R/W, RO RINTCNT Response Interrupt Count 0000h R/W RIRBCTL RIRB Control 00h R/W Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) Table 18-6. Intel(R) HD Audio PCI Register Address Map (Intel(R) HD Audio D27:F0) (Sheet 2 of 4) HDBAR + Offset Mnemonic 5Dh RIRBSTS RIRB Status 5Eh RIRBSIZE RIRB Size 60h-63h IC 64h-67h IR 68h-69h ICS Register Name Default Attribute 00h R/WC 42h RO Immediate Command 00000000h R/W Immediate Response 00000000h RO 0000h R/W, R/WC Immediate Command Status 70h-73h DPLBASE DMA Position Lower Base Address 00000000h R/W, RO 74h-77h DPUBASE DMA Position Upper Base Address 00000000h R/W 80-82h ISD0CTL Input Stream Descriptor 0 (ISD0) Control 83h ISD0STS ISD0 Status 040000h R/W, RO 00h R/WC, RO 84h-87h ISD0LPIB ISD0 Link Position in Buffer 00000000h RO 88h-8Bh ISD0CBL ISD0 Cyclic Buffer Length 00000000h R/W 8Ch-8Dh ISD0LVI ISD0 Last Valid Index 0000h R/W 8Eh-8F ISD0FIFOW ISD0 FIFO Watermark 0004h R/W 90h-91h ISD0FIFOS ISD0 FIFO Size 0077h RO 92h-93h ISD0FMT ISD0 Format 0000h R/W 98h-9Bh ISD0BDPL ISD0 Buffer Descriptor List Pointer-Lower Base Address 00000000h R/W, RO 9Ch-9Fh ISD0BDPU ISD0 Buffer Description List Pointer-Upper Base Address 00000000h R/W A0h-A2h ISD1CTL Input Stream Descriptor 1(ISD01) Control 040000h R/W, RO A3h ISD1STS ISD1 Status 00h R/WC, RO A4h-A7h ISD1LPIB ISD1 Link Position in Buffer 00000000h RO A8h-ABh ISD1CBL ISD1 Cyclic Buffer Length 00000000h R/W ACh-ADh ISD1LVI ISD1 Last Valid Index 0000h R/W AEh-AFh ISD1FIFOW ISD1 FIFO Watermark 0004h R/W B0h-B1h ISD1FIFOS ISD1 FIFO Size 0077h RO B2h-B3h ISD1FMT ISD1 Format 0000h R/W B8h-BBh ISD1BDPL ISD1 Buffer Descriptor List Pointer-Lower Base Address 00000000h R/W, RO BCh-BFh ISD1BDPU ISD1 Buffer Description List Pointer-Upper Base Address 00000000h R/W 040000h R/W, RO 00h R/WC, RO C0h-C2h ISD2CTL Input Stream Descriptor 2 (ISD2) Control C3h ISD2STS ISD2 Status C4h-C7h ISD2LPIB ISD2 Link Position in Buffer 00000000h RO C8h-CBh ISD2CBL ISD2 Cyclic Buffer Length 00000000h R/W CCh-CDh ISD2LVI ISD2 Last Valid Index 0000h R/W CEh-CFh ISD1FIFOW ISD1 FIFO Watermark 0004h R/W D0h-D1h ISD2FIFOS ISD2 FIFO Size 0077h RO D2h-D3h ISD2FMT ISD2 Format 0000h R/W D8h-DBh ISD2BDPL ISD2 Buffer Descriptor List Pointer-Lower Base Address 00000000h R/W, RO DCh-DFh ISD2BDPU ISD2 Buffer Description List Pointer-Upper Base Address 00000000h R/W Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 673 Intel(R) High Definition Audio Controller Registers (D27:F0) Table 18-6. Intel(R) HD Audio PCI Register Address Map (Intel(R) HD Audio D27:F0) (Sheet 3 of 4) 674 HDBAR + Offset Mnemonic E0h-E2h ISD3CTL Input Stream Descriptor 3 (ISD3) Control Register Name Default Attribute 040000h R/W, RO E3h ISD3STS ISD3 Status 00h R/WC, RO E4h-E7h ISD3LPIB ISD3 Link Position in Buffer 00000000h RO E8h-EBh ISD3CBL ISD3 Cyclic Buffer Length 00000000h R/W ECh-EDh ISD3LVI ISD3 Last Valid Index 0000h R/W EEh-EFh ISD3FIFOW ISD3 FIFO Watermark 0004h R/W F0h-F1h ISD3FIFOS ISD3 FIFO Size 0077h RO F2h-F3h ISD3FMT ISD3 Format 0000h R/W F8h-FBh ISD3BDPL ISD3 Buffer Descriptor List Pointer-Lower Base Address 00000000h R/W, RO FCh-FFh ISD3BDPU ISD3 Buffer Description List Pointer-Upper Base Address 00000000h R/W 100h-102h OSD0CTL Output Stream Descriptor 0 (OSD0) Control 040000h R/W, RO 103h OSD0STS OSD0 Status 00h R/WC, RO 104h-107h OSD0LPIB OSD0 Link Position in Buffer 00000000h RO 108h-10Bh OSD0CBL OSD0 Cyclic Buffer Length 00000000h R/W 10Ch-10Dh OSD0LVI OSD0 Last Valid Index 0000h R/W 10Eh-10Fh OSD0FIFOW OSD0 FIFO Watermark 0004h R/W 110h-111h OSD0FIFOS OSD0 FIFO Size 00BFh R/W 112-113h OSD0FMT OSD0 Format 0000h R/W 118h-11Bh OSD0BDPL OSD0 Buffer Descriptor List Pointer-Lower Base Address 00000000h R/W, RO 11Ch-11Fh OSD0BDPU OSD0 Buffer Description List Pointer-Upper Base Address 00000000h R/W 120h-122h OSD1CTL Output Stream Descriptor 1 (OSD1) Control 040000h R/W, RO 123h OSD1STS OSD1 Status 00h R/WC, RO 124h-127h OSD1LPIB OSD1 Link Position in Buffer 00000000h RO 128h-12Bh OSD1CBL OSD1 Cyclic Buffer Length 00000000h R/W 12Ch-12Dh OSD1LVI OSD1 Last Valid Index 0000h R/W 12Eh-12Fh OSD1FIFOW OSD1 FIFO Watermark 0004h R/W 130h-131h OSD1FIFOS OSD1 FIFO Size 00BFh R/W 132h-133h OSD1FMT OSD1 Format 0000h R/W 138h-13Bh OSD1BDPL OSD1 Buffer Descriptor List Pointer-Lower Base Address 00000000h R/W, RO 13Ch-13Fh OSD1BDPU OSD1 Buffer Description List Pointer-Upper Base Address 00000000h R/W 140h-142h OSD2CTL Output Stream Descriptor 2 (OSD2) Control 040000h R/W, RO 143h OSD2STS OSD2 Status 00h R/WC, RO 144h-147h OSD2LPIB OSD2 Link Position in Buffer 00000000h RO 148h-14Bh OSD2CBL OSD2 Cyclic Buffer Length 00000000h R/W 14Ch-14Dh OSD2LVI OSD2 Last Valid Index 0000h R/W 14Eh-14Fh OSD2FIFOW OSD2 FIFO Watermark 0004h R/W 150h-151h OSD2FIFOS OSD2 FIFO Size 00BFh R/W Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) Table 18-6. Intel(R) HD Audio PCI Register Address Map (Intel(R) HD Audio D27:F0) (Sheet 4 of 4) 18.2.1 HDBAR + Offset Mnemonic 152h-153h OSD2FMT OSD2 Format 158h-15Bh OSD2BDPL 15Ch-15Fh OSD2BDPU Register Name Default Attribute 0000h R/W OSD2 Buffer Descriptor List Pointer-Lower Base Address 00000000h R/W, RO OSD2 Buffer Description List Pointer-Upper Base Address 00000000h R/W 040000h R/W, RO 00h R/WC, RO 160h-162h OSD3CTL Output Stream Descriptor 3 (OSD3) Control 163h OSD3STS OSD3 Status 164h-167h OSD3LPIB OSD3 Link Position in Buffer 00000000h RO 168h-16Bh OSD3CBL OSD3 Cyclic Buffer Length 00000000h R/W 16Ch-16Dh OSD3LVI OSD3 Last Valid Index 0000h R/W 16Eh-16Fh OSD3FIFOW OSD3 FIFO Watermark 0004h R/W 170h-171h OSD3FIFOS OSD3 FIFO Size 00BFh R/W 172h-173h OSD3FMT OSD3 Format 0000h R/W 178h-17Bh OSD3BDPL OSD3 Buffer Descriptor List Pointer-Lower Base Address 00000000h R/W, RO 17Ch-17Fh OSD3BDPU OSD3 Buffer Description List Pointer-Upper Base Address 00000000h R/W GCAP--Global Capabilities Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 00h Default Value: 4401h Bit 15:12 18.2.2 Attribute: Size: RO 16 bits Description (R) Number of Output Stream Supported -- R/WO. 0100b indicates that the PCH's Intel High Definition Audio controller supports 4 output streams. 11:8 Number of Input Stream Supported -- R/WO. 0100b indicates that the PCH's Intel(R) High Definition Audio controller supports 4 input streams. 7:3 Number of Bidirectional Stream Supported -- RO. Hardwired to 0 indicating that the PCH's Intel(R) High Definition Audio controller supports 0 bidirectional stream. 2:1 Number of Serial Data Out Signals -- RO. Hardwired to 0 indicating that the PCH's Intel(R) High Definition Audio controller supports 1 serial data output signal. 0 64-bit Address Supported -- R/WO. 1b indicates that the PCH's Intel(R) High Definition Audio controller supports 64-bit addressing for BDL addresses, data buffer addressees, and command buffer addresses. VMIN--Minor Version Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 02h Default Value: 00h Attribute: Size: RO 8 bits Bit Description 7:0 Minor Version -- RO. Hardwired to 0 indicating that the PCH supports minor revision number 00h of the Intel HD Audio specification. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 675 Intel(R) High Definition Audio Controller Registers (D27:F0) 18.2.3 VMAJ--Major Version Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 03h Default Value: 01h 18.2.4 Description 7:0 Major Version -- RO. Hardwired to 01h indicating that the PCH supports major revision number 1 of the Intel HD Audio specification. OUTPAY--Output Payload Capability Register (Intel(R) HD Audio Controller--D27:F0) Bit 15:7 6:0 Attribute: Size: RO 16 bits Description Reserved. Output Payload Capability -- RO. Hardwired to 3Ch indicating 60 word payload. This field indicates the total output payload available on the link. This does not include bandwidth used for command and control. This measurement is in 16-bit word quantities per 48 MHz frame. The default link clock of 24.000 MHz (the data is double pumped) provides 1000 bits per frame, or 62.5 words in total. 40 bits are used for command and control, leaving 60 words available for data payload. 00h = 0 word 01h = 1 word payload. ..... FFh = 256 word payload. INPAY--Input Payload Capability Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 06h Default Value: 001Dh Bit 15:7 6:0 676 RO 8 bits Bit Memory Address:HDBAR + 04h Default Value: 003Ch 18.2.5 Attribute: Size: Attribute: Size: RO 16 bits Description Reserved. Input Payload Capability -- RO. Hardwired to 1Dh indicating 29 word payload. This field indicates the total output payload available on the link. This does not include bandwidth used for response. This measurement is in 16-bit word quantities per 48 MHz frame. The default link clock of 24.000 MHz provides 500 bits per frame, or 31.25 words in total. 36 bits are used for response, leaving 29 words available for data payload. 00h = 0 word 01h = 1 word payload. ..... FFh = 256 word payload. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 18.2.6 GCTL--Global Control Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 08h Default Value: 00000000h Bit 31:9 8 7:2 Attribute: Size: R/W 32 bits Description Reserved. Accept Unsolicited Response Enable -- R/W. 0 = Unsolicited responses from the codecs are not accepted. 1 = Unsolicited response from the codecs are accepted by the controller and placed into the Response Input Ring Buffer. Reserved. 1 Flush Control -- R/W. Writing a 1 to this bit initiates a flush. When the flush completion is received by the controller, hardware sets the Flush Status bit and clears this Flush Control bit. Before a flush cycle is initiated, the DMA Position Buffer must be programmed with a valid memory address by software, but the DMA Position Buffer bit 0 needs not be set to enable the position reporting mechanism. Also, all streams must be stopped (the associated RUN bit must be 0). When the flush is initiated, the controller will flush the pipelines to memory to ensure that the hardware is ready to transition to a D3 state. Setting this bit is not a critical s4tep in the power state transition if the content of the FIFOs is not critical. 0 Controller Reset # -- R/W. 0 = Writing a 0 causes the Intel HD Audio controller to be reset. All state machines, FIFOs and nonresume well memory mapped configuration registers (not PCI configuration registers) in the controller will be reset. The Intel HD Audio link RESET# signal will be asserted, and all other link signals will be driven to their default values. After the hardware has completed sequencing into the reset state, it will report a 0 in this bit. Software must read a 0 from this bit to verify the controller is in reset. 1 = Writing a 1 causes the controller to exit its reset state and deassert the Intel HD Audio link RESET# signal. Software is responsible for setting/clearing this bit such that the minimum Intel HD Audio link RESET# signal assertion pulse width specification is met. When the controller hardware is ready to begin operation, it will report a 1 in this bit. Software must read a 1 from this bit before accessing any controller registers. This bit defaults to a 0 after Hardware reset, therefore, software needs to write a 1 to this bit to begin operation. Notes: 1. The CORB/RIRB RUN bits and all stream RUN bits must be verified cleared to 0 before writing a 0 to this bit in order to assure a clean re-start. 2. When setting or clearing this bit, software must ensure that minimum link timing requirements (minimum RESET# assertion time, and so forth) are met. 3. When this bit is 0 indicating that the controller is in reset, writes to all Intel HD Audio memory mapped registers are ignored as if the device is not present. The only exception is this register itself. The Global Control register is write-able as a DWord, Word, or Byte even when CRST# (this bit) is 0 if the byte enable for the byte containing the CRST# bit (Byte Enable 0) is active. If Byte Enable 0 is not active, writes to the Global Control register will be ignored when CRST# is 0. When CRST# is 0, reads to Intel HD Audio memory mapped registers will return their default value except for registers that are not reset with PLTRST# or on a D3HOT to D0 transition. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 677 Intel(R) High Definition Audio Controller Registers (D27:F0) 18.2.7 WAKEEN--Wake Enable Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 0Ch Default Value: 0000h Function Level Reset: No Bit 15:4 3:0 Reserved. SDIN Wake Enable Flags -- R/W. These bits control which SDI signal(s) may generate a wake event. A 1b in the bit mask indicates that the associated SDIN signal is enabled to generate a wake. Bit 0 is used for SDI[0] Bit 1 is used for SDI[1] Bit 2 is used for SDI[2] Bit 3 is used for SDI[3] These bits are in the resume well and only cleared on a power on reset. Software must not make assumptions about the reset state of these bits and must set them appropriately. STATESTS--State Change Status Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 0Eh Default Value: 0000h Function Level Reset: No Bit 15:4 3:0 18.2.9 Attribute: Size: R/WC 16 bits Description Reserved. SDIN State Change Status Flags -- R/WC. Flag bits that indicate which SDI signal(s) received a state change event. The bits are cleared by writing 1s to them. Bit 0 = SDI[0] Bit 1 = SDI[1] Bit 2 = SDI[2] Bit 3 = SDI[3] These bits are in the resume well and only cleared on a power on reset. Software must not make assumptions about the reset state of these bits and must set them appropriately. GSTS--Global Status Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 10h Default Value: 0000h Bit 15:2 678 R/W 16 bits Description Note: 18.2.8 Attribute: Size: Attribute: Size: R/WC 16 bits Description Reserved. 1 Flush Status -- R/WC. This bit is set to 1 by hardware to indicate that the flush cycle initiated when the Flush Control bit (HDBAR + 08h, bit 1) was set has completed. Software must write a 1 to clear this bit before the next time the Flush Control bit is set to clear the bit. 0 Reserved. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 18.2.10 OUTSTRMPAY--Output Stream Payload Capability (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 18h Default Value: 0030h Bit 15:8 7:0 18.2.11 RO 16 bits Description Reserved Output Stream Payload Capability (OUTSTRMPAY)-- RO: Indicates maximum number of words per frame for any single output stream. This measurement is in 16 bit word quantities per 48 kHz frame. 48 Words (96B) is the maximum supported, therefore a value of 30h is reported in this register. Software must ensure that a format which would cause more words per frame than indicated is not programmed into the Output Stream Descriptor register. 00h: 0 words 01h: 1 word payload ... FFh: 255h word payload INSTRMPAY--Input Stream Payload Capability (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 1Ah Default Value: 0018h Bit 15:8 7:0 18.2.12 Attribute: Size: Attribute: Size: RO 16 bits Description Reserved Input Stream Payload Capability (INSTRMPAY)-- RO. Indicates maximum number of words per frame for any single input stream. This measurement is in 16 bit word quantities per 48 kHz frame. 24 Words (48B) is the maximum supported, therefore a value of 18h is reported in this register. Software must ensure that a format which would cause more words per frame than indicated is not programmed into the Input Stream Descriptor register. 00h: 0 words 01h: 1 word payload ... FFh: 255h word payload INTCTL--Interrupt Control Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 20h Default Value: 00000000h Attribute: Size: R/W 32 bits Bit Description 31 Global Interrupt Enable (GIE) -- R/W. Global bit to enable device interrupt generation. 1 = When set to 1, the Intel HD Audio function is enabled to generate an interrupt. This control is in addition to any bits in the bus specific address space, such as the Interrupt Enable bit in the PCI configuration space. Note: This bit is not affected by the D3HOT to D0 transition. 30 Controller Interrupt Enable (CIE) -- R/W. Enables the general interrupt for controller functions. 1 = When set to 1, the controller generates an interrupt when the corresponding status bit gets set due to a Response Interrupt, a Response Buffer Overrun, and State Change events. Note: This bit is not affected by the D3HOT to D0 transition. 29:8 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 679 Intel(R) High Definition Audio Controller Registers (D27:F0) Bit 7:0 18.2.13 Description Stream Interrupt Enable (SIE) -- R/W. When set to 1, the individual streams are enabled to generate an interrupt when the corresponding status bits get set. A stream interrupt will be caused as a result of a buffer with IOC = 1in the BDL entry being completed, or as a result of a FIFO error (underrun or overrun) occurring. Control over the generation of each of these sources is in the associated Stream Descriptor. The streams are numbered and the SIE bits assigned sequentially, based on their order in the register set. Bit 0 = input stream 1 Bit 1 = input stream 2 Bit 2 = input stream 3 Bit 3 = input stream 4 Bit 4 = output stream 1 Bit 5 = output stream 2 Bit 6 = output stream 3 Bit 7 = output stream 4 INTSTS--Interrupt Status Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 24h Default Value: 00000000h Bit Attribute: Size: RO 32 bits Description 31 Global Interrupt Status (GIS) -- RO. This bit is an OR of all the interrupt status bits in this register. Note: This bit is not affected by the D3HOT to D0 transition. 30 Controller Interrupt Status (CIS) -- RO. Status of general controller interrupt. 1 = Interrupt condition occurred due to a Response Interrupt, a Response Buffer Overrun Interrupt, or a SDIN State Change event. The exact cause can be determined by interrogating other registers. This bit is an OR of all of the stated interrupt status bits for this register. Notes: 1. This bit is set regardless of the state of the corresponding interrupt enable bit, but a hardware interrupt will not be generated unless the corresponding enable bit is set. 2. This bit is not affected by the D3HOT to D0 transition. 29:8 Reserved Stream Interrupt Status (SIS) -- RO. 1 = Interrupt condition occurred on the corresponding stream. This bit is an OR of all of the stream's interrupt status bits. 7:0 680 Note: These bits are set regardless of the state of the corresponding interrupt enable bits. The streams are numbered and the SIE bits assigned sequentially, based on their order in the register set. Bit 0 = input stream 1 Bit 1 = input stream 2 Bit 2 = input stream 3 Bit 3 = input stream 4 Bit 4 = output stream 1 Bit 5 = output stream 2 Bit 6 = output stream 3 Bit 7 = output stream 4 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 18.2.14 WALCLK--Wall Clock Counter Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 30h Default Value: 00000000h 18.2.15 RO 32 bits Bit Description 31:0 Wall Clock Counter -- RO. A 32 bit counter that is incremented on each link Bit Clock period and rolls over from FFFF FFFFh to 0000 0000h. This counter will roll over to 0 with a period of approximately 179 seconds. This counter is enabled while the Bit Clock bit is set to 1. Software uses this counter to synchronize between multiple controllers. Will be reset on controller reset. SSYNC--Stream Synchronization Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 38h Default Value: 00000000h Bit 31:8 7:0 18.2.16 Attribute: Size: Attribute: Size: R/W 32 bits Description Reserved Stream Synchronization (SSYNC) -- R/W. When set to 1, these bits block data from being sent on or received from the link. Each bit controls the associated stream descriptor (that is, bit 0 corresponds to the first stream descriptor, and so forth). To synchronously start a set of DMA engines, these bits are first set to 1. The RUN bits for the associated stream descriptors are then set to 1 to start the DMA engines. When all streams are ready (FIFORDY =1), the associated SSYNC bits can all be set to 0 at the same time, and transmission or reception of bits to or from the link will begin together at the start of the next full link frame. To synchronously stop the streams, fist these bits are set, and then the individual RUN bits in the stream descriptor are cleared by software. If synchronization is not desired, these bits may be left as 0, and the stream will simply begin running normally when the stream's RUN bit is set. The streams are numbered and the SIE bits assigned sequentially, based on their order in the register set. Bit 0 = input stream 1 Bit 1 = input stream 2 Bit 2 = input stream 3 Bit 3 = input stream 4 Bit 4 = output stream 1 Bit 5 = output stream 2 Bit 6 = output stream 3 Bit 7 = output stream 4 CORBLBASE--CORB Lower Base Address Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 40h Default Value: 00000000h Bit 31:7 6:0 Attribute: Size: R/W, RO 32 bits Description CORB Lower Base Address -- R/W. Lower address of the Command Output Ring Buffer, allowing the CORB base address to be assigned on any 128-B boundary. This register field must not be written when the DMA engine is running or the DMA transfer may be corrupted. CORB Lower Base Unimplemented Bits -- RO. Hardwired to 0. This required the CORB to be allocated with 128B granularity to allow for cache line fetch optimizations. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 681 Intel(R) High Definition Audio Controller Registers (D27:F0) 18.2.17 CORBUBASE--CORB Upper Base Address Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 44h Default Value: 00000000h Bit 31:0 18.2.18 CORB Upper Base Address -- R/W. Upper 32 bits of the address of the Command Output Ring buffer. This register field must not be written when the DMA engine is running or the DMA transfer may be corrupted. CORBWP--CORB Write Pointer Register (Intel(R) HD Audio Controller--D27:F0) Bit 15:8 7:0 Attribute: Size: R/W 16 bits Description Reserved. CORB Write Pointer -- R/W. Software writes the last valid CORB entry offset into this field in DWord granularity. The DMA engine fetches commands from the CORB until the Read pointer matches the Write pointer. Supports 256 CORB entries (256x4B = 1 KB). This register field may be written when the DMA engine is running. CORBRP--CORB Read Pointer Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 4Ah Default Value: 0000h Attribute: Size: R/W, RO 16 bits Bit Description 15 CORB Read Pointer Reset -- R/W. Software writes a 1 to this bit to reset the CORB Read Pointer to 0 and clear any residual prefetched commands in the CORB hardware buffer within the Intel High Definition Audio controller. The hardware will physically update this bit to 1 when the CORB Pointer reset is complete. Software must read a 1 to verify that the reset completed correctly. Software must clear this bit back to 0 and read back the 0 to verify that the clear completed correctly. The CORB DMA engine must be stopped prior to resetting the Read Pointer or else DMA transfer may be corrupted. 14:8 7:0 682 R/W 32 bits Description Memory Address:HDBAR + 48h Default Value: 0000h 18.2.19 Attribute: Size: Reserved. CORB Read Pointer (CORBRP)-- RO. Software reads this field to determine how many commands it can write to the CORB without over-running. The value read indicates the CORB Read Pointer offset in Dword granularity. The offset entry read from this field has been successfully fetched by the DMA controller and may be over-written by software. Supports 256 CORB entries (256 x 4B=1 KB). This field may be read while the DMA engine is running. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 18.2.20 Using CORBCTL--CORB Control Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 4Ch Default Value: 00h Bit 7:2 18.2.21 R/W 8 bits Description Reserved. 1 Enable CORB DMA Engine -- R/W. 0 = DMA stop 1 = DMA run After software writes a 0 to this bit, the hardware may not stop immediately. The hardware will physically update the bit to 0 when the DMA engine is truly stopped. Software must read a 0 from this bit to verify that the DMA engine is truly stopped. 0 CORB Memory Error Interrupt Enable -- R/W. If this bit is set the controller will generate an interrupt if the CMEI status bit (HDBAR + 4Dh: bit 0) is set. CORBST--CORB Status Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 4Dh Default Value: 00h Bit 7:1 0 18.2.22 Attribute: Size: Attribute: Size: R/WC 8 bits Description Reserved. CORB Memory Error Indication (CMEI) -- R/WC. 1 = Controller detected an error in the path way between the controller and memory. This may be an ECC bit error or any other type of detectable data error which renders the command data fetched invalid. Software can clear this bit by writing a 1 to it. However, this type of error leaves the audio subsystem in an un-viable state and typically requires a controller reset by writing a 0 to the Controller Reset # bit (HDBAR + 08h: bit 0). CORBSIZE--CORB Size Register Intel(R) HD Audio Controller--D27:F0using) Memory Address:HDBAR + 4Eh Default Value: 42h Bit Attribute: Size: RO 8 bits Description 7:4 CORB Size Capability -- RO. Hardwired to 0100b indicating that the PCH only supports a CORB size of 256 CORB entries (1024B) 3:2 Reserved. 1:0 CORB Size -- RO. Hardwired to 10b which sets the CORB size to 256 entries (1024B) Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 683 Intel(R) High Definition Audio Controller Registers (D27:F0) 18.2.23 RIRBLBASE--RIRB Lower Base Address Register (Intel(R) HD AudioController--D27:F0) Memory Address:HDBAR + 50h Default Value: 00000000h 18.2.24 Description 31:7 RIRB Lower Base Address -- R/W. Lower address of the Response Input Ring Buffer, allowing the RIRB base address to be assigned on any 128-B boundary. This register field must not be written when the DMA engine is running or the DMA transfer may be corrupted. 6:0 RIRB Lower Base Unimplemented Bits -- RO. Hardwired to 0. This required the RIRB to be allocated with 128-B granularity to allow for cache line fetch optimizations. RIRBUBASE--RIRB Upper Base Address Register (Intel(R) HD Audio Controller--D27:F0) Attribute: Size: R/W 32 bits Bit Description 31:0 RIRB Upper Base Address -- R/W. Upper 32 bits of the address of the Response Input Ring Buffer. This register field must not be written when the DMA engine is running or the DMA transfer may be corrupted. RIRBWP--RIRB Write Pointer Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 58h Default Value: 0000h Attribute: Size: R/W, RO 16 bits Bit Description 15 RIRB Write Pointer Reset -- R/W. Software writes a 1 to this bit to reset the RIRB Write Pointer to 0. The RIRB DMA engine must be stopped prior to resetting the Write Pointer or else DMA transfer may be corrupted. This bit is always read as 0. 14:8 7:0 684 R/W, RO 32 bits Bit Memory Address:HDBAR + 54h Default Value: 00000000h 18.2.25 Attribute: Size: Reserved. RIRB Write Pointer (RIRBWP) -- RO. Indicates the last valid RIRB entry written by the DMA controller. Software reads this field to determine how many responses it can read from the RIRB. The value read indicates the RIRB Write Pointer offset in 2 DWord RIRB entry units (since each RIRB entry is 2 DWords long). Supports up to 256 RIRB entries (256 x 8 B = 2 KB). This register field may be written when the DMA engine is running. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 18.2.26 RINTCNT--Response Interrupt Count Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 5Ah Default Value: 0000h Bit 15:8 7:0 18.2.27 Attribute: Size: R/W 16 bits Description Reserved. N Response Interrupt Count -- R/W. 0000 0001b = 1 response sent to RIRB ........... 1111 1111b = 255 responses sent to RIRB 0000 0000b = 256 responses sent to RIRB The DMA engine should be stopped when changing this field or else an interrupt may be lost. Note that each response occupies 2 DWords in the RIRB. This is compared to the total number of responses that have been returned, as opposed to the number of frames in which there were responses. If more than one codecs responds in one frame, then the count is increased by the number of responses received in the frame. RIRBCTL--RIRB Control Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 5Ch Default Value: 00h Bit 7:3 Attribute: Size: R/W 8 bits Description Reserved. 2 Response Overrun Interrupt Control -- R/W. If this bit is set, the hardware will generate an interrupt when the Response Overrun Interrupt Status bit (HDBAR + 5Dh: bit 2) is set. 1 Enable RIRB DMA Engine -- R/W. 0 = DMA stop 1 = DMA run After software writes a 0 to this bit, the hardware may not stop immediately. The hardware will physically update the bit to 0 when the DMA engine is truly stopped. Software must read a 0 from this bit to verify that the DMA engine is truly stopped. 0 Response Interrupt Control -- R/W. 0 = Disable Interrupt 1 = Generate an interrupt after N number of responses are sent to the RIRB buffer OR when an empty Response slot is encountered on all SDI[x] inputs (whichever occurs first). The N counter is reset when the interrupt is generated. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 685 Intel(R) High Definition Audio Controller Registers (D27:F0) 18.2.28 RIRBSTS--RIRB Status Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 5Dh Default Value: 00h Bit 7:3 2 18.2.29 Reserved. Response Overrun Interrupt Status -- R/WC. 1 = Software sets this bit to 1 when the RIRB DMA engine is not able to write the incoming responses to memory before additional incoming responses overrun the internal FIFO. When the overrun occurs, the hardware will drop the responses which overrun the buffer. An interrupt may be generated if the Response Overrun Interrupt Control bit is set. Note that this status bit is set even if an interrupt is not enabled for this event. Software clears this bit by writing a 1 to it. 1 Reserved. 0 Response Interrupt -- R/WC. 1 = Hardware sets this bit to 1 when an interrupt has been generated after N number of Responses are sent to the RIRB buffer OR when an empty Response slot is encountered on all SDI[x] inputs (whichever occurs first). Note that this status bit is set even if an interrupt is not enabled for this event. Software clears this bit by writing a 1 to it. RIRBSIZE--RIRB Size Register (Intel(R) HD Audio Controller--D27:F0) Attribute: Size: RO 8 bits Bit Description 7:4 RIRB Size Capability -- RO. Hardwired to 0100b indicating that the PCH only supports a RIRB size of 256 RIRB entries (2048B) 3:2 Reserved. 1:0 RIRB Size -- RO. Hardwired to 10b which sets the CORB size to 256 entries (2048B) IC--Immediate Command Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 60h Default Value: 00000000h 686 R/WC 8 bits Description Memory Address:HDBAR + 5Eh Default Value: 42h 18.2.30 Attribute: Size: Attribute: Size: R/W 32 bits Bit Description 31:0 Immediate Command Write -- R/W. The command to be sent to the codec using the Immediate Command mechanism is written to this register. The command stored in this register is sent out over the link during the next available frame after a 1 is written to the ICB bit (HDBAR + 68h: bit 0) Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 18.2.31 IR--Immediate Response Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 64h Default Value: 00000000h Bit 31:0 18.2.32 RO 32 bits Description Immediate Response Read (IRR) -- RO. This register contains the response received from a codec resulting from a command sent using the Immediate Command mechanism. If multiple codecs responded in the same time, there is no assurance as to which response will be latched. Therefore, broadcast-type commands must not be issued using the Immediate Command mechanism. ICS--Immediate Command Status Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 68h Default Value: 0000h Bit 15:2 1 0 Attribute: Size: R/W, R/WC 16 bits Description Reserved. Immediate Result Valid (IRV) -- R/WC. 1 = Set to 1 by hardware when a new response is latched into the Immediate Response register (HDBAR + 64). This is a status flag indicating that software may read the response from the Immediate Response register. Software must clear this bit by writing a 1 to it before issuing a new command so that the software may determine when a new response has arrived. Immediate Command Busy (ICB) -- R/W. When this bit is read as 0, it indicates that a new command may be issued using the Immediate Command mechanism. When this bit transitions from a 0 to a 1 (using software writing a 1), the controller issues the command currently stored in the Immediate Command register to the codec over the link. When the corresponding response is latched into the Immediate Response register, the controller hardware sets the IRV flag and clears the ICB bit back to 0. Software may write this bit to a 0 if the bit fails to return to 0 after a reasonable time out period. Note: 18.2.33 Attribute: Size: An Immediate Command must not be issued while the CORB/RIRB mechanism is operating, otherwise the responses conflict. This must be enforced by software. DPLBASE--DMA Position Lower Base Address Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 70h Default Value: 00000000h Attribute: Size: R/W, RO 32 bits Bit Description 31:7 DMA Position Lower Base Address -- R/W. Lower 32 bits of the DMA Position Buffer Base Address. This register field must not be written when any DMA engine is running or the DMA transfer may be corrupted. This same address is used by the Flush Control and must be programmed with a valid value before the Flush Control bit (HDBAR+08h:bit 1) is set. 6:1 0 DMA Position Lower Base Unimplemented bits -- RO. Hardwired to 0 to force the 128-byte buffer alignment for cache line write optimizations. DMA Position Buffer Enable -- R/W. 1 = Controller will write the DMA positions of each of the DMA engines to the buffer in the main memory periodically (typically once per frame). Software can use this value to know what data in memory is valid data. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 687 Intel(R) High Definition Audio Controller Registers (D27:F0) 18.2.34 DPUBASE--DMA Position Upper Base Address Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:HDBAR + 74h Default Value: 00000000h 18.2.35 Attribute: Size: Bit Description 31:0 DMA Position Upper Base Address -- R/W. Upper 32 bits of the DMA Position Buffer Base Address. This register field must not be written when any DMA engine is running or the DMA transfer may be corrupted. SDCTL--Stream Descriptor Control Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:Input Stream[0]: HDBAR + 80hAttribute: Input Stream[1]: HDBAR + A0h Input Stream[2]: HDBAR + C0h Input Stream[3]: HDBAR + E0h Output Stream[0]: HDBAR + 100h Output Stream[1]: HDBAR + 120h Output Stream[2]: HDBAR + 140h Output Stream[3]: HDBAR + 160h Default Value: 040000h Size:24 bits R/W, RO Bit Description 23:20 Stream Number -- R/W. This value reflect the Tag associated with the data being transferred on the link. When data controlled by this descriptor is sent out over the link, it will have its stream number encoded on the SYNC signal. When an input stream is detected on any of the SDI signals that match this value, the data samples are loaded into FIFO associated with this descriptor. Note that while a single SDI input may contain data from more than one stream number, two different SDI inputs may not be configured with the same stream number. 0000 = Reserved 0001 = Stream 1 ........ 1110 = Stream 14 1111 = Stream 15 19 Bidirectional Direction Control -- RO. This bit is only meaningful for bidirectional streams; therefore, this bit is hardwired to 0. 18 Traffic Priority -- RO. Hardwired to 1 indicating that all streams will use VC1 if it is enabled through the PCI Express* registers. 17:16 15:5 688 R/W 32 bits Stripe Control -- RO. This bit is only meaningful for input streams; therefore, this bit is hardwired to 0. Reserved 4 Descriptor Error Interrupt Enable -- R/W. 0 = Disable 1 = An interrupt is generated when the Descriptor Error Status bit is set. 3 FIFO Error Interrupt Enable -- R/W. This bit controls whether the occurrence of a FIFO error (overrun for input or underrun for output) will cause an interrupt or not. If this bit is not set, bit 3in the Status register will be set, but the interrupt will not occur. Either way, the samples will be dropped. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 18.2.36 Bit Description 2 Interrupt on Completion Enable -- R/W. This bit controls whether or not an interrupt occurs when a buffer completes with the IOC bit set in its descriptor. If this bit is not set, bit 2 in the Status register will be set, but the interrupt will not occur. 1 Stream Run (RUN) -- R/W. 0 = DMA engine associated with this input stream will be disabled. The hardware will report a 0 in this bit when the DMA engine is actually stopped. Software must read a 0 from this bit before modifying related control registers or restarting the DMA engine. 1 = DMA engine associated with this input stream will be enabled to transfer data from the FIFO to the main memory. The SSYNC bit must also be cleared in order for the DMA engine to run. For output streams, the cadence generator is reset whenever the RUN bit is set. 0 Stream Reset (SRST) -- R/W. 0 = Writing a 0 causes the corresponding stream to exit reset. When the stream hardware is ready to begin operation, it will report a 0 in this bit. Software must read a 0 from this bit before accessing any of the stream registers. 1 = Writing a 1 causes the corresponding stream to be reset. The Stream Descriptor registers (except the SRST bit itself) and FIFOs for the corresponding stream are reset. After the stream hardware has completed sequencing into the reset state, it will report a 1 in this bit. Software must read a 1 from this bit to verify that the stream is in reset. The RUN bit must be cleared before SRST is asserted. SDSTS--Stream Descriptor Status Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:Input Stream[0]: HDBAR + 83h Input Stream[1]: HDBAR + A3h Input Stream[2]: HDBAR + C3h Input Stream[3]: HDBAR + E3h Output Stream[0]: HDBAR + 103h Output Stream[1]: HDBAR + 123h Output Stream[2]: HDBAR + 143h Output Stream[3]: HDBAR + 163h Default Value: 00h Bit 7:6 Attribute:R/WC, RO Size: 8 bits Description Reserved. 5 FIFO Ready (FIFORDY) -- RO. For output streams, the controller hardware will set this bit to 1 while the output DMA FIFO contains enough data to maintain the stream on the link. This bit defaults to 0 on reset because the FIFO is cleared on a reset. For input streams, the controller hardware will set this bit to 1 when a valid descriptor is loaded and the engine is ready for the RUN bit to be set. 4 Descriptor Error -- R/WC. 1 = A serious error occurred during the fetch of a descriptor. This could be a result of a Master Abort, a parity or ECC error on the bus, or any other error which renders the current Buffer Descriptor or Buffer Descriptor list useless. This error is treated as a fatal stream error, as the stream cannot continue running. The RUN bit will be cleared and the stream will stopped. Software may attempt to restart the stream engine after addressing the cause of the error and writing a 1 to this bit to clear it. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 689 Intel(R) High Definition Audio Controller Registers (D27:F0) Bit Description 3 FIFO Error -- R/WC. 1 = FIFO error occurred. This bit is set even if an interrupt is not enabled. The bit is cleared by writing a 1 to it. For an input stream, this indicates a FIFO overrun occurring while the RUN bit is set. When this happens, the FIFO pointers do not increment and the incoming data is not written into the FIFO, thereby being lost. For an output stream, this indicates a FIFO underrun when there are still buffers to send. The hardware should not transmit anything on the link for the associated stream if there is not valid data to send. 2 Buffer Completion Interrupt Status -- R/WC. This bit is set to 1 by the hardware after the last sample of a buffer has been processed, AND if the Interrupt on Completion bit is set in the command byte of the buffer descriptor. It remains active until software clears it by writing a 1 to it. 1:0 18.2.37 18.2.38 690 Reserved. SDLPIB--Stream Descriptor Link Position in Buffer Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:Input Stream[0]: HDBAR + 84h Input Stream[1]: HDBAR + A4h Input Stream[2]: HDBAR + C4h Input Stream[3]: HDBAR + E4h Output Stream[0]: HDBAR + 104h Output Stream[1]: HDBAR + 124h Output Stream[2]: HDBAR + 144h Output Stream[3]: HDBAR + 164h Attribute:RO Default Value: 32 bits 00000000h Size: Bit Description 31:0 Link Position in Buffer -- RO. Indicates the number of bytes that have been received off the link. This register will count from 0 to the value in the Cyclic Buffer Length register and then wrap to 0. SDCBL--Stream Descriptor Cyclic Buffer Length Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:Input Stream[0]: HDBAR + 88h Input Stream[1]: HDBAR + A8h Input Stream[2]: HDBAR + C8h Input Stream[3]: HDBAR + E8h Output Stream[0]: HDBAR + 108h Output Stream[1]: HDBAR + 128h Output Stream[2]: HDBAR + 148h Output Stream[3]: HDBAR + 168h Attribute:R/W Default Value: Size:32 bits 00000000h Bit Description 31:0 Cyclic Buffer Length -- R/W. Indicates the number of bytes in the complete cyclic buffer. This register represents an integer number of samples. Link Position in Buffer will be reset when it reaches this value. Software may only write to this register after Global Reset, Controller Reset, or Stream Reset has occurred. This value should be only modified when the RUN bit is 0. Once the RUN bit has been set to enable the engine, software must not write to this register until after the next reset is asserted, or transfer may be corrupted. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 18.2.39 SDLVI--Stream Descriptor Last Valid Index Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:Input Stream[0]: HDBAR + 8Ch Input Stream[1]: HDBAR + ACh Input Stream[2]: HDBAR + CCh Input Stream[3]: HDBAR + ECh Output Stream[0]: HDBAR + 10Ch Output Stream[1]: HDBAR + 12Ch Output Stream[2]: HDBAR + 14Ch Output Stream[3]: HDBAR + 16Ch Attribute:R/W Default Value: 16 bits 0000h Bit 15:8 7:0 18.2.40 Size: Description Reserved. Last Valid Index -- R/W. The value written to this register indicates the index for the last valid Buffer Descriptor in BDL. After the controller has processed this descriptor, it will wrap back to the first descriptor in the list and continue processing. This field must be at least 1; that is, there must be at least 2 valid entries in the buffer descriptor list before DMA operations can begin. This value should only modified when the RUN bit is 0. SDFIFOW--Stream Descriptor FIFO Watermark Register (Intel(R) HD Audio Controller--D27:F0) Memory Address:Input Stream[0]: HDBAR + 8Eh Input Stream[1]: HDBAR + AEh Input Stream[2]: HDBAR + CEh Input Stream[3]: HDBAR + EEh Output Stream[0]: HDBAR + 10Eh Output Stream[1]: HDBAR + 12Eh Output Stream[2]: HDBAR + 14Eh Output Stream[3]: HDBAR + 16Eh Default Value: 0004h Bit 15:3 2:0 Size: Attribute:R/W 16 bits Description Reserved. FIFO Watermark (FIFOW) -- RO. Indicates the minimum number of bytes accumulated/free in the FIFO before the controller will start a fetch/eviction of data. The HD Audio Controller hardwires the FIFO Watermark to either 32 B or 64 B based on the number of bytes per frame for the configured input stream. 100 = 32B (Default) 101 = 64B Others = Unsupported Note: When the bit field is programmed to an unsupported size, the hardware sets itself to the default value. Software must read the bit field to test if the value is supported after setting the bit field. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 691 Intel(R) High Definition Audio Controller Registers (D27:F0) 18.2.41 ISDFIFOS--Stream Descriptor FIFO Size Register - Input Streams (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:Input Stream[0]: Input Stream[1]: Input Stream[2]: Input Stream[3]: Default Value: 0000h 18.2.42 HDBAR HDBAR HDBAR HDBAR + + + + 90h B0h D0h F0h Size:16 bits Bit Description 15:0 FIFO Size --R/W. Indicates the maximum number of bytes that could be evicted by the controller at one time. This is the maximum number of bytes that may have been received from the link but not yet DMA'd into memory, and is also the maximum possible value that the PICB count will increase by at one time. The FIFO size is calculated based on factors including the stream format programmed in SDFMT register. As the default value is zero, SW must write to the respective SDFMT register to kick of the FIFO size calculation, and read back to find out the HW allocated FIFO size. SDFIFOS--Stream Descriptor FIFO Size Register - Output Streams (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:Output Stream[0]: HDBAR + 110h Output Stream[1]: HDBAR + 130h Output Stream[2]: HDBAR + 150h Output Stream[3]: HDBAR + 170h Default Value: 0000h 692 Attribute:RO Attribute: R/W Size:16 bits Bit Description 15:0 FIFO Size -- R/W. Indicates the maximum number of bytes that could be fetched by the controller at one time. This is the maximum number of bytes that may have been DMA'd into memory but not yet transmitted on the link, and is also the maximum possible value that the PICB count will increase by at one time. The FIFO size is calculated based on factors including the stream format programmed in SDFMT register. As the default value is zero, SW must write to the respective SDFMT register to kick of the FIFO size calculation, and read back to find out the HW allocated FIFO size. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 18.2.43 SDFMT--Stream Descriptor Format Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:Input Stream[0]: HDBAR + 92h Input Stream[1]: HDBAR + B2h Input Stream[2]: HDBAR + D2h Input Stream[3]: HDBAR + F2h Output Stream[0]: HDBAR + 112h Output Stream[1]: HDBAR + 132h Output Stream[2]: HDBAR + 152h Output Stream[3]: HDBAR + 172h Attribute:R/W Default Value: 16 bits 0000h Bit Description 15 Reserved. 14 Sample Base Rate -- R/W 0 = 48 kHz 1 = 44.1 kHz 13:11 10:8 7 Size: Sample Base Rate Multiple -- R/W 000 = 48 kHz, 44.1 kHz or less 001 = x2 (96 kHz, 88.2 kHz, 32 kHz) 010 = x3 (144 kHz) 011 = x4 (192 kHz, 176.4 kHz) Others = Reserved. Sample Base Rate Devisor -- R/W. 000 = Divide by 1(48 kHz, 44.1 kHz) 001 = Divide by 2 (24 kHz, 22.05 kHz) 010 = Divide by 3 (16 kHz, 32 kHz) 011 = Divide by 4 (11.025 kHz) 100 = Divide by 5 (9.6 kHz) 101 = Divide by 6 (8 kHz) 110 = Divide by 7 111 = Divide by 8 (6 kHz) Reserved. 6:4 Bits per Sample (BITS) -- R/W. 000 =8 bits. The data will be packed in memory in 8-bit containers on 16-bit boundaries 001 =16 bits. The data will be packed in memory in 16-bit containers on 16-bit boundaries 010 = 20 bits. The data will be packed in memory in 32-bit containers on 32-bit boundaries 011 =24 bits. The data will be packed in memory in 32-bit containers on 32-bit boundaries 100 =32 bits. The data will be packed in memory in 32-bit containers on 32-bit boundaries Others = Reserved. 3:0 Number of Channels (CHAN) -- R/W. Indicates number of channels in each frame of the stream. 0000 =1 0001 =2 ........ 1111 =16 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 693 Intel(R) High Definition Audio Controller Registers (D27:F0) 18.2.44 SDBDPL--Stream Descriptor Buffer Descriptor List Pointer Lower Base Address Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:Input Stream[0]: HDBAR + 98hAttribute:R/W,RO Input Stream[1]: HDBAR + B8h Input Stream[2]: HDBAR + D8h Input Stream[3]: HDBAR + F8h Output Stream[0]: HDBAR + 118h Output Stream[1]: HDBAR + 138h Output Stream[2]: HDBAR + 158h Output Stream[3]: HDBAR + 178h Default Value: 00000000h Bit 31:7 6:0 18.2.45 Size: 32 bits Description Buffer Descriptor List Pointer Lower Base Address -- R/W. Lower address of the Buffer Descriptor List. This value should only be modified when the RUN bit is 0, or DMA transfer may be corrupted. Hardwired to 0 forcing alignment on 128-B boundaries. SDBDPU--Stream Descriptor Buffer Descriptor List Pointer Upper Base Address Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:Input Stream[0]: HDBAR + 9ChAttribute:R/W Input Stream[1]: HDBAR + BCh Input Stream[2]: HDBAR + DCh Input Stream[3]: HDBAR + FCh Output Stream[0]: HDBAR + 11Ch Output Stream[1]: HDBAR + 13Ch Output Stream[2]: HDBAR + 15Ch Output Stream[3]: HDBAR + 17Ch Default Value: 00000000h Size: 32 bits Bit Description 31:0 Buffer Descriptor List Pointer Upper Base Address -- R/W. Upper 32-bit address of the Buffer Descriptor List. This value should only be modified when the RUN bit is 0, or DMA transfer may be corrupted. 694 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SMBus Controller Registers (D31:F3) 19 SMBus Controller Registers (D31:F3) 19.1 PCI Configuration Registers (SMBus--D31:F3) Table 19-1. SMBus Controller PCI Register Address Map (SMBus--D31:F3) Offset Mnemonic 00h-01h VID 02h-03h DID 04h-05h PCICMD PCI Command 06h-07h PCISTS PCI Status 08h Default Attribute Vendor Identification 8086 RO Device Identification See register description RO 0000h R/W, RO 0280h RO See register description RO Revision Identification 09h PI Programming Interface 00h RO 0Ah SCC Sub Class Code 05h RO 0Bh BCC Base Class Code 0Ch RO 00000004h R/W 10h SMBMBAR0 Memory Base Address Register 0 (Bit 31:0) 14h SMBMBAR1 Memory Based Address Register 1 (Bit 63:32) 00000000h R/W 20h-23h SMB_BASE SMBus Base Address 00000001h R/W, RO 2Ch-2Dh SVID 2Eh-2Fh SID 3Ch INT_LN Subsystem Vendor Identification 0000h RO Subsystem Identification 0000h R/WO Interrupt Line 00h R/W See register description RO 00h R/W 3Dh INT_PN Interrupt Pin 40h HOSTC Host Configuration Note: 19.1.1 RID Register Name Registers that are not shown should be treated as Reserved.(See Section 9.2 for details.) VID--Vendor Identification Register (SMBus--D31:F3) Address: Default Value: 00h-01h 8086h Bit 15:0 Attribute: Size: RO 16 bits Description Vendor ID -- RO. This is a 16-bit value assigned to Intel Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 695 SMBus Controller Registers (D31:F3) 19.1.2 DID--Device Identification Register (SMBus--D31:F3) Address: Default Value: 19.1.3 02h-03h See bit description RO 16 bits Bit Description 15:0 Device ID -- RO. This is a 16-bit value assigned to the PCH's SMBus controller. Refer to the Intel(R) C600 Series Chipset Specification Update for the value of the Device ID Register. PCICMD--PCI Command Register (SMBus--D31:F3) Address: Default Value: 04h-05h 0000h Bit 15:11 10 696 Attribute: Size: Attributes: Size: RO, R/W 16 bits Description Reserved Interrupt Disable -- R/W. 0 = Enable 1 = Disables SMBus to assert its PIRQB# signal. 9 Fast Back to Back Enable (FBE) -- RO. Hardwired to 0. 8 SERR# Enable (SERR_EN) -- R/W. 0 = Enables SERR# generation. 1 = Disables SERR# generation. 7 Wait Cycle Control (WCC) -- RO. Hardwired to 0. 6 Parity Error Response (PER) -- R/W. 0 = Disable 1 = Sets Detected Parity Error bit (D31:F3:06, bit 15) when a parity error is detected. 5 VGA Palette Snoop (VPS) -- RO. Hardwired to 0. 4 Postable Memory Write Enable (PMWE) -- RO. Hardwired to 0. 3 Special Cycle Enable (SCE) -- RO. Hardwired to 0. 2 Bus Master Enable (BME) -- RO. Hardwired to 0. 1 Memory Space Enable (MSE) -- R/W. 0 = Disables memory mapped config space. 1 = Enables memory mapped config space. 0 I/O Space Enable (IOSE) -- R/W. 0 = Disable 1 = Enables access to the SMBus I/O space registers as defined by the Base Address Register. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SMBus Controller Registers (D31:F3) 19.1.4 PCISTS--PCI Status Register (SMBus--D31:F3) Address: Default Value: Note: 06h-07h 0280h Attributes: Size: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit Description 15 Detected Parity Error (DPE) -- R/WC. 0 = No parity error detected. 1 = Parity error detected. 14 Signaled System Error (SSE) -- R/WC. 0 = No system error detected. 1 = System error detected. 13 Received Master Abort (RMA) -- RO. Hardwired to 0. 12 Received Target Abort (RTA) -- RO. Hardwired to 0. 11 Signaled Target Abort (STA) -- RO. Hardwired to 0. 10:9 DEVSEL# Timing Status (DEVT) -- RO. This 2-bit field defines the timing for DEVSEL# assertion for positive decode. 01 = Medium timing. 8 Data Parity Error Detected (DPED) -- RO. Hardwired to 0. 7 Fast Back to Back Capable (FB2BC) -- RO. Hardwired to 1. 6 User Definable Features (UDF) -- RO. Hardwired to 0. 5 66 MHz Capable (66MHZ_CAP) -- RO. Hardwired to 0. 4 Capabilities List (CAP_LIST) -- RO. Hardwired to 0 because there are no capability list structures in this function 3 Interrupt Status (INTS) -- RO. This bit indicates that an interrupt is pending. It is independent from the state of the Interrupt Enable bit in the PCI Command register. 2:0 19.1.5 RO 16 bits Reserved RID--Revision Identification Register (SMBus--D31:F3) Offset Address: 08h Default Value: See bit description Bit 7:0 Attribute: Size: RO 8 bits Description Revision ID -- RO. Refer to the Revision ID Register. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) C600 Series Chipset Specification Update for the value of the 697 SMBus Controller Registers (D31:F3) 19.1.6 PI--Programming Interface Register (SMBus--D31:F3) Offset Address: 09h Default Value: 00h Bit 7:0 19.1.7 Reserved SCC--Sub Class Code Register (SMBus--D31:F3) Bit 7:0 RO 8 bits Sub Class Code (SCC) -- RO. 05h = SMBus serial controller BCC--Base Class Code Register (SMBus--D31:F3) Bit 7:0 Attributes: Size: RO 8 bits Description Base Class Code (BCC) -- RO. 0Ch = Serial controller. SMBMBAR0--D31_F3_SMBus Memory Base Address 0 (SMBus--D31:F3) Address Offset: 10-13h Default Value: 00000004h Bit 31:8 7:4 3 2:1 0 698 Attributes: Size: Description Address Offset: 0Bh Default Value: 0Ch 19.1.9 RO 8 bits Description Address Offset: 0Ah Default Value: 05h 19.1.8 Attribute: Size: Attributes: Size: R/W, RO 32 bits Description Base Address -- R/W. Provides the 32 byte system memory base address for the PCH SMB logic. Reserved Prefetchable (PREF) -- RO. Hardwired to 0. Indicates that SMBMBAR is not pre-fetchable. Address Range (ADDRNG) -- RO. Indicates that this SMBMBAR can be located anywhere in 64 bit address space. Hardwired to 10b. Memory Space Indicator -- RO. This read-only bit always is 0, indicating that the SMB logic is Memory mapped. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SMBus Controller Registers (D31:F3) 19.1.10 SMBMBAR1--D31_F3_SMBus Memory Base Address 1 (SMBus--D31:F3) Address Offset: 14h-17h Default Value: 00000000h Bit 31:0 19.1.11 Base Address -- R/W. Provides bits 63-32 system memory base address for the PCH SMB logic. SMB_BASE--SMBus Base Address Register (SMBus--D31:F3) Bit 31:16 15:5 4:1 0 Attribute: Size: R/W, RO 32-bits Description Reserved -- RO Base Address -- R/W. This field provides the 32-byte system I/O base address for the PCH's SMB logic. Reserved -- RO IO Space Indicator -- RO. Hardwired to 1 indicating that the SMB logic is I/O mapped. SVID--Subsystem Vendor Identification Register (SMBus--D31:F2/F4) Address Offset: 2Ch-2Dh Default Value: 0000h Lockable: No 19.1.13 R/W 32 bits Description Address Offset: 20-23h Default Value: 00000001h 19.1.12 Attributes: Size: Attribute: Size: Power Well: RO 16 bits Core Bit Description 15:0 Subsystem Vendor ID (SVID) -- RO. The SVID register, in combination with the Subsystem ID (SID) register, enables the operating system (OS) to distinguish subsystems from each other. The value returned by reads to this register is the same as that which was written by BIOS into the IDE SVID register. Note: Software can write to this register only once per core well reset. Writes should be done as a single 16-bit cycle. SID--Subsystem Identification Register (SMBus--D31:F2/F4) Address Offset: 2Eh-2Fh Default Value: 0000h Lockable: No Attribute: Size: Power Well: R/WO 16 bits Core Bit Description 15:0 Subsystem ID (SID) -- R/WO. The SID register, in combination with the SVID register, enables the operating system (OS) to distinguish subsystems from each other. The value returned by reads to this register is the same as that which was written by BIOS into the IDE SID register. Note: Software can write to this register only once per core well reset. Writes should be done as a single 16-bit cycle. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 699 SMBus Controller Registers (D31:F3) 19.1.14 INT_LN--Interrupt Line Register (SMBus--D31:F3) Address Offset: 3Ch Default Value: 00h Bit 7:0 19.1.15 Interrupt Line (INT_LN) -- R/W. This data is not used by the PCH. It is to communicate to software the interrupt line that the interrupt pin is connected to PIRQB#. INT_PN--Interrupt Pin Register (SMBus--D31:F3) Bit 7:0 Attributes: Size: RO 8 bits Description Interrupt PIN (INT_PN) -- RO. This reflects the value of D31IP.SMIP in chipset configuration space. HOSTC--Host Configuration Register (SMBus--D31:F3) Address Offset: 40h Default Value: 00h Bit 7:4 700 R/W 8 bits Description Address Offset: 3Dh Default Value: See description 19.1.16 Attributes: Size: Attribute: Size: R/W 8 bits Description Reserved 3 SSRESET - Soft SMBus Reset-- R/W. 0 = The HW will reset this bit to 0 when SMBus reset operation is completed. 1 = The SMBus state machine and logic in the PCH is reset. 2 I2C_EN -- R/W. 0 = SMBus behavior. 1 = The PCH is enabled to communicate with I2C devices. This will change the formatting of some commands. 1 SMB_SMI_EN -- R/W. 0 = SMBus interrupts will not generate an SMI#. 1 = Any source of an SMB interrupt will instead be routed to generate an SMI#. Refer to Section 5.22.6 (Interrupts / SMI#). This bit needs to be set for SMBALERT# to be enabled. 0 SMBus Host Enable (HST_EN) -- R/W. 0 = Disable the SMBus Host controller. 1 = Enable. The SMB Host controller interface is enabled to execute commands. The INTREN bit (offset SMB_BASE + 02h, bit 0) needs to be enabled for the SMB Host controller to interrupt or SMI#. Note that the SMB Host controller will not respond to any new requests until all interrupt requests have been cleared. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SMBus Controller Registers (D31:F3) 19.2 SMBus I/O and Memory Mapped I/O Registers The SMBus registers (see Table 19-2)can be accessed through I/O BAR or Memory BAR registers in PCI configuration space. The offsets are the same for both I/O and Memory Mapped I/O registers. Table 19-2. SMBus I/O and Memory Mapped I/O Register Address Map SMB_BASE + Offset Mnemonic Register Name Default Attribute 00h HST_STS Host Status 00h R/WC, RO 02h HST_CNT Host Control 00h R/W, WO Host Command 00h R/W Transmit Slave Address 00h R/W 03h HST_CMD 04h XMIT_SLVA 05h HST_D0 Host Data 0 00h R/W 06h HST_D1 Host Data 1 00h R/W 07h HOST_BLOCK_DB 08h PEC Host Block Data Byte 00h R/W Packet Error Check 00h R/W 09h RCV_SLVA Receive Slave Address 0Ah-0Bh SLV_DATA Receive Slave Data 44h R/W 0000h RO 0Ch AUX_STS Auxiliary Status 00h R/WC, RO 0Dh AUX_CTL Auxiliary Control 00h R/W 0Eh SMLINK_PIN_CTL SMLink Pin Control (TCO Compatible Mode) See register description R/W, RO 0Fh SMBus_PIN_CTL SMBus Pin Control See register description R/W, RO 10h SLV_STS Slave Status 00h R/WC 11h SLV_CMD Slave Command 00h R/W 14h NOTIFY_DADDR Notify Device Address 00h RO 16h NOTIFY_DLOW Notify Data Low Byte 00h RO 17h NOTIFY_DHIGH Notify Data High Byte 00h RO Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 701 SMBus Controller Registers (D31:F3) 19.2.1 HST_STS--Host Status Register (SMBus--D31:F3) Register Offset: SMB_BASE + 00h Default Value: 00h Attribute: Size: R/WC, RO 8-bits All status bits are set by hardware and cleared by the software writing a one to the particular bit position. Writing a 0 to any bit position has no effect. Bit Description Byte Done Status (DS) -- R/WC. 0 = Software can clear this by writing a 1 to it. 1 = Host controller received a byte (for Block Read commands) or if it has completed transmission of a byte (for Block Write commands) when the 32-byte buffer is not being used. Note that this bit will be set, even on the last byte of the transfer. This bit is not set when transmission is due to the LAN interface heartbeat. This bit has no meaning for block transfers when the 32-byte buffer is enabled. 7 702 Note: When the last byte of a block message is received, the host controller will set this bit. However, it will not immediately set the INTR bit (bit 1 in this register). When the interrupt handler clears the DS bit, the message is considered complete, and the host controller will then set the INTR bit (and generate another interrupt). Thus, for a block message of n bytes, the PCH will generate n+1 interrupts. The interrupt handler needs to be implemented to handle these cases. When not using the 32 Byte Buffer, hardware will drive the SMBCLK signal low when the DS bit is set until SW clears the bit. This includes the last byte of a transfer. Software must clear the DS bit before it can clear the BUSY bit. 6 INUSE_STS -- R/W. This bit is used as semaphore among various independent software threads that may need to use the PCH's SMBus logic, and has no other effect on hardware. 0 = After a full PCI reset, a read to this bit returns a 0. 1 = After the first read, subsequent reads will return a 1. A write of a 1 to this bit will reset the next read value to 0. Writing a 0 to this bit has no effect. Software can poll this bit until it reads a 0, and will then own the usage of the host controller. 5 SMBALERT_STS -- R/WC. 0 = Interrupt or SMI# was not generated by SMBALERT#. Software clears this bit by writing a 1 to it. 1 = The source of the interrupt or SMI# was the SMBALERT# signal. This bit is only cleared by software writing a 1 to the bit position or by RSMRST# going low. If the signal is programmed as a GPIO, then this bit will never be set. 4 FAILED -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = The source of the interrupt or SMI# was a failed bus transaction. This bit is set in response to the KILL bit being set to terminate the host transaction. 3 BUS_ERR -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = The source of the interrupt of SMI# was a transaction collision. 2 DEV_ERR -- R/WC. 0 = Software clears this bit by writing a 1 to it. The PCH will then deassert the interrupt or SMI#. 1 = The source of the interrupt or SMI# was due to one of the following: * Invalid Command Field, * Unclaimed Cycle (host initiated), * Host Device Time-out Error. 1 INTR -- R/WC. This bit can only be set by termination of a command. INTR is not dependent on the INTREN bit (offset SMB_BASE + 02h, bit 0) of the Host controller register (offset 02h). It is only dependent on the termination of the command. If the INTREN bit is not set, then the INTR bit will be set, although the interrupt will not be generated. Software can poll the INTR bit in this non-interrupt case. 0 = Software clears this bit by writing a 1 to it. The PCH then deasserts the interrupt or SMI#. 1 = The source of the interrupt or SMI# was the successful completion of its last command. 0 HOST_BUSY -- R/WC. 0 = Cleared by the PCH when the current transaction is completed. 1 = Indicates that the PCH is running a command from the host interface. No SMB registers should be accessed while this bit is set, except the BLOCK DATA BYTE Register. The BLOCK DATA BYTE Register can be accessed when this bit is set only when the SMB_CMD bits in the Host Control Register are programmed for Block command or I2C Read command. This is necessary in order to check the DONE_STS bit. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SMBus Controller Registers (D31:F3) 19.2.2 HST_CNT--Host Control Register (SMBus--D31:F3) Register Offset: SMB_BASE + 02h Default Value: 00h Note: Attribute: Size: R/W, WO 8-bits A read to this register will clear the byte pointer of the 32-byte buffer. Bit Description 7 PEC_EN. -- R/W. 0 = SMBus host controller does not perform the transaction with the PEC phase appended. 1 = Causes the host controller to perform the SMBus transaction with the Packet Error Checking phase appended. For writes, the value of the PEC byte is transferred from the PEC Register. For reads, the PEC byte is loaded in to the PEC Register. This bit must be written prior to the write in which the START bit is set. 6 START -- WO. 0 = This bit will always return 0 on reads. The HOST_BUSY bit in the Host Status register (offset 00h) can be used to identify when the PCH has finished the command. 1 = Writing a 1 to this bit initiates the command described in the SMB_CMD field. All registers should be setup prior to writing a 1 to this bit position. LAST_BYTE -- WO. This bit is used for Block Read commands. 5 4:2 1 = Software sets this bit to indicate that the next byte will be the last byte to be received for the block. This causes the PCH to send a NACK (instead of an ACK) after receiving the last byte. Note: Once the SECOND_TO_STS bit in TCO2_STS register (D31:F0, TCOBASE+6h, bit 1) is set, the LAST_BYTE bit also gets set. While the SECOND_TO_STS bit is set, the LAST_BYTE bit cannot be cleared. This prevents the PCH from running some of the SMBus commands (Block Read/Write, I2C Read, Block I2C Write). SMB_CMD -- R/W. The bit encoding below indicates which command the PCH is to perform. If enabled, the PCH will generate an interrupt or SMI# when the command has completed If the value is for a non-supported or reserved command, the PCH will set the device error (DEV_ERR) status bit (offset SMB_BASE + 00h, bit 2) and generate an interrupt when the START bit is set. The PCH will perform no command, and will not operate until DEV_ERR is cleared. 000 = Quick: The slave address and read/write value (bit 0) are stored in the transmit slave address register. 001 = Byte: This command uses the transmit slave address and command registers. Bit 0 of the slave address register determines if this is a read or write command. 010 = Byte Data: This command uses the transmit slave address, command, and DATA0 registers. Bit 0 of the slave address register determines if this is a read or write command. If it is a read, the DATA0 register will contain the read data. 011 = Word Data: This command uses the transmit slave address, command, DATA0 and DATA1 registers. Bit 0 of the slave address register determines if this is a read or write command. If it is a read, after the command completes, the DATA0 and DATA1 registers will contain the read data. 100 = Process Call: This command uses the transmit slave address, command, DATA0 and DATA1 registers. Bit 0 of the slave address register determines if this is a read or write command. After the command completes, the DATA0 and DATA1 registers will contain the read data. 101 = Block: This command uses the transmit slave address, command, DATA0 registers, and the Block Data Byte register. For block write, the count is stored in the DATA0 register and indicates how many bytes of data will be transferred. For block reads, the count is received and stored in the DATA0 register. Bit 0 of the slave address register selects if this is a read or write command. For writes, data is retrieved from the first n (where n is equal to the specified count) addresses of the SRAM array. For reads, the data is stored in the Block Data Byte register. 110 = I2C Read: This command uses the transmit slave address, command, DATA0, DATA1 registers, and the Block Data Byte register. The read data is stored in the Block Data Byte register. The PCH continues reading data until the NAK is received. 111 = Block Process: This command uses the transmit slave address, command, DATA0 and the Block Data Byte register. For block write, the count is stored in the DATA0 register and indicates how many bytes of data will be transferred. For block read, the count is received and stored in the DATA0 register. Bit 0 of the slave address register always indicate a write command. For writes, data is retrieved from the first m (where m is equal to the specified count) addresses of the SRAM array. For reads, the data is stored in the Block Data Byte register. Note: E32B bit in the Auxiliary Control register must be set for this command to work. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 703 SMBus Controller Registers (D31:F3) Bit 19.2.3 Description 1 KILL -- R/W. 0 = Normal SMBus host controller functionality. 1 = Kills the current host transaction taking place, sets the FAILED status bit, and asserts the interrupt (or SMI#). This bit, once set, must be cleared by software to allow the SMBus host controller to function normally. 0 INTREN -- R/W. 0 = Disable. 1 = Enable the generation of an interrupt or SMI# upon the completion of the command. HST_CMD--Host Command Register (SMBus--D31:F3) Register Offset: SMB_BASE + 03h Default Value: 00h Attribute: Size: Bit 7:0 19.2.4 R/W 8 bits Description This 8-bit field is transmitted by the host controller in the command field of the SMBus protocol during the execution of any command. XMIT_SLVA--Transmit Slave Address Register (SMBus--D31:F3) Register Offset: SMB_BASE + 04h Default Value: 00h Attribute: Size: R/W 8 bits This register is transmitted by the host controller in the slave address field of the SMBus protocol. Bit 7:1 0 19.2.5 Description Address -- R/W. This field provides a 7-bit address of the targeted slave. RW -- R/W. Direction of the host transfer. 0 = Write 1 = Read HST_D0--Host Data 0 Register (SMBus--D31:F3) Register Offset: SMB_BASE + 05h Default Value: 00h 19.2.6 R/W 8 bits Bit Description 7:0 Data0/Count -- R/W. This field contains the 8-bit data sent in the DATA0 field of the SMBus protocol. For block write commands, this register reflects the number of bytes to transfer. This register should be programmed to a value between 1 and 32 for block counts. A count of 0 or a count above 32 will result in unpredictable behavior. The host controller does not check or log invalid block counts. HST_D1--Host Data 1 Register (SMBus--D31:F3) Register Offset: SMB_BASE + 06h Default Value: 00h 704 Attribute: Size: Attribute: Size: R/W 8 bits Bit Description 7:0 Data1 -- R/W. This 8-bit register is transmitted in the DATA1 field of the SMBus protocol during the execution of any command. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SMBus Controller Registers (D31:F3) 19.2.7 Host_BLOCK_DB--Host Block Data Byte Register (SMBus--D31:F3) Register Offset: SMB_BASE + 07h Default Value: 00h 19.2.8 R/W 8 bits Bit Description 7:0 Block Data (BDTA) -- R/W. This is either a register, or a pointer into a 32-byte block array, depending upon whether the E32B bit is set in the Auxiliary Control register. When the E32B bit (offset SMB_BASE + 0Dh, bit 1) is cleared, this is a register containing a byte of data to be sent on a block write or read from on a block read. When the E32B bit is set, reads and writes to this register are used to access the 32-byte block data storage array. An internal index pointer is used to address the array, which is reset to 0 by reading the HCTL register (offset 02h). The index pointer then increments automatically upon each access to this register. The transfer of block data into (read) or out of (write) this storage array during an SMBus transaction always starts at index address 0. When the E2B bit is set, for writes, software will write up to 32-bytes to this register as part of the setup for the command. After the Host controller has sent the Address, Command, and Byte Count fields, it will send the bytes in the SRAM pointed to by this register. When the E2B bit is cleared for writes, software will place a single byte in this register. After the host controller has sent the address, command, and byte count fields, it will send the byte in this register. If there is more data to send, software will write the next series of bytes to the SRAM pointed to by this register and clear the DONE_STS bit. The controller will then send the next byte. During the time between the last byte being transmitted to the next byte being transmitted, the controller will insert wait-states on the interface. When the E2B bit is set for reads, after receiving the byte count into the Data0 register, the first series of data bytes go into the SRAM pointed to by this register. If the byte count has been exhausted or the 32-byte SRAM has been filled, the controller will generate an SMI# or interrupt (depending on configuration) and set the DONE_STS bit. Software will then read the data. During the time between when the last byte is read from the SRAM to when the DONE_STS bit is cleared, the controller will insert wait-states on the interface. PEC--Packet Error Check (PEC) Register (SMBus--D31:F3) Register Offset: SMB_BASE + 08h Default Value: 00h 19.2.9 Attribute: Size: Attribute: Size: R/W 8 bits Bit Description 7:0 PEC_DATA -- R/W. This 8-bit register is written with the 8-bit CRC value that is used as the SMBus PEC data prior to a write transaction. For read transactions, the PEC data is loaded from the SMBus into this register and is then read by software. Software must ensure that the INUSE_STS bit is properly maintained to avoid having this field over-written by a write transaction following a read transaction. RCV_SLVA--Receive Slave Address Register (SMBus--D31:F3) Register Offset: SMB_BASE + 09h Default Value: 44h Lockable: No Bit 7 6:0 Attribute: Size: Power Well: R/W 8 bits Resume Description Reserved SLAVE_ADDR -- R/W. This field is the slave address that the PCH decodes for read and write cycles. the default is not 0, so the SMBus Slave Interface can respond even before the processor comes up (or if the processor is dead). This register is cleared by RSMRST#, but not by PLTRST#. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 705 SMBus Controller Registers (D31:F3) 19.2.10 SLV_DATA--Receive Slave Data Register (SMBus--D31:F3) Register Offset: SMB_BASE + 0Ah-0Bh Default Value: 0000h Lockable: No Attribute: Size: Power Well: RO 16 bits Resume This register contains the 16-bit data value written by the external SMBus master. The processor can then read the value from this register. This register is reset by RSMRST#, but not PLTRST#. . Bit 15:8 7:0 19.2.11 Description Data Message Byte 1 (DATA_MSG1) -- RO. See Section 5.22.9 for a discussion of this field. Data Message Byte 0 (DATA_MSG0) -- RO. See Section 5.22.9 for a discussion of this field. AUX_STS--Auxiliary Status Register (SMBus--D31:F3) Register Offset: SMB_BASE + 0Ch Default Value: 00h Lockable: No Bit 7:2 19.2.12 R/WC, RO 8 bits Resume Description Reserved 1 SMBus TCO Mode (STCO) -- RO. This bit reflects the strap setting of TCO compatible mode vs. Advanced TCO mode. 0 = The PCH is in the compatible TCO mode. 1 = The PCH is in the advanced TCO mode. 0 CRC Error (CRCE) -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set if a received message contained a CRC error. When this bit is set, the DERR bit of the host status register will also be set. This bit will be set by the controller if a software abort occurs in the middle of the CRC portion of the cycle or an abort happens after the PCH has received the final data bit transmitted by an external slave. AUX_CTL--Auxiliary Control Register (SMBus--D31:F3) Register Offset: SMB_BASE + 0Dh Default Value: 00h Lockable: No Bit 7:2 706 Attribute: Size: Power Well: Attribute: Size: Power Well: R/W 8 bits Resume Description Reserved 1 Enable 32-Byte Buffer (E32B) -- R/W. 0 = Disable. 1 = Enable. When set, the Host Block Data register is a pointer into a 32-byte buffer, as opposed to a single register. This enables the block commands to transfer or receive up to 32-bytes before the PCH generates an interrupt. 0 Automatically Append CRC (AAC) -- R/W. 0 = The PCH will Not automatically append the CRC. 1 = The PCH will automatically append the CRC. This bit must not be changed during SMBus transactions or undetermined behavior will result. It should be programmed only once during the lifetime of the function. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SMBus Controller Registers (D31:F3) 19.2.13 SMLINK_PIN_CTL--SMLink Pin Control Register (SMBus--D31:F3) Register Offset: SMB_BASE + 0Eh Default Value: See below Note: Attribute: Size: R/W, RO 8 bits This register is in the resume well and is reset by RSMRST#. This register is only applicable in the TCO compatible mode. Bit 7:3 19.2.14 Description Reserved 2 SMLINK_CLK_CTL -- R/W. 0 = The PCH will drive the SML0CLK pin low, independent of what the other SMLink logic would otherwise indicate for the SML0CLK pin. 1 = The SML0CLK pin is not overdriven low. The other SMLink logic controls the state of the pin. (Default) 1 SML0DATA_CUR_STS -- RO. This read-only bit has a default value that is dependent on an external signal level. This pin returns the value on the SML0DATA pin. This allows software to read the current state of the pin. 0 = Low 1 = High 0 SML0CLK_CUR_STS -- RO. This read-only bit has a default value that is dependent on an external signal level. This pin returns the value on the SML0CLK pin. This allows software to read the current state of the pin. 0 = Low 1 = High SMBus_PIN_CTL--SMBus Pin Control Register (SMBus--D31:F3) Register Offset: SMB_BASE + 0Fh Default Value: See below Note: Attribute: Size: R/W, RO 8 bits This register is in the resume well and is reset by RSMRST#. Bit 7:3 Description Reserved 2 SMBCLK_CTL -- R/W. 1 = The SMBCLK pin is not overdriven low. The other SMBus logic controls the state of the pin. 0 = The PCH drives the SMBCLK pin low, independent of what the other SMB logic would otherwise indicate for the SMBCLK pin. (Default) 1 SMBDATA_CUR_STS -- RO. This read-only bit has a default value that is dependent on an external signal level. This pin returns the value on the SMBDATA pin. This allows software to read the current state of the pin. 0 = Low 1 = High 0 SMBCLK_CUR_STS -- RO. This read-only bit has a default value that is dependent on an external signal level. This pin returns the value on the SMBCLK pin. This allows software to read the current state of the pin. 0 = Low 1 = High Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 707 SMBus Controller Registers (D31:F3) 19.2.15 SLV_STS--Slave Status Register (SMBus--D31:F3) Register Offset: SMB_BASE + 10h Default Value: 00h Note: Attribute: Size: R/WC 8 bits This register is in the resume well and is reset by RSMRST#. All bits in this register are implemented in the 64 kHz clock domain. Therefore, software must poll this register until a write takes effect before assuming that a write has completed internally. Bit 7:1 0 19.2.16 Description Reserved HOST_NOTIFY_STS -- R/WC. The PCH sets this bit to a 1 when it has completely received a successful Host Notify Command on the SMBus pins. Software reads this bit to determine that the source of the interrupt or SMI# was the reception of the Host Notify Command. Software clears this bit after reading any information needed from the Notify address and data registers by writing a 1 to this bit. Note that the PCH will allow the Notify Address and Data registers to be over-written once this bit has been cleared. When this bit is 1, the PCH will NACK the first byte (host address) of any new "Host Notify" commands on the SMBus pins. Writing a 0 to this bit has no effect. SLV_CMD--Slave Command Register (SMBus--D31:F3) Register Offset: SMB_BASE + 11h Default Value: 00h Note: R/W 8 bits This register is in the resume well and is reset by RSMRST#. Bit 7:2 708 Attribute: Size: Description Reserved 2 SMBALERT_DIS -- R/W. 0 = Allows the generation of the interrupt or SMI#. 1 = Software sets this bit to block the generation of the interrupt or SMI# due to the SMBALERT# source. This bit is logically inverted and ANDed with the SMBALERT_STS bit (offset SMB_BASE + 00h, bit 5). The resulting signal is distributed to the SMI# and/or interrupt generation logic. This bit does not effect the wake logic. 1 HOST_NOTIFY_WKEN -- R/W. Software sets this bit to 1 to enable the reception of a Host Notify command as a wake event. When enabled this event is "OR'd" in with the other SMBus wake events and is reflected in the SMB_WAK_STS bit of the General Purpose Event 0 Status register. 0 = Disable 1 = Enable 0 HOST_NOTIFY_INTREN -- R/W. Software sets this bit to 1 to enable the generation of interrupt or SMI# when HOST_NOTIFY_STS (offset SMB_BASE + 10h, bit 0) is 1. This enable does not affect the setting of the HOST_NOTIFY_STS bit. When the interrupt is generated, either PIRQB# or SMI# is generated, depending on the value of the SMB_SMI_EN bit (D31:F3:40h, bit 1). If the HOST_NOTIFY_STS bit is set when this bit is written to a 1, then the interrupt (or SMI#) will be generated. The interrupt (or SMI#) is logically generated by AND'ing the STS and INTREN bits. 0 = Disable 1 = Enable Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet SMBus Controller Registers (D31:F3) 19.2.17 NOTIFY_DADDR--Notify Device Address Register (SMBus--D31:F3) Register Offset: SMB_BASE + 14h Default Value: 00h Note: 7:1 0 Description DEVICE_ADDRESS -- RO. This field contains the 7-bit device address received during the Host Notify protocol of the SMBus 2.0 Specification. Software should only consider this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMB_BASE +10, bit 0) is set to 1. Reserved NOTIFY_DLOW--Notify Data Low Byte Register (SMBus--D31:F3) Register Offset: SMB_BASE + 16h Default Value: 00h Note: Attribute: Size: 7:0 Description DATA_LOW_BYTE -- RO. This field contains the first (low) byte of data received during the Host Notify protocol of the SMBus 2.0 specification. Software should only consider this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMB_BASE +10, bit 0) is set to 1. NOTIFY_DHIGH--Notify Data High Byte Register (SMBus--D31:F3) Register Offset: SMB_BASE + 17h Default Value: 00h Note: RO 8 bits This register is in the resume well and is reset by RSMRST#. Bit 19.2.19 RO 8 bits This register is in the resume well and is reset by RSMRST#. Bit 19.2.18 Attribute: Size: Attribute: Size: RO 8 bits This register is in the resume well and is reset by RSMRST#. Bit 7:0 Description DATA_HIGH_BYTE -- RO. This field contains the second (high) byte of data received during the Host Notify protocol of the SMBus 2.0 specification. Software should only consider this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMB_BASE +10, bit 0) is set to 1. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 709 SMBus Controller Registers (D31:F3) 710 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Configuration Registers 20 PCI Express* Configuration Registers 20.1 PCI Express* Configuration Registers (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Note: Register address locations that are not shown in Table 20-1, should be treated as Reserved. Note: This section assumes the default PCI Express* Function Number-to-Root Port mapping is used. Function numbers for a given root port are assignable through the "Root Port Function Number and Hide for PCI Express* Root Ports" registers (RCBA+0404h). / Table 20-1. PCI Express* Configuration Registers Address Map (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/) (Sheet 1 of 3) Offset Mnemonic 00h-01h VID 02h-03h DID Function 0-5 Default Attribute Vendor Identification 8086h RO Device Identification See register description RO Register Name 04h-05h PCICMD PCI Command 0000h R/W, RO 06h-07h PCISTS PCI Status 0010h R/WC, RO 08h RID Revision Identification See register description RO 09h PI Programming Interface 00h RO 0Ah SCC Sub Class Code 04h RO 0Bh BCC Base Class Code 06h RO 0Ch CLS Cache Line Size 00h R/W 0Dh PLT Primary Latency Timer 00h RO 0Eh HEADTYP Header Type 81h RO 18h-1Ah BNUM Bus Number 000000h R/W 1Bh SLT 1Ch-1Dh IOBL Secondary Latency Timer I/O Base and Limit 00h RO 0000h R/W, RO 1Eh-1Fh SSTS Secondary Status Register 0000h R/WC 20h-23h MBL Memory Base and Limit 00000000h R/W 24h-27h PMBL Prefetchable Memory Base and Limit 00010001h R/W, RO 28h-2Bh PMBU32 Prefetchable Memory Base Upper 32 Bits 00000000h R/W 2Ch-2Fh PMLU32 Prefetchable Memory Limit Upper 32 Bits 00000000h R/W 34h CAPP Capabilities List Pointer 40h RO 3Ch-3Dh INTR Interrupt Information See bit description R/W, RO 3Eh-3Fh BCTRL Bridge Control Register 0000h R/W 40h-41h CLIST Capabilities List 8010 RO 42h-43h XCAP PCI Express* Capabilities 0042 R/WO, RO Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 711 PCI Express* Configuration Registers Table 20-1. PCI Express* Configuration Registers Address Map (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/) (Sheet 2 of 3) 712 Offset Mnemonic Register Name 44h-47h DCAP Device Capabilities Function 0-5 Default Attribute 00008000h RO 48h-49h DCTL Device Control 0000h R/W, RO 4Ah-4Bh DSTS Device Status 0010h R/WC, RO 4Ch-4Fh LCAP Link Capabilities See bit description R/W, RO, R/ WO 50h-51h LCTL Link Control 0000h R/W, WO, RO 52h-53h LSTS Link Status See bit description RO 54h-57h SLCAP Slot Capabilities Register 00040060h R/WO, RO 58h-59h SLCTL Slot Control 0000h R/W, RO 5Ah-5Bh SLSTS Slot Status 0000h R/WC, RO 5Ch-5Dh RCTL Root Control 0000h R/W 60h-63h RSTS Root Status 00000000h R/WC, RO 64h-67h DCAP2 Device Capabilities 2 Register 00000016h RO 68h-69h DCTL2 Device Control 2 Register 0000h R/W, RO 70h-71h LCTL2 Link Control 2 Register 0002h RO 72h-73h LSTS2 Link Status 2 Register 0000h RO 80h-81h MID Message Signaled Interrupt Identifiers 9005h RO 82h-83h MC Message Signaled Interrupt Message Control 0000h R/W, RO 84h-87h MA Message Signaled Interrupt Message Address 00000000h R/W 88h-89h MD Message Signaled Interrupt Message Data 0000h R/W 90h-91h SVCAP 94h-97h SVID A0h-A1h PMCAP A2h-A3h PMC A4-A7h PMCS D4-D7h MPC2 D8-DBh MPC DC-DFh SMSCS Subsystem Vendor Capability Subsystem Vendor Identification A00Dh RO 00000000h R/WO Power Management Capability 0001h RO PCI Power Management Capability C802h RO PCI Power Management Control and Status 00000000h R/W, RO Miscellaneous Port Configuration 2 00000000h R/W, RO Miscellaneous Port Configuration 08110000h R/W SMI/SCI Status Register 00000000h R/WC E1h RPDCGEN Rort Port Dynamic Clock Gating Enable 00h R/W E8-EBh PECR1 PCI Express* Configuration Register 1 00000020h R/W PCI Express* Configuration Register 3 00000000h R/W -- -- EC-EFh PECR3 11Ch-143h -- 104h-107h UES Uncorrectable Error Status See bit description R/WC, RO 108h-10Bh UEM Uncorrectable Error Mask 00000000h R/WO, RO 10Ch-10Fh UEV Uncorrectable Error Severity 00060011h RO 110h-113h CES Correctable Error Status 00000000h R/WC 114h-117h CEM Correctable Error Mask 00002000h R/WO Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Configuration Registers Table 20-1. PCI Express* Configuration Registers Address Map (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/) (Sheet 3 of 3) 20.1.1 Offset Mnemonic 118h-11Bh AECC Function 0-5 Default Attribute Advanced Error Capabilities and Control 00000000h RO Root Error Status 00000000h R/WC, RO Root Complex Topology Capability List 00010005h RO Register Name 130h-133h RES 180h-183h RCTCL 184h-187h ESD Element Self Description See bit description RO 190h-193h ULD Upstream Link Description 00000001h RO 198h-19Fh ULBA Upstream Link Base Address See bit description RO 318h PEETM PCI Express* Extended Test Mode Register See bit description RO VID--Vendor Identification Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 00h-01h Default Value: 8086h Attribute: Size: Bit 15:0 20.1.2 RO 16 bits Description Vendor ID -- RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h DID--Device Identification Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 02h-03h Default Value: Port 1= Bit Port 2= Bit Port 3= Bit Port 4= Bit Port 5= Bit Port 6= Bit Port 7= Bit Port 8= Bit Description Description Description Description Description Description Description Description Bit 15:0 Attribute: Size: RO 16 bits Description Device ID -- RO. This is a 16-bit value assigned to the PCH's PCI Express* controller. Refer to the Intel(R) C600 Series Chipset Specification Update for the value of the Device ID Register. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 713 PCI Express* Configuration Registers 20.1.3 PCICMD--PCI Command Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 04h-05h Default Value: 0000h Bit 15:11 10 Attribute: Size: R/W, RO 16 bits Description Reserved Interrupt Disable -- R/W. This disables pin-based INTx# interrupts on enabled Hot-Plug and power management events. This bit has no effect on MSI operation. 0 = Internal INTx# messages are generated if there is an interrupt for Hot-Plug or power management and MSI is not enabled. 1 = Internal INTx# messages will not be generated. This bit does not affect interrupt forwarding from devices connected to the root port. Assert_INTx and Deassert_INTx messages will still be forwarded to the internal interrupt controllers if this bit is set. 714 9 Fast Back to Back Enable (FBE) -- Reserved per the PCI Express* Base Specification. 8 SERR# Enable (SEE) -- R/W. 0 = Disable. 1 = Enables the root port to generate an SERR# message when PSTS.SSE is set. 7 Wait Cycle Control (WCC) -- Reserved per the PCI Express* Base Specification. 6 Parity Error Response (PER) -- R/W. 0 = Disable. 1 = Indicates that the device is capable of reporting parity errors as a master on the backbone. 5 VGA Palette Snoop (VPS) -- Reserved per the PCI Express* Base Specification. 4 Postable Memory Write Enable (PMWE) -- Reserved per the PCI Express* Base Specification. 3 Special Cycle Enable (SCE) -- Reserved per the PCI Express* Base Specification. 2 Bus Master Enable (BME) -- R/W. 0 = Disable. Memory and I/O requests received at a Root Port must be handled as Unsupported Requests 1 = Enable. Allows the root port to forward cycles onto the backbone from a PCI Express* device. Note: This bit does not affect forwarding of completions in either upstream or downstream direction nor controls forwarding of requests other than memory or I/O.PCI Express 1 Memory Space Enable (MSE) -- R/W. 0 = Disable. Memory cycles within the range specified by the memory base and limit registers are master aborted on the backbone. 1 = Enable. Allows memory cycles within the range specified by the memory base and limit registers can be forwarded to the PCI Express* device. 0 I/O Space Enable (IOSE) -- R/W. This bit controls access to the I/O space registers. 0 = Disable. I/O cycles within the range specified by the I/O base and limit registers are master aborted on the backbone. 1 = Enable. Allows I/O cycles within the range specified by the I/O base and limit registers can be forwarded to the PCI Express* device. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Configuration Registers 20.1.4 PCISTS--PCI Status Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 06h-07h Default Value: 0010h R/WC, RO 16 bits Bit Description 15 Detected Parity Error (DPE) -- R/WC. 0 = No parity error detected. 1 = Set when the root port receives a command or data from the backbone with a parity error. This is set even if PCIMD.PER (D28:F0/F1/F2/F3:04, bit 6) is not set. 14 Signaled System Error (SSE) -- R/WC. 0 = No system error signaled. 1 = Set when the root port signals a system error to the internal SERR# logic. 13 Received Master Abort (RMA) -- R/WC. 0 = Root port has not received a completion with unsupported request status from the backbone. 1 = Set when the root port receives a completion with unsupported request status from the backbone. 12 Received Target Abort (RTA) -- R/WC. 0 = Root port has not received a completion with completer abort from the backbone. 1 = Set when the root port receives a completion with completer abort from the backbone. 11 Signaled Target Abort (STA) -- R/WC. 0 = No target abort received. 1 = Set whenever the root port forwards a target abort received from the downstream device onto the backbone. 10:9 DEVSEL# Timing Status (DEV_STS) -- Reserved per the PCI Express* Base Specification. 8 Master Data Parity Error Detected (DPED) -- R/WC. 0 = No data parity error received. 1 = Set when the root port receives a completion with a data parity error on the backbone and PCIMD.PER (D28:F0/F1/F2/F3:04, bit 6) is set. 7 Fast Back to Back Capable (FB2BC) -- Reserved per the PCI Express* Base Specification. 6 Reserved 5 66 MHz Capable -- Reserved per the PCI Express* Base Specification. 4 Capabilities List -- RO. Hardwired to 1. Indicates the presence of a capabilities list. 3 Interrupt Status -- RO. Indicates status of Hot-Plug and power management interrupts on the root port that result in INTx# message generation. 0 = Interrupt is deasserted. 1 = Interrupt is asserted. This bit is not set if MSI is enabled. If MSI is not enabled, this bit is set regardless of the state of PCICMD.Interrupt Disable bit (D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7:04h:bit 10). 2:0 20.1.5 Attribute: Size: Reserved RID--Revision Identification Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Offset Address: 08h Default Value: See bit description Bit 7:0 Attribute: Size: RO 8 bits Description Revision ID -- RO. Refer to the Intel(R) C600 Series Chipset Specification Update for the value of the Revision ID Register Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 715 PCI Express* Configuration Registers 20.1.6 PI--Programming Interface Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 09h Default Value: 00h Bit 7:0 20.1.7 Attribute: Size: Description Programming Interface -- RO. 00h = No specific register level programming interface defined. SCC--Sub Class Code Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 0Ah Default Value: 04h Bit 7:0 20.1.8 Attribute: Size: Sub Class Code (SCC) -- RO. This field is determined by bit 2 of the MPC register (D28:F05:Offset D8h, bit 2). 04h = PCI-to-PCI bridge. 00h = Host Bridge. BCC--Base Class Code Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Bit 7:0 RO 8 bits Base Class Code (BCC) -- RO. 06h = Indicates the device is a bridge device. CLS--Cache Line Size Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Bit 7:0 Attribute: Size: R/W 8 bits Description Cache Line Size (CLS) -- R/W. This is read/write but contains no functionality, per the PCI Express* Base Specification. PLT--Primary Latency Timer Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 0Dh Default Value: 00h Bit 716 Attribute: Size: Description Address Offset: 0Ch Default Value: 00h 20.1.10 RO 8 bits Description Address Offset: 0Bh Default Value: 06h 20.1.9 RO 8 bits Attribute: Size: RO 8 bits Description 7:3 Latency Count. Reserved per the PCI Express* Base Specification. 2:0 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Configuration Registers 20.1.11 HEADTYP--Header Type Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 0Eh Default Value: 81h Bit 7 6:0 20.1.12 Multi-Function Device -- RO. 0 = Single-function device. 1 = Multi-function device. Configuration Layout-- RO. This field is determined by bit 2 of the MPC register (D28:F0-5:Offset D8h, bit 2). 00h = Indicates a Host Bridge. 01h = Indicates a PCI-to-PCI bridge. BNUM--Bus Number Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Bit 23:16 15:8 7:0 Attribute: Size: R/W 24 bits Description Subordinate Bus Number (SBBN) -- R/W. Indicates the highest PCI bus number below the bridge. Secondary Bus Number (SCBN) -- R/W. Indicates the bus number the port. Primary Bus Number (PBN) -- R/W. Indicates the bus number of the backbone. SLT--Secondary Latency Timer (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 1Bh Default Value: 00h Bit 7:0 20.1.14 RO 8 bits Description Address Offset: 18-1Ah Default Value: 000000h 20.1.13 Attribute: Size: Attribute: Size: RO 8 bits Description Secondary Latency Timer -- Reserved for a Root Port per the PCI Express* Base Specification. IOBL--I/O Base and Limit Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 1Ch-1Dh Default Value: 0000h Bit 15:12 11:8 Attribute: Size: R/W, RO 16 bits Description I/O Limit Address (IOLA) -- R/W. I/O Base bits corresponding to address lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to FFFh. I/O Limit Address Capability (IOLC) -- R/O. Indicates that the bridge does not support 32-bit I/ O addressing. 7:4 I/O Base Address (IOBA) -- R/W. I/O Base bits corresponding to address lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to 000h. 3:0 I/O Base Address Capability (IOBC) -- R/O. Indicates that the bridge does not support 32-bit I/ O addressing. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 717 PCI Express* Configuration Registers 20.1.15 SSTS--Secondary Status Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 1Eh-1Fh Default Value: 0000h Bit R/WC 16 bits Description 15 Detected Parity Error (DPE) -- R/WC. 0 = No error. 1 = The port received a poisoned TLP. 14 Received System Error (RSE) -- R/WC. 0 = No error. 1 = The port received an ERR_FATAL or ERR_NONFATAL message from the device. 13 Received Master Abort (RMA) -- R/WC. 0 = Unsupported Request not received. 1 = The port received a completion with "Unsupported Request" status from the device. 12 Received Target Abort (RTA) -- R/WC. 0 = Completion Abort not received. 1 = The port received a completion with "Completion Abort" status from the device. 11 Signaled Target Abort (STA) -- R/WC. 0 = Completion Abort not sent. 1 = The port generated a completion with "Completion Abort" status to the device. 10:9 Secondary DEVSEL# Timing Status (SDTS): Reserved per PCI Express* Base Specification. 8 Data Parity Error Detected (DPD) -- R/WC. 0 = Conditions below did not occur. 1 = Set when the BCTRL.PERE (D28:FO/F1/F2/F3/F4/F5:3E: bit 0) is set, and either of the following two conditions occurs: * Port receives completion marked poisoned. * Port poisons a write request to the secondary side. 7 Secondary Fast Back to Back Capable (SFBC): Reserved per PCI Express* Base Specification. 6 Reserved 5 Secondary 66 MHz Capable (SC66): Reserved per PCI Express* Base Specification. 4:0 20.1.16 Attribute: Size: Reserved MBL--Memory Base and Limit Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 20h-23h Default Value: 00000000h Attribute: Size: R/W 32 bits Accesses that are within the ranges specified in this register will be sent to the attached device if CMD.MSE (D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7:04:bit 1) is set. Accesses from the attached device that are outside the ranges specified will be forwarded to the backbone if CMD.BME (D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7:04:bit 2) is set. The comparison performed is MB AD[31:20] ML. Bit 31:20 Memory Limit (ML) -- R/W. These bits are compared with bits 31:20 of the incoming address to determine the upper 1-MB aligned value of the range. 19:16 Reserved 15:4 3:0 718 Description Memory Base (MB) -- R/W. These bits are compared with bits 31:20 of the incoming address to determine the lower 1-MB aligned value of the range. Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Configuration Registers 20.1.17 PMBL--Prefetchable Memory Base and Limit Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 24h-27h Default Value: 00010001h Attribute: Size: R/W, RO 32 bits Accesses that are within the ranges specified in this register will be sent to the device if CMD.MSE (D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7;04, bit 1) is set. Accesses from the device that are outside the ranges specified will be forwarded to the backbone if CMD.BME (D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7;04, bit 2) is set. The comparison performed is PMBU32:PMB AD[63:32]:AD[31:20] PMLU32:PML. Bit 31:20 Prefetchable Memory Limit (PML) -- R/W. These bits are compared with bits 31:20 of the incoming address to determine the upper 1-MB aligned value of the range. 19:16 64-bit Indicator (I64L) -- RO. Indicates support for 64-bit addressing 15:4 3:0 20.1.18 Description Prefetchable Memory Base (PMB) -- R/W. These bits are compared with bits 31:20 of the incoming address to determine the lower 1-MB aligned value of the range. 64-bit Indicator (I64B) -- RO. Indicates support for 64-bit addressing PMBU32--Prefetchable Memory Base Upper 32 Bits Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/ F7/F6/F7) Address Offset: 28h-2Bh Default Value: 00000000h Bit 31:0 20.1.19 Attribute: Size: R/W 32 bits Description Prefetchable Memory Base Upper Portion (PMBU) -- R/W. Upper 32-bits of the prefetchable address base. PMLU32--Prefetchable Memory Limit Upper 32 Bits Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/ F7/F6/F7) Address Offset: 2Ch-2Fh Default Value: 00000000h Bit 31:0 Attribute: Size: R/W 32 bits Description Prefetchable Memory Limit Upper Portion (PMLU) -- R/W. Upper 32-bits of the prefetchable address limit. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 719 PCI Express* Configuration Registers 20.1.20 CAPP--Capabilities List Pointer Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 34h Default Value: 40h Attribute: Size: Bit 7:0 20.1.21 R0 8 bits Description Capabilities Pointer (PTR) -- RO. Indicates that the pointer for the first entry in the capabilities list is at 40h in configuration space. INTR--Interrupt Information Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 3Ch-3Dh Default Value: See bit description Function Level Reset: No (Bits 7:0 only) Bit Attribute: Size: R/W, RO 16 bits Description Interrupt Pin (IPIN) -- RO. Indicates the interrupt pin driven by the root port. At reset, this register takes on the following values, which reflect the reset state of the D28IP register in chipset config space: 15:8 Note: 7:0 720 Port Reset Value 1 D28IP.P1IP 2 D28IP.P2IP 3 D28IP.P3IP 4 D28IP.P4IP 5 D28IP.P5IP 6 D28IP.P6IP 7 D28IP.P7IP 8 D28IP.P8IP The value that is programmed into D28IP is always reflected in this register. Interrupt Line (ILINE) -- R/W. Default = 00h. Software written value to indicate which interrupt line (vector) the interrupt is connected to. No hardware action is taken on this register. These bits are not reset by FLR. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Configuration Registers 20.1.22 BCTRL--Bridge Control Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) Address Offset: 3Eh-3Fh Default Value: 0000h Bit 15:12 20.1.23 Attribute: Size: R/W 16 bits Description Reserved 11 Discard Timer SERR# Enable (DTSE): Reserved per PCI Express* Base Specification, Revision 1.0a 10 Discard Timer Status (DTS): Reserved per PCI Express* Base Specification, Revision 1.0a. 9 Secondary Discard Timer (SDT): Reserved per PCI Express* Base Specification, Revision 1.0a. 8 Primary Discard Timer (PDT): Reserved per PCI Express* Base Specification, Revision 1.0a. 7 Fast Back to Back Enable (FBE): Reserved per PCI Express* Base Specification, Revision 1.0a. 6 Secondary Bus Reset (SBR) -- R/W. Triggers a hot reset on the PCI Express port. 5 Master Abort Mode (MAM): Reserved per Express specification. 4 VGA 16-Bit Decode (V16) -- R/W. 0 = VGA range is enabled. 1 = The I/O aliases of the VGA range (see BCTRL:VE definition below), are not enabled, and only the base I/O ranges can be decoded 3 VGA Enable (VE)-- R/W. 0 = The ranges below will not be claimed off the backbone by the root port. 1 = The following ranges will be claimed off the backbone by the root port: * Memory ranges A0000h-BFFFFh * I/O ranges 3B0h - 3BBh and 3C0h - 3DFh, and all aliases of bits 15:10 in any combination of 1s 2 ISA Enable (IE) -- R/W. This bit only applies to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of PCI I/O space. 0 = The root port will not block any forwarding from the backbone as described below. 1 = The root port will block any forwarding from the backbone to the device of I/O transactions addressing the last 768 bytes in each 1-KB block (offsets 100h to 3FFh). 1 SERR# Enable (SE) -- R/W. 0 = The messages described below are not forwarded to the backbone. 1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages received are forwarded to the backbone. 0 Parity Error Response Enable (PERE) -- R/W. When set, 0 = Poisoned write TLPs and completions indicating poisoned TLPs will not set the SSTS.DPD (D28:F0/F1/F2/F3/F4/F5/F6/F7:1E, bit 8). 1 = Poisoned write TLPs and completions indicating poisoned TLPs will set the SSTS.DPD (D28:F0/ F1/F2/F3/F4/F5/F6/F7:1E, bit 8). CLIST--Capabilities List Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 40-41h Default Value: 8010h Bit 15:8 7:0 Attribute: Size: RO 16 bits Description Next Capability (NEXT) -- RO. Value of 80h indicates the location of the next pointer. Capability ID (CID) -- RO. Indicates this is a PCI Express* capability. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 721 PCI Express* Configuration Registers 20.1.24 XCAP--PCI Express* Capabilities Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 42h-43h Default Value: 0042h Bit 15:14 13:9 8 20.1.25 Reserved Interrupt Message Number (IMN) -- RO. The PCH does not have multiple MSI interrupt numbers. Slot Implemented (SI) -- R/WO. Indicates whether the root port is connected to a slot. Slot support is platform specific. BIOS programs this field, and it is maintained until a platform reset. 7:4 Device / Port Type (DT) -- RO. Indicates this is a PCI Express* root port. 3:0 Capability Version (CV) -- RO. Indicates PCI Express* 2.0. DCAP--Device Capabilities Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Bit 31:28 Attribute: Size: Reserved Captured Slot Power Limit Scale (CSPS) -- RO. Not supported. 25:18 Captured Slot Power Limit Value (CSPV) -- RO. Not supported. 17:16 Reserved 14:12 RO 32 bits Description 27:26 15 Role Based Error Reporting (RBER) -- RO. Indicates that this device implements the functionality defined in the Error Reporting ECN as required by the PCI Express* 2.0 Specification. Reserved 11:9 Endpoint L1 Acceptable Latency (E1AL) -- RO. This field is reserved with a setting of 000b for devices other than Endpoints, per the PCI Express* 2.0 Specification. 8:6 Endpoint L0s Acceptable Latency (E0AL) -- RO. This field is reserved with a setting of 000b for devices other than Endpoints, per the PCI Express 2.0 Specification. 5 Extended Tag Field Supported (ETFS) -- RO. Indicates that 8-bit tag fields are supported. 4:3 Phantom Functions Supported (PFS) -- RO. No phantom functions supported. 2:0 Max Payload Size Supported (MPS) -- RO. Indicates the maximum payload size supported is 128B. DCTL--Device Control Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 48h-49h Default Value: 0000h Bit 15 14:12 722 R/WO, RO 16 bits Description Address Offset: 44h-47h Default Value: 00008000h 20.1.26 Attribute: Size: Attribute: Size: R/W, RO 16 bits Description Reserved Max Read Request Size (MRRS) -- RO. Hardwired to 0. 11 Enable No Snoop (ENS) -- RO. Not supported. The root port will never issue non-snoop requests. 10 Aux Power PM Enable (APME) -- R/W. The OS will set this bit to 1 if the device connected has detected aux power. It has no effect on the root port otherwise. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Configuration Registers Bit 9 Phantom Functions Enable (PFE) -- RO. Not supported. 8 Extended Tag Field Enable (ETFE) -- RO. Not supported. 7:5 20.1.27 Description Max Payload Size (MPS) -- R/W. The root port only supports 128-B payloads, regardless of the programming of this field. 4 Enable Relaxed Ordering (ERO) -- RO. Not supported. 3 Unsupported Request Reporting Enable (URE) -- R/W. 0 = The root port will ignore unsupported request errors. 1 = Allows signaling ERR_NONFATAL, ERR_FATAL, or ERR_COR to the Root Control register when detecting an unmasked Unsupported Request (UR). An ERR_COR is signaled when a unmasked Advisory Non-Fatal UR is received. An ERR_FATAL, ERR_or NONFATAL, is sent to the Root Control Register when an uncorrectable non-Advisory UR is received with the severity set by the Uncorrectable Error Severity register. 2 Fatal Error Reporting Enable (FEE) -- R/W. 0 = The root port will ignore fatal errors. 1 = Enables signaling of ERR_FATAL to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting. 1 Non-Fatal Error Reporting Enable (NFE) -- R/W. 0 = The root port will ignore non-fatal errors. 1 = Enables signaling of ERR_NONFATAL to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting. 0 Correctable Error Reporting Enable (CEE) -- R/W. 0 = The root port will ignore correctable errors. 1 = Enables signaling of ERR_CORR to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting. DSTS--Device Status Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 4Ah-4Bh Default Value: 0010h Bit 15:6 Attribute: Size: R/WC, RO 16 bits Description Reserved 5 Transactions Pending (TDP) -- RO. This bit has no meaning for the root port since only one transaction may be pending to the PCH, so a read of this bit cannot occur until it has already returned to 0. 4 AUX Power Detected (APD) -- RO. The root port contains AUX power for wakeup. 3 Unsupported Request Detected (URD) -- R/WC. Indicates an unsupported request was detected. 2 Fatal Error Detected (FED) -- R/WC. Indicates a fatal error was detected. 0 = Fatal has not occurred. 1 = A fatal error occurred from a data link protocol error, link training error, buffer overflow, or malformed TLP. 1 Non-Fatal Error Detected (NFED) -- R/WC. Indicates a non-fatal error was detected. 0 = Non-fatal has not occurred. 1 = A non-fatal error occurred from a poisoned TLP, unexpected completions, unsupported requests, completer abort, or completer timeout. 0 Correctable Error Detected (CED) -- R/WC. Indicates a correctable error was detected. 0 = Correctable has not occurred. 1 = The port received an internal correctable error from receiver errors / framing errors, TLP CRC error, DLLP CRC error, replay num rollover, replay timeout. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 723 PCI Express* Configuration Registers 20.1.28 LCAP--Link Capabilities Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 4Ch-4Fh Default Value: See bit description Bit Attribute: Size: R/WO, RO 32 bits Description Port Number (PN) -- RO. Indicates the port number for the root port. This value is different for each implemented port: 31:24 23:21 20 Function Port # Value of PN Field D28:F0 1 01h D28:F1 2 02h D28:F2 3 03h D28:F3 4 04h D28:F4 5 05h D28:F5 6 06h D28:F6 7 07h D28:F7 8 08h Reserved Link Active Reporting Capable (LARC) -- RO. Hardwired to 1 to indicate that this port supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine. 19:18 Reserved 17:15 L1 Exit Latency (EL1) -- RO. 000b = Less than 1 us 001b = 1 us to less than 2 us 010b = 2 us to less than 4 us 011b = 4 us to less than 8 us 100b = 8 us to less than 16 us 101b = 16 us to less than 32 us 110b = 32 us to 64 us 111b = more than 64 us L0s Exit Latency (EL0) -- R/WO. Indicates as exit latency based upon common-clock configuration. 14:12 Note: 724 LCLT.CCC Value of EL0 (these bits) 0 MPC.UCEL (D28:F0/F1/F2/F3:D8h:bits20:18) 1 MPC.CCEL (D28:F0/F1/F2/F3:D8h:bits17:15) LCLT.CCC is at D28:F0/F1/F2/F3/F4/F5/F6/F7:50h:bit 6 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Configuration Registers Bit Description Active State Link PM Support (APMS) -- R/WO. Indicates what level of active state link power management is supported on the root port. 11:10 Bits Definition 00b Neither L0s nor L1 are supported 01b L0s Entry Supported 10b L1 Entry Supported 11b Both L0s and L1 Entry Supported Maximum Link Width (MLW) -- RO. For the root ports, several values can be taken, based upon the value of the chipset config register field RPC.PC1 (Chipset Config Registers:Offset 0224h:bits1:0) for Ports 1-4 and RPC.PC2 (Chipset Config Registers:Offset 0224h:bits1:0) for Ports 5 and 6. Value of MLW Field 9:4 3:0 Port # RPC.PC1=00b RPC.PC1=11b 1 01h 04h 2 01h 01h 3 01h 01h 4 01h 01h Port # RPC.PC2=00b RPC.PC2=11b 5 01h 04h 6 01h 01h 7 01h 01h 8 01h 01h Maximum Link Speed (MLS) -- RO. 0001b = indicates the link speed is 2.5 Gb/s 0010b = 5.0 Gb/s and 2.5Gb/s link speeds supported These bits report a value of 0001b if Gen2 disable bit 14 is set in the MPC register, else the value reported is 0010b. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 725 PCI Express* Configuration Registers 20.1.29 LCTL--Link Control Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 50h-51h Default Value: 0000h Bit 15:10 R/W, RO 16 bits Description Reserved 9 Hardware Autonomous Width Disable - RO. Hardware never attempts to change the link width except when attempting to correct unreliable Link operation. 8 Reserved 7 Extended Synch (ES) -- R/W. 0 = Extended synch disabled. 1 = Forces extended transmission of FTS ordered sets in FTS and extra TS2 at exit from L1 prior to entering L0. 6 Common Clock Configuration (CCC) -- R/W. 0 = The PCH and device are not using a common reference clock. 1 = The PCH and device are operating with a distributed common reference clock. 5 Retrain Link (RL) -- R/W. 0 = This bit always returns 0 when read. 1 = The root port will train its downstream link. Note: Software uses LSTS.LT (D28:F0/F1/F2/F3/F4/F5/F6/F7:52, bit 11) to check the status of training. Note: It is permitted to write 1b to this bit while simultaneously writing modified values to other fields in this register. If the LTSSM is not already in Recovery or Configuration, the resulting Link training must use the modified values. If the LTSSM is already in Recovery or Configuration, the modified values are not required to affect the Link training that is already in progress. 4 Link Disable (LD) -- R/W. 0 = Link enabled. 1 = The root port will disable the link. 3 Read Completion Boundary Control (RCBC) -- RO. Indicates the read completion boundary is 64 bytes. 2 Reserved 1:0 726 Attribute: Size: Active State Link PM Control (APMC) -- R/W. Indicates whether the root port should enter L0s or L1 or both. Bits Definition 00 Disabled 01 L0s Entry Enabled 10 L1 Entry Enabled 11 L0s and L1 Entry Enabled Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Configuration Registers 20.1.30 LSTS--Link Status Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 52h-53h Default Value: See bit description Bit 15:14 Attribute: Size: RO 16 bits Description Reserved 13 Data Link Layer Active (DLLA) -- RO. Default value is 0b. 0 = Data Link Control and Management State Machine is not in the DL_Active state 1 = Data Link Control and Management State Machine is in the DL_Active state 12 Slot Clock Configuration (SCC) -- RO. Set to 1b to indicate that the PCH uses the same reference clock as on the platform and does not generate its own clock. 11 Link Training (LT) -- RO. Default value is 0b. 0 = Link training completed. 1 = Link training is occurring. 10 Link Training Error (LTE) -- RO. Not supported. Set value is 0b. Negotiated Link Width (NLW) -- RO. This field indicates the negotiated width of the given PCI Express* link. The contents of this NLW field is undefined if the link has not successfully trained. 9:4 Note: 3:0 Port # Possible Values 1 000001b, 000010b, 000100b 2 000001b 3 000001b, 000010b 4 000001b 5 000001b, 000010b, 000100b 6 000001b 7 000001b, 000010b 8 000001b 000001b = x1 link width, 000010b =x2 linkwidth, 000100b = x4 linkwidth Link Speed (LS) -- RO. This field indicates the negotiated Link speed of the given PCI Express* link. 0001h = Link is 2.5 Gb/s. 0010h = Link is 5.0 Gb/s Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 727 PCI Express* Configuration Registers 20.1.31 SLCAP--Slot Capabilities Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 54h-57h Default Value: 00040060h Description 31:19 Physical Slot Number (PSN) -- R/WO. This is a value that is unique to the slot number. BIOS sets this field and it remains set until a platform reset. 18:17 Reserved. 16:15 Slot Power Limit Scale (SLS) -- R/WO. Specifies the scale used for the slot power limit value. BIOS sets this field and it remains set until a platform reset. Slot Power Limit Value (SLV) -- R/WO. Specifies the upper limit (in conjunction with SLS value), on the upper limit on power supplied by the slot. The two values together indicate the amount of power in watts allowed for the slot. BIOS sets this field and it remains set until a platform reset. 6 Hot Plug Capable (HPC) -- R/WO. 1b = Indicates that Hot-Plug is supported. 5 Hot Plug Surprise (HPS) -- R/WO. 1b = Indicates the device may be removed from the slot without prior notification. 4 Power Indicator Present (PIP) -- RO. 0b = Indicates that a power indicator LED is not present for this slot. 3 Attention Indicator Present (AIP) -- RO. 0b = Indicates that an attention indicator LED is not present for this slot. 2 MRL Sensor Present (MSP) -- RO. 0b = Indicates that an MRL sensor is not present. 1 Power Controller Present (PCP) -- RO. 0b = Indicates that a power controller is not implemented for this slot. 0 Attention Button Present (ABP) -- RO. 0b = Indicates that an attention button is not implemented for this slot. SLCTL--Slot Control Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 58h-59h Default Value: 0000h Bit 15:13 12 Attribute: Size: R/W, RO 16 bits Description Reserved Link Active Changed Enable (LACE) -- R/W. When set, this field enables generation of a hot plug interrupt when the Data Link Layer Link Active field (D28:F0/F1/F2/F3/F4/F5/F6/F7:52h:bit 13) is changed. 11 Reserved 10 Power Controller Control (PCC) -- RO.This bit has no meaning for module based Hot-Plug. 9:6 Reserved 5 Hot-Plug Interrupt Enable (HPE) -- R/W. 0 = Hot-plug interrupts based on Hot-Plug events is disabled. 1 = Enables generation of a Hot-Plug interrupt on enabled hot-plug events. 4 Reserved 3 Presence Detect Changed Enable (PDE) -- R/W. 0 = Hot-plug interrupts based on presence detect logic changes is disabled. 1 = Enables the generation of a hot-plug interrupt or wake message when the presence detect logic changes state. 2:0 728 R/WO, RO 32 bits Bit 14:7 20.1.32 Attribute: Size: Reserved. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Configuration Registers 20.1.33 SLSTS--Slot Status Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 5Ah-5Bh Default Value: 0000h Bit 15:9 Attribute: Size: R/WC, RO 16 bits Description Reserved 8 Link Active State Changed (LASC) -- R/WC. 1 = This bit is set when the value reported in Data Link Layer Link Active field of the Link Status register (D28:F0/F1/F2/F3/F4/F5/F6/F7:52h:bit 13) is changed. In response to a Data Link Layer State Changed event, software must read Data Link Layer Link Active field of the Link Status register to determine if the link is active before initiating configuration cycles to the hot plugged device. 7 Reserved 6 Presence Detect State (PDS) -- RO. If XCAP.SI (D28:F0/F1/F2/F3/F4/F5/F6/F7:42h:bit 8) is set (indicating that this root port spawns a slot), then this bit: 0 = Indicates the slot is empty. 1 = Indicates the slot has a device connected. Otherwise, if XCAP.SI is cleared, this bit is always set (1). 5 MRL Sensor State (MS) -- Reserved as the MRL sensor is not implemented. 4 Reserved 3 Presence Detect Changed (PDC) -- R/WC. 0 = No change in the PDS bit. 1 = The PDS bit changed states. 2 MRL Sensor Changed (MSC) -- Reserved as the MRL sensor is not implemented. 1 Power Fault Detected (PFD) -- Reserved as a power controller is not implemented. 0 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 729 PCI Express* Configuration Registers 20.1.34 RCTL--Root Control Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 5Ch-5Dh Default Value: 0000h Bit 15:4 20.1.35 R/W 16 bits Description Reserved 3 PME Interrupt Enable (PIE) -- R/W. 0 = Interrupt generation disabled. 1 = Interrupt generation enabled when PCISTS.Inerrupt Status (D28:F0/F1/F2/F3/F4/F5/F6/ F7:60h, bit 16) is in a set state (either due to a 0 to 1 transition, or due to this bit being set with RSTS.IS already set). 2 System Error on Fatal Error Enable (SFE) -- R/W. 0 = An SERR# will not be generated. 1 = An SERR# will be generated, assuming CMD.SEE (D28:F0/F1/F2/F3/F4/F5/F6/F7:04, bit 8) is set, if a fatal error is reported by any of the devices in the hierarchy of this root port, including fatal errors in this root port. 1 System Error on Non-Fatal Error Enable (SNE) -- R/W. 0 = An SERR# will not be generated. 1 = An SERR# will be generated, assuming CMD.SEE (D28:F0/F1/F2/F3/F4/F5/F6/F7:04, bit 8) is set, if a non-fatal error is reported by any of the devices in the hierarchy of this root port, including non-fatal errors in this root port. 0 System Error on Correctable Error Enable (SCE) -- R/W. 0 = An SERR# will not be generated. 1 = An SERR# will be generated, assuming CMD.SEE (D28:F0/F1/F2/F3/F4/F5/F6/F7:04, bit 8) if a correctable error is reported by any of the devices in the hierarchy of this root port, including correctable errors in this root port. RSTS--Root Status Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 60h-63h Default Value: 00000000h Bit 31:18 Attribute: Size: R/WC, RO 32 bits Description Reserved 17 PME Pending (PP) -- RO. 0 = When the original PME is cleared by software, it will be set again, the requestor ID will be updated, and this bit will be cleared. 1 = Indicates another PME is pending when the PME status bit is set. 16 PME Status (PS) -- R/WC. 0 = PME was not asserted. 1 = Indicates that PME was asserted by the requestor ID in RID. Subsequent PMEs are kept pending until this bit is cleared. 15:0 730 Attribute: Size: PME Requestor ID (RID) -- RO. Indicates the PCI requestor ID of the last PME requestor. Valid only when PS is set. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Configuration Registers 20.1.36 DCAP2--Device Capabilities 2 Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 64h-67h Default Value: 00000016h Bit 31:5 4 3:0 20.1.37 Attribute: Size: RO 32 bits Description Reserved Completion Timeout Disable Supported (CTDS) -- RO. A value of 1b indicates support for the Completion Timeout Disable mechanism. Completion Timeout Ranges Supported (CTRS) - RO. This field indicates device support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value. This field is hardwired to support 10 ms to 250 ms and 250 ms to 4 s. DCTL2--Device Control 2 Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 68h-69h Default Value: 0000h Bit 15:5 4 3:0 Attribute: Size: RO, R/W 16 bits Description Reserved Completion Timeout Disable (CTD) -- R/W. When set to 1b, this bit disables the Completion Timeout mechanism. If there are outstanding requests when the bit is cleared, it is permitted but not required for hardware to apply the completion timeout mechanism to the outstanding requests. If this is done, it is permitted to base the start time for each request on either the time this bit was cleared or the time each request was issued. Completion Timeout Value (CTV) -- R/W. This field allows system software to modify the Completion Timeout value. 0000b = Default range: 40-50 ms (specification range 50 us to 50 ms) 0101b = 40-50 ms (specification range is 16 ms to 55 ms) 0110b = 160-170 ms (specification range is 65 ms to 210 ms) 1001b = 400-500 ms (specification range is 260 ms to 900 ms) 1010b = 1.6-1.7 s (specification range is 1 s to 3.5 s) All other values are Reserved. Note: Software is permitted to change the value in this field at any time. For requests already pending when the Completion Timeout Value is changed, hardware is permitted to use either the new or the old value for the outstanding requests, and is permitted to base the start time for each request either on when this value was changed or on when each request w as issued. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 731 PCI Express* Configuration Registers 20.1.38 LCTL2--Link Control 2 Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 70h-71h Default Value: 0002h Bit 15:13 12 11:5 4 3:0 20.1.39 Reserved Compliance De-Emphasis (CD) -- R/W. This bit sets the de-emphasis level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. Encodings: 0 = 6 dB 1 = 3.5 dB When the Link is operating at 2.5 GT/s, the setting of this bit has no effect. The default value of this bit is 0b. This bit is intended for debug, compliance testing purposes. System firmware and software are allowed to modify this bit only during debug or compliance testing. Reserved Enter Compliance (EC) -- R/W. Software is permitted to force a Link to enter Compliance mode at the speed indicated in the Target Link Speed field by setting this bit to 1b in both components on a Link and then initiating a hot reset on the Link. Target Link Speed (TLS)-- RO. This field sets an upper limit on Link operational speed by restricting the values advertised by the upstream component in its training sequences. 0001b = 2.5 GT/s Target Link Speed 0010b = 5.0 GT/s and 2.5 GT/s Target Link Speeds All other values reserved LSTS2--Link Status 2 Register (PCI Express*-- D28:F0/F1/F2/F3/F4/F5/F6/F7) Bit 15:1 0 Attribute: Size: RO 16 bits Description Reserved Current De-emphasis Level (CDL) -- RO. When the Link is operating at 5 GT/s speed, this bit reflects the level of de-emphasis. Encodings: 0 = 6 dB 1 = 3.5 dB The value in this bit is undefined when the Link is operating at 2.5 GT/s speed. MID--Message Signaled Interrupt Identifiers Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 80h-81h Default Value: 9005h Bit 15:8 7:0 732 RO 16 bits Description Address Offset: 72h-73h Default Value: 0000h 20.1.40 Attribute: Size: Attribute: Size: RO 16 bits Description Next Pointer (NEXT) -- RO. Indicates the location of the next pointer in the list. Capability ID (CID) -- RO. Capabilities ID indicates MSI. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Configuration Registers 20.1.41 MC--Message Signaled Interrupt Message Control Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 82-83h Default Value: 0000h Bit 15:8 7 Attribute: Size: R/W, RO 16 bits Description Reserved 64 Bit Address Capable (C64) -- RO. Capable of generating a 32-bit message only. 6:4 Multiple Message Enable (MME) -- R/W. These bits are R/W for software compatibility, but only one message is ever sent by the root port. 3:1 Multiple Message Capable (MMC) -- RO. Only one message is required. MSI Enable (MSIE) -- R/W. 0 = MSI is disabled. 1 = MSI is enabled and traditional interrupt pins are not used to generate interrupts. 0 Note: 20.1.42 CMD.BME (D28:F0/F1/F2/F3/F4/F5/F6/F7:04h:bit 2) must be set for an MSI to be generated. If CMD.BME is cleared, and this bit is set, no interrupts (not even pin based) are generated. MA--Message Signaled Interrupt Message Address Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 84h-87h Default Value: 00000000h Bit 31:2 1:0 20.1.43 R/W 32 bits Description Address (ADDR) -- R/W. Lower 32 bits of the system specified message address, always DW aligned. Reserved MD--Message Signaled Interrupt Message Data Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 88h-89h Default Value: 0000h Bit 15:0 20.1.44 Attribute: Size: Attribute: Size: R/W 16 bits Description Data (DATA) -- R/W. This 16-bit field is programmed by system software if MSI is enabled. Its content is driven onto the lower word (PCI AD[15:0]) during the data phase of the MSI memory write transaction. SVCAP--Subsystem Vendor Capability Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 90h-91h Default Value: A00Dh Bit 15:8 7:0 Attribute: Size: RO 16 bits Description Next Capability (NEXT) -- RO. Indicates the location of the next pointer in the list. Capability Identifier (CID) -- RO. Value of 0Dh indicates this is a PCI bridge subsystem vendor capability. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 733 PCI Express* Configuration Registers 20.1.45 SVID--Subsystem Vendor Identification Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 94h-97h Default Value: 00000000h Bit 20.1.46 31:16 Subsystem Identifier (SID) -- R/WO. Indicates the subsystem as identified by the vendor. This field is write once and is locked down until a bridge reset occurs (not the PCI bus reset). 15:0 Subsystem Vendor Identifier (SVID) -- R/WO. Indicates the manufacturer of the subsystem. This field is write once and is locked down until a bridge reset occurs (not the PCI bus reset). PMCAP--Power Management Capability Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Bit 15:8 7:0 Attribute: Size: RO 16 bits Description Next Capability (NEXT) -- RO. Indicates this is the last item in the list. Capability Identifier (CID) -- RO. Value of 01h indicates this is a PCI power management capability. PMC--PCI Power Management Capabilities Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: A2h-A3h Default Value: C802h Attribute: Size: RO 16 bits Bit Description 15:11 PME_Support (PMES) -- RO. Indicates PME# is supported for states D0, D3HOT and D3COLD. The root port does not generate PME#, but reporting that it does is necessary for some legacy operating systems to enable PME# in devices connected behind this root port. 10 9 8:6 D2_Support (D2S) -- RO. The D2 state is not supported. D1_Support (D1S) -- RO The D1 state is not supported. Aux_Current (AC) -- RO. Reports 375 mA maximum suspend well current required when in the D3COLD state. 5 Device Specific Initialization (DSI) -- RO. 1 = Indicates that no device-specific initialization is required. 4 Reserved 3 PME Clock (PMEC) -- RO. 1 = Indicates that PCI clock is not required to generate PME#. 2:0 734 R/WO 32 bits Description Address Offset: A0h-A1h Default Value: 0001h 20.1.47 Attribute: Size: Version (VS) -- RO. Indicates support for Revision 1.1 of the PCI Power Management Specification. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Configuration Registers 20.1.48 PMCS--PCI Power Management Control and Status Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: A4h-A7h Default Value: 00000000h Bit 31:24 R/W, RO 32 bits Description Reserved 23 Bus Power / Clock Control Enable (BPCE) -- Reserved per PCI Express* Base Specification, Revision 1.0a. 22 B2/B3 Support (B23S) -- Reserved per PCI Express* Base Specification, Revision 1.0a. 21:16 15 14:9 8 7:2 1:0 Reserved PME Status (PMES) -- RO. 1 = Indicates a PME was received on the downstream link. Reserved PME Enable (PMEE) -- R/W. 1 = Indicates PME is enabled. The root port takes no action on this bit, but it must be R/W for some legacy operating systems to enable PME# on devices connected to this root port. This bit is sticky and resides in the resume well. The reset for this bit is RSMRST# which is not asserted during a warm reset. Reserved Power State (PS) -- R/W. This field is used both to determine the current power state of the root port and to set a new power state. The values are: 00 = D0 state 11 = D3HOT state Note: 20.1.49 Attribute: Size: When in the D3HOT state, the controller's configuration space is available, but the I/O and memory spaces are not. Type 1 configuration cycles are also not accepted. Interrupts are not required to be blocked as software will disable interrupts prior to placing the port into D3HOT. If software attempts to write a `10' or `01' to these bits, the write will be ignored. MPC2--Miscellaneous Port Configuration Register 2 (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: D4h-D7h Default Value: 00000000h Bit 31:5 4 Attribute: Size: R/W, RO 32 bits Description Reserved ASPM Control Override Enable (ASPMCOEN) -- R/W. 1 = Root port will use the values in the ASPM Control Override registers 0 = Root port will use the ASPM Registers in the Link Control register. Notes: This register allows BIOS to control the root port ASPM settings instead of the OS. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 735 PCI Express* Configuration Registers Bit 3:2 20.1.50 Description ASPM Control Override (ASPMO) -- R/W. Provides BIOS control of whether root port should enter L0s or L1 or both. 00 = Disabled 01 = L0s Entry Enabled 10 = L1 Entry Enabled 11 = L0s and L1 Entry Enabled. 1 EOI Forwarding Disable (EOIFD) -- R/W. When set, EOI messages are not claimed on the backbone by this port an will not be forwarded across the PCIe link. 0 = EOI forwarding is enabled. 1 = EOI forwarding is disabled. 0 L1 Completion Timeout Mode (LICTM) -- R/W. 0 = PCI Express* Specification Compliant. Completion timeout is disabled during software initiated L1, and enabled during ASPM initiate L1. 1 = Completion timeout is enabled during L1, regardless of how L1 entry was initiated. MPC--Miscellaneous Port Configuration Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: D8h-DBh Default Value: 08110000h Bit Attribute: Size: R/W, RO 32 bits Description 31 Power Management SCI Enable (PMCE) -- R/W. 0 = SCI generation based on a power management event is disabled. 1 = Enables the root port to generate SCI whenever a power management event is detected. 30 Hot-Plug SCI Enable (HPCE) -- R/W. 0 = SCI generation based on a Hot-Plug event is disabled. 1 = Enables the root port to generate SCI whenever a hot-plug event is detected. Link Hold Off (LHO) -- R/W. 29 1 = Port will not take any TLP. This is used during loopback mode to fill up the downstream queue. 736 28 Address Translator Enable (ATE) -- R/W. This bit is used to enable address translation using the AT bits in this register during loopback mode. 0 = Disable 1 = Enable 27 Reserved 26 Invalid Receive Bus Number Check Enable (IRBNCE) -- R/W. When set, the receive transaction layer will signal an error if the bus number of a Memory request does not fall within the range between SCBN and SBBN. If this check is enabled and the request is a memory write, it is treated as an Unsupported Request. If this check is enabled and the request is a non-posted memory read request, the request is considered a Malformed TLP and a fatal error. Messages, I/O, Config, and Completions are never checked for valid bus number. 25 Invalid Receive Range Check Enable (IRRCE) -- R/W. When set, the receive transaction layer will treat the TLP as an Unsupported Request error if the address range of a Memory request does not outside the range between prefetchable and non-prefetchable base and limit. Messages, I/O, Configuration, and Completions are never checked for valid address ranges. 24 BME Receive Check Enable (BMERCE) -- R/W. When set, the receive transaction layer will treat the TLP as an Unsupported Request error if a memory read or write request is received and the Bus Master Enable bit is not set. Messages, IO, Config, and Completions are never checked for BME. 23 Reserved 22 Detect Override (FORCEDET) -- R/W. 0 = Normal operation. Detected output from AFE is sampled for presence detection. 1 = Override mode. Ignores AFE detect output and link training proceeds as if a device were detected. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Configuration Registers Bit 21 Description Flow Control During L1 Entry (FCDL1E) -- R/W. 0 = No flow control update DLLPs sent during L1 Ack transmission. 1 = Flow control update DLLPs sent during L1 Ack transmission as required to meet the 30 s periodic flow control update. 20:18 Unique Clock Exit Latency (UCEL) -- R/W. This value represents the L0s Exit Latency for uniqueclock configurations (LCTL.CCC = 0) (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 50h:bit 6). It defaults to 512 ns to less than 1 s, but may be overridden by BIOS. 17:15 Common Clock Exit Latency (CCEL) -- R/W. This value represents the L0s Exit Latency for common-clock configurations (LCTL.CCC = 1) (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 50h:bit 6). It defaults to 128 ns to less than 256 ns, but may be overridden by BIOS. 14:8 Reserved Port I/OxApic Enable (PAE) -- R/W. 0 = Hole is disabled. 1 = A range is opened through the bridge for the following memory addresses: Port # Address 1 FEC1_0000h - FEC1_7FFFh 2 FEC1_8000h - FEC1_FFFFh 3 FEC2_0000h - FEC2_7FFFh 4 FEC2_8000h - FEC2_FFFFh 5 FEC3_0000h - FEC3_7FFFh 6 FEC3_8000h - FEC3_FFFFh 7 FEC4_0000h - FEC4_7FFFh 8 FEC4_8000h - FEC4_FFFFh 7 6:3 Reserved 2 Bridge Type (BT) -- RO. This register can be used to modify the Base Class and Header Type fields from the default P2P bridge to a Host Bridge. Having the root port appear as a Host Bridge is useful in some server configurations. 0 = The root port bridge type is a P2P Bridge, Header Sub-Class = 04h, and Header Type = Type 1. 1 = The root port bridge type is a P2P Bridge, Header Sub-Class = 00h, and Header Type = Type 0. 1 Hot Plug SMI Enable (HPME) -- R/W. 0 = SMI generation based on a Hot-Plug event is disabled. 1 = Enables the root port to generate SMI whenever a Hot-Plug event is detected. 0 Power Management SMI Enable (PMME) -- R/W. 0 = SMI generation based on a power management event is disabled. 1 = Enables the root port to generate SMI whenever a power management event is detected. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 737 PCI Express* Configuration Registers 20.1.51 SMSCS--SMI/SCI Status Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: DCh-DFh Default Value: 00000000h Bit Attribute: Size: R/WC 32 bits Description Power Management SCI Status (PMCS) -- R/WC. 31 1 = PME control logic needs to generate an interrupt, and this interrupt has been routed to generate an SCI. Hot-Plug SCI Status (HPCS) -- R/WC. 30 29:5 1 = Hot-Plug controller needs to generate an interrupt, and has this interrupt been routed to generate an SCI. Reserved Hot-Plug Link Active State Changed SMI Status (HPLAS) -- R/WC. 4 1 = SLSTS.LASC (D28:F0/F1/F2/F3/F4/F5/F6/F7:5A, bit 8) transitioned from 0-to-1, and MPC.HPME (D28:F0/F1/F2/F3/F4/F5/F6/F7:D8, bit 1) is set. When this bit is set, an SMI# will be generated. Hot-Plug Command Completed SMI Status (HPCCM) -- R/WC. 3 1 = SLSTS.CC (D28:F0/F1/F2/F3/F4/F5/F6/F7:5A, bit 4) transitioned from 0-to-1, and MPC.HPME (D28:F0/F1/F2/F3/F4/F5/F6/F7:D8, bit 1) is set. When this bit is set, an SMI# will be generated. Hot-Plug Attention Button SMI Status (HPABM) -- R/WC. 2 1 = SLSTS.ABP (D28:F0/F1/F2/F3/F4/F5/F6/F7:5A, bit 0) transitioned from 0-to-1, and MPC.HPME (D28:F0/F1/F2/F3/F4/F5/F6/F7:D8, bit 1) is set. When this bit is set, an SMI# will be generated. Hot-Plug Presence Detect SMI Status (HPPDM) -- R/WC. 1 1 = SLSTS.PDC (D28:F0/F1/F2/F3/F4/F5/F6/F7:5A, bit 3) transitioned from 0-to-1, and MPC.HPME (D28:F0/F1/F2/F3/F4/F5/F6/F7:D8, bit 1) is set. When this bit is set, an SMI# will be generated. Power Management SMI Status (PMMS) -- R/WC. 0 738 1 = RSTS.PS (D28:F0/F1/F2/F3/F4/F5/F6/F7:60, bit 16) transitioned from 0-to-1, and MPC.PMME (D28:F0/F1/F2/F3/F4/F5/F6/F7:D8, bit 1) is set. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Configuration Registers 20.1.52 RPDCGEN--Root Port Dynamic Clock Gating Enable (PCI Express-D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: E1h Default Value: 00h Bits 7:4 20.1.53 R/W 8-bits Description Reserved. RO 3 Shared Resource Dynamic Link Clock Gating Enable (SRDLCGEN) -- R/W. 0 = Disables dynamic clock gating of the shared resource link clock domain. 1 = Enables dynamic clock gating on the root port shared resource link clock domain. Only the value from Port 1 is used for ports 1-4. Only the value from Port 5 is used for ports 5-8. 2 Shared Resource Dynamic Backbone Clock Gate Enable (SRDBCGEN) -- R/W. 0 = Disables dynamic clock gating of the shared resource backbone clock domain. 1 = Enables dynamic clock gating on the root port shared resource backbone clock domain. Only the value from Port 1 is used for ports 1-4. Only the value from Port 5 is used for ports 5-8. 1 Root Port Dynamic Link Clock Gate Enable (RPDLCGEN) -- R/W. 0 = Disables dynamic clock gating of the root port link clock domain. 1 = Enables dynamic clock gating on the root port link clock domain. 0 Root Port Dynamic Backbone Clock Gate Enable (RPDBCGEN) -- R/W. 0 = Disables dynamic clock gating of the root port backbone clock domain. 1 = Enables dynamic clock gating on the root port backbone clock domain. PECR1--PCI Express* Configuration Register 1 (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: E8h-EBh Default Value: 00000020h Bit 31:2 20.1.54 Attribute: Size: Attribute: Size: R/W 32 bits Description Reserved 1 PECR1 Field 2 -- R/W. BIOS may set this bit to 1. 0 Reserved. PECR3--PCI Express* Configuration Register 3 (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: ECh-EFh Default Value: 00000000h Bit 31:2 Attribute: Size: R/W 32 bits Description Reserved 1 Subtractive Decode Compatibility Device ID (SDCDID) -- R/W. 0 = This function reports the device Device ID value assigned to the PCI Express* Root Ports listed in .the Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Specification Update 1 = This function reports a Device ID of 244Eh. If subtractive decode (SDE) is enabled, having this bit as '0' allows the function to present a Device ID that is recognized by the OS. 0 Subtractive Decode Enable (SDE) -- R/W. 0 = Subtractive decode is disabled this function and will only claim transactions positively. 1 = This port will subtractively forward transactions across the PCIe link downstream memory and IO transactions that are not positively claimed any internal device or bridge. Software must ensure that only one PCH device is enabled for Subtractive decode at a time. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 739 PCI Express* Configuration Registers 20.1.55 UES--Uncorrectable Error Status Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 104h-107h Attribute: R/WC, RO Default Value: 00000000000x0xxx0x0x0000000x0000bSize:32 bits This register maintains its state through a platform reset. It loses its state upon suspend. Bit 31:21 20 Reserved Unsupported Request Error Status (URE) -- R/WC. Indicates an unsupported request was received. 19 ECRC Error Status (EE) -- RO. ECRC is not supported. 18 Malformed TLP Status (MT) -- R/WC. Indicates a malformed TLP was received. 17 Receiver Overflow Status (RO) -- R/WC. Indicates a receiver overflow occurred. 16 Unexpected Completion Status (UC) -- R/WC. Indicates an unexpected completion was received. 15 Completion Abort Status (CA) -- R/WC. Indicates a completer abort was received. 14 Completion Timeout Status (CT) -- R/WC. Indicates a completion timed out. This bit is set if Completion Timeout is enabled and a completion is not returned within the time specified by the Completion TImeout Value 13 Flow Control Protocol Error Status (FCPE) -- RO. Flow Control Protocol Errors not supported. 12 Poisoned TLP Status (PT) -- R/WC. Indicates a poisoned TLP was received. 11:5 4 3:1 0 740 Description Reserved Data Link Protocol Error Status (DLPE) -- R/WC. Indicates a data link protocol error occurred. Reserved Training Error Status (TE) -- RO. Training Errors not supported. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Configuration Registers 20.1.56 UEM--Uncorrectable Error Mask (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 108h-10Bh Default Value: 00000000h Attribute: Size: R/WO, RO 32 bits When set, the corresponding error in the UES register is masked, and the logged error will cause no action. When cleared, the corresponding error is enabled. Bit 31:21 Description Reserved 20 Unsupported Request Error Mask (URE) -- R/WO. 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is masked. 19 ECRC Error Mask (EE) -- RO. ECRC is not supported. 18 Malformed TLP Mask (MT) -- R/WO. 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is masked. 17 Receiver Overflow Mask (RO) -- R/WO. 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is masked. 16 Unexpected Completion Mask (UC) -- R/WO. 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is masked. 15 Completion Abort Mask (CA) -- R/WO. 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is masked. 14 Completion Timeout Mask (CT) -- R/WO. 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is masked. 13 Flow Control Protocol Error Mask (FCPE) -- RO. Flow Control Protocol Errors not supported. 12 Poisoned TLP Mask (PT) -- R/WO. 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is masked. 11:5 4 3:1 0 Reserved Data Link Protocol Error Mask (DLPE) -- R/WO. 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is masked. Reserved Training Error Mask (TE) -- RO. Training Errors not supported Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 741 PCI Express* Configuration Registers 20.1.57 UEV -- Uncorrectable Error Severity (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 10Ch-10Fh Default Value: 00060011h Attribute: Size: Bit 31:21 Description Reserved 20 Unsupported Request Error Severity (URE) -- R/W. 0 = Error considered non-fatal. (Default) 1 = Error is fatal. 19 ECRC Error Severity (EE) -- RO. ECRC is not supported. 18 Malformed TLP Severity (MT) -- R/W. 0 = Error considered non-fatal. 1 = Error is fatal. (Default) 17 Receiver Overflow Severity (RO) -- R/W. 0 = Error considered non-fatal. 1 = Error is fatal. (Default) 16 Reserved 15 Completion Abort Severity (CA) -- R/W. 0 = Error considered non-fatal. (Default) 1 = Error is fatal. 14 Reserved 13 Flow Control Protocol Error Severity (FCPE) -- RO. Flow Control Protocol Errors not supported. 12 Poisoned TLP Severity (PT) -- R/W. 0 = Error considered non-fatal. (Default) 1 = Error is fatal. 11:5 4 3:1 0 20.1.58 Reserved Data Link Protocol Error Severity (DLPE) -- R/W. 0 = Error considered non-fatal. 1 = Error is fatal. (Default) Reserved Training Error Severity (TE) -- R/W. TE is not supported. CES -- Correctable Error Status Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 110h-113h Default Value: 00000000h Bit 31:14 Attribute: Size: R/WC 32 bits Description Reserved 13 Advisory Non-Fatal Error Status (ANFES) -- R/WC. 0 = Advisory Non-Fatal Error did not occur. 1 = Advisory Non-Fatal Error did occur. 12 Replay Timer Timeout Status (RTT) -- R/WC. Indicates the replay timer timed out. 11:9 742 RO, R/W 32 bits Reserved 8 Replay Number Rollover Status (RNR) -- R/WC. Indicates the replay number rolled over. 7 Bad DLLP Status (BD) -- R/WC. Indicates a bad DLLP was received. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Configuration Registers Bit 6 5:1 0 20.1.59 Description Bad TLP Status (BT) -- R/WC. Indicates a bad TLP was received. Reserved Receiver Error Status (RE) -- R/WC. Indicates a receiver error occurred. CEM -- Correctable Error Mask Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 114h-117h Default Value: 00002000h Attribute: Size: R/WO 32 bits When set, the corresponding error in the CES register is masked, and the logged error will cause no action. When cleared, the corresponding error is enabled. Bit 31:14 13 12 11:9 Reserved Advisory Non-Fatal Error Mask (ANFEM) -- R/WO. 0 = Does not mask Advisory Non-Fatal errors. 1 = Masks Advisory Non-Fatal errors from (a) signaling ERR_COR to the device control register and (b) updating the Uncorrectable Error Status register. This register is set by default to enable compatibility with software that does not comprehend RoleBased Error Reporting. Note: The correctable error detected bit in device status register is set whenever the Advisory Non-Fatal error is detected, independent of this mask bit. Replay Timer Timeout Mask (RTT) -- R/WO. Mask for replay timer timeout. Reserved 8 Replay Number Rollover Mask (RNR) -- R/WO. Mask for replay number rollover. 7 Bad DLLP Mask (BD) -- R/WO. Mask for bad DLLP reception. 6 Bad TLP Mask (BT) -- R/WO. Mask for bad TLP reception. 5:1 0 20.1.60 Description Reserved Receiver Error Mask (RE) -- R/WO. Mask for receiver errors. AECC -- Advanced Error Capabilities and Control Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 118h-11Bh Default Value: 00000000h Bit 31:9 Attribute: Size: Description Reserved 8 ECRC Check Enable (ECE) -- RO. ECRC is not supported. 7 ECRC Check Capable (ECC) -- RO. ECRC is not supported. 6 ECRC Generation Enable (EGE) -- RO. ECRC is not supported. 5 4:0 RO 32 bits ECRC Generation Capable (EGC) -- RO. ECRC is not supported. First Error Pointer (FEP) -- RO. Identifies the bit position of the last error reported in the Uncorrectable Error Status Register. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 743 PCI Express* Configuration Registers 20.1.61 RES -- Root Error Status Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 130h-133h Default Value: 00000000h Bit 31:27 26:7 20.1.62 Attribute: Size: R/WC, RO 32 bits Description Advanced Error Interrupt Message Number (AEMN) -- RO. There is only one error interrupt allocated. Reserved 6 Fatal Error Messages Received (FEMR) -- RO. Set when one or more Fatal Uncorrectable Error Messages have been received. 5 Non-Fatal Error Messages Received (NFEMR)-- RO. Set when one or more Non-Fatal Uncorrectable error messages have been received 4 First Uncorrectable Fatal (FUF)-- RO. Set when the first Uncorrectable Error message received is for a fatal error. 3 Multiple ERR_FATAL/NONFATAL Received (MENR) -- RO. For the PCH, only one error will be captured. 2 ERR_FATAL/NONFATAL Received (ENR) -- R/WC. 0 = No error message received. 1 = Either a fatal or a non-fatal error message is received. 1 Multiple ERR_COR Received (MCR) -- RO. For the PCH, only one error will be captured. 0 ERR_COR Received (CR) -- R/WC. 0 = No error message received. 1 = A correctable error message is received. PEETM -- PCI Express* Extended Test Mode Register (PCI Express*--D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: 324h-327h Default Value: See Description Bit 31:5 4 Attribute: Size: RO 32 bits Description Reserved Lane Reversal (LR) -- RO. This register reads the setting of the PCIELR1 soft strap for port 1 and the PCIELR2 soft strap for port 5. 0 = No Lane reversal (default). 1 = PCI Express* lanes 0-3 (register in port 1) or lanes 4-7 (register in port 5) are reversed. Notes: 1. The port configuration straps must be set such that Port 1 or Port 5 is configured as a x4 port using lanes 0-3, or 4-7 when Lane Reversal is enabled. x2 lane reversal is not supported. 2. This register is only valid on port 1 (for ports 1-4) or port 5 (for ports 5-8). 3 Reserved 2 Scrambler Bypass Mode (BAU) -- R/W. 0 = Normal operation. Scrambler and descrambler are used. 1 = Bypasses the data scrambler in the transmit direction and the data de-scrambler in the receive direction. Note: This functionality intended for debug/testing only. Note: If bypassing scrambler with the PCH root port 1 in x4 configuration, each PCH root port must have this bit set. 1:0 Reserved 744 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet High Precision Event Timer Registers 21 High Precision Event Timer Registers The timer registers are memory-mapped in a non-indexed scheme. This allows the processor to directly access each register without having to use an index register. The timer register space is 1024 bytes. The registers are generally aligned on 64-bit boundaries to simplify implementation with IA64 processors. There are four possible memory address ranges beginning at 1) FED0_0000h, 2) FED0_1000h, 3) FED0_2000h, 4) FED0_3000h. The choice of address range will be selected by configuration bits in the High Precision Timer Configuration Register (Chipset Config Registers:Offset 3404h). Behavioral Rules: 1. Software must not attempt to read or write across register boundaries. For example, a 32-bit access should be to offset x0h, x4h, x8h, or xCh. 32-bit accesses should not be to 01h, 02h, 03h, 05h, 06h, 07h, 09h, 0Ah, 0Bh, 0Dh, 0Eh, or 0Fh. Any accesses to these offsets will result in an unexpected behavior, and may result in a master abort. However, these accesses should not result in system hangs. 64-bit accesses can only be to x0h and must not cross 64-bit boundaries. 2. Software should not write to read-only registers. 3. Software should not expect any particular or consistent value when reading reserved registers or bits. 21.1 Memory Mapped Registers Table 21-1. Memory-Mapped Registers (Sheet 1 of 2) Offset Mnemonic 000-007h GCAP_ID 008-00Fh -- 010-017h GEN_CONF 018-01Fh -- 020-027h GINTR_STA 028-0EFh -- 0F0-0F7h MAIN_CNT 0F8-0FFh -- 100-107h TIM0_CONF 108-10Fh TIM0_COMP 110-11Fh -- Register General Capabilities and Identification Reserved General Configuration Reserved General Interrupt Status Reserved Main Counter Value Reserved Default Type 0429B17F80 86A201h RO -- -- 00000000 00000000h R/W -- -- 00000000 00000000h R/WC, R/W -- -- N/A R/W -- -- Timer 0 Configuration and Capabilities N/A R/W, RO Timer 0 Comparator Value N/A R/W -- -- Reserved 120-127h TIM1_CONF Timer 1 Configuration and Capabilities N/A R/W, RO 128-12Fh TIM1_COMP Timer 1 Comparator Value N/A R/W 130-13Fh -- -- -- 140-147h TIM2_CONF Timer 2 Configuration and Capabilities Reserved N/A R/W, RO 148-14Fh TIM2_COMP Timer 2 Comparator Value N/A R/W Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 745 High Precision Event Timer Registers Table 21-1. Memory-Mapped Registers (Sheet 2 of 2) Offset Mnemonic 150-15Fh -- 160-167h TIM3_CONG Register Default Reserved Timer 3 Configuration and Capabilities Type -- -- N/A R/W, RO 168-16Fh TIM3_COMP Timer 3 Comparator Value N/A R/W 180-187h TIM4_CONG Timer 4 Configuration and Capabilities N/A R/W, RO Timer 4 Comparator Value N/A R/W -- -- 188-18Fh TIM4_COMP 190-19Fh -- 1A0-1A7h TIM5_CONG Timer 5 Configuration and Capabilities N/A R/W, RO 1A8-1AFh TIM5_COMP Timer 5 Comparator Value N/A R/W 1B0-1BFh -- 1C0-1C7h TIM6_CONG Reserved Reserved -- -- Timer 6 Configuration and Capabilities N/A R/W, RO Timer 6 Comparator Value N/A R/W -- -- 1C8-1CFh TIM6_COMP 1D0-1DFh -- 1E0-1E7h TIM7_CONG Timer 7 Configuration and Capabilities N/A R/W, RO 1E8-1EFh TIM7_COMP Timer 7 Comparator Value N/A R/W Reserved 1F0-19Fh -- Reserved -- -- 200-3FFh -- Reserved -- -- Notes: 1. Reads to reserved registers or bits will return a value of 0. 2. Software must not attempt locks to the memory-mapped I/O ranges for High Precision Event Timers. If attempted, the lock is not honored, which means potential deadlock conditions may occur. 21.1.1 GCAP_ID--General Capabilities and Identification Register Address Offset: 00h Default Value: 0429B17F8086A201h 746 Attribute: Size: RO 64 bits Bit Description 63:32 Main Counter Tick Period (COUNTER_CLK_PER_CAP) -- RO. This field indicates the period at which the counter increments in femptoseconds (10^-15 seconds). This will return 0429B17F when read. This indicates a period of 69841279 fs (69.841279 ns). 31:16 Vendor ID Capability (VENDOR_ID_CAP) -- RO. This is a 16-bit value assigned to Intel. 15 Legacy Replacement Rout Capable (LEG_RT_CAP) -- RO. Hardwired to 1. Legacy Replacement Interrupt Rout option is supported. 14 Reserved. This bit returns 0 when read. 13 Counter Size Capability (COUNT_SIZE_CAP) -- RO. Hardwired to 1. Counter is 64-bit wide. 12:8 Number of Timer Capability (NUM_TIM_CAP) -- RO. This field indicates the number of timers in this block. 07h = Eight timers. 7:0 Revision Identification (REV_ID) -- RO. This indicates which revision of the function is implemented. Default value will be 01h. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet High Precision Event Timer Registers 21.1.2 GEN_CONF--General Configuration Register Address Offset: 010h Default Value: 00000000 00000000h Bit 63:2 1 0 R/W 64 bits Description Reserved. These bits return 0 when read. Legacy Replacement Rout (LEG_RT_CNF) -- R/W. If the ENABLE_CNF bit and the LEG_RT_CNF bit are both set, then the interrupts will be routed as follows: * Timer 0 is routed to IRQ0 in 8259 or IRQ2 in the I/O APIC * Timer 1 is routed to IRQ8 in 8259 or IRQ8 in the I/O APIC * Timer 2-n is routed as per the routing in the timer n config registers. * If the Legacy Replacement Rout bit is set, the individual routing bits for Timers 0 and 1 (APIC) will have no impact. * If the Legacy Replacement Rout bit is not set, the individual routing bits for each of the timers are used. * This bit will default to 0. BIOS can set it to 1 to enable the legacy replacement routing, or 0 to disable the legacy replacement routing. Overall Enable (ENABLE_CNF) -- R/W. This bit must be set to enable any of the timers to generate interrupts. If this bit is 0, then the main counter will halt (will not increment) and no interrupts will be caused by any of these timers. For level-triggered interrupts, if an interrupt is pending when the ENABLE_CNF bit is changed from 1 to 0, the interrupt status indications (in the various Txx_INT_STS bits) will not be cleared. Software must write to the Txx_INT_STS bits to clear the interrupts. Note: 21.1.3 Attribute: Size: This bit will default to 0. BIOS can set it to 1 or 0. GINTR_STA--General Interrupt Status Register Address Offset: 020h Default Value: 00000000 00000000h Attribute: Size: R/W, R/WC 64 bits . Bit 63:8 Description Reserved. These bits will return 0 when read. 7 Timer 7Interrupt Active (T07_INT_STS) -- R/WC. Same functionality as Timer 0. 6 Timer 6Interrupt Active (T06_INT_STS) -- R/WC. Same functionality as Timer 0. 5 Timer 5Interrupt Active (T05_INT_STS) -- R/WC. Same functionality as Timer 0. 4 Timer 4Interrupt Active (T04_INT_STS) -- R/WC. Same functionality as Timer 0. 3 Timer 3Interrupt Active (T03_INT_STS) -- R/WC. Same functionality as Timer 0. 2 Timer 2 Interrupt Active (T02_INT_STS) -- R/WC. Same functionality as Timer 0. 1 Timer 1 Interrupt Active (T01_INT_STS) -- R/WC. Same functionality as Timer 0. 0 Timer 0 Interrupt Active (T00_INT_STS) -- R/WC. The functionality of this bit depends on whether the edge or level-triggered mode is used for this timer. (default = 0) If set to level-triggered mode: This bit will be set by hardware if the corresponding timer interrupt is active. Once the bit is set, it can be cleared by software writing a 1 to the same bit position. Writes of 0 to this bit will have no effect. If set to edge-triggered mode: This bit should be ignored by software. Software should always write 0 to this bit. Note: Defaults to 0. In edge triggered mode, this bit will always read as 0 and writes will have no effect. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 747 High Precision Event Timer Registers 21.1.4 MAIN_CNT--Main Counter Value Register Address Offset: 0F0h Default Value: N/A Attribute: Size: R/W 64 bits . Bit Description Counter Value (COUNTER_VAL[63:0]) -- R/W. Reads return the current value of the counter. Writes load the new value to the counter. 63:0 21.1.5 Notes: 1. Writes to this register should only be done while the counter is halted. 2. Reads to this register return the current value of the main counter. 3. 32-bit counters will always return 0 for the upper 32-bits of this register. 4. If 32-bit software attempts to read a 64-bit counter, it should first halt the counter. Since this delays the interrupts for all of the timers, this should be done only if the consequences are understood. It is strongly recommended that 32-bit software only operate the timer in 32-bit mode. 5. Reads to this register are monotonic. No two consecutive reads return the same value. The second of two reads always returns a larger value (unless the timer has rolled over to 0). TIMn_CONF--Timer n Configuration and Capabilities Register Address Offset: Timer Timer Timer Timer Timer Timer Timer Timer Default Value: N/A Note: 0: 1: 2: 3: 4: 5: 6: 7: 100-107h, 120-127h, 140-147h, 160-167h, 180-187h, 1A0-1A7h, 1C0-1C7h, 1E0-1E7h, RO, R/W Size: 64 bit The letter n can be 0, 1, 2, 3, 4, 5, 6, or 7 referring to Timer 0, 1, 2, 3, 4, 5, 6, or 7. Bit 63:56 55:52, 43 51:45, 42:16 15 748 Attribute: Description Reserved. These bits will return 0 when read. Timer Interrupt Rout Capability (TIMERn_INT_ROUT_CAP) -- RO. Timer 0, 1:Bits 52, 53, 54, and 55 in this field (corresponding to IRQ 20, 21, 22, and 23) have a value of 1. Writes will have no effect. Timer 2: Bits 43, 52, 53, 54, and 55 in this field (corresponding to IRQ 11, 20, 21, 22, and 23) have a value of 1. Writes will have no effect. Timer 3: Bits 44, 52, 53, 54, and 55 in this field (corresponding to IRQ 11, 20, 21, 22, and 23) have a value of 1. Writes will have no effect. Timer 4, 5, 6, 7 This field is always 0 as interrupts from these timers can only be delivered using direct processor interrupt messages. Note: If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared with any other devices to ensure the proper operation of HPET #2. Note: If IRQ 12 is used for HPET #3, software should ensure IRQ 12 is not shared with any other devices to ensure the proper operation of HPET #3. Reserved. These bits return 0 when read. Timer n Processor Message Interrupt Delivery (Tn_PROCMSG_INT_DEL_CAP) -- RO. This bit is always read as `1', since the PCH HPET implementation supports the direct processor interrupt delivery. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet High Precision Event Timer Registers Bit Description 14 Timer n Processor Message Interrupt Enable (Tn_PROCMSG_EN_CNF) -- R/W / RO. If the Tn_PROCMSG_INT_DEL_CAP bit is set for this timer, then the software can set the Tn_PROCMSG_EN_CNF bit to force the interrupts to be delivered directly as processor messages, rather than using the 8259 or I/O (x) APIC. In this case, the Tn_INT_ROUT_CNF field in this register will be ignored. The Tn_PROCMSG_ROUT register will be used instead. Timer 0, 1, 2, 3 Specific: This bit is a read/write bit. Timer 4, 5, 6, 7 Specific: This bit is always Read Only `1' as interrupt from these timers can only be delivered using direct processor interrupt messages. 13:9 Timer n Interrupt Rout (Tn_INT_ROUT_CNF) -- R/W / RO. This 5-bit field indicates the routing for the interrupt to the 8259 or I/O (x) APIC. Software writes to this field to select which interrupt in the 8259 or I/O (x) will be used for this timer's interrupt. If the value is not supported by this particular timer, then the value read back will not match what is written. The software must only write valid values. Timer 4, 5, 6, 7: This field is Read-only and reads will return 0. Notes: 1. If the interrupt is handled using the 8259, only interrupts 0-15 are applicable and valid. Software must not program any value other than 0-15 in this field. 2. If the Legacy Replacement Rout bit is set, then Timers 0 and 1 will have a different routing, and this bit field has no effect for those two timers. 3. Timer 0,1: Software is responsible to make sure it programs a valid value (20, 21, 22, or 23) for this field. The PCH logic does not check the validity of the value written. 4. Timer 2: Software is responsible to make sure it programs a valid value (11, 20, 21, 22, or 23) for this field. The PCH logic does not check the validity of the value written. 5. Timer 3: Software is responsible to make sure it programs a valid value (12, 20, 21, 22, or 23) for this field. The PCH logic does not check the validity of the value written. 6. Timers 4, 5, 6, 7: This field is always Read Only 0 as interrupts from these timers can only be delivered using direct processor interrupt messages. 8 Timer n 32-bit Mode (TIMERn_32MODE_CNF) -- R/W or RO. Software can set this bit to force a 64-bit timer to behave as a 32-bit timer. Timer 0:Bit is read/write (default to 0). 0 = 64 bit; 1 = 32 bit Timers 1, 2, 3, 4, 5, 6, 7:Hardwired to 0. Writes have no effect (since these seven timers are 32-bits). Note: When this bit is set to `1', the hardware counter will do a 32-bit operation on comparator match and rollovers, thus the upper 32-bit of the Timer 0 Comparator Value register is ignored. The upper 32-bit of the main counter is not involved in any rollover from lower 32-bit of the main counter and becomes all zeros. 7 Reserved. This bit returns 0 when read. 6 Timer n Value Set (TIMERn_VAL_SET_CNF) -- R/W. Software uses this bit only for Timer 0 if it has been set to periodic mode. By writing this bit to a 1, the software is then allowed to directly set the timer's accumulator. Software does not have to write this bit back to 1 (it automatically clears). Software should not write a 1 to this bit position if the timer is set to non-periodic mode. Note: This bit will return 0 when read. Writes will only have an effect for Timer 0 if it is set to periodic mode. Writes will have no effect for Timers 1, 2, 3, 4, 5, 6, 7. 5 Timer n Size (TIMERn_SIZE_CAP) -- RO. This read only field indicates the size of the timer. Timer 0:Value is 1 (64-bits). Timers 1, 2, 3, 4, 5, 6, 7.:Value is 0 (32-bits). 4 Periodic Interrupt Capable (TIMERn_PER_INT_CAP) -- RO. If this bit is 1, the hardware supports a periodic mode for this timer's interrupt. Timer 0: Hardwired to 1 (supports the periodic interrupt). Timers 1, 2, 3, 4, 5, 6, 7.: Hardwired to 0 (does not support periodic interrupt). 3 Timer n Type (TIMERn_TYPE_CNF) -- R/W or RO. Timer 0:Bit is read/write. 0 = Disable timer to generate periodic interrupt; 1 = Enable timer to generate a periodic interrupt. Timers 1, 2, 3, 4, 5, 6, 7.: Hardwired to 0. Writes have no affect. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 749 High Precision Event Timer Registers Bit Description 2 Timer n Interrupt Enable (TIMERn_INT_ENB_CNF) -- R/W. This bit must be set to enable timer n to cause an interrupt when it times out. 0 = Disable (Default). The timer can still count and generate appropriate status bits, but will not cause an interrupt. 1 = Enable. 1 Timer Interrupt Type (TIMERn_INT_TYPE_CNF) -- R/W. 0 = The timer interrupt is edge triggered. This means that an edge-type interrupt is generated. If another interrupt occurs, another edge will be generated. 1 = The timer interrupt is level triggered. This means that a level-triggered interrupt is generated. The interrupt will be held active until it is cleared by writing to the bit in the General Interrupt Status Register. If another interrupt occurs before the interrupt is cleared, the interrupt will remain active. Timer 4, 5, 6, 7: This bit is Read-Only, and will return 0 when read 0 Reserved. These bits will return 0 when read. Note: 21.1.6 Reads or writes to unimplemented timers should not be attempted. Read from any unimplemented registers will return an undetermined value. TIMn_COMP--Timer n Comparator Value Register Address Offset: Timer Timer Timer Timer Timer Timer Timer Timer Attribute: Default Value: Bit R/W N/A 0: 1: 2: 3: 4: 5: 6: 7: 108h-10Fh, 128h-12Fh, 148h-14Fh, 168h-16Fh, 188h - 18Fh, 1A8h - 1AFh, 1C8h - 1CFh, 1E8h - 1EFh Size: 64 bit Description Timer Compare Value -- R/W. Reads to this register return the current value of the comparator if Timers n are configured to non-periodic mode: Writes to this register load the value against which the main counter should be compared for this timer. * When the main counter equals the value last written to this register, the corresponding interrupt can be generated (if so enabled). * The value in this register does not change based on the interrupt being generated. Timer 0 is configured to periodic mode: * When the main counter equals the value last written to this register, the corresponding interrupt can be generated (if so enabled). * After the main counter equals the value in this register, the value in this register is increased by the value last written to the register. For example, if the value written to the register is 00000123h, then 63:0 1. 2. 3. 4. An interrupt will be generated when the main counter reaches 00000123h. The value in this register will then be adjusted by the hardware to 00000246h. Another interrupt will be generated when the main counter reaches 00000246h The value in this register will then be adjusted by the hardware to 00000369h * As each periodic interrupt occurs, the value in this register will increment. When the incremented value is greater than the maximum value possible for this register (FFFFFFFFh for a 32-bit timer or FFFFFFFFFFFFFFFFh for a 64-bit timer), the value will wrap around through 0. For example, if the current value in a 32-bit timer is FFFF0000h and the last value written to this register is 20000h, then after the next interrupt the value will change to 00010000h Default value for each timer is all 1s for the bits that are implemented. For example, a 32-bit timer has a default value of 00000000FFFFFFFFh. A 64-bit timer has a default value of FFFFFFFFFFFFFFFFh. 750 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet High Precision Event Timer Registers 21.1.7 TIMERn_PROCMSG_ROUT-- Timer n Processor Message Interrupt Rout Register Address Offset: Timer Timer Timer Timer Timer Timer Timer Timer Default Value: N/A Note: 0: 1: 2: 3: 4: 5: 6: 7: 110-117h, 130-137h, 150-157h, 170-177h, 190-197h, 1B0-1B7h, 1D0-1D7h, 1F0-1F7h, Attribute: R/W Size: 64 bit The letter n can be 0, 1, 2, 3, 4, 5, 6, or 7 referring to Timer 0, 1, 2, 3, 4, 5, 6, or 7. Software can access the various bytes in this register using 32-bit or 64-bit accesses. 32-bit accesses can be done to offset 1x0h or 1x4h. 64-bit accesses can be done to 1x0h. 32-bit accesses must not be done to offsets 1x1h, 1x2h, 1x3h, 1x5h, 1x6h, or 1x7h. Bit 63:32 31:0 Description Tn_PROCMSG_INT_ADDR -- R/W. Software sets this 32-bit field to indicate the location that the direct processor interrupt message should be written. Tn_PROCMSG_INT_VAL -- R/W. Software sets this 32-bit field to indicate that value that is written during the direct processor interrupt message. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 751 High Precision Event Timer Registers 752 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Serial Peripheral Interface (SPI) 22 Serial Peripheral Interface (SPI) The Serial Peripheral Interface resides in memory mapped space. This function contains registers that allow for the setup and programming of devices that reside on the SPI interface. Note: All registers in this function (including memory-mapped registers) must be addressable in byte, word, and DWord quantities. The software must always make register accesses on natural boundaries (that is, DWord accesses must be on DWord boundaries; word accesses on word boundaries, and so forth) In addition, the memory-mapped register space must not be accessed with the LOCK semantic exclusive-access mechanism. If software attempts exclusive-access mechanisms to the SPI memory-mapped space, the results are undefined. 22.1 Serial Peripheral Interface Memory Mapped Configuration Registers The SPI Host Interface registers are memory-mapped in the RCRB (Root Complex Register Block) Chipset Register Space with a base address (SPIBAR) of 3800h and are located within the range of 3800h to 39FFh. The address for RCRB can be found in RCBA Register see Section 13.1.40. The individual registers are then accessible at SPIBAR + Offset as indicated in the following table. These memory mapped registers must be accessed in byte, word, or DWord quantities. Table 22-1. Serial Peripheral Interface (SPI) Register Address Map (SPI Memory Mapped Configuration Registers) (Sheet 1 of 2) SPIBAR + Offset Mnemonic Register Name 00h-03h BFPR BIOS Flash Primary Region 04h-05h HSFS Hardware Sequencing Flash Status 06h-07h HSFC 08h-0Bh FADDR Hardware Sequencing Flash Control Flash Address Default 00000000h 0000h 0000h 00000000h 10h-13h FDATA0 Flash Data 0 00000000h 14h-4Fh FDATAN Flash Data N 00000000h 50h-53h FRAP Flash Region Access Permissions 00000202h 54h-57h FREG0 Flash Region 0 00000000h 58h-5Bh FREG1 Flash Region 1 00000000h 5Ch-5F FREG2 Flash Region 2 00000000h 60h-63h FREG3 Flash Region 3 00000000h 64h-67h FREG4 Flash Region 4 00000000h 68h-73h Reserved Reserved for Future Flash Regions 00000000h 74h-77h PR0 Protected Range 0 00000000h 78h-7Bh PR1 Protected Range 1 00000000h 7Ch-7Fh PR2 Protected Range 2 00000000h 80-83h PR3 Protected Range 3 00000000h 84h-87h PR4 Protected Range 4 00000000h Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 753 Serial Peripheral Interface (SPI) Table 22-1. Serial Peripheral Interface (SPI) Register Address Map (SPI Memory Mapped Configuration Registers) (Sheet 2 of 2) 22.1.1 SPIBAR + Offset Mnemonic 90h SSFS Register Name Software Sequencing Flash Status 00h Software Sequencing Flash Control F80000h 91h-93h SSFC 94h-95h PREOP Prefix Opcode Configuration 96h-97h OPTYPE Opcode Type Configuration 0000h Opcode Menu Configuration 00000000 00000000h OPMENU A0h-A3h BBAR BIOS Base Address Configuration 00000000h B0h-B3h FDOC Flash Descriptor Observability Control 00000000h B4h-B7h FDOD Flash Descriptor Observability Data 00000000h C0h-C3h AFC Additional Flash Control 00000000h C4-C7h LVSCC Lower Vendor Specific Component Capabilities 00000000h C8-CBh UVSCC Upper Vendor Specific Component Capabilities 00000000h D0-D3h FPB Flash Partition Boundary 00000000h F0-F3H SRDL Soft Reset Data Lock 00000000h F4-F7H SRDC Soft Reset Data Control 00000000h F8-FBH SRD Soft Reset Data 00000000h BFPR -BIOS Flash Primary Region Register (SPI Memory Mapped Configuration Registers) Attribute: Size: RO 32 bits This register is only applicable when SPI device is in descriptor mode. Bit 31:29 Description Reserved 28:16 BIOS Flash Primary Region Limit (PRL) -- RO. This specifies address bits 24:12 for the Primary Region Limit. The value in this register loaded from the contents in the Flash Descriptor.FLREG1.Region Limit 15:13 Reserved 12:0 754 0000h 98h-9Fh Memory Address:SPIBAR + 00h Default Value: 00000000h Note: Default BIOS Flash Primary Region Base (PRB) -- RO. This specifies address bits 24:12 for the Primary Region Base The value in this register is loaded from the contents in the Flash Descriptor.FLREG1.Region Base Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Serial Peripheral Interface (SPI) 22.1.2 HSFS--Hardware Sequencing Flash Status Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 04hAttribute: Default Value: 0000hSize: Bit RO, R/WC, R/W 16 bits Description 15 Flash Configuration Lock-Down (FLOCKDN) -- R/WL. When set to 1, those Flash Program Registers that are locked down by this FLOCKDN bit cannot be written. Once set to 1, this bit can only be cleared by a hardware reset due to a global reset or host partition reset in an Intel ME-enabled system. 14 Flash Descriptor Valid (FDV) -- RO. This bit is set to a 1 if the Flash Controller read the correct Flash Descriptor Signature. If the Flash Descriptor Valid bit is not 1, software cannot use the Hardware Sequencing registers, but must use the software sequencing registers. Any attempt to use the Hardware Sequencing registers will result in the FCERR bit being set. 13 Flash Descriptor Override Pin-Strap Status (FDOPSS) -- RO: This bit indicates the condition of the Flash Descriptor Security Override / Intel ME Debug Mode Pin-Strap. 0 = The Flash Descriptor Security Override / Intel ME Debug Mode strap is set using external pullup on HDA_SDO 1 = No override 12:6 Reserved 5 SPI Cycle In Progress (SCIP)-- RO. Hardware sets this bit when software sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. This bit remains set until the cycle completes on the SPI interface. Hardware automatically sets and clears this bit so that software can determine when read data is valid and/or when it is safe to begin programming the next command. Software must only program the next command when this bit is 0. Note: This field is only applicable when in Descriptor mode and Hardware sequencing is being used. 4:3 Block/Sector Erase Size (BERASE) -- RO. This field identifies the erasable sector size for all Flash components. Valid Bit Settings: 00 = 256 Byte 01 = 4 K Byte 10 = 8 K Byte 11 = 64 K Byte If the FLA is less than FPBA then this field reflects the value in the LVSCC.LBES register. If the FLA is greater or equal to FPBA then this field reflects the value in the UVSCC.UBES register. Note: This field is only applicable when in Descriptor mode and Hardware sequencing is being used. 2 Access Error Log (AEL) -- R/WC. Hardware sets this bit to a 1 when an attempt was made to access the BIOS region using the direct access method or an access to the BIOS Program Registers that violated the security restrictions. This bit is simply a log of an access security violation. This bit is cleared by software writing a 1. Note: This field is only applicable when in Descriptor mode and Hardware sequencing is being used. 1 Flash Cycle Error (FCERR) -- R/WC. Hardware sets this bit to 1 when an program register access is blocked to the FLASH due to one of the protection policies or when any of the programmed cycle registers is written while a programmed access is already in progress. This bit remains asserted until cleared by software writing a 1 or until hardware reset occurs due to a global reset or host partition reset in an Intel ME enabled system. Software must clear this bit before setting the FLASH Cycle GO bit in this register. Note: This field is only applicable when in Descriptor mode and Hardware sequencing is being used. 0 Flash Cycle Done (FDONE) -- R/WC. The PCH sets this bit to 1 when the SPI Cycle completes after software previously set the FGO bit. This bit remains asserted until cleared by software writing a 1 or hardware reset due to a global reset or host partition reset in an Intel ME enabled system. When this bit is set and the SPI SMI# Enable bit is set, an internal signal is asserted to the SMI# generation block. Software must make sure this bit is cleared prior to enabling the SPI SMI# assertion for a new programmed access. Note: This field is only applicable when in Descriptor mode and Hardware sequencing is being used. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 755 Serial Peripheral Interface (SPI) 22.1.3 HSFC--Hardware Sequencing Flash Control Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 06hAttribute: Default Value: 0000hSize: Note: This register is only applicable when SPI device is in descriptor mode. Bit Description 15 Flash SPI SMI# Enable (FSMIE) -- R/W. When set to 1, the SPI asserts an SMI# request whenever the Flash Cycle Done bit is 1. 14 Reserved 13:8 22.1.4 Flash Data Byte Count (FDBC) -- R/W. This field specifies the number of bytes to shift in or out during the data portion of the SPI cycle. The contents of this register are 0s based with 0b representing 1 byte and 111111b representing 64 bytes. The number of bytes transferred is the value of this field plus 1. This field is ignored for the Block Erase command. 7:3 Reserved 2:1 FLASH Cycle (FCYCLE) -- R/W. This field defines the Flash SPI cycle type generated to the FLASH when the FGO bit is set as defined below: 00 = Read (1 up to 64 bytes by setting FDBC) 01 = Reserved 10 = Write (1 up to 64 bytes by setting FDBC) 11 = Block Erase 0 Flash Cycle Go (FGO) -- R/W/S. A write to this register with a 1 in this bit initiates a request to the Flash SPI Arbiter to start a cycle. This register is cleared by hardware when the cycle is granted by the SPI arbiter to run the cycle on the SPI bus. When the cycle is complete, the FDONE bit is set. Software is forbidden to write to any register in the HSFLCTL register between the FGO bit getting set and the FDONE bit being cleared. Any attempt to violate this rule will be ignored by hardware. Hardware allows other bits in this register to be programmed for the same transaction when writing this bit to 1. This saves an additional memory write. This bit always returns 0 on reads. FADDR--Flash Address Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 08hAttribute: Default Value: 00000000hSize: Bit 31:25 24:0 756 R/W, R/WS 16 bits R/W 32 bits Description Reserved Flash Linear Address (FLA) -- R/W. The FLA is the starting byte linear address of a SPI Read or Write cycle or an address within a Block for the Block Erase command. The Flash Linear Address must fall within a region for which BIOS has access permissions. Hardware must convert the FLA into a Flash Physical Address (FPA) before running this cycle on the SPI bus. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Serial Peripheral Interface (SPI) 22.1.5 FDATA0--Flash Data 0 Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 10hAttribute: Default Value: 00000000hSize: 22.1.6 R/W 32 bits Bit Description 31:0 Flash Data 0 (FD0) -- R/W. This field is shifted out as the SPI Data on the Master-Out Slave-In Data pin during the data portion of the SPI cycle. This register also shifts in the data from the Master-In Slave-Out pin into this register during the data portion of the SPI cycle. The data is always shifted starting with the least significant byte, msb to lsb, followed by the next least significant byte, msb to lsb, etc. Specifically, the shift order on SPI in terms of bits within this register is: 7-6-5-4-3-2-1-0-15-14-13-...8-23-22-...16-31...24 Bit 24 is the last bit shifted out/in. There are no alignment assumptions; byte 0 always represents the value specified by the cycle address. Note that the data in this register may be modified by the hardware during any programmed SPI transaction. Direct Memory Reads do not modify the contents of this register. FDATAN--Flash Data [N] Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 14hAttribute: SPIBAR + 18h SPIBAR + 1Ch SPIBAR + 20h SPIBAR + 24h SPIBAR + 28h SPIBAR + 2Ch SPIBAR + 30h SPIBAR + 34h SPIBAR + 38h SPIBAR + 3Ch SPIBAR + 40h SPIBAR + 44h SPIBAR + 48h SPIBAR + 4Ch Default Value: 00000000hSize: Bit 31:0 R/W 32 bits Description Flash Data N (FD[N]) -- R/W. Similar definition as Flash Data 0. However, this register does not begin shifting until FD[N-1] has completely shifted in/out.-- R/W. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 757 Serial Peripheral Interface (SPI) 22.1.7 FRAP--Flash Regions Access Permissions Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 50hAttribute: Default Value: 00000202hSize: Note: 22.1.8 This register is only applicable when SPI device is in descriptor mode. Bit Description 31:24 BIOS Master Write Access Grant (BMWAG) -- R/W. Each bit [31:29] corresponds to Master[7:0]. BIOS can grant one or more masters write access to the BIOS region 1 overriding the permissions in the Flash Descriptor. Master[1] is Host processor/BIOS, Master[2] is Intel ME, Master[3] is Host processor/GbE. Master[0] and Master[7:4] are reserved. The contents of this register are locked by the FLOCKDN bit. 23:16 BIOS Master Read Access Grant (BMRAG) -- R/W. Each bit [28:16] corresponds to Master[7:0]. BIOS can grant one or more masters read access to the BIOS region 1 overriding the read permissions in the Flash Descriptor. Master[1] is Host processor/BIOS, Master[2] is Intel ME, Master[3] is Host processor/GbE. Master[0] and Master[7:4] are reserved. The contents of this register are locked by the FLOCKDN bit 15:8 BIOS Region Write Access (BRWA) -- RO. Each bit [15:8] corresponds to Regions [7:0]. If the bit is set, this master can erase and write that particular region through register accesses. The contents of this register are that of the Flash Descriptor. Flash Master 1 Master Region Write Access OR a particular master has granted BIOS write permissions in their Master Write Access Grant register or the Flash Descriptor Security Override strap is set. 7:0 BIOS Region Read Access (BRRA) -- RO. Each bit [7:0] corresponds to Regions [7:0]. If the bit is set, this master can read that particular region through register accesses. The contents of this register are that of the Flash Descriptor.Flash Master 1.Master Region Write Access OR a particular master has granted BIOS read permissions in their Master Read Access Grant register or the Flash Descriptor Security Override strap is set. FREG0--Flash Region 0 (Flash Descriptor) Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 54h Default Value: 00000000h Note: Attribute: Size: RO 32 bits This register is only applicable when SPI device is in descriptor mode. Bit Description 31:29 Reserved 28:16 Region Limit (RL) -- RO. This specifies address bits 24:12 for the Region 0 Limit. The value in this register is loaded from the contents in the Flash Descriptor.FLREG0.Region Limit 15:13 Reserved 12:0 758 RO, R/W 32 bits Region Base (RB) / Flash Descriptor Base Address Region (FDBAR) -- RO. This specifies address bits 24:12 for the Region 0 Base. The value in this register is loaded from the contents in the Flash Descriptor.FLREG0.Region Base. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Serial Peripheral Interface (SPI) 22.1.9 FREG1--Flash Region 1 (BIOS Descriptor) Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 58hAttribute: Default Value: 00000000hSize: Note: This register is only applicable when SPI device is in descriptor mode. Bit Description 31:29 Reserved 28:16 Region Limit (RL) -- RO. This specifies address bits 24:12 for the Region 1 Limit. The value in this register is loaded from the contents in the Flash Descriptor.FLREG1.Region Limit. 15:13 Reserved 12:0 22.1.10 Region Base (RB) -- RO. This specifies address bits 24:12 for the Region 1 Base The value in this register is loaded from the contents in the Flash Descriptor.FLREG1.Region Base. FREG2--Flash Region 2 (Intel(R) ME) Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 5ChAttribute: Default Value: 00000000hSize: Note: Description 31:29 Reserved 28:16 Region Limit (RL) -- RO. This specifies address bits 24:12 for the Region 2 Limit. The value in this register is loaded from the contents in the Flash Descriptor.FLREG2.Region Limit. 15:13 12:0 Reserved Region Base (RB) -- RO. This specifies address bits 24:12 for the Region 2 Base. The value in this register is loaded from the contents in the Flash Descriptor.FLREG2.Region Base. FREG3--Flash Region 3 (GbE) Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 60hAttribute: Default Value: 00000000hSize: Note: RO 32 bits This register is only applicable when SPI device is in descriptor mode. Bit 22.1.11 RO 32 bits RO 32 bits This register is only applicable when SPI device is in descriptor mode. Bit Description 31:29 Reserved 28:16 Region Limit (RL) -- RO. This specifies address bits 24:12 for the Region 3 Limit. The value in this register is loaded from the contents in the Flash Descriptor.FLREG3.Region Limit. 15:13 Reserved 12:0 Region Base (RB) -- RO. This specifies address bits 24:12 for the Region 3 Base. The value in this register is loaded from the contents in the Flash Descriptor.FLREG3.Region Base. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 759 Serial Peripheral Interface (SPI) 22.1.12 FREG4--Flash Region 4 (Platform Data) Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 64h Default Value: 00000000h Note: Attribute: Size: This register is only applicable when SPI device is in descriptor mode. Bit Description 31:29 Reserved 28:16 Region Limit (RL) -- RO. This specifies address bits 24:12 for the Region 4 Limit. The value in this register is loaded from the contents in the Flash Descriptor.FLREG4.Region Limit. 15:13 Reserved 12:0 22.1.13 Region Base (RB) -- RO. This specifies address bits 24:12 for the Region 4 Base The value in this register is loaded from the contents in the Flash Descriptor.FLREG4.Region Base. PR0--Protected Range 0 Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 74hAttribute: Default Value: 00000000h Note: R/W Size: 32 bits This register can not be written when the FLOCKDN bit is set to 1. Bit Description 31 Write Protection Enable -- R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that writes and erases directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. 30:29 28:16 15 14:13 12:0 760 RO 32 bits Reserved Protected Range Limit -- R/W. This field corresponds to FLA address bits 24:12 and specifies the upper limit of the protected range. Address bits 11:0 are assumed to be FFFh for the limit comparison. Any address greater than the value programmed in this field is unaffected by this protected range. Read Protection Enable -- R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that read directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. Reserved Protected Range Base -- R/W. This field corresponds to FLA address bits 24:12 and specifies the lower base of the protected range. Address bits 11:0 are assumed to be 000h for the base comparison. Any address less than the value programmed in this field is unaffected by this protected range. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Serial Peripheral Interface (SPI) 22.1.14 PR1--Protected Range 1 Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 78h Default Value: 00000000h Note: Bit Description 31 Write Protection Enable -- R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that writes and erases directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. 28:16 15 14:13 12:0 Reserved Protected Range Limit -- R/W. This field corresponds to FLA address bits 24:12 and specifies the upper limit of the protected range. Address bits 11:0 are assumed to be FFFh for the limit comparison. Any address greater than the value programmed in this field is unaffected by this protected range. Read Protection Enable -- R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that read directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. Reserved Protected Range Base -- R/W. This field corresponds to FLA address bits 24:12 and specifies the lower base of the protected range. Address bits 11:0 are assumed to be 000h for the base comparison. Any address less than the value programmed in this field is unaffected by this protected range. PR2--Protected Range 2 Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 7Ch Default Value: 00000000h Note: R/W 32 bits This register can not be written when the FLOCKDN bit is set to 1. 30:29 22.1.15 Attribute: Size: Attribute: Size: R/W 32 bits This register can not be written when the FLOCKDN bit is set to 1. Bit Description 31 Write Protection Enable -- R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that writes and erases directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. 30:29 28:16 15 14:13 12:0 Reserved Protected Range Limit -- R/W. This field corresponds to FLA address bits 24:12 and specifies the upper limit of the protected range. Address bits 11:0 are assumed to be FFFh for the limit comparison. Any address greater than the value programmed in this field is unaffected by this protected range. Read Protection Enable -- R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that read directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. Reserved Protected Range Base -- R/W. This field corresponds to FLA address bits 24:12 and specifies the lower base of the protected range. Address bits 11:0 are assumed to be 000h for the base comparison. Any address less than the value programmed in this field is unaffected by this protected range. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 761 Serial Peripheral Interface (SPI) 22.1.16 PR3--Protected Range 3 Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 80h Default Value: 00000000h Note: Bit Description 31 Write Protection Enable -- R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that writes and erases directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. 28:16 15 14:13 12:0 Reserved Protected Range Limit -- R/W. This field corresponds to FLA address bits 24:12 and specifies the upper limit of the protected range. Address bits 11:0 are assumed to be FFFh for the limit comparison. Any address greater than the value programmed in this field is unaffected by this protected range. Read Protection Enable -- R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that read directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. Reserved Protected Range Base -- R/W. This field corresponds to FLA address bits 24:12 and specifies the lower base of the protected range. Address bits 11:0 are assumed to be 000h for the base comparison. Any address less than the value programmed in this field is unaffected by this protected range. PR4--Protected Range 4 Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 84h Default Value: 00000000h Note: Attribute: Size: R/W 32 bits This register can not be written when the FLOCKDN bit is set to 1. Bit Description 31 Write Protection Enable -- R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that writes and erases directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. 30:29 28:16 15 14:13 12:0 762 R/W 32 bits This register can not be written when the FLOCKDN bit is set to 1. 30:29 22.1.17 Attribute: Size: Reserved Protected Range Limit -- R/W. This field corresponds to FLA address bits 24:12 and specifies the upper limit of the protected range. Address bits 11:0 are assumed to be FFFh for the limit comparison. Any address greater than the value programmed in this field is unaffected by this protected range. Read Protection Enable -- R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that read directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. Reserved Protected Range Base -- R/W. This field corresponds to FLA address bits 24:12 and specifies the lower base of the protected range. Address bits 11:0 are assumed to be 000h for the base comparison. Any address less than the value programmed in this field is unaffected by this protected range. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Serial Peripheral Interface (SPI) 22.1.18 SSFS--Software Sequencing Flash Status Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 90h Default Value: 00h Note: Attribute: Size: RO, R/WC 8 bits The Software Sequencing control and status registers are reserved if the hardware sequencing control and status registers are used. Bit Description 7 Fast Read Supported -- RO. This bit reflects the value of the Fast Read Support bit in the flash Descriptor Component Section. 6 Dual Output Fast Read Supported -- RO. This bit reflects the value of the Dual Output Fast Read support bit in the Flash Descriptor Component Section 5 Reserved 4 Access Error Log (AEL) -- RO. This bit reflects the value of the Hardware Sequencing Status AEL register. 3 Flash Cycle Error (FCERR) -- R/WC. Hardware sets this bit to 1 when a programmed access is blocked from running on the SPI interface due to one of the protection policies or when any of the programmed cycle registers is written while a programmed access is already in progress. This bit remains asserted until cleared by software writing a 1 or hardware reset due to a global reset or host partition reset in an Intel(R) ME enabled system. 2 Cycle Done Status -- R/WC. The PCH sets this bit to 1 when the SPI Cycle completes (that is, SCIP bit is 0) after software sets the GO bit. This bit remains asserted until cleared by software writing a 1 or hardware reset due to a global reset or host partition reset in an Intel(R) ME enabled system. When this bit is set and the SPI SMI# Enable bit is set, an internal signal is asserted to the SMI# generation block. Software must make sure this bit is cleared prior to enabling the SPI SMI# assertion for a new programmed access. 1 Reserved 0 SPI Cycle In Progress (SCIP) -- RO. Hardware sets this bit when software sets the SPI Cycle Go bit in the Command register. This bit remains set until the cycle completes on the SPI interface. Hardware automatically sets and clears this bit so that software can determine when read data is valid and/or when it is safe to begin programming the next command. Software must only program the next command when this bit is 0. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 763 Serial Peripheral Interface (SPI) 22.1.19 SSFC--Software Sequencing Flash Control Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 91h Default Value: F80000h Bit R/W 24 bits Description 23:19 Reserved - BIOS must set this field to `11111'b 18:16 SPI Cycle Frequency (SCF) -- R/W. This register sets frequency to use for all SPI software sequencing cycles (write, erase, fast read, read status, etc.) except for the read cycle which always run at 20 MHz. 000 = 20 MHz 001 = 33 MHz 100 = 50 MHz All other values reserved. This register is locked when the SPI Configuration Lock-Down bit is set. 15 SPI SMI# Enable (SME) -- R/W. When set to 1, the SPI asserts an SMI# request whenever the Cycle Done Status bit is 1. 14 Data Cycle (DS) -- R/W. When set to 1, there is data that corresponds to this transaction. When 0, no data is delivered for this cycle, and the DBC and data fields themselves are don't cares. 13:8 7 764 Attribute: Size: Data Byte Count (DBC) -- R/W. This field specifies the number of bytes to shift in or out during the data portion of the SPI cycle. The valid settings (in decimal) are any value from 0 to 63. The number of bytes transferred is the value of this field plus 1. Note that when this field is 00_0000b, then there is 1 byte to transfer and that 11_1111b means there are 64 bytes to transfer. Reserved 6:4 Cycle Opcode Pointer (COP) -- R/W. This field selects one of the programmed opcodes in the Opcode Menu to be used as the SPI Command/Opcode. In the case of an Atomic Cycle Sequence, this determines the second command. -- R/W. 3 Sequence Prefix Opcode Pointer (SPOP) -- R/W. This field selects one of the two programmed prefix opcodes for use when performing an Atomic Cycle Sequence. A value of 0 points to the opcode in the least significant byte of the Prefix Opcodes register. By making this programmable, the PCH supports flash devices that have different opcodes for enabling writes to the data space vs. status register. 2 Atomic Cycle Sequence (ACS) -- R/W. When set to 1 along with the SCGO assertion, the PCH will execute a sequence of commands on the SPI interface without allowing the LAN component to arbitrate and interleave cycles. The sequence is composed of: * Atomic Sequence Prefix Command (8-bit opcode only) * Primary Command specified below by software (can include address and data) * Polling the Flash Status Register (opcode 05h) until bit 0 becomes 0b. The SPI Cycle in Progress bit remains set and the Cycle Done Status bit remains unset until the Busy bit in the Flash Status Register returns 0. 1 SPI Cycle Go (SCGO) -- R/WS. This bit always returns 0 on reads. However, a write to this register with a 1 in this bit starts the SPI cycle defined by the other bits of this register. The "SPI Cycle in Progress" (SCIP) bit gets set by this action. Hardware must ignore writes to this bit while the Cycle In Progress bit is set. Hardware allows other bits in this register to be programmed for the same transaction when writing this bit to 1. This saves an additional memory write. 0 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Serial Peripheral Interface (SPI) 22.1.20 PREOP--Prefix Opcode Configuration Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 94hAttribute: Default Value: 0000h 16 bits Bit Description 15:8 Prefix Opcode 1-- R/W. Software programs an SPI opcode into this field that is permitted to run as the first command in an atomic cycle sequence. 7:0 Prefix Opcode 0 -- R/W. Software programs an SPI opcode into this field that is permitted to run as the first command in an atomic cycle sequence. Note: 22.1.21 R/W Size: This register is not writable when the Flash Configuration Lock-Down bit (SPIBAR + 04h:15) is set. OPTYPE--Opcode Type Configuration Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 96h Default Value: 0000h Attribute: Size: R/W 16 bits Entries in this register correspond to the entries in the Opcode Menu Configuration register. Note: The definition below only provides write protection for opcodes that have addresses associated with them. Therefore, any erase or write opcodes that do not use an address should be avoided (for example, "Chip Erase" and "Auto-Address Increment Byte Program") Bit Description 15:14 Opcode Type 7 -- R/W. See the description for bits 1:0 13:12 Opcode Type 6 -- R/W. See the description for bits 1:0 11:10 Opcode Type 5 -- R/W. See the description for bits 1:0 9:8 Opcode Type 4 -- R/W. See the description for bits 1:0 7:6 Opcode Type 3 -- R/W. See the description for bits 1:0 5:4 Opcode Type 2 -- R/W. See the description for bits 1:0 3:2 Opcode Type 1 -- R/W. See the description for bits 1:0 1:0 Opcode Type 0 -- R/W. This field specifies information about the corresponding Opcode 0. This information allows the hardware to 1) know whether to use the address field and 2) provide BIOS and Shared Flash protection capabilities. The encoding of the two bits is: 00 = No address associated with this Opcode; Read cycle type 01 = No address associated with this Opcode; Write cycle type 10 = Address required; Read cycle type 11 = Address required; Write cycle type Note: This register is not writable when the SPI Configuration Lock-Down bit (SPIBAR + 00h:15) is set. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 765 Serial Peripheral Interface (SPI) 22.1.22 OPMENU--Opcode Menu Configuration Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 98h Default Value: 0000000000000000h Attribute: Size: R/W 64 bits Eight entries are available in this register to give BIOS a sufficient set of commands for communicating with the flash device, while also restricting what malicious software can do. This keeps the hardware flexible enough to operate with a wide variety of SPI devices. Note: It is recommended that BIOS avoid programming Write Enable opcodes in this menu. Malicious software could then perform writes and erases to the SPI flash without using the atomic cycle mechanism. This could cause functional failures in a shared flash environment. Write Enable opcodes should only be programmed in the Prefix Opcodes. Bit Description 63:56 Allowable Opcode 7 -- R/W. See the description for bits 7:0 55:48 Allowable Opcode 6 -- R/W. See the description for bits 7:0 47:40 Allowable Opcode 5 -- R/W. See the description for bits 7:0 39:32 Allowable Opcode 4 -- R/W. See the description for bits 7:0 31:24 Allowable Opcode 3 -- R/W. See the description for bits 7:0 23:16 Allowable Opcode 2 -- R/W. See the description for bits 7:0 15:8 Allowable Opcode 1 -- R/W. See the description for bits 7:0 7:0 Allowable Opcode 0 -- R/W. Software programs an SPI opcode into this field for use when initiating SPI commands through the Control Register. This register is not writable when the SPI Configuration Lock-Down bit (SPIBAR + 00h:15) is set. 22.1.23 FDOC--Flash Descriptor Observability Control Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + B0h Default Value: 00000000h Note: R/W 32 bits This register that can be used to observe the contents of the Flash Descriptor that is stored in the PCH Flash Controller. This register is only applicable when SPI device is in descriptor mode. Bit Description 31:15 Reserved 14:12 Flash Descriptor Section Select (FDSS) -- R/W. Selects which section within the loaded Flash Descriptor to observe. 000 = Flash Signature and Descriptor Map 001 = Component 010 = Region 011 = Master 111 = Reserved 11:2 1:0 766 Attribute: Size: Flash Descriptor Section Index (FDSI) -- R/W. Selects the DW offset within the Flash Descriptor Section to observe. Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Serial Peripheral Interface (SPI) 22.1.24 FDOD--Flash Descriptor Observability Data Register (SPI Memory Mapped Configuration Registers) Memory Address: SPIBAR + B4h Default Value: 00000000h Note: 31:0 Description Flash Descriptor Section Data (FDSD) -- RO. Returns the DW of data to observe as selected in the Flash Descriptor Observability Control. AFC--Additional Flash Control Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + C0h 00000000h Bit 31:3 2:1 0 22.1.26 Attribute: Size: RO, R/W 32 bits. Description Reserved. Flash Controller Interface Dynamic Clock Gating Enable -- R/W. 0 = Flash Controller Interface Dynamic Clock Gating is Disabled 1 = Flash Controller Interface Dynamic Clock Gating is Enabled Other configurations are Reserved. Flash Controller Core Dynamic Clock Gating Enable -- R/W. 0 = Flash Controller Core Dynamic Clock Gating is Disabled 1 = Flash Controller Core Dynamic Clock Gating is Enabled LVSCC-- Host Lower Vendor Specific Component Capabilities Register (SPI Memory Mapped Configuration Registers) Memory Address: SPIBAR + C4h Default Value: 00000000h Note: RO 32 bits This register that can be used to observe the contents of the Flash Descriptor that is stored in the PCH Flash Controller. Bit 22.1.25 Attribute: Size: Attribute: Size: RO, R/WL 32 bits All attributes described in LVSCC must apply to all flash space below the FPBA, even if it spans between two separate flash parts. This register is only applicable when SPI device is in descriptor mode. Bit 31:24 23 22:16 15:8 7:5 Description Reserved. Vendor Component Lock (LVCL) -- R/W. This register locks itself when set. 0 = The lock bit is not set 1 = The Vendor Component Lock bit is set. Note: This bit applies to both UVSCC and LVSCC registers. Reserved Lower Erase Opcode (LEO)-- R/W. This register is programmed with the Flash erase instruction opcode required by the vendor's Flash component. This register is locked by the Vendor Component Lock (LVCL) bit. Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 767 Serial Peripheral Interface (SPI) 22.1.27 Bit Description 4 Write Enable on Write Status (LWEWS) -- R/W. This register is locked by the Vendor Component Lock (LVCL) bit. 0 = No automatic write of 00h will be made to the SPI flash's status register) 1 = A write of 00h to the SPI flash's status register will be sent on EVERY write and erase to the SPI flash. 06h 01h 00h is the opcode sequence used to unlock the Status register. Notes: 1. This bit should not be set to `1' if there are non volatile bits in the SPI flash's status register. This may lead to premature flash wear out 2. This is not an atomic sequence. If the SPI component's status register is non-volatile, then BIOS should issue an atomic software sequence cycle to unlock the flash part. 3. Bit 3 and bit 4 should NOT be both set to `1'. 3 Lower Write Status Required (LWSR) -- R/W. This register is locked by the Vendor Component Lock (LVCL) bit. 0 = No automatic write of 00h will be made to the SPI flash's status register) 1 = A write of 00h to the SPI flash's status register will be sent on EVERY write and erase to the SPI flash. 50h 01h 00h is the opcode sequence used to unlock the Status register. Notes: 1. This bit should not be set to `1' if there are non volatile bits in the SPI flash's status register. This may lead to premature flash wear out. 2. This is not an atomic sequence. If the SPI component's status register is non-volatile, then BIOS should issue an atomic software sequence cycle to unlock the flash part. 3. Bit 3 and bit 4 should NOT be both set to `1'. 2 Lower Write Granularity (LWG) -- R/W. This register is locked by the Vendor Component Lock (LVCL) bit. 0 = 1 Byte 1 = 64 Byte Notes: 1. If more than one Flash component exists, this field must be set to the lowest common write granularity of the different Flash components. 2. If using 64 B write, BIOS must ensure that multiple byte writes do not occur over 256 B boundaries. This will lead to corruption as the write will wrap around the page boundary on the SPI flash part. This is a a feature page writable SPI flash. 1:0 Lower Block/Sector Erase Size (LBES)-- R/W. This field identifies the erasable sector size for all Flash components. 00 = 256 Byte 01 = 4 KB 10 = 8 KB 11 = 64 KB This register is locked by the Vendor Component Lock (LVCL) bit. Hardware takes no action based on the value of this register. The contents of this register are to be used only by software and can be read in the HSFSTS.BERASE register in both the BIOS and the GbE program registers if FLA is less than FPBA. UVSCC-- Host Upper Vendor Specific Component Capabilities Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + C8h 00000000h Attribute: Size: RO, R/WL 32 bits Note: All attributes described in UVSCC must apply to all flash space equal to or above the FPBA, even if it spans between two separate flash parts. This register is only applicable when SPI device is in descriptor mode. Note: To prevent this register from being modified you must use LVSCC.VCL bit. Bit 31:16 15:8 7:5 768 Description Reserved. Upper Erase Opcode (UEO)-- R/W. This register is programmed with the Flash erase instruction opcode required by the vendor's Flash component. This register is locked by the Vendor Component Lock (UVCL) bit. Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Serial Peripheral Interface (SPI) Bit Description Write Enable on Write Status (UWEWS) -- R/W. This register is locked by the Vendor Component Lock (UVCL) bit. 0 = No automatic write of 00h will be made to the SPI flash's status register) 1 = A write of 00h to the SPI flash's status register will be sent on EVERY write and erase to the SPI flash. 06h 01h 00h is the opcode sequence used to unlock the Status register. 4 Notes: 1. This bit should not be set to `1' if there are non volatile bits in the SPI flash's status register. This may lead to premature flash wear out 2. This is not an atomic sequence. If the SPI component's status register is non-volatile, then BIOS should issue an atomic software sequence cycle to unlock the flash part. 3. Bit 3 and bit 4 should NOT be both set to `1'. Upper Write Status Required (UWSR) -- R/W. This register is locked by the Vendor Component Lock (UVCL) bit. 0 = No automatic write of 00h will be made to the SPI flash's status register) 1 = A write of 00h to the SPI flash's status register will be sent on EVERY write and erase to the SPI flash. 50h 01h 00h is the opcode sequence used to unlock the Status register. 3 Notes: 1. This bit should not be set to `1' if there are non volatile bits in the SPI flash's status register. This may lead to premature flash wear out 2. This is not an atomic sequence. If the SPI component's status register is non-volatile, then BIOS should issue an atomic software sequence cycle to unlock the flash part. 3. Bit 3 and bit 4 should NOT be both set to `1'. Upper Write Granularity (UWG) -- R/W. This register is locked by the Vendor Component Lock (UVCL) bit. 0 = 1 Byte 1 = 64 Byte 2 1:0 22.1.28 Notes: 1. If more than one Flash component exists, this field must be set to the lowest common write granularity of the different Flash components. 2. If using 64 B write, BIOS must ensure that multiple byte writes do not occur over 256 B boundaries. This will lead to corruption as the write will wrap around the page boundary on the SPI flash part. This is a a feature page writable SPI flash. Upper Block/Sector Erase Size (UBES)-- R/W. This field identifies the erasable sector size for all Flash components. Valid Bit Settings: 00 = 256 Byte 01 = 4 KB 10 = 8 KB 11 = 64 KB This register is locked by the Vendor Component Lock (UVCL) bit. Hardware takes no action based on the value of this register. The contents of this register are to be used only by software and can be read in the HSFSTS.BERASE register in both the BIOS and the GbE program registers if FLA is greater or equal to FPBA. FPB -- Flash Partition Boundary (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + D0h Default Value: 00000000h Note: Attribute: Size: RO 32 bits This register is only applicable when SPI device is in descriptor mode. Bit 31:13 12:0 Description Reserved. Flash Partition Boundary Address (FPBA) -- RO. This register reflects the value of Flash Descriptor Component FPBA field. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 769 Serial Peripheral Interface (SPI) 22.1.29 SRDL -- Soft Reset Data Lock (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + F0h 00000000h Bit 31:1 0 22.1.30 Reserved. Set_Strap Lock (SSL) -- R/WL. 0 = The SRDL (this register), SRDC (SPIBAR+F4h), and SRD (SPIBAR+F4h) registers are writable. 1 = The SRDL (this register), SRDC (SPIBAR+F4h), and SRD (SPIBAR+F4h) registers are locked. Note: That this bit is reset to `0' on CF9h resets. SRDC -- Soft Reset Data Control (SPI Memory Mapped Configuration Registers) SPIBAR + F4h 00000000h Bit 31:1 0 Attribute: Size: R/WL 32 bits Description Reserved. Soft Reset Data Select (SRDS) -- R/WL. 0 = The Set_Strap data sends the default processor configuration data. 1 = The Set_Strap message bits come from the Set_Strap Msg Data register. Notes: 1. This bit is reset by the RSMRST# or when the Resume well loses power. 2. This bit is locked by the SSL bit (SPIBAR+F0h:bit 0). SRD -- Soft Reset Data (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + F8h 00000000h Bit 31:14 13:0 22.2 R/WL 32 bits Description Memory Address: Default Value: 22.1.31 Attribute: Size: Attribute: Size: R/WL 32 bits Description Reserved. Set_Stap Data (SSD) -- R/WL. Notes: 1. These bits are reset by the RSMRST#, or when the Resume well loses power. 2. These bits are locked by the SSL bit (SPIBAR+F0h:bit 0). Flash Descriptor Records The following sections describe the data structure of the Flash Descriptor on the SPI device. These are not registers within the PCH. 22.3 OEM Section Memory Address:F00h 770 Default Value: Size:256 Bytes Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Serial Peripheral Interface (SPI) 256 Bytes are reserved at the top of the Flash Descriptor for use by the OEM. The information stored by the OEM can only be written during the manufacturing process as the Flash Descriptor read/write permissions must be set to Read Only when the computer leaves the manufacturing floor. The PCH Flash controller does not read this information. FFh is suggested to reduce programming time. 22.4 GbE SPI Flash Program Registers The GbE Flash registers are memory-mapped with a base address MBARB found in the GbE LAN register chapter Device 25: Function 0: Offset 14h. The individual registers are then accessible at MBARB + Offset as indicated in the following table. These memory mapped registers must be accessed in byte, word, or DWord quantities. Note: These registers are only applicable when SPI flash is used in descriptor mode. Table 22-2. Gigabit LAN SPI Flash Program Register Address Map (GbE LAN Memory Mapped Configuration Registers) MBARB + Offset Mnemonic 00h-03h GLFPR 04h-05h HSFS 06h-07h HSFC 08h-0Bh FADDR 0Ch-0Fh Reserved 10h-13h FDATA0 14h-4Fh Reserved 50h-53h FRAP Register Name Gigabit LAN Flash Primary Region Hardware Sequencing Flash Status Hardware Sequencing Flash Control Flash Address Default Attribute 00000000h RO 0000h RO, R/WC, R/W 0000h R/W, R/WS 00000000h R/W Reserved 00000000h Flash Data 0 00000000h Reserved 00000000h Flash Region Access Permissions 00000088h R/W RO, R/W 54h-57h FREG0 Flash Region 0 00000000h RO 58h-5Bh FREG1 Flash Region 1 00000000h RO 5Ch-5Fh FREG2 Flash Region 2 00000000h RO 60h-63h FREG3 Flash Region 3 00000000h RO 64h-73h Reserved 74h-77h PR0 Protected Range 0 00000000h R/W Protected Range 1 00000000h R/W 78h-7Bh PR1 7Ch-8Fh Reserved Reserved for Future Flash Regions Reserved 90h SSFS Software Sequencing Flash Status 00h RO, R/WC 91h-93h SSFC Software Sequencing Flash Control 000000h R/W 94h-95h PREOP Prefix Opcode Configuration 0000h R/W 96h-97h OPTYPE Opcode Type Configuration 0000h R/W 98h-9Fh OPMENU Opcode Menu Configuration 00000000 00000000h R/W A0h-DFh Reserved Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 771 Serial Peripheral Interface (SPI) 22.4.1 GLFPR -Gigabit LAN Flash Primary Region Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: MBARB + 00h 00000000h Bit 31:29 Description Reserved GbE Flash Primary Region Limit (PRL)-- RO. This specifies address bits 24:12 for the Primary Region Limit. The value in this register loaded from the contents in the Flash Descriptor.FLREG3.Region Limit 15:13 Reserved GbE Flash Primary Region Base (PRB) -- RO. This specifies address bits 24:12 for the Primary Region Base The value in this register is loaded from the contents in the Flash Descriptor.FLREG3.Region Base HSFS--Hardware Sequencing Flash Status Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: Bit MBARB + 04h 0000h Attribute: Size: RO, R/WC, R/W 16 bits Description 15 Flash Configuration Lock-Down (FLOCKDN)-- R/W. When set to 1, those Flash Program Registers that are locked down by this FLOCKDN bit cannot be written. Once set to 1, this bit can only be cleared by a hardware reset due to a global reset or host partition reset in an Intel(R) ME enabled system. 14 Flash Descriptor Valid (FDV)-- RO. This bit is set to a 1 if the Flash Controller read the correct Flash Descriptor Signature. If the Flash Descriptor Valid bit is not `1', software cannot use the Hardware Sequencing registers, but must use the software sequencing registers. Any attempt to use the Hardware Sequencing registers will result in the FCERR bit being set. 13 Flash Descriptor Override Pin Strap Status (FDOPSS)-- RO. his bit indicates the condition of the Flash Descriptor Security Override / Intel ME Debug Mode Pin-Strap. 0 = The Flash Descriptor Security Override / Intel ME Debug Mode strap is set using external pullup on HDA_SDO 1 = No override 12:6 5 4:3 772 RO 32 bits 28:16 12:0 22.4.2 Attribute: Size: Reserved SPI Cycle In Progress (SCIP)-- RO. Hardware sets this bit when software sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. This bit remains set until the cycle completes on the SPI interface. Hardware automatically sets and clears this bit so that software can determine when read data is valid and/or when it is safe to begin programming the next command. Software must only program the next command when this bit is 0. Block/Sector Erase Size (BERASE) -- RO. This field identifies the erasable sector size for all Flash components. 00 = 256 Byte 01 = 4 K Byte 10 = 8 K Byte 11 = 64 K Byte If the Flash Linear Address is less than FPBA then this field reflects the value in the LVSCC.LBES register. If the Flash Linear Address is greater or equal to FPBA then this field reflects the value in the UVSCC.UBES register. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Serial Peripheral Interface (SPI) 22.4.3 Bit Description 2 Access Error Log (AEL)-- R/WC. Hardware sets this bit to a 1 when an attempt was made to access the GbE region using the direct access method or an access to the GbE Program Registers that violated the security restrictions. This bit is simply a log of an access security violation. This bit is cleared by software writing a `1.' 1 Flash Cycle Error (FCERR) -- R/WC. Hardware sets this bit to 1 when an program register access is blocked to the FLASH due to one of the protection policies or when any of the programmed cycle registers is written while a programmed access is already in progress. This bit remains asserted until cleared by software writing a 1 or until hardware reset occurs due to a global reset or host partition reset in an Intel(R) ME enabled system. Software must clear this bit before setting the FLASH Cycle GO bit in this register. 0 Flash Cycle Done (FDONE) -- R/WC. The PCH sets this bit to 1 when the SPI Cycle completes after software previously set the FGO bit. This bit remains asserted until cleared by software writing a 1 or hardware reset due to a global reset or host partition reset in an Intel(R) ME enabled system. When this bit is set and the SPI SMI# Enable bit is set, an internal signal is asserted to the SMI# generation block. Software must make sure this bit is cleared prior to enabling the SPI SMI# assertion for a new programmed access. HSFC--Hardware Sequencing Flash Control Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: MBARB + 06h Default Value: 0000h Bit 15:10 22.4.4 Attribute: Size: R/W, R/WS 16 bits Description Reserved 9:8 Flash Data Byte Count (FDBC) -- R/W. This field specifies the number of bytes to shift in or out during the data portion of the SPI cycle. The content's of this register are 0s based with 0b representing 1 byte and 11b representing 4 bytes. The number of bytes transferred is the value of this field plus 1. This field is ignored for the Block Erase command. 7:3 Reserved 2:1 FLASH Cycle (FCYCLE) -- R/W. This field defines the Flash SPI cycle type generated to the FLASH when the FGO bit is set as defined below: 00 = Read (1 up to 4 bytes by setting FDBC) 01 = Reserved 10 = Write (1 up to 4 bytes by setting FDBC) 11 = Block Erase 0 Flash Cycle Go (FGO) -- R/W/S. A write to this register with a `1' in this bit initiates a request to the Flash SPI Arbiter to start a cycle. This register is cleared by hardware when the cycle is granted by the SPI arbiter to run the cycle on the SPI bus. When the cycle is complete, the FDONE bit is set. Software is forbidden to write to any register in the HSFLCTL register between the FGO bit getting set and the FDONE bit being cleared. Any attempt to violate this rule will be ignored by hardware. Hardware allows other bits in this register to be programmed for the same transaction when writing this bit to 1. This saves an additional memory write. This bit always returns 0 on reads. FADDR--Flash Address Register (GbE LAN Memory Mapped Configuration Registers) Memory Address:MBARB + 08hAttribute: Default Value: 00000000h Bit 31:25 24:0 R/W Size: 32 bits Description Reserved Flash Linear Address (FLA) -- R/W. The FLA is the starting byte linear address of a SPI Read or Write cycle or an address within a Block for the Block Erase command. The Flash Linear Address must fall within a region for which GbE has access permissions. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 773 Serial Peripheral Interface (SPI) 22.4.5 FDATA0--Flash Data 0 Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: 22.4.6 Attribute: Size: R/W 32 bits Bit Description 31:0 Flash Data 0 (FD0) -- R/W. This field is shifted out as the SPI Data on the Master-Out Slave-In Data pin during the data portion of the SPI cycle. This register also shifts in the data from the Master-In Slave-Out pin into this register during the data portion of the SPI cycle. The data is always shifted starting with the least significant byte, msb to lsb, followed by the next least significant byte, msb to lsb, etc. Specifically, the shift order on SPI in terms of bits within this register is: 7-6-5-4-3-2-1-0-15-14-13-...8-23-22-...16-31...24 Bit 24 is the last bit shifted out/in. There are no alignment assumptions; byte 0 always represents the value specified by the cycle address. Note that the data in this register may be modified by the hardware during any programmed SPI transaction. Direct Memory Reads do not modify the contents of this register. FRAP--Flash Regions Access Permissions Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: Bit 774 MBARB + 10h 00000000h MBARB + 50h 00000808h Attribute: Size: RO, R/W 32 bits Description 31:24 GbE Master Write Access Grant (GMWAG) -- R/W. Each bit 31:24 corresponds to Master[7:0]. GbE can grant one or more masters write access to the GbE region 3 overriding the permissions in the Flash Descriptor. Master[1] is Host Processor/BIOS, Master[2] is Intel(R) Management Engine, Master[3] is Host processor/GbE. Master[0] and Master[7:4] are reserved. The contents of this register are locked by the FLOCKDN bit. 23:16 GbE Master Read Access Grant (GMRAG) -- R/W. Each bit 23:16 corresponds to Master[7:0]. GbE can grant one or more masters read access to the GbE region 3 overriding the read permissions in the Flash Descriptor. Master[1] is Host processor/BIOS, Master[2] is Intel(R) Management Engine, Master[3] is GbE. Master[0] and Master[7:4] are reserved. The contents of this register are locked by the FLOCKDN bit 15:8 GbE Region Write Access (GRWA) -- RO. Each bit 15:8 corresponds to Regions 7:0. If the bit is set, this master can erase and write that particular region through register accesses. The contents of this register are that of the Flash Descriptor. Flash Master 3.Master Region Write Access OR a particular master has granted GbE write permissions in their Master Write Access Grant register OR the Flash Descriptor Security Override strap is set. 7:0 GbE Region Read Access (GRRA) -- RO. Each bit 7:0 corresponds to Regions 7:0. If the bit is set, this master can read that particular region through register accesses. The contents of this register are that of the Flash Descriptor. Flash Master 3.Master Region Write Access OR a particular master has granted GbE read permissions in their Master Read Access Grant register. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Serial Peripheral Interface (SPI) 22.4.7 FREG0--Flash Region 0 (Flash Descriptor) Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: MBARB + 54h Default Value: 00000000h Bit Description Reserved 28:16 Region Limit (RL) -- RO. This specifies address bits 24:12 for the Region 0 Limit. The value in this register is loaded from the contents in the Flash Descriptor.FLREG0.Region Limit. 12:0 Reserved Region Base (RB) -- RO. This specifies address bits 24:12 for the Region 0 Base The value in this register is loaded from the contents in the Flash Descriptor.FLREG0.Region Base. FREG1--Flash Region 1 (BIOS Descriptor) Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: MBARB + 58h Default Value: 00000000h Bit Attribute: Size: RO 32 bits Description 31:29 Reserved 28:16 Region Limit (RL) -- RO. This specifies address bits 24:12 for the Region 1 Limit. The value in this register is loaded from the contents in the Flash Descriptor.FLREG1.Region Limit. 15:13 Reserved 12:0 22.4.9 RO 32 bits 31:29 15:13 22.4.8 Attribute: Size: Region Base (RB) -- RO. This specifies address bits 24:12 for the Region 1 Base The value in this register is loaded from the contents in the Flash Descriptor.FLREG1.Region Base. FREG2--Flash Region 2 (Intel(R) ME) Register (GbE LAN Memory Mapped Configuration Registers) Memory Address:MBARB + 5Ch Default Value: 00000000h Bit Attribute: Size: RO 32 bits Description 31:29 Reserved 28:16 Region Limit (RL) -- RO. This specifies address bits 24:12 for the Region 2 Limit. The value in this register is loaded from the contents in the Flash Descriptor.FLREG2.Region Limit. 15:13 Reserved 12:0 Region Base (RB) -- RO. This specifies address bits 24:12 for the Region 2 Base The value in this register is loaded from the contents in the Flash Descriptor.FLREG2.Region Base. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 775 Serial Peripheral Interface (SPI) 22.4.10 FREG3--Flash Region 3 (GbE) Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: MBARB + 60h 00000000h Bit Description Reserved 28:16 Region Limit (RL) -- RO. This specifies address bits 24:12 for the Region 3 Limit. The value in this register is loaded from the contents in the Flash Descriptor.FLREG3.Region Limit. 15:13 Reserved Region Base (RB) -- RO. This specifies address bits 24:12 for the Region 3 Base The value in this register is loaded from the contents in the Flash Descriptor.FLREG3.Region Base. PR0--Protected Range 0 Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: Note: MBARB + 74h 00000000h Attribute: Size: R/W 32 bits This register can not be written when the FLOCKDN bit is set to 1. Bit Description 31 Write Protection Enable -- R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that writes and erases directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. 30:29 28:16 15 14:13 12:0 776 RO 32 bits 31:29 12:0 22.4.11 Attribute: Size: Reserved Protected Range Limit -- R/W. This field corresponds to FLA address bits 24:12 and specifies the upper limit of the protected range. Address bits 11:0 are assumed to be FFFh for the limit comparison. Any address greater than the value programmed in this field is unaffected by this protected range. Read Protection Enable -- R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that read directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. Reserved Protected Range Base -- R/W. This field corresponds to FLA address bits 24:12 and specifies the lower base of the protected range. Address bits 11:0 are assumed to be 000h for the base comparison. Any address less than the value programmed in this field is unaffected by this protected range. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Serial Peripheral Interface (SPI) 22.4.12 PR1--Protected Range 1 Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: MBARB + 78h Default Value: 00000000h Note: Bit Description 31 Write Protection Enable -- R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that writes and erases directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. 28:16 15 14:13 12:0 Reserved Protected Range Limit -- R/W. This field corresponds to FLA address bits 24:12 and specifies the upper limit of the protected range. Address bits 11:0 are assumed to be FFFh for the limit comparison. Any address greater than the value programmed in this field is unaffected by this protected range. Read Protection Enable -- R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that read directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. Reserved Protected Range Base -- R/W. This field corresponds to FLA address bits 24:12 and specifies the lower base of the protected range. Address bits 11:0 are assumed to be 000h for the base comparison. Any address less than the value programmed in this field is unaffected by this protected range. SSFS--Software Sequencing Flash Status Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: MBARB + 90h Default Value: 00h Note: R/W 32 bits This register can not be written when the FLOCKDN bit is set to 1. 30:29 22.4.13 Attribute: Size: Attribute: Size: RO, R/WC 8 bits The Software Sequencing control and status registers are reserved if the hardware sequencing control and status registers are used. Bit Description 7 Fast Read Supported -- RO. This bit reflects the value of the Fast Read Support bit in the flash Descriptor Component Section. 6 Dual Output Fast Read Supported -- RO. This bit reflects the value of the Dual Output Fast Read support bit in the Flash Descriptor Component Section. 5 Reserved 4 Access Error Log (AEL) -- RO. This bit reflects the value of the Hardware Sequencing Status AEL register. 3 Flash Cycle Error (FCERR) -- R/WC. Hardware sets this bit to 1 when a programmed access is blocked from running on the SPI interface due to one of the protection policies or when any of the programmed cycle registers is written while a programmed access is already in progress. This bit remains asserted until cleared by software writing a 1 or hardware reset due to a global reset or host partition reset in an Intel ME enabled system. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 777 Serial Peripheral Interface (SPI) 22.4.14 Bit Description 2 Cycle Done Status -- R/WC. The PCH sets this bit to 1 when the SPI Cycle completes (that is, SCIP bit is 0) after software sets the GO bit. This bit remains asserted until cleared by software writing a 1 or hardware reset due to a global reset or host partition reset in an Intel(R) ME enabled system. When this bit is set and the SPI SMI# Enable bit is set, an internal signal is asserted to the SMI# generation block. Software must make sure this bit is cleared prior to enabling the SPI SMI# assertion for a new programmed access. 1 Reserved 0 SPI Cycle In Progress (SCIP) -- RO. Hardware sets this bit when software sets the SPI Cycle Go bit in the Command register. This bit remains set until the cycle completes on the SPI interface. Hardware automatically sets and clears this bit so that software can determine when read data is valid and/or when it is safe to begin programming the next command. Software must only program the next command when this bit is 0. SSFC--Software Sequencing Flash Control Register (GbE LAN Memory Mapped Configuration Registers) Memory Address:MBARB + 91hAttribute: Default Value: 000000h Bit 24 bits Description 23:19 Reserved 18:16 SPI Cycle Frequency (SCF) -- R/W. This register sets frequency to use for all SPI software sequencing cycles (write, erase, fast read, read status, etc.) except for the read cycle which always run at 20 MHz. 000 = 20 MHz 001 = 33 MHz All other values = Reserved. This register is locked when the SPI Configuration Lock-Down bit is set. 15 Reserved 14 Data Cycle (DS) -- R/W. When set to 1, there is data that corresponds to this transaction. When 0, no data is delivered for this cycle, and the DBC and data fields themselves are don't cares. 13:8 7 6:4 3 778 R/W Size: Data Byte Count (DBC) -- R/W. This field specifies the number of bytes to shift in or out during the data portion of the SPI cycle. The valid settings (in decimal) are any value from 0 to 3. The number of bytes transferred is the value of this field plus 1. Note that when this field is 00b, then there is 1 byte to transfer and that 11b means there are 4 bytes to transfer. Reserved Cycle Opcode Pointer (COP) -- R/W. This field selects one of the programmed opcodes in the Opcode Menu to be used as the SPI Command/Opcode. In the case of an Atomic Cycle Sequence, this determines the second command. Sequence Prefix Opcode Pointer (SPOP) -- R/W. This field selects one of the two programmed prefix opcodes for use when performing an Atomic Cycle Sequence. A value of 0 points to the opcode in the least significant byte of the Prefix Opcodes register. By making this programmable, the PCH supports flash devices that have different opcodes for enabling writes to the data space vs. status register. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Serial Peripheral Interface (SPI) 22.4.15 Bit Description 2 Atomic Cycle Sequence (ACS) -- R/W. When set to 1 along with the SCGO assertion, the PCH will execute a sequence of commands on the SPI interface without allowing the LAN component to arbitrate and interleave cycles. The sequence is composed of: * Atomic Sequence Prefix Command (8-bit opcode only) * Primary Command specified below by software (can include address and data) * Polling the Flash Status Register (opcode 05h) until bit 0 becomes 0b. The SPI Cycle in Progress bit remains set and the Cycle Done Status bit remains unset until the Busy bit in the Flash Status Register returns 0. 1 SPI Cycle Go (SCGO) -- R/WS. This bit always returns 0 on reads. However, a write to this register with a `1' in this bit starts the SPI cycle defined by the other bits of this register. The "SPI Cycle in Progress" (SCIP) bit gets set by this action. Hardware must ignore writes to this bit while the Cycle In Progress bit is set. Hardware allows other bits in this register to be programmed for the same transaction when writing this bit to 1. This saves an additional memory write. 0 Reserved PREOP--Prefix Opcode Configuration Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: MBARB + 94h Default Value: 0000h R/W 16 bits Bit Description 15:8 Prefix Opcode 1-- R/W. Software programs an SPI opcode into this field that is permitted to run as the first command in an atomic cycle sequence. 7:0 Prefix Opcode 0 -- R/W. Software programs an SPI opcode into this field that is permitted to run as the first command in an atomic cycle sequence. Note: 22.4.16 Attribute: Size: This register is not writable when the SPI Configuration Lock-Down bit (MBARB + 00h:15) is set. OPTYPE--Opcode Type Configuration Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: MBARB + 96h Default Value: 0000h Attribute: Size: R/W 16 bits Entries in this register correspond to the entries in the Opcode Menu Configuration register. Note: The definition below only provides write protection for opcodes that have addresses associated with them. Therefore, any erase or write opcodes that do not use an address should be avoided (for example, "Chip Erase" and "Auto-Address Increment Byte Program"). Bit Description 15:14 Opcode Type 7 -- R/W. See the description for bits 1:0 13:12 Opcode Type 6 -- R/W. See the description for bits 1:0 11:10 Opcode Type 5 -- R/W. See the description for bits 1:0 9:8 Opcode Type 4 -- R/W. See the description for bits 1:0 7:6 Opcode Type 3 -- R/W. See the description for bits 1:0 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 779 Serial Peripheral Interface (SPI) Bit 5:4 Opcode Type 2 -- R/W. See the description for bits 1:0 3:2 Opcode Type 1 -- R/W. See the description for bits 1:0 1:0 Opcode Type 0 -- R/W. This field specifies information about the corresponding Opcode 0. This information allows the hardware to 1) know whether to use the address field and 2) provide BIOS and Shared Flash protection capabilities. The encoding of the two bits is: 00 = No address associated with this Opcode; Read cycle type 01 = No address associated with this Opcode; Write cycle type 10 = Address required; Read cycle type 11 = Address required; Write cycle type Note: 22.4.17 Description This register is not writable when the SPI Configuration Lock-Down bit (MBARB + 00h:15) is set. OPMENU--Opcode Menu Configuration Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: MBARB + 98h 0000000000000000h Attribute: Size: R/W 64 bits Eight entries are available in this register to give GbE a sufficient set of commands for communicating with the flash device, while also restricting what malicious software can do. This keeps the hardware flexible enough to operate with a wide variety of SPI devices. Note: It is recommended that GbE avoid programming Write Enable opcodes in this menu. Malicious software could then perform writes and erases to the SPI flash without using the atomic cycle mechanism. This could cause functional failures in a shared flash environment. Write Enable opcodes should only be programmed in the Prefix Opcodes. Bit Description 63:56 Allowable Opcode 7 -- R/W. See the description for bits 7:0 55:48 Allowable Opcode 6 -- R/W. See the description for bits 7:0 47:40 Allowable Opcode 5 -- R/W. See the description for bits 7:0 39:32 Allowable Opcode 4 -- R/W. See the description for bits 7:0 31:24 Allowable Opcode 3 -- R/W. See the description for bits 7:0 23:16 Allowable Opcode 2 -- R/W. See the description for bits 7:0 15:8 Allowable Opcode 1 -- R/W. See the description for bits 7:0 7:0 Note: Allowable Opcode 0 -- R/W. Software programs an SPI opcode into this field for use when initiating SPI commands through the Control Register. This register is not writable when the SPI Configuration Lock-Down bit (MBARB + 00h:15) is set. 780 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Thermal Sensor Registers (D31:F6) 23 Thermal Sensor Registers (D31:F6) 23.1 PCI Bus Configuration Registers Table 23-1. Thermal Sensor Register Address Map Offset Mnemonic 00h-01h VID Register Name Default Attribute Vendor Identification 8086h RO 02h-03h DID Device Identification 1D24h RO 04h-05h CMD Command Register 0000h R/W, RO 06h-07h STS Device Status 0010h R/WC, RO 08h RID Revision ID 00h RO 09h PI 0Ah SCC 0Bh BCC Base Class Code 11h RO 0Ch CLS Cache Line Size 00h RO 0Dh LT 0Eh HTYPE Programming Interface 00h RO Sub Class Code 80h RO Latency Timer 00h RO Header Type 00h RO 0Fh BIST Built-in Self Test 00h RO 10h-13h TBAR Thermal Base Address (Memory) 00000004h R/W, RO 14h-17h TBARH Thermal Base Address High DWord 2Ch-2Dh SVID 2Eh-2Fh SID 34h CAP_PTR 00000000h RO Subsystem Vendor Identifier 0000h R/WO Subsystem Identifier 0000h R/WO 50h RO Capabilities Pointer 3Ch INTLN Interrupt Line 00h R/W 3Dh INTPN Interrupt Pin 03h RO 40h-43h TBARB BIOS Assigned Thermal Base Address 00000004h R/W, RO 44h-47h TBARBH BIOS Assigned Thermal Base High DWord 00000000h R/W 50h-51h PID Power Management Identifiers 8001h RO 52h-53h PC Power Management Capabilities 0023h RO 54-57h PCS Power Management Control and Status 0008h R/W, RO Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 781 Thermal Sensor Registers (D31:F6) 23.1.1 VID--Vendor Identification Register Offset Address: 00h-01h Default Value: 8086h Lockable: No Bit 15:0 23.1.2 Vendor ID -- RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h DID--Device Identification Register Bit 15:0 Attribute: Size: RO 16 bits Description Device ID (DID) -- RO. Indicates the device number assigned by the SIG. CMD--Command Register Address Offset: 04h-05h Default Value: 0000h Bit 15:11 10 782 RO 16 bit Core Description Offset Address: 02h-03h Default Value: 1D24h 23.1.3 Attribute: Size: Power Well: Attribute: Size: RO, R/W 16 bits Description Reserved Interrupt Disable (ID) -- R/W. Enables the device to assert an INTx#. 0 = When cleared, the INTx# signal may be asserted. 1 = When set, the Thermal logic's INTx# signal will be deasserted. 9 FBE (Fast Back to Back Enable) -- RO. Not implemented. Hardwired to 0. 8 SEN (SERR Enable) -- RO. Not implemented. Hardwired to 0. 7 WCC (Wait Cycle Control) -- RO. Not implemented. Hardwired to 0. 6 PER (Parity Error Response) -- RO. Not implemented. Hardwired to 0. 5 VPS (VGA Palette Snoop) -- RO. Not implemented. Hardwired to 0. 4 MWI (Memory Write and Invalidate Enable) -- RO. Not implemented. Hardwired to 0. 3 SCE (Special Cycle Enable) -- RO. Not implemented. Hardwired to 0. 2 BME (Bus Master Enable) -- R/W. 0 = Function disabled as bus master. 1 = Function enabled as bus master. 1 Memory Space Enable (MSE) -- R/W. 0 = Disable 1 = Enable. Enables memory space accesses to the Thermal registers. 0 IOS (I/O Space) -- RO. The Thermal logic does not implement IO Space; therefore, this bit is hardwired to 0. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Thermal Sensor Registers (D31:F6) 23.1.4 STS--Status Register Address Offset: 06h-07h Default Value: 0010h Bit 15 Description Detected Parity Error (DPE) -- R/WC. This bit is set whenever a parity error is seen on the internal interface for this function, regardless of the setting of bit 6 in the command register. Software clears this bit by writing a 1 to this bit location. SERR# Status (SERRS) -- RO. Not implemented. Hardwired to 0. 13 Received Master Abort (RMA) -- RO. Not implemented. Hardwired to 0. 12 Received Target Abort (RTA) -- RO. Not implemented. Hardwired to 0. 11 Signaled Target-Abort (STA) -- RO. Not implemented. Hardwired to 0. 8 DEVSEL# Timing Status (DEVT) -- RO. Does not apply. Hardwired to 0. Master Data Parity Error (MDPE) -- RO. Not implemented. Hardwired to 0. 7 Fast Back to Back Capable (FBC) -- RO. Does not apply. Hardwired to 0. 6 Reserved 5 66 MHz Capable (C66) -- RO. Does not apply. Hardwired to 0. 4 Capabilities List Exists (CLIST) -- RO. Indicates that the controller contains a capabilities pointer list. The first item is pointed to by looking at configuration offset 34h. 3 Interrupt Status (IS) -- RO. Reflects the state of the INTx# signal at the input of the enable/ disable circuit. This bit is a 1 when the INTx# is asserted. This bit is a 0 after the interrupt is cleared (independent of the state of the Interrupt Disable bit in the command register). 2:0 Reserved RID--Revision Identification Register Address Offset: 08h Default Value: 00h Bit 7:0 23.1.6 R/WC, RO 16 bits 14 10:9 23.1.5 Attribute: Size: Attribute: Size: RO 8 bits Description Revision ID (RID) -- RO. Indicates the device specific revision identifier. PI-- Programming Interface Register Address Offset: 09h Default Value: 00h Bit 7:0 Attribute: Size: RO 8 bits Description Programming Interface (PI) -- RO. The PCH Thermal logic has no standard programming interface. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 783 Thermal Sensor Registers (D31:F6) 23.1.7 SCC--Sub Class Code Register Address Offset: 0Ah Default Value: 80h Attribute: Size: Bit 7:0 23.1.8 Description Sub Class Code (SCC) -- RO. Value assigned to the PCH Thermal logic. BCC--Base Class Code Register Address Offset: 0Bh Default Value: 11h Attribute: Size: Bit 7:0 23.1.9 Base Class Code (BCC) -- RO. Value assigned to the PCH Thermal logic. CLS--Cache Line Size Register Attribute: Size: Bit 7:0 Cache Line Size (CLS) -- RO. Does not apply to PCI Bus Target-only devices. LT--Latency Timer Register Bit 7:0 Attribute: Size: RO 8 bits Description Latency Timer (LT) -- RO. Does not apply to PCI Bus Target-only devices. HTYPE--Header Type Register Address Offset: 0Eh Default Value: 00h Attribute: Size: RO 8 bits Bit Description 7 Multi-Function Device (MFD) -- RO. This bit is 0 because a multi-function device only needs to be marked as such in Function 0, and the Thermal registers are not in Function 0. 6:0 784 RO 8 bits Description Address Offset: 0Dh Default Value: 00h 23.1.11 RO 8 bits Description Address Offset: 0Ch Default Value: 00h 23.1.10 RO 8 bits Header Type (HTYPE) -- RO. Implements Type 0 Configuration header. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Thermal Sensor Registers (D31:F6) 23.1.12 TBAR--Thermal Base Register Address Offset: 10h-13h Default Value: 00000004h Attribute: Size: R/W, RO 32 bits This BAR creates 4K bytes of memory space to signify the base address of Thermal memory mapped configuration registers. This memory space is active when the Command (CMD) register Memory Space Enable (MSE) bit is set and either TBAR[31:12] or TBARH are programmed to a non-zero address. This BAR is owned by the Operating System, and allows the OS to locate the Thermal registers in system memory space. Bit Description 31:12 Thermal Base Address (TBA) -- R/W. This field provides the base address for the Thermal logic memory mapped configuration registers. 4KB bytes are requested by hardwiring bits 11:4 to 0s. 11:4 3 2:1 0 23.1.13 Reserved Prefetchable (PREF) -- RO. Indicates that this BAR is NOT pre-fetchable. Address Range (ADDRNG) -- RO. Indicates that this BAR can be located anywhere in 64 bit address space. Space Type (SPTYP) -- RO. Indicates that this BAR is located in memory space. TBARH--Thermal Base High DWord Register Address Offset: 14h-17h Default Value: 00000000h Attribute: Size: R/W, RO 32 bits This BAR extension holds the high 32 bits of the 64 bit TBAR. In conjunction with TBAR, it creates 4 KB of memory space to signify the base address of Thermal memory mapped configuration registers. Bit 31:0 23.1.14 Description Thermal Base Address High (TBAH) -- R/W. TBAR bits 63:32. SVID--Subsystem Vendor ID Register Address Offset: 2Ch-2Dh Default Value: 0000h Attribute: Size: R/WO 16 bits This register should be implemented for any function that could be instantiated more than once in a given system. The SVID register, in combination with the Subsystem ID register, enables the operating environment to distinguish one subsystem from the other(s). Software (BIOS) will write the value to this register. After that, the value can be read, but writes to the register will have no effect. The write to this register should be combined with the write to the SID to create one 32-bit write. This register is not affected by D3HOT to D0 reset. Bit 15:0 Description SVID (SVID) -- R/WO. These R/WO bits have no PCH functionality. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 785 Thermal Sensor Registers (D31:F6) 23.1.15 SID--Subsystem ID Register Address Offset: 2Eh-2Fh Default Value: 0000h Attribute: Size: R/WO 16 bits This register should be implemented for any function that could be instantiated more than once in a given system. The SID register, in combination with the Subsystem Vendor ID register make it possible for the operating environment to distinguish one subsystem from the other(s). Software (BIOS) will write the value to this register. After that, the value can be read, but writes to the register will have no effect. The write to this register should be combined with the write to the SVID to create one 32-bit write. This register is not affected by D3HOT to D0 reset. Bit 15:0 23.1.16 Description SID (SAID) -- R/WO. These R/WO bits have no PCH functionality. CAP_PTR --Capabilities Pointer Register Address Offset: 34h Default Value: 50h Bit 7:0 23.1.17 Attribute: Size: Description Capability Pointer (CP) -- RO. Indicates that the first capability pointer offset is offset 50h (Power Management Capability). Offset 3Ch - INTLN--Interrupt Line Register Address Offset: 3Ch Default Value: 00h 23.1.18 Attribute: Size: R/W 8 bits Bit Description 7:0 Interrupt Line -- R/W. PCH hardware does not use this field directly. It is used to communicate to software the interrupt line that the interrupt pin is connected to. INTPN--Interrupt Pin Register Address Offset: 3Dh Default Value: See Description Bit 786 RO 8 bits Attribute: Size: RO 8 bits Description 7:4 RsvdP Reserved 3:0 Interrupt Pin -- RO. This reflects the value of the Device 31 interrupt pin bits 27:24 (TTIP) in chipset configuration space. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Thermal Sensor Registers (D31:F6) 23.1.19 TBARB--BIOS Assigned Thermal Base Address Register Address Offset: 40h-43h Default Value: 00000004h Attribute: Size: R/W,RO 32 bits This BAR creates 4 KB of memory space to signify the base address of Thermal memory mapped configuration registers. This memory space is active when TBARB.SPTYPEN is asserted. This BAR is owned by the BIOS, and allows the BIOS to locate the Thermal registers in system memory space. If both TBAR and TBARB are programmed, then the OS and BIOS each have their own independent "view" of the Thermal registers, and must use the TSIU register to denote Thermal registers ownership/availability. Bit Description 31:12 Thermal Base Address (TBA) -- R/W. This field provides the base address for the Thermal logic memory mapped configuration registers. 4 KB bytes are requested by hardwiring bits 11:4 to 0s. 11:4 3 2:1 0 23.1.20 Reserved Prefetchable (PREF) -- RO. Indicates that this BAR is NOT pre-fetchable. Address Range (ADDRNG) -- RO. Indicates that this BAR can be located anywhere in 64 bit address space. Space Type Enable (SPTYPEN) -- R/W. 0 = Disable. 1 = Enable. When set to 1b by software, enables the decode of this memory BAR. TBARBH--BIOS Assigned Thermal Base High DWord Register Address Offset: 44h-47h Default Value: 00000000h Attribute: Size: R/W 32 bits This BAR extension holds the high 32 bits of the 64 bit TBARB. Bit 31:0 23.1.21 Description Thermal Base Address High (TBAH) -- R/W. TBAR bits 61:32. PID--PCI Power Management Capability ID Register Address Offset: 50h-51h Default Value: 0001h Bit 15:8 7:0 Attribute: Size: RO 16 bits Description Next Capability (NEXT) -- RO. Indicates that this is the last capability structure in the list. Cap ID (CAP) -- RO. Indicates that this pointer is a PCI power management capability Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 787 Thermal Sensor Registers (D31:F6) 23.1.22 PC--Power Management Capabilities Register Address Offset: 52h-53h Default Value: 0023h Bit 15:11 PME_Support -- RO. Indicates PME# is not supported D2_Support -- RO. The D2 state is not supported. 9 D1_Support -- RO. The D1 state is not supported. Aux_Current -- RO. PME# from D3COLD state is not supported, therefore this field is 000b. 5 Device Specific Initialization (DSI) -- RO. Indicates that device-specific initialization is required. 4 Reserved 3 PME Clock (PMEC) -- RO. Does not apply. Hardwired to 0. 2:0 Version (VS) -- RO. Indicates support for Revision 1.2 of the PCI Power Management Specification. PCS--Power Management Control And Status Register Address Offset: 54h-57h Default Value: 00000008h Bit 31:24 Attribute: Size: RO, R/W 32 bits Description Data -- RO. Does not apply. Hardwired to 0s. 23 Bus Power/Clock Control Enable (BPCCE) -- RO. Hardwired to 0. 22 B2/B3 Support (B23) -- RO. Does not apply. Hardwired to 0. 21:16 15 14:9 8 7:4 Reserved PME Status (PMES) -- RO. This bit is always 0, since this PCI Function does not generate PME# Reserved PME Enable (PMEE) -- RO. This bit is always zero, since this PCI Function does not generate PME# Reserved 3 No Soft Reset -- RO. When set to 1, this bit indicates that devices transitioning from D3HOT to D0 because of PowerState commands do not perform an internal reset. Configuration context is preserved. Upon transition from D3HOT to D0 initialized state, no additional operating system intervention is required to preserve Configuration Context beyond writing the PowerState bits. 2 Reserved 1:0 788 RO 16 bits Description 10 8:6 23.1.23 Attribute: Size: Power State (PS) -- R/W. This field is used both to determine the current power state of the Thermal controller and to set a new power state. The values are: 00 = D0 state 11 = D3HOT state If software attempts to write a value of 10b or 01b in to this field, the write operation must complete normally; however, the data is discarded and no state change occurs. When in the D3HOT states, the Thermal controller's configuration space is available, but the I/O and memory spaces are not. Additionally, interrupts are blocked. When software changes this value from the D3HOT state to the D0 state, no internal warm (soft) reset is generated. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Thermal Sensor Registers (D31:F6) 23.2 Thermal Memory Mapped Configuration Registers (Thermal Sensor - D31:F26) The base memory for these thermal memory mapped configuration registers is specified in the TBARB (D31:F6:Offset 40h). The individual registers are then accessible at TBARB + Offset. Table 23-2. Thermal Memory Mapped Configuration Register Address Map 23.2.1 Default Host Attribute ME Attribute Thermal Sensor In Use 00h RO, R/W TSE Thermal Sensor Enable 00h R/W TSS Thermal Sensor Status 00h R/W Offset Mnemonic 0h TSIU 1h 2h Register Name 3h TSTR Thermal Sensor Thermometer Read 4-7h TSTTP Thermal Sensor Temperature Trip Point FFh RO 00000000h R/W 8h TSC0 Thermal Sensor Catastrophic Lock Down 00h R/W 0Ch TSES Thermal Sensor Error Status 00h R/WC 0Dh TSGPEN 0Eh TSPC Thermal Sensor General Purpose Event Enable 00h R/W Thermal Sensor Policy Control 00h R/W, RO 14-15h PTA PCH Temperature Adjust 0000h R/W 1A-1Bh TRC Thermal Reporting control 0000h R/W 3Fh AE Alert enable 56-57h PTL Processor Temperature Limit 60-61h PTV 6C-6Fh TT Processor Temperature Value Thermal Throttling 00h R/W 0000h R/W 0000h RO 00000000h R/W 70h PHL PCH Hot Level 00h R/W 82h TSPIEN Thermal Sensor PCI Interrupt Event enable 00h R/W Thermal Sensor Register Lock Controls 00h R/W 00000000h RO 83H TSLOCK AC-AFh TC2 B0-B3h DTV DIMM Temperature values 00000000h RO D8-DBh ITV Internal Temperature Values 00000000h RO Thermal Compares 2 TSIU--Thermal Sensor In Use Register Offset Address: Default Value: TBARB+00h 00h Bit 7:1 0 Attribute: Size: RO, R/W 8 bit Description Reserved. Thermal Sensor In Use (TSIU) -- R/W. This is a SW semaphore bit. After a core well reset, a read to this bit returns a 0. After the first read, subsequent reads will return a 1. A write of a 1 to this bit will reset the next read value to 0. Writing a 0 to this bit has no effect. Software can poll this bit until it reads a 0, and will then own the usage of the thermal sensor. This bit has no other effect on the hardware, and is only used as a semaphore among various independent software threads that may need to use the thermal sensor. Software that reads this register but does not intend to claim exclusive access of the thermal sensor must write a 1 to this bit if it reads a 0, in order to allow other software threads to claim it. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 789 Thermal Sensor Registers (D31:F6) 23.2.2 TSE--Thermal Sensor Enable Register Offset Address: Default Value: 23.2.3 TBARB+01h 00h R/W 8 bit Bit Description 7:0 Thermal Sensor Enable (TSE) -- R/W BIOS programs this register to enable the thermal sensor. TSS--Thermal Sensor Status Register Offset Address: Default Value: TBARB+02h 00h Bit Attribute: Size: RO 8 bit Description 7 Catastrophic Trip Indicator (CTI) -- RO. 0 = The temperature is below the catastrophic setting. 1 = The temperature is above the catastrophic setting. 6 Hot Trip Indicator (HTI) -- RO. 0 = The temperature is below the Hot setting. 1 = The temperature is above the Hot setting. 5 Auxiliary Trip Indicator (ATI) -- RO. 0 = The temperature is below the Auxiliary setting. 1 = The temperature is above the Auxiliary setting. 4 Reserved 3 Auxiliary2 Trip Indicator (ATI) -- RO. 0 = The temperature is below the Auxiliary2 setting. 1 = The temperature is above the Auxiliary2 setting. 2:0 23.2.4 Attribute: Size: Reserved TSTR -- Thermal Sensor Thermometer Read Register Offset Address: Default Value: TBARB+03h yFh (y = x111b) Attribute: Size: RO 8 bit This register generally provides the current calibrated temperature from the thermometer circuit when the thermometer is enabled. Bit 7 Description Reserved Thermometer Reading (TR)-- R/O. Value corresponds to the thermal sensor temperature. A 6:0 790 value of 00h means the hottest temperature and 7Fh is the lowest. The range is approximately between 40 C to 130 C. Temperature below 40 C will be truncated to 40 C. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Thermal Sensor Registers (D31:F6) 23.2.5 TSTTP--Thermal Sensor Temperature Trip Point Register Offset Address:TBARB+04hAttribute:R/W Default Value: 00000000hSize: Bit Description 31:24 Auxiliary2 Trip Point Setting (A2TPS) -- R/W. These bits set the Auxiliary2 trip point. These bits are lockable by programming the policy-lock down bit (bit 7) of TSPC register. These bits may only be programmed from 0h to 7Fh. Setting bit 31 is illegal. 23:16 Auxiliary Trip Point Setting (ATPS) -- R/W. These bits set the Auxiliary trip point. These bits are lockable using programming the policy-lock down bit (bit 7) of TSPC register. These bits may only be programmed from 0h to 7Fh. Setting bit 23is illegal. 15:8 7:0 23.2.6 Hot Trip Point Setting (HTPS) -- R/W. These bits set the Hot trip point. These bits are lockable by programming the policy-lock down bit (bit 7) of TSPC register. These bits may only be programmed from 0h to 7Fh. Setting bit 15 is illegal. BIOS should program to 3Ah for setting Hot Trip Point to 108 C. Catastrophic Trip Point Setting (CTPS) -- R/W. These bits set the catastrophic trip point. These bits are lockable using TSCO.bit 7. These bits may only be programmed from 0h to 7Fh. Setting bit 7 is illegal. BIOS should program to 2Bh for setting Catastrophic Trip Point to 120 C. TSCO--Thermal Sensor Catastrophic Lock-Down Register Offset Address: Default Value: TBARB+08h 00h Bit 7 6:0 23.2.7 32 bit Attribute: Size: R/W 8 bit Description Lock bit for Catastrophic (LBC) -- R/W 0 = Catastrophic programming interface is unlocked 1 = Locks the Catastrophic programming interface including TSTTP.bits[7:0]. This bit may only be set to a 0 by a host partitioned reset (note that CF9 warm reset is a host partitioned reset). Writing a 0 to this bit has no effect. TSCO.[7] is unlocked by default and can be locked through BIOS. Reserved TSES--Thermal Sensor Error Status Register Offset Address: TBARB+0Ch Default Value: 00h Bit Attribute: Size: R/WC 8 bit Description 7 Auxiliary2 High-to-LowEvent -- R/WC. 0 = No trip occurs. 1 = Indicates that an Auxiliary2 Thermal Sensor trip event occurred based on a higher to lower temperature transition through the trip point. Software must write a 1 to clear this status bit. 6 Catastrophic High-to-LowEvent -- R/WC. 0 = No trip occurs. 1 = Indicates that a Catastrophic Thermal Sensor trip event occurred based on a higher to lower temperature transition through the trip point. 1 = Software must write a 1 to clear this status bit. 5 Hot High-to-LowEvent -- R/WC. 0 = No trip occurs. 1 = Indicates that a Hot Thermal Sensor trip event occurred based on a higher to lower temperature transition through the trip point. Software must write a 1 to clear this status bit. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 791 Thermal Sensor Registers (D31:F6) Bit 23.2.8 Description 4 Auxiliary High-to-LowEvent -- R/WC. 0 = No trip occurs. 1 = Indicates that an Auxiliary Thermal Sensor trip event occurred based on a higher to lower temperature transition through the trip point. Software must write a 1 to clear this status bit. 3 Auxiliary2 Low-to-High Event -- R/WC. 0 = No trip occurs. 1 = Indicates that an Auxiliary2 Thermal Sensor trip event occurred based on a lower to higher temperature transition through the trip point. Software must write a 1 to clear this status bit. 2 Catastrophic Low-to-High Event -- R/WC. 0 = No trip occurs. 1 = Indicates that a Catastrophic Thermal Sensor trip event occurred based on a lower to higher temperature transition through the trip point. Software must write a 1 to clear this status bit. 1 Hot Low-to-High Event -- R/WC. 0 = No trip occurs. 1 = Indicates that a hot Thermal Sensor trip event occurred based on a lower to higher temperature transition through the trip point. Software must write a 1 to clear this status bit. 0 Auxiliary Low-to-High Event -- R/WC. 0 = No trip occurs. 1 = Indicates that an Auxiliary Thermal Sensor trip event occurred based on a lower to higher temperature transition through the trip point. Software must write a 1 to clear this status bit. TSGPEN--Thermal Sensor General Purpose Event Enable Register Offset Address: Default Value: TBARB+0Dh 00h Attribute: Size: R/W 8 bit This register controls the conditions that result in General Purpose Events to be signalled from Thermal Sensor trip events. Bit 792 Description 7 Auxiliary2 High-to-Low Enable -- R/W. 0 = Corresponding status bit does not result in General Purpose event. 1 = General purpose event is signaled when the corresponding status bit is set in the Thermal Error Status Register. 6 Catastrophic High-to-Low Enable -- R/W. 0 = Corresponding status bit does not result in General Purpose event. 1 = General purpose event is signaled when the corresponding status bit is set in the Thermal Error Status Register. 5 Hot High-to-Low Enable -- R/W. 0 = Corresponding status bit does not result in General Purpose event. 1 = General purpose event is signaled when the corresponding status bit is set in the Thermal Error Status Register. 4 Auxiliary High-to-Low Enable -- R/W. 0 = Corresponding status bit does not result in General Purpose event. 1 = General purpose event is signaled when the corresponding status bit is set in the Thermal Error Status Register. 3 Auxiliary2 Low-to-High Enable -- R/W. 0 = Corresponding status bit does not result in General Purpose event. 1 = General purpose event is signaled when the corresponding status bit is set in the Thermal Error Status Register. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Thermal Sensor Registers (D31:F6) Bit 23.2.9 Description 2 Catastrophic Low-to-High Enable -- R/W. 0 = Corresponding status bit does not result in General Purpose event. 1 = General purpose event is signaled when the corresponding status bit is set in the Thermal Error Status Register. 1 Hot Low-to-High Enable-- R/W. 0 = Corresponding status bit does not result in General Purpose event. 1 = General purpose event is signaled when the corresponding status bit is set in the Thermal Error Status Register. 0 Auxiliary Low-to-High Enable -- R/W. 0 = Corresponding status bit does not result in General Purpose event. 1 = General purpose event is signaled when the corresponding status bit is set in the Thermal Error Status Register. TSPC--Thermal Sensor Policy Control Register Offset Address: Default Value: TBARB+0Eh 00h Bit Attribute: Size: R/W, RO 8 bit Description Policy Lock-Down Bit -- R/W. 0 = This register can be programmed and modified. 1 = Prevents writes to this register and TSTTP.bits [31:16] (offset 04h). 7 6 Note: TSCO.bit 7 (offset 08h) and TSLOCK.bit2 (offset 83h) must also be 1 when this bit is set to 1. This bit is reset to 0 by a host partitioned reset (note that CF9 warm reset is a host partitioned reset). Writing a 0 to this bit has no effect. Catastrophic Power-Down Enable -- R/W. When set to 1, the power management logic unconditionally transitions to the S5 state when a catastrophic temperature is detected by the sensor. Note: 5:4 BIOS should set this bit to 1 to enable Catastrophic power-down. Reserved 3 SMI Enable on Auxiliary2 Thermal Sensor Trip -- R/W. 0 = Disables SMI# assertion for Auxiliary2 Thermal Sensor events. 1 = Enables SMI# assertions on Auxiliary2 Thermal Sensor events for either low-to-high or high-tolow events. (Both edges are enabled by this bit.) 2 SMI Enable on Catastrophic Thermal Sensor Trip -- R/W. 0 = Disables SMI# assertion for Catastrophic Thermal Sensor events. 1 = Enables SMI# assertions on Catastrophic Thermal Sensor events for either low-to-high or highto-low events. (Both edges are enabled by this bit.) 1 SMI Enable on Hot Thermal Sensor Trip -- R/W. 0 = Disables SMI# assertion for Hot Thermal Sensor events. 1 = Enables SMI# assertions on Hot Thermal Sensor events for either low-to-high or high-to-low events. (Both edges are enabled by this bit.) 0 SMI Enable on Auxiliary Thermal Sensor Trip -- R/W. 0 = Disables SMI# assertion for Auxiliary Thermal Sensor events. 1 = Enables SMI# assertions on Auxiliary Thermal Sensor events for either low-to-high or high-tolow events. (Both edges are enabled by this bit.) Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 793 Thermal Sensor Registers (D31:F6) 23.2.10 PTA--PCH Temperature Adjust Register Offset Address: TBARB+14h Default Value: 0000h Bit Attribute: Size: R/W 16 bit Description PCH Slope (PSLOPE) -- R/W. This field contains the PCH slope for calculating PCH 15:8 temperature. The bits are locked by AE.bit7 (offset 3Fh). Note: When thermal reporting is enabled, BIOS must write DEh into this field. Offset (POFFSET) -- R/W This field contains the PCH offset for calculating PCH 7:0 temperature. The bits are locked by AE.bit7 (offset 3Fh). Note: 23.2.11 When thermal reporting is enabled, BIOS must write 87h into this field. TRC--Thermal Reporting Control Register Offset Address: TBARB+1Ah Default Value: 0000h Bit 15:13 12 11:6 5 794 Attribute: Size: R/W 16 bit Description Reserved SMBUS Thermal Data Reporting Enable -- R/W. 0 = Disable 1 = Enable Reserved PCH Temperature Read Enable -- R/W. 0 = Disables reads of the PCH temperature. 1 = Enables reads of the PCH temperature. 4 Reserved - This bit must be set to 0. 3 DIMM4 Temperature Read Enable -- R/W 0 = Disables reads of DIMM4 temperature. 1 = Enables reads of DIMM4 temperature. 2 DIMM3 Temperature Read Enable --R/W 0 = Disables reads of DIMM3 temperature. 1 = Enables reads of DIMM3 temperature. 1 DIMM2 Temperature Read Enable --R/W 0 = Disables reads of DIMM2 temperature. 1 = Enables reads of DIMM2 temperature. 0 DIMM1 Temperature Read Enable --R/W. 0 = Disables reads of DIMM1 temperature. 1 = Enables reads of DIMM1 temperature. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Thermal Sensor Registers (D31:F6) 23.2.12 AE--Alert Enable Register Offset Address: TBARB+3Fh Default Value: 00h Description 7 Lock Enable -- R/W. 0 = Lock Disabled. 1 = Lock Enabled. This will lock this register (including this bit) This bit is reset by a Host Partitioned Reset. Note that CF9 warm reset is a Host Partitioned Reset. Reserved 4 PCH Alert Enable -- R/W. 0 = Alert Disabled 1 = Alert Enabled When this bit is set, it will assert the PCH's TEMP_ALERT# signal if the PCH temperature is outside the temperature limits. This bit is lockable by bit 7 in this register. 3 DIMM 1-4 Alert Enable -- R/W. 0 = Alert Disabled 1 = Alert Enabled When this bit is set, it will assert the PCH's TEMP_ALERT# signal if DIMM1-4 temperature is outside of the temperature limits. Note that the actual DIMMs that are read and used for the alert are enabled in the TRC register (offset 1Ah). This bit is lockable by bit 7 in this register. Note: Same Upper and Lower limits for triggering TEMP_ALERT# are used for all enabled DIMMs in the system. 2:0 Reserved. PTL--Processor Temperature Limit Register Offset Address: TBARB+56h Default Value: 0000h Bit 15:0 23.2.14 Attribute: Size: R/W 16 bit Description Processor Temperature Limit -- R/W. These bits are programmed by BIOS PTV--Processor Temperature Value Register Offset Address: TBARB+60h Default Value: 0000h Bit 15:8 7:0 23.2.15 R/W 8 bit Bit 6:5 23.2.13 Attribute: Size: Attribute: Size: RO 16 bit Description Reserved Processor Temperature Value-- RO. These bits contain the processor package temperature. TT--Thermal Throttling Register Offset Address: TBARB+6Ch Default Value: 00000000h Bit 31:0 Attribute: Size: R/W 32 bit Description BIOS must program this field to 05201B16h Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 795 Thermal Sensor Registers (D31:F6) 23.2.16 PHL--PCH Hot Level Register Offset Address: TBARB+70h Default Value: 00h 23.2.17 Attribute: Size: R/W 8 bit Bit Description 7:0 PCH Hot Level (PHL)-- R/W. When temperature reading in Thermal Sensor Thermometer Read (TSTR) is less than PHL programmed here, this will assert PCHHOT# (active low). (Note that TSTR reading of 00h is the hottest temperature and 7Fh is the lowest temperature.) Default state for this register is PHL disabled (00h). For utilizing the PCHHOT# functionality, a soft strap has to be configured and BIOS programs this PHL value. Please refer to the Intel ME FW collaterals for information on enabling PCHHOT#. TSPIEN--Thermal Sensor PCI Interrupt Enable Register Offset Address: TBARB+82h Default Value: 00h Attribute: Size: R/W 8 bit This register controls the conditions that result in PCI interrupts to be signalled from Thermal Sensor trip events. Software (device driver) needs to ensure that it can support PCI interrupts, even though BIOS may enable PCI interrupt capability through this register. 796 Bit Description 7 Auxiliary2 High-to-Low Enable -- R/W. 0 = Corresponding status bit does not result in PCI interrupt. 1 = PCI interrupt is signaled when the corresponding status bit is set in the Thermal Error Status Register. 6 Catastrophic High-to-Low Enable -- R/W. 0 = Corresponding status bit does not result in PCI interrupt. 1 = PCI interrupt is signalled when the corresponding status bit is set in the Thermal Error Status Register. 5 Hot High-to-Low Enable -- R/W. 0 = Corresponding status bit does not result in PCI interrupt. 1 = PCI interrupt is signaled when the corresponding status bit is set in the Thermal Error Status Register. 4 Auxiliary High-to-Low Enable -- R/W. 0 = Corresponding status bit does not result in PCI interrupt. 1 = PCI interrupt is signaled when the corresponding status bit is set in the Thermal Error Status Register. 3 Auxiliary2 Low-to-High Enable -- R/W. 0 = Corresponding status bit does not result in PCI interrupt. 1 = PCI interrupt is signaled when the corresponding status bit is set in the Thermal Error Status Register. 2 Catastrophic Low-to-High Enable -- R/W. 0 = Corresponding status bit does not result in PCI interrupt. 1 = PCI interrupt is signalled when the corresponding status bit is set in the Thermal Error Status Register. 1 Hot Low-to-High Enable-- R/W. 0 = Corresponding status bit does not result in PCI interrupt. 1 = PCI interrupt is signaled when the corresponding status bit is set in the Thermal Error Status Register. 0 Auxiliary Low-to-High Enable -- R/W. 0 = Corresponding status bit does not result in PCI interrupt. 1 = PCI interrupt is signaled when the corresponding status bit is set in the Thermal Error Status Register. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Thermal Sensor Registers (D31:F6) 23.2.18 TSLOCK--Thermal Sensor Register Lock Control Register Offset Address: TBARB+83h Default Value: 00h Attribute: Size: R/W 8 bit T Bit 7:3 2 1:0 23.2.19 Description Reserved Lock Control-- R/W. This bit can only be set to a 0 by a host-partitioned reset. Writing a 0 to this bit has no effect. 1 = Hot Trip programming interface (bits [15:8] of TSTTP. is locked. Note: CF9 warm reset is a host-partitioned reset. Reserved TTC2--Thermal Compares 2 Register Offset Address: TBARB+ACh Default Value: 00000000h Attribute: Size: RO 32 bit Bits [31:16] of this register are set when an external controller (for example, EC) does the Write DIMM Temp Limits Command. Refer to Section 5.22.2 for more info. Bits [15:0] of this register are set when an external controller (for example, EC) does the Write PCH Temp Limits Command. Refer to Section 5.22.2 for more information. Bit 23.2.20 Description 31:24 DIMM Thermal Compare Upper Limit -- RO. This is the upper limit used to compare against the DIMM's temperature. If the DIMM's temperature is greater than this value, then the PCH's alert GPIOl is asserted if enabled. 23:16 DIMM Thermal Compare Lower Limit -- RO. This is the lower limit used to compare against the DIMM's temperature. If the DIMM's temperature is lower than this value, then the PCH's alert GPIO is asserted if enabled. 15:8 PCH Thermal Compare Upper Limit -- RO. This is the upper limit used to compare against the PCH temperature. If the PCH temperature is greater than this value, then the PCH's alert GPIO is asserted if enabled. 7:0 PCH Thermal Compare Lower Limit -- RO. This is the lower limit used to compare against the PCH temperature. If the PCH temperature is lower than this value, then the PCH's alert GPIO is asserted if enabled. DTV--DIMM Temperature Values Register Offset Address: TBARB+B0h Default Value: 00000000h Bit Attribute: Size: RO 32 bit Description 31:24 DIMM3 Temperature -- RO The bits contain DIMM3 temperature data in absolute degrees Celsius. These bits are data byte 8 provided to the external controller when it does a read over SMLink1. Refer to Section 5.23.2 for more details 23:16 DIMM2 Temperature -- RO The bits contain DIMM2 temperature data in absolute degrees Celsius. These bits are data byte 7 provided to the external controller when it does a read over SMLink1. Refer to Section 5.23.2 for more details. 15:8 DIMM1 Temperature -- RO The bits contain DIMM1 temperature data in absolute degrees Celsius. These bits are data byte 6 provided to the external controller when it does a read over SMLink1. Refer to Section 5.23.2 for more details. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 797 Thermal Sensor Registers (D31:F6) Bit 7:0 23.2.21 Description DIMM0 Temperature -- RO The bits contain DIMM0 temperature data in absolute degrees Celsius. These bits are data byte 5 provided to the external controller when it does a read over SMLink1. Refer to Section 5.23.2 for more details. ITV--Internal Temperature Values Register Offset Address: TBARB+D8h Default Value: 00000000h Bit Attribute: Size: RO 32 bit Description 31:24 Reserved 23:16 Sequence Number -- RO Provides a sequence number which can be used by the host to detect if the Intel ME FW has hung. The value will roll over to 00h from 0Fh. The count is updated at approximately 200 ms. Host SW can check this value and if it isn't incriminated over a second or so, software should assume that the Intel ME FW is hung. Note: If the Intel ME is reset, then this value will not change during the reset. After the reset is done, which may take up to 30 seconds, the Intel ME may be on again and this value will start incrementing, indicating that the thermal values are valid again. These bits are data byte 9 provided to the external controller when it does a read over SMLink1. Refer to Section 5.23.2 for more details. 15:8 7:0 Reserved PCH Temperature -- RO The bits contain PCH temperature data in absolute degrees Celsius. These bits are data byte 1 provided to the external controller when it does a read over SMLink1. Refer to Section 5.23.2 for more details. 798 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) Note: The HEDT SKU Only supports D22:F0. 24.1 First Intel(R) Management Engine Interface (Intel MEI) Configuration Registers (Intel MEI 1 -- D22:F0) 24.1.1 PCI Configuration Registers (Intel MEI 1-- D22:F0) Table 24-1. Intel MEI 1 Configuration Registers Address Map (Intel MEI 1 --D22:F0) (Sheet 1 of 2) Offset Mnemonic 00h-01h VID 02h-03h DID 04h-05h PCICMD PCI Command 06h-07h PCISTS PCI Status 08h RID Register Name Default Attribute Vendor Identification 8086h RO Device Identification See register description RO 0000h R/W, RO Revision Identification 09h-0Bh CC Class Code 0Ch CLS Cache Line Size 0Dh PLT 0Eh HTYPE 10h-17h MEI0_MBAR 2Ch-2Dh SVID 0010h RO See register description RO 078000h RO 00h RO Primary Latency Timer 00h RO Header Type 80h RO 00000000 00000004h R/W, RO Subsystem Vendor ID 0000h R/WO Subsystem ID 0000h R/WO 50h RO MEI0 MMIO Base Address 2Eh-2Fh SID 34h CAPP Capabilities List Pointer 3Ch-3Dh INTR Interrupt Information 0000h R/W, RO 40h-43h HFS Host Firmware Status 00000000h RO 44h-47h ME_UMA 8000000h RO 48-4Bh GMES General Intel ME Status 00000000h RO 4Ch-4Fh H_GS Host General Status 50h-51h PID 52h-53h Intel ME UMA Register 00000000h RO PCI Power Management Capability ID 6001h RO PC PCI Power Management Capabilities C803h RO 54h-55h PMCS PCI Power Management Control and Status 0008h R/WC, R/W, RO 8Ch-8Dh MID Message Signaled Interrupt Identifiers 0005h RO MC Message Signaled Interrupt Message Control 0080h R/W, RO 8Eh-8Fh Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 799 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) Table 24-1. Intel MEI 1 Configuration Registers Address Map (Intel MEI 1 --D22:F0) (Sheet 2 of 2) 24.1.1.1 Offset Mnemonic 90h-93h MA 94h-97h MUA 98h-99h MD A0h HIDM BC-BF HERES C0-DF HER[1:8] Register Name Default Attribute Message Signaled Interrupt Message Address 00000000h R/W, RO Message Signaled Interrupt Upper Address 00000000h R/W 0000h R/W Message Signaled Interrupt Message Data 00h R/W Intel MEI Extended Register Status Intel MEI Interrupt Delivery Mode 40000000h RO Intel MEI Extended Register DW[1:8] 00000000h RO VID--Vendor Identification Register (Intel MEI 1--D22:F0) Address Offset: 00h-01h Default Value: 8086h Bit 15:0 24.1.1.2 Vendor ID (VID) -- RO. This is a 16-bit value assigned to Intel. DID--Device Identification Register (Intel MEI 1--D22:F0) Bit 15:0 Attribute: Size: RO 16 bits Description Device ID (DID) -- RO. This is a 16-bit value assigned to the Intel MEI controller. Refer to the Intel(R) C600 Series Chipset Specification Update for the value of the Device ID Register. PCICMD--PCI Command Register (Intel MEI 1--D22:F0) Address Offset: 04h-05h Default Value: 0000h Bit 15:11 800 RO 16 bits Description Address Offset: 02h-03h Default Value: See bit description 24.1.1.3 Attribute: Size: Attribute: Size: R/W, RO 16 bits Description Reserved 10 Interrupt Disable (ID) -- R/W. Disables this device from generating PCI line based interrupts. This bit does not have any effect on MSI operation. 9:3 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) Bit 2 Description Bus Master Enable (BME): Controls the Intel MEI host controller's ability to act as a system memory master for data transfers. When this bit is cleared, Intel MEI bus master activity stops and any active DMA engines return to an idle condition. This bit is made visible to firmware through the H_PCI_CSR register, and changes to this bit may be configured by the H_PCI_CSR register to generate an Intel ME MSI. When this bit is '0', Intel MEI is blocked from generating MSI to the host CPU. Note: 24.1.1.4 This bit does not block Intel MEI accesses to Intel ME-UMA; that is, writes or reads to the host and Intel ME circular buffers through the read window and write window registers still cause Intel ME backbone transactions to Intel ME-UMA. 1 Memory Space Enable (MSE) -- R/W. Controls access to the Intel MEI's memory mapped register space. 0 = Disable. Memory cycles within the range specified by the memory base and limit registers are master aborted. 1 = Enable. Allows memory cycles within the range specified by the memory base and limit registers accepted. 0 I/O Space Enable (IOSE) -- RO. Not implemented, hardwired to 0. PCISTS--PCI Status Register (Intel MEI 1--D22:F0) Address Offset: 06h-07h Default Value: 0010h Attribute: Size: Bit 15:5 Description Reserved 4 Capabilities List (CL) -- RO. Indicates the presence of a capabilities list, hardwired to 1. 3 Interrupt Status -- RO. Indicates the interrupt status of the device. 0 = Interrupt is deasserted. 1 = Interrupt is asserted. 2:0 24.1.1.5 Reserved RID--Revision Identification Register (Intel MEI 1--D22:F0) Offset Address: 08h Default Value: See bit description Bit 7:0 24.1.1.6 RO 16 bits Attribute: Size: RO 8 bits Description Revision ID -- RO. Refer to the Revision ID Register Intel(R) C600 Series Chipset Specification Update for the value of the CC--Class Code Register (Intel MEI 1--D22:F0) Address Offset: 09h-0Bh Default Value: 078000h Bit 23:16 15:8 7:0 Attribute: Size: RO 24 bits Description Base Class Code (BCC) -- RO. Indicates the base class code of the Intel MEI device. Sub Class Code (SCC) -- RO. Indicates the sub class code of the Intel MEI device. Programming Interface (PI) -- RO. Indicates the programming interface of the Intel MEI device. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 801 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.1.1.7 HTYPE--Header Type Register (Intel MEI 1--D22:F0) Address Offset: 0Eh Default Value: 80h Bit 7 6:0 24.1.1.8 Attribute: Size: RO 8 bits Description Multi-Function Device (MFD) -- RO. Indicates the Intel MEI host controller is part of a multifunction device. Header Layout (HL) -- RO. Indicates that the Intel MEI uses a target device layout. MEI0_MBAR--MEI 1 MMIO Base Address Register (Intel MEI 1--D22:F0) Address Offset: 10h-17h Default Value: 0000000000000004h Attribute: Size: R/W, RO 64 bits This register allocates space for the MEI0 memory mapped registers. Bit 63:4 3 2:1 0 24.1.1.9 Description Base Address (BA) -- R/W. Software programs this field with the base address of this region. Prefetchable Memory (PM) -- RO. Indicates that this range is not pre-fetchable. Type (TP) -- RO. Set to 10b to indicate that this range can be mapped anywhere in 64-bit address space. Resource Type Indicator (RTE) -- RO. Indicates a request for register memory space. SVID--Subsystem Vendor ID Register (Intel MEI 1--D22:F0) Address Offset: 2Ch-2Dh Default Value: 0000h Bit 15:0 Note: 24.1.1.10 R/WO 16 bits Description Subsystem Vendor ID (SSVID) -- R/WO. Indicates the sub-system vendor identifier. This field should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This field can only be cleared by PLTRST#. Register must be written as a Word write or as a DWord write with SID register. SID--Subsystem ID Register (Intel MEI 1--D22:F0) Address Offset: 2Eh-2Fh Default Value: 0000h Attribute: Size: R/WO 16 bits Bit Description 15:0 Subsystem ID (SSID) -- R/WO. Indicates the sub-system identifier. This field should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This field can only be cleared by PLTRST#. Note: 802 Attribute: Size: Register must be written as a Word write or as a DWord write with SVID register. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.1.1.11 CAPP--Capabilities List Pointer Register (Intel MEI 1--D22:F0) Address Offset: 34h Default Value: 50h Bit 7:0 24.1.1.12 Capabilities Pointer (PTR) -- RO. Indicates that the pointer for the first entry in the capabilities list is at 50h in configuration space. INTR--Interrupt Information Register (Intel MEI 1--D22:F0) Attribute: Size: R/W, RO 16 bits Bit Description 15:8 Interrupt Pin (IPIN) -- RO. This indicates the interrupt pin the Intel MEI host controller uses. A value of 1h/2h/3h/4h indicates that this function implements legacy interrupt on INTA/INTB/INTC/ INTD, respectively. The upper 4 bits are hardwired to 0 and the lower 4 bits are programmed by the MEI1IP bits (RCBA+3124:bits 3:0). 7:0 Interrupt Line (ILINE) -- R/W. Software written value to indicate which interrupt line (vector) the interrupt is connected to. No hardware action is taken on this register. HFS--Host Firmware Status Register (Intel MEI 1--D22:F0) Address Offset: 40h-43h Default Value: 00000000h 24.1.1.14 RO 8 bits Description Address Offset: 3Ch-3Dh Default Value: 0100h 24.1.1.13 Attribute: Size: Attribute: Size: RO 32 bits Bit Description 31:0 Host Firmware Status (HFS) -- RO. This register field is used by Firmware to reflect the operating environment to the host. ME_UMA--Intel(R) Management Engine UMA Register (Intel MEI 1--D22:F0) Address Offset: 44h-47h Default Value: 80000000h Attribute: Size: RO 32 bits Bit Description 31 Reserved-- RO. Hardwired to 1. Can be used by host software to discover that this register is valid. 30:7 16 15:6 5:0 Reserved Intel ME UMA Size Valid -- RO. This bit indicates that FW has written to the MUSZ field. Reserved Intel ME UMA Size (MUSZ) -- RO. This field reflect Intel ME Firmware's desired size of MEUMA memory region. This field is set by Intel ME firmware prior to core power bringup allowing BIOS to initialize memory. 000000b = 0 MB, No memory allocated to MEUMA 000001b = 1 MB 000010b = 2 MB 000100b = 4 MB 001000b = 8 MB 010000b = 16 MB 100000b = 32 MB Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 803 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.1.1.15 GMES--General Intel(R) ME Status (Intel MEI 1--D22:F0) Address Offset: 48h-4Bh Default Value: 00000000h Bit 31:0 24.1.1.16 General Intel ME Status (ME_GS)-- RO. This field is populated by Intel ME. H_GS--Host General Status (Intel MEI 1--D22:F0) Bit 31:0 RO 32 bits Host General Status(H_GS)-- RO. General Status of Host, this field is not used by Hardware PID--PCI Power Management Capability ID Register (Intel MEI 1--D22:F0) Bit 15:8 7:0 Attribute: Size: RO 16 bits Description Next Capability (NEXT) -- RO. Value of 8Ch indicates the location of the next pointer. Capability ID (CID) -- RO. Indicates the linked list item is a PCI Power Management Register. PC--PCI Power Management Capabilities Register (Intel MEI 1--D22:F0) Address Offset: 52h-53h Default Value: C803h Bit 15:11 Attribute: Size: RO 16 bits Description PME_Support (PSUP) -- RO. This five-bit field indicates the power states in which the function may assert PME#. Intel MEI can assert PME# from any D-state except D1 or D2 which are not supported by Intel MEI. 10 D2_Support (D2S) -- RO. The D2 state is not supported. 9 D1_Support (D1S) -- RO. The D1 state is not supported. 8:6 Aux_Current (AC) -- RO. Reports the maximum Suspend well current required when in the D3cold state. Value of 00b is reported. 5 Device Specific Initialization (DSI) -- RO. Indicates whether device-specific initialization is required. 4 Reserved 3 PME Clock (PMEC) -- RO. Indicates that PCI clock is not required to generate PME#. 2:0 804 Attribute: Size: Description Address Offset: 50h-51h Default Value: 6001h 24.1.1.18 RO 32 bits Description Address Offset: 4Ch-4Fh Default Value: 00000000h 24.1.1.17 Attribute: Size: Version (VS) -- RO. Hardwired to 011b to indicate support for Revision 1.2 of the PCI Power Management Specification. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.1.1.19 PMCS--PCI Power Management Control and Status Register (Intel MEI 1--D22:F0) Address Offset: 54h-55h Default Value: 0008h Description 15 PME Status (PMES) -- R/WC. Bit is set by Intel ME Firmware. Host software clears bit by writing `1' to bit. This bit is reset when CL_RST0# asserted. 8 7:4 3 2 1:0 Reserved PME Enable (PMEE) -- R/W. This bit is read/write and is under the control of host SW. It does not directly have an effect on PME events. However, this bit is shadowed so Intel ME FW can monitor it. Intel ME FW will not cause the PMES bit to transition to '1' while the PMEE bit is '0', indicating that host SW had disabled PME. This bit is reset when PLTRST# asserted. Reserved No_Soft_Reset (NSR) -- RO. This bit indicates that when the Intel MEI host controller is transitioning from D3hot to D0 due to a power state command, it does not perform an internal reset. Configuration context is preserved. Reserved Power State (PS) -- R/W. This field is used both to determine the current power state of the Intel MEI host controller and to set a new power state. The values are: 00 - D0 state (default) 11 - D3hot state The D1 and D2 states are not supported for the Intel MEI host controller. When in the D3hot state, the Intel MEI's configuration space is available, but the register memory spaces are not. Additionally, interrupts are blocked. MID--Message Signaled Interrupt Identifiers Register (Intel MEI 1--D22:F0) Address Offset: 8Ch-8Dh Default Value: 0005h Bit 15:8 7:0 24.1.1.21 R/WC, R/W, RO 16 bits Bit 14:9 24.1.1.20 Attribute: Size: Attribute: Size: RO 16 bits Description Next Pointer (NEXT) -- RO. Value of 00h indicates that this is the last item in the list. Capability ID (CID) -- RO. Capabilities ID indicates MSI. MC--Message Signaled Interrupt Message Control Register (Intel MEI 1--D22:F0) Address Offset: 8Eh-8Fh Default Value: 0080h Bit 15:8 7 6:4 3:1 0 Attribute: Size: R/W, RO 16 bits Description Reserved. 64 Bit Address Capable (C64) -- RO. Specifies that function is capable of generating 64-bit messages. Multiple Message Enable (MME) -- RO. Not implemented, hardwired to 0. Multiple Message Capable (MMC) -- RO. Not implemented, hardwired to 0. MSI Enable (MSIE) -- R/W. If set, MSI is enabled and traditional interrupt pins are not used to generate interrupts. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 805 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.1.1.22 MA--Message Signaled Interrupt Message Address Register (Intel MEI 1--D22:F0) Address Offset: 90h-93h Default Value: 00000000h Bit 31:2 1:0 24.1.1.23 Address (ADDR) -- R/W. Lower 32 bits of the system specified message address, always DW aligned. Reserved. MUA--Message Signaled Interrupt Upper Address Register (Intel MEI 1--D22:F0) R/W 32 bits Description 31:0 Upper Address (UADDR) -- R/W. Upper 32 bits of the system specified message address, always DW aligned. MD--Message Signaled Interrupt Message Data Register (Intel MEI 1--D22:F0) Bit 15:0 Attribute: Size: R/W 16 bits Description Data (DATA) -- R/W. This 16-bit field is programmed by system software if MSI is enabled. Its content is driven during the data phase of the MSI memory write transaction. HIDM--Intel MEI Interrupt Delivery Mode (Intel MEI 1--D22:F0) Address Offset: A0h Default Value: 00h Bit 806 Attribute: Size: Bit Address Offset: 98h-99h Default Value: 0000h 24.1.1.25 R/W, RO 32 bits Description Address Offset: 94h-97h Default Value: 00000000h 24.1.1.24 Attribute: Size: Attribute: Size: R/W 8 bits Description 7:2 Reserved. 1:0 Intel MEI Interrupt Delivery Mode (HIDM) -- R/W. These bits control what type of interrupt the Intel MEI will send the host. They are interpreted as follows: 00 = Generate Legacy or MSI interrupt 01 = Generate SCI 10 = Generate SMI 11 = Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.1.1.26 HERES--Intel MEI Extend Register Status (Intel MEI 1-D22:F0) Address Offset: BCh-BFh Default Value: 40000000h Bit RO 32 bits Description 31 Extend Register Valid (ERV): Set by firmware after all firmware has been loaded. If ERA field is SHA-1, the result of the extend operation is in HER:5-1. If ERA field is SHA-256, the result of the extend operation is in HER:8-1. 30 Extend Feature Present (EFP): This bit is hardwired to 1 to allow driver software to easily detect the chipset supports the Extend Register FW measurement feature. 29:4 3:0 24.1.1.27 Attribute: Size: Reserved Extend Register Algorithm (ERA): This field indicates the hash algorithm used in the FW measurement extend operations. Encodings are: 0x0: SHA-1 0x2: SHA-256 Other values: Reserved. HERX--Intel MEI Extend Register DWX (Intel MEI 1--D22:F0) Address Offset: HER1: C0h-C3h HER2: C4h-C7h HER3: C8h-CBh HER4: CCh-CFh HER5: D0h-D3h HER6: D4h-D7h HER7: D8h-DBh HER8: DCh-DFh Default Value: 00000000h Bit 31:0 Attribute: RO Size: 32 bits Description Extend Register DWX (ERDWX): Nth DWORD result of the extend operation. Note: N Extend Operation is HER[5:1] if using SHA-1. If using SHA-2 then Extend Operation is HER[8:1] Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 807 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.1.2 MEI0_MBAR--MEI 1MMIO Registers (SRV/WS SKUs Only) These MMIO registers are accessible starting at the Intel MEI 1 MMIO Base Address (MEI0_MBAR) which gets programmed into D22:F0:Offset 10-17h. These registers are reset by PLTRST# unless otherwise noted. Table 24-2. Intel MEI 1 MMIO Register Address Map 24.1.2.1 MEI0_MBAR + Offset Mnemonic 00-03h H_CB_WW 04h-07h H_CSR 08h-0Bh 0Ch-0Fh Register Name Attribute Host Circular Buffer Write Window 00000000h RO Host Control Status 02000000h R/W, R/WC, RO ME_CB_RW Intel ME Circular Buffer Read Window FFFFFFFFh RO ME CSR_HA Intel ME Control Status Host Access 02000000h RO H_CB_WW--Host Circular Buffer Write Window Register (Intel MEI 1 MMIO Register) Address Offset: MEI0_MBAR + 00h Default Value: 00000000h 24.1.2.2 Default Attribute: Size: RO 32 bits Bit Description 31:0 Host Circular Buffer Write Window Field (H_CB_WWF): This bit field is for host to write into its circular buffer. The host's circular buffer is located at the Intel ME subsystem address specified in the Host CB Base Address register. This field is write only, reads will return arbitrary data. Writes to this register will increment the H_CBWP as long as ME_RDY is 1. When ME_RDY is 0, writes to this register have no effect and are not delivered to the H_CB, nor is H_CBWP incriminated. H_CSR--Host Control Status Register (Intel MEI 1 MMIO Register) Address Offset: MEI0_MBAR + 04h Default Value: 02000000h Bit Attribute: Size: RO, R/W, R/WC 32 bits Description Host Circular Buffer Depth (H_CBD) -- RO. This field indicates the maximum number of 32 bit entries available in the host circular buffer (H_CB). Host software uses this field along with the H_CBRP and H_CBWP fields to calculate the number of valid entries in the H_CB to read or # of entries available for write. 31:24 This field is implemented with a "1-hot" scheme. Only one bit will be set to a "1" at a time. Each bit position represents the value n of a buffer depth of (2^n). For example, when bit# 1 is 1, the buffer depth is 2; when bit#2 is 1, the buffer depth is 4, etc. The allowed buffer depth values are 2, 4, 8, 16, 32, 64 and 128. 23:16 Host CB Write Pointer (H_CBWP) -- RO. Points to next location in the H_CB for host to write the data. Software uses this field along with H_CBRP and H_CBD fields to calculate the number of valid entries in the H_CB to read or number of entries available for write. 15:8 Host CB Read Pointer (H_CBRP) -- RO. Points to next location in the H_CB where a valid data is available for embedded controller to read. Software uses this field along with H_CBWR and H_CBD fields to calculate the number of valid entries in the host CB to read or number of entries available for write. 7:5 808 Reserved Note: For writes to this register, these bits shall be written as 000b. 4 Host Reset (H_RST) -- R/W. Setting this bit to 1 will initiate a Intel MEI reset sequence to get the circular buffers into a known good state for host and Intel ME communication. When this bit transitions from 0 to 1, hardware will clear the H_RDY and ME_RDY bits. 3 Host Ready (H_RDY) -- R/W. This bit indicates that the host is ready to process messages. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.1.2.3 Bit Description 2 Host Interrupt Generate (H_IG) -- R/W. Once message(s) are written into its CB, the host sets this bit to one for the HW to set the ME_IS bit in the ME_CSR and to generate an interrupt message to Intel ME. HW will send the interrupt message to Intel ME only if the ME_IE is enabled. HW then clears this bit to 0. 1 Host Interrupt Status (H_IS) -- R/WC. Hardware sets this bit to 1 when ME_IG bit is set to 1. Host clears this bit to 0 by writing a 1 to this bit position. H_IE has no effect on this bit. 0 Host Interrupt Enable (H_IE) -- R/W. Host sets this bit to 1 to enable the host interrupt (INTR# or MSI) to be asserted when H_IS is set to 1. ME_CB_RW--ME Circular Buffer Read Window Register (Intel MEI 1 MMIO Register) Address Offset: MEI0_MBAR + 08h Default Value: FFFFFFFFh 24.1.2.4 Attribute: Size: RO 32 bits Bit Description 31:0 Intel ME Circular Buffer Read Window Field (ME_CB_RWF): This bit field is for host to read from the Intel ME Circular Buffer. The Intel ME's circular buffer is located at the Intel ME subsystem address specified in the Intel ME CB Base Address register. This field is read only, writes have no effect. Reads to this register will increment the ME_CBRP as long as ME_RDY is 1. When ME_RDY is 0, reads to this register have no effect, all 1s are returned, and ME_CBRP is not incremented. Intel(R) ME CSR_HA--ME Control Status Host Access Register (Intel MEI 1 MMIO Register) Address Offset: MEI0_MBAR + 0Ch Default Value: 02000000h Bit Attribute: Size: Description 31:24 Intel ME Circular Buffer Depth Host Read Access (ME_CBD_HRA) Host read only access to ME_CBD. 23:16 Intel ME CB Write Pointer Host Read Access (ME_CBWP_HRA) Host read only access to ME_CBWP. 15:8 Intel ME CB Read Pointer Host Read Access (ME_CBRP_HRA) Host read only access to ME_CBRP. 7:5 RO 32 bits Reserved 4 Intel ME Reset Host Read Access (ME_RST_HRA) Host read access to ME_RST. 3 Intel ME Ready Host Read Access (ME_RDY_HRA) Host read access to ME_RDY. 2 Intel ME Interrupt Generate Host Read Access (ME_IG_HRA) Host read only access to ME_IG. 1 Intel ME Interrupt Status Host Read Access (ME_IS_HRA) Host read only access to ME_IS. 0 Intel ME Interrupt Enable Host Read Access (ME_IE_HRA) Host read only access to ME_IE. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 809 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.2 Second Host Embedded Controller Interface (Intel MEI 2) Configuration Registers (Intel MEI 2--D22:F1) 24.2.1 PCI Configuration Registers (Intel MEI 2 -- D22:F0) Table 24-3. Intel MEI 2 Configuration Registers Address Map (Intel MEI 2--D22:F1) Offset Mnemonic 00h-01h VID 02h-03h DID 04h-05h PCICMD PCI Command 06h-07h PCISTS PCI Status 08h 810 Register Name Default Attribute Vendor Identification 8086h RO Device Identification See register description RO 0000h R/W, RO RID Revision Identification 09h-0Bh CC Class Code 0Ch CLS Cache Line Size 0Dh PLT 0Eh HTYPE 10h-17h MEI1_MBAR 2Ch-2Dh SVID 0010h RO See register description RO 0C8000h RO 00h RO Primary Latency Timer 00h RO Header Type 80h RO 00000000 00000004h R/W, RO Subsystem Vendor ID 0000h R/WO Subsystem ID 0000h R/WO 50h RO MEI1 MMIO Base Address 2Eh-2Fh SID 34h CAPP Capabilities List Pointer 3Ch-3Dh INTR Interrupt Information 0000h R/W, RO 40h-43h HFS Host Firmware Status 00000000h RO 48-4Bh GMES General Intel ME Status 00000000h RO 4Ch-4Fh H_GS Host General Status 00000000h RO 50h-51h PID PCI Power Management Capability ID 6001h RO 52h-53h PC PCI Power Management Capabilities C803h RO 54h-55h PMCS PCI Power Management Control and Status 0008h R/WC, R/ W, RO 8Ch-8Dh MID Message Signaled Interrupt Identifiers 0005h RO 8Eh-8Fh MC Message Signaled Interrupt Message Control 0080h R/W, RO 90h-93h MA Message Signaled Interrupt Message Address 00000000h R/W, RO 94h-97h MUA Message Signaled Interrupt Upper Address 00000000h R/W 98h-99h MD Message Signaled Interrupt Message Data 0000h R/W A0h HIDM Intel MEI Interrupt Delivery Mode 00h R/W BC-BF HERS Intel MEI Extended Register Status 40000000h RO C0-DF HER[1:8] Intel MEI Extended Register DW[1:8] 00000000h RO Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.2.1.1 VID--Vendor Identification Register (Intel MEI 2--D22:F1) Address Offset: 00h-01h Default Value: 8086h Bit 15:0 24.2.1.2 RO 16 bits Description Vendor ID (VID) -- RO. This is a 16-bit value assigned to Intel. DID--Device Identification Register (Intel MEI 2--D22:F1) Address Offset: 02h-03h Default Value: See bit description 24.2.1.3 Attribute: Size: Attribute: Size: RO 16 bits Bit Description 15:0 Device ID (DID) -- RO. This is a 16-bit value assigned to the PCH Intel MEI controller. Refer to the Intel(R) C600 Series Chipset Specification Update for the value of the Device ID Register. PCICMD--PCI Command Register (Intel MEI 2--D22:F1) Address Offset: 04h-05h Default Value: 0000h Bit 15:11 Attribute: Size: R/W, RO 16 bits Description Reserved 10 Interrupt Disable (ID) -- R/W. Disables this device from generating PCI line based interrupts. This bit does not have any effect on MSI operation. 9:3 Reserved 2 Bus Master Enable (BME): Controls the Intel MEI host controller's ability to act as a system memory master for data transfers. When this bit is cleared, Intel MEI bus master activity stops and any active DMA engines return to an idle condition. This bit is made visible to firmware through the H_PCI_CSR register, and changes to this bit may be configured by the H_PCI_CSR register to generate an Intel ME MSI. When this bit is '0', Intel MEI is blocked from generating MSI to the host CPU. Note: This bit does not block Intel MEI accesses to Intel ME-UMA; that is, writes or reads to the host and Intel ME circular buffers through the read window and write window registers still cause Intel ME backbone transactions to Intel ME-UMA. 1 Memory Space Enable (MSE) -- R/W. Controls access to the Intel MEI's memory mapped register space. 0 = Disable. Memory cycles within the range specified by the memory base and limit registers are master aborted. 1 = Enable. Allows memory cycles within the range specified by the memory base and limit registers accepted. 0 I/O Space Enable (IOSE) -- RO. Not implemented, hardwired to 0. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 811 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.2.1.4 PCISTS--PCI Status Register (Intel MEI 2--D22:F1) Address Offset: 06h-07h Default Value: 0010h Attribute: Size: Bit 15:5 Description Reserved 4 Capabilities List (CL) -- RO. Indicates the presence of a capabilities list, hardwired to 1. 3 Interrupt Status -- RO. Indicates the interrupt status of the device. 0 = Interrupt is deasserted. 1 = Interrupt is asserted. 2:0 24.2.1.5 Reserved RID--Revision Identification Register (Intel MEI 2--D22:F1) Offset Address: 08h Default Value: See bit description Bit 7:0 24.2.1.6 Revision ID -- RO. Refer to the Revision ID Register RO 8 bits Intel(R) C600 Series Chipset Specification Update for the value of the CC--Class Code Register (Intel MEI 2--D22:F1) Bit 23:16 15:8 7:0 Attribute: Size: RO 24 bits Description Base Class Code (BCC) -- RO. Indicates the base class code of the Intel MEI device. Sub Class Code (SCC) -- RO. Indicates the sub class code of the Intel MEI device. Programming Interface (PI) -- RO. Indicates the programming interface of the Intel MEI device. HTYPE--Header Type Register (Intel MEI 2--D22:F1) Address Offset: 0Eh Default Value: 80h Bit 7 6:0 812 Attribute: Size: Description Address Offset: 09h-0Bh Default Value: 078000h 24.2.1.7 RO 16 bits Attribute: Size: RO 8 bits Description Multi-Function Device (MFD) -- RO. Indicates the Intel MEI host controller is part of a multifunction device. Header Layout (HL) -- RO. Indicates that the Intel MEI uses a target device layout. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.2.1.8 MEI1_MBAR--MEI 2 MMIO Base Address Register (Intel MEI 2--D22:F1) Address Offset: 10h-17h Default Value: 0000000000000004h Attribute: Size: R/W, RO 64 bits This register allocates space for the Intel MEI memory mapped registers. Bit 63:4 3 2:1 0 24.2.1.9 Description Base Address (BA) -- R/W. Software programs this field with the base address of this region. Prefetchable Memory (PM) -- RO. Indicates that this range is not pre-fetchable. Type (TP) -- RO. Set to 10b to indicate that this range can be mapped anywhere in 64-bit address space. Resource Type Indicator (RTE) -- RO. Indicates a request for register memory space. SVID--Subsystem Vendor ID Register (Intel MEI 2--D22:F1) Address Offset: 2Ch-2Dh Default Value: 0000h Bit 15:0 Note: 24.2.1.10 R/WO 16 bits Description Subsystem Vendor ID (SSVID) -- R/WO. Indicates the sub-system vendor identifier. This field should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This field can only be cleared by PLTRST#. Register must be written as a Word write or as a DWord write with SID register. SID--Subsystem ID Register (Intel MEI 2--D22:F1) Address Offset: 2Eh-2Fh Default Value: 0000h Attribute: Size: R/WO 16 bits Bit Description 15:0 Subsystem ID (SSID) -- R/WO. Indicates the sub-system identifier. This field should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This field can only be cleared by PLTRST#. Note: 24.2.1.11 Attribute: Size: Register must be written as a Word write or as a DWord write with SVID register. CAPP--Capabilities List Pointer Register (Intel MEI 2--D22:F1) Address Offset: 34h Default Value: 50h Bit 7:0 Attribute: Size: RO 8 bits Description Capabilities Pointer (PTR) -- RO. Indicates that the pointer for the first entry in the capabilities list is at 50h in configuration space. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 813 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.2.1.12 INTR--Interrupt Information Register (Intel MEI 2--D22:F1) Address Offset: 3Ch-3Dh Default Value: 0200h 24.2.1.13 Description 15:8 Interrupt Pin (IPIN) -- RO. TRO. This field indicates the interrupt pin the Intel MEI host controller uses. A value of 1h/2h/3h/4h indicates that this function implements legacy interrupt on INTA/INTB/ INTC/INTD, respectively. The upper 4 bits are hardwired to 0 and the lower 4 bits are programmed by the MEI2IP bits (RCBA+3124:bits 7:4). 7:0 Interrupt Line (ILINE) -- R/W. Software written value to indicate which interrupt line (vector) the interrupt is connected to. No hardware action is taken on this register. HFS--Host Firmware Status Register (Intel MEI 2--D22:F1) 31:0 Host Firmware Status (HFS) -- RO. This register field is used by Firmware to reflect the operating environment to the host. GMES--General Intel(R) ME Status (Intel MEI 2--D22:F1) 31:0 Attribute: Size: RO 32 bits Description General Intel ME Status (ME_GS)-- RO. This field is populated by Intel ME. H_GS--Host General Status (Intel MEI 2--D22:F1) Address Offset: 4Ch-4Fh Default Value: 00000000h Bit 31:0 Attribute: Size: RO 32 bits Description Host General Status(H_GS)-- RO. General Status of Host, this field is not used by Hardware PID--PCI Power Management Capability ID Register (Intel MEI 2--D22:F1) Address Offset: 50h-51h Default Value: 6001h Bit 15:8 7:0 814 RO 32 bits Description Bit 24.2.1.16 Attribute: Size: Bit Address Offset: 48h-4Bh Default Value: 00000000h 24.2.1.15 R/W, RO 16 bits Bit Address Offset: 40h-43h Default Value: 00000000h 24.2.1.14 Attribute: Size: Attribute: Size: RO 16 bits Description Next Capability (NEXT) -- RO. Value of 8Ch indicates the location of the next pointer. Capability ID (CID) -- RO. Indicates the linked list item is a PCI Power Management Register. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.2.1.17 PC--PCI Power Management Capabilities Register (Intel MEI 2--D22:F1) Address Offset: 52h-53h Default Value: C803h Bit 15:11 PME_Support (PSUP) -- RO. This five-bit field indicates the power states in which the function may assert PME#. Intel MEI can assert PME# from any D-state except D1 or D2 which are not supported by Intel MEI. D2_Support (D2S) -- RO. The D2 state is not supported. 9 D1_Support (D1S) -- RO. The D1 state is not supported. 5 RO 16 bits Description 10 8:6 Aux_Current (AC) -- RO. Reports the maximum Suspend well current required when in the D3cold state. Value of 00b is reported. Device Specific Initialization (DSI) -- RO. Indicates whether device-specific initialization is required. 4 Reserved 3 PME Clock (PMEC) -- RO. Indicates that PCI clock is not required to generate PME#. 2:0 24.2.1.18 Attribute: Size: Version (VS) -- RO. Hardwired to 011b to indicate support for Revision 1.2 of the PCI Power Management Specification. PMCS--PCI Power Management Control and Status Register (Intel MEI 2--D22:F1) Address Offset: 54h-55h Default Value: 0008h Attribute: Size: R/WC, R/W, RO 16 bits Bit Description 15 PME Status (PMES) -- R/WC. Bit is set by Intel ME Firmware. Host software clears bit by writing `1' to bit. This bit is reset when CL_RST0# asserted. 14:9 8 7:4 Reserved PME Enable (PMEE) -- R/W. This bit is read/write and is under the control of host SW. It does not directly have an effect on PME events. However, this bit is shadowed so Intel ME FW can monitor it. Intel ME FW will not cause the PMES bit to transition to '1' while the PMEE bit is '0', indicating that host SW had disabled PME. This bit is reset when PLTRST# asserted. Reserved 3 No_Soft_Reset (NSR) -- RO. This bit indicates that when the Intel MEI host controller is transitioning from D3hot to D0 due to a power state command, it does not perform an internal reset. Configuration context is preserved. 2 Reserved 1:0 Power State (PS) -- R/W. This field is used both to determine the current power state of the Intel MEI host controller and to set a new power state. The values are: 00 - D0 state (default) 11 - D3hot state The D1 and D2 states are not supported for the Intel MEI host controller. When in the D3hot state, the Intel MEI's configuration space is available, but the register memory spaces are not. Additionally, interrupts are blocked. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 815 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.2.1.19 MID--Message Signaled Interrupt Identifiers Register (Intel MEI 2--D22:F1) Address Offset: 8Ch-8Dh Default Value: 0005h Bit 15:8 7:0 24.2.1.20 Next Pointer (NEXT) -- RO. Value of 00h indicates that this is the last item in the list. Capability ID (CID) -- RO. Capabilities ID indicates MSI. MC--Message Signaled Interrupt Message Control Register (Intel MEI 2--D22:F1) Bit 15:8 7 R/W, RO 16 bits Description Reserved. 64 Bit Address Capable (C64) -- RO. Specifies that function is capable of generating 64-bit messages. Multiple Message Enable (MME) -- RO. Not implemented, hardwired to 0. 3:1 Multiple Message Capable (MMC) -- RO. Not implemented, hardwired to 0. MSI Enable (MSIE) -- R/W. If set, MSI is enabled and traditional interrupt pins are not used to generate interrupts. MA--Message Signaled Interrupt Message Address Register (Intel MEI 2--D22:F1) Address Offset: 90h-93h Default Value: 00000000h Bit 31:2 1:0 Attribute: Size: R/W, RO 32 bits Description Address (ADDR) -- R/W. Lower 32 bits of the system specified message address, always DW aligned. Reserved. MUA--Message Signaled Interrupt Upper Address Register (Intel MEI 2--D22:F1) Address Offset: 94h-97h Default Value: 00000000h 816 Attribute: Size: 6:4 0 24.2.1.22 RO 16 bits Description Address Offset: 8Eh-8Fh Default Value: 0080h 24.2.1.21 Attribute: Size: Attribute: Size: R/W 32 bits Bit Description 31:0 Upper Address (UADDR) -- R/W. Upper 32 bits of the system specified message address, always DW aligned. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.2.1.23 MD--Message Signaled Interrupt Message Data Register (Intel MEI 2--D22:F1) Address Offset: 98h-99h Default Value: 0000h Bit 15:0 24.2.1.24 Attribute: Size: R/W 16 bits Description Data (DATA) -- R/W. This 16-bit field is programmed by system software if MSI is enabled. Its content is driven during the data phase of the MSI memory write transaction. HIDM--Intel MEI Interrupt Delivery Mode (Intel MEI 2--D22:F1) Address Offset: A0h Default Value: 00h Bit 7:2 Attribute: Size: R/W 8 bits Description Reserved. Intel MEI Interrupt Delivery Mode (HIDM) -- R/W. These bits control what type of interrupt the Intel MEI will send when ARC writes to set the M_IG bit in AUX space. They are interpreted as follows: 1:0 00: Generate Legacy or MSI interrupt 01: Generate SCI 10: Generate SMI 24.2.1.25 HERES--Intel MEI Extend Register Status (Intel MEI 2-D22:F1) Address Offset: BCh-BFh Default Value: 40000000h Bit Attribute: Size: RO 32 bits Description 31 Extend Register Valid (ERV): Set by firmware after all firmware has been loaded. If ERA field is SHA-1, the result of the extend operation is in HER:5-1. If ERA field is SHA-256, the result of the extend operation is in HER:8-1. 30 Extend Feature Present (EFP): This bit is hardwired to 1 to allow driver software to easily detect the chipset supports the Extend Register FW measurement feature. 29:4 3:0 Reserved Extend Register Algorithm (ERA): This field indicates the hash algorithm used in the FW measurement extend operations. Encodings are: 0h: SHA-1 2h: SHA-256 Other values: Reserved. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 817 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.2.1.26 HERX--Intel MEI Extend Register DWX (Intel MEI 2--D22:F1) Address Offset: HER1: C0h-C3h HER2: C4h-C7h HER3: C8h-CBh HER4: CCh-CFh HER5: D0h-D3h HER6: D4h-D7h HER7: D8h-DBh HER8: DCh-DFh Default Value: 00000000h Bit RO Size: 32 bits Description 31:0 24.2.2 Attribute: Extend Register DWX (ERDWX): Xth DWORD result of the extend operation. Note: Extend Operation is HER[5:1] if using SHA-1. If using SHA-2 then Extend Operation is HER[8:1] MEI1_MBAR--Intel MEI 2MMIO Registers These MMIO registers are accessible starting at the Intel MEI 2MMIO Base Address (MEI1_MBAR) which gets programmed into D22:F1:Offset 10-17h. These registers are reset by PLTRST# unless otherwise noted. Table 24-4. Intel MEI 2 MMIO Register Address Map 24.2.2.1 MEI_MBAR+Offset Mnemonic 00-03h H_CB_WW 04h-07h H_CSR 08h-0Bh ME_CB_RW 0Ch-0Fh Intel ME CSR_HA Register Name Default Attribute Host Circular Buffer Write Window 00000000h RO Host Control Status 02000000h R/W, R/WC, RO Intel ME Circular Buffer Read Window FFFFFFFFh RO Intel ME Control Status Host Access 02000000h RO H_CB_WW--Host Circular Buffer Write Window (Intel MEI 2 MMIO Register) Address Offset: MEI1_MBAR + 00h Default Value: 00000000h 818 Attribute: Size: RO 32 bits Bit Description 31:0 Host Circular Buffer Write Window Field (H_CB_WWF) This bit field is for host to write into its circular buffer. The host's circular buffer is located at the Intel ME subsystem address specified in the Host CB Base Address register. This field is write only, reads will return arbitrary data. Writes to this register will increment the H_CBWP as long as ME_RDY is 1. When ME_RDY is 0, writes to this register have no effect and are not delivered to the H_CB, nor is H_CBWP incremented. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.2.2.2 H_CSR--Host Control Status (Intel MEI 2 MMIO Register) Address Offset: MEI1_MBAR + 04h Default Value: 02000000h Bit 31:24 RO, R/W, R/WC 32 bits Description Host Circular Buffer Depth (H_CBD) -- RO. This field indicates the maximum number of 32 bit entries available in the host circular buffer (H_CB). Host software uses this field along with the H_CBRP and H_CBWP fields to calculate the number of valid entries in the H_CB to read or # of entries available for write. Note: This field is implemented with a "1-hot" scheme. Only one bit will be set to a "1" at a time. Each bit position represents the value n of a buffer depth of (2^n). For example, when bit# 1 is 1, the buffer depth is 2; when bit#2 is 1, the buffer depth is 4, etc. The allowed buffer depth values are 2, 4, 8, 16, 32, 64 and 128. 23:16 Host CB Write Pointer (H_CBWP) -- RO. Points to next location in the H_CB for host to write the data. Software uses this field along with H_CBRP and H_CBD fields to calculate the number of valid entries in the H_CB to read or number of entries available for write. 15:8 Host CB Read Pointer (H_CBRP) -- RO. Points to next location in the H_CB where a valid data is available for embedded controller to read. Software uses this field along with H_CBWR and H_CBD fields to calculate the number of valid entries in the host CB to read or number of entries available for write. 7:5 24.2.2.3 Attribute: Size: Reserved Note: For writes to this register, these bits shall be written as 000b. 4 Host Reset (H_RST) -- R/W. Setting this bit to 1 will initiate a Intel MEI reset sequence to get the circular buffers into a known good state for host and Intel ME communication. When this bit transitions from 0 to 1, hardware will clear the H_RDY and ME_RDY bits. 3 Host Ready (H_RDY) -- R/W. This bit indicates that the host is ready to process messages. 2 Host Interrupt Generate (H_IG) -- R/W. Once message(s) are written into its CB, the host sets this bit to one for the HW to set the ME_IS bit in the ME_CSR and to generate an interrupt message to Intel ME. HW will send the interrupt message to Intel ME only if the ME_IE is enabled. HW then clears this bit to 0. 1 Host Interrupt Status (H_IS) -- R/WC. Hardware sets this bit to 1 when ME_IG bit is set to 1. Host clears this bit to 0 by writing a 1 to this bit position. H_IE has no effect on this bit. 0 Host Interrupt Enable (H_IE) -- R/W. Host sets this bit to 1 to enable the host interrupt (INTR# or MSI) to be asserted when H_IS is set to 1. ME_CB_RW--ME Circular Buffer Read Window (Intel MEI 2 MMIO Register) Address Offset: MEI1_MBAR + 08h Default Value: FFFFFFFFh Attribute: Size: RO 32 bits Bit Description 31:0 Intel ME Circular Buffer Read Window Field (ME_CB_RWF): This bit field is for host to read from the Intel ME Circular Buffer. The Intel ME's circular buffer is located at the Intel ME subsystem address specified in the Intel ME CB Base Address register. This field is read only, writes have no effect. Reads to this register will increment the ME_CBRP as long as ME_RDY is 1. When ME_RDY is 0, reads to this register have no effect, all 1s are returned, and ME_CBRP is not incremented. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 819 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.2.2.4 Intel(R) ME CSR_HA--ME Control Status Host Access (Intel MEI 2 MMIO Register) Address Offset: MEI1_MBAR + 0Ch Default Value: 02000000h Attribute: Size: Bit Description 31:24 Intel ME Circular Buffer Depth Host Read Access (ME_CBD_HRA) Host read only access to ME_CBD. 23:16 Intel ME CB Write Pointer Host Read Access (ME_CBWP_HRA) Host read only access to ME_CBWP. 15:8 Intel ME CB Read Pointer Host Read Access (ME_CBRP_HRA) Host read only access to ME_CBRP. 7:5 RO 32 bits Reserved 4 Intel ME Reset Host Read Access (ME_RST_HRA) Host read access to ME_RST. 3 Intel ME Ready Host Read Access (ME_RDY_HRA) Host read access to ME_RDY. 2 Intel ME Interrupt Generate Host Read Access (ME_IG_HRA) Host read only access to ME_IG. 1 Intel ME Interrupt Status Host Read Access (ME_IS_HRA) Host read only access to ME_IS. 0 Intel ME Interrupt Enable Host Read Access (ME_IE_HRA) Host read only access to ME_IE. 24.3 IDE Function for Remote Boot and Installations PT IDER Registers (IDER -- D22:F2) 24.3.1 PCI Configuration Registers (IDER--D22:f2) Table 24-5. IDE Function for remote boot and Installations PT IDER Register Address Map Attribute Vendor Identification 8086h RO Device Identification See register description RO 0000h RO, R/W PCI Status 00B0h RO Revision ID See register description RO 010185h RO 00h RO Register Symbol 00h-01h VID 02h-03h DID 04h-05h PCICMD PCI Command 06h-07h PCISTS 08h 820 Default Value Address Offset RID Register Name 09-0Bh CC Class Codes 0Ch CLS Cache Line Size 0Dh PLT Primary Latency Timer 00h RO 10-13h PCMDBA Primary Command Block IO Bar 00000001h RO, R/W 14-17h PCTLBA Primary Control Block Base Address 00000001h RO, R/W 18-1Bh SCMDBA Secondary Command Block Base Address 00000001h RO, R/W 1C-1Fh SCTLBA Secondary Control Block base Address 00000001h RO, R/W Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) Table 24-5. IDE Function for remote boot and Installations PT IDER Register Address Map 24.3.1.1 Address Offset Register Symbol 20-23h LBAR 2C-2Fh SS 30-33h 34h Register Name Legacy Bus Master Base Address 00000001h RO, R/W 00008086h R/WO EROM Expansion ROM Base Address 00000000h RO CAPP Capabilities Pointer C8h RO 3C-3Dh INTR Interrupt Information 0200h R/W, RO C8-C9h PID PCI Power Management Capability ID D001h RO CA-CBh PC PCI Power Management Capabilities 0023h RO 00000000h RO, R/W, RO/V CC-CFh PMCS D0-D1h MID Message Signaled Interrupt Capability ID 0005h RO D2-D3h MC Message Signaled Interrupt Message Control 0080h RO, R/W D4-D7h MA Message Signaled Interrupt Message Address 00000000h R/W, RO Message Signaled Interrupt Message Upper Address 00000000h RO, R/W 0000h R/W D8-DBh MAU DC-DDh MD PCI Power Management Control and Status Message Signaled Interrupt Message Data VID--Vendor Identification Register (IDER--D22:F2) Bit 15:0 Attribute: Size: RO 16 bits Description Vendor ID (VID) -- RO. This is a 16-bit value assigned by Intel. DID--Device Identification Register (IDER--D22:F2) Address Offset: 02-03h Default Value: See bit description 24.3.1.3 Attribute Sub System Identifiers Address Offset: 00-01h Default Value: 8086h 24.3.1.2 Default Value Attribute: Size: RO 16 bits Bit Description 15:0 Device ID (DID) -- RO. This is a 16-bit value assigned to the PCH IDER controller. Refer to the Intel(R) C600 Series Chipset Specification Update for the value of the Device ID Register. PCICMD-- PCI Command Register (IDER--D22:F2) Address Offset: 04-05h Default Value: 0000h Bit 15:11 Attribute: Size: RO, R/W 16 bits Description Reserved 10 Interrupt Disable (ID)--R/W. This disables pin-based INTx# interrupts. This bit has no effect on MSI operation. When set, internal INTx# messages will not be generated. When cleared, internal INTx# messages are generated if there is an interrupt and MSI is not enabled. 9:3 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 821 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.3.1.4 Bit Description 2 Bus Master Enable (BME)--RO. This bit controls the PT function's ability to act as a master for data transfers. This bit does not impact the generation of completions for split transaction commands. 1 Memory Space Enable (MSE)--RO. PT function does not contain target memory space. 0 I/O Space enable (IOSE)--RO. This bit controls access to the PT function's target I/O space. PCISTS--PCI Device Status Register (IDER--D22:F2) Address Offset: 06-07h Default Value: 00B0h Bit 15:11 10:9 8:5 Description Reserved DEVSEL# Timing Status (DEVT)--RO. This bit controls the device select time for the PT function's PCI interface. Reserved Capabilities List (CL)--RO. This bit indicates that there is a capabilities pointer implemented in the device. 3 Interrupt Status (IS)--RO. This bit reflects the state of the interrupt in the function. Setting of the Interrupt Disable bit to 1 has no affect on this bit. Only when this bit is a 1 and ID bit is 0 is the INTc interrupt asserted to the Host. Reserved RID--Revision Identification Register (IDER--D22:F2) Address Offset: 08h Default Value: See bit description Bit 7:0 24.3.1.6 Attribute: Size: RO 8 bits Description Revision ID--RO. Refer to the Intel(R) C600 Series Chipset Specification Update for the value of the Device ID Register. CC--Class Codes Register (IDER--D22:F2) Address Offset: 09-0Bh Default Value: 010185h 822 RO 16 bits 4 2:0 24.3.1.5 Attribute: Size: Attribute: Size: RO 24 bits Bit Description 23:16 Base Class Code (BCC)--RO This field indicates the base class code of the IDER host controller device. 15:8 Sub Class Code (SCC)--RO This field indicates the sub class code of the IDER host controller device. 7:0 Programming Interface (PI)--RO This field indicates the programming interface of the IDER host controller device. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.3.1.7 CLS--Cache Line Size Register (IDER--D22:F2) Address Offset: 0Ch Default Value: 00h Bit 7:0 24.3.1.8 Cache Line Size (CLS)--RO. All writes to system memory are Memory Writes. PCMDBA--Primary Command Block IO Bar Register (IDER--D22:F2) Bit 31:16 15:3 2:1 0 Attribute: Size: RO, R/W 32 bits Description Reserved Base Address (BAR)--R/W Base Address of the BAR0 I/O space (8 consecutive I/O locations). Reserved Resource Type Indicator (RTE)--RO. This bit indicates a request for I/O space. PCTLBA--Primary Control Block Base Address Register (IDER-- D22:F2) Address Offset: 14-17h Default Value: 00000001h Bit 31:16 15:2 24.3.1.10 RO 8 bits Description Address Offset: 10-13h Default Value: 00000001h 24.3.1.9 Attribute: Size: Attribute: Size: RO, R/W 32 bits Description Reserved Base Address (BAR)--R/W. Base Address of the BAR1 I/O space (4 consecutive I/O locations) 1 Reserved 0 Resource Type Indicator (RTE)--RO. This bit indicates a request for I/O space SCMDBA--Secondary Command Block Base Address Register (IDER--D22:F2) Address Offset: 18-1Bh Default Value: 00000001h Bit 31:16 15:3 2:1 0 Attribute: Size: RO, R/W 32 bits Description Reserved Base Address (BAR)--R/W. Base Address of the I/O space (8 consecutive I/O locations). Reserved Resource Type Indicator (RTE)--RO. This bit indicates a request for I/O space. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 823 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.3.1.11 SCTLBA--Secondary Control Block base Address Register (IDER--D22:F2) Address Offset: 1C-1Fh Default Value: 00000001h Bit 15:2 Reserved Base Address (BAR)--R/W. Base Address of the I/O space (4 consecutive I/O locations). 1 Reserved 0 Resource Type Indicator (RTE)--RO. This bit indicates a request for I/O space. LBAR--Legacy Bus Master Base Address Register (IDER--D22:F2) Address Offset: 20-23h Default Value: 00000001h Bit 15:4 3:1 0 Reserved Reserved Resource Type Indicator (RTE)--RO. This bit indicates a request for I/O space. SVID--Subsystem Vendor ID Register (IDER--D22:F2) Bit 15:0 Note: Attribute: Size: R/WO 16 bits Description Subsystem Vendor ID (SSVID) -- R/WO. Indicates the sub-system vendor identifier. This field should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This field can only be cleared by PLTRST#. Register must be written as a DWord write with SID register. SID--Subsystem ID Register (IDER--D22:F2) Address Offset: 2Eh-2Fh Default Value: 8086h Attribute: Size: R/WO 16 bits Bit Description 15:0 Subsystem ID (SSID) -- R/WO. Indicates the sub-system identifier. This field should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This field can only be cleared by PLTRST#. Note: 824 RO, R/W 32 bits Base Address (BA)--R/W. Base Address of the I/O space (16 consecutive I/O locations). Address Offset: 2Ch-2Dh Default Value: 0000h 24.3.1.14 Attribute: Size: Description 31:16 24.3.1.13 RO, R/W 32 bits Description 31:16 24.3.1.12 Attribute: Size: Register must be written as a DWord write with SVID register. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.3.1.15 CAPP--Capabilities List Pointer Register (IDER--D22:F2) Address Offset: 34h Default Value: C8h 24.3.1.16 Description 7:0 Capability Pointer (CP)-- R/WO. This field indicates that the first capability pointer is offset C8h (the power management capability). INTR--Interrupt Information Register (IDER--D22:F2) R/W, RO Size: 16 bits Bit Description 15:8 Interrupt Pin (IPIN) -- RO. A value of 1h/2h/3h/4h indicates that this function implements legacy interrupt on INTA/INTB/INTC/INTD, respectively. The upper 4 bits are hardwired to 0 and the lower 4 bits are programmed by the IDERIP bits (RCBA+3124:bits 11:8). 7:0 Interrupt Line (ILINE)-- R/W. The value written in this register indicates which input of the system interrupt controller, the device's interrupt pin is connected to. This value is used by the OS and the device driver, and has no affect on the hardware. PID--PCI Power Management Capability ID Register (IDER--D22:F2) Address Offset: C8-C9h Default Value: D001h Bit 15:8 7:0 24.3.1.18 RO 8 bits Bit Address Offset: 3C-3Dh Attribute: Default Value: 0200h 24.3.1.17 Attribute: Size: Attribute: Size: RO 16 bits Description Next Capability (NEXT) -- RO. Its value of D0h points to the MSI capability. Cap ID (CID)-- RO. This field indicates that this pointer is a PCI power management. PC--PCI Power Management Capabilities Register (IDER--D22:F2) Address Offset: CA-CBh Default Value: 0023h Attribute: Size: RO 16 bits Bit Description 15:11 PME_Support (PSUP) -- RO. This five-bit field indicates the power states in which the function may assert PME#. IDER can assert PME# from any D-state except D1 or D2 which are not supported by IDER. 10:9 8:6 5 Reserved Aux_Current (AC) -- RO. Reports the maximum Suspend well current required when in the D3cold state. Value of 00b is reported. Device Specific Initialization (DSI) -- RO. Indicates whether device-specific initialization is required. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 825 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) Bit 4 Reserved 3 PME Clock (PMEC) -- RO. Indicates that PCI clock is not required to generate PME#. 2:0 24.3.1.19 Description Version (VS) -- RO. Hardwired to 011b to indicate support for Revision 1.2 of the PCI Power Management Specification. PMCS--PCI Power Management Control and Status Register (IDER--D22:F2) Address Offset: CC-CFh Default Value: 00000000h Bit 31:4 3 2 1:0 24.3.1.20 Reserved No Soft Reset (NSR) -- RO. 0 = Devices do perform an internal reset upon transitioning from D3hot to D0 using software control of the PowerState bits. Configuration Context is lost when performing the soft reset. Upon transition from the D3hot to the D0 state, full re-initialization sequence is needed to return the device to D0 Initialized. 1 = This bit indicates that devices transitioning from D3hot to D0 because of PowerState commands do not perform an internal reset. Configuration Context is preserved. Upon transition from the D3hot to the D0 Initialized state, no additional operating system intervention is required to preserve Configuration Context beyond writing the PowerState bits. Reserved Power State (PS)-- R/W. This field is used both to determine the current power state of the PT function and to set a new power state. The values are: 00 = D0 state 11 = D3HOT state When in the D3HOT state, the controller's configuration space is available, but the I/O and memory spaces are not. Additionally, interrupts are blocked. If software attempts to write a '10' or '01' to these bits, the write will be ignored. MID--Message Signaled Interrupt Capability ID Register (IDER--D22:F2) Bit 15:8 7:0 Attribute: Size: RO 16 bits Description Next Pointer (NEXT) -- RO. This value indicates this is the last item in the capabilities list. Capability ID (CID) -- RO. The Capabilities ID value indicates device is capable of generating an MSI. MC--Message Signaled Interrupt Message Control Register (IDER--D22:F2) Address Offset: D2-D3h Default Value: 0080h Bit 826 RO, R/W 32 bits Description Address Offset: D0-D1h Default Value: 0005h 24.3.1.21 Attribute: Size: Attribute: Size: RO, R/W 16 bits Description 15:8 Reserved 7 64 Bit Address Capable (C64) -- RO. Capable of generating 64-bit and 32-bit messages. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) Bit Multiple Message Enable (MME) -- R/W. These bits are R/W for software compatibility, but only one message is ever sent by the PT function. 6:4 24.3.1.22 Description 3:1 Multiple Message Capable (MMC) -- RO. Only one message is required. 0 MSI Enable (MSIE) -- R/W. If set, MSI is enabled and traditional interrupt pins are not used to generate interrupts. MA--Message Signaled Interrupt Message Address Register (IDER--D22:F2) Address Offset: D4-D7h Default Value: 00000000h Attribute: Size: Bit 31:2 1:0 24.3.1.23 Description Address (ADDR) -- R/W. This field contains the Lower 32 bits of the system specified message address, always DWord aligned Reserved MAU--Message Signaled Interrupt Message Upper Address Register (IDER--D22:F2) Address Offset: D8-DBh Default Value: 00000000h Attribute: Size: Bit 31:4 3:0 24.3.1.24 RO, R/W 32 bits Description Reserved Address (ADDR) -- R/W. This field contains the Upper 4 bits of the system specified message address. MD--Message Signaled Interrupt Message Data Register (IDER--D22:F2) Address Offset: DC-DDh Default Value: 0000h Attribute: Size: Bit 15:0 24.3.2 R/W, RO 32 bits R/W 16 bits Description Data (DATA) -- R/W. This content is driven onto the lower word of the data bus of the MSI memory write transaction. IDER BAR0 Registers Table 24-6. IDE BAR0 Register Address Map (Sheet 1 of 2) Address Offset Register Symbol Default Value Attribute 0h IDEDATA IDE Data Register 00h R/W 1h 1h IDEERD1 IDE Error Register DEV1 00h R/W IDEERD0 IDE Error Register DEV0 00h R/W 1h IDEFR IDE Features Register 00h R/W Register Name Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 827 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) Table 24-6. IDE BAR0 Register Address Map (Sheet 2 of 2) Address Offset 24.3.2.1 Register Symbol Register Name Default Value Attribute 2h IDESCIR IDE Sector Count In Register 00h R/W 2h IDESCOR1 IDE Sector Count Out Register Device 1 00h R/W 2h IDESCOR0 IDE Sector Count Out Register Device 0 00h R/W 3h IDESNOR0 IDE Sector Number Out Register Device 0 00h R/W 3h IDESNOR1 IDE Sector Number Out Register Device 1 00h R/W 3h IDESNIR IDE Sector Number In Register 00h R/W 4h IDECLIR IDE Cylinder Low In Register 00h R/W 4h IDCLOR1 IDE Cylinder Low Out Register Device 1 00h R/W 4h IDCLOR0 IDE Cylinder Low Out Register Device 0 00h R/W 5h IDCHOR0 IDE Cylinder High Out Register Device 0 00h R/W 5h IDCHOR1 IDE Cylinder High Out Register Device 1 00h R/W 5h IDECHIR IDE Cylinder High In Register 00h R/W 6h IDEDHIR IDE Drive/Head In Register 00h R/W 6h IDDHOR1 IDE Drive Head Out Register Device 1 00h R/W 6h IDDHOR0 IDE Drive Head Out Register Device 0 00h R/W 7h IDESD0R IDE Status Device 0 Register 80h R/W 7h IDESD1R 7h IDECR IDE Status Device 1 Register 80h R/W IDE Command Register 00h R/W IDEDATA--IDE Data Register (IDER--D22:F2) Address Offset: 0h Default Value: 00h Attribute: Size: R/W 8 bits The IDE data interface is a special interface that is implemented in the HW. This data interface is mapped to IO space from the host and takes read and write cycles from the host targeting master or slave device. Writes from host to this register result in the data being written to Intel ME memory. Reads from host to this register result in the data being fetched from Intel ME memory. Data is typically written/ read in WORDs. Intel ME-FW must enable hardware to allow it to accept Host initiated Read/ Write cycles, else the cycles are dropped. 24.3.2.2 Bit Description 7:0 IDE Data Register (IDEDR) -- R/W. Data Register implements the data interface for IDE. All writes and reads to this register translate into one or more corresponding write/reads to Intel ME memory IDEERD1--IDE Error Register DEV1 (IDER--D22:F2) Address Offset: 01h Default Value: 00h Attribute: Size: R/W 8 bits This register implements the Error register of the command block of the IDE function. This register is read only by the HOST interface when DEV = 1 (slave device). 828 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) Bit 7:0 24.3.2.3 Description IDE Error Data (IDEED) -- R/W. Drive reflects its error/ diagnostic code to the host using this register at different times. IDEERD0--IDE Error Register DEV0 (IDER--D22:F2) Address Offset: 01h Default Value: 00h Attribute: Size: R/W 8 bits This register implements the Error register of the command block of the IDE function. This register is read only by the HOST interface when DEV = 0 (master device). Bit 7:0 24.3.2.4 Description IDE Error Data (IDEED)-- R/W. Drive reflects its error/ diagnostic code to the host using this register at different times. IDEFR--IDE Features Register (IDER--D22:F2) Address Offset: 01h Default Value: 00h Attribute: Size: R/W 8 bits This register implements the Feature register of the command block of the IDE function. This register can be written only by the Host. When the HOST reads the same address, it reads the Error register of Device 0 or Device 1 depending on the device_select bit (bit 4 of the drive/head register). Bit 7:0 Description IDE Feature Data (IDEFD) -- R/W. IDE drive specific data written by the Host Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 829 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.3.2.5 IDESCIR--IDE Sector Count In Register (IDER--D22:F2) Address Offset: 02h Default Value: 00h Attribute: Size: R/W 8 bits This register implements the Sector Count register of the command block of the IDE function. This register can be written only by the Host. When host writes to this register, all 3 registers (IDESCIR, IDESCOR0, IDESCOR1) are updated with the written value. A host read to this register address reads the IDE Sector Count Out Register IDESCOR0 if DEV=0 or IDESCOR1 if DEV=1 Bit 7:0 24.3.2.6 Description IDE Sector Count Data (IDESCD)-- R/W. Host writes the number of sectors to be read or written. IDESCOR1--IDE Sector Count Out Register Device 1 Register (IDER--D22:F2) Address Offset: 02h Default Value: 00h Attribute: Size: R/W 8 bits This register is read by the HOST interface if DEV = 1. Intel ME-Firmware writes to this register at the end of a command of the selected device. When the host writes to this address, the IDE Sector Count In Register (IDESCIR), this register is updated. Bit 7:0 24.3.2.7 Description IDE Sector Count Out Dev1 (ISCOD1) -- R/W. Sector Count register for Slave Device (that is, Device 1) IDESCOR0--IDE Sector Count Out Register Device 0 Register (IDER-- D22:F2) Address Offset: 02h Default Value: 00h Attribute: Size: R/W 8 bits This register is read by the HOST interface if DEV = 0. Intel ME-Firmware writes to this register at the end of a command of the selected device. When the host writes to this address, the IDE Sector Count In Register (IDESCIR), this register is updated. Bit 7:0 830 Description IDE Sector Count Out Dev0 (ISCOD0) -- R/W. Sector Count register for Master Device (that is, Device 0). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.3.2.8 IDESNOR0--IDE Sector Number Out Register Device 0 Register (IDER--D22:F2) Address Offset: 03h Default Value: 00h Attribute: Size: R/W 8 bits This register is read by the Host if DEV = 0. Intel ME-Firmware writes to this register at the end of a command of the selected device. When the host writes to the IDE Sector Number In Register (IDESNIR), this register is updated with that value. Bit 7:0 24.3.2.9 Description IDE Sector Number Out DEV 0 (IDESNO0) -- R/W. Sector Number Out register for Master device. IDESNOR1--IDE Sector Number Out Register Device 1 Register (IDER--D22:F2) Address Offset: 03h Default Value: 00h Attribute: Size: R/W 8 bits This register is read by the Host if DEV = 1. Intel ME-Firmware writes to this register at the end of a command of the selected device. When the host writes to the IDE Sector Number In Register (IDESNIR), this register is updated with that value. Bit 7:0 24.3.2.10 Description IDE Sector Number Out DEV 1 (IDESNO1) -- R/W. Sector Number Out register for Slave device. IDESNIR--IDE Sector Number In Register Register (IDER--D22:F2) Address Offset: 03h Default Value: 00h Attribute: Size: R/W 8 bits This register implements the Sector Number register of the command block of the IDE function. This register can be written only by the Host. When host writes to this register, all 3 registers (IDESNIR, IDESNOR0, IDESNOR1) are updated with the written value. Host read to this register address reads the IDE Sector Number Out Register IDESNOR0 if DEV=0 or IDESNOR1 if DEV=1. Bit 7:0 Description IDE Sector Number Data (IDESND) -- R/W. This register contains the number of the first sector to be transferred. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 831 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.3.2.11 IDECLIR--IDE Cylinder Low In Register Register (IDER--D22:F2) Address Offset: 04h Default Value: 00h Attribute: Size: R/W 8 bits This register implements the Cylinder Low register of the command block of the IDE function. This register can be written only by the Host. When host writes to this register, all 3 registers (IDECLIR, IDECLOR0, IDECLOR1) are updated with the written value. Host read to this register address reads the IDE Cylinder Low Out Register IDECLOR0 if DEV=0 or IDECLOR1 if DEV=1. Bit 7:0 24.3.2.12 Description IDE Cylinder Low Data (IDECLD) -- R/W. Cylinder Low register of the command block of the IDE function. IDCLOR1--IDE Cylinder Low Out Register Device 1 Register (IDER--D22:F2) Address Offset: 04h Default Value: 00h Attribute: Size: R/W 8 bits This register is read by the Host if DEV = 1. Intel ME-Firmware writes to this register at the end of a command of the selected device. When the host writes to the IDE Cylinder Low In Register (IDECLIR), this register is updated with that value. 24.3.2.13 Bit Description 7:0 IDE Cylinder Low Out DEV 1. (IDECLO1) -- R/W. Cylinder Low Out Register for Slave Device. IDCLOR0--IDE Cylinder Low Out Register Device 0 Register (IDER--D22:F2) Address Offset: 04h Default Value: 00h Attribute: Size: R/W 8 bits This register is read by the Host if DEV = 0. Intel ME-Firmware writes to this register at the end of a command of the selected device. When the host writes to the IDE Cylinder Low In Register (IDECLIR), this register is updated with that value. 832 Bit Description 7:0 IDE Cylinder Low Out DEV 0. (IDECLO0) -- R/W. Cylinder Low Out Register for Master Device. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.3.2.14 IDCHOR0--IDE Cylinder High Out Register Device 0 Register (IDER--D22:F2) Address Offset: 05h Default Value: 00h Attribute: Size: R/W 8 bits This register is read by the Host if DEVice = 0. Intel ME-Firmware writes to this register at the end of a command of the selected device. When the host writes to the IDE Cylinder High In Register (IDECHIR), this register is updated with that value. 24.3.2.15 Bit Description 7:0 IDE Cylinder High Out DEV 0 (IDECHO0) -- R/W. Cylinder High out register for Master device. IDCHOR1--IDE Cylinder High Out Register Device 1 Register (IDER--D22:F2) Address Offset: 05h Default Value: 00h Attribute: Size: R/W 8 bits This register is read by the Host if Device = 1. Intel ME-Firmware writes to this register at the end of a command of the selected device. When the host writes to the IDE Cylinder High In Register (IDECHIR), this register is updated with that value. 24.3.2.16 Bit Description 7:0 IDE Cylinder High Out DEV 1 (IDECHO1) -- R/W. Cylinder High out register for Slave device. IDECHIR--IDE Cylinder High In Register (IDER--D22:F2) Address Offset: 05h Default Value: 00h Attribute: Size: R/W 8 bits This register implements the Cylinder High register of the command block of the IDE function. This register can be written only by the Host. When host writes to this register, all 3 registers (IDECHIR, IDECHOR0, IDECHOR1) are updated with the written value. Host read to this register address reads the IDE Cylinder High Out Register IDECHOR0 if DEV=0 or IDECHOR1 if DEV=1. Bit Description 7:0 IDE Cylinder High Data (IDECHD) -- R/W. Cylinder High data register for IDE command block. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 833 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.3.2.17 IDEDHIR--IDE Drive/Head In Register (IDER--D22:F2) Address Offset: 06h Default Value: 00h Attribute: Size: R/W 8 bits This register implements the Drive/Head register of the command block of the IDE. This register can be written only by the Host. When host writes to this register, all 3 registers (IDEDHIR, IDEDHOR0, IDEDHOR1) are updated with the written value. Host read to this register address reads the IDE Drive/Head Out Register (IDEDHOR0) if DEV=0 or IDEDHOR1 if DEV=1. Bit 4 of this register is the DEV (master/slave) bit. This bit is cleared by hardware on IDE software reset (S_RST toggles to '1') in addition to Host system reset and D3->D0 transition of the function. 24.3.2.18 Bit Description 7:0 IDE Drive/Head Data (IDEDHD) -- R/W. Register defines the drive number, head number and addressing mode. IDDHOR1--IDE Drive Head Out Register Device 1 Register (IDER-- D22:F2) Address Offset: 06h Default Value: 00h Attribute: Size: R/W 8 bits This register is read only by the Host. Host read to this Drive/head In register address reads the IDE Drive/Head Out Register (IDEDHOR0) if DEV=1 Bit 4 of this register is the DEV (master/slave) bit. This bit is cleared by hardware on IDE software reset (S_RST toggles to '1') in addition to the Host system reset and D3 to D0 transition of the IDE function. When the host writes to this address, it updates the value of the IDEDHIR register. Bit 7:0 24.3.2.19 Description IDE Drive Head Out DEV 1 (IDEDHO1) -- R/W. Drive/Head Out register of Slave device. IDDHOR0--IDE Drive Head Out Register Device 0 Register (IDER--D22:F2) Address Offset: 06h Default Value: 00h Attribute: Size: R/W 8 bits This register is read only by the Host. Host read to this Drive/head In register address reads the IDE Drive/Head Out Register (IDEDHOR0) if DEV=0. Bit 4 of this register is the DEV (master/slave) bit. This bit is cleared by hardware on IDE software reset (S_RST toggles to 1) in addition to the Host system reset and D3 to D0 transition of the IDE function. When the host writes to this address, it updates the value of the IDEDHIR register. Bit 7:0 834 Description IDE Drive Head Out DEV 0 (IDEDHO0) -- R/W. Drive/Head Out register of Master device. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.3.2.20 IDESD0R--IDE Status Device 0 Register (IDER--D22:F2) Address Offset: 07h Default Value: 80h Attribute: Size: R/W 8 bits This register implements the status register of the Master device (DEV = 0). This register is read only by the Host. Host read of this register clears the Master device's interrupt. When the HOST writes to the same address it writes to the command register The bits description is for ATA mode. 24.3.2.21 Bit Description 7 Busy (BSY) -- R/W. This bit is set by HW when the IDECR is being written and DEV=0, or when SRST bit is asserted by Host or host system reset or D3-to-D0 transition of the IDE function. This bit is cleared by FW write of 0. 6 Drive Ready (DRDY) -- R/W. When set, this bit indicates drive is ready for command. 5 Drive Fault (DF)-- R/W. Indicates Error on the drive. 4 Drive Seek Complete (DSC)-- R/W. Indicates Heads are positioned over the desired cylinder. 3 Data Request (DRQ)-- R/W. Set when, the drive wants to exchange data with the Host using the data register. 2 Corrected Data (CORR)-- R/W. When set, this bit indicates a correctable read error has occurred. 1 Index (IDX)-- R/W. This bit is set once per rotation of the medium when the index mark passes under the read/write head. 0 Error (ERR)-- R/W. When set, this bit indicates an error occurred in the process of executing the previous command. The Error Register of the selected device contains the error information. IDESD1R--IDE Status Device 1 Register (IDER--D22:F2) Address Offset: 07h Default Value: 80h Attribute: Size: R/W 8 bits This register implements the status register of the slave device (DEV = 1). This register is read only by the Host. Host read of this register clears the slave device's interrupt. When the HOST writes to the same address it writes to the command register. The bits description is for ATA mode. Bit 7 Description Busy (BSY)-- R/W. This bit is set by hardware when the IDECR is being written and DEV=0, or when SRST bit is asserted by the Host or host system reset or D3-to-D0 transition of the IDE function. This bit is cleared by FW write of 0. 6 Drive Ready (DRDY)-- R/W. When set, indicates drive is ready for command. 5 Drive Fault (DF)-- R/W. Indicates Error on the drive. 4 Drive Seek Complete (DSC) -- R/W. Indicates Heads are positioned over the desired cylinder. 3 Data Request (DRQ) -- R/W. Set when the drive wants to exchange data with the Host using the data register. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 835 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) Bit 24.3.2.22 Description 2 Corrected Data (CORR) -- R/W. When set indicates a correctable read error has occurred. 1 Index (IDX) -- R/W. This bit is set once per rotation of the medium when the index mark passes under the read/write head. 0 Error (ERR) -- R/W. When set, this bit indicates an error occurred in the process of executing the previous command. The Error Register of the selected device contains the error information IDECR--IDE Command Register (IDER--D22:F2) Address Offset: 07h Default Value: 00h Attribute: Size: R/W 8 bits This register implements the Command register of the command block of the IDE function. This register can be written only by the Host. When the HOST reads the same address it reads the Status register DEV0 if DEV=0 or Status Register DEV1 if DEV=1 (Drive/Head register bit [4]). Bit 7:0 24.3.3 Description IDE Command Data (IDECD) -- R/W. Host sends the commands (read/ write, etc.) to the drive using this register. IDER BAR1 Registers Table 24-7. IDER BAR1 Register Address Map 24.3.3.1 Address Offset Register Symbol 2h IDDCR 2h IDASR Default Value Attribute IDE Device Control Register 00h RO, WO IDE Alternate status Register 00h RO Register Name IDDCR--IDE Device Control Register (IDER--D22:F2) Address Offset: 2h Default Value: 00h Attribute: Size: WO 8 bits This register implements the Device Control register of the Control block of the IDE function. This register is Write only by the Host. When the HOST reads to the same address it reads the Alternate Status register. Bit 7:3 836 Description Reserved 2 Software reset (S_RST) -- WO. When this bit is set by the Host, it forces a reset to the device. 1 Host interrupt Disable (nIEN) -- WO. When set, this bit disables hardware from sending interrupt to the Host. 0 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.3.3.2 IDASR--IDE Alternate status Register (IDER--D22:F2) Address Offset: 2h Default Value: 00h Attribute: Size: RO 8 bits This register implements the Alternate Status register of the Control block of the IDE function. This register is a mirror register to the status register in the command block. Reading this register by the HOST does not clear the IDE interrupt of the DEV selected device Host read of this register when DEV=0 (Master), Host gets the mirrored data of IDESD0R register. Host read of this register when DEV=1 (Slave), host gets the mirrored data of IDESD1R register. 24.3.4 Bit Description 7:0 IDE Alternate Status Register (IDEASR)-- RO. This field mirrors the value of the DEV0/ DEV1 status register, depending on the state of the DEV bit on Host reads. IDER BAR4 Registers Table 24-8. IDER BAR4 Register Address Map Address Offset Register Symbol 0h IDEPBMCR 1h IDEPBMDS0R 2h IDEPBMSR Register Name Default Value Attribute IDE Primary Bus Master Command Register 00h RO, R/W IDE Primary Bus Master Device Specific 0 Register 00h R/W IDE Primary Bus Master Status Register 80h RO, R/W 00h R/W 3h IDEPBMDS1R IDE Primary Bus Master Device Specific 1 Register 4h IDEPBMDTPR0 IDE Primary Bus Master Descriptor Table Pointer Register Byte 0 00h R/W 5h IDEPBMDTPR1 IDE Primary Bus Master Descriptor Table Pointer Register Byte 1 00h R/W 6h IDEPBMDTPR2 IDE Primary Bus Master Descriptor Table Pointer Register Byte 2 00h R/W 7h IDEPBMDTPR3 IDE Primary Bus Master Descriptor Table Pointer Register Byte 3 00h R/W 8h IDESBMCR 9h IDESBMDS0R Ah IDESBMSR IDE Secondary Bus Master Command Register 00h RO, R/W IDE Secondary Bus Master Device Specific 0 Register 00h R/W IDE Secondary Bus Master Status Register 00h R/W, RO 00h R/W Bh IDESBMDS1R IDE Secondary Bus Master Device Specific 1 Register Ch IDESBMDTPR0 IDE Secondary Bus Master Descriptor Table Pointer Register Byte 0 00h R/W Dh IDESBMDTPR1 IDE Secondary Bus Master Descriptor Table Pointer Register Byte 1 00h R/W Eh IDESBMDTPR2 IDE Secondary Bus Master Descriptor Table Pointer Register Byte 2 00h R/W Fh IDESBMDTPR3 IDE Secondary Bus Master Descriptor Table Pointer Register Byte 3 00h R/W Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 837 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.3.4.1 IDEPBMCR--IDE Primary Bus Master Command Register (IDER--D22:F2) Address Offset: 00h Default Value: 00h Attribute: Size: RO, R/W 8 bits This register implements the bus master command register of the primary channel. This register is programmed by the Host. Bit 7:4 3 2:1 0 24.3.4.2 Description Reserved Read Write Command (RWC) -- R/W. This bit sets the direction of bus master transfer. 0 = Reads are performed from system memory 1 = Writes are performed to System Memory. This bit should not be changed when the bus master function is active. Reserved Start/Stop Bus Master (SSBM) -- R/W. This bit gates the bus master operation of IDE function when 0. Writing 1 enables the bus master operation. Bus master operation can be halted by writing a 0 to this bit. Operation cannot be stopped and resumed. This bit is cleared after data transfer is complete as indicated by either the BMIA bit or the INT bit of the Bus Master status register is set or both are set. IDEPBMDS0R--IDE Primary Bus Master Device Specific 0 Register (IDER--D22:F2) Address Offset: 01h Default Value: 00h Bit 7:0 24.3.4.3 R/W 8 bits Description Device Specific Data0 (DSD0) -- R/W. Device Specific IDEPBMSR--IDE Primary Bus Master Status Register (IDER--D22:F2) Address Offset: 02h Default Value: 80h Attribute: Size: RO, R/W 8 bits Bit Description 7 Simplex Only (SO) -- RO. Value indicates whether both Bus Master Channels can be operated at the same time or not. 0 = Both can be operated independently 1 = Only one can be operated at a time. 6 Drive 1 DMA Capable (D1DC) -- R/W. This bit is read/write by the host (not write 1 clear). 5 Drive 0 DMA Capable (D0DC) -- R/W. This bit is read/write by the host (not write 1 clear). 4:3 838 Attribute: Size: Reserved 2 Interrupt (INT) -- R/W. This bit is set by the hardware when it detects a positive transition in the interrupt logic (refer to IDE host interrupt generation diagram).The hardware will clear this bit when the Host SW writes 1 to it. 1 Error (ER) -- R/W. Bit is typically set by FW. Hardware will clear this bit when the Host SW writes 1 to it. 0 Bus Master IDE Active (BMIA) -- RO. This bit is set by hardware when SSBM register is set to 1 by the Host. When the bus master operation ends (for the whole command) this bit is cleared by FW. This bit is not cleared when the HOST writes 1 to it. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.3.4.4 IDEPBMDS1R--IDE Primary Bus Master Device Specific 1 Register (IDER--D22:F2) Address Offset: 03h Default Value: 00h Bit 7:0 24.3.4.5 Device Specific Data1 (DSD1) -- R/W. Device Specific Data. IDEPBMDTPR0--IDE Primary Bus Master Descriptor Table Pointer Byte 0 Register (IDER--D22:F2) R/W 8 bits Description 7:0 Descriptor Table Pointer Byte 0 (DTPB0) -- R/W. This register implements the Byte 0 (1 of 4 bytes) of the descriptor table Pointer (four I/O byte addresses) for bus master operation of the primary channel. This register is read/write by the HOST interface. IDEPBMDTPR1--IDE Primary Bus Master Descriptor Table Pointer Byte 1 Register (IDER--D22:F2) Attribute: Size: R/W 8 bits Bit Description 7:0 Descriptor Table Pointer Byte 1 (DTPB1) -- R/W. This register implements the Byte 1 (of four bytes) of the descriptor table Pointer (four I/O byte addresses) for bus master operation of the primary channel. This register is programmed by the Host. IDEPBMDTPR2--IDE Primary Bus Master Descriptor Table Pointer Byte 2 Register (IDER--D22:F2) Address Offset: 06h Default Value: 00h 24.3.4.8 Attribute: Size: Bit Address Offset: 05h Default Value: 00h 24.3.4.7 R/W 8 bits Description Address Offset: 04h Default Value: 00h 24.3.4.6 Attribute: Size: Attribute: Size: R/W 8 bits Bit Description 7:0 Descriptor Table Pointer Byte 2 (DTPB2) -- R/W. This register implements the Byte 2 (of four bytes) of the descriptor table Pointer (four I/O byte addresses) for bus master operation of the primary channel. This register is programmed by the Host. IDEPBMDTPR3--IDE Primary Bus Master Descriptor Table Pointer Byte 3 Register (IDER--D22:F2) Address Offset: 07h Default Value: 00h Attribute: Size: R/W 8 bits Bit Description 7:0 Descriptor Table Pointer Byte 3 (DTPB3) -- R/W. This register implements the Byte 3 (of four bytes) of the descriptor table Pointer (four I/O byte addresses) for bus master operation of the primary channel. This register is programmed by the Host Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 839 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.3.4.9 IDESBMCR--IDE Secondary Bus Master Command Register (IDER--D22:F2) Address Offset: 08h Default Value: 00h Bit 7:4 3 2:1 0 24.3.4.10 Reserved Read Write Command (R/WC) -- R/W. This bit sets the direction of bus master transfer. When 0, Reads are performed from system memory; when 1, writes are performed to System Memory. This bit should not be changed when the bus master function is active. Reserved Start/Stop Bus Master (SSBM) -- R/W. This bit gates the bus master operation of IDE function when zero. Writing 1 enables the bus master operation. Bus master operation can be halted by writing a 0 to this bit. Operation cannot be stopped and resumed. This bit is cleared after data transfer is complete as indicated by either the BMIA bit or the INT bit of the Bus Master status register is set or both are set. IDESBMDS0R--IDE Secondary Bus Master Device Specific 0 Register (IDER--D22:F2) R/W 8 bits Description 7:0 Device Specific Data0 (DSD0) -- R/W. This register implements the bus master Device Specific 1 register of the secondary channel. This register is programmed by the Host. IDESBMSR--IDE Secondary Bus Master Status Register (IDER--D22:F2) Attribute: Size: R/W, RO 8 bits Bit Description 7 Simplex Only (SO) -- R/W. This bit indicates whether both Bus Master Channels can be operated at the same time or not. 0 = Both can be operated independently 1 = Only one can be operated at a time. 6 Drive 1 DMA Capable (D1DC) -- R/W. This bit is read/write by the host. 5 4:0 Drive 0 DMA Capable (D0DC) -- R/W. This bit is read/write by the host. Reserved IDESBMDS1R--IDE Secondary Bus Master Device Specific 1 Register (IDER--D22:F2) Address Offset: 0Bh Default Value: 00h 840 Attribute: Size: Bit Address Offset: 0Ah Default Value: 80h 24.3.4.12 R/W 8 bits Description Address Offset: 09h Default Value: 00h 24.3.4.11 Attribute: Size: Attribute: Size: R/W 8 bits Bit Description 7:0 Device Specific Data1 (DSD1) -- R/W. This register implements the bus master Device Specific 1 register of the secondary channel. This register is programmed by the Host for device specific data if any. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.3.4.13 IDESBMDTPR0--IDE Secondary Bus Master Descriptor Table Pointer Byte 0 Register (IDER--D22:F2) Address Offset: 0Ch Default Value: 00h 24.3.4.14 Description 7:0 Descriptor Table Pointer Byte 0 (DTPB0) -- R/W. This register implements the Byte 0 (1 of 4 bytes) of the descriptor table Pointer (four I/O byte addresses) for bus master operation of the secondary channel. This register is read/write by the HOST interface. IDESBMDTPR1--IDE Secondary Bus Master Descriptor Table Pointer Byte 1 Register (IDER--D22:F2) Attribute: Size: R/W 8 bits Bit Description 7:0 Descriptor Table Pointer Byte 1 (DTPB1) -- R/W. This register implements the Byte 1 (of four bytes) of the descriptor table Pointer (four I/O byte addresses) for bus master operation of the secondary channel. This register is programmed by the Host. IDESBMDTPR2--IDE Secondary Bus Master Descriptor Table Pointer Byte 2 Register (IDER--D22:F2) Address Offset: 0Eh Default Value: 00h 24.3.4.16 R/W 8 bits Bit Address Offset: 0Dh Default Value: 00h 24.3.4.15 Attribute: Size: Attribute: Size: R/W 8 bits Bit Description 7:0 Descriptor Table Pointer Byte 2 (DTPB2) -- R/W. This register implements the Byte 2 (of four bytes) of the descriptor table Pointer (four I/O byte addresses) for bus master operation of the secondary channel. This register is programmed by the Host. IDESBMDTPR3--IDE Secondary Bus Master Descriptor Table Pointer Byte 3 Register (IDER--D22:F2) Address Offset: 0Fh Default Value: 00h Attribute: Size: R/W 8 bits Bit Description 7:0 Descriptor Table Pointer Byte 3 (DTPB3) -- R/W. This register implements the Byte 3 (of four bytes) of the descriptor table Pointer (four I/O byte addresses) for bus master operation of the secondary channel. This register is programmed by the Host. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 841 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.4 Serial Port for Remote Keyboard and Text (KT) Redirection (KT -- D22:F3) 24.4.1 PCI Configuration Registers (KT -- D22:F3) Table 24-9. Serial Port for Remote Keyboard and Text (KT) Redirection Register Address Map 24.4.1.1 Address Offset Register Symbol 00-01h VID Default Value Attribute Vendor Identification 8086h RO Device Identification See Register description RO Register Name 02-03h DID 04-05h CMD Command Register 0000h RO, R/W 06-07h STS Device Status 00B0h RO 08h RID Revision ID See Register description RO 09-0Bh CC Class Codes 070002h RO Cache Line Size 0Ch CLS 10-13h KTIBA 14-17h KTMBA 2C-2Fh SS 30-33h EROM 34h CAP Capabilities Pointer 3C-3Dh INTR C8-C9h PID CA-CBh PC PCI Power Management Capabilities CC-CFh PMCS D0-D1h MID Message Signaled Interrupt Capability ID 0005h RO D2-D3h MC Message Signaled Interrupt Message Control 0080h RO, R/W D4-D7h MA Message Signaled Interrupt Message Address 00000000h RO, R/W Message Signaled Interrupt Message Upper Address 00000000h RO, R/W 0000h R/W D8-DBh MAU DC-DDh MD KT IO Block Base Address RO RO, R/W KT Memory Block Base Address 00000000h RO, R/W Sub System Identifiers 00008086h R/WO Expansion ROM Base Address 00000000h RO C8h RO Interrupt Information 0200h R/W, RO PCI Power Management Capability ID D001h RO PCI Power Management Control and Status Message Signaled Interrupt Message Data 0023h RO 00000000h RO, R/W VID--Vendor Identification Register (KT--D22:F3) Address Offset: 00-01h Default Value: 8086h Bit 15:0 842 00h 00000001h Attribute: Size: RO 16 bits Description Vendor ID (VID) -- RO. This is a 16-bit value assigned by Intel. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.4.1.2 DID--Device Identification Register (KT--D22:F3) Address Offset: 02-03h Default Value: See bit description Bit 15:0 24.4.1.3 Device ID (DID) -- RO. This is a 16-bit value assigned to the PCH KT controller. Refer to the Intel(R) C600 Series Chipset Specification Update for the value of the Device ID Register. CMD--Command Register Register (KT--D22:F3) Bit 15:11 10 9:3 Attribute: Size: RO, R/W 16 bits Description Reserved Interrupt Disable (ID)-- R/W. This bit disables pin-based INTx# interrupts. This bit has no effect on MSI operation. 1 = Internal INTx# messages will not be generated. 0 = Internal INTx# messages are generated if there is an interrupt and MSI is not enabled. Reserved 2 Bus Master Enable (BME)-- R/W. This bit controls the KT function's ability to act as a master for data transfers. This bit does not impact the generation of completions for split transaction commands. For KT, the only bus mastering activity is MSI generation. 1 Memory Space Enable (MSE)-- R/W. This bit controls Access to the PT function's target memory space. 0 I/O Space enable (IOSE)-- R/W. This bit controls access to the PT function's target I/O space. STS--Device Status Register (KT--D22:F3) Address Offset: 06-07h Default Value: 00B0h Bit 15:11 10:9 8:5 Attribute: Size: RO 16 bits Description Reserved DEVSEL# Timing Status (DEVT)-- RO. This field controls the device select time for the PT function's PCI interface. Reserved 4 Capabilities List (CL)-- RO. This bit indicates that there is a capabilities pointer implemented in the device. 3 Interrupt Status (IS)-- RO. This bit reflects the state of the interrupt in the function. Setting of the Interrupt Disable bit to 1 has no affect on this bit. Only when this bit is a 1 and ID bit is 0 is the INTB interrupt asserted to the Host. 2:0 24.4.1.5 RO 16 bits Description Address Offset: 04-05h Default Value: 0000h 24.4.1.4 Attribute: Size: Reserved RID--Revision ID Register (KT--D22:F3) Address Offset: 08h Default Value: See bit description Attribute: Size: RO 8 bits Bit Description 7:0 Revision ID (RID)-- RO. Refer to the Intel(R) C600 Series Chipset Specification Update for the value of the Device ID Register. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 843 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.4.1.6 CC--Class Codes Register (KT--D22:F3) Address Offset: 09-0Bh Default Value: 070002h Bit 23:16 15:8 7:0 24.4.1.7 Attribute: Size: RO 24 bits Description Base Class Code (BCC)--RO This field indicates the base class code of the KT host controller device. Sub Class Code (SCC)--RO This field indicates the sub class code of the KT host controller device. Programming Interface (PI)--RO This field indicates the programming interface of the KT host controller device. CLS--Cache Line Size Register (KT--D22:F3) Address Offset: 0Ch Default Value: 00h Attribute: Size: RO 8 bits This register defines the system cache line size in DWORD increments. Mandatory for master which use the Memory-Write and Invalidate command. Bit 7:0 24.4.1.8 Description Cache Line Size (CLS)-- RO. All writes to system memory are Memory Writes. KTIBA--KT IO Block Base Address Register (KT--D22:F3) Address Offset: 10-13h Default Value: 00000001h Bit 31:16 15:3 2:1 0 24.4.1.9 RO, R/W 32 bits Description Reserved Base Address (BAR)-- R/W. This field provides the base address of the I/O space (8 consecutive I/O locations). Reserved Resource Type Indicator (RTE)-- RO. This bit indicates a request for I/O space KTMBA--KT Memory Block Base Address Register (KT--D22:F3) Address Offset: 14-17h Default Value: 00000000h Bit 31:12 11:4 3 844 Attribute: Size: Attribute: Size: RO, R/W 32 bits Description Base Address (BAR)-- R/W. This field provides the base address for Memory Mapped I,O BAR. Bits 31:12 correspond to address signals 31:12. Reserved Prefetchable (PF)-- RO. This bit indicates that this range is not pre-fetchable. 2:1 Type (TP)-- RO. This field indicates that this range can be mapped anywhere in 32-bit address space. 0 Resource Type Indicator (RTE)-- RO. This bit indicates a request for register memory space. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.4.1.10 SVID--Subsystem Vendor ID Register (KT--D22:F3) Address Offset: 2Ch-2Dh Default Value: 0000h Bit 15:0 Note: 24.4.1.11 R/WO 16 bits Description Subsystem Vendor ID (SSVID) -- R/WO. Indicates the sub-system vendor identifier. This field should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This field can only be cleared by PLTRST#. Register must be written as a DWord write with SID register. SID--Subsystem ID Register (KT--D22:F3) Address Offset: 2Eh-2Fh Default Value: 8086h Attribute: Size: R/WO 16 bits Bit Description 15:0 Subsystem ID (SSID) -- R/WO. Indicates the sub-system identifier. This field should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This field can only be cleared by PLTRST#. Note: 24.4.1.12 Attribute: Size: Register must be written as a DWord write with SVID register. CAP--Capabilities Pointer Register (KT--D22:F3) Address Offset: 34h Default Value: C8h Attribute: Size: RO 8 bits This optional register is used to point to a linked list of new capabilities implemented by the device. Bit 7:0 24.4.1.13 Description Capability Pointer (CP)-- RO. This field indicates that the first capability pointer is offset C8h (the power management capability). INTR--Interrupt Information Register (KT--D22:F3) Address Offset: 3C-3Dh Default Value: 0400h Attribute: Size: R/W, RO 16 bits Bit Description 15:8 Interrupt Pin (IPIN)-- RO. A value of 1h/2h/3h/4h indicates that this function implements legacy interrupt on INTA/INTB/INTC/INTD, respectively. The upper 4 bits are hardwired to 0 and the lower 4 bits are programmed by the KTIP bits (RCBA+3124:bits 15:12). 7:0 Interrupt Line (ILINE)-- R/W. The value written in this register tells which input of the system interrupt controller, the device's interrupt pin is connected to. This value is used by the OS and the device driver, and has no affect on the hardware. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 845 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.4.1.14 PID--PCI Power Management Capability ID Register (KT--D22:F3) Address Offset: C8-C9h Default Value: D001h Bit 15:8 7:0 24.4.1.15 RO 16 bits Description Next Capability (NEXT)-- RO. A value of D0h points to the MSI capability. Cap ID (CID)-- RO. This field indicates that this pointer is a PCI power management. PC--PCI Power Management Capabilities ID Register (KT--D22:F3) Address Offset: CA-CBh Default Value: 0023h Bit 15:11 10:6 Attribute: Size: RO 16 bits Description PME Support (PME)-- RO.This field indicates no PME# in the PT function. Reserved 5 Device Specific Initialization (DSI)-- RO. This bit indicates that no device-specific initialization is required. 4 Reserved 3 PME Clock (PMEC)-- RO. This bit indicates that PCI clock is not required to generate PME# 2:0 24.4.1.16 Attribute: Size: Version (VS)-- RO. This field indicates support for the PCI Power Management Specification, Revision 1.2. MID--Message Signaled Interrupt Capability ID Register (KT--D22:F3) Address Offset: D0-D1h Default Value: 0005h Attribute: Size: RO 16 bits Message Signalled Interrupt is a feature that allows the device/function to generate an interrupt to the host by performing a DWORD memory write to a system specified address with system specified data. This register is used to identify and configure an MSI capable device. Bit 15:8 7:0 846 Description Next Pointer (NEXT)-- RO. This value indicates this is the last item in the list. Capability ID (CID)-- RO. This field value of Capabilities ID indicates device is capable of generating MSI. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.4.1.17 MC--Message Signaled Interrupt Message Control Register (KT--D22:F3) Address Offset: D2-D3h Default Value: 0080h Bit 15:8 7 RO, R/W 16 bits Description Reserved 64 Bit Address Capable (C64)-- RO. Capable of generating 64-bit and 32-bit messages. 6:4 Multiple Message Enable (MME)-- R/W.These bits are R/W for software compatibility, but only one message is ever sent by the PT function. 3:1 Multiple Message Capable (MMC)-- RO. Only one message is required. 0 24.4.1.18 Attribute: Size: MSI Enable (MSIE)-- R/W. If set, MSI is enabled and traditional interrupt pins are not used to generate interrupts. MA--Message Signaled Interrupt Message Address Register (KT--D22:F3) Address Offset: D4-D7h Default Value: 00000000h Attribute: Size: RO, R/W 32 bits This register specifies the DWORD aligned address programmed by system software for sending MSI. Bit Description 31:2 Address (ADDR)-- R/W. Lower 32 bits of the system specified message address, always DWord aligned. 1:0 24.4.1.19 Reserved MAU--Message Signaled Interrupt Message Upper Address Register (KT--D22:F3) Address Offset: D8-DBh Default Value: 00000000h Bit 31:4 3:0 24.4.1.20 Attribute: Size: RO, R/W 32 bits Description Reserved Address (ADDR)-- R/W. Upper 4 bits of the system specified message address. MD--Message Signaled Interrupt Message Data Register (KT--D22:F3) Address Offset: DC-DDh Default Value: 0000h Attribute: Size: R/W 16 bits This 16-bit field is programmed by system software if MSI is enabled Bit 15:0 Description Data (DATA)-- R/W. This MSI data is driven onto the lower word of the data bus of the MSI memory write transaction. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 847 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.4.2 KT IO/ Memory Mapped Device Registers Table 24-10. KT IO/ Memory Mapped Device Register Address Map 24.4.2.1 Address Offset Register Symbol 0h KTRxBR 0h KTTHR 0h KTDLLR 1h KTIER Default Value Register Name Attribute KT Receive Buffer Register 00h RO KT Transmit Holding Register 00h WO KT Divisor Latch LSB Register 00h R/W KT Interrupt Enable register 00h R/W, RO R/W 1h KTDLMR KT Divisor Latch MSB Register 00h 2h KTIIR KT Interrupt Identification register 01h RO 2h KTFCR KT FIFO Control register 00h WO 3h KTLCR KT Line Control register 03h R/W 4h KTMCR KT Modem Control register 00h RO, R/W 5h KTLSR KT Line Status register 00h RO 6h KTMSR KT Modem Status register 00h RO 7h KTSCR KT Scratch register 00h R/W KTRxBR--KT Receive Buffer Register (KT--D22:F3) Address Offset: 00h Default Value: 00h Attribute: Size: RO 8 bits This implements the KT Receiver Data register. Host access to this address, depends on the state of the DLAB bit (KTLCR[7]). It must be 0 to access the KTRxBR. RxBR: Host reads this register when FW provides it the receive data in non-FIFO mode. In FIFO mode, host reads to this register translate into a read from Intel ME memory (RBR FIFO). 24.4.2.2 Bit Description 7:0 Receiver Buffer Register (RBR)-- RO. Implements the Data register of the Serial Interface. If the Host does a read, it reads from the Receive Data Buffer. KTTHR--KT Transmit Holding Register (KT--D23:F3) Address Offset: 00h Default Value: 00h Attribute: Size: RO 8 bits This implements the KT Transmit Data register. Host access to this address, depends on the state of the DLAB bit (KTLCR[7]). It must be 0 to access the KTTHR. THR: When host wants to transmit data in the non-FIFO mode, it writes to this register. In FIFO mode, writes by host to this address cause the data byte to be written by hardware to Intel ME memory (THR FIFO). Bit 7:0 848 Description Transmit Holding Register (THR)-- WO. Implements the Transmit Data register of the Serial Interface. If the Host does a write, it writes to the Transmit Holding Register. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.4.2.3 KTDLLR--KT Divisor Latch LSB Register (KT--D22:F3) Address Offset: 00h Default Value: 00h Attribute: Size: R/W 8 bits This register implements the KT DLL register. Host can Read/Write to this register only when the DLAB bit (KTLCR[7]) is 1. When this bit is 0, Host accesses the KTTHR or the KTRBR depending on Read or Write. This is the standard Serial Port Divisor Latch register. This register is only for software compatibility and does not affect performance of the hardware. Bit 7:0 24.4.2.4 Description Divisor Latch LSB (DLL)-- R/W. Implements the DLL register of the Serial Interface. KTIER--KT Interrupt Enable Register (KT--D22:F3) Address Offset: 01h Default Value: 00h Attribute: Size: R/W 8 bits This implements the KT Interrupt Enable register. Host access to this address, depends on the state of the DLAB bit (KTLCR[7]). It must be "0" to access this register. The bits enable specific events to interrupt the Host. Bit 7:4 24.4.2.5 Description Reserved 3 MSR (IER2)-- R/W. When set, this bit enables bits in the Modem Status register to cause an interrupt to the host. 2 LSR (IER1)-- R/W.When set, this bit enables bits in the Receiver Line Status Register to cause an Interrupt to the Host. 1 THR (IER1)-- R/W. When set, this bit enables an interrupt to be sent to the Host when the transmit Holding register is empty. 0 DR (IER0)-- R/W. When set, the Received Data Ready (or Receive FIFO Timeout) interrupts are enabled to be sent to Host. KTDLMR--KT Divisor Latch MSB Register (KT--D22:F3) Address Offset: 01h Default Value: 00h Attribute: Size: R/W 8 bits Host can Read/Write to this register only when the DLAB bit (KTLCR[7]) is 1. When this bit is 0, Host accesses the KTIER. This is the standard Serial interface's Divisor Latch register's MSB. This register is only for SW compatibility and does not affect performance of the hardware. Bit Description 7:0 Divisor Latch MSB (DLM)-- R/W. Implements the Divisor Latch MSB register of the Serial Interface. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 849 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.4.2.6 KTIIR--KT Interrupt Identification Register (KT--D22:F3) Address Offset: 02h Default Value: 01h Attribute: Size: RO 8 bits The KT IIR register prioritizes the interrupts from the function into 4 levels and records them in the IIR_STAT field of the register. When Host accesses the IIR, hardware freezes all interrupts and provides the priority to the Host. Hardware continues to monitor the interrupts but does not change its current indication until the Host read is over. Table in the Host Interrupt Generation section shows the contents. Bit 7 FIFO Enable (FIEN1)-- RO. This bit is connected by hardware to bit 0 in the FCR register. 6 FIFO Enable (FIEN0)-- RO. This bit is connected by hardware to bit 0 in the FCR register. 5:4 Reserved 3:1 IIR STATUS (IIRSTS)-- RO. These bits are asserted by the hardware according to the source of the interrupt and the priority level. 0 24.4.2.7 Description Interrupt Status (INTSTS)-- RO. 0 = Pending interrupt to Host 1 = No pending interrupt to Host KTFCR--KT FIFO Control Register (KT--D22:F3) Address Offset: 02h Default Value: 00h Attribute: Size: WO 8 bits When Host writes to this address, it writes to the KTFCR. The FIFO control Register of the serial interface is used to enable the FIFOs, set the receiver FIFO trigger level and clear FIFOs under the direction of the Host. When Host reads from this address, it reads the KTIIR. Bit 850 Description 7:6 Receiver Trigger Level (RTL)-- WO. Trigger level in bytes for the RCV FIFO. Once the trigger level number of bytes is reached, an interrupt is sent to the Host. 00 = 01 01 = 04 10 = 08 11 = 14 5:3 Reserved 2 XMT FIFO Clear (XFIC)-- WO. When the Host writes one to this bit, the hardware will clear the XMT FIFO. This bit is self-cleared by hardware. 1 RCV FIFO Clear (RFIC)-- WO. When the Host writes one to this bit, the hardware will clear the RCV FIFO. This bit is self-cleared by hardware. 0 FIFO Enable (FIE)-- WO.When set, this bit indicates that the KT interface is working in FIFO node. When this bit value is changed the RCV and XMT FIFO are cleared by hardware. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) 24.4.2.8 KTLCR--KT Line Control Register (KT--D22:F3) Address Offset: 03h Default Value: 03h Attribute: Size: R/W 8 bits The line control register specifies the format of the asynchronous data communications exchange and sets the DLAB bit. Most bits in this register have no affect on hardware and are only used by the FW. Bit Description 7 Divisor Latch Address Bit (DLAB)-- R/W. This bit is set when the Host wants to read/write the Divisor Latch LSB and MSB Registers. This bit is cleared when the Host wants to access the Receive Buffer Register or the Transmit Holding Register or the Interrupt Enable Register. 6 5:4 3 Parity Enable (PE)-- R/W.This bit has no affect on hardware. 2 Stop Bit Select (SBS)-- R/W. This bit has no affect on hardware. 1:0 24.4.2.9 Break Control (BC)-- R/W. This bit has no affect on hardware. Parity Bit Mode (PBM)-- R/W. This bit has no affect on hardware. Word Select Byte (WSB)-- R/W. This bit has no affect on hardware. KTMCR--KT Modem Control Register (KT--D22:F3) Address Offset: 04h Default Value: 00h Attribute: Size: R/W 8 bits The Modem Control Register controls the interface with the modem. Since the FW emulates the modem, the Host communicates to the FW using this register. Register has impact on hardware when the Loopback mode is on. Bit 7:5 24.4.2.10 Description Reserved 4 Loop Back Mode (LBM)-- R/W. When set by the Host, this bit indicates that the serial port is in loop Back mode. This means that the data that is transmitted by the host should be received. Helps in debug of the interface. 3 Output 2 (OUT2)-- R/W. This bit has no affect on hardware in normal mode. In loop back mode the value of this bit is written by hardware to the Modem Status Register bit 7. 2 Output 1 (OUT1)-- R/W. This bit has no affect on hardware in normal mode. In loop back mode the value of this bit is written by hardware to Modem Status Register bit 6. 1 Request to Send Out (RTSO)-- R/W. This bit has no affect on hardware in normal mode. In loopback mode, the value of this bit is written by hardware to Modem Status Register bit 4. 0 Data Terminal Ready Out (DRTO)-- R/W. This bit has no affect on hardware in normal mode. In loopback mode, the value in this bit is written by hardware to Modem Status Register Bit 5. KTLSR--KT Line Status Register (KT--D22:F3) Address Offset: 05h Default Value: 00h Attribute: Size: WO 8 bits This register provides status information of the data transfer to the Host. Error indication, and so on are provided by the HW/FW to the host using this register. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 851 Intel(R) Management Engine Subsystem Registers (D22:F[3:0]) Bit 7 RX FIFO Error (RXFER)-- RO. This bit is cleared in non FIFO mode. This bit is connected to BI bit in FIFO mode. 6 Transmit Shift Register Empty (TEMT)-- RO. This bit is connected by HW to bit 5 (THRE) of this register. 5 Transmit Holding Register Empty (THRE)-- RO. This bit is always set when the mode (FIFO/ Non-FIFO) is changed by the Host. This bit is active only when the THR operation is enabled by the FW. This bit has acts differently in the different modes: Non FIFO: This bit is cleared by hardware when the Host writes to the THR registers and set by hardware when the FW reads the THR register. FIFO mode: This bit is set by hardware when the THR FIFO is empty, and cleared by hardware when the THR FIFO is not empty. This bit is reset on Host system reset or D3->D0 transition. 4 Break Interrupt (BI)-- RO. This bit is cleared by hardware when the LSR register is being read by the Host. 3:2 24.4.2.11 Description Reserved 1 Overrun Error (OE): This bit is cleared by hardware when the LSR register is being read by the Host. The FW typically sets this bit, but it is cleared by hardware when the host reads the LSR. 0 Data Ready (DR)-- RO. Non-FIFO Mode: This bit is set when the FW writes to the RBR register and cleared by hardware when the RBR register is being Read by the Host. FIFO Mode: This bit is set by hardware when the RBR FIFO is not empty and cleared by hardware when the RBR FIFO is empty. This bit is reset on Host System Reset or D3->D0 transition. KTMSR--KT Modem Status Register (KT--D22:F3) Address Offset: 06h Default Value: 00h Attribute: Size: RO 8 bits The functionality of the Modem is emulated by the FW. This register provides the status of the current state of the control lines from the modem. Bit Description 7 Data Carrier Detect (DCD)-- RO. In Loop Back mode this bit is connected by hardware to the value of MCR bit 3. 6 Ring Indicator (RI)-- RO. In Loop Back mode this bit is connected by hardware to the value of MCR bit 2. 5 Data Set Ready (DSR)-- RO. In Loop Back mode this bit is connected by hardware to the value of MCR bit 0. 4 Clear To Send (CTS)-- RO. In Loop Back mode this bit is connected by hardware to the value of MCR bit 1. 3 Delta Data Carrier Detect (DDCD)-- RO. This bit is set when bit 7 is changed. This bit is cleared by hardware when the MSR register is being read by the HOST driver. 2 Trailing Edge of Read Detector (TERI)-- RO. This bit is set when bit 6 is changed from 1 to 0. This bit is cleared by hardware when the MSR register is being read by the Host driver. 1 Delta Data Set Ready (DDSR)-- RO. This bit is set when bit 5 is changed. This bit is cleared by hardware when the MSR register is being read by the Host driver. 0 Delta Clear To Send (DCTS)-- RO. This bit is set when bit 4 is changed. This bit is cleared by hardware when the MSR register is being read by the Host driver. 852 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25 PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1 PCI Express* Upstream Configuration Registers (PCI Express*--D0:F0) Note: Register address locations that are not shown in Table 25-1 and should be treated as Reserved. / Table 25-1. PCI Express* UpStream Configuration Registers Address Map (PCI Express*--D0:F0) (Sheet 1 of 3) Function 0-5 Default Attribute Vendor Identification 8086h RO Device Identification See register description RO 0000h R/W, RO 0010h R/WC, RO See register description RO Offset Mnemonic 00h-01h VID 02h-03h DID 04h-05h PCICMD PCI Command 06h-07h PCISTS PCI Status 08h RID 09-0Bh PI 0Ch CLS 0Dh PLT 0Eh HEADTYP 10-13h EXPPTMBAR 18h PRINUM Register Name Revision Identification Programming Interface Register Cache Line Size see description RO 00h R/W Primary Latency Timer 00h RO Header Type 81h RO Express Port Memory Base Address RO, R/W Primary Bus Number 00h R/W 19h SECBUS Secondary Bus Number 00h R/W 1Ah SUBBUS Subordinate Bus Number 00h R/w 1Bh SLT Secondary Latency Timer 00h RO 1Chh IOBL I/O Base 00h R/W, RO 1D IOBL I/O Limit Register 00h R/W, RO 1Eh-1Fh SSTS Secondary Status Register 0000h R/WC 20h-21h MBL Memory Base 0000h R/W 22-23h MBL Memory Limit 0000h R/W 24h-27h PMBL Prefetchable Memory Base 0001h R/W, RO 26-27h PMBL Prefetchable Limit 0001h R/W, RO 28h-2Bh PMBU32 Prefetchable Memory Base Upper 32 Bits 00000000h R/W 2Ch-2Fh PMLU32 Prefetchable Memory Limit Upper 32 Bits 00000000h R/W 34h CAPP 3Ch-3Dh INTR 3Eh-3Fh BCTRL Capabilities List Pointer Interrupt Information Bridge Control Register Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 40h RO See bit description R/W, RO 0000h R/W 853 PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) Table 25-1. PCI Express* UpStream Configuration Registers Address Map (PCI Express*--D0:F0) (Sheet 2 of 3) 854 Offset Mnemonic Register Name 40h-41h CLIST Capabilities List 42h-43h XCAP PCI Express* Capabilities 44h-47h DCAP Device Capabilities Function 0-5 Default Attribute 8010 RO 0052 R/WO, RO 00008001h RO 48h-49h DCTL Device Control 2000h R/W, RO 4Ah-4Bh DSTS Device Status 0000h R/WC, RO 4Ch-4Fh LCAP Link Capabilities See bit description R/W, RO, R/WO 50h-51h LCTL Link Control 0000h R/W, WO, RO 52h-53h LSTS Link Status See bit description RO 64h-67h DCAP2 Device Capabilities 2 Register 00000016h RO 68h-69h DCTL2 Device Control 2 Register 0000h R/W, RO 6A-6B DEVSTS2 Device Status 2 Register 0000 RO 70h-71h LCTL2 72-73h LINKSTS2 Link Control 2 Register 80h-81h PMCAP Power Management Capability 0001 RO 82h-83h PMC PCI Power Management Capabilities C803 R/W, RO 84h-85h PMCSR PCI Power Management Control and Status 0004 R/W, RO 86h PMBSE Power Management Bridge Support Extensions 00 RO 88-89h SVCAP Susbsytem Capability List 000D RO 8C-8D SVID Subsystem Vendor Identification 8086 R/WO Link Status 2 Subsytem ID Register 0003h RO 0000 RO 8E-8F SVID 100-103h AERCAPHDR 0000 R/WO see description RO, R/WO 104h-107h UES Uncorrectable Error Status See bit description R/WC, RO 108h-10Bh UEM Uncorrectable Error Mask 00000000h R/WO, RO 10Ch-10Fh UEV Uncorrectable Error Severity See Description RO 110h-113h CES Correctable Error Status 00000000h R/WC 114h-117h CEM Correctable Error Mask 00000000h R/WO 118h-11Bh AECC Advanced Error Capabilities and Control 00000000h RO 11C-11Fh AEHRDLOG1 Advanced Header Log 0000h RO 120-123h AEHRDLOG2 Advanced Header Log 0000h RO Advanced Error Reporting Capabilities 124-127h AEHRDLOG3 Advanced Header Log 0000h RO 128-12Bh AEHDRLOG4 Advanced Header Log 0000h RO 140h-143h ERRUNCDETMSK Uncorrectable Error Detect Mask 00000000h R/WO, RO 144h-147h ERRCORDETMSK Correctable Error Detect Mask 00000000 R/WO, RO Multicast Extended Capability Header 150-153 MCSTCAPHDR 00010012 RO, R/WO 154-155h MCSTCAP Multicast Capability Register 8000 RO 156-157 MCSTCTL Multicast Control Register 0000 RO,R/W Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) Table 25-1. PCI Express* UpStream Configuration Registers Address Map (PCI Express*--D0:F0) (Sheet 3 of 3) 25.1.1 Offset Mnemonic 158-15B MCSTBAR 15C-15F MCSTUBAR 160-163h MCSTRCV Function 0-5 Default Attribute Multicast Base Address Register 0000000C R/W Multicast Upper Base Address 00000000 R/W Multicast Receive 00000000 RO, R/W Register Name 164-167h MCSTRCV2 Multicast Receive 2 00000000 RO 168-16Bh MCSTBLKALL Multicast Block All 00000000 RO, R/W 16C-16F MCSTBLKALL2 170-173 MCSTRCV 174-177 MCSTRCV2 178-17B MCSTBAR 17C-17F MCSTUBAR Multicast Block All 2 00000000 RO Multicast Block Untranslate 00000000 RO, R/W Multicast Block Untranslate 2 00000000 RO Multicast Overlay Base Address 00000000 R/W Multicast Upper Overlay Base 00000000 R/W VID--Vendor Identification Register (PCI Express*--D0:F0) Address Offset: 00h-01h Default Value: 8086h Bit 15:0 25.1.2 Attribute: Size: RO 16 bits Description Vendor ID -- RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h DID--Device Identification Register (PCI Express*--D0:F0) Address Offset: 02h-03h Default Value: Bit Description Bit 15:0 Attribute: Size: RO 16 bits Description Device ID -- RO. This is a 16-bit value assigned to the PCH's PCI Express* controller. Refer to the Intel(R) C600 Series Chipset Specification Update for the value of the Device ID Register Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 855 PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.3 PCICMD--PCI Command Register (PCI Express*--D0:F0) Address Offset: 04h-05h Default Value: 0000h Bit 15:11 10 856 Attribute: Size: R/W, RO 16 bits Description Reserved Interrupt Disable -- R/W. This bit controls the ability of the PCI-Express Function to generate legacy INTx interrupt message 0 = Internal INTx# messages are generated for PCI-Express errors detected internally in this port (for example, Malformed TLP, CRC error, completion time out etc.) or when receiving root port error messages or interrupts due to HP/PM events generated in legacy mode. 1 = Internal INTx# messages will not be generated. This bit does not affect interrupt forwarding from devices connected to the root port. Assert_INTx and Deassert_INTx messages will still be forwarded to the internal interrupt controllers if this bit is set. 9 Fast Back to Back Enable (FBE) -- Reserved per the PCI Express* Base Specification. 8 SERR# Enable (SEE) -- R/W. 0 = Disable. 1 = this bit enables reporting of Non-Fatal and Fatal errors detected by the Function of the Root Complex. For Type 1 Configuration Space headers, this bit controls transmission by the primary interface of ERR_NONFATAL and ERR_FATAL error messages forwarded from the secondary interface. ERR_COR messages are not affected by this bit... 7 Wait Cycle Control (WCC) -- Reserved per the PCI Express* Base Specification. 6 Parity Error Response (PER) -- R/W. 0 = Disable. 1 = This bit controls the setting of the master data parity error bit in the Status Register in response to a parity error received on the PCI Express interface . 5 VGA Palette Snoop (VPS) -- Reserved per the PCI Express* Base Specification. 4 Postable Memory Write Enable (PMWE) -- Reserved per the PCI Express* Base Specification. 3 Special Cycle Enable (SCE) -- Reserved per the PCI Express* Base Specification. 2 Bus Master Enable (BME) -- R/W. 0 = Disable. memory and I/O requests received at the root port or downstream side of a switch port (secondary side) must be handled as an Unsupported Request (UR). For Non-posted requests, a completion with UR completion status must be returned 1 = Enable. Allows the root port or switch to forward memory and I/O read or write requests in the upstream direction. 1 Memory Space Enable (MSE) -- R/W. 0 = Disable. The function will handle memory transactions targeting the Function as an Unsupported Request (UR). 1 = Enable. Allows memory cycles within the range specified by the memory base and limit registers can be forwarded. 0 I/O Space Enable (IOSE) -- R/W. This bit controls access to the I/O space registers. 0 = Disable. The function will handle I/O transactions targeting the Function as an Unsupported Request (UR). 1 = Enable. Allows I/O cycles within the range specified by the I/O base and limit registers can be forwarded. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.4 PCISTS--PCI Status Register (PCI Express*--D0:F0) Address Offset: 06h-07h Default Value: 0010h Attribute: Size: R/WC, RO 16 bits Bit Description 15 Detected Parity Error (DPE) -- R/WC. 0 = No parity error detected. 1 = This bit is set when a poisoned TLP is received from PCI Express. This bit is set even when the parity error response enable bit (bit[6] of the PCICMD Register) is not set. On Type 1 configuration header functions, the bit is set when the poisoned TLP is received on the primary sideSet when the... 14 Signaled System Error (SSE) -- R/WC. 0 = No system error signaled. 1 = This bit is set when ERR_FATAL or ERR_NONFATAL messages are sent to the root complex and the SERR enable bit in the PCICMD Register is set. 13 Received Master Abort (RMA) -- R/WC. 0 = Port has not received a completion with unsupported request status. 1 = This bit is set when the requester receives a completion with an UR completion status. On Type 1 configuration header functions, the bit is set when a UR completions status is received on the primary side. 12 Received Target Abort (RTA) -- R/WC. 0 = Port has not received a completion with completer abort. 1 = This bit is set when a requester receives a CA completions status. On Type 1 configuration header functions, the bit is set when a "Completer Abort" is received on the primary side. 11 Signaled Target Abort (STA) -- R/WC. 0 = No target abort received. Signaled Target Abort (STA): 1 = This bit is Set when the port completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function with a Type 1 Configuration header when the Completer Abort was generated by its Primary Side. 10:9 DEVSEL# Timing Status (DEV_STS) -- Reserved per the PCI Express* Base Specification. 8 Master Data Parity Error Detected (DPED) -- R/WC. 0 = No data parity error received. 1 = This bit is set by a requester (primary side for type1 configuration header functions) if the parity error response enable bit (PERE) in the Command Register is set and either of the following two conditions occur: *Requester receives a completion marked poisoned. *Requester sends a poisoned request (includes writes and messages) If the parity error bit is 0b, this bit is never set. 7 Fast Back to Back Capable (FB2BC) -- Reserved per the PCI Express* Base Specification. 6 Reserved 5 66 MHz Capable -- Reserved per the PCI Express* Base Specification. 4 Capabilities List -- RO. Hardwired to 1. Indicates the presence of a capabilities list. 3 Interrupt Status -- RO. 0 = Interrupt is deasserted. 1 = this bit indicates that an INTx emulation interrupt is pending internally in this function for Type 1 configuration header functions, forwarded INTx messages are not reflected in this bit. unless the INTx messages is being generated from the Type 1 configuration header functioned. 2:0 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 857 PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.5 RID--Revision Identification Register (PCI Express*--D0:F0) Offset Address: 08h Default Value: See bit description 25.1.6 Attribute: Size: Bit Description 7:0 Revision ID -- RO. Refer to the Intel(R) C600 Series Chipset Specification Update for the value of the Revision ID Register PI--Programming Interface Register (PCI Express*--D0:F0) Address Offset: 09h Default Value: 060400h Bit 23:16 15:8 7:0 25.1.7 RO 24 bits Base Class -- RO. 06h = This is a bridge device. SubClass Interface -- RO 04h = this device is a PCI to PCI bridge Programming Interface -- RO. 00h = No specific register level programming interface defined. CLS--Cache Line Size Register (PCI Express*--D0:F0) Bit 7:0 Attribute: Size: R/W 8 bits Description Cache Line Size (CLS) -- R/W. This is read/write but contains no functionality, per the PCI Express* Base Specification. PLT--Primary Latency Timer Register (PCI Express*--D0:F0) Address Offset: 0Dh Default Value: 00h Bit 858 Attribute: Size: Description Address Offset: 0Ch Default Value: 00h 25.1.8 RO 8 bits Attribute: Size: RO 8 bits Description 7:3 Latency Count. Reserved per the PCI Express* Base Specification. 2:0 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.9 HEADTYP--Header Type Register (PCI Express*--D0:F0) Address Offset: 0Eh Default Value: 81h Bit 7 6:0 25.1.10 Attribute: Size: Description Multi-Function Device -- RO. 1 = Multi-function device. Configuration Layout-- RO. These bits define the layout of addresses 10h through 3Fh in the configuration space. These bits read as 01h to indicate that the register layout conforms to the standard PCI-to-PCI Bridge layout. EXPPTMBAR_U--Express Port Memory Base Address Register (PCI Express*--D0:F0) Address Offset: 10-13h Default Value: 00000000h Bit 31:14 13:4 3 2:1 0 25.1.11 RO 8 bits Attribute: Size: RO, R/W 32 bits Description Memory Base Address-- R/W. Memory Size-- R0. Hardwired to all `0' Prefetchable Memory (PFMEM)-- R0. Hardwired to all 0, not prefetchable Memory Type (MTYPE)-- R0. Indicates 32 bit address space Memory Space Indicator (MSI)-- R0. 0b = Memory space PRIBUS--Primiary Bus Number Register (PCI Express*--D0:F0 Address Offset: 18h Default Value: 00h Bit Attribute: Size: R/W 8 bits Description Primary Bus Number (PBN) -- R/W. 7:0 These bits indicate the PCI Express bus number. Any Type 1 configuration cycle with a bus number less than this number is not accepted by this bridge (in other words, it may still match the other bridge). Indicates the bus number of the backbone. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 859 PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.12 SECBUS--Secondary Bus Number Register (PCI Express*--D0:F0) Address Offset: 19h Default Value: 00h 25.1.13 Attribute: Size: Bit Description 7:0 Secondary Bus Number (SCBN): These bits indicate the bus number of the PCI device to which the secondary interface is connected. Any Type 1 configuration cycle matching this bus number is translated to a Type 0 configuration cycle and run on the PCI bus. SUBBus--Subordinate Bus Number Register (PCI Express*--D0:F0) Address Offset: 1Ah Default Value: 00h 25.1.14 Attribute: Size: Description 7:0 Subordinate Bus Number (SBBN): These bits indicate the highest PCI bus number downstream of this bridge. Every Type 1 configuration cycle on PCI Express with a bus number greater than the secondary bus number and less than or equal to the subordinate bus number is forwarded as a Type 1 configuration cycle to the secondary PCI bus. IOBL--I/O Base Register (PCI Express*--D0:F0) Attribute: Size: R/W, RO 8 bits Bit Description 7:4 I/O Base Address Bits (IOBA): These bits define the bottom address of an address range to determine when to forward I/O transactions from one interface to another. These bits correspond to address lines[15:12] for 4 KB alignment. Bits[11:0] are assumed to be 000h. 3:0 I/O Base Addressing Capability (IOBC): Each of these bits is hard-wired to 0, indicating support for 16-bit I/O addressing only. IOLIMIT--I/O Limit Register (PCI Express*--D0:F0) Address Offset: 1Dh Default Value: 0000h Bit 860 R/W 8 bits Bit Address Offset: 1Ch Default Value: 00h 25.1.15 R/W 8 bits Attribute: Size: R/W, RO 8 bits Description 7:4 I/O Limit Address Bits (IOLA): These bits define the top address of an address range to determine when to forward I/O transactions from PCI Express to PCI. These bits correspond to address lines[15:12] for 4 KB aligned window. Bits[11:0] are assumed to be FFFh. 3:0 I/O Limit Addressing Capability (IOLC): Each of these bits is hard-wired to 0, indicating support for 16-bit I/O addressing only. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.16 SSTS--Secondary Status Register (PCI Express*--D0:F0) Address Offset: 1Eh-1Fh Default Value: 0000h Attribute: Size: R/WC 16 bits Bit Description 15 Detected Parity Error (DPE) -- R/WC. 0 = No error. 1 = This bit is set by the secondary side for a Type 1 Configuration Space header function whenever it receives a Poisoned TLP, regardless of the state in the Parity Error Response Enable (PERE) field of the Bridge Control Register (BCTL) 14 Received System Error (RSE) -- R/WC. 0 = No error. 1 = This bit is set by the secondary side for a Type 1 Configuration Space header function whenever it receives an ERR_FATAL or ERR_NONFATAL message. 13 Received Master Abort (RMA) -- R/WC. 0 = Unsupported Request not received. 1 = This bit is set when the secondary side for Type 1 configuration space header function (for requests initiated by the Type 1 header function itself) receives a completion with Unsupported Requests Completion Status... 12 Received Target Abort (RTA) -- R/WC. 0 = Completion Abort not received. 1 = This bit is set when the secondary side for Type 1 Configuration Space Header Function (for Requests initiated by the Type 1 header Function itself) receives a completion with Completer About Completion Status... 11 Signaled Target Abort (STA) -- R/WC. 0 = Completion Abort not sent. 1 = This bit is set when the secondary side for Type 1 configuration space header function (for requests completed by type 1 header functions itself) completes a Posted or Non-posted request as a Completer Abort error. 10:9 Secondary DEVSEL# Timing Status (SDTS): Reserved per PCI Express* Base Specification. 8 Data Parity Error Detected (DPD) -- R/WC. 0 = Conditions below did not occur.. 1 = This bit is set by the secondary side requester if the Parity Error Response Enable (PERE) bit in the Bridge Control Register (BCTL) is set and either of the following conditions occur * Requester receives completion marked poisoned * Requester sends a poisoned request (includes writes and messages) 7 Secondary Fast Back to Back Capable (SFBC): Reserved per PCI Express* Base Specification. 6 Reserved 5 Secondary 66 MHz Capable (SC66): Reserved per PCI Express* Base Specification. 4:0 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 861 PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.17 MEMBASE--Memory Base Register (PCI Express*--D0:F0) Address Offset: 20h-21h Default Value: 0000h Description 15:4 Memory Base (MB) -- R/W. These bits are compared with bits[31:20] of the incoming address to determine the lower 1 MB-aligned value (inclusive) of the range. The incoming address must be greater than or equal to this value. Reserved MEMLIMIT--Memory Limit Register (PCI Express*--D0:F0) Address Offset: 22h-23h Default Value: 0000h 15:4 Memory Limit (ML) -- R/W. These bits are compared with bits[31:20] of the incoming address to determine the upper 1 MB-aligned value (exclusive) of the range. The incoming address must be less than this value. Reserved PFBASE--Prefetchable Memory Base (PCI Express*--D0:F0) Attribute: Size: R/W, RO 16 bits Bit Description 15:4 Prefetchable Memory Base (PMB) -- R/W. These bits are compared with bits[31:20] of the incoming address to determine the lower 1 MB-aligned value (inclusive) of the range. The incoming address must be greater than or equal to this value. 3:0 64-bit Indicator (I64B) -- RO 0 = 32-bit Prefetchable Memory addressing. 1 = 64-bit Prefetchable Memory addressing. This field indicates that 64-bit addressing is supported for the limit. PFLIMIT--Prefetchable Limit Register (PCI Express*--D0:F0) Address Offset: 26h-27h Default Value: 0001h Attribute: Size: R/W, RO 16 bits Bit Description 15:4 Prefetchable Memory Limit (PML) -- R/W. These bits are compared with bits[31:20] of the incoming address to determine the upper 1 MB-aligned value (inclusive) of the range. The incoming address must be less than this value. 3:0 862 R/W 16 bits Description Address Offset: 24h-25h Default Value: 0001h 25.1.20 Attribute: Size: Bit 3:0 25.1.19 R/W 16 bits Bit 3:0 25.1.18 Attribute: Size: 64-bit Indicator (I64L) -- RO. Indicates support for 64-bit addressing Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.21 PMBU32--Prefetchable Memory Base Upper 32 Bits Register (PCI Express*--D0:F0) Address Offset: 28h-2Bh Default Value: 00000000h Bit 31:0 25.1.22 Prefetchable Memory Base Upper Portion (PMBU) -- R/W. Lower 32-bits of the prefetchable address base. PMLU32--Prefetchable Memory Limit Upper 32 Bits Register (PCI Express*--D0:F0) Bit 31:0 Attribute: Size: R/W 32 bits Description Prefetchable Memory Limit Upper Portion (PMLU) -- R/W. Upper 32-bits of the prefetchable address limit. CAPP--Capabilities List Pointer Register (PCI Express*--D0:F0) Address Offset: 34h Default Value: 40h Bit 7:0 25.1.24 R/W 32 bits Description Address Offset: 2Ch-2Fh Default Value: 00000000h 25.1.23 Attribute: Size: Attribute: Size: R0 8 bits Description Capabilities Pointer (PTR) -- RO. Indicates that the pointer for the first entry in the capabilities list is at 40h in configuration space. INTR--Interrupt Information Register (PCI Express*--D0:F0) Address Offset: 3Ch-3Dh Default Value: See bit description Function Level Reset: No (Bits 7:0 only) Bit 15:8 7:0 Attribute: Size: R/W, RO 16 bits Description Interrupt Pin (IPIN) -- RO. This register tells which interrupt pin the function uses. 01h: Generate INTA 02h: Generate INTB 03h: Generate INTC 04h: Generate INTD Others: Reserved BIOS has the ability to write this register once during boot to setup the correct interrupt for the Function. Note: Lock Key bit is located in the Personality Lock Key Control Register Interrupt Line (ILINE) -- R/W. Default = 00h. Software written value to indicate which interrupt line (vector) the interrupt is connected to. No hardware action is taken on this register. These bits are not reset by FLR. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 863 PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.25 BCTRL--Bridge Control Register (PCI Express*--D0:F0) Address Offset: 3Eh-3Fh Default Value: 0000h Bit 15:12 864 Attribute: Size: R/W 16 bits Description Reserved 11 Discard Timer SERR# Enable (DTSE): Reserved per PCI Express* Base Specification, Revision 2.1 10 Discard Timer Status (DTS): Reserved per PCI Express* Base Specification, Revision 2.1. 9 Secondary Discard Timer (SDT): Reserved per PCI Express* Base Specification, Revision 2.1. 8 Primary Discard Timer (PDT): Reserved per PCI Express* Base Specification, Revision 2.1. 7 Fast Back to Back Enable (FBE): Reserved per PCI Express* Base Specification, Revision 2.1. 6 Secondary Bus Reset (SBR) -- R/W. Setting this bit triggers a hot reset on the downstream link for the corresponding PCI Express* port and the PCI Express* hierarchy domain subordinate to the port. Software must ensure a minimum reset duration of 1 us as defined in the PCI Local Bus Specification, Revision 3.0. Hardware will continue to maintain the hot reset state as long as the SBR bit is set. For Root Ports/switch, it is recommended that software assert this field for a minimum of 2 ms to ensure that all downstream links enters hot reset state. For a Switch, the following must cause a hot reset to be sent on all Downstream Ports: * Setting the Secondary Bus Reset bit of the Bridge Control register associated with the Upstream Port * The Data Link Layer of the Upstream Port reporting DL_Down status 30 * Receiving a hot reset on the Upstream Port A secondary bus reset will not reset any register of a Type 1 configuration space header function. 5 Master Abort Mode (MAM): Reserved per Express specification. 4 VGA 16-Bit Decode (V16) -- R/W. This bit enables the bridge to provide 16-bit decoding of VGA I/O address precluding the decoding of VGA alias addresses every 1 KB. This bit requires the VGA enable bit (bit 3 of this register) to be set to 1. 0 = execute 10-bit address decode on VGA I/O accesses 1 = execute 16-bit address decode on VGA I/O accesses 3 VGA Enable (VE)-- R/W. 0 = The ranges below will not be claimed off the backbone by the root port. 1 = This bit modifies the response to VGA-compatible addresses. When set to 1b, the bridge positively decodes and forwards the following transactions from primary side to secondary side regardless of the value of the I/O base and limit registers. The transactions are qualified by the memory enable and I/O enable in the command register. Memory addresses: 000A 0000h-000B FFFFh I/O addresses: 3B0h-3BBh and 3C0h-3DFh in first 64 KB of I/O address space (Inclusive of ISA address aliases when IO address bits[15:10] are not decoded) The following ranges will be claimed off the backbone by the root port: * Memory ranges A0000h-BFFFFh * I/O ranges 3B0h - 3BBh and 3C0h - 3DFh, and all aliases of bits 15:10 in any combination of 1s Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.26 Bit Description 2 ISA Enable (IE) -- R/W. This bit modifies the response by the bridge to ISA I/O addresses. This field applies only to I/O addresses that are enabled by the I/O base and I/O limit registers and are in the first 64 KB of PCI I/O space. When this bit is set, the bridge blocks all forwarding from primary to secondary of I/O transactions addressing the last 768 bytes in each 1 KB block (offsets 100h to 3FFh). In the opposite direction (secondary to primary), I/O transactions will be forwarded if they address the last 768B in each 1 KB block. 1: Forward upstream ISA I/O addresses in the address range defined yb the I/O Base and I/O Limit registers that are in the firsts 64KB of PCI I/O address space (Top 768B of each 1K block). 0: Forward downstream all I/O addresses in the address range defined by the I/O Base and I/O Limit registers. 1 SERR# Enable (SE) -- R/W. This bit controls the forwarding of PCI Express ERR_COR, ERR_NONFATAL and ERR_FATAL messages to the primary side. 1: Enables forwarding of ERR_COR, ERR_NONFATAL, ERR_FATAL messages. 0: Disables forwarding of ERR_COR, ERR_NONFATAL, ERR_FATAL messages. 0 Parity Error Response Enable (PERE) -- R/W., This bit controls the response to poisoned TLPs in the PCI Express* port. 1: Enables reporting of poisoned TLP errors. 0: Disables reporting of poisoned TLP errors CLIST--Capabilities List Register (PCI Express*--D0:F0) Address Offset: 40-41h Default Value: 8010h Bit 15:8 7:0 25.1.27 Attribute: Size: RO 16 bits Description Next Capability (NEXT) -- RO. Value of 80h indicates the location of the next pointer. Capability ID (CID) -- RO. Indicates this is a PCI Express* capability. XCAP--PCI Express* Capabilities Register (PCI Express*--D0:F0) Address Offset: 42h-43h Default Value: 0052h Bit 15:14 13:9 8 Attribute: Size: R/WO, RO 16 bits Description Reserved Interrupt Message Number (IMN) -- RO. The PCH does not have multiple MSI interrupt numbers. Slot Implemented (SI) -- RO. Hardwired to 0 for non root ports and non DP 7:4 Device / Port Type (DT) -- RO. 5h: Upstream port of a PCIe* switch 3:0 Capability Version (CV) -- RO. Indicates PCI Express* 2.0. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 865 PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.28 DCAP--Device Capabilities Register (PCI Express*--D0:F0) Address Offset: 44h-47h Default Value: 00008001h Bit Description Reserved 27:26 Captured Slot Power Limit Scale (CSPS) -- RO-V In combination with the Slot Power Limit value (bits[25:18], this field specifies the upper limit of the power supplied by slot. The power limit (in Watts) is calculated by multiplying the value in this field by the value in the Slot Power Limit Value field. This value is set by the Set_Slot_Power_Limit message. 25:18 Captured Slot Power Limit Value (CSPV) -- RO-V In combination with the Slot Power Limit Scale value (bits[27:26]), this field specifies the upper limit of the power supplied by slot. The power limit (in Watts) is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field. This value is set by the Set_Slot_Power_Limit message. 17:16 Reserved 14:12 Role Based Error Reporting (RBER) -- RO. Indicates that this device implements the functionality defined in the Error Reporting ECN as required by the PCI Express* 1.1 spec. Reserved 11:9 Endpoint L1 Acceptable Latency (E1AL) -- RO. This field is reserved with a setting of 000b for devices other than Endpoints, per the PCI Express* 1.1 Spec. 8:6 Endpoint L0s Acceptable Latency (E0AL) -- RO. This field is reserved with a setting of 000b for devices other than Endpoints, per the PCI Express* 1.1 Spec. 5 Extended Tag Field Supported (ETFS) -- RO. Indicates that a 5-bit tag fields are supported. 4:3 Phantom Functions Supported (PFS) -- RO. No phantom functions supported. 2:0 Max Payload Size Supported (MPS) -- RO. Indicates the maximum payload size supported is 256B. DCTL--Device Control Register (PCI Express*--D0:F0) Address Offset: 48h-49h Default Value: 2000h Bit 15 14:12 Attribute: Size: R/W, RO 16 bits Description Reserved Max Read Request Size (MRRS) -- R/W. 512Bytes is the maximum read request size. 11 Enable No Snoop (ENS) -- RO. Not supported. The root port will never issue non-snoop requests. 10 Aux Power PM Enable (APME) -- R0. Not supported, hardwired to 0. 9 Phantom Functions Enable (PFE) -- RO. Not supported. 8 Extended Tag Field Enable (ETFE) -- RO. Not supported. 7:5 866 RO 32 bits 31:28 15 25.1.29 Attribute: Size: Max Payload Size (MPS) -- R/W. 128 bytes is the default, but 256 is also supported. Not other sizes are supported. 4 Enable Relaxed Ordering (ERO) -- RO. Not supported. 3 Unsupported Request Reporting Enable (URE) -- R/W. 0 = The root port will ignore unsupported request errors. 1 = Allows signaling ERR_NONFATAL, ERR_FATAL, or ERR_COR to the Root Control register when detecting an unmasked Unsupported Request (UR). An ERR_COR is signaled when a unmasked Advisory Non-Fatal UR is received. An ERR_FATAL, ERR_or NONFATAL, is sent to the Root Control Register when an uncorrectable non-Advisory UR is received with the severity set by the Uncorrectable Error Severity register. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.30 Bit Description 2 Fatal Error Reporting Enable (FEE) -- R/W. 0 = The root port will ignore fatal errors. 1 = Enables signaling of ERR_FATAL to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting. 1 Non-Fatal Error Reporting Enable (NFE) -- R/W. 0 = The root port will ignore non-fatal errors. 1 = Enables signaling of ERR_NONFATAL to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting. 0 Correctable Error Reporting Enable (CEE) -- R/W. 0 = The root port will ignore correctable errors. 1 = Enables signaling of ERR_CORR to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting. DSTS--Device Status Register (PCI Express*--D0:F0) Address Offset: 4Ah-4Bh Default Value: 0000h Bit 15:6 25.1.31 Attribute: Size: R/WC, RO 16 bits Description Reserved 5 Transactions Pending (TDP) -- RO. Functions that do not issue Non-Posted requests on their own behalf should hardwire this bit to 0b... 4 AUX Power Detected (APD) -- RO. Auxiliary Power is not supported. 3 Unsupported Request Detected (URD) -- R/WC. Indicates an unsupported request was detected. 2 Fatal Error Detected (FED) -- R/WC. Indicates a fatal error was detected. 0 = Fatal has not occurred. 1 = This bit indicates that this function has detected a Fatal error. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. 1 Non-Fatal Error Detected (NFED) -- R/WC. Indicates a non-fatal error was detected. 0 = Non-fatal has not occurred. 1 = This bit indicates that this function has detected a Non-Fatal error. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. 0 Correctable Error Detected (CED) -- R/WC. Indicates a correctable error was detected. 0 = Correctable has not occurred. 1 = This bit indicates that this function has detected a Correctable error. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. LCAP--Link Capabilities Register (PCI Express*--D0:F0) Address Offset: 4Ch-4Fh Default Value: See description Bit 31:24 Attribute: Size: R/WO, RO 32 bits Description Port Number (PN) -- RO. This field indicates the PCI Express* port number assigned to this link. 23 Reserved 22 SPM Optionality Compliance (ASPMOPCMP): The ASPM Optionality Compliance bit was created as a tool to set clear expectations for hardware and software interaction. This bit is Set to indicate hardware that conforms to the current specification. 21 Link Bandwidth Notification Capability (LBNC): R0: Hardwired to 0 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 867 PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) Bit 20 Data Link Layer Active Error Reporting Capable (DLLERC): RO. Not supported, hardwired to 0 19 Surprise Link Down Error Reporting Capable (SLDERC): RO. Hardwired to 0 18 Clock Power Management Capable (CPMC): RO. Hardwired to 0 17:15 L1 Exit Latency (EL1) -- R/WL. Set to 010b to indicate an exit latency of 2 s to 4 s. 14:12 L0s Exit Latency (EL0) -- R/WL. Set to 100 to indicate an exit latency of 512 ns to less than 1 s 11:10 Active State Link PM Support (APMS) -- R/WL. Indicates what level of active state link power management is supported on the root port. Default is both L1 and L0s supported 9:4 Maximum Link Width (MLW) -- RO default is 04, indicating the maximum width is a x4. 3:1 Reserved 0 25.1.32 Description Maximum Link Speed (MLS) -- RO. 1b: 2.5 Gb/s link speed is supported LCTL--Link Control Register (PCI Express*--D:F0) Address Offset: 50h-51h Default Value: 0000h Bit 15:12 Attribute: Size: R/W, RO 16 bits Description Reserved 11 Link Autonomous Bandwidth Interrupt Enable (LABIE): RO. Hardwired to 0 as not applicable 10 Link Bandwidth Management Interrupt Enable (LBMIE): RO. Hardwired to 0 as not applicable 9 Hardware Autonomous Width Disable - RO. Components that do not implement the ability such as (Upstream Ports, Virtual Switch Ports) to autonomously change link width are permitted to hardwire this bit to 0b 8 Reserved 7 Extended Synch (ES) -- R/W. 0 = Extended synch disabled. 1 = Forces extended transmission of FTS ordered sets in FTS and extra TS2 at exit from L1 prior to entering L0. 6 Common Clock Configuration (CCC) -- R/W. 0 = The PCH and device are not using a common reference clock. 1 = The PCH and device are operating with a distributed common reference clock. After changing the value in this bit in bother components on a link, software must trigger the link to retrain by writing a 1b to the Retrain Link bit of the Downstream Port. 5 Retrain Link (RL) -- RO. Hardwired to 0. For the upstream port or virtual switch port, it is Read-only Link Disable (LD) -- RO. 4 868 hardwired to 0. This bit is reserved on Endpoints, PCI Express* to PCI/PCI-X bridges, and Upstream Ports of Switches Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) Bit 3 Read Completion Boundary Control (RCBC) -- RO. Indicates the read completion boundary is 64 bytes. 2 Reserved 1:0 25.1.33 Description Active State Link PM Control (APMC) -- R/W. Indicates whether the upstream port should enter L0s or L1 or both. Bits Definition 00 Disabled 01 L0s Entry Enabled 10 L1 Entry Enabled 11 L0s and L1 Entry Enabled LSTS--Link Status Register (PCI Express*--D0:F0) Address Offset: 52h-53h Default Value: See bit description Bit Attribute: Size: RO 16 bits Description 15 Link Autonomous Bandwidth Status (LABS) -- RO Not applicable, hardwired to 0 14 Link Bandwidth Management Status (LBMS) -- RO Hardwired to 0. This bit is not applicable and is reserved for endpoints, PCI Express-to-PCI/PCI-X bridges, and upstream ports of switches. 13 Data Link Layer Active (DLLA) -- RO. Default value is 0b. 0 = Data Link Control and Management State Machine is not in the DL_Active state 1 = Data Link Control and Management State Machine is in the DL_Active state 12 Slot Clock Configuration (SCC) -- RO. Set to 1b to indicate that the PCH uses the same reference clock as on the platform and does not generate its own clock. 11 Link Training (LT) -- RO. This field is not applicable and reserved for the upstream port, end point and must be hardwired to 0b. 10 Undefined: hard wired to zero. 9:4 Negotiated Link Width (NLW) -- RO. This field indicates the negotiated width of the given PCI Express* link. The contents of this NLW field is undefined if the link has not successfully trained. 00 0001b = x1 00 0010b = X2 00 0100b = x4 Only valid width is 00_0100b 3:0 Link Speed (LS) -- RO. This field indicates the negotiated Link speed of the given PCI Express* link. Default value is 1h 0001b = 2.5 Gb/s PCI Express Link Others: Reserved Note: The encoding is the binary value of the bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the current Link speed. Note: The value in this field is undefined when the link is not up. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 869 PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.34 DCAP2--Device Capabilities 2 Register (PCI Express*--D0:F0) Address Offset: 64h-67h Default Value: 00000000h Bit 31:5 870 Attribute: Size: RO 32 bits Description Reserved 19:18 OBFF Supported (OBFFS) 00b = OBFF Not Supported Applicable only to Root Ports, Switch Ports, and Endpoints that support this capability. Must be 00b for other function types. 17:14 Reserved 13:12 TPH Completer Supported (TPHCS) Applicable only to Root Ports and Endpoints. Must be 00b for other function types 11 LTBWR Mechanism Supported (LTBWRMS) his bit must be hardwired to 0b for function that do not implement this capability. 10 No RO-enabled PR-PR Passing (NROEPRPASS) Hardwiired to 0b. This bit applies only for Switches and RCs that support peer-to-peer traffic between ports 9 AD128 CAS Completer Supported (AD128ACS) hardwired to 0b 8 AD64-bit AtomicOp Completer Supported (AD64ACS) Hardwired to 0b 7 AD32 bit AtomicOp Completer Supported (AD32ACS) Hardwired to 0b 6 AtomicOp Routing Supported (ARS) -- R/WO Default is 0b 5 Alternative RID Interpretation Capable (ARI) Does not apply to endpoints and upstream ports and is hardwired to 0. 4 Completion Timeout Disable Supported (CTDS) -- RO. Hardwired to 0. 3:0 Completion Timeout Ranges Supported (CTRS) - RO. Hardwired to 0000b Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.35 DCTL2--Device Control 2 Register (PCI Express*--D0:F0) Address Offset: 68h-69h Default Value: 0000h Bit 15 Reserved OBFF Enable (OBFFE) -- RO Hardwired to 00b 12;11 Reserved LTBWR Mechanism Enable (LTBWRME) -- RO Not supported so hardwired to 0b 9 IDO Completion Enable (IDOCE) -- RO Hardwired to 0b. Applicable only to Endpoints including RC integrated Endpoints and Root Ports. 8 IDO Request Enable (IDORE) -- RO Hardwired to 0b. Applicable only to Endpoints including RC integrated Endpoints and Root Ports. 7 AtomicOp Egress Blocking (AEB) -- R/W 0 = AtomicOp requests that target this out going Egress port are permitted 1 = AtomicOp requests that target this out going Egress port must be blocked. 6 AtomicOp Requester Enable (ARE) Applicable only to Endpoints and Root Ports; must be hardwired to 0b for other Function types. 5 Alternative RID Interpretation Enable (ARIE) Hardwired to 0 for functions such as endpoints and upstream ports 4 Completion Timeout Disable (CTD) -- RO. Hardwired to 0b 1 = Disable the completions timeout mechanism for all NP transactions. 0 = Completion timeout is enabled for all NP transactions. 3:0 25.1.36 RO, R/W 16 bits Description 14:13 10 Attribute: Size: Completion Timeout Value (CTV) -- R0 Hardwired to 0000b. DEVSTS2--Device Status 2 Register (PCI Express*--D0:F0) Address Offset: 6Ah-6Bh Default Value: 0000h Bit 15:0 Attribute: Size: RO 16 bits Description Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 871 PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.37 L2--Link Control 2 Register (PCI Express*--D0:F0) Address Offset: 70h-71h Default Value: 0003h Bit 15:13 RO, R/WS 16 bits Description Reserved. Hardwired to 00b 12 Compliance De-emphasis (CD) -- R/WS. Default is 0b This bit sets the de-emphasis level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit (EC) (bit 4) in this register being 1b. 1b = -3.5 dB 0b = -6 dB When the link is operating at 2.5 Gb/s, the setting of this bit has no effect. Only cleared to default with a power good reset. 11 Compliance SOS (CSOS) -- R/WS. Default is 0b When set to 1b, the LTSSM is required to send Skip Ordered Sets periodically in between the (modified) compliance patterns. Only cleared to default with a power good reset. 10 Enter Modified Compliance (EMC) -- R/WS. Default is 0b When set to 1b, the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate. This register is intended for debug, compliance testing purposes only. System firmware and software is allowed to modify this register only during debug or compliance testing. In all other cases, the system must ensure that this register is set to the default value. Only cleared with a power good reset. 9:7 Transmit Margin (TM). Reserved = 000b This field controls the value of the non-de-emphasized voltage level at the transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate. 6 Selectable De-emphasis (SD) -- RO. Hardwired to 0b This bit is not applicable and reserved for Endpoints, PCI Express* to PCI/PCI-X bridges, and upstream ports of switches. 5 Hardware Autonomous Speed Disable (HASD) --R/WS. Default is 0b 0 = HW can change the link speed. 1 = Disabled HW from changing the link speed for a device specific reason other than attempting to correct unreliable link operation by reducing speed. Until transition to the highest supported common link speed is not blocked by this bit. 4 Enter Compliance (EC) -- R/WS Software is permitted to force a link to enter compliance mode at the speed indicated in the Target Link Speed field by setting this bit to 1b in both components on a link and then initiating a hot reset on the link. 3:0 872 Attribute: Size: Target Link Speed (TLS) -- R/WS. 0001b = 2.5 Gb/s Target Link Speed Others = Reserved For both Upstream and Downstream Ports, this field is used to set the target compliance mode speed when software is using the Enter Compliance bit to force a Link into compliance mode. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.38 LINKSTS2--Link STatus2 Register (PCI Express*--D0:F0) Address Offset: 72h-73h Default Value: 0000h Bit 15:1 0 25.1.39 RO 16 bits Description Reserved Current De-emphasis Level (CDL): When the link is operating at 5 Gb/s speed, this bit reflects the level of de-emphasis. 1b = -3.5 dB 0b = -6 dB PMCAP--Power Management Capability Register (PCI Express*--D0:F0) Address Offset: 80h-81h Default Value: 8801h Bit 15:8 7:0 25.1.40 Attribute: Size: Attribute: Size: RO 16 bits Description Next Capability (NEXT) -- RO. Contains the offset of the next item in the capabilities list. Capability Identifier (CID) -- RO. Value of 01h indicates this is a PCI power management capability. PMC--PCI Power Management Capabilities Register (PCI Express*--D0:F0) Address Offset: 82h-83h Default Value: C803h Bit 15:11 10 Attribute: Size: Description PME_Support (PMES) -- RO. Indicates PME# is supported for states D0, D3HOT and D3COLD... D2_Support (D2S) -- RO. The D2 state is not supported. 9 D1_Support (D1S) -- RO The D1 state is not supported. 8:6 Aux_Current (AC) -- RO. Aux current is not supported 5 Device Specific Initialization (DSI) -- RO. Device-specific initialization is not required when transitioning to D0 from D3hot state. This bit is zero. 4 Reserved 3 PME Clock (PMEC) -- RO. Does not apply to PCI Express. Hard-wired to 0. 2:0 RO 16 bits Version (VS) -- RO. Indicates support for Revision 1.2 of the PCI Power Management Specification. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 873 PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.41 PMCSR--PCI Power Management Control and Status Register (PCI Express*--D0:F0) Address Offset: 84h-85h Default Value: 0008h Bit 15 12:9 Data Select (DS): Not supported, hardwired to 0 PME Enable (PMEE) -- R/WS. 0 = PME messages are gated and PME messages are not generated 1 = PME messages are enabled Reserved 3 No Soft Reset (NSR): R/WL This bit when 1b indicates that a device transitioning from D3hot to D0 does not perform an internal reset. The configuration context is preserved. 2 Reserved 1:0 25.1.42 PME Status (PMES) -- R/W1C 0 = Indicates no PME received from downstream link 1 = Indicates a PME was received on the downstream link. Data Scale (DC):RO Not supported. Hardwired to 0 7:4 Power State (PS) -- R/W. This field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the supported values is given below: 0h = D0 3h = D3hot If software attempts to write an unsupported, optional state to this field, the write operation must complete normally; however, the data is discarded and no state change occurs. PMBSE--Power Management Bridge Support Extensions Register (PCI Express*--D0:F0) Address Offset: 86h Default Value: 00h Bit Attribute: Size: RO 8 bits Description 7 Bus Power/Clock Control Enable (BPCC_EN) Neither bus or clock control of PCI is supported when in D3hot state. This bit is hard-wired to 0. 6 B2/B3# (B23EN) Not supported. This bit has no meaning since the BPCC_En bit is hard-wired to 0. 5:0 874 R/W, RO 16 bits Description 14:13 8 Attribute: Size: Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.43 SVCAP--Subsystem Capability List Register (PCI Express*--D0:F0) Address Offset: 88h-89h Default Value: 000Dh Bit 15:8 7:0 25.1.44 Attribute: Size: Description Next Capability (NEXT) -- RO. For upstream ports, there is no MSI structure and hence the capability is terminated. Capability Identifier (CID) -- RO. Identifies the function as Subsystem Identification capable SVID--Subsystem Vendor ID Register (PCI Express*--D0:F0) Address Offset: 8Ch-8Dh Default Value: 8086h Bit 15:0 25.1.45 Attribute: Size: R/WO 16 bits Description Subsystem Vendor Identifier (SVID) -- R/WO. Indicates the manufacturer of the subsystem. This field is write once and is locked down until a bridge reset occurs (not the PCI bus reset). SVID--Subsystem ID Register (PCI Express*--D0:F0) Address Offset: 8Eh-8Fh Default Value: 0000h Bit 15:0 25.1.46 RO 16 bits Attribute: Size: R/WO 16 bits Description Subsystem Identifier (SID) -- R/WO. Indicates the subsystem as identified by the vendor. This field is write once and is locked down until a bridge reset occurs (not the PCI bus reset). AERCAPHDR--Advanced Error Reporting Capabilities Header Register (PCI Express*--D0:F0) Address Offset: 100-103h Default Value: 15010001h Bit Attribute: Size: RO/R/WO 16 bits Description 31:20 Next Capability Offset (NCO) -- R/WL Contains the offset of the next structure in the Extended Capabilities list for endpoint. 19i:16 Capability Version (CV) -- RO Indicates the version of the Capability structure present. 15:0 Extended Capability ID (EXCAPID) -- RO Identifies the function as Advanced Error Reporting capable. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 875 PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.47 UES--Uncorrectable Error Status Register (PCI Express*--D0:F0) Address Offset: 104h-107h Default Value: 00000000h Attribute: Size: R/WC, RO 32 bits This register maintains its state through a platform reset. It loses its state upon suspend. Bit 31:25 Reserved, hardwired to 0 24 Atomic Egress Blocked Error (AEBE) -- R/WC This bit is set whenever an Atomic OP TLP is blocked on any egress port. 23 MC Blocked TLP Error (MCE) -- R/WC This bit is set whenever a Multicast TLP is blocked. 22 Uncorrectable Internal Error (UIE) -- R/WC This bit is set whenever an uncorrectable internal error is detected. 21 ACS Violation Error (ACSE) -- RO This bit is set whenever an ACS violation is detected by the PCI Express* port. 20 Unsupported Request Error Status (URE) -- R/WC. Indicates an unsupported request was received. 19 ECRC Error Status (EE) -- RO. ECRC is not supported. 18 Malformed TLP Status (MT) -- R/WC. Indicates a malformed TLP was received. 17 Receiver Overflow Status (RO) -- R/WC. Indicates a receiver overflow occurred. 16 Unexpected Completion Status (UC) -- R/WC. This bit is set whenever a completion is received with a requestor ID that does not match side A or side B, or when a completion is received with a matching requestor ID but an unexpected tag field. Header logging is performed. 15 Completion Abort Status (CA) -- R/WC. The bridge sets this bit and logs the header associated with the request when the configuration unit signals a completer abort. 14 Completion Timeout Status (CT) -- R/WC. For Switch Ports, this bit is set if the Switch Port issues Non-Posted Requests on its own behalf (vs. only forwarding such as Requests generated by other devices). 13 Flow Control Error (FCE) -- R/WC This bit is set when a flow control protocol error is detected. 12 Poisoned TLP Error (PTLPE) -- R/WC This bit is set and the bridge logs the header when a poisoned TLP is received from PCI Express. 11:6 Reserved 5 Surprise Link Down Error (SLDE) -- RO. This bit is set when a surprise link down error is detected. This bit does not apply to upstream ports so it is hardwired to 0 4 Data Link Protocol Error Status (DLPE) -- R/WC. Indicates a data link protocol error occurred. 3:1 0 876 Description Reserved Training Error Status (TE) -- RO. Training Errors not supported. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.48 UEM--Uncorrectable Error Mask (PCI Express*--D0:F0) Address Offset: 108h-10Bh Default Value: 00000000h Attribute: Size: R/WO, RO 32 bits When set, the corresponding error in the UES register is masked, and the logged error will cause no action. When cleared, the corresponding error is enabled. Bit 31:25 Reserved 24 AtomicOp Egress Blocked Error Mask (AEBEM) -- R/WO 23 MC Blocked TLP Error Mask (MCEM) -- R/WO 22 Uncorrectable Internal Error Mask (UIEM) -- R/WO 21 ACS Violation Error Mask (ACSEM) -- RO. Hardwired to 0 20 Unsupported Request Error Mask (URE) -- R/WO. 19 ECRC Error Mask (EE) -- RO. ECRC is not supported. 18 Malformed TLP Mask (MT) -- R/WO. 17 Receiver Overflow Mask (RO) -- R/WO. 16 Unexpected Completion Mask (UC) -- R/WO. 15 Completion Abort Mask (CA) -- R/WO. 14 Completion Timeout Mask (CT) -- RO Hardwired to 0 13 Flow Control Protocol Error Mask (FCPE) -- R/WO 12 Poisoned TLP Mask (PT) -- R/WO 11:6 Reserved 5 Surprise Link Down Error Mask (SLDEM) -- RO Hardwired to 0 4 Data Link Protocol Error Mask (DLPE) -- R/WO. 3:1 0 25.1.49 Description Reserved Training Error Mask (TE) -- RO. Training Errors not supported UEV -- Uncorrectable Error Severity (PCI Express*--D0:F0) Address Offset: 10Ch-10Fh Default Value: 00462010h Bit 31:25 Attribute: Size: RO, R/W 32 bits Description Reserved 24 AtomicOp Egress Blocked Severity (AEBES) 0 = Error considered non-fatal. (Default) 1 = Error is fatal. 23 MC Blocked TLP Error Severity (MCES) 0 = Error considered non-fatal. (Default) 1 = Error is fatal. 22 Uncorrectable Internal Error Severity (UIES) 0 = Error considered non-fatal. 1 = Error is fatal.(default) 21 ACS Violation Error Severity (ACSES) -- RO. Hardwired to 0 20 Unsupported Request Error Severity (URE) -- R/W. 0 = Error considered non-fatal. (Default) 1 = Error is fatal. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 877 PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) Bit 19 ECRC Error Severity (EE) -- RO. ECRC is not supported. 18 Malformed TLP Severity (MT) -- R/W. 0 = Error considered non-fatal. 1 = Error is fatal. (Default) 17 Receiver Overflow Severity (RO) -- R/W. 0 = Error considered non-fatal. 1 = Error is fatal. (Default) 16 Unexpected Completion Error Severity (UCES) 0 = Error considered non-fatal. (Default) 1 = Error is fatal. 15 Completion Abort Severity (CA) -- R/W. 0 = Error considered non-fatal. (Default) 1 = Error is fatal. 14 Completion Timeout Error Severity (CTES) -- RO. Hardwired to 0 13 Flow Control Protocol Error Severity (FCPE) 0 = Error considered non-fatal. 1 = Error is fatal (Default). 12 Poisoned TLP Severity (PT) -- R/W. 0 = Error considered non-fatal. (Default) 1 = Error is fatal. 11:6 Reserved 5 Surprise Link Down Severity (SLDES) -- RO. Hardwired to 0. 4 Data Link Protocol Error Severity (DLPE) -- R/W. 0 = Error considered non-fatal. 1 = Error is fatal. (Default) 3:0 25.1.50 Description Reserved CES--Correctable Error Status Register (PCI Express*--D0:F0) Address Offset: 110h-113h Default Value: 00000000h Bit 31:16 R/WC 32 bits Description Reserved 15 Header Log Overflow Error (HLOE) -- R/WC Indicates a Header Log Overflow occurred 14 Correctable Internal Error (CIE) -- R/WC. Indicates a correctable Internal Error occurred 13 Advisory Non-Fatal Error Status (ANFES) -- R/WC. 0 = Advisory Non-Fatal Error did not occur. 1 = Advisory Non-Fatal Error did occur. 12 Replay Timer Timeout Status (RTT) -- R/WC. Indicates the replay timer timed out. 11:9 Reserved 8 Replay Number Rollover Status (RNR) -- R/WC. Indicates the replay number rolled over. 7 Bad DLLP Status (BD) -- R/WC. Indicates CRC Error on a DLLP was received. 6 Bad TLP Status (BT) -- R/WC. Indicates a CRC error on a TLP was received. 5:1 0 878 Attribute: Size: Reserved Receiver Error Status (RE) -- R/WC. Indicates a receiver error occurred. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.51 CEM--Correctable Error Mask Register (PCI Express*--D0:F0) Address Offset: 114h-117h Default Value: 0000E000h Attribute: Size: R/WO 32 bits When set, the corresponding error in the CES register is masked, and the logged error will cause no action. When cleared, the corresponding error is enabled. Bit 31:16 Reserved 15 Header Log Overflow Error Mask (HLOEM) R/WO Mask for Header Log Overflow 14 Correctable Internal Error Mask (CIEM) R/WO. Mask for Correctable Internal Error 13 Advisory Non-Fatal Error Mask (ANFEM) -- R/WO. 0 = Does not mask Advisory Non-Fatal errors. 1 = Masks Advisory Non-Fatal errors from (a) signaling ERR_COR to the device control register and (b) updating the Uncorrectable Error Status register. This register is set by default to enable compatibility with software that does not comprehend RoleBased Error Reporting. Note: The correctable error detected bit in device status register is set whenever the Advisory Non-Fatal error is detected, independent of this mask bit. 12 Replay Timer Timeout Mask (RTT) -- R/WO. Mask for replay timer timeout. 11:9 Reserved 8 Replay Number Rollover Mask (RNR) -- R/WO. Mask for replay number rollover. 7 Bad DLLP Mask (BD) -- R/WO. Mask for bad DLLP reception. 6 Bad TLP Mask (BT) -- R/WO. Mask for bad TLP reception. 5:1 0 25.1.52 Description Reserved Receiver Error Mask (RE) -- R/WO. Mask for receiver errors. AECC -- Advanced Error Capabilities and Control Register (PCI Express*--D0:F0) Address Offset: 118h-11Bh Default Value: 00000000h Bit 31:11 Attribute: Size: RO 32 bits Description Reserved Multiple Header Recording Enable (MHRE) -- RO. Not supported, hardwired to 0b. Multiple Header Recording Capable (MHRC) -- RO. Not supported, hardwired to 0b. 8 ECRC Check Enable (ECE) -- RO. ECRC is not supported. Hardwired to 0b. 7 ECRC Check Capable (ECC) -- RO. ECRC is not supported.Hardwired to 0b. 6 ECRC Generation Enable (EGE) -- RO. ECRC is not supported. Hardwired to 0b. 5 ECRC Generation Capable (EGC) -- RO. ECRC is not supported. Hardwired to 0b. 4:0 First Error Pointer (FEP) -- RO. This field identifies the bit position of the first error reported in the Uncorrectable Error Status Register (xref). This register re-arms itself (which does not change its current value) as soon as the error status bit indicated by the pointer is cleared by the software by writing a 1 to that status bit. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 879 PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.53 AEHRDLOG [1-4]-- Advanced Error Header Log (PCI Express*--D0:F0) Address Offset: 11Ch-128hFh Default Value: 0000h Bit 31:0 25.1.54 RRO 32 bits Description TLP Header Log (TLPHDRLOG) As soon as an error is logged in this register, it remains locked for further error-logging until the software clears the status bit that caused the header log (in other words, until the error pointer is re-armed for logging again). ERRUNCDETMSK-- Uncorrectable Error Detect Mask Register (PCI Express*--D0:F0) Address Offset: 140h-143h Default Value: 00000000h Bit 31:25 880 Attribute: Size: Attribute: Size: R/WC, RO 32 bits Description Reserved 24 AtomicOp Egress Blocked Error Detect Mask (AEBEDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled 23 MC Blocked TLP Error Detect Mask (MCEDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled 22 Uncorrectable Internal Error Detect Mask (UIEDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled 21 ACS Violation Error Detect Mask (ACSEDM) RO - hardwired to 0 20 Unsupported Request Error Detect Mask (UREDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled 19 ECRC Check Error Mask (ECRCEDM). Not supported RO - hardwired to 0 18 Malformed TLP Error Detect Mask (MTLPEDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled 17 Receiver Overflow Error Detect Mask (ROEDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled 16 Unexpected Completion Error Detect Mask (UCEDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled 15 Completer Abort Error Detect Mask (CAEDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled 14 Completion Timeout Error Detect Mask (CTEDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled 13 Flow Control Error Detect Mask (FCEDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) Bit 12 11:6 Poisoned TLP Error Detect Mask (PTLPEDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled Reserved 5 Surprise Link Down Error Detect Mask (SLDEDM) -- RO. Hardwired to 0 4 Data Link Protocol Error Detect Mask (DLPEDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled 3:0 25.1.55 Description Reserved ERRCORDETMSK-- Correctable Error Detect Mask Register (PCI Express*--D0:F0) Address Offset: 144h-147h Default Value: 0000E000h Attribute: Size: R/WO 32 bits When set, the corresponding error in the CES register is masked, and the logged error will cause no action. When cleared, the corresponding error is enabled. Bit 31:16 Description Reserved 15 Header Log Overflow Error Mask (HLOEM) R/WO Mask for Header Log Overflow 14 Correctable Internal Error Mask (CIEM) R/WO. Mask for Correctable Internal Error 13 Advisory Non-Fatal Error Mask (ANFEM) -- R/WO. 0 = Does not mask Advisory Non-Fatal errors. 1 = Masks Advisory Non-Fatal errors from (a) signaling ERR_COR to the device control register and (b) updating the Uncorrectable Error Status register. This register is set by default to enable compatibility with software that does not comprehend RoleBased Error Reporting. Note: The correctable error detected bit in device status register is set whenever the Advisory Non-Fatal error is detected, independent of this mask bit. 12 Replay Timer Timeout Mask (RTT) -- R/WO. Mask for replay timer timeout. 11:9 Reserved 8 Replay Number Rollover Mask (RNR) -- R/WO. Mask for replay number rollover. 7 Bad DLLP Mask (BD) -- R/WO. Mask for bad DLLP reception. 6 Bad TLP Mask (BT) -- R/WO. Mask for bad TLP reception. 5:1 0 Reserved Receiver Error Mask (RE) -- R/WO. Mask for receiver errors. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 881 PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.56 MCSTCAPHDR--Multicast Extended Capability Header (PCI Express*--D0:F0) Address Offset: 150-153h Default Value: 00010012h Bit Description Next Capability Offset (NCO) -- R/WL Contains the offset of the next structure in the Extended Capabilities list for endpoint. 19i:16 Capability Version (CV) -- RO Indicates the version of the Capability structure present. Extended Capability ID (EXCAPID) -- RO Identifies the function as Advanced Error Reporting capable. MCSTCAP--Multicast Capability Register (PCI Express*--D0:F0) Address Offset: 154-155h Default Value: 8000h Bit 25.1.58 Attribute: Size: RO 16 bits Description 15 MC Overlay Supported (MCOS) If set to 1b, this bit indicates that the MC Overlay mechanism is supported. 14 MC ECRC Regeneration supported (MCERS) Set to 0b, ECRC regeneration is not supported. 13:6 Reserved 5:0 MC Max Group (MCMG) This field indicates the maximum number of Multicast Groups that the component supports, encoded as M-1. A value of 00h indicates that one multicast Group is supported. MCSTCTL--Multicast Control Register (PCI Express*--D0:F0) Address Offset: 156-157h Default Value: 0000h Bit 15 882 RO, R/WO 32 bits 31:20 15:0 25.1.57 Attribute: Size: Attribute: Size: RO, R/W 16 bits Description MC Enable (MCEN) -- R/W 0 = Indicates the Multicast Capability is NOT enabled for the component 1 = Indicates the Multicast Capability is enabled for the component. 14:6 Reserved. RO 5:0 MC Max Group (MCMG) -- R/W This field indicates the number of Multicast Groups configured for use, encoded as N-1. A value of 00h indicates that one Multicast Group is configured for use. Behavior is undefined if value exceeds MC Max Group. This parameter indirectly defines the upper limit of the Multicast address range. This field is ignored if MC Enable is Clear. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.59 MCSTBAR--Multicast Base Address Register (PCI Express*--D0:F0) Address Offset: 158-15Bh Default Value: 0000000Ch Bit 25.1.60 31:12 Address 32-bit (ADR32BIT) -- R/W Bits 31:12 of the lower 64 bit address. 14:6 Reserved- RV 5:0 MC Index Position (MCIP) This field indicates the location of the LSB of the Multicast Group number within the address. Behavior is undefined if this field is less than 12 when MC Enable is set. MCSTUBAR--Multicast Upper Base Address Register (PCI Express*--D0:F0) Bit 31:12 Attribute: Size: R/W 32 bits Description Upper Address 32-bit (U32ADR) Bits 63:32 of the lower 64 bit address. MCSTRCV--Multicast Receive Register (PCI Express*--D0:F0) Address Offset: 160-163h Default Value: 00000000h Bit 25.1.62 R/W 32 bits Description Address Offset: 15C-15Fh Default Value: 00000000h 25.1.61 Attribute: Size: Attribute: Size: RO, R/W 32 bits Description 31:1 Reserved. RO 0 MC Receive (MCR) -- R/W For each bit that is set, this function gets a copy of any Multicast TLPs for the associated Multicast Group. Bits above MC Number Groups are ignored by hardware. MCSTRCV2--Multicast Receive 2 Register (PCI Express*--D0:F0) Address Offset: 164-167h Default Value: 00000000h Bit 31:0 Attribute: Size: RO 32 bits Description Reserved. RO Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 883 PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.63 MCSTBLKALL--Multicast Block All Register (PCI Express*--D0:F0) Address Offset: 168-16Bh Default Value: 00000000h Bit 25.1.64 31:1 Reserved. RO 0 MC Block All (MCBA) -- R/W For each bit that is set, this function is blocked from sending TLPs to the associated Multicast Group. Bits above MC Number Groups are ignored by hardware. MCSTBLKALL2--Multicast Block All 2 Register (PCI Express*--D0:F0) Bit 31:0 RO 32 bits Reserved. RO MCSTBLKUT--Multicast Block Untranslated Register (PCI Express*--D0:F0) Bit Attribute: Size: RO 32 bits Description 31:1 Reserved. RO 0 MC Block Untranslated (MCBUT) -- R/W For each bit that is Set, this device/function is blocked from sending TLPs containing Untranslated Addresses to the associated MCG. Bits above MC_Num_Group (See MCCAP.MCMG) are ignored by hardware. MCSTBLKUT2--Multicast Block Untranslated 2 Register (PCI Express*--D0:F0) Address Offset: 174-177h Default Value: 0000000h Bit 31:0 884 Attribute: Size: Description Address Offset: 170-173h Default Value: 00000000h 25.1.66 RO, R/W 32 bits Description Address Offset: 16C-16Fh Default Value: 00000000h 25.1.65 Attribute: Size: Attribute: Size: RO 32 bits Description Reserved. RO Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 25.1.67 MCSTOLBAR--Multicast Overlay Base Address Register (PCI Express*--D0:F0) Address Offset: 178-17B Default Value: 00000000h Bit 25.1.68 Attribute: Size: R/W 32 bits Description 31:6 MC Overlay BAR (MCOVRBAR) Specifies the base address of the window onto which MC TLPs passing through this function will be overlaid. 5:0 MC Overlay Size (MCOVRSZ) If 6 or greater, specifies the size in bytes of the overlay aperture as a power of 2. If less than 6, disables the overlay mechanism. MCSTUOLBAR--Multicast Upper Overlay Base Address Register (PCI Express*--D0:F0) Address Offset: 17C-17Fh Default Value: 00000000h Bit 31:0 Attribute: Size: R/W 32 bits Description MC Overlay BAR Upper 32 (MCOVRBARU32) Specifies the base address of the window onto which MC TLPs passing through this function will be overlaid. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 885 PCI Express* UpStream Configuration Registers (PCH) (SRV/WS SKUs only) 886 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) 26 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) 26.1 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (PCI Express*--B0:D17:F0/Bn+1:D8:F0) The Virtual root port and virtual switch port are the same port, but configured somewhat differently based upon how PCH is configured. If the PCH has an upstream PCIe port, then this port becomes a virtual switch port that connects the SCUs and MFDs downstream to the Upstream port. If there is no upstream port, then this port becomes a virtual root port and connects those devices downstream with the backbone of the PCH that routes the data upstream using the DMI2 bus. 26.2 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (PCI Express*--B0:D17:F0/Bn+1:D8:F0) Note: Register address locations that are not shown in Table 20-1 and should be treated as Reserved. Function 0-5 Default Attribute Vendor Identification 8086h RO Device Identification See register description RO 0000h R/W, RO 0010h R/WC, RO See register description RO Offset Mnemonic 00h-01h VID 02h-03h DID 04h-05h PCICMD PCI Command 06h-07h PCISTS PCI Status 08h RID 09-0Bh PI 0Ch CLS 0Dh PLT 0Eh HEADTYP Register Name Revision Identification Programming Interface Register Cache Line Size see description RO 00h R/W Primary Latency Timer 00h RO Header Type 81h RO 18h PRINUM Primary Bus Number 00h R/W 19h SECBUS Secondary Bus Number 00h R/W 1Ah SUBBUS Subordinate Bus Number 00h R/w 1Chh IOBL I/O Base 00h R/W, RO 1D IOBL I/O Limit Register 00h R/W, RO 1Eh-1Fh SSTS Secondary Status Register 0000h R/WC 20h-21h MBL Memory Base 0000h R/W 22-23h MBL Memory Limit 0000h R/W Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 887 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) Offset 888 Mnemonic Register Name Function 0-5 Default Attribute 24h-25h PMBL Prefetchable Memory Base 0001h R/W, RO 26-27h PMBL Prefetchable Limit 0001h R/W, RO 28h-2Bh PMBU32 Prefetchable Memory Base Upper 32 Bits 00000000h R/W 2Ch-2Fh PMLU32 Prefetchable Memory Limit Upper 32 Bits 00000000h R/W 34h CAPP Capabilities List Pointer 3Ch-3Dh INTR Interrupt Information 3Eh-3Fh BCTRL Bridge Control Register 40h-41h CLIST Capabilities List 42h-43h XCAP PCI Express* Capabilities 44h-47h DCAP Device Capabilities 40h RO See bit description R/W, RO 0000h R/W 8010 RO See Description R/WO, RO 00008001h RO 48h-49h DCTL Device Control 2000h R/W, RO 4Ah-4Bh DSTS Device Status 0000h R/WC, RO 4Ch-4Fh LCAP Link Capabilities See bit description R/W, RO, R/ WO 50h-51h LCTL Link Control 0000h R/W, WO, RO 52h-53h LSTS Link Status See bit description RO 5C-5Dh ROOTCTL Root control 00000000 RO, R/W 5E-FFh ROOTCAP Root Capabilities 60-63h ROOTSTS Root Status 64h-67h DCAP2 Device Capabilities 2 Register 68h-69h DCTL2 Device Control 2 Register Device Status 2 Register 6A-6Bh DEVSTS2 70h-71h LCTL2 72-73h LINKSTS2 80h-81h PMCAP Link Control 2 Register 0000 RO 00000000 RO, R/WC 00000016h RO 0000h R/W, RO 0000 RO 0003h RO Link Status 2 0000 RO Power Management Capability 0001 RO 82h-83h PMC PCI Power Management Capabilities C803 R/W, RO 84h-85h PMCSR PCI Power Management Control and Status 0004 R/W, RO 86h PMBSE Power Management Bridge Support Extensions 00 RO 88-89h SVCAP Susbsytem Capability List 000D RO 8C-8Dh SVID Subsystem Vendor Identification 8086 R/WO 8E-8F SVID Subsytem ID Register 0000 R/WO 90-91h MSICAPLST 92-93h MSICTL 94-97h MSIADDR MSI Message Address Register 98-99h MSIDATA MIS Message Data Register 100-103h AERCAPHDR MSI Capability List MSI Message Control Advanced Error Reporting Capabilities 104h-107h UES Uncorrectable Error Status 108h-10Bh UEM Uncorrectable Error Mask 10Ch-10Fh UEV Uncorrectable Error Severity 110h-113h CES Correctable Error Status 0005 RO 0000h RO, R/W 00000000 RO, R/W 0000 R/W see description RO, R/WO See bit description R/WC, RO 00000000h R/WO, RO See Description RO 00000000h R/WC Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) Offset 26.2.1 Mnemonic Register Name Attribute 114h-117h CEM Correctable Error Mask 00000000h RO, R/WO 118h-11Bh AECC Advanced Error Capabilities and Control 00000000h RO 11C-11Fh AEHRDLOG1 Advanced Header Log 0000h RO 120-123h AEHRDLOG2 Advanced Header Log 0000h RO 124-127h AEHRDLOG3 Advanced Header Log 0000h RO 128-12Bh AEHDRLOG4 Advanced Header Log 0000h RO 12C-12Fh ROOTERRCMD Root Error Command Register 130-133h ROOTERRSTS Root Error Status 00000000h RO, R/W 00000000 RO, R/WC 134-137h ERRSRCID 138-13Bh ACSCAPHDER Err Source Identification 00000000 RO Access Control Services Extended Capabilities 0001000D RO 13C-13Dh ACSCAP Access Control Services Capability 005F RO 13E-13Fh ACSCAP Access Control Services Capability 0000 RO, R/W 140h-143h ERRUNCDETMSK Uncorrectable Error Detect Mask 00000000h R/WO, RO 144h-147h ERRCORDETMSK Correctable Error Detect Mask 00000000 R/WO, RO 148-14Bh ROOTERRDETMSK Root Error Detect Mask 0000E000 RO, R/WO VID--Vendor Identification Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 00h-01h Default Value: 8086h Bit 15:0 26.2.2 Function 0-5 Default Attribute: Size: RO 16 bits Description Vendor ID -- RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h DID--Device Identification Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 02h-03h Default Value: Bit Description Bit 15:0 Attribute: Size: RO 16 bits Description Device ID -- RO. This is a 16-bit value assigned to the PCH's PCI Express* controller. Refer to the Intel(R) C600 Series Chipset Specification Update for the value of the Device ID Register Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 889 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) 26.2.3 PCICMD--PCI Command Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 04h-05h Default Value: 0000h Bit 15:11 10 890 Attribute: Size: R/W, RO 16 bits Description Reserved Interrupt Disable -- R/W. This bit controls the ability of the PCI-Express Function to generate legacy INTx interrupt message 0 = Internal INTx# messages are generated for PCI-Express errors detected internally in this port (for example, Malformed TLP, CRC error, completion time out etc.) or when receiving root port error messages or interrupts due to HP/PM events generated in legacy mode. 1 = Internal INTx# messages will not be generated. 1 = This bit does not affect interrupt forwarding from devices connected to the root port. Assert_INTx and Deassert_INTx messages will still be forwarded to the internal interrupt controllers if this bit is set. 9 Fast Back to Back Enable (FBE) -- Reserved per the PCI Express* Base Specification. 8 SERR# Enable (SEE) -- R/W. 0 = Disable. 1 = this bit enables reporting of Non-Fatal and Fatal errors detected by the Function of the Root Complex. For Type 1 Configuration Space headers, this bit controls transmission by the primary interface of ERR_NONFATAL and ERR_FATAL error messages forwarded from the secondary interface. ERR_COR messages are not affected by this bit... 7 Wait Cycle Control (WCC) -- Reserved per the PCI Express* Base Specification. 6 Parity Error Response (PER) -- R/W. 0 = Disable. 1 = This bit controls the setting of the master data parity error bit in the Status Register in response to a parity error received on the PCI Express interface. 5 VGA Palette Snoop (VPS) -- Reserved per the PCI Express* Base Specification. 4 Postable Memory Write Enable (PMWE) -- Reserved per the PCI Express* Base Specification. 3 Special Cycle Enable (SCE) -- Reserved per the PCI Express* Base Specification. 2 Bus Master Enable (BME) -- R/W. 0 = Disable. memory and I/O requests received at the root port or downstream side of a switch port (secondary side) must be handled as an Unsupported Request (UR). For Non-posted requests, a completion with UR completion status must be returned. 1 = Enable. Allows the root port or switch to forward memory and I/O read or write requests in the upstream direction. 1 Memory Space Enable (MSE) -- R/W. 0 = Disable. The function will handle memory transactions targeting the Function as an Unsupported Request (UR). 1 = Enable. Allows memory cycles within the range specified by the memory base and limit registers can be forwarded. 0 I/O Space Enable (IOSE) -- R/W. This bit controls access to the I/O space registers. 0 = Disable. The function will handle I/O transactions targeting the Function as an Unsupported Request (UR). 1 = Enable. Allows I/O cycles within the range specified by the I/O base and limit registers can be forwarded. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) 26.2.4 PCISTS--PCI Status Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 06h-07h Default Value: 0010h Attribute: Size: R/WC, RO 16 bits Bit Description 15 Detected Parity Error (DPE) -- R/WC. 0 = No parity error detected. 1 = This bit is set when a poisoned TLP is received from PCI Express. This bit is set even when the parity error response enable bit (bit[6] of the PCICMD Register) is not set. On Type 1 configuration header functions, the bit is set when the poisoned TLP is received on the primary sideSet when the... 14 Signaled System Error (SSE) -- R/WC. 0 = No system error signaled. 1 = This bit is set when ERR_FATAL or ERR_NONFATAL messages are sent to the root complex and the SERR enable bit in the PCICMD Register is set. 13 Received Master Abort (RMA) -- R/WC. 0 = Port has not received a completion with unsupported request status. 1 = This bit is set when the requester receives a completion with an UR completion status. On Type 1 configuration header functions, the bit is set when a UR completions status is received on the primary side. 12 Received Target Abort (RTA) -- R/WC. 0 = Port has not received a completion with completer abort. 1 = This bit is set when a requester receives a CA completions status. On Type 1 configuration header functions, the bit is set when a "Completer Abort" is received on the primary side. 11 Signaled Target Abort (STA) -- R/WC. 0 = No target abort received. Signaled Target Abort (STA): 1 = This bit is Set when the port completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function with a Type 1 Configuration header when the Completer Abort was generated by its Primary Side. 10:9 DEVSEL# Timing Status (DEV_STS) -- Reserved per the PCI Express* Base Specification. 8 Master Data Parity Error Detected (DPED) -- R/WC. 0 = No data parity error received. 1 = This bit is set by a requester (primary side for type1 configuration header functions) if the parity error response enable bit (PERE) in the Command Register is set and either of the following two conditions occur: *Requester receives a completion marked poisoned. *Requester sends a poisoned request (includes writes and messages) If the parity error bit is 0b, this bit is never set. 7 Fast Back to Back Capable (FB2BC) -- Reserved per the PCI Express* Base Specification. 6 Reserved 5 66 MHz Capable -- Reserved per the PCI Express* Base Specification. 4 Capabilities List -- RO. Hardwired to 1. Indicates the presence of a capabilities list. 3 Interrupt Status -- RO. 0 = Interrupt is deasserted. 1 = this bit indicates that an INTx emulation interrupt is pending internally in this functionFor Type 1 configuration header functions, forwarded INTx messages are not reflected in this bit. unless the INTx messages is being generated from the Type 1 configuration header functioned. 2:0 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 891 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) 26.2.5 RID--Revision Identification Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Offset Address: 08h Default Value: See bit description Attribute: Size: Bit 7:0 26.2.6 Description (R) Revision ID -- RO. Refer to the Intel the Revision ID Register C600 Series Chipset Specification Update for the value of PI--Programming Interface Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 09h Default Value: 00h Bit 23-16 15-8 7:0 26.2.7 RO 24 bits Base Class-- RO. 06h = This is a bridge device. SubClass Interface - RO 04h = this device is a PCI to PCI bridge Programming Interface -- RO. 00h = No specific register level programming interface defined. CLS--Cache Line Size Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Bit 7:0 Attribute: Size: R/W 8 bits Description Cache Line Size (CLS) -- R/W. This is read/write but contains no functionality, per the PCI Express* Base Specification. PLT--Primary Latency Timer Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 0Dh Default Value: 00h Bit 892 Attribute: Size: Description Address Offset: 0Ch Default Value: 00h 26.2.8 RO 8 bits Attribute: Size: RO 8 bits Description 7:3 Latency Count. Reserved per the PCI Express* Base Specification. 2:0 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) 26.2.9 HEADTYP--Header Type Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 0Eh Default Value: 01h Bit 7 6:0 26.2.10 Multi-Function Device -- RO. 0= Not a Multi-function device. Configuration Layout-- RO. These bits define the layout of addresses 10h through 3Fh in the configuration space. These bits read as 01h to indicate that the register layout conforms to the standard PCI-to-PCI Bridge layout. PRIBUS--Primiary Bus Number Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Attribute: Size: R/W 24 bits Bit Description 7:0 Primary Bus Number (PBN) -- R/W.Primary Bus Number (PBN): These bits indicate the PCI Express bus number. Any Type 1 configuration cycle with a bus number less than this number is not accepted by this bridge (in other words, it may still match the other bridge). Indicates the bus number of the backbone. SECBUS--Secondary Bus Number Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 19h Default Value: 00h 26.2.12 RO 8 bits Description Address Offset: 18h Default Value: 00h 26.2.11 Attribute: Size: Attribute: Size: R/W 8 bits Bit Description 7:0 Secondary Bus Number (SCBN): These bits indicate the bus number of the PCI device to which the secondary interface is connected. Any Type 1 configuration cycle matching this bus number is translated to a Type 0 configuration cycle and run on the PCI bus. SUBBus--Subordinate Bus Number Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 1Ah Default Value: 00h Attribute: Size: R/W 8 bits Bit Description 7:0 Subordinate Bus Number (SBBN): These bits indicate the highest PCI bus number downstream of this bridge. Every Type 1 configuration cycle on PCI Express with a bus number greater than the secondary bus number and less than or equal to the subordinate bus number is forwarded as a Type 1 configuration cycle to the secondary PCI bus. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 893 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) 26.2.13 IOBL--I/O Base Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 1Ch Default Value: 00h 26.2.14 Description 7:4 I/O Base Address Bits (IOBA): These bits define the bottom address of an address range to determine when to forward I/O transactions from one interface to another. These bits correspond to address lines[15:12] for 4 KB alignment. Bits[11:0] are assumed to be 000h. 3:0 I/O Base Addressing Capability (IOBC): Each of these bits is hard-wired to 0, indicating support for 16-bit I/O addressing only. IOBL--I/O Limit Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Bit 15:12 11:8 Attribute: Size: R/W, RO 8 bits Description I/O Limit Address Bits (IOLA): These bits define the top address of an address range to determine when to forward I/O transactions from PCI Express to PCI. These bits correspond to address lines[15:12] for 4 KB aligned window. Bits[11:0] are assumed to be FFFh. I/O Limit Addressing Capability (IOLC): Each of these bits is hard-wired to 0, indicating support for 16-bit I/O addressing only. SSTS--Secondary Status Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 1Eh-1Fh Default Value: 0000h 894 R/W, RO 8 bits Bit Address Offset: 1Dh Default Value: 0000h 26.2.15 Attribute: Size: Attribute: Size: R/WC 16 bits Bit Description 15 Detected Parity Error (DPE) -- R/WC. 0 = No error. 1 = This bit is set by the secondary side for a Type 1 Configuration Space header function whenever it receives a Poisoned TLP, regardless of the state in the Parity Error Response Enable (PERE) field of the Bridge Control Register (BCTL) 14 Received System Error (RSE) -- R/WC. 0 = No error. 1 = This bit is set by the secondary side for a Type 1 Configuration Space header function whenever it receives an ERR_FATAL or ERR_NONFATAL message. 13 Received Master Abort (RMA) -- R/WC. 0 = Unsupported Request not received. 1 = This bit is set when the secondary side for Type 1 configuration space header function (for requests initiated by the Type 1 header function itself) receives a completion with Unsupported Requests Completion Status. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) Bit 12 Received Target Abort (RTA) -- R/WC. 0 = Completion Abort not received. 1 = This bit is set when the secondary side for Type 1 Configuration Space Header Function (for Requests initiated by the Type 1 header Function itself) receives a completion with Completer About Completion Status... 11 Signaled Target Abort (STA) -- R/WC. 0 = Completion Abort not sent. 1 = This bit is set when the secondary side for Type 1 configuration space header function (for requests completed by type 1 header functions itself) completes a Posted or Non-posted request as a Completer Abort error. 10:9 Secondary DEVSEL# Timing Status (SDTS): Reserved per PCI Express* Base Specification. 8 Data Parity Error Detected (DPD) -- R/WC. 0 = Conditions below did not occur.. 1 = This bit is set by the secondary side requester if the Parity Error Response Enable (PERE) bit in the Bridge Control Register (BCTL) is set and either of the following conditions occur * Requester receives completion marked poisoned * Requester sends a poisoned request (includes writes and messages). 7 Secondary Fast Back to Back Capable (SFBC): Reserved per PCI Express* Base Specification. 6 Reserved 5 Secondary 66 MHz Capable (SC66): Reserved per PCI Express* Base Specification. 4:0 26.2.16 Description Reserved MBL--Memory Base Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 20h-21h Default Value: 0000h R/W 16 bits Bit Description 15:4 Memory Base (MB) -- R/W. These bits are compared with bits[31:20] of the incoming address to determine the lower 1 MB-aligned value (inclusive) of the range. The incoming address must be greater than or equal to this value. 3:0 26.2.17 Attribute: Size: Reserved MBL--Memory Limit Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 22h-23h Default Value: 00000000h Attribute: Size: R/W 16 bits Bit Description 15:4 Memory Limit (ML) -- R/W. These bits are compared with bits[31:20] of the incoming address to determine the upper 1 MB-aligned value (exclusive) of the range. The incoming address must be less than this value. 3:0 Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 895 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) 26.2.18 PMBL--Prefetchable Memory Base (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 24h-25h Default Value: 0001h Description 15:4 Prefetchable Memory Base (PMB) -- R/W. These bits are compared with bits[31:20] of the incoming address to determine the lower 1 MB-aligned value (inclusive) of the range. The incoming address must be greater than or equal to this value. 64-bit Indicator (I64B) -- RO 0: 32-bit Prefetchable Memory addressing. 1: 64-bit Prefetchable Memory addressing. This field indicates that 64-bit addressing is supported for the limit. PMBL--Prefetchable Limit Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 26h-27h Default Value: 0001h 15:4 Prefetchable Memory Limit (PML) -- R/W. These bits are compared with bits[31:20] of the incoming address to determine the upper 1 MB-aligned value (inclusive) of the range. The incoming address must be less than this value. 64-bit Indicator (I64L) -- RO. Indicates support for 64-bit addressing PMBU32--Prefetchable Memory Base Upper 32 Bits Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) Bit 31:0 Attribute: Size: R/W 32 bits Description Prefetchable Memory Base Upper Portion (PMBU) -- R/W. Lower 32-bits of the prefetchable address base. PMLU32--Prefetchable Memory Limit Upper 32 Bits Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) Address Offset: 2Ch-2Fh Default Value: 00000000h Bit 31:0 896 R/W, RO 32 bits Description Address Offset: 28h-2Bh Default Value: 00000000h 26.2.21 Attribute: Size: Bit 3:0 26.2.20 R/W, RO 16 bits Bit 3:0 26.2.19 Attribute: Size: Attribute: Size: R/W 32 bits Description Prefetchable Memory Limit Upper Portion (PMLU) -- R/W. Upper 32-bits of the prefetchable address limit. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) 26.2.22 CAPP--Capabilities List Pointer Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 34h Default Value: 40h Bit 7:0 26.2.23 R0 8 bits Description Capabilities Pointer (PTR) -- RO. Indicates that the pointer for the first entry in the capabilities list is at 40h in configuration space. INTR--Interrupt Information Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 3Ch-3Dh Default Value: 0100 Function Level Reset: No (Bits 7:0 only) Bit 15:8 7:0 26.2.24 Attribute: Size: Attribute: Size: R/W, RO 16 bits Description Interrupt Pin (IPIN) -- RO. This register tells which interrupt pin the function uses. 01h: Generate INTA 02h: Generate INTB 03h: Generate INTC 04h: Generate INTD Others: Reserved BIOS has the ability to write this register once during boot to setup the correct interrupt for the Function. Note: Lock Key bit is located in the Personality Lock Key Control Register Interrupt Line (ILINE) -- R/W. Default = 00h. Software written value to indicate which interrupt line (vector) the interrupt is connected to. No hardware action is taken on this register. These bits are not reset by FLR. BCTRL--Bridge Control Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 3Eh-3Fh Default Value: 0000h Bit Attribute: Size: R/W 16 bits Description 15: 12 Reserved 11 Discard Timer SERR# Enable (DTSE): Reserved per PCI Express* Base Specification, Revision 2.1 10 Discard Timer Status (DTS): Reserved per PCI Express* Base Specification, Revision 2.1. 9 Secondary Discard Timer (SDT): Reserved per PCI Express* Base Specification, Revision 2.1. 8 Primary Discard Timer (PDT): Reserved per PCI Express* Base Specification, Revision 2.1. 7 Fast Back to Back Enable (FBE): Reserved per PCI Express* Base Specification, Revision 2.1. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 897 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) Bit Description Secondary Bus Reset (SBR) -- R/W. Setting this bit triggers a hot reset on the downstream link for the corresponding PCIE Express port and the PCI Express* hierarchy domain subordinate to the port. Software must ensure a minimum reset duration of 1us as defined in the PCI Local Bus Specification, Revision 3.0. Hardware will continue to maintain the hot reset state as long as the SBR bit is set. 6 For Root Ports/switch, it is recommended that software assert this field for a minimum of 2 ms to ensure that all downstream links enters hot reset state. For a Switch, the following must cause a hot reset to be sent on all Downstream Ports: * Setting the Secondary Bus Reset bit of the Bridge Control register associated with the Upstream Port * The Data Link Layer of the Upstream Port reporting DL_Down status 30 * Receiving a hot reset on the Upstream Port A secondary bus reset will not reset any register of a Type 1 configuration space header function. 898 5 Master Abort Mode (MAM): Reserved per Express specification. 4 VGA 16-Bit Decode (V16) -- R/W. This bit enables the bridge to provide 16-bit decoding of VGA I/O address precluding the decoding of VGA alias addresses every 1 KB. This bit requires the VGA enable bit (bit 3 of this register) to be set to 1. 0: execute 10-bit address decode on VGA I/O accesses 1: execute 16-bit address decode on VGA I/O accesses 3 VGA Enable (VE)-- R/W. 0 = The ranges below will not be claimed off the backbone by the root port. 1 = This bit modifies the response to VGA-compatible addresses. When set to 1b, the bridge positively decodes and forwards the following transactions from primary side to secondary side regardless of the value of the I/O base and limit registers. The transactions are qualified by the memory enable and I/O enable in the command register. Memory addresses: 000A 0000h-000B FFFFh I/O addresses: 3B0h-3BBh and 3C0h-3DFh in first 64 KB of I/O address space (Inclusive of ISA address aliases when IO address bits[15:10] are not decoded) The following ranges will be claimed off the backbone by the root port: * Memory ranges A0000h-BFFFFh * I/O ranges 3B0h - 3BBh and 3C0h - 3DFh, and all aliases of bits 15:10 in any combination of 1s 2 ISA Enable (IE) -- R/W. This bit modifies the response by the bridge to ISA I/O addresses. This field applies only to I/O addresses that are enabled by the I/O base and I/O limit registers and are in the first 64 KB of PCI I/O space. When this bit is set, the bridge blocks all forwarding from primary to secondary of I/O transactions addressing the last 768 bytes in each 1 KB block (offsets 100h to 3FFh). In the opposite direction (secondary to primary), I/O transactions will be forwarded if they address the last 768B in each 1 KB block. 1: Forward upstream ISA I/O addresses in the address range defined yb the I/O Base and I/O Limit registers that are in the firsts 64KB of PCI I/O address space (Top 768B of each 1K block). 0: Forward downstream all I/O addresses in the address range defined by the I/O Base and I/O Limit registers. 1 SERR# Enable (SE) -- R/W. This bit controls the forwarding of PCI Express ERR_COR, ERR_NONFATAL and ERR_FATAL messages to the primary side. 1: Enables forwarding of ERR_COR, ERR_NONFATAL, ERR_FATAL messages. 0: Disables forwarding of ERR_COR, ERR_NONFATAL, ERR_FATAL messages. 0 Parity Error Response Enable (PERE) -- R/W., This bit controls the response to poisoned TLPs in the PCI Express* port. 1: Enables reporting of poisoned TLP errors. 0: Disables reporting of poisoned TLP errors Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) 26.2.25 CLIST--Capabilities List Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 40-41h Default Value: 8010h Bit 15:8 7:0 26.2.26 RO 16 bits Description Next Capability (NEXT) -- RO. Value of 80h indicates the location of the next pointer. Capability ID (CID) -- RO. Indicates this is a PCI Express* capability. XCAP--PCI Express* Capabilities Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 42h-43h Default Value: 0042h or 0062h Bit 15:14 13:9 8 26.2.27 Attribute: Size: Attribute: Size: R/WO, RO 16 bits Description Reserved Interrupt Message Number (IMN) -- RO. The PCH does not have multiple MSI interrupt numbers. Slot Implemented (SI) -- RO. Hardwired to 0 for non root ports and non DP 7:4 Device / Port Type (DT) -- RO. 6h: Virtual Switch Port 4h: Virtual Root Port 3:0 Capability Version (CV) -- RO. Indicates PCI Express* 2.0. DCAP--Device Capabilities Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 44h-47h Default Value: 00008000 or 00008001h Bit Attribute: Size: RO 32 bits Description 31:28 Reserved 27:26 Captured Slot Power Limit Scale (CSPS) -- RO-V In combination with the Slot Power Limit value (bits[25:18], this field specifies the upper limit of the power supplied by slot. The power limit (in Watts) is calculated by multiplying the value in this field by the value in the Slot Power Limit Value field. This value is set by the Set_Slot_Power_Limit message. 25:18 Captured Slot Power Limit Value (CSPV) -- RO-V In combination with the Slot Power Limit Scale value (bits[27:26]), this field specifies the upper limit of the power supplied by slot. The power limit (in Watts) is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field. This value is set by the Set_Slot_Power_Limit message. 17:16 Reserved 15 14:12 Role Based Error Reporting (RBER) -- RO. Indicates that this device implements the functionality defined in the Error Reporting ECN as required by the PCI Express* 1.1 spec. Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 899 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) Bit 26.2.28 Description 11:9 Endpoint L1 Acceptable Latency (E1AL) -- RO. This field is reserved with a setting of 000b for devices other than Endpoints, per the PCI Express* 1.1 Spec. 8:6 Endpoint L0s Acceptable Latency (E0AL) -- RO. This field is reserved with a setting of 000b for devices other than Endpoints, per the PCI Express* 1.1 Spec. 5 Extended Tag Field Supported (ETFS) -- RO. Indicates that a 5-bit tag fields are supported. 4:3 Phantom Functions Supported (PFS) -- RO. No phantom functions supported. 2:0 Max Payload Size Supported (MPS) -- RO. Indicates the maximum payload size VRP: 000 = 128B VSP: 001 = 256B DCTL--Device Control Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 48h-49h Default Value: 2000h Bit 15 14:12 R/W, RO 16 bits Description Reserved Max Read Request Size (MRRS) -- R/W. 512Bytes is the maximum read request size. 11 Enable No Snoop (ENS) -- RO. Not supported. The root port will never issue non-snoop requests. 10 Aux Power PM Enable (APME) -- R0. Not supported, hardwired to 0. 9 8 7:5 900 Attribute: Size: Phantom Functions Enable (PFE) -- RO. Not supported. Extended Tag Field Enable (ETFE) -- RO. Not supported. Max Payload Size (MPS) -- R/W. 128 bytes is the default, but 256 is also supported. Not other sizes are supported. 4 Enable Relaxed Ordering (ERO) -- RO. Not supported. 3 Unsupported Request Reporting Enable (URE) -- R/W. 0 = The root port will ignore unsupported request errors. 1 = Allows signaling ERR_NONFATAL, ERR_FATAL, or ERR_COR to the Root Control register when detecting an unmasked Unsupported Request (UR). An ERR_COR is signaled when a unmasked Advisory Non-Fatal UR is received. An ERR_FATAL, ERR_or NONFATAL, is sent to the Root Control Register when an uncorrectable non-Advisory UR is received with the severity set by the Uncorrectable Error Severity register. 2 Fatal Error Reporting Enable (FEE) -- R/W. 0 = The root port will ignore fatal errors. 1 = Enables signaling of ERR_FATAL to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting. 1 Non-Fatal Error Reporting Enable (NFE) -- R/W. 0 = The root port will ignore non-fatal errors. 1 = Enables signaling of ERR_NONFATAL to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting. 0 Correctable Error Reporting Enable (CEE) -- R/W. 0 = The root port will ignore correctable errors. 1 = Enables signaling of ERR_CORR to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) 26.2.29 DSTS--Device Status Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 4Ah-4Bh Default Value: 0000h Bit 15:6 26.2.30 Attribute: Size: R/WC, RO 16 bits Description Reserved 5 Transactions Pending (TDP) -- RO. Functions that do not issue Non-Posted requests on their own behalf should hardwire this bit to 0b... 4 AUX Power Detected (APD) -- RO. Auxiliary Power is not supported. 3 Unsupported Request Detected (URD) -- R/WC. Indicates an unsupported request was detected. 2 Fatal Error Detected (FED) -- R/WC. Indicates a fatal error was detected. 0 = Fatal has not occurred. 1 = This bit indicates that this function has detected a Fatal error. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. 1 Non-Fatal Error Detected (NFED) -- R/WC. Indicates a non-fatal error was detected. 0 = Non-fatal has not occurred. 1 = This bit indicates that this function has detected a Non-Fatal error. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register... 0 Correctable Error Detected (CED) -- R/WC. Indicates a correctable error was detected. 0 = Correctable has not occurred. 1 = This bit indicates that this function has detected a Correctable error. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. LCAP--Link Capabilities Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 4Ch-4Fh Default Value: see description Bit Attribute: Size: R/WO, RO 32 bits Description Port Number (PN) -- RO. This field indicates the PCI Express* port number assigned to this 31:24 link. VRP = 11h VSP = 08h 23 Reserved 22 SPM Optionality Compliance (ASPMOPCMP): The ASPM Optionality Compliance bit was created as a tool to set clear expectations for hardware and software interaction. This bit is Set to indicate hardware that conforms to the current specification. 21 Link Bandwidth Notification Capability (LBNC): R0: Hardwired to 0 20 Data Link Layer Active Error Reporting Capable (DLLERC): RO. Not supported, hardwired to 0 19 Surprise Link Down Error Reporting Capable (SLDERC): RO. Hardwired to 0 18 Clock Power Management Capable (CPMC): RO. Hardwired to 0 17:15 L1 Exit Latency (EL1) -- RO. Set to 000b to indicate an exit latency of less than 1s. 14:12 L0s Exit Latency (EL0) -- RO. Set to 000 to indicate an exit latency of less than 64 ns Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 901 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) Bit 11:10 Active State Link PM Support (APMS) -- RO. 11b Indicates both L1 and L0s supported 9:4 Maximum Link Width (MLW) -- RO 01h indicating the maximum width is a x1. 3:1 Reserved 0 26.2.31 Description Maximum Link Speed (MLS) -- RO. 1b = 2.5 Gb/s link speed is supported LCTL--Link Control Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 50h-51h Default Value: 0000h Bit 15:12 R/W, RO 16 bits Description Reserved 11 Link Autonomous Bandwidth Interrupt Enable (LABIE) -- RO Hardwired to 0 as not applicable 10 Link Bandwidth Management Interrupt Enable (LBMIE) -- RO Hardwired to 0 as not applicable 9 Hardware Autonomous Width Disable - RO. Components that do not implement the ability such as (Upstream Ports, Virtual Switch Ports) to autonomously change link width are permitted to hardwire this bit to 0b 8 Reserved 7 Extended Synch (ES) -- R/W. 0 = Extended synch disabled. 1 = Forces extended transmission of FTS ordered sets in FTS and extra TS2 at exit from L1 prior to entering L0. 6 Common Clock Configuration (CCC) -- R/W. 0 = The PCH and device are not using a common reference clock. 1 = The PCH and device are operating with a distributed common reference clock. After changing the value in this bit in bother components on a link, software must trigger the link to retrain by writing a 1b to the Retrain Link bit of the Downstream Port. 5 Retrain Link (RL) -- RO. Hardwired to 0. For the upstream port or virtual switch port, it is Read-only 4 Link Disable (LD) -- R/W. This bit disables the link when set. 3 Read Completion Boundary Control (RCBC) -- RO. Indicates the read completion boundary is 64 bytes. 2 Reserved 1:0 902 Attribute: Size: Active State Link PM Control (APMC) -- R/W. Indicates whether the upstream port should enter L0s or L1 or both. Bits Definition 00 Disabled 01 L0s Entry Enabled 10 L1 Entry Enabled 11 L0s and L1 Entry Enabled Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) 26.2.32 LSTS--Link Status Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 52h-53h Default Value: See bit description Bit 26.2.33 Attribute: Size: RO 16 bits Description 15 Link Autonomous Bandwidth Status (LABS): - RO Not applicable, hardwired to 0 14 Link Bandwidth Management Status (LBMS): -RO Hardwired to 0. This bit is not applicable and is reserved for endpoints, PCI Express-to-PCI/PCI-X bridges, and upstream ports of switches. 13 Data Link Layer Active (DLLA) -- RO. Default value is 0b. 0 = Data Link Control and Management State Machine is not in the DL_Active state 1 = Data Link Control and Management State Machine is in the DL_Active state 12 Slot Clock Configuration (SCC) -- RO. Set to 1b to indicate that the PCH uses the same reference clock as on the platform and does not generate its own clock. 11 Link Training (LT) -- RO. This field is not applicable and reserved for the upstream port, end point and must be hardwired to 0b. 10 Undefined: hard wired to zero. 9:4 Negotiated Link Width (NLW) -- RO. This field indicates the negotiated width of the given PCI Express* link. The contents of this NLW field is undefined if the link has not successfully trained. 00 0001b = x1 00 0010b = X2 00 0100b = x4 Only valid width is 00_0001b 3:0 Link Speed (LS) -- RO. This field indicates the negotiated Link speed of the given PCI Express* link. Only valid value is 1h 0001b = 2.5 Gb/s PCI Express Link Others = Reserved Note: The encoding is the binary value of the bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the current Link speed. Note: The value in this field is undefined when the link is not up. ROOTCTL--Root Control Register (Virtual Root Port--B0:D17:F0) Address Offset: 5C-5Dh Default Value: 00000000h Bit 15:5 Attribute: Size: RO, R/W 16 bits Description Reserved 4 CRS Software Visibility Enable (CRSSVE) -- RO 0b = The VRP does not support CRS Enablement 3 PME Interrupt Enable (PMEIE) R/W 0 = Disables interrupt generation for PME messages (default) 1 = Enables interrupt generation upon receipt of PME message Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 903 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) Bit 26.2.34 Description 2 System Error on Fatal Error Enable (SEFEE) -- R/W 0 = No system error should be generated on a fatal error reported by any of the devices in the hierarchy. 1 = A system error should be generated if a fatal error (ERR_FATAL) is reported by any of the devices in the hierarchy associated with and including this PCI Express* port. 1 System Error on non-Fatal Error Enable (SENFEE) -- R/W 0 = No system error should be generated on a non-fatal error reported by any of the devices in the hierarchy. 1 = A system error should be generated if a non-fatal error (ERR_NONFATAL) is reported by any of the devices in the hierarchy associated with and including this PCI Express* port. 0 System Error on Correctable Error Enable (SECEE) 0 = No system error should be generated on a correctable error reported by any of the devices in the hierarchy. 1 = A system error should be generated if a correctable error (ERR_COR) is reported by any of the devices in the hierarchy associated with and including this PCI Express* port. ROOTCAP--Root Capabilities Register (Virtual Root Port--B0:D17:F0) Address Offset: 5E-5Fh Default Value: 0000h Bit 15:1 0 26.2.35 RO 16 bits Description Reserved CRS Software Visibility (CRSSV) -- RO This bit, when set, indicates that the root port is capable of returning Configuration Retry Status on completions to software. This port does not support this capability and is set to "0" ROOTSTS--Root Status Register (Virtual Root Port--B0:D17:F0) Address Offset: 60-63h Default Value: 00000000h Bit 31:18 Attribute: Size: RO, R/W1C 32 bits Description Reserved 17 PME Pending (PMEPEND) -- RO This field indicates that another PME is pending when the PME status bit is set. When the PME status bit is cleared by software, the pending PME is delivered by HW by setting the PME status bit again and updating the Requester ID appropriately. The PME pending bit is cleared by HW if no more PMEs are pending. The root port can handle two outstanding PM_PME messages in it's internal queues of the power management controller per port. 16 PME Status (PMESTS) -- R/W1C When set, indicates that a PME was asserted by a requester as indicated by the PMEREQID field. This bit is cleared by writing a "1" to it. Subsequent PMEs are kept pending until the PME Status is cleared 15;0 904 Attribute: Size: PME Requester ID (PMERID) -- R0 This field indicates the PCI Requester ID of the last PME requestor... Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) 26.2.36 DCAP2--Device Capabilities 2 Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 64h-67h Default Value: 00000020h Bit 31:5 26.2.37 Attribute: Size: RO 32 bits Description Reserved 19:18 OBFF Supported (OBFFS) 00b: OBFF Not Supported Applicable only to Root Ports, Switch Ports, and Endpoints that support this capability. Must be 00b for other function types. 17:14 Reserved 13:12 TPH Completer Supported (TPHCS) Applicable only to Root Ports and Endpoints. Must be 00b for other function types 11 LTBWR Mechanism Supported (LTBWRMS) his bit must be hardwired to 0b for function that do not implement this capability. 10 No RO-enabled PR-PR Passing (NROEPRPASS) Hardwiired to 0b. This bit applies only for Switches and RCs that support peer-to-peer traffic between ports 9 AD128 CAS Completer Supported (AD128ACS) hardwired to 0b 8 AD64-bit AtomicOp Completer Supported (AD64ACS) Hardwired to 0b 7 AD32 bit AtomicOp Completer Supported (AD32ACS) Hardwired to 0b 6 AtomicOp Routing Supported (ARS) -- R/WO Default is 0b 5 Alternative RID Interpretation Capable (ARI) This bit is set to 1b indicating that the downstream port supports this capability. 4 Completion Timeout Disable Supported (CTDS) -- RO. Hardwired to 0. 3:0 Completion Timeout Ranges Supported (CTRS) - RO. Hardwired to 0000b DCTL2--Device Control 2 Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 68h-69h Default Value: 0000h Bit 15 RO, R/W 16 bits Description Reserved 14:13 OBFF Enable (OBFFE) -- RO Hardwired to 00b 12;11 Reserved 10 Attribute: Size: LTBWR Mechanism Enable (LTBWRME) -- RO Not supported so hardwired to 0b Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 905 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) Bit 9 IDO Completion Enable (IDOCE) -- RO Hardwired to 0b. Applicable only to Endpoints including RC integrated Endpoints and Root Ports. 8 IDO Request Enable (IDORE) -- RO Hardwired to 0b. Applicable only to Endpoints including RC integrated Endpoints and Root Ports. 7 AtomicOp Egress Blocking (AEB) -- R/W 0 = AtomicOp requests that target this out going Egress port are permitted 1 = AtomicOp requests that target this out going Egress port must be blocked. 6 AtomicOp Requester Enable (ARE) Applicable only to Endpoints and Root Ports; must be hardwired to 0b for other Function types. 5 Alternative RID Interpretation Enable (ARIE) -- R/W When set to 1b, ARI is enabled for the downstream port or root ports. 4 Completion Timeout Disable (CTD) -- RO. Hardwired to 0b 1 = Disable the completions timeout mechanism for all NP transactions. 0 = Completion timeout is enabled for all NP transactions. 3:0 26.2.38 Description Completion Timeout Value (CTV) -- R0 Hardwired to 0000b. DEVSTS2--Device Status 2 Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 6Ah-6Bh Default Value: 0000h Bit 15:0 26.2.39 Attribute: Size: Description Reserved L2--Link Control 2 Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 70h-71h Default Value: 0001h Bit 15:13 Attribute: Size: RO, R/WS 16 bits Description Reserved. Hardwired to 00b 12 Compliance De-emphasis (CD) -- RO. This bit sets the de-emphasis level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit (EC) (bit 4) in this register being 1b. 1b = -3.5 dB 0b = -6 dB When the link is operating at 2.5 Gb/s, the setting of this bit has no effect. Only cleared to default with a power good reset 11 Compliance SOS (CSOS) -- RO. Set to 0b 10 Enter Modified Compliance (EMC) -- RO. Set to 0b 9:7 Transmit Margin (TM) -- RO - set to 000b 6 906 RO 16 bits Selectable De-emphasis (SD) -- RO. Hardwired to 0b This bit is not applicable and reserved for Endpoints, PCI Express* to PCI/PCI-X bridges, and upstream ports of switches. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) Bit 5 Hardware Autonomous Speed Disable (HASD) -- RO. Set to 0b 4 Enter Compliance (EC) -- RO. Set to 0b 3:0 26.2.40 Description Target Link Speed (TLS) -- R/WS . 0001b = 2.5 Gb/s Target Link Speed LINKSTS2--Link STatus2 Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 72h-73h Default Value: 0000h Bit 15:1 0 26.2.41 RO 16 bits Description Reserved Current De-emphasis Level (CDL): RO When the link is operating at 5 Gb/s speed, this bit reflects the level of de-emphasis. 1b: -3.5 dB 0b: -6 dB PMCAP--Power Management Capability Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 80h-81h Default Value: 0001h Bit 15:8 7:0 26.2.42 Attribute: Size: Attribute: Size: RO 16 bits Description Next Capability (NEXT) -- RO. Indicates this is the last item in the list. Capability Identifier (CID) -- RO. Value of 01h indicates this is a PCI power management capability. PMC--PCI Power Management Capabilities Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 82h-83h Default Value: C803h Bit 15:11 Attribute: Size: Description PME_Support (PMES) -- RO. Indicates PME# is supported for states D0, D3HOT and D3COLD... 10 D2_Support (D2S) -- RO. The D2 state is not supported. 9 D1_Support (D1S) -- RO The D1 state is not supported. 8:6 Aux_Current (AC) -- RO. Aux current is not supported 5 RO 16 bits Device Specific Initialization (DSI) -- RO. Device-specific initialization is not required when transitioning to D0 from D3hot state. This bit is zero. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 907 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) Bit 4 Reserved 3 PME Clock (PMEC) -- RO. Does not apply to PCI Express. Hard-wired to 0. 2:0 26.2.43 Description Version (VS) -- RO. Indicates support for Revision 1.2 of the PCI Power Management Specification. PMCSR--PCI Power Management Control and Status Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) Address Offset: 84h-85h Default Value: 0004h Bit 15 12:9 Data Select (DS): Not supported, hardwired to 0 PME Enable (PMEE) -- R/WS. 0 = PME messages are gated and PME messages are not generated 1 = PME messages are enabled Reserved 3 No Soft Reset (NSR): R/WL This bit when 1b indicates that a device transitioning from D3hot to D0 does not perform an internal reset. The configuration context is preserved. 2 Reserved 1:0 26.2.44 PME Status (PMES) -- R/W1C 0 = Indicates no PME received from downstream link 1 = Indicates a PME was received on the downstream link. Data Scale (DC):RO Not supported. Hardwired to 0 7:4 Power State (PS) -- R/W. This field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the supported values is given below: 0h - D0 3h - D3hot If software attempts to write an unsupported, optional state to this field, the write operation must complete normally; however, the data is discarded and no state change occurs. PMBSE--Power Management Bridge Support Extensions Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) Address Offset: 86h Default Value: 00h Bit Attribute: Size: RO 0 bits Description 7 Bus Power/Clock Control Enable (BPCC_EN): Neither bus or clock control of PCI is supported when in D3hot state. This bit is hard-wired to 0. 6 B2/B3# (B23EN): Not supported. This bit has no meaning since the BPCC_En bit is hard-wired to 0. 5:0 908 R/W, RO 16 bits Description 14:13 8 Attribute: Size: Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) 26.2.45 SVCAP--Subsystem Capability List Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 88h-89h Default Value: 900Dh Bit 15:8 7:0 26.2.46 Next Capability (NEXT) -- RO. Contains the offset of the next item in the capabilities list Capability Identifier (CID) -- RO. Identifies the function as Subsystem Identification capable. SVID--Subsystem Vendor ID Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Bit 15:0 Attribute: Size: R/WO 16 bits Description Subsystem Vendor Identifier (SVID) -- R/WO. Indicates the manufacturer of the subsystem. This field is write once and is locked down until a bridge reset occurs (not the PCI bus reset). SVID--Subsystem ID Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 8Eh-8Fh Default Value: 0000h Bit 15:0 26.2.48 RO 16 bits Description Address Offset: 8Ch-8Dh Default Value: 8086h 26.2.47 Attribute: Size: Attribute: Size: R/WO 16 bits Description Subsystem Identifier (SID) -- R/WO. Indicates the subsystem as identified by the vendor. This field is write once and is locked down until a bridge reset occurs (not the PCI bus reset). MSICAPLST--MSI Capability List Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 88h-89h Default Value: 0005h Attribute: Size: RO 16 bits Bit Description 15:8 Next Capability (NEXT) -- RO. Contains the offset of the next item in the capabilities list. A null value is used to indicate that this is the last capability 7:0 Capability Identifier (CID) -- RO. Identifies the function as MSI capable. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 909 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) 26.2.49 MSICTL--MSI Message Control Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 92h Default Value: 0000h Bit 15:8 7 RO, R/W 16 bits Description Reserved Address 64-bit Capable (AD64C): RO 0b means the function is not capable of 64 bit message addresses 6:4 Multiple Message Enable (MMEN): R/W Only one message is supported. These bits are R/W for software compatibility. 3:1 Multiple Message Capable (MMC): RO Only one message is supported so these bits are wired 000b 0 910 Attribute: Size: MSI Enable (MSIE): R/W When set, MSI is enabled and traditional pins are not used to generate interrupts. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) 26.2.50 MSIADDR--MSI Message Address Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 94h Default Value: 00000000h Bit 31:2 1:0 26.2.51 RO, R/W 32 bits Description Address: R/W Message address specified by the system, always DWORD aligned Reserved: RO MSIDATA--MSI Message Data Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 98h Default Value: 0000h Bit 15:0 26.2.52 Attribute: Size: Attribute: Size: R/W 16 bits Description DATA This 16 bit field is programmed by system software when MSI is enabled. It's content is driven on the lower work of the MSI Memory write transaction. AERCAPHDR--Advanced Error Reporting Capabilities Header (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) Address Offset: 100-103h Default Value: 13810001h Bit Attribute: Size: RO, R/WO 16 bits Description 31:20 Next Capability Offset (NCO):R/WL Contains the offset of the next structure in the Extended Capabilities list for endpoint. 19i:16 Capability Version (CV):RO Indicates the version of the Capability structure present. 15:0 Extended Capability ID (EXCAPID): RO Identifies the function as Advanced Error Reporting capable. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 911 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) 26.2.53 UES--Uncorrectable Error Status Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 104h-107h Default Value: 00000000h Attribute: Size: R/WC, RO 32 bits This register maintains its state through a platform reset. It loses its state upon suspend. Bit 31:25 Reserved, hardwired to 0 24 Atomic Egress Blocked Error (AEBE): R/WC. default 0b This bit is set whenever an Atomic OP TLP is blocked on any egress port 23 MC Blocked TLP Error (MCE): RO Not supported, set to 0b 22 Uncorrectable Internal Error (UIE):R/WC. default 0b This bit is set whenever an uncorrectable internal error is detected. 21 ACS Violation Error (ACSE): R/WC. Default 0b This bit is set whenever an ACS violation is detected by the PCI Express* port. 20 Unsupported Request Error Status (URE) -- R/WC. Default 0b Indicates an unsupported request was received. 19 ECRC Error Status (EE) -- RO. ECRC is not supported. 18 Malformed TLP Status (MT) -- R/WC. Default 0b Indicates a malformed TLP was received. 17 Receiver Overflow Status (RO) -- R/WC. Default 0b Indicates a receiver overflow occurred. 16 Unexpected Completion Status (UC) -- R/WC. Default 0b This bit is set whenever a completion is received with a requestor ID that does not match side A or side B, or when a completion is received with a matching requestor ID but an unexpected tag field. Header logging is performed. 15 Completion Abort Status (CA) -- R/WC. Default 0b The bridge sets this bit and logs the header associated with the request when the configuration unit signals a completer abort. 14 Completion Timeout Status (CT) -- RO. Not supported, set to 0b 13 Flow Control Error (FCE):R/WC. default is 0b This bit is set when a flow control protocol error is detected. 12 Poisoned TLP Error (PTLPE): R/WC Default is 0b This bit is set and the bridge logs the header when a poisoned TLP is received from PCI Express. 11:6 Reserved Software must write 0 to these bits 5 Surprise Link Down Error (SLDE): R/WC: Default is 0b This bit is set when a surprise link down error is detected. 4 Data Link Protocol Error Status (DLPE) -- R/WC. Indicates a data link protocol error occurred. 3:0 912 Description Reserved Set to 0h Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) 26.2.54 UEM--Uncorrectable Error Mask (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 108h-10Bh Default Value: 00000000h Attribute: Size: R/WS, RO 32 bits When set, the corresponding error in the UES register is masked, and the logged error will cause no action. When cleared, the corresponding error is enabled. Bit 31:25 Description Reserved 24 AtomicOp Egress Blocked Error Mask (AEBEM):R/WS 23 MC Blocked TLP Error Mask (MCEM):RO 22 Uncorrectable Internal Error Mask (UIEM):R/WS 21 ACS Violation Error Mask (ACSEM): R/WS 20 Unsupported Request Error Mask (URE) -- R/WS. 19 ECRC Error Mask (EE) -- RO. ECRC is not supported. 18 Malformed TLP Mask (MT) -- R/WS. 17 Receiver Overflow Mask (RO) -- R/WS. 16 Unexpected Completion Mask (UC) -- R/WS. 15 Completion Abort Mask (CA) -- R/WS. 14 Completion Timeout Mask (CT) -- RO Hardwired to 0 13 Flow Control Protocol Error Mask (FCPE) -- R/WS 12 Poisoned TLP Mask (PT) -- R/WS 11:6 5 4 3:0 Reserved Surprise Link Down Error Mask (SLDEM):R/WS Data Link Protocol Error Mask (DLPE) -- R/WS. Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 913 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) 26.2.55 UEV -- Uncorrectable Error Severity (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 10Ch-10Fh Default Value: 00462030h Attribute: Size: Bit 31:25 Description Reserved 24 AtomicOp Egress Blocked Severity (AEBES) -- R/W. 0 = Error considered non-fatal. (Default) 1 = Error is fatal. 23 MC Blocked TLP Error Severity (MCES): RO hardwired to 0b 22 Uncorrectable Internal Error Severity (UIES) -- R/W. 0 = Error considered non-fatal. 1 = Error is fatal.(default) 21 ACS Violation Error Severity (ACSES) -- RO 0 = Error considered non-fatal. (default) 1 = Error is fatal. 20 Unsupported Request Error Severity (URE) -- R/W. 0 = Error considered non-fatal. (Default) 1 = Error is fatal. 19 ECRC Error Severity (EE) -- RO. ECRC is not supported. 18 Malformed TLP Severity (MT) -- R/W. 0 = Error considered non-fatal. 1 = Error is fatal. (Default) 17 Receiver Overflow Severity (RO) -- R/W. 0 = Error considered non-fatal. 1 = Error is fatal. (Default) 16 Unexpected Completion Error Severity (UCES) -- R/W. 0 = Error considered non-fatal. (Default) 1 = Error is fatal. 15 Completion Abort Severity (CA) -- R/W. 0 = Error considered non-fatal. (Default) 1 = Error is fatal. 14 Completion Timeout Error Severity (CTES) -- RO - hardwired to 0 13 Flow Control Protocol Error Severity (FCPE) -- R/W. 0 = Error considered non-fatal. 1 = Error is fatal (Default). 12 Poisoned TLP Severity (PT) -- R/W. 0 = Error considered non-fatal. (Default) 1 = Error is fatal. 11:6 Reserved 5 Surprise Link Down Severity (SLDES) -- R/W. 0 = Error considered non-fatal. 1 = Error is fatal. (Default) 4 Data Link Protocol Error Severity (DLPE) -- R/W. 0 = Error considered non-fatal. 1 = Error is fatal. (Default) 3:0 914 RO, R/W 32 bits Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) 26.2.56 CES--Correctable Error Status Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 110h-113h Default Value: 00000000h Bit 31:16 R/WC 32 bits Description Reserved 15 Header Log Overflow Error (HLOE) -- R/WC Indicates a Header Log Overflow occurred 14 Correctable Internal Error (CIE) -- R/WC - Indicates a correctable Internal Error occurred 13 Advisory Non-Fatal Error Status (ANFES) -- R/WC. 0 = Advisory Non-Fatal Error did not occur. 1 = Advisory Non-Fatal Error did occur. 12 Replay Timer Timeout Status (RTT) -- R/WC. Indicates the replay timer timed out. 11:9 Reserved 8 Replay Number Rollover Status (RNR) -- R/WC. Indicates the replay number rolled over. 7 Bad DLLP Status (BD) -- R/WC. Indicates CRC Error on a DLLP was received. 6 Bad TLP Status (BT) -- R/WC. Indicates a CRC error on a TLP was received. 5:1 0 26.2.57 Attribute: Size: Reserved Receiver Error Status (RE) -- R/WC. Indicates a receiver error occurred. CEM--Correctable Error Mask Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 114h-117h Default Value: 0000E000h Attribute: Size: R/WO 32 bits When set, the corresponding error in the CES register is masked, and the logged error will cause no action. When cleared, the corresponding error is enabled. Bit 31:16 Description Reserved 15 Header Log Overflow Error Mask (HLOEM) --RO Mask for Header Log Overflow 14 Correctable Internal Error Mask (CIEM) -- RO Mask for Correctable Internal Error 13 Advisory Non-Fatal Error Mask (ANFEM) -- R/WO. 0 = Does not mask Advisory Non-Fatal errors. 1 = Masks Advisory Non-Fatal errors from (a) signaling ERR_COR to the device control register and (b) updating the Uncorrectable Error Status register. This register is set by default to enable compatibility with software that does not comprehend RoleBased Error Reporting. Note: The correctable error detected bit in device status register is set whenever the Advisory Non-Fatal error is detected, independent of this mask bit. 12 11:9 Replay Timer Timeout Mask (RTT) -- RO. Mask for replay timer timeout. Reserved 8 Replay Number Rollover Mask (RNR) -- RO. Mask for replay number rollover. 7 Bad DLLP Mask (BD) -- RO. Mask for bad DLLP reception. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 915 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) Bit 6 5:1 0 26.2.58 Description Bad TLP Mask (BT) -- RO. Mask for bad TLP reception. Reserved Receiver Error Mask (RE) -- RO. Mask for receiver errors. AECC--Advanced Error Capabilities and Control Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 118h-11Bh Default Value: 00000000h Bit 31:11 10 Description Reserved Multiple Header Recording Enable (MHRE):RO- Not supported, hardwired to 0b Multiple Header Recording Capable (MHRC): RO - Not supported, hardwired to 0b 8 ECRC Check Enable (ECE) -- RO. ECRC is not supported. Hardwired to 0b 7 ECRC Check Capable (ECC) -- RO. ECRC is not supported.Hardwired to 0b 6 ECRC Generation Enable (EGE) -- RO. ECRC is not supported. Hardwired to 0b 5 ECRC Generation Capable (EGC) -- RO. ECRC is not supported. Hardwired to 0b First Error Pointer (FEP) -- RO. This field identifies the bit position of the first error reported in the Uncorrectable Error Status Register (xref). This register re-arms itself (which does not change its current value) as soon as the error status bit indicated by the pointer is cleared by the software by writing a 1 to that status bit. AEHRDLOG [1-4]--Advanced Error Header Log (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 11Ch-128hFh Default Value: 0000h Bit 31:00 916 RO 32 bits 9 4:0 26.2.59 Attribute: Size: Attribute: Size: RRO 32 bits Description TLP Header Log (TLPHDRLOG): As soon as an error is logged in this register, it remains locked for further error-logging until the software clears the status bit that caused the header log (in other words, until the error pointer is re-armed for logging again). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) 26.2.60 ROOTERRCMD--Root Error Command Register (Virtual Root Port--B0:D17:F0) Address Offset: 12Ch Default Value: 0000h Bit 31:3 26.2.61 Attribute: Size: RO, R/W 32 bits Description Reserved 2 Fatal Error Report Enable (FERE) - R/W When set, enables the generation of an interrupt when a Fatal error is reported by any of the functions in the hierarchy associated with this root port. 1 Non-Fatal Error Report Enable (NFERE) - R/W When set, enables the generation of an interrupt when a Non-Fatal error is reported by any of the functions in the hierarchy associated with this root port. 0 Correctable Error Report Enable (CERE) - R/W When set, enables the generation of an interrupt when a correctable error is reported by any of the functions in the hierarchy associated with this root port. ROOTERRSTS--Root Error Status Register (Virtual Root Port--B0:D17:F0) Address Offset: 130h Default Value: 00000000h Bit 31:27 26:7 Attribute: Size: RO, R/W1C 32 bits Description Advanced Error Interrupt Message Number (AEMN) Reserved - RO 6 Fatal Error Message Received (FEMR) Set by hardware, cleared by writing a 1 to this bit 5 Non-Fatal Error Message Received (NFEMR) Set by hardware, cleared by writing a 1 to this bit 4 First Uncorrectable Fatal (FUF) Set by hardware, cleared by writing a 1 to this bit 3 Multiple Error Fatal/Non-Fatal Received (MEFR) Set by hardware, cleared by writing a 1 to this bit 2 Error Fatal/Non-Fatal Received (EFR) Set by hardware, cleared by writing a 1 to this bit 1 Multiple Error Correctable Received (MCER) Set by hardware, cleared by writing a 1 to this bit 0 Correctable Error Received (CER) Set by hardware, cleared by writing a 1 to this bit Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 917 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) 26.2.62 ERRSRCID-- Error Source Identification Register (Virtual Root Port--B0:D17:F0) Address Offset: 134h Default Value: 00000000h Bit 31:16 15:0 26.2.63 Fatal/Non-Fatal Error Source ID (EFSID) Requester ID of the source when a Fatal or Non-Fatal error is received Correctable Error Source ID (ECSID) Requester ID of the source when a correctable error is received ACSCAPHDR--Access Control Services Extended Capabilities Header (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Bit Attribute: Size: RO 32 bits Description 31:20 Next Capability Offset (NCO):R/WL A value of 000h indicates that this is the last capability 19i:16 Capability Version (CV):RO Indicates the version of the Capability structure present. 15:0 Extended Capability ID (EXCAPID): RO Identifies the function as Access control services capable ACSCAP-- Access Control Services Capability Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 13Ch Default Value: 005Fh Bit 15:8 918 RO 32 bits Description Address Offset: 138-13Bh Default Value: 0001000Dh 26.2.64 Attribute: Size: Attribute: Size: RO 16 bits Description Egress Control Vector Size (ECVS) Indicates the number of bits in the Egress Control Vector. This is set to 00h as the ACS P2P Egress Control (ACSP2PEC) bit 5 in this register is 0b 7 Reserved - 6 ACS Direct Translated P2P (T) (ACSDTP2P) Indicates that the component does implement ACS Direct Translated P2P 5 ACS P2P Egress Control (E) (ACSP2PEC) Hardwired to 0, this component does not implement ACS P2P Egress Control. 4 ACS Upstream Forwarding U (ACSUF) Indicates that the component implements ACS Upstream Forwarding 3 xACS P2P Completion Redirect (C) (ACSP2PRR) Indicates the component implements ACS P2P Completion redirect. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) Bit 26.2.65 Description 2 ACS P2P Request Redirect (R) (ACSP2PRR) Indicates that the component implements ACS P2P Request redirect. 1 ACS Translation Blocking (B) (ACSTB) Indicates that the component implements ACS Translation Blocking. 0 ACS Source Validation (V) (ACSSV) Indicates the component implements ACS Source Validation. ACSCAP--Access Control Services Capability Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 13E-13Fh Default Value: 0000h Bit 15:7 26.2.66 Attribute: Size: RO, R/W 16 bits Description Reserved - RO, hardwired to 00h 6 ACS Direct Translated P2P Enable (T) (ACSDTP2PE) -- R/W. When set, overrides the ACS P2P request Redirect and ACS P2P Egress Control mechanisms with P2P memory requests whose Address Translation (AT) field indicates a Translated Address Note: This bit is ignored if ACS Translation blocking is enabled. 5 ACS P2P Egress Control (E) (ACSP2PEC) -- RO. Hardwired to 0, this component does not implement ACS P2P Egress Control. 4 ACS Upstream Forwarding Enable U (ACSUFE) -- R/W. When set, the port forwards upstream any Request or Completion TLPs it receives that were redirected upstream by a component lower in the hierarchy. Note the U bit only applies to upstream TLPS arriving at a downstream port, and whose normal routing targets the same downstream port. 3 ACS P2P Completion Redirect Enable (C) (ACSP2PCRE) -- R/W. Determines when the component redirects peer-to-peer completions upstream; applicable only to Read Completions who relaxed ordering attribute is clear. 2 ACS P2P Request Redirect Enable (R) (ACSP2PRRE) -- R/W. This bit determines when the component redirects peer-to-peer requests upstream. 1 ACS Translation Blocking Enable (B) (ACSTBE) -- R/W. When set, the port blocks all upstream memory requests whose address translation (AT) field is not set to the default value. 0 ACS Source Validation Enable(V) (ACSSVE) -- R/W. When set, the port validates the bus number from the Requester ID of upstream requests against the secondary/subordinate bus number. ERRUNCDETMSK--Uncorrectable Error Detect Mask Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port--BN+1:D8:F0) Address Offset: 140h-143h Default Value: 00000000h Bit 31:25 Attribute: Size: R/WC, RO 32 bits Description Reserved 24 AtomicOp Egress Blocked Error Detect Mask (AEBEDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled 23 MC Blocked TLP Error Detect Mask (MCEDM) -- RO 0 = Detection and logging enabled Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 919 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) Bit 22 Uncorrectable Internal Error Detect Mask (UIEDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled 21 ACS Violation Error Detect Mask (ACSEDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled 20 Unsupported Request Error Detect Mask (UREDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled 19 ECRC Check Error Mask (ECRCEDM) -- Not supported RO - hardwired to 0 18 Malformed TLP Error Detect Mask (MTLPEDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled 17 Receiver Overflow Error Detect Mask (ROEDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled 16 Unexpected Completion Error Detect Mask (UCEDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled 15 Completer Abort Error Detect Mask (CAEDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled 14 Completion Timeout Error Detect Mask (CTEDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled 13 Flow Control Error Detect Mask (FCEDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled 12 Poisoned TLP Error Detect Mask (PTLPEDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled 11-6 Reserved 5 Surprise Link Down Error Detect Mask (SLDEDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled 4 Data Link Protocol Error Detect Mask (DLPEDM) -- R/WS 0 = Detection and logging enabled 1 = Detection and logging disabled 3-0 920 Description Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) 26.2.67 ERRCORDETMSK--Correctable Error Detect Mask Register (Virtual Root Port--B0:D17:F0, Virtual Switch Port-- BN+1:D8:F0) Address Offset: 144h-147h Default Value: 0000E000h Attribute: Size: R/WO, RO 32 bits When set, the corresponding error in the CES register is masked, and the logged error will cause no action. When cleared, the corresponding error is enabled. Bit 31:16 Reserved 15 Header Log Overflow Error Mask (HLOEM) R/WO Mask for Header Log Overflow 14 Correctable Internal Error Mask (CIEM) R/WO. Mask for Correctable Internal Error 13 Advisory Non-Fatal Error Mask (ANFEM) -- R/WO. 0 = Does not mask Advisory Non-Fatal errors. 1 = Masks Advisory Non-Fatal errors from (a) signaling ERR_COR to the device control register and (b) updating the Uncorrectable Error Status register. This register is set by default to enable compatibility with software that does not comprehend RoleBased Error Reporting. Note: The correctable error detected bit in device status register is set whenever the Advisory Non-Fatal error is detected, independent of this mask bit. 12 11:9 Replay Timer Timeout Mask (RTT) -- R/WO. Mask for replay timer timeout. Reserved 8 Replay Number Rollover Mask (RNR) -- R/WO. Mask for replay number rollover. 7 Bad DLLP Mask (BD) -- R/WO. Mask for bad DLLP reception. 6 Bad TLP Mask (BT) -- R/WO. Mask for bad TLP reception. 5:1 0 26.2.68 Description Reserved Receiver Error Mask (RE) -- R/WO. Mask for receiver errors. ROOTERRDETMSK--Root Error Detect Mask Register (Virtual Root Port--B0:D17:F0) Address Offset: 148h-149h Default Value: 0000E000h Bit 31:3 Attribute: Size: R/WO, RO 32 bits Description Reserved 2 Received Fatal Message Detect Mask (RFMDM)-- R/WO Masks detection and logging of Fatal Messages 1 Received Non-Fatal Message Detect Mask (RNFMDM)- R/WO Masks detecting and logging of non-Fatal messages 0 Received Correctable Error Detect Mask (RCEMDM) -- R/WO. Masks detection and logging of correctable messages Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 921 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers (SRV/WS SKUs Only) 922 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27 Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.1 IDF SMBus Registers 27.1.1 SMBus Function Configuration Space Registers Table 27-2. SMBus PCI Function 3,4,5 Configuration Map Offset Mnemonic 00h-01h VID Register Name Default Attributes Vendor Identification 8086 RO Device Identification See register description RO 02h-03h DID 04h-05h PCICMD PCI Command 0000h R/W, RO 06h-07h PCISTS PCI Status 0280h RO See register description RO 08h RID 09h PI 0Ah SCC 0Bh 0Ch Revision Identification Programming Interface 00h RO Sub Class Code 05h RO BCC Base Class Code 0Ch RO CLS Cacheline Size 00h R/W 0Eh HDR 10h SMBMBAR0 20h-23h SMBIOBAR 2Ch-2Dh SVID 2Eh-2Fh SID Header Type Memory Base Address Register SMBus IO BAR 80h RO 0000h R/W 00000001h R/W, RO Subsystem Vendor Identification 0000h RO Subsystem Identification 0000h R/WO 34h CAPPTR Capabilities Pointer 90h RO 3Ch INT_LN Interrupt Line 00h R/W 3Dh INT_PN Interrupt Pin See register description RO 40h HOSTC 64-67h HSTTCTL 7C-7Fh SDWMPSCTL 80-83h SMBMODE E4-E5h DEVCLKGCTL E6-E7h SBDEVCLKGCT L 00h R/W Host Timing Control Host Configuration 08000000h R/WS Shadowed Max Payload Size Control 00000000h R/W SMbus Mode Control 00000000h R/WS, RO Device Clock Gate Control 0010h R/W Sideband Device Clock Gate Control 0010h R/W E8-E9h PLKCTL FC-FFh CFGAGTERR Configuration Agent Error 100-103h ARICAPHDR Alternative Routing-ID Extended Capability Header 104-105h ARICAP 106-107 ARICTL 110-113h ERRUNCSTS 114-117h ERRUNCDETMS K Personality Lock Key Control 0000h R/W 00000000h R/WS 000100Eh RO, R/W Alternative Routing_ID Interpretation Capability 0400h 0500h 0600h R/W, RO Alternative Routing-ID Interpretation Control 0000h RO Uncorrectable Error Status 00000000h RO, R/W Uncorrectable Error Detect Mask 00000000h RO, R/WS Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 923 Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.1.2 PCI Standard Header Registers This section describes the PCI Configuration Space registers that make up the standard Type 1 header for PCI to PCI Bridges. Some information from the specification is repeated here as an aid to the reader or to describe implementation choice. Please refer to the PCI Express(R) Base Specification 2.0, PCI-to-PCI Bridge Architecture Specification and PCI Local Bus Specification for the full register descriptions and additional information regarding their operation. 27.1.2.1 Vendor ID Register (VID) VID Bus: X Bus: X Bus: X 27.1.2.2 Device: 0 Device: 0 Device: 0 Bit Attr Default 15:0 RO 8086h Offset: 00h; Offset: 00h; Offset: 00h; Description Vendor ID (VID): This field identifies Intel as the manufacturer of the device. Device ID Register (DID) DID Bus: X Bus: X Bus: X 27.1.2.3 Function: 3 Function: 4 Function: 5 Device: 0 Device: 0 Device: 0 Function: 3 Function: 4 Function: 5 Offset: 02h; Offset: 02h; Offset: 02h; Bit Attr Default Description 15:0 RO-V 0000h Device ID -- RO. This is a 16-bit value assigned to the PCH IDF SMBus controller. Refer to the Intel(R) C600 Series Chipset Specification Update for the value of the Device ID Register. PCI Command Register (PCICMD) PCICMD Bus: X Bus: X Bus: X Device: 0 Device: 0 Device: 0 Bit Attr Default 15: 11 RV 00h 10 R/W 0b Function: 3 Function: 4 Function: 5 Offset: 04h; Offset: 04h; Offset: 04h; Description Reserved Interrupt Disable (Nixed): This bit controls the ability of the PCI-Express Function to generate INTx interrupt message. When set, functions are prevented from asserting INTx interrupt messages. Any INTx emulation interrupts already asserted by the function must be deserted when this bit is set by generating a Deassert_INTx message(s). This bit has no effect on interrupts that pass through the port from the secondary side of root ports, switch ports, and bridges. 9 924 RO 0b Fast Back-to-back enable (FBE): Not applicable to PCI-Express. Hardwired to 0. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) PCICMD Bus: X Bus: X Bus: X Bit 8 Device: 0 Device: 0 Device: 0 Attr R/W Function: 3 Function: 4 Function: 5 Offset: 04h; Offset: 04h; Offset: 04h; Default 0b Description SERR# Enable (SEE): When set, this bit enables reporting of Non-Fatal and Fatal errors detected by the Function of the Root Complex. For Type 1 Configuration Space headers, this bit controls transmission by the primary interface of ERR_NONFATAL and ERR_FATAL error messages forwarded from the secondary interface. ERR_COR messages are not affected by this bit. Note: Errors are reported when enabled either through this bit or through the PCI Express-specific bits in the Device Control Register ("Device Control Register (DEVCTL)" on page 931). 7 RO 0b Wait Cycle Control (WCC): Not applicable to PCI-Express. Hardwired to 0. 6 R/W 0b Parity Error Response Enable (PERE): This bit controls the setting of the master data parity error bit in the Status Register ("PCI Status Register (PCISTS)" on page 926) in response to a parity error received on the PCI Express interface (poisoned TLP). 5 RO 0b VGA Palette Snoop Enable (VGA_PSE): Not applicable to PCI-Express. Hardwired to 0. 4 RO 0b Memory Write and Invalidate Enable (MWIE): Not applicable to PCI-Express. Hardwired to 0. 3 RO 0b Special Cycle Enable (SCE): Not applicable to PCI-Express. Hardwired to 0. 2 R/W 0b Bus Master Enable (BME): This bit controls the ability of the Function to issue Memory and I/O read or write requests, and the ability of Root or Switch port to forward memory and I/O read or write requests in the upstream direction. When this bit is 0b, memory and I/O requests received at the root port or downstream side of a switch port (secondary side) must be handled as an Unsupported Request (UR). For Non-posted requests, a completion with UR completion status must be returned The forwarding of requests other than memory or I/O requests is not controlled by this bit. Note: 1 0 R/W R/W MSI interrupts are inband memory writes and are blocked when this bit is 0b. 0b Memory Space Enable (MSE): This bit controls the function's response to Memory Space accesses. When this bit is 0b, the function will handle memory transactions targeting the Function as an Unsupported request (UR). For Type 1 Configuration Space headers, this bit controls the primary side response to memory space accesses targeting the secondary side. When this bit is 0b, every memory transaction targeting a secondary interface is handled as an Unsupported Request (UR). For Non-posted requests, a completion with UR completion status must be returned. 0b I/O Space Enable (IOSE): This bit controls the function's response to IO Space accesses. When this bit is 0b, the function will handle memory transactions targeting the Function as an Unsupported request (UR). For Type 1 Configuration Space headers, this bit controls the primary side response to IO Space accesses targeting the secondary side. When this bit is 0b, every memory transaction targeting a secondary interface is handled as an Unsupported Request (UR). For Non-posted requests, a completion with UR completion status must be returned. This register controls how the device behaves on the primary interface (PCI Express). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 925 Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.1.2.4 PCI Status Register (PCISTS) PCISTS Bus: X Bus: X Bus: X Bit Attr Function: 3 Function: 4 Function: 5 Offset: 06h; Offset: 06h; Offset: 06h; Default Description 15 R/W1C 0b Detected Parity Error (DPE): This bit is set when a poisoned TLP is received from PCI Express. This bit is set even when the parity error response enable bit (bit[6] of the PCICMD Register-- "PCI Command Register (PCICMD)" on page 924) is not set. On Type 1 configuration header functions, the bit is set when the poisoned TLP is received on the primary side. 14 R/W1C 0b Signaled System Error (SSE): This bit is set when ERR_FATAL or ERR_NONFATAL messages are sent to the root complex and the SERR enable bit in the PCICMD Register ("PCI Command Register (PCICMD)" on page 924) is set. 13 RO 0b Received Master Abort (RMA): This bit is set when the requester receives a completion with an UR completion status. On Type 1 configuration header functions, the bit is set when a UR completions status is received on the primary side. 12 RO 0b Received Target Abort (RTA): This bit is set when a requester receives a CA completions status. On Type 1 configuration header functions, the bit is set when a "Completer Abort" is received on the primary side. 11 R/W1C 0b Signaled Target Abort (STA): This bit is set when the switch generates a completion packet with Completer Abort (CA) status is generated by its primary side. 10:9 RO 00b DEVSEL# Timing (DVT): These bits have no meaning on PCI Express. Fast decode timing is reported. 8 R/W1C 0b Master Data Parity Error Detected (MDPD): This bit is set by a requester (primary side for type1 configuration header functions) if the parity error response enable bit (PERE) in the Command Register ("PCI Command Register (PCICMD)" on page 924) is set and either of the following two conditions occur: * Requester receives a completion marked poisoned. * Requester poisons a write requests. If the parity error bit is 0b, this bit is never set. 7 RO 0b Fast Back-to-Back Capable (FBC): This bit has no meaning on PCI Express. 6 RV 0b Reserved 5 RO 0b 66 MHz Capable (C66): This bit has no meaning on PCI Express. 1b Capabilities List Enable (CAPE): This bit indicates the presence of an Extended capabilities list items. Offset 34H indicates the offset for the first entry in the linked list of capabilities. All PCI Express* Functions are required to have a PCI Express* Capability Structure. So this bit must be hardwired to 1b. 4 926 Device: 0 Device: 0 Device: 0 RO 3 RO-V 0b Interrupt Status (INTS): When set, this bit indicates that an INTx emulation interrupt is pending internally in this function. For Type 1 configuration header functions, forwarded INTx messages are not reflected in this bit. unless the INTx messages is being generated from the Type 1 configuration header function. 2:0 RV 0h Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.1.2.5 Revision ID Register (RID) RID Bus: X Bus: X Bus: X 27.1.2.6 Offset: 08h; Offset: 08h; Offset: 08h; Attr Default Description 7:0 ROS-V 00h Revision ID -- RO. Refer to the Intel(R) C600 Series Chipset Specification Update for the value of the Revision ID Register. Class Code Register (CC) Device: 0 Device: 0 Device: 0 Function: 3 Function: 4 Function: 5 Offset: 09h; Offset: 09h; Offset: 09h; Bit Attr Default 23:16 RO 0Ch Base Class (BC): The value of 0Ch indicates that this is a serial bus controller device. 15:8 RO 05h Sub-Class (SC): This 8-bit value indicates that this device is a SMBus Controller. 7:0 RO 00h Register-Level Programming Interface (RLPI): Description Cacheline Size Register (CLS) CLS Bus: X Bus: X Bus: X 27.1.2.8 Function: 3 Function: 4 Function: 5 Bit CC Bus: X Bus: X Bus: X 27.1.2.7 Device: 0 Device: 0 Device: 0 Device: 0 Device: 0 Device: 0 Function: 3 Function: 4 Function: 5 Bit Attr Default 7:0 R/W 00h Offset: 0Ch; Offset: 0Ch; Offset: 0Ch; Description Cache Line Size (CLS): These bits specify the system cache-line size in units of DWords. This field is implemented by PCI Express* devices but has no effect on device behavior. Header Type Register (HDR) HDR Bus: X Bus: X Bus: X Device: 0 Device: 0 Device: 0 Bit Attr Default 7 RO 1b 6:0 RO 00h Function: 3 Function: 4 Function: 5 Offset: 0Eh; Offset: 0Eh; Offset: 0Eh; Description Multi-function device (MFD): Reserved as 1 to indicate that the switch is a multi-function device. Header Type (HTYPE): These bits define the layout of addresses 10h through 3Fh in the configuration space. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 927 Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.1.2.9 SMBUS Memory Base Address Register (SMBMBAR) SMBMBAR Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 27.1.2.10 Function: 3 Function: 4 Function: 5 Bit Attr Default 31:12 R/W 0h Memory Base Address (MBA): 11:4 RO 0h Memory Size (MSIZE): Hardwired to 0h. 3 RO 0b Prefetchable Memory (PFMEM): Not prefetchable memory space. 2:1 RO 00b 0 RO 0b Bit Memory Type (MTYPE): Indicates 32-bit address space. Memory Space Indicator (MSI): 0b: Memory space 1b: IO space Attr Function: 3 Function: 4 Function: 5 Offset: 20h; Offset: 20h; Offset: 20h; Default Description 31:16 RV 0h Reserved. 15:5 R/W 0h IO Base Address (IOBA): 4:1 RV 0h Reserved. 1b IO Space Indicator (IOSI): 0b: Memory space 1b: IO space 0 RO Subsystem Vendor ID Register (SVID) SVID Bus: X Bus: X Bus: X 928 Description SMBUS IO BAR Register (SMBIOBAR) SMBIOBAR Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 27.1.2.11 Offset: 10h; Offset: 10h; Offset: 10h; Device: 0 Device: 0 Device: 0 Function: 3 Function: 4 Function: 5 Offset: 2Ch; Offset: 2Ch; Offset: 2Ch; Bit Attr Default Description 15:0 R/WL PRST 8086h Subsystem Vendor ID (SVID): This field identifies Intel as the manufacturer of the device. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.1.2.12 Subsystem ID Register (SID) SID Bus: X Bus: X Bus: X 27.1.2.13 Device: 0 Device: 0 Device: 0 Function: 3 Function: 4 Function: 5 Bit Attr Default Description 15:0 R/WL PRST 0000h Subsystem ID (SID): This field identifies the particular function as allocated by Intel. Capabilities Pointer Register (CAPPTR) CAPPTR Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 27.1.2.14 Attr Default 7:0 RO 90h Offset: 34h; Offset: 34h; Offset: 34h; Description Capabilities Pointer (CPTR): Contains the offset of the first item in the list of capabilities. (EXPCAPLST) Interrupt Line Register (INTL) Device: 0 Device: 0 Device: 0 Function: 3 Function: 4 Function: 5 Offset: 3Ch; Offset: 3Ch; Offset: 3Ch; Bit Attr Default Description 7:0 R/W 00h Interrupt Line (INTL): This register is used to communicate interrupt line routing information. The device itself does not use this value, rather it is used by device drivers and operating systems. Interrupt Pin Register (INTP) INTP Bus: X Bus: X Bus: X Bit 7:0 27.1.3 Function: 3 Function: 4 Function: 5 Bit INTL Bus: X Bus: X Bus: X 27.1.2.15 Offset: 2Eh; Offset: 2Eh; Offset: 2Eh; Device: 0 Device: 0 Device: 0 Attr RO Function: 3 Function: 4 Function: 5 Offset: 3Dh; Offset: 3Dh; Offset: 3Dh; Default Func ? 3: 03h 4: 03h 5: 04h Description Interrupt Pin (INTP): This register tells which interrupt pin the function uses. 01h: Generate INTA 02h: Generate INTB 03h: Generate INTC 04h: Generate INTD Others: Reserved PCI Express* Capability Structure This section describes the PCI Configuration Space registers that make up the PCI Express* Capability Structure. These registers are first in the capabilities list, so they are discovered through the Capabilities Pointer Register (CAPPTR). Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 929 Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) Some information from the specification is repeated here as an aid to the reader or to describe implementation choice. Please refer to the PCI Express(R) Base Specification 2.0 for the full register descriptions and additional information regarding their operation. 27.1.3.1 PCI Express* Capability List Register (EXPCAPLST) EXPCAPLST Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 27.1.3.2 Function: 3 Function: 4 Function: 5 Offset: 90h; Offset: 90h; Offset: 90h; Bit Attr Default Description 15:8 R/WL CCh Next Pointer (NP): Contains the offset of the next item in the capabilities list. (PMCAPLST) 7:0 RO 10h Capability ID (CAPID): Identifies the function as PCI Express* capable. PCI Express* Capabilities Register (EXPCAP) EXPCAP Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 Function: 3 Function: 4 Function: 5 Offset: 92h; Offset: 92h; Offset: 92h; Bit Attr Default 15:14 RV 0h Reserved Interrupt Message Number (IMN): This field indicates the interrupt message number that is generated from the PCI Express* port. When there is more than one MSI interrupt number, this register is required to contain the offset between the base Message Data and the MSI Message that is generated when the status bits in the slot status register or root port status registers are set. The chipset us required to update this field if the number of MSI messages change. 13:9 RO 0h 8 RO 0 Description Slot Implemented (SI): Indicates the PCI Express* link associated with this port is connected to a slot. Indicates no slot is connected to this port. 7:4 RO 0h Device/Port Type (DT): 0h: PCI Express* Endpoint 4h: Root Port of a PCIe Root Complex 5h: Upstream port of a PCIe switch. 6h: Downstream port of a PCIe switch. 3:0 RO 2h Version Number (VN): These bits indicate the version number of the PCI Express capability structure. This register stores the version number of the capability item and other base information contained in the capability structure. 27.1.3.3 Device Capabilities Register (DEVCAP) DEVCAP Bus: X Bus: X Bus: X 930 Device: 0 Device: 0 Device: 0 Function: 3 Function: 4 Function: 5 Bit Attr Default 31:29 RV 0h Offset: 94h; Offset: 94h; Offset: 94h; Description Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) DEVCAP Bus: X Bus: X Bus: X Bit 28 27:26 27.1.3.4 Device: 0 Device: 0 Device: 0 Attr Function: 3 Function: 4 Function: 5 Offset: 94h; Offset: 94h; Offset: 94h; Default RO 0b RO Description Function Level Reset Capability (FLR): This field when set indicates this function supports optional function Level Reset mechanism. This field applies to Endpoints only. For all other function types this bit must be hardwired to 0b. 00b Captured Slot Power Limit Scale (CSPLS): In combination with the Slot Power Limit value (bits[25:18], this field specifies the upper limit of the power supplied by slot. The power limit (in Watts) is calculated by multiplying the value in this field by the value in the Slot Power Limit Value field. This value is set by the Set_Slot_Power_Limit message. Captured Slot Power Limit Value (CSPLV): In combination with the Slot Power Limit Scale value (bits[27:26]), this field specifies the upper limit of the power supplied by slot. The power limit (in Watts) is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field. This value is set by the Set_Slot_Power_Limit message. 25:18 RO 0h 17:16 RV 00b Reserved 15 RO 1b Role-Based Error Reporting (RBER): 14:12 RO 0h Undefined 11:9 RO 000b Endpoint L1 Acceptable Latency (EPL1AL): The least latency possible out of L1 is supported. 8:6 RO 000b Endpoint L0s Acceptable Latency (EPL0AL): The least latency possible out of L0s is supported. 5 RO 0b 4:3 RO 00b 2:0 RO 001b Extended Tag Field Supported (ETFG): Only a 5-bit tag is supported. Phantom Functions Supported (PFS): Not supported Supported Max Payload sizes (MPSS): 256-byte packets are the maximum supported. Device Control Register (DEVCTL) DEVCTL Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 Function: 3 Function: 4 Function: 5 Bit Attr Default 15 RV 0b 14:12 RO 000b Offset: 98h; Offset: 98h; Offset: 98h; Description Reserved. Max_Read_Request_Size (MRRS): This field sets the maximum Read Requests size for the function as a requester. The Function must not generate read requests with size exceeding the set value. 000b: 128 bytes maximum Read Request size 001b: 256 bytes maximum Read Request size 010b: 512 bytes maximum Read Request size 011b: 1024 bytes maximum Read Request size 100b: 2048 bytes maximum Read Request size 101b: 4096 bytes maximum Read Request size Others: Reserved Functions that do not generate Read Requests larger than 128B and functions that do not generate Read Requests on their own behalf are permitted to implement this field as Read Only (RO) with a value of 000b. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 931 Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) DEVCTL Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 Bit Default Offset: 98h; Offset: 98h; Offset: 98h; Description 11 RO 0b Enable No Snoop (ENOSNP): If this bit this is set, the function is permitted to set the No Snoop bit in the Requester attributes of transactions it initiates that do not require hardware enforced cache coherency. This bit is permitted to be hardwired to 0b if a function would never set the No Snoop attribute in transactions it initiates. 10 RO 0b Auxiliary Power PM Enable (AUXPME): Not supported 9 RO 0b Phantom Function Enable (PFE): When set, this bit enables a function to user unclaimed functions as phantom functions to extend the number of outstanding transaction identifiers. Functions that do not implement this capability hardware this bit to 0b. 8 RO 0b Extended Tag Field Enable (ETFE): When set, this bit enables a function to use an 8-bit tag field as a Requester. Functions that do not implement this capability hardwire this bit to 0b. 000b Maximum Payload Size (MPS): This field sets maximum TLP payload size for the function. As a receiver, the function must handle TLPs as larger as the set value. As a Transmitter, the function must not generate TLPs exceeding the set value. 000b: 128 bytes maximum payload size 001b: 256 bytes maximum payload size 010b: 512 bytes maximum payload size (Unsupported) 011b: 1024 bytes maximum payload size (Unsupported) 100b: 2048 bytes maximum payload size (Unsupported) 101b: 4096 bytes maximum payload size (Unsupported) Others: Reserved 7:5 932 Attr Function: 3 Function: 4 Function: 5 R/W 4 RO 0b Enable Relaxed Ordering (ENRO): When set, the function is permitted to set the relaxed ordering bit in the attribute field of transactions it initiates that do not require strong write ordering. A function is permitted to hardwire this bit to 0b if it never sets the Relaxed ordering attribute in transactions it initiates as a requester. 3 R/W 0b Unsupported Request Reporting Enable (URRE): This bit controls the enabling of ERR_CORR, ERR_NONFATAL or ERR_FATAL messages on PCI Express for reporting "Unsupported Request" errors. 2 R/W 0b Fatal Error Reporting Enable (FERE): When this bit is set, generation of the ERR_FATAL message is enabled. 1 R/W 0b NonFatal Error Reporting Enable (NFERE): When this bit is set, generation of the ERR_NONFATAL message is enabled. 0 R/W 0b Correctable Error Reporting Enable (CERE): When this bit is set, generation of the ERR_CORR message is enabled. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.1.3.5 Device Status Register (DEVSTS) DEVSTS Bus: X Bus: X Bus: X 27.1.3.6 Device: 0 Device: 0 Device: 0 Function: 3 Function: 4 Function: 5 Bit Attr Default 15:6 RV 000h Offset: 9Ah; Offset: 9Ah; Offset: 9Ah; Description Reserved Zero: Software must always write a 0 to these bits. 5 RO 0b Transactions Pending (TP): When set, this bit indicates that the function has issued Non-Posted REquests that have not been completed. For Root or Switch port, it applies to Non-Posted Requests the port has issued on its own behalf (Port's Request ID). A function reports this bit cleared only when all outstanding Non-Posted Requests have completed. Functions that do not issue Non-Posted requests on their own behalf hardwire this bit to 0b. 4 RO 0b Auxiliary Power Detected (APD): Auxiliary Power is not supported. 3 R/W1C 0b Unsupported Request Detected (URD): This bit indicates that this function received an unsupported request from PCI Express link. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. 2 R/W1C 0b Fatal Error Detected (FED): This bit indicates that this function has detected a Fatal error. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. 1 R/W1C 0b Non-Fatal Error Detected (NFED): This bit indicates that this function has detected a Non-Fatal error. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. 0 R/W1C 0b Correctable Error Detected (CED): This bit indicates that this function has detected a Correctable error. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. Link Capabilities Register (LINKCAP) LINKCAP Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 Function: 3 Function: 4 Function: 5 Bit Attr Default 31:24 RO 00h Offset: 9Ch; Offset: 9Ch; Offset: 9Ch; Description Port Number (PN): This field indicates the PCI Express* port number assigned to this link. Note: Applicable to the downstream ports only. Read-only for upstream port. 23:22 RV 00h 21 RO 0b Reserved 20 RO 0b Data Link Layer Active Error Reporting Capable (DLLERC): 19 RO 0b Surprise Link Down Error Reporting Capable (SLDERC): 18 RO 0b Clock Power Management Capable (CPMC): Link Bandwidth Notification Capability (LBNC): Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 933 Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) LINKCAP Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 Bit 17:15 14:12 11:10 9:4 3:0 934 Attr RO RO RO RO RO Function: 3 Function: 4 Function: 5 Offset: 9Ch; Offset: 9Ch; Offset: 9Ch; Default Description 000b L1 Exit Latency(L1EL): This field indicates the L1 exit latency for the given PCI-Express Link. It indicates the length of time this port requires to complete transition from L1 to L0. 000: Less than 1us 001: 1 us to less than 2 us 010: 2 us to less than 4 us 011: 4 us to less than 8 us 100: 8 us to less than 16 us 101: 16 us to less than 32 us 110: 32 us to less than 64 us 111: More than 64 us 000b L0s Exit Latency(L0sEL): This field indicates the L0s exit latency for the given PCI Express Link. It indicates the length of time this port requires to complete transition from L0s to L0. 000b: Less than 64 ns 001b: 64 ns to less than 128 ns 010b: 128 ns to less than 256 ns 011b: 256 ns to less than 1 us 101b: 1 us to less than 2 us 110b: 2 us to less than 4 us 111b: More than 4 us 11b ASPM Support (ASPMSUP): This field indicates the level of ASPM supported on the given PCI Express* Link. 00b: Reserved 01b: L0s Entry Supported 10b: Reserved 11b: L0s and L1 Supported 01h Maximum Link Width (MLW): This field indicates the maximum link width implemented by the given PCI Express* Link. 00h: Reserved 01h: x1 02h: x2 04h: x4 08h: x8 10h: x16 20h: x32 (Unsupported) Others Reserved 1h Maximum Link Speed (MLS): This field indicates the supported link speed(s) for the associated port. 0001b: 2.5 Gb/s link speed is supported 0010b: 5.0 Gb/s and 2.5 Gb/s link speed supported Others: Reserved. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.1.3.7 Link Control Register (LINKCTL) LINKCTL Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 Function: 3 Function: 4 Function: 5 Offset: A0h; Offset: A0h; Offset: A0h; Bit Attr Default 15:12 RV 0h Reserved 0b Link Autonomous Bandwidth Interrupt Enable (LABIE): When Set, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. Functions that do not implement the Link Bandwidth Notification Capability must hardwire this bit to 0b. 0b Link Bandwidth Management Interrupt Enable (LBMIE): When set, this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. Functions that do not implement the Link Bandwidth Notification Capability must hardwire this bit to 0b. 11 10 RO RO Description 9 RO 0b Hardware Autonomous Width Disable (HAWD): When set, this bit disables hardware from changing the Link Width for reasons other than attempting to correct unreliable Link operation by reducing Link width. Components that do not implement the ability to autonomously change link width are permitted to hardwire this bit to 0b. 8 RO 0b Enable Clock Power Management (ECPM): Not Applicable. 0b Extended Synch (ES): When set, this bit forces extended transmission of 4096 FTS ordered sets in FTS and an extra 1024 TS1 at exit from L1 prior to entering L0. This mode provides external devices monitoring the link time to achieve bit and symbol lock before the link enters L0 state and resumes communication. Default value for this bit is 0. 1b Common Clock Configuration (CCCFG): When set, this bit indicates that this component and the component at the opposite end of this link are operating with distributed common reference clocks. A value of 0b indicates that this component and the component at the opposite end of this link are operating with asynchronous reference clock. After changing the value in this bit in bother components on a link, software must trigger the link to retrain by writing a 1b to the Retrain Link bit of the Downstream Port. 0b Retrain Link (RL): When set, this bit initiates link retraining by directing the physical layer LTSSM to recovery state. If the LTSSM is already in REcovery or configuration, re-entering Recovery is permitted but not required. Reads of this bit always return 0b. This is used by the downstream ports only. For the upstream port, it is Read-only. 7 6 5 4 R/W R/W RO RO 0b Link Disable (LD): When set, this bit disables the link by directing the LTSSM to the disabled state when set. This bit is reversed on Endpoints, for the given PCI Express* port. This is used by the downstream ports only. For the upstream port, it is Read-only. 3 RO 0b 2 RV 0b Read Completion Boundary (RCB): This bit indicates the RCB value for Root Port, Endpoints and Bridges. 0b: 64 byte 1b: 128 byte Not applicable to switch ports - must be hardwire the bit to 0b. 1:0 R/W 00b Reserved ASPM Control (ASPMCTL): This field controls the level of ASPM supported on a given PCI Express* Link. 00b: Disabled 01b: L0s Entry Enabled 10b: L1 Entry Enabled 11b: L0s and L1 Entry Enabled Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 935 Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.1.3.8 Link Status Register (LINKSTS) LINKSTS Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 Bit 15 14 Attr RO RO Function: 3 Function: 4 Function: 5 Offset: A2h; Offset: A2h; Offset: A2h; Default Description 0b Link Autonomous Bandwidth Status (LABS): This bit is set by hardware to indicate that hardwire has autonomously changes link or width, without the port transitioning through DL_Down status, for reason other than to attempt to correct unreliable link operation. This bit is not applicable and is reserved for endpoints, PCI Express-to-PCI/PCI-X bridges, and upstream ports of switches. Functions that do not implement the Link Bandwidth Notification Capability must hardwire this bit to 0b. 0b Link Bandwidth Management Status (LBMS): This bit is set by hardware to indicate that either of the following has occurred without the port transitioning through DL_Down status: * A link retraining has completed following a write of 1b to the Retrain link bit. * Hardware has changed link speed of width to attempt to correct unreliable link operation, either through an LTSSM timeout or a higher level process. This bit is not applicable and is reserved for endpoints, PCI Express-to-PCI/PCI-X bridges, and upstream ports of switches. Functions that do not implement the Link Bandwidth Notification Capability must hardwire this bit to 0b. 13 12 RO 0b Data Link Layer Link Active (DLLLA): This bit indicates the status of the Data Link Control and Management Status Machine. It returns a 1b to indicate the DL_Active state, 0b otherwise. 1b Slot Clock Configuration (SCC): When the X is on a PCI Express connector, this bit indicates whether it is using the same reference clock that is provided at the connector. Indicates independent reference clock Indicates same reference clock. 11 RO 0 Link Training (LT): This bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state, or a 1b was written to the Retrain Link bit but the Link training has not yet begun. Hardware clears this bit when the LTSSM exits the Configuration/Recovery state. This field is not applicable and reserved for the upstream port, and must be hardwired to 0b. 10 RO 0 Undefined: Not applicable 9:4 3:0 936 RO RO RO 1h Negotiated Link Width (NLW): This field indicates the negotiated width of the PCI Express link. 00 0001b: x1 00 0010b: X2 00 0100b: x4 00 1000b: X8 00 1100b: X12--not supported 01 0000b: X16 10 0000b: X32--not supported All other values are reserved. 1h Current Link Speed (CLS): This field indicates the negotiated link speed of the given PCI Express link. 0001b: 2.5 Gb/s PCI Express Link 0010b: 5.0 Gb/s PCI Express Link Others: Reserved The value in this field is undefined when the link is not up. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.1.3.9 Device Capabilities 2 Register (DEVCAP2) DEVCAP2 Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 Function: 3 Function: 4 Function: 5 Bit Attr Default 31:6 RV 0 Offset: B4h; Offset: B4h; Offset: B4h; Description Reserved. 5 RO 0b Alternative RID Interpretation Capable (ARI): This bit is set to 1b when indicating that the switch downstream or root port supports this capability. Must be 0b for all other types of functions. 4 RO 0b Completion Timeout Disable Support (CTDS): A value of 1b indicates support for the completion Timeout Disable Mechanism. Support of completion timeout disable is optional for Root Ports. The port supports completions timeout disable. 0h Completion Timeout Range Supported (CTRS): This field indicates device support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value. This field is applicable only to Root Ports, Endpoints that issue requests on their own behalf, and PCI Express* to PCI/PCI-X Bridges that take ownership of request issues on PCI Express. For all other devices this field is reserved and maybe be hardwired to 0000b. Four time values ranges are defined: Range A: 50 us to 10 ms Range B: 10 ms to 250 ms Range C: 250 ms to 4 s Range D: 4 s to 64 s Bits ares set according to table below to show timeout value ranges supported. 0000b: Completions Timeout programming not supported -- values is fixed by implementation in the range 50us to 50ms. 0001b: Range A 0010b: Range B 0011b: Range A & B 0110b: Range B & C 0111b: Range A, B, & C 1111b: Range A, B, C & D All other values are reserved. 3:0 RO Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 937 Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.1.3.10 Device Control 2 Register (DEVCTL2) DEVCTL2 Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 Bit Attr Default 15:6 RV 0h Reserved. RO 0b 4 RO 0b Completion Timeout Disable (CTD): 1: disable the completions timeout mechanism for all NP tx. 0: completion timeout is enabled for all NP tx 0h Completion Timeout Value (CTV): In devices that support completion timeout programmability, this field allows system software to modify the completion timeout range. The following encodings and corresponding timeout ranges are defined: 0000b: 50 us to 50 ms (16.3 ms - 24.6 ms based on core clk period) 0001b: 50 us to 100 us (61.4 us - 92.4 us based on core clk period) 0010b: 1 ms to 10 ms (2.6 ms - 3.9 ms based on core clk period) 0101b: 16 ms to 55 ms (16.3 ms - 24.6 ms based on core clk period) 0110b: 65 ms to 210 ms (83.8 ms - 126.1 ms based on core clk period) 1001b: 260 ms to 900 ms (335.5 ms - 504.5 ms based on core clk period) 1010b: 1s to 3.5 s (1.3 s - 2.1 s based on core clk period) All others are reserved. 1111b: 256 core clock cycles for SV debug. Note: It is highly recommended that the completion timeout value not be less then 10ms. A small completion timeout value may result in premature completion timeout for slower responding devices. If a greater than 25 ms timeout value is required. RO Device Status 2 Register (DEVSTS2) Function: 3 Function: 4 Function: 5 Bit Attr Default 15:0 RV 0h Offset: BAh; Offset: BAh; Offset: BAh; Description Reserved. Link Capabilities 2 Register (LINKCAP2) LINKCAP2 Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 938 Description 5 DEVSTS2 Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 27.1.3.12 Offset: B8h; Offset: B8h; Offset: B8h; Alternative RID Interpretation Enable (ARIE): When set to 1b, ARI is enabled for the downstream or root ports. Must be 0b for all other types of functions. 3:0 27.1.3.11 Function: 3 Function: 4 Function: 5 Function: 3 Function: 4 Function: 5 Bit Attr Default 15:0 RV 0h Offset: BCh; Offset: BCh; Offset: BCh; Description Reserved. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.1.3.13 Link Control 2 Register (LINKCTL2) LINKCTL2 Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 Function: 3 Function: 4 Function: 5 Offset: C0h; Offset: C0h; Offset: C0h; Bit Attr Default Description 15:13 RV 0h Reserved. 12 RO 0b Compliance De-emphasis (CD): This bit sets the de-emphasis level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. 1b: -3.5 dB 0b: -6 dB When the link is operating at 2.5 Gb/s, the setting of this bit has no effect. 11 RO 0b Compliance SOS (CSOS): When set to 1b, the LTSSM is required to send Skip Ordered Sets periodically in between the (modified) compliance patterns. This bit has no affect on hardware. 10 RO 0b Enter Modified Compliance (EMC): When set to 1b, the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Complinace substate. This bit has no affect on hardware. 9:7 6 5 4 3:0 RO RO RO RO RO 000b Transmit Margin (TM): This field controls the value of the non-deemphasized voltage level at the transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate. 000b: Normal operating range 001b: 800-1200 mV for full swing and 400-700 mV for half-swing 010b-110b: TBD Others: Reserved This field has no affect on hardware. 0b Selectable De-emphasis (SD): When the link is operating at 5 Gb/s speed, this bit selects the level of deemphasis for an upstream component. This bit is not applicable and reserved for Endpoints, PCI Express* to PCI/PCI-X bridges, and upstream ports of switches. 0b Hardware Autonomous Speed Disable (HASD): When set, this bit disables hardware from changing the link speed for device specific reasons other than attempting to correct unreliable link operation by reducing link speed for device-specific reasons other than attempting to correct unreliable link operations by reducing link speed. Initial transition to the highest supported common link speed is not blocked by this bit. 0b Enter Compliance (EC): Software is permitted to force a link to enter compliance mode at the speed indicated in the Target Link Speed field by setting this bit to 1b in both components on a link and then initiating a hot reset on the link. This bit has no affect on hardware. 0h Target Link Speed (TLS): For downstream ports, this field sets an upper limit on link operational speed by restricting the values advertised by the upstream component in its training sequences. 0001b: 2.5 Gb/s Target Link Speed 0010b: 5.0 Gb/s Target Link Speed Others: Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 939 Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.1.3.14 Link Status 2 Register (LINKSTS2) LINKSTS2 Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 Offset: C2h; Offset: C2h; Offset: C2h; Bit Attr Default 15:1 RV 0 Reserved. 0 Current De-emphasis Level (CDL): When the link is operating at 5 Gb/s speed, this bit reflects the level of deemphasis. 1b: -3.5 dB 0b: -6 dB 0 27.1.4 Function: 3 Function: 4 Function: 5 RO Description Power Management Capability Structure This section describes the PCI Configuration Space registers that make up the PCI Power Management Capability Structure. These registers are second in the capabilities list, so they are discovered through the prior PCI Express* Capability List Register (EXPCAPLST). Some information from the specification is repeated here as an aid to the reader or to describe implementation choice. Please refer to the PCI Express(R) Base Specification 2.0 and PCI Bus Power Management Interface Specification for the full register descriptions and additional information regarding their operation. 27.1.4.1 Power Management Capability List Register (PMCAPLST) PMCAPLST Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 940 Function: 3 Function: 4 Function: 5 Offset: CCh; Offset: CCh; Offset: CCh; Bit Attr Default Description 15:8 R/WL D4h Next Pointer (NP): Contains the offset of the next item in the capabilities list. (MSICAPLST) 7:0 RO 01h Capability ID (CAPID): Identifies the function as PCI Power Management capable. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.1.4.2 Power Management Capabilities Register (PMCAP) PMCAP Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 27.1.4.3 Function: 3 Function: 4 Function: 5 Offset: CEh; Offset: CEh; Offset: CEh; Bit Attr Default Description 15:11 RO 19h 10 RO 0b D2 Support (D2S): Not supported 9 RO 0b D1 Support (D1S): Not supported 8:6 RO 000b 5 RO 0b PME_Support (PMES): PME assertion is supported when in D3hot. PME assertion from D3cold is not supported. Auxiliary Current (AC): Auxiliary power is not supported. Device Specific Initialization (DSI): Device-specific initialization is not required when transitioning to D0 from D3hot state. This bit is zero. 4 RV 0b Reserved 3 RO 0b PME Clock (PMECLK): Does not apply to PCI Express. Hard-wired to 0. 2:0 RO 3h Version (VER): PM implementation is compliant with PCI Bus Power Management Interface Specification, Revision 1.2. Power Management Control / Status Register (PMCSR) PMCSR Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 Function: 3 Function: 4 Function: 5 Offset: D0h; Offset: D0h; Offset: D0h; Bit Attr Default 15 R/W1CS 0 14:13 RO 0h Data Scale (DC): Not supported 12:9 RO 0h Data Select (DS): Not supported 8 R/WS 0 7:2 RV 0h Reserved 0h Power State (PS): This field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the supported values is given below: 0h = D0 3h = D3hot If software attempts to write an unsupported, optional state to this field, the write operation must complete normally; however, the data is discarded and no state change occurs. 1:0 R/W-R Description PME Status (PMESTS): PME Enable (PMEEN): Gates assertion of the PME message. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 941 Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.1.5 MSI Capability Structure This section describes the PCI Configuration Space registers that make up the Message Signaled Interrupts Capability Structure. Some information from the specification is repeated here as an aid to the reader or to describe implementation choice. Please refer to the PCI Local Bus Specification for the full register descriptions and additional information regarding their operation. 27.1.5.1 MSI Capability List Register (MSICAPLST) MSICAPLST Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 27.1.5.2 Attr Default Description 15:8 R/WL 0h Next Pointer (NP): Contains the offset of the next item in the capabilities list. A null value is used to indicate that this is the last capability. 7:0 RO 05h Capability ID (CAPID): Identifies the function as MSI capable. MSI Message Control Register (MSICTL) Device: 0 Device: 0 Device: 0 Function: 3 Function: 4 Function: 5 Offset: D6h; Offset: D6h; Offset: D6h; Bit Attr Default 15:8 RV 00h 7 RO 0b Address 64-Bit Capable (AD64C): When set, this bit indicates that the function is capable of generating a 64-bit message address. 6:4 R/W 000b Multiple Message Enable (MMEN): Only one message is supported. These bits are R/W for software compatibility. 3:1 RO 000b Multiple Message Capable (MMC): Only one message is supported. 0 R/W 0b Description Reserved MSI Enable (MSIE): When set, MSI is enabled and traditional interrupt pins are not used to generate interrupts. MSI Message Address Register (MSIADDR) MSIADDR Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 942 Offset: D4h; Offset: D4h; Offset: D4h; Bit MSICTL Bus: X Bus: X Bus: X 27.1.5.3 Function: 3 Function: 4 Function: 5 Function: 3 Function: 4 Function: 5 Bit Attr Default 31:2 R/W 0h 1:0 RV 00b Offset: D8h; Offset: D8h; Offset: D8h; Description Address: Message address specified by the system, always DWORD aligned Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.1.5.4 MSI Message Data Register (MSIDATA) MSIDATA Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 27.1.6 Function: 3 Function: 4 Function: 5 Bit Attr Default 15:0 R/W 0000h Offset: DCh; Offset: DCh; Offset: DCh; Description Data: This 16-bit field is programmed by system software when MSI is enabled. Its content is driven onto the lower word (D[15:0]) of the MSI memory write transaction. Implementation Specific Registers This section describes the PCI Express* Configuration Space registers that are specific to the PCH implementation. These registers are unique to the device and are only discovered by being listed in the Component Specification. 27.1.6.1 Host Configuration Register (HSTCFG) HSTCFG Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 Function: 3 Function: 4 Function: 5 Offset: 40h; Offset: 40h; Offset: 40h; Bit Attr Default Description 7:4 RV 0h Reserved 3 R/W 0h Soft SMBus Reset (SSRESET): When set to 1b, the SMBus state machine and logic in SMBus is reset. The hardware sill reset this bit to 0 when reset operation is completed. 2 R/WS 0h I2C Enable: When set to 1b, the SMBus controller communicates with I2C devices. This will change the formatting of some commands. The controller behaves as an SMBus controller otherwise. 1 RO 0h SMI Enable: When set to 1b, any source of an SMB interrupt will instead be routed to generate an SMI#. This feature is not supported for the SMBus controllers. 0h Host Enable: When set to 1b, the SMBus Host controller interface is enabled to execute commands. The HSTCTL.Interrupt Enable bit needs to be enabled in order for the SMB host Controller to interrupt. Additionally, the SMBus Host controller will not respond to any new requests until all interrupt requests have been cleared. 0 R/WS Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 943 Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.1.6.2 Host Timing Control Register (HSTTCTL) HSTTCTL Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 Bit Attr Function: 3 Function: 4 Function: 5 Offset: 64h; Offset: 64h; Offset: 64h; Default Description THIGH Value: This field determines the time value to added/subtracted to the nominal Thigh timing parameter as defined in the SMB 2.0 spec. 31:24 23:16 R/WS 08h R/WS 00h 00h: -7 clocks (-840 ns) 01h: -6 clocks (-720 ns) ... 07h: -1 clock (-120 ns) 08h: 0 clock (0 ns) 09h: 1 clock (120 ns) ... FFh: 247 clocks (29640 ns) TLOW Value: This field determines the time value to add/subtract to the nominal Thigh timing parameter as defined in the SMB 2.0 spec. Refer to THIGH Value field for defined values. 15:12 R/WS 0h THDSTA Value: This field determines the time value to add/subtract to the nominal Thdsta timing parameter as defined in the SMB 2.0 spec. Fh: -7 clocks (-840 ns) Eh: -6 clocks (-720 ns) ... 9h: -1 clock (-120 ns) 8h: 0 clock (0 ns) 7h: 7 clocks (840 ns) ... 1h: 1 clock (120 ns) 0h: 0 clock (0 ns) 11:8 R/WS 0h TSUSTA Value: This field determines the time value to add/subtract to the nominal Thdsta timing parameter as defined in the SMB 2.0 spec. Refer to THDSTA Value field for defined values. 7:4 R/WS 0h TBUF Value: 3:0 R/WS 0h TTSUSTO Value: This field determines the time value to add/subtract to the nominal Thdsta timing parameter as defined in the SMB 2.0 spec. Refer to THDSTA Value field for defined values. This register affects the SMBus master timing parameters. Values should only be changed when the SMBus is idle. 27.1.6.3 Shadowed Max Payload Size Control Register (SDWMPSCTL) SDWMPSCTL Bus: X Device: Bus: X Device: Bus: X Device: Bus: X Device: 944 0 0 0 0 Function: Function: Function: Function: Bit Attr Default 31:8 RV 0h 3 4 5 6 Offset: 7Ch; (Alias:); (Alias:); (Alias:); Description Reserved Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) SDWMPSCTL Bus: X Device: Bus: X Device: Bus: X Device: Bus: X Device: Bit Attr 0 0 0 0 Function: Function: Function: Function: 3 4 5 6 Offset: 7Ch; (Alias:); (Alias:); (Alias:); Default Description Shadowed Max Payload Size (SMPS): This field is the shadowed copy of the Function 0's MPS register to support ARI Functions. The Multi-function Glue will update this register. Software should not write to this register. Hardware should use this register field instead of the DEVCTL.MPS field as the max payload size. 27.1.6.4 7:5 R/W 0b 000b: 128 bytes maximum payload size 001b: 256 bytes maximum payload size 010b: 512 bytes maximum payload size (Unsupported) 011b: 1024 bytes maximum payload size (Unsupported) 100b: 2048 bytes maximum payload size (Unsupported) 101b: 4096 bytes maximum payload size (Unsupported) Others: Reserved 4:0 RV 0h Reserved. SMBus Mode Control Register (SMBMODE) SMBMODE Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 Function: 3 Function: 4 Function: 5 Bit Attr Default 31:16 RV 0h 15:8 R/WS 00b 7 R/WS 00b Offset: 80h; Offset: 80h; Offset: 80h; Description Reserved Unused0 I2C Operating Frequency Mode (I2COFM): This bit set the operating frequency for the IO buffers when operating in I2C mode. 0b: Standard & Fast Modes 1b: Fast Mode Plus Note: This bit control the ogioi2ccfg signal to the IO buffers. I2C 6 R/WS 00b Mode Disable (I2CMD): This bit when set to 1 disable i2C mode in the IO buffers. 0b: I2C/SMB interface 1b: Cmos interface mode Note: 5 RO This bit control the ogioi2cenb signal to the IO buffers. 0b Slave Auto Clock Stretch Enable (SACSE): Setting this bit to 1b will cause HW to start stretching SMBus clock even if it is not the target of the SMBus transaction. Note: Field has no effect because slave mode not used. Watchdog Timer Read Policy (WTRP): Setting this bit to 1b will select the legacy behavior when reading SMB slave register 3 for the watchdog timer (bit 5 is logically the OR of timer bits 9:5, bits 4:0 mapped to bits 4:0 of the timer. When this bit is 0b, reads to the SMBus slave register 3 returns 3Fh if the watchdog timer is equal or greater than the 6-bit value 3Fh. Note: Field has no effect because slave mode not used. 4 RO 0b 3 RV 0b Reserved 0b Block Write Interrupt Policy (BWIP): Setting this bit to 1b will enable the SMBus host to always generate n+1 interrupts for a block write of n bytes (with e32b disabled). 2 R/WS Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 945 Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) SMBMODE Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 27.1.6.5 Function: 3 Function: 4 Function: 5 Offset: 80h; Offset: 80h; Offset: 80h; Bit Attr Default Description 1 R/WS 0b Block Read Interrupt Policy (BRIP): Setting this bit will enable the SMB host to always generate n+1 interrupts for a block read of n bytes (with e32b disabled) 0 RO 0b Repeat Policy: Setting this bit will revert back to the legacy behavior of ignoring the R/W bit field during a repeat start for any SMBus read protocol as a slave. Note: Field has no effect because slave mode not used. Device Clock Gate Control Register (DEVCLKGCTL) DEVCLKGCTL Bus: X Device: Bus: X Device: Bus: X Device: Bus: X Device: 0 0 0 0 Function: Function: Function: Function: Bit Attr Default 15 R/W PRST 0b 14:8 RV 000b 7:0 R/W PRST 10h 3 4 5 6 Offset: E4h; (Alias:); (Alias:); (Alias:); Description Idle Clock Gate Enable (ICGE): This bit when set enables clock gating to occur when the IP block is idle longer than the Idle Clock Timer. Reserved Idle Clock Timer (ICT): This field indicates the number of oclocks that the IP block must be idle before the clock disable process begins. Note: 16 (default value) is the minimum number of clocks recommended. IDF NVSRAM Device Clock Gate Control Register is defined here. 27.1.6.6 Sideband Device Clock Gate Control Register (SBDEVCLKGCTL) SBDEVCLKGCTL Bus: X Device: Bus: X Device: Bus: X Device: Bus: X Device: 0 0 0 0 Function: Function: Function: Function: Bit Attr Default 15 R/W PRST 0b 14:8 RV 000b 7:0 R/W PRST 10h 3 4 5 6 Offset: E6h; (Alias:); (Alias:); (Alias:); Description Idle Clock Gate Enable (ICGE): This bit when set enables clock gating to occur when the IP block is idle longer than the Idle Clock Timer. Reserved Idle Clock Timer (ICT): This field indicates the number of oclocks that the IP block must be idle before the clock disable process begins. Note: 16 (default value) is the minimum number of clocks recommended. IDF NVSRAM Sideband Device Clock Gate Control Register is defined here. 946 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.1.6.7 Personality Lock Key Control Register (PLKCTL) PLKCTL Bus: XDevice: 0Function: 3Offset: E8h; Bus: XDevice: 0Function: 4Offset: E8h; Bus: XDevice: 0Function: 5Offset: E8h; Bit Attr Default 15:1 RV 0h 0 R/W-KL PRST 0b Description Reserved Capability Lock (CL): Lock key bit for all R/WL bits (capabilities, next capability pointer, SSID/SVID, slot register, etc) bits for the function. 1b: Lock 0b: Unlocked Note: 27.1.6.8 This bit is self-locking. Once this bit is set to a 1b, this key bit can not be unlocked. Writing a 0b has no affect on this bit. Configuration Agent Error Register (CFGAGTERR) CFGAGTERR Bus: X Device: Bus: X Device: Bus: X Device: Bus: X Device: 0 0 0 0 Function: Function: Function: Function: Bit Attr Default 31:14 RV 0h 3 4 5 6 Offset: FCh; (Alias:); (Alias:); (Alias:); Description Reserved. 13 R/W1CS 0b Command Parity Error Status (CPES): 12 R/W1CS 0b Data Parity Error Status (DPES): 11 R/W1CS 0b Poisoned TLP Error Status (PTES): 10 R/W1CS 0b SMBus0 Internal Parity Error Status (S0IPES): 9 R/W1CS 0b SMBus1 Internal Parity Error Status (S1IPES): 8 R/W1CS 0b SMBus2 Internal Parity Error Status (S2IPES): 7 R/W1CS 0b NVSRAM Internal Parity Error Status (NIPES): 6 R/WS 0b Command Parity Error Mask (CPEM): 5 R/WS 0b Data Parity Error Mask (DPEM): 4 R/WS 0b Poisoned TLP Error Mask (PTEM): 3 R/WS 0b SMBus0 Internal Parity Error Mask (S0IPEM): 2 R/WS 0b SMBus1 Internal Parity Error Mask (S1IPEM): 1 R/WS 0b SMBus2 Internal Parity Error Mask (S2IPEM): 0 R/WS 0b NVSRAM Internal Parity Error Mask (NIPEM): Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 947 Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.1.6.9 Uncorrectable Error Status Register (ERRUNCSTS) ERRUNCSTS Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 Function: 3 Function: 4 Function: 5 Bit Attr Default 31:25 RV 000h Offset: 110h; (Alias:); (Alias:); Description Reserved 24 RO 0b Atomic Egress Blocked Error (AEBE): This bit is set whenever an AtomicOP TLP is blocked on any egress port Not Applicable. 23 RO 0b MC Blocked TLP Error (MCE): This bit is set whenever a Multicast TLP is blocked. Not Applicable. 22 R/W1CS 0b Uncorrectable Internal Error (UIE): This bit is set whenever a uncorrectable internal error is detected. 21 RO 0b ACS Violation Error (ACSE): This bit is set whenever an ACS violation is detected by the PCI Express* port. Not Applicable. 20 R/W1CS 0b Unsupported Request Error (URE): This bit is set whenever an unsupported request is detected on PCI Express. 19 RO 0b ECRC Check Error (ECRCE): PCH does not do ECRC checking, and this bit is never set. Not Applicable. 18 R/W1CS 0b Malformed TLP Error (MTLPE): This bit is set when it receives a malformed TLP. Header logging is performed. 17 RO 0b Receiver Overflow Error (ROE): This bit is set when the PCI Express interface unit receive buffers overflow. Not supported. 16 R/W1CS 0b Unexpected Completion Error (UCE): This bit is set whenever a completion is received with a requestor ID that does not match side A or side B, or when a completion is received with a matching requestor ID but an unexpected tag field. Header logging is performed. Note: This bit will never be set for the SMBus functions. 15 R/W1CS 0b Completer Abort Error (CAE): The bridge sets this bit and logs the header associated with the request when the configuration unit signals a completer abort. 14 RO 0b Completion Timeout Error (CTE): This bit is set when upstream memory configuration I/O reads do not receive completions within 16-32 ms. Not supported. 13 RO 0b Flow Control Error (FCE): This bit is set when a flow control protocol error is detected. Not supported. 12 R/W1CS 0b Poisoned TLP Error (PTLPE): This bit is set and the bridge logs the header when a poisoned TLP is received from PCI Express. 11:6 RV 00h 5 RO 0b Surprise Link Down Error (SLDE): This bit is set when a surprise link down error is detected. Not supported. 4 RO 0b Data Link Protocol Error (DLPE): This bit is set when a data link protocol error is detected. 3:0 RV 000b Reserved Zero: Software must write 0 to these bits. Reserved This is implementation specific register. 948 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.1.6.10 Uncorrectable Error Detect Mask Register (ERRUNCDETMSK) ERRUNCDETMSK Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 Function: 3 Function: 4 Function: 5 Bit Attr Default 31:25 RV 000h Offset: 114h; (Alias:); (Alias:); Description Reserved 24 RO 0b AtomicOp Egress Blocked Error Detect Mask (AEBEDM): Not Applicable. 23 RO 0b MC Blocked TLP Error Detect Mask (MCEDM): Not Applicable. 22 R/WS 0b Uncorrectable Internal Error Detect Mask (UIEDM): 21 RO 0b ACS Violation Error Detect Mask (ACSEDM): Not Applicable. 20 R/WS 0b Unsupported Request Error Detect Mask (UREDM): 19 RO 0b ECRC Check Error Mask (ECRCEDM): Not supported 18 R/WS 0b Malformed TLP Error Detect Mask (MTLPEDM): 17 RO 0b Receiver Overflow Error Detect Mask (ROEDM): Not Applicable. 16 R/WS 0b Unexpected Completion Error Detect Mask (UCEDM): 15 R/WS 0b Completer Abort Error Detect Mask (CAEDM): 14 RO 0b Completion Timeout Error Detect Mask (CTEDM): Not Applicable. 13 RO 0b Flow Control Error Detect Mask (FCEDM): Not Applicable. Poisoned TLP Error Detect Mask (PTLPEDM): 12 R/WS 0b 11:6 RV 00h 5 RO 0b Surprise Link Down Error Detect Mask (SLDEDM): Not Supported. 4 RO 0b Data Link Protocol Error Detect Mask (DLPEDM): Not Supported. 3:1 RV 000b 0 RO 0b Reserved Reserved Training Error Mask: Not supported Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 949 Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.1.7 Alternative Routing-ID Interpretation Extended Capability Structure This section describes the PCI Express* Extended Configuration Space registers that make up the Alternative Routing-ID Interpretation Extended Capability Structure. These registers are first in the extended capabilities list, so they are located at the base of Extended Configuration Space (100h). 27.1.7.1 Alternative Routing-ID Interpretation Extended Capability Header (ARICAPHDR) ARICAPHDR Bus: X Device: 0 Bus: X Device: 0 Bus: X Device: 0 27.1.7.2 Bit Attr Default 31:20 RO 000h 19:16 RO 1h 15:0 RO 000Eh Description Next Capability Offset (NCO): Contains the offset of the next structure in the Extended Capabilities list. Note: Lock Key bit is located in the Personality Lock Key Control Register ("PLKCTL"). Capability Version (CV): Indicates the version of the Capability structure present. Extended Capability ID (ECID): Identifies the function as Alternative RoutingID Interpretation capable. Device: 0 Device: 0 Device: 0 Function:3 Function:4 Function:5 Offset: 104h; Offset: 104h; Offset: 104h; Bit Attr Default Description 15:8 R/WL PRST Func? 3: 04h 4: 05h 5: 06h Next Function Number (NFN): This field indicates the next highest function number in this device, or 00h if there are not higher numbered function. Function 0 starts the linked list of functions. Note: Lock Key bit is located in the Personality Lock Key Control Register ("PLKCTL"). 7:2 RV 0h Reserved. 1 RO 0b ACS Function Group Capability (ACSFGC): Indicates the version of the Capability structure present. 0 RO 0b MFVC Function Group Capability (MFVCFGC): Contains the offset of the next structure in the Extended Capabilities list. Alternative Routing-ID Interpretation Control Register (ARICTL) ARICTL Bus: X Bus: X Bus: X 950 Offset: 100h; Offset: 100h; Offset: 100h; Alternative Routing-ID Interpretation Capability Register (ARICAP) ARICAP Bus: X Bus: X Bus: X 27.1.7.3 Function:3 Function:4 Function:5 Device: 0 Device: 0 Device: 0 Function:3 Function:4 Function:5 Bit Attr Default 15:7 RO 0h 6:4 RO 000b 3:2 RV 00b Offset: 106h; Offset: 106h; Offset: 106h; Description Reserved. Function Number (FN): Reserved. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) ARICTL Bus: X Bus: X Bus: X 27.2 Device: 0 Device: 0 Device: 0 Function:3 Function:4 Function:5 Offset: 106h; Offset: 106h; Offset: 106h; Bit Attr Default Description 1 RO 0b ACS Function Group Enable (ACSFGE): 0 RO 0b MFVC Function Group Enable (MFVCFGE): SMBus IO and Memory Space Registers The SMBus registers can be access through the IO BAR or Memory BAR registers in PCI configuration space. The Offset are same for both I/O and Memory Mapped I/O registers. 27.2.1 SMBus Function IO and MEM BAR Space Registers Table 27-3. SMBus I/O and Memory Mapped I/O Register Address Map SMB_BASE + Offset Mnemonic Register Name Default Attribute 00h HST_STS Host Status 00h R/WC, RO 02h HST_CNT Host Control 00h R/W, WO 03h HST_CMD Host Command 00h R/W 04h TSLVADR Transmit Slave Address 00h R/W 05h HST_D0 Host Data 0 00h R/W 06h HST_D1 Host Data 1 00h R/W 07h HSTBKDATA 08h PECDAT Host Block Data Byte 00h R/W Packet Error Check 00h R/W 09h RCV_SLVA Receive Slave Address 0Ah-0Bh SLV_DATA Receive Slave Data 44h R/W 0000h RO 0Ch AUX_STS Auxiliary Status 00h R/WC, RO 0Dh AUX_CTL Auxiliary Control 00h R/W 0Eh SMLINK_PIN_CTL SMLink Pin Control (TCO Compatible Mode) See register description R/W, RO 0Fh SMBus_PIN_CTL SMBus Pin Control See register description R/W, RO Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 951 Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.2.1.1 Host Status Register (HSTSTS) HSTSTS Base: SMBMBAR IO Base: SMBIOBAR Bit Default 7 R/W1C 0 6 RO 0 In Use Status (IUS): This host SMBus controller does not support multiple independent software threads using this host controller. Note: This bit has no effect on the host controller. 5 RO 0 SMBAlert Status: This bit when set to1b indicates the interrupt was due to the SMBAlert# signal. Note: Not used in this SMBus controller. No SMBAlert# pin. 4 R/W1C 0 Failed: This bit when set to 1b indicates the interrupt was due to a failed bus transaction. This bit is also set in response to a HSTCTL.Kill command. 3 R/W1C 0 Bus Error: This bit when set to 1b indicates that the source of the interrupt was due to a transaction collision. 2 R/W1C 0 Device Error: This bit when set to 1b indicates that the source of the interrupt was due to one of the following: Illegal command Field, Unclaimed Cycle (host master initiated), Host Device Time-out Error, CRC Error. 1 R/W1C 0 Interrupt: This bit when set to 1b indicates that the source of the interrupt was the successful completion of its last command. 0 Host Busy: This bit when set to 1b indicates the controller is running a command from the host interface. No SMBus register should be accessed while this bit is set. The only exception is when controller is programmed for block command or I2C read command. The Block Data Register can be accessed. This is necessary in order to check the Byte Done Status (BDS) bit in this register. R/W1C Host Control Register (HSTCTL) HSTCTL Base: SMBMBAR IO Base: SMBIOBAR 952 Description Byte Done Status (BDS): This bit is set to 1b when the host controller has received a byte (for Block Read commands) or if it has completed transmission of a byte (for Block Write commands) when the 32-byte buffer is not being used. This bit has no meaning for block transfers when the 32-byte buffer is enabled. Note: When the last byte of a block message is received, the host controller will set this bit. However, it will not immediately set the INTR bit (bit 1 in HSTSTS register). when the interrupt handler clears the Byte Done Status bit, the messages is considered complete, and the host controller will then set the INTR bit (and generate another interrupt). Thus, for a block message of n bytes, the Intel PCH will generate n+1 interrupts. The interrupt handler needs to be implemented to handle these cases. 0 27.2.1.2 Attr Offset: 00h; (Alias:) Offset: 02h; (Alias:) Bit Attr Default Description 7 R/W 0 PEC Enable: When set to a 1b, the controller will perform a Packet Error Checking phase append on SMBus transaction. For writes, the value of the PECDAT register is used for the PEC byte. For reads, the PEC byte is loaded in the PECDAT register. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) HSTCTL Base: SMBMBAR IO Base: SMBIOBAR Bit 6 5 Attr R/W-V R/W Offset: 02h; (Alias:) Default Description 0 Start: This bit is used to initiate the command programmed in the SMBus Command field. All registers should be setup prior to writing a 1b to this bit. The Controller will auto-clear this bit after software writes a 1b. The HSTSTS.Busy register bit can be used to identify when the SMBus has finished the command. 0 Last Byte: This bit is for software to indicate the controller that the next byte will be the last one to be received for that block. The algorithm and usage model for this bit will be as follows: 1. When the software sees the BYTE_DONE_STS bit set (bit 7 of HSTSTS register) for each of bytes 1 through n-2 of the message, the software should then read the block HSTBLKDAT to get the byte that was just received. 2. After reading each of bytes 1 to n-2 of the message, the software sill then clear the BYTE_DONE_STS bit. 3. After receiving byte n-1 of the message, the software will then set the "LAST BYTE" bit. The software will then clear the BYTE_DONE_STS bit. 4. The controller will the receive the las byte of the message (Byte N) However the controller state machine will see the last byte bit set. It will send a ACK after receiving the last byte instead of a NAK. 5. After receiving the last byte n, software will still clear the BYTE_DONE_STS bit. However the LAST_BYTE bit will be irrelevant at that point. 4:2 R/W 0 SMBus Command: This field indicates which command the e controller is to perform. If enabled, the controller will generate an interrupt when the command has been completed. If the value is for a non-supported or reserved command, the controller will set a device error status bit and generate an interrupt. The controller will not operate until DEV_ERR is cleared. 000b: Quick - The slave address and read/write value (bit 0) are stored in the Tx slave address register. 001b: Byte - This command uses the transmit slave address and command register. 010b: Bye Data - This command uses the transmit slave address, command, and DATA0 register. If command was a read, the DATA0 register will contain the data. 011b: Word Data - This command uses the transmit slave address, command, Data0, and Data1 register. If command was a read, the Data0 and Data1 registers will contain the read data. 100b: Process Call - This command uses the transmit slave address, command, Data0, and Data1 registers. If command was a read, the Data0 and Data1 registers will contain the read data. 101b: Block - This command uses the transmit slave address, command, Data0 register and the block Data Byte register. The count is stored in the Data0 register and indicates how many bytes of data will be transferred. For writes, write data must be serially written into the block data byte register before starting the controller. For reads, the data is stored in the data byte register. 110b: I2C read - This command uses the transmit slave address, command, Data0, Data1 and the block data byte register. The read is stored in the block data byte register. The Intel PCH will continue reading until the NAK is received. 111b: Block-process - This command uses the transmit slave address, command DAta0 and the block data byte register. The count is stored in the data0 register and indicates how many bytes the data will be transferred. For writes, write data must be serially written into the block data byte register. before starting the controller. For reads, the data is stored in the data byte register. 1 R/W 0 Kill: When set to 1b, the controller will stop the current transaction taking place and set the failed status bit. An interrupt will be asserted. Once set, this bit must be cleared by software to allow the controller to function normally. 0 R/W 0 Interrupt Enable: Enable the generation of an interrupt upon the completion of the command. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 953 Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.2.1.3 Host Command Register (HSTCMD) HSTCMD Base: SMBMBAR IO Base: SMBIOBAR 27.2.1.4 Bit Attr Default 7:0 R/W 0 Command: Eight bit field that is transmitted by the controller in the command field of the SMBus protocol during the execution of any command. Offset: 04h; (Alias:) Bit Attr Default 7:1 R/W 0 Target Address: 7-bit address of the targeted slave device. 0 R/W 0 RW: Direction of host transfer. 1b: read 0b: write Description Host Data 0 Register (HSTDATA0) HSTDATA0 Base: SMBMBAR IO Base: SMBIOBAR Bit 7:0 27.2.1.6 Description Transmit Slave Address Register (TSLVADR) TSLVADR Base: SMBMBAR IO Base: SMBIOBAR 27.2.1.5 Offset: 03h; (Alias:) Attr R/W-V Offset: 05h; (Alias:) Default Description 0 Data0: This register contains the eight bit data sent in the DATA0 field of the SMBus protocol. For block writes commands, this register reflects the number of bytes to transfer. This register should be programmed to a value between 1 and 32 for block counts. Other values will result in unpredictable behavior. The controller does not check or log illegal block counts. Host Data 1 Register (HSTDATA1) HSTDATA1 Base: SMBMBAROffset: 06h; IO Base: SMBIOBAR(Alias:) 954 Bit Attr Default 7:0 R/W-V 0 Description Data1: This register contains the eight bit data sent in the DATA1 field of the SMBus protocol during the execution of any command. Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.2.1.7 Host Block Data Register (HSTBKDATA) HSTBKDATA Base: SMBMBAROffset: 07h; IO Base: SMBIOBAR(Alias:) Bit 7:0 27.2.1.8 Attr R/W-V Default Description 0 Block Data: This register is the block data register used when the controller issues block writes or block reads. When the E32B bit is set in the AUXCTL register, reads and writes to this registers are used to access the 32-byte block data storage array. An internal index pointer is used to address the array, which is reset to 0 by reading the HSTCTL register. The index pointer than increments automatically upon each access to this register. the transfer of block transaction always starts at index address 0. Software can write up to 32-bytes to this register as part of the setup for the command. After the controller has sent the address, command, and byte count fields, it will send the bytes in the SRAM pointed to by this register. When the E2B bit is set for reads, the read data is stored into the 32-byte storage array until filled. An interrupt will be generated and the Done_STS bit will be set. When the E32B bit is not set in the AUXCTL register, software places a single byte in this register. After the controller has sent the address, command, and byte count fields, it will send the byte in this register. If there is more data to send, software will write the next byte in series to this register and clear the DONE_STS bit. The controller will send the next byte. The controller will insert wait-states on the SMBus interface waiting for data until the last byte has been transmitted. Packet Error Check Data Register (PECDAT) PECDAT Base: SMBMBAR IO Base: SMBIOBAR Bit 7:0 Attr R/W-V Offset: 08h; (Alias:) Default Description PEC DATA: This 8-bit register field is written with the SMBus PEC data prior to a write transaction. For read transactions, the PEC data is loaded form the SMBus controller into this register to allow software to read Packet Error check data. Software must ensure that the INUSE Status bit is properly maintained to avoid having this field over-written by a write transaction following a read. 0 This register contains the 8-bit CRC value that is used as the Packet Error Check on SMBus. For writes, this register is written by software prior to running the command. For reads, this register is read by software after the read command is completed on the SMBus. 27.2.1.9 Auxiliary Status Register (AUXSTS) AUXSTS Base: SMBMBAR IO Base: SMBIOBAR Offset: 0Ch; (Alias:) Bit Attr Default 7:1 RV 0 Reserved 0 CRC Error (CRCE): This bit when set to 1b indicates that a received message contained a CRC error. When this bit is set, the DERR bit of the Host STatus Register will also be set. This bet will be set by the controller if a software abort occurs in the middle of the CRC portion of the cycle or an abort happens after the controller has received the final data bit transmitted by external slave. 0 R/W1C Description Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet 955 Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) 27.2.1.10 Auxiliary Control Register (AUXCTL) AUXCTL Base: SMBMBAR IO Base: SMBIOBAR 27.2.1.11 Offset: 0Dh; (Alias:) Bit Attr Default Description 7:2 RV 0 Reserved 1 R/W 0 Enable 32-byte Buffer (E32B): This bit when set to 1b will enable Host Block Data Register to reference a 32-byte buffer, as opposed to a single register. This enables the block command to transfer or receive up to 32-bytes before the SMBus controller generates an interrupt. 0 R/W 0 Auto Append CRC Enable (AACRCE): This bit when set to 1b will enable the controller to automatically append the CRC. SMBus Pin Control Register (SMBPINCTL) SMBPINCTL Base: SMBMBAR IO Base: SMBIOBAR Offset: 0Fh; (Alias:) Bit Attr Default Description 7:3 RV 0 Reserved 2 R/W 1 SMBus Clock Force Disable (CFLD): This bit control the Clock pin over drive logic to drive the clock pin low. 1b: SMBus Clock pin is not driven low 0b: SMBus clock pin is driven low 1 RO-V 0 SMBus Data Pin Current Status (DPCS): This bit allows software to read the current state of the data pin on SMBus. A 1b indicates a high pin state and a 0b indicates a low pin state. 0 RO-V 0 SMBus Clock Pin Current Status (CPCS): This bit allows software to read the current state of the Clock pin on SMBus. A 1b indicates a high pin state and a 0b indicates a low pin state. 956 Intel(R) C600 Series Chipset and Intel(R) X79 Express Chipset Datasheet