BD82C604SLJKJ - INTEL

Document Number: 326514-002

Intel® C600 Series Chipset and

Intel® X79 Express Chipset

Datasheet

April 2013

2Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

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Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

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an OS or an application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing

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the necessary drivers installed. System sound quality will vary depending on actual implementation, controller, codec, drivers and

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Intel® C600 Series Chipset and Intel® X79 Express Chipset 3

Datasheet

Contents

1Introduction............................................................................................................41

1.1 About This Manual.............................................................................................41

1.2 Overview .........................................................................................................44

1.2.1 Capability Overview................................................................................ 45

1.3 Intel® C600 Series Chipset and Intel® X79 Express Chipset SKU Definition ............ ...50

2 Signal Description ...................................................................................................51

2.1 Direct Media Interface (DMI) to Host Controller.....................................................53

2.2 PCI Express* ....................................................................................................53

2.3 PCI Express* Uplink (Intel® C606, C 608 Chipset SKUs Only)........................ ........... 54

2.4 PCI Interface ....................................................................................................54

2.5 Serial ATA Interface.................. .. .. .. .. ............. ............ .. ............. .. ............. .. ........56

2.6 SAS Interface (SRV/WS SKUs Only).....................................................................58

2.7 LPC Interface....................................................................................................60

2.8 Interrupt Interface ............................................................................................60

2.9 USB 2.0 Interface................ .. ........... .. ........... .. .......... .. ........... .......... ... .......... .. ..61

2.10 Power Management Interface..............................................................................62

2.11 Processor Interface............................................................................................64

2.12 SMBus Interface................................................................................................65

2.13 System Management Interface............................................................................65

2.14 SAS System Management Interface (SRV/WS SKUs Only).......................................65

2.15 Real Time Clock Interface...................................................................................66

2.16 Miscellaneous Sig n als .......... .. ... ............ .. ............. ............. .. ............ .. ............. .. ..66

2.17 Intel® High Definition Audio (Intel® HD Audio) Link ................ ............ .. ............. .. ..67

2.18 Serial Peripheral Interface (SPI)..........................................................................68

2.19 Thermal Signals ................................................................................................68

2.20 JTAG Signals ....................................................................................................68

2.21 Clock Signals....................................................................................................69

2.22 General Purpose I/O Signals ...............................................................................70

2.23 GPIO Serial Expander Signals..................... .. ............. .. ............. ............. .. ............73

2.24 Manageability Signals ........................................................................................ 73

2.25 Power and Ground Signals..................................................................................74

2.26 Pin Straps ........................................................................................................76

2.26.1 Functional Straps .......... .. .. ............ .. ............. ............. .. ............. .. ............76

2.27 External RTC Circuitry........................................................................................79

3PCH Pin States.........................................................................................................81

3.1 Integrated Pull-Ups and Pull-Downs.....................................................................81

3.2 Output and I/O Signals Planes and States.............................................................82

3.3 Power Planes for Input Signals............................................................................87

4System Clock Domains.............................................................................................91

4.1 System Clock Domains.......................................................................................91

4.2 Functional Blocks .................. ... .. ............ .. ............. ............. .. ............ ... ............ ..93

5 Functional Description.............................................................................................95

5.1 PCI-to-PCI Bridge (D30:F0 )..................... .. ............. ............. .. ............ ... ............ ..95

5.1.1 PCI Bus Interface ...................................................................................95

5.1.2 PCI Bridge As an Initiator........................................................................95

5.1.3 Parity Error Detection and Generation.......................................................97

5.1.4 PCIRST#...............................................................................................98

5.1.5 Pe er Cycle s ............... ........... .. ........... .. .......... .. ........... .. ........... .......... .. ..98

5.1.6 PCI-to-P CI Bridge Model..... .. .. .. ............. ............ .. ............. .. ............. .. ......98

5.1.7 IDSEL to Device Number Mapping ............................................................99

4Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.1.8 Standard PCI Bus Configuration Mechanism................................................99

5.2 PCI Legacy Mode ...............................................................................................99

5.3 PCI Express*...................................................................................................100

5.3.1 PCI Express* UpLink Port (Bn:D0:F0) (SRV/WS SKUs Only) .......................100

5.3.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7) ..........................106

5.4 Gigabit Ethernet Controller (B0:D25:F0) .............................................................110

5.4.1 GbE PCI Express Bus Interface ...............................................................112

5.4.2 Error Events and Error Reporting ............................................................113

5.4.3 Ethernet Interface ................................................................................113

5.4.4 PCI Power Management.........................................................................113

5.4.5 Configurable LEDs.................................................................................115

5.4.6 Function Level Reset Support (FLR) (SRV/WS SKUs Only) ..........................116

5.5 LPC Bridge (with System and Management Functions) (D31:F0).............................117

5.5.1 LPC Interface .......................................................................................117

5.6 DMA Operation (D31:F0 ) ................. ............ .. ............. .. ............. ............. .. ........121

5.6.1 Channel Priority....................................................................................122

5.6.2 Address Compatibility Mode ...................................................................122

5.6.3 Summary of DMA Transfer Sizes.............................................................122

5.6.4 Autoinitialize........................................................................................123

5.6.5 Software Commands.............................................................................123

5.7 LPC DMA ........................................................................................................124

5.7.1 Asse rting DM A Requ e sts................. .. ............. ............. .. ............ ... ..........124

5.7.2 Abandoning DMA Requests.....................................................................124

5.7.3 General Flow of DMA Transfers...............................................................125

5.7.4 Te r minal Count......... .. ............. .. ............. ............ .. ............. .. ............. .. ..125

5.7.5 V e rify Mod e ...................... .. .......... ........... .. .......... ... .......... .. ........... .. ....125

5.7.6 DM A Re q u e st Deasse rtion........... .. .. ............. .. ............. .. ............ ... ..........126

5.7.7 SYNC Field / LDRQ# Rules .....................................................................126

5.8 8254 Timers (D31:F0)......................................................................................127

5.8.1 Timer Programming ..............................................................................127

5.8.2 Reading from the Interval Timer.............................................................128

5.9 8259 Interrupt Controllers (PIC) (D31:F0)...........................................................130

5.9.1 Interrupt Handling ................................................................................131

5.9.2 Initialization Command Words (ICWx) .....................................................132

5.9.3 Operation Command Words (OCW) .........................................................133

5.9.4 Modes of Operation...............................................................................133

5.9.5 M askin g Interrupts........ ........... .. ........... .. .......... .. ........... .. ........... .. ........135

5.9.6 Ste ering PCI Interrupts........... .. ............. .. ............ ............. .. ............. .. ....135

5.10 Advanced P rogrammable Interrupt Controller (APIC) (D31:F0)...............................136

5.10.1 Interrupt Handling ................................................................................136

5.10.2 Interrupt Mapping.................................................................................136

5.10.3 PCI / PCI Express* Message-Based Interrupts ..........................................137

5.10.4 IOxAPIC Address Re map p i ng (SRV/WS SKUs Only) .......... .. .. ............. .. ......137

5.10.5 External Interrupt Controller Support ......................................................137

5.11 Serial Interrupt (D31:F0)..................................................................................138

5.11.1 Start Frame .........................................................................................138

5.11.2 Data Frames ........................................................................................139

5.11.3 Stop Frame..........................................................................................139

5.11.4 Specific Interrupts Not Supported using SERIRQ .......................................139

5.11.5 Data Frame Format...............................................................................140

5.12 Real Time Clock (D31:F0).................................................................................140

5.12.1 Update Cycles ......................................................................................141

5.12.2 Interrupts............................................................................................141

5.12.3 Lockable RAM Ranges............................................................................141

5.12.4 Century Rollover................ .. .. .......... ........... .. ........... .. .......... .. ........... .. ..142

5.12.5 Clearing Battery-Backed RTC RAM...........................................................142

Intel® C600 Series Chipset and Intel® X79 Express Chipset 5

Datasheet

5.13 Processor Interface (D31:F0)............................................................................ 143

5.13.1 Processor Interface Signals and VLW Messages ........................................ 144

5.13.2 Dual-Processor Issues........................................................................... 145

5.13.3 Virtual Legacy Wire (VLW) Messages....................................................... 145

5.14 Power Management ......................................................................................... 146

5.14.1 Features ............................................................................................. 146

5.14.2 PCH and System Power States ............................................................... 146

5.14.3 System Power Planes............................................................................ 148

5.14.4 SMI#/SCI Generation ........................................................................... 148

5.14.5 C-States ............................................................................................. 151

5.14.6 Sleep States........................................................................................ 151

5.14.7 Event Input Signals and Th eir Usag e..................... ... ............ .. ............. .... 155

5.14.8 ALT Access Mode.................................................................................. 158

5.14.9 System Power Supplies, Planes, and Signals ............................................ 161

5.14.10Legacy Power Management Theory of Operation....................................... 163

5.14.11Reset Behavior..... .. .. .. ............. .. ............. ............ ... ............ .. ............. .. .. 163

5.15 System Management (D31:F0).......................................................................... 165

5.15.1 Theory of Operation.............................................................................. 166

5.15.2 TCO Modes....................... .. .......... .. ........... .. ........... .. .......... .. ........... .. .. 167

5.16 General Purpose I/O (D31:F0) .......................................................................... 169

5.16.1 Power Wells......................................................................................... 169

5.16.2 SMI# SCI and NMI Routing .................................................................... 169

5.16.3 Triggering ........................................................................................... 169

5.16.4 GPIO Registers Lockdown...................................................................... 169

5.16.5 Serial POST Codes over GPIO................................................................. 170

5.16.6 GPIO Serial Expander (GSX).................................................................. 172

5.17 SATA Host Controller (D31:F2, F5) ......... .. .. .. ... ............ ............. .. ............. .. ........ 174

5.17.1 SATA 6 Gb/s Support............... .. ........... .. .......... .. ........... .. ........... .. ........ 174

5.17.2 SATA Feature Sup p o rt.......... .. .. ........... .......... .. ........... .. .......... ... .......... .. 174

5.17.3 Theory of Operation.............................................................................. 175

5.17.4 SATA Swap Bay Support ............ .. ........... .. .......... ... .......... .. ........... .. ...... 176

5.17.5 Hot-Plug Operation............................................................................... 176

5.17.6 Function Level Reset Support (FLR) (SRV/WS SKUs Only).......................... 176

5.17.7 Intel® Rapid Storage Technology Enterprise Configuration......................... 177

5.17.8 Power Management Operation................................................................ 178

5.17.9 SATA Device Pre s ence . ... .......... ........... .. .......... .. ........... .. ........... .. .......... 179

5.17.10SATA LED................ ........... .. .......... ... .......... ........... .. .......... .. ........... .. .. 180

5.17.11AHCI Operation.................................................................................... 180

5.17.12SGPIO Signals ..... ........... .. .......... .. ........... .. ........... .. .......... .. ........... .. .... 181

5.17.13External SATA...................................................................................... 184

5.18 SAS/SATA Controller Overview (SAS is for SRV/WS SKUs Only)............................. 185

5.18.1 SCU Features................ .......... .. ........... .. .......... .. ........... .. ........... .. ........ 185

5.18.2 SCU Configurations............ .......... .. ........... .......... ... .......... .. ........... .. ...... 186

5.18.3 Storage Controller Unit (SCU) Architecture .............................................. 188

5.18.4 SCU Physical Layer/PHY Overview .......................................................... 196

5.18.5 Interrupts and Interrupt Coalescing ........................................................ 198

5.18.6 SMU Error and Event Generation ............................................................ 199

5.18.7 Host Interface Error Conditions .............................................................. 200

5.18.8 Host Interface Messages Received.......................................................... 204

5.18.9 Reset.................................................................................................. 204

5.18.10SGPIO ................................................................................................ 205

5.19 High Precision Event Ti me rs (HPE T)................... .. .. .. ............. ............ .. ............. .. 214

5.19.1 Timer Accuracy.................................................................................... 214

5.19.2 Interrupt Mapping ................................................................................ 215

5.19.3 Periodic versus Non-Periodic Modes ........................................................ 216

5.19.4 Enabling the Timers.............................................................................. 217

6Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.19.5 Interrupt Levels....................................................................................217

5.19.6 Handling Interrupts...............................................................................217

5.19.7 Issues Related to 64-Bit Timers with 32-Bit Processors ..............................217

5.20 USB EHCI Host Controllers (D29:F0 and D26:F0).................................................217

5.20.1 EHC Initialization..................................................................................217

5.20.2 Data Structures in Main Memory.............................................................218

5.20.3 USB 2.0 Enhanced Host Controller DMA ...................................................218

5.20.4 Data Encoding and Bit Stuffing ...............................................................218

5.20.5 Packet Formats ....................................................................................218

5.20.6 USB 2.0 Interrupts and Error Conditions ..................................................219

5.20.7 USB 2.0 Power Management ..................................................................220

5.20.8 USB 2.0 Legacy Keyboard Operation .......................................................221

5.20.9 USB 2.0 Based Debug Port.....................................................................221

5.20.10EHCI Caching.......................................................................................225

5.20.11USB Pre-Fetch Based Pause ...................................................................225

5.20.12Function Level Reset Support (FLR) (SRV/WS SKUs Only) ..........................226

5.20.13USB Overcurrent Protection....................................................................226

5.21 Integrated USB 2.0 Rate Matching Hub...............................................................227

5.21.1 Overview.............................................................................................227

5.21.2 Architecture.........................................................................................227

5.22 SMBus Controller.............................................................................................228

5.22.1 Host SMBus Controller(D31:F3)..............................................................228

5.22.2 IDF SMbus Controllers (Bus x:Device 0:Function 3,4,5)

(SRV/WS SKUs Only) ............................................................................228

5.22.3 Host Controller.....................................................................................229

5.22.4 Bus Arbitration.....................................................................................233

5.22.5 Bus Timing ..........................................................................................234

5.22.6 Interrupts / SMI#.................................................................................234

5.22.7 SMBALERT#.........................................................................................235

5.22.8 SMBus CRC Generation and Checking......................................................235

5.22.9 SMBus Slave Interface...........................................................................236

5.23 Thermal Manage me nt.................. .. .. .. ............ ............. .. ............. .. ............. .. ......241

5.23.1 Thermal Sensor............ ... .. .......... .. ........... .......... .. ........... .. ........... .. ......241

5.23.2 Thermal Reporting Over System Management Link 1 Interface (SMLink1).....243

5.24 Intel® High Definition Audio (Intel® HD Audio) Overview (D27:F0).........................251

5.25 PCH Intel® Management Engin e Firm ware.............................. .. ............ .. .............251

5.25.1 Intel® Server Platform Services Firmware................................................251

5.25.2 Intel® AMT 7.0 (SRV/WS SKUs Only) ......................................................253

5.25.3 Intel® Management Engine Require m e nts................... .. ............ ............. ..254

5.26 Serial Peripheral Interface (SPI) ........................................................................255

5.26.1 SPI Supported Feature Overview ............................................................255

5.26.2 Flash Descriptor ........... ............. .. ............. .. ............. .. ............ .. .............256

5.26.3 Flash Access ................... .. .. .. ............ ... ............ .. ............. .. ............. .. ....258

5.26.4 Serial Flash Device Compatibility Requirements ........................................259

5.26.5 Multiple Page Write Usage Model.............................................................261

5.26.6 Flash Device Configurations .......... .. ............. .. ............. .. ............ .............262

5.26.7 SPI Flash Device Recommended Pinout....................................................263

5.26.8 Serial Flash Device Package ...................................................................263

5.27 Fan Control/Thermal Management .....................................................................264

5.27.1 PWM Outputs.......................................................................................264

5.27.2 TACH Inputs ........................................................................................264

5.28 Feature Capability Mechanism ...........................................................................265

5.29 Intel® Virtualization Technology (SRV/WS SKUs Only)..........................................265

5.29.1 Intel® Virtualization Technology (Intel® VT) for Directed

I/O (Intel® VT-d) Objectives ..................................................................265

5.29.2 Intel® VT-d features supported on PCH....................................................265

Intel® C600 Series Chipset and Intel® X79 Express Chipset 7

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5.29.3 Supp o rt for Function Level Reset (FLR) in PCH.......................................... 266

5.29.4 Virtualization Support for PCH’s IOxAPIC ................................................. 266

5.29.5 Virtualization Support for High Precision Event Timer (HPET)...................... 266

6 PCH Ballout Definition ........................................................................................... 267

7 Package Information ............................................................................................. 281

8 Electrical Characteristics ....................................................................................... 283

8.1 Thermal Specifications..................................................................................... 283

8.2 Absolute Maxim u m Ratings.................... .. ............. .. ............. ............ .. ............. .. 283

8.3 PCH Power Supply Range ................................................................................. 284

8.4 General DC Characteristics ............................................................................... 284

8.5 AC Characteristics ........................................................................................... 294

8.6 Power Sequencing and Reset Signal Timings....................................................... 302

8.7 Power Management Timing Diagrams................................................................. 305

8.8 AC Timing Diagrams........................................................................................ 309

9 Register and Memory Mapping............................................................................... 319

9.1 PCI Devices and Functions................................................................................ 320

9.2 PCI Configuration Map ..................................................................................... 321

9.3 I/O Map......................................................................................................... 322

9.3.1 Fixed I/O Address Ranges ..................................................................... 322

9.3.2 Variable I/O Decode Ranges .................................................................. 324

9.4 Memory Map..................... .. ........... .. .......... ........... .. ........... .. .......... .. ........... .. .. 325

9.4.1 Boot-Block Update Scheme.................................................................... 327

10 Chipset Configuration Registers............................................................................. 329

10.1 Chipset Configuration Reg i sters (Memory Space).................... .. .. ............. ............ 329

10.1.2 RPC—Root Port Configuration Register .................................................... 331

10.1.4 FLRSTAT—FLR Pending Status Register ................................................... 333

10.1.6 TRCR—Trapped Cycle Register ............................................................... 334

10.1.7 TWDR—Trapped Write Data Register....................................................... 334

10.1.9 V0CTL—Virtual Channel 0 Resource Control Register................................. 336

10.1.10V0STS—Virtual Channel 0 Resource Status Register.................................. 336

10.1.11V1CTL—Virtual Channel 1 Resource Control Register................................. 336

10.1.12V1STS—Virtual Channel 1 Resource Status Register.................................. 337

10.1.13REC—Root Error Command Register ....................................................... 337

10.1.14LCAP—Link Capabilities Register............................................................. 337

10.1.15LCTL—Link Control Register................................................................... 338

10.1.16LLSTS—Link Status Reg i ster .................. ............ ............. .. ............. .. ...... 338

10.1.17DLCTL2—DM I Li nk Control 2 Re g i ste r.................. .. ............. ............. .. ...... 338

10.1.18DMIC—DMI Control Register .................................................................. 338

10.1.19TCTL—TCO Configuration Register.......................................................... 339

10.1.20D31IP—Device 31 Interrupt Pin Register.................................................. 339

10.1.21D30IP—Device 30 Interrupt Pin Register.................................................. 340

10.1.22D29IP—Device 29 Interrupt Pin Register.................................................. 340

10.1.23D28IP—Device 28 Interrupt Pin Register.................................................. 340

10.1.25D26IP—Device 26 Interrupt Pin Register.................................................. 342

10.1.26D25IP—Device 25 Interrupt Pin Register.................................................. 342

10.1.28D31IR—Device 31 Interrupt Route Register ............................................. 344

10.1.29D30IR—Device 30 Interrupt Route Register ............................................. 344

10.1.37PRSTS—Power and Reset Status Register ................................................ 351

10.1.38PM_CFG—Power Management Configuration............................................. 352

10.1.39DEEP_S4_POL—Deep S4/S5 From S4 Power Policies . .............. .................. 353

10.1.40DEEP_S5_POL—Deep S4/S5 From S5 Power Policies . .............. .................. 353

10.1.41RC—RTC Configuration Register ............................................................. 353

10.1.42HPTC—High Precision Timer Configuration Register................................... 354

10.1.43GCS—General Control and Status Register............................................... 354

8Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

10.1.44BUC—Backed Up Control Register ...........................................................356

10.1.45FD—Function Disable Register ................................................................356

10.1.46CG—Clock Gating..................................................................................359

10.1.47FDSW—Function Disable SUS Well ..........................................................360

10.1.48FD2—Function Disable 2........................................................................360

10.1.49GSXBAR—GPIO Serial Expander Base Addr e ss................. .. ............. .. ........361

10.1.50GSXCTRL—GPIO Serial Expander Control Register.....................................361

10.1.51MISCCTL—M iscellane ous Control Reg i ster ............ .. ............. ............. .. ......361

10.1.52USBOCM1 — Ove rcurre nt MA P Re g i ster 1.......................... .. ............. .. ........362

10.1.53USBOCM2 — Ove rcurre nt MA P Re g i ster 2.......................... .. ............. .. ........363

10.1.54RMHWKCTL- Rate Matching Hub Wake Control Register .............................363

11 PCI-to-PCI Bridge Registers (D30:F0)....................................................................365

11.1 PCI Configuration Registers (D30:F0) .................................................................365

11.1.1 VID—Vendor Identification Register (PCI-PCI—D30:F0)..............................366

11.1.2 DID—Device Identification Register (PCI-PCI—D30:F0)..............................366

11.1.3 PCICMD—PC I Command (PCI-PCI—D30:F0 ).................... .. .. .. .. ............. ....366

11.1.4 PSTS—PCI Status Register (PCI-PCI—D30:F0)..........................................367

11.1.5 RID—Revision Identification Register (PCI-PCI—D30:F0)............................368

11.1.6 CC—Class Code Register (PCI-PCI—D30:F0).............................................368

11.1.7 PMLT—Primary Master Latency Timer Register

(PCI-PCI—D30:F0)................................................................................368

11.1.8 HEADTYP—Head er Ty pe Regi ster (PC I -PC I —D3 0: F0) ........................... .. ....369

11.1.9 BNUM—Bus Number Register (PCI-P CI—D 30 :F0 ) ......................... ... ..........369

11.1.10SMLT—Seco ndary Master Latency Timer Re g is t er

(PCI-PCI—D30:F0)................................................................................369

11.1.11IOBASE_LIMIT—I/O Base and Limit Register

(PCI-PCI—D30:F0)................................................................................370

11.1.12SECSTS—Sec ond ary Status Reg ister (PCI-PCI—D30:F0) ............................370

11.1.13MEMBASE_LIMIT—Memory Base and Limit Register

(PCI-PCI—D30:F0)................................................................................371

11.1.14PREF_MEM_BASE_LIMIT—Prefetchable Memory Base

and Limit Register (PC I-PCI—D30:F0) ............. ............. .. ............ ... ..........371

11.1.15PMBU32—Prefetchable Memory Base Upper 32 Bits

11.1.16PMLU32—Prefetchable Memory Limit Upper 32 Bits

11.1.17CAPP—Capability List Pointer Register (PCI-PCI—D30:F0) ..........................372

11.1.18INTR—Interrupt Information Register (PCI-PCI—D30:F0)...........................372

11.1.19BCTRL—Bridge Control Register (PCI-PCI—D30:F0)...................................372

11.1.20SPDH—Secondary PCI Device Hiding Register

(PCI-PCI—D30:F0)................................................................................374

11.1.21DTC—Delayed Transaction Control Register

(PCI-PCI—D30:F0)................................................................................374

11.1.22BPS—Bridge Proprietary Status Register

(PCI-PCI—D30:F0)................................................................................375

11.1.23BPC—Bridge Policy Configuration Register

(PCI-PCI—D30:F0)................................................................................376

11.1.24SVCAP—Subsystem Vendor Capability Register

(PCI-PCI—D30:F0)................................................................................377

11.1.25SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0).........................377

12 Gigabit LAN Configuration Registers ......................................................................379

12.1 Gigabit LAN Configuration Registers

(Gigabit LAN — D25:F0) ...................................................................................379

12.1.1 VID—Vendor Identification Register

(Gigabit LAN—D25:F0) ..........................................................................380

12.1.2 DID—Device Identification Register

(Gigabit LAN—D25:F0) ..........................................................................380

Intel® C600 Series Chipset and Intel® X79 Express Chipset 9

Datasheet

12.1.3 PCICMD—PCI Command Register

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 381

12.1.4 PCISTS—PCI Status Register

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 382

12.1.5 RID—Revision Identification Register

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 382

12.1.6 CC—Class Code Reg ister

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 383

12.1.7 CLS—Cache Line Size Reg ister

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 383

12.1.8 PLT—Primary Latency Timer Register

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 383

12.1.9 HEAD TYP—Header Type Register

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 383

12.1.10MBARA—Memory Base Address Register A

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 384

12.1.11MBARB—Memory Base Address Register B

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 384

12.1.12MBARC—Memory Base Address Register C

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 385

12.1.13SVID—Subsystem Vendor ID Register

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 385

12.1.14SID—Subsystem ID Register

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 385

12.1.15ERBA—Expansion ROM Base Address Register

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 385

12.1.16CAPP—Capabilities List Pointer Register

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 386

12.1.17INTR—Interrupt Information Register

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 386

12.1.18MLMG—Maximum Latency/Minimum Grant Register

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 386

12.1.19CLIST 1—Capabilities List Register 1

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 386

12.1.20PMC—PCI Powe r Management Capabilities Register

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 387

12.1.21PMCS—PCI Power Management Control and Status

12.1.23CLIST 2—Capabilities List Register 2

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 389

12.1.24MCTL—Message Control Register

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 389

12.1.25MADDL—Message Address Low Register

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 389

12.1.26MADDH—Message Address High Register

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 389

12.1.27MDAT—Message Data Register

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 390

12.1.28FLR CAP—Function Level Reset Capability

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 390

12.1.29FLR CLV—Function Level Reset Capability Le ngth and Version

(Gigabit LAN—D25:F0)................... .. ... .. ............ .. ............. ............. .. ...... 390

12.1.301DEVCTRL—Device Control (Gig ab it LAN—D 25: F0 ) ................ .. ............. .... 391

12.2 Gigabit LAN Capabilities and Status Registers (CSR)............................................. 391

12.2.1 GBECSR1—Gigabit Ethernet Capabilities and Status Register 1 . .................. 391

12.2.2 GBECSR2—Gigabit Ethernet Capabilities and Status Register 2 . .................. 392

12.2.3 GBECSR3—Gigabit Ethernet Capabilities and Status Register 3 . .................. 392

12.2.4 GBECSR4—Gigabit Ethernet Capabilities and Status Register 4 . .................. 392

12.2.5 GBECSR5—Gigabit Ethernet Capabilities and Status Register 5 . .................. 393

10 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

12.2.6 GBECSR6—Gigabit Ethernet Capabilities and Status Register 6....................393

12.2.7 GBECSR7—Gigabit Ethernet Capabilities and Status Register 7....................393

12.2.9 GBECSR9—Gigabit Ethernet Capabilities and Status Register 9....................394

13 LPC Interface Bridge Registers (D31:F0) ...............................................................395

13.1 PCI Configuration Registers (LPC I/F—D31:F0) ....................................................395

13.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0) ..............................396

13.1.2 DID—Device Identification Reg i ster (LPC I/F—D31:F0)...............................396

13.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0).................................397

13.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0)........................................397

13.1.5 RID—Revision Identification Register (LPC I/F—D31: F0 ) ..... .. ........... .. ........398

13.1.6 PI—Programming Interface Register (LPC I/F—D31 : F0) .......................... ...398

13.1.7 SCC—Sub Class Code Re g ister (LP C I/F—D31:F0) ........................... .. ........398

13.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0)....................................398

13.1.10HEADTYP — He ad er Type Register (LPC I/F— D3 1 : F0 )........... ............. .. ........399

13.1.11SS—Sub System Identifiers Register (LPC I/F—D31:F0)............. ................399

13.1.12CAPP—Capability List Pointer Register (LPC I/F—D31:F0)...........................399

13.1.15GPIOBASE—GPIO Base Address Register

(LPC I/F — D31:F0) ..............................................................................401

13.1.17PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register

(LPC I/F—D31:F0) ................................................................................402

13.1.18SIRQ_CNTL—Serial IRQ Control Register

(LPC I/F—D31:F0) ................................................................................403

13.1.20LPC_IBDF—IOxAPIC Bus:Device:Function

(LPC I/F—D31:F0) ................................................................................404

13.1.21LPC_HnBDF – HPET n Bus:Device:Function(LPC I/F—D31:F0).....................405

13.1.22LPC_I/O_DEC—I/O Decode Ranges Register

(LPC I/F—D31:F0) ................................................................................406

13.1.23LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0)................................407

13.1.24GEN1_DEC—LPC I/F Generic Decode Range 1 Register

(LPC I/F—D31:F0) ................................................................................408

13.1.25GEN2_DEC—LPC I/F Generic Decode Range 2 Register

(LPC I/F—D31:F0) ................................................................................408

13.1.26GEN3_DEC—LPC I/F Generic Decode Range 3 Register

(LPC I/F—D31:F0) ................................................................................409

13.1.27GEN4_DEC—LPC I/F Generic Decode Range 4 Register

(LPC I/F—D31:F0) ................................................................................409

13.1.29LGMR — LPC I/F Generic Memory Range

(LPC I/F—D31:F0) ................................................................................411

13.1.30BIOS_SEL1—BIOS Select 1 Register

(LPC I/F—D31:F0) ................................................................................411

13.1.31BIOS_SEL2—BIOS Select 2 Register

(LPC I/F—D31:F0) ................................................................................412

13.1.32BIOS_DEC_EN1—BIOS Decode Enable Register

(LPC I/F—D31:F0) ................................................................................412

13.1.33BIOS_CNTL—BIOS Control Register

(LPC I/F—D31:F0) ................................................................................414

13.1.34FDCAP—Feature Detection Capability ID

(LPC I/F—D31:F0) ................................................................................415

13.1.35FDLEN—Feature Detection Capability Length

(LPC I/F—D31:F0) ................................................................................415

13.1.36FDVER—Feature Detection Version

(LPC I/F—D31:F0) ................................................................................415

13.1.37FVECIDX—Feature Vector Index

(LPC I/F—D31:F0) ................................................................................416

13.1.38FVECD—Feature Vector Data

(LPC I/F—D31:F0) ................................................................................416

13.1.39Feature Vector Space ............................................................................416

Intel® C600 Series Chipset and Intel® X79 Express Chipset 11

Datasheet

13.1.40RCBA—Root Complex Base Address Register

(LPC I/F—D31:F0)................................................................................ 418

13.2 DMA I/O Registers........................................................................................... 418

13.2.1 DMABASE_C A—D M A Ba se and Curre nt Ad dress Registers ........... ............. .. 419

13.2.2 DMABASE_CC—DMA Base and Current Count Registers ............................. 420

13.2.3 DMAMEM_LP—DMA Memory Low Page Registers....................................... 420

13.2.4 DMACMD—DMA Command Register ........................................................ 420

13.2.6 DMA_WRSMSK— DM A Write Si ng le Mask Registe r.... ............. .. ............. .. .... 421

13.2.7 DMACH_MODE—DMA Channel Mode Register ........................................... 422

13.2.8 DMA Clear Byte Pointer Register............................................................. 422

13.2.9 DMA Master Clear Register .................................................................... 423

13.2.11DMA_WRMSK—DMA Write All Mask Register ............................................ 423

13.3 Timer I/O Registers ......................................................................................... 424

13.3.1 TCW—Timer Control Word Register......................................................... 424

13.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register........................... 426

13.3.3 Counter Access Ports Register................................................................ 426

13.4 8259 Interrupt Controller (PIC) Registers ........................................................... 427

13.4.1 Interrupt Controller I/O MAP.................................................................. 427

13.4.2 ICW1—Initialization Command Word 1 Register........................................ 427

13.4.3 ICW2—Initialization Command Word 2 Register........................................ 428

13.4.4 I CW3—Master Controller Initialization Command

Word 3 Register................................................................................... 429

13.4.5 ICW3—Slave Controller Initialization Command

Word 3 Register................................................................................... 429

13.4.6 ICW4—Initialization Command Word 4 Register........................................ 429

13.4.7 O CW1—Operational Control Word 1 (Interrupt Mask)

13.4.9 OCW3—Operational Control Word 3 Register............................................ 431

13.4.10ELCR1—Master Controller Edge/Level Triggered Register ........................... 431

13.4.11ELCR2—Slave Controller Edge/Level Triggered Register............................. 432

13.5 Advanced Programmable Interrupt Controller (APIC)............................................ 432

13.5.1 APIC Register Map................................................................................ 432

13.5.2 IND—Index Register............................................................................. 433

13.5.3 DAT—Data Register.............................................................................. 434

13.5.4 EOIR—EOI Register .............................................................................. 434

13.5.5 ID—Identification Register..................................................................... 434

13.5.6 VER—Version Register .......................................................................... 435

13.5.7 REDIR_TBL—Redirec tion Tab l e..................... .. .. .. ............. ............. .. ........ 435

13.6 Real Time Clock Registers................................................................................. 437

13.6.1 I/O Register Address Map...................................................................... 437

13.6.2 Indexed Regi ste r s ......................... .. ........... .. ........... .. .......... .. ........... .. .. 437

13.7 Processor Interface Registers............................................................................ 441

13.7.1 NMI_SC—NMI Status and Control Re g i ster............. ... ............ ............. .. .... 441

13.7.3 PORT92— Init Register.......................................................................... 442

13.7.4 COPROC_ERR—Coprocessor Error Register .............................................. 442

13.8 Power Management Registers ........................................................................... 443

13.8.1 Power Management PCI Configuration Registers

(PM—D31:F0)...................................................................................... 443

13.8.2 APM I/O Decode................................................................................... 450

13.8.3 Power Management I/O Registers........................................................... 451

13.9 System Management TCO Registers................................................................... 469

13.9.1 TCO_RLD—TCO Timer Reload and Current Value Register .......................... 470

13.9.2 TCO_DAT_IN—TCO Data In Register....................................................... 470

13.9.3 TCO_DAT_OUT—TCO Data Out Register .................................................. 470

13.9.4 TCO1_STS—TCO1 Status Register .......................................................... 470

13.9.5 TCO2_STS—TCO2 Status Register .......................................................... 472

13.9.6 TCO1_CNT—TCO1 Control Register......................................................... 473

12 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

13.9.7 TCO2_CNT—TCO2 Control Register .........................................................473

13.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers .......................................474

13.9.9 TCO_WDCNT—TCO Watchdog Control Register .........................................474

13.9.10SW_IRQ_GEN—Software IRQ Generation Register.....................................474

13.9.11TCO_TMR—TCO Time r In itial Value Regi ster........... .. ............. ............. .. ....475

13.10 General Purpose I/O Registers (D31:F0).............................................................475

13.10.1GPIO_USE_SE L—GP IO Use Se le ct Reg iste r............... ............. ............. .. ....476

13.10.2GP_IO_SEL—GPIO Input/Output Select Register .......................................476

13.10.3GP_LVL—GPIO Level for Input or Output Register......................................477

13.10.4GPO_BLINK—GPO Blink Enable Register ...................................................477

13.10.5GP_SER_BLINK—GP Serial Blink .............................................................478

13.10.6GP_SB_CMDSTS—GP Serial Blink Command Status...................................478

13.10.7GP_SB_DATA—GP Serial Blink Data.........................................................479

13.10.8GPI_NMI_EN—GPI NMI Enable................................................................479

13.10.9GPI_NMI_STS—GPI NMI Status ..............................................................479

13.10.10GPI_INV—GPIO Signal Invert Register....................................................480

13.10.11GPIO_USE_SEL2—GPIO Use Select 2 Register.........................................480

13.10.12GP_IO_SEL2—GPIO Input/Output Select 2 Register .................................480

13.10.13GP_LVL2—GPIO Level for Input or Output 2 Register................................481

13.10.15GP_IO_SEL3—GPIO Input/Output Select 3 Register .................................481

13.10.16GP_LVL3—GPIO Level for Input or Output 3 Register................................482

13.10.17GP_RST_SEL1 — GPIO Reset Select.......................................................482

13.10.18GP_RST_SEL2 — GPIO Reset Select.......................................................483

13.10.19GP_RST_SEL3 — GPIO Reset Select.......................................................483

13.11 GPIO Serial Expander MMIO Registers ................................................................484

13.11.1GSX_CxCAP — GSX Capabilities Register 1...............................................484

13.11.2GSX_CxCAP2 — GSX Capabilities Register 2.............................................485

13.11.3GSX_CxGPILVL — GSX Input Level Register DW0......................................485

13.11.4GSX_CxGPILVL_DW1 — GSX Input Level Register DW1 ............. ................485

13.11.5GSX_CxGPOLVL — GSX Output Level Register DW0 ...................................485

13.11.6GSX_CxGPOLVL_DW1 — GSX Output Level Register DW1 ..........................486

13.11.7GSX_CxCMD — GSX Command Register ..................................................486

14 SATA Controller Registers (D31:F2) .......................................................................487

14.1 PCI Configuration Registers (SATA–D31:F2)........................................................487

14.1.1 VID—Vendor Identification Register (SATA—D31:F2).................................488

14.1.2 DID—Device Identification Register (SATA—D31:F2) .................................488

14.1.4 PCISTS — PCI Status Register (SATA–D31:F2) .........................................489

14.1.5 RID—Revision Identification Register (SATA—D3 1:F2) ... .............. ..............490

14.1.6 PI—Programming Interface Register (SATA–D31:F2) .................................490

14.1.7 SCC—Sub Class Code Re g ister (SA T A– D3 1 : F2).................. .. ............. .. ......491

14.1.8 BCC—Base Class Code Register

(SATA–D31:F2)....................................................................................491

14.1.9 PMLT—Primary Master Latency Timer Register

(SATA–D31:F2)....................................................................................492

14.1.10HTYPE—Header Type

(SATA–D31:F2)....................................................................................492

14.1.11PCMD_BAR—Primary Command Block Base Address

14.1.12PCNL_BAR—Primary Control Block Base Address Register

(SATA–D31:F2)....................................................................................492

14.1.13SCMD_BAR—Secondary Command Block Base Address

14.1.14SCNL_BAR—Secondary Control Block Base Address

14.1.15BAR — Legacy Bus Master Base Address Register

(SATA–D31:F2)....................................................................................493

Intel® C600 Series Chipset and Intel® X79 Express Chipset 13

Datasheet

14.1.16ABAR/SIDPBA1 — AHCI Base Address Register/Serial ATA

Index Data Pair Base Address (SATA–D31:F2).......................................... 494

14.1.17SVID—Subsystem Vendor Identification Register

(SATA–D31:F2).................................................................................... 495

14.1.18SID—Subsystem Identification Register (SATA–D31:F2)............................ 495

14.1.19CAP—Capabilitie s Pointer Register (SATA–D31:F2).................................... 495

14.1.20INT_LN—Interrupt Line Register (SATA–D31:F2) ...................................... 495

14.1.21INT_PN—Interrupt Pin Register (SATA–D31:F2)........................................ 495

14.1.22IDE_TIM — IDE Timing Register (SATA–D31:F2) ...................................... 496

14.1.23SIDETIM—Slave IDE Timing Register (SATA–D31:F2)................................ 496

14.1.24SDMA_CNT—Synchronous DMA Control Register

(SATA–D31:F2).................................................................................... 496

14.1.25SDMA_TIM—Synchronous DMA Timing Register

(SATA–D31:F2).................................................................................... 497

14.1.26IDE_CONFIG—IDE I/O Configuration Register

(SATA–D31:F2).................................................................................... 497

14.1.27PID—PCI Power Management Capability Identification

14.1.28PC—PCI Power Management Capabilities Register

(SATA–D31:F2).................................................................................... 498

14.1.29PMCS—PCI Power Management Control and Status

14.1.30MSICI—Message Signaled Interrupt Capability Identification

(SATA–D31:F2).................................................................................... 499

14.1.31MSIMC—Message Signaled Interrupt Message Control (SATA–D31:F2) ........ 500

14.1.33MSIMD—Message Signaled Interrupt Message Data (SATA–D31:F2)............ 501

14.1.34MAP—Address Map Register (SATA–D31:F2)............................................ 502

14.1.35PCS—Port Control and Status Register (SATA–D31:F2).............................. 503

14.1.36SCLKCG—SATA Clock Gating Control Register .......................................... 504

14.1.37SGC—SATA General Configuration Register.............................................. 505

14.1.38FLR CID—FLR Capability ID (SATA–D3 1:F2).............................................. 507

14.1.39FLRCLV—FLR Capability Length and Version (SATA–D31:F2) ...................... 507

14.1.40FLRC—FLR Control (SAT A– D3 1 :F2)......... .. .. .. ............. .. ............ ... ............ 507

14.1.41ATC—APM Trapping Control Register (SATA–D31:F2)................................ 508

14.1.42ATS—APM Trapping Status Register (SATA–D31:F2) ................................. 508

14.1.43SP Scratch Pad Register (SATA–D31:F2) ................................................. 508

14.1.44BFCS—BIST FIS Control/Status Register (SATA–D31:F2)........................... 509

14.1.45BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2)........................ 510

14.1.46BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2)........................ 510

14.2 Bus Master IDE I/O Registers (D31:F2) .............................................................. 511

14.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2).......................... 512

14.2.2 BMIS[P,S]—Bus Master IDE St atus Register (D31:F2) ......... ...................... 513

14.2.3 B MID[P,S]—Bus Master IDE Descriptor Table Pointer

14.2.4 AIR—AHCI Index Register (D31:F2)........................................................ 514

14.2.5 AIDR—AHCI Index Data Register (D31:F2) .............................................. 514

14.3 Serial ATA Index/Data Pair Superset Registers .................................................... 514

14.3.1 SINDX – Serial ATA Index (D31:F2)........................................................ 515

14.3.2 SDATA – Serial ATA Data (D31:F2)......................................................... 515

14.4 AHCI Registers (D31:F2).................................................................................. 519

14.4.1 AHCI Generic Host Control Registers (D31:F2) ......................................... 519

14.4.2 Port Registers (D31:F2) ........................................................................ 527

15 SATA Controller Registers (D31:F5)....................................................................... 541

15.1 PCI Configuration Registers (SATA–D31:F5)........................................................ 541

15.1.1 VID—Vendor Identification Register (SATA—D31:F5) ................................ 542

15.1.2 DID—Device Identification Register (SATA—D31:F5)................. ................ 542

15.1.3 PCICMD—PCI Command Register (SATA–D31:F5)..................................... 543

14 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

15.1.4 PCISTS — PCI Status Register (SATA–D31:F5) .........................................544

15.1.5 RID—Revision Identification Register (SATA—D3 1:F5) ... .............. ..............545

15.1.6 PI—Programming Interface Register (SATA–D31:F5) .................................545

15.1.7 SCC—Sub Class Code Re g ister (SA T A– D3 1 : F5).................. .. ............. .. ......545

15.1.8 BCC—Base Class Code Register

(SATA–D31:F5SATA–D31:F5).................................................................546

15.1.9 PMLT—Primary Master Latency Timer Register

(SATA–D31:F5)....................................................................................546

15.1.10PCMD_BAR—Primary Command Block Base Address

15.1.11PCNL_BAR—Primary Control Block Base Address Register

(SATA–D31:F5)....................................................................................546

15.1.12SCMD_BAR—Secondary Command Block Base Address

15.1.13SCNL_BAR—Secondary Control Block Base Address

15.1.14BAR — Legacy Bus Master Base Address Register

(SATA–D31:F5)....................................................................................547

15.1.15SIDPBA — SATA Index/Data Pair Base Address Register

(SATA–D31:F5)....................................................................................548

15.1.16SVID—Subsystem Vendor Identification Register

(SATA–D31:F5)....................................................................................548

15.1.17SID—Subsystem Identification Register (SATA–D31:F5).............................548

15.1.18CAP—Capabilities Pointer Register (SATA–D31:F5)....................................548

15.1.19INT_LN—Interrupt Line Register (SATA–D31:F5).......................................549

15.1.20INT_PN—Interrupt Pin Register (SATA–D31:F5)........................................549

15.1.21IDE_TIM — IDE Timing Register (SATA–D31:F5).......................................549

15.1.22SDMA_CNT—Synchronous DMA Control Register

(SATA–D31:F5)....................................................................................550

15.1.23SDMA_TIM—Synchronous DMA Timing Register

(SATA–D31:F5)....................................................................................550

15.1.24IDE_CONFIG—IDE I/O Configuration Register

(SATA–D31:F5)....................................................................................551

15.1.25PID—PCI Power Management Capability Identification

15.1.26PC—PCI Power Management Capabilities Register

(SATA–D31:F5)....................................................................................551

15.1.27PMCS—PCI Power Management Control and Status

15.1.28MAP—Address Map Register (SATA–D31:F5)16.........................................552

15.1.29PCS—Port Control and Status Register (SATA–D31:F5)..............................553

15.1.30SATACR0— SATA Capability Register 0 (SATA–D31:F5) .............................554

15.1.31SATACR1— SATA Capability Register 1 (SATA–D31:F5) .............................554

15.1.32FLRCID— FLR Capability ID (SATA–D31:F5) .............................................554

15.1.33FLRCLV— FLR Capability Length and Value (SATA–D31:F5) ........................555

15.1.34FLRCTRL— FLR Control (SATA–D31:F5) ...................................................555

15.1.35ATS—APM Trap p ing Status Reg iste r (SAT A– D 31 :F5 )................... .. ... .. ........555

15.1.36ATC—APM Trap ping Control (SATA– D3 1 : F5)................ ............ .. ............. ..556

15.2 Bus Master IDE I/O Registers (D31:F5)...............................................................556

15.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F5) ............... ...........557

15.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F5)................................557

15.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer

15.3 Serial ATA Index/Data Pair Superset Registers.....................................................558

15.3.1 SINDX—SATA Inde x Reg i ste r (D31 :F5).......... .. ............. .. ............ ... ..........558

15.3.2 SDATA—SATA Index Data Register (D31:F5)............................................559

16 Storage Controller Unit (SCU) Registers (SRV/WS SKUs Only)...............................563

Intel® C600 Series Chipset and Intel® X79 Express Chipset 15

Datasheet

16.1 Register Attribute Definitions ............................................................................ 563

16.2 SCU Physical Function Configuration Registers..................................................... 565

16.2.1 PCI Standard Head er Reg i ste rs .................. .. .. ............. ............ ... ............ 567

16.2.2 PF Power Management Capability Structure ............................................. 574

16.2.3 PF MSI-X Capability Structure ................................................................ 576

16.2.4 PF PCI Express* Capability Structure ...................................................... 577

16.2.5 PF Advanced Error Reporting Extended Capability Structure ....................... 582

16.2.6 PF Alternative Routing ID Extended Capability Structure............................ 586

16.2.7 PF SR-IOV Extended Capability Structure................................................. 587

16.2.8 PF TPH Requester Extended Capability Structure . ..................................... 592

16.3 SCU Virtual Function Configuration Registers....................................................... 594

16.3.1 PCI Standard Head er Reg i ste rs .................. .. .. ............. ............ ... ............ 595

16.3.2 VF MSI-X Capability Structure................................................................ 600

16.3.3 VF PCI Express* Capability Structure ...................................................... 602

16.3.4 VF Advanced Error Reporting Extended Capability Structure....................... 606

16.3.5 Advanced Error Header Log Registers...................................................... 611

16.3.6 VF Alternative Routing ID Extended Capability Structure............................ 612

16.3.7 VF TPH Requester Extended Capability Structure ...................................... 613

16.4 SCU SGPIO Memory Mapped Reg iste r s............. .. .. ............ ............. .. ............. .. .... 614

16.4.1 SGICR- SGPIO Interface Control Register ................................................ 614

16.4.2 SGPBR- SGPIO Programmable Blink Re g ister............. .. ............ .. ............. .. 615

16.4.3 SGSDLR- SGPIO Start Drive Lower Register............................................. 616

16.4.4 SGSDUR- SGPIO Start Drive Upper Register............................................. 617

16.4.5 SGSIDLR- SGPIO Input Data Lower Register ............................................ 618

16.4.6 SGSIDUR- SGPIO Input Data Upper Register............................................ 618

16.4.7 SGVSCR- SGPIO Vendor Specific Code Register........................................ 618

16.4.8 SGODSR[0-7]—SGPIO Output Data Select Register[0-7] ........................... 620

17 EHCI Controller Registers (D29:F0, D26:F0) .......................................................... 621

17.1 USB EHCI Configuration Registers

(USB EHCI—D29 : F0 , D26: F0 ).......... ............ ... ............ .. ............. .. ............. ........ 621

17.1.1 VID —Vendor Identification Register

(USB EHCI—D29 : F0, D26: F0 )......... ............. ............. .. ............ ... ............ 622

17.1.2 DID—Device Identification Register

(USB EHCI—D29 : F0, D26: F0 )......... ............. ............. .. ............ ... ............ 622

17.1.4 PCISTS—PCI Status Register

(USB EHCI—D29 : F0, D26: F0 )......... ............. ............. .. ............ ... ............ 624

17.1.6 PI—Programming Interface Register

(USB EHCI—D29 : F0, D26: F0 )......... ............. ............. .. ............ ... ............ 625

17.1.7 SCC—S ub Class Code Register

(USB EHCI—D29 : F0, D26: F0 )......... ............. ............. .. ............ ... ............ 625

17.1.8 BCC—Base Class Code Register

(USB EHCI—D29 : F0, D26: F0 )......... ............. ............. .. ............ ... ............ 625

17.1.9 PML T—Primary Master Latency Timer Register

(USB EHCI—D29 : F0, D26: F0 )......... ............. ............. .. ............ ... ............ 625

17.1.10HEADTYP—Header Type Register

(USB EHCI—D29 : F0, D26: F0 )......... ............. ............. .. ............ ... ............ 626

17.1.11MEM_BASE—Memory Base Address Register

(USB EHCI—D29 : F0, D26: F0 )......... ............. ............. .. ............ ... ............ 626

17.1.12SVID—USB EHCI Subsystem Vendor ID Register

(USB EHCI—D29 : F0, D26: F0 )......... ............. ............. .. ............ ... ............ 626

17.1.13SID—USB EHCI Subsystem ID Register

(USB EHCI—D29 : F0, D26: F0 )......... ............. ............. .. ............ ... ............ 627

17.1.14CAP_PTR—Capabilities Pointer Register

(USB EHCI—D29 : F0, D26: F0 )......... ............. ............. .. ............ ... ............ 627

17.1.15INT_LN—Interrupt Line Register

(USB EHCI—D29 : F0, D26: F0 )......... ............. ............. .. ............ ... ............ 627

16 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

17.1.16INT_PN—Interrupt Pin Register

(USB EHCI—D29:F0, D26:F0).................................................................627

17.1.17PWR_CAPID—PCI Power Management Capability ID

17.1.18NXT_PTR1—Next Item Pointer #1 Register

(USB EHCI—D29:F0, D26:F0).................................................................628

17.1.19PWR_CAP—Power Management Capabilities Register

(USB EHCI—D29:F0, D26:F0).................................................................628

17.1.20PWR_CNTL_STS—Power Management Control/

Status Register (USB EHCI—D29:F0, D26:F0) . .........................................629

17.1.21DEBUG_CAPID—Debug Port Capability ID Register

(USB EHCI—D29:F0, D26:F0).................................................................629

17.1.22NXT_PTR2—Next Item Pointer #2 Register

(USB EHCI—D29:F0, D26:F0).................................................................630

17.1.23DEBUG_BASE—Debug Port Base Offset Register

(USB EHCI—D29:F0, D26:F0).................................................................630

17.1.24USB_RELNUM—USB Release Number Register

(USB EHCI—D29:F0, D26:F0).................................................................630

17.1.25FL_ADJ—Frame Length Adjustment Register

(USB EHCI—D29:F0, D26:F0).................................................................630

17.1.26PWAKE_CAP—Port Wake Capability Register

(USB EHCI—D29:F0, D26:F0).................................................................631

17.1.27LEG_EXT_CAP—USB EHCI Legacy Support Extended

Capability Register (USB EHCI—D29:F0, D26:F0)......................................632

17.1.28LEG_EXT_CS—USB EHCI Legacy Support Extended

Control / Status Register (USB EHCI —D29:F0, D26:F0) .............................632

17.1.29SPECIAL_SMI—Intel® Specific USB 2.0 Intel® SMI

17.1.30ACCESS_CNTL—Access Control Register

(USB EHCI—D29:F0, D26:F0).................................................................635

17.1.31EHCIIR1—EHCI Initialization Register 1

(USB EHCI—D29:F0, D26:F0).................................................................635

17.1.32EHCIIR2—EHCI Initialization Register 2 (USB EHCI—D29:F0, D26:F0) .........636

17.1.33FLR_CID—Function Level Reset Capability ID

(USB EHCI—D29:F0, D26:F0).................................................................636

17.1.35FLR_CLV—Function Level Reset Capability Length and Version

(USB EHCI—D29:F0, D26:F0).................................................................637

17.1.36FLR_CTRL—Function Level Reset Control Register

(USB EHCI—D29:F0, D26:F0).................................................................637

17.1.37FLR_STAT—Function Level Reset Status Register

(USB EHCI—D29:F0, D26:F0).................................................................638

17.1.38EHCIIR3—EHCI Initialization Register 3 (USB EHCI—D29:F0, D26:F0) .........638

17.1.39EHCIIR4—EHCI Initialization Register 4 (USB EHCI—D29:F0, D26:F0) .........638

17.2 Memory-Mapped I/O Registers ..........................................................................639

17.2.1 Host Controller Capability Registers.........................................................639

17.2.2 Host Controller Operational Registers ......................................................642

17.2.3 USB 2.0-Based De b u g Port Reg i ste rs........... .. ............. .. ............ .. .............652

18 Intel® High Definition Audio Controller Registers (D27:F0)....................................655

18.1 Intel® HD Audio PCI Configuration Space (Intel HD Audio—D27:F0) .......................655

18.1.1 VID—Vendor Identification Register

(Intel® HD Audio Controller—D27:F0 ) ................... .. ... ............ ............. .. ..656

18.1.2 DID—Device Identification Register

(Intel® High Definition Audio Controller—D27:F0) .....................................657

18.1.3 PCICMD—PCI Command Register

(Intel® HD Audio Controller—D27:F0) ................. .. .. ... ............ .. ............. ..657

18.1.4 PCISTS—PCI Status Register

(Intel® HD Audio Controller—D27:F0) ................. .. .. ... ............ .. ............. ..658

Intel® C600 Series Chipset and Intel® X79 Express Chipset 17

Datasheet

18.1.5 RID—Revision Identification Register

(Intel® HD Audio Controller—D27:F0)..................................................... 658

18.1.6 PI—Programming Interface Register

(Intel® HD Audio Controller—D27:F0)..................................................... 658

18.1.8 BCC—Base Class Code Register

(Intel® HD Audio Controller—D27:F0)..................................................... 659

18.1.9 CLS—Cache Line Size Reg ister

(Intel® HD Audio Controller—D27:F0)..................................................... 659

18.1.10LT—Latency Timer Register

(Intel® HD Audio Controller—D27:F0)..................................................... 659

18.1.11HEADTYP—Header Type Register

(Intel® HD Audio Controller—D27:F0)..................................................... 659

18.1.13HDBARU—Intel® HD Audio Upper Base Address Register

(Intel® HD Audio Controller—D27:F0)..................................................... 660

18.1.14SVID—Subsystem Vendor Identification Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 660

18.1.16CAPPTR—Capabilities Pointer Register

(Intel® HD Audio Controller—D27:F0)..................................................... 661

18.1.17INTLN—Interrupt Line Register

(Intel® HD Audio Controller—D27:F0)..................................................... 661

18.1.18INTPN—Interrupt Pin Register

(Intel® HD Audio Controller—D27:F0)..................................................... 661

18.1.20HDINIT1—Intel® High Definition Audio Initialization Register 1

(Intel® High Definition Audio Controller—D27:F0)..................................... 662

18.1.21PID—PCI Power Management Capability ID Register

(Intel® HD Audio Controller—D27:F0)..................................................... 662

18.1.22PC—Powe r Management Capabilities Register

(Intel® HD Audio Controller—D27:F0)..................................................... 662

18.1.23PCS—Power Management Control and Status Register

(Intel® HD Audio Controller—D27:F0)..................................................... 663

18.1.24MID—MSI Capability ID Re gister

(Intel® HD Audio Controller—D27:F0)..................................................... 663

18.1.25MMC—MSI Message Control Register

(Intel® HD Audio Controller—D27:F0)..................................................... 664

18.1.26MMLA—MSI Message Lower Address Register

(Intel® HD Audio Controller—D27:F0)..................................................... 664

18.1.27MMUA—MSI Message Upper Address Register

(Intel® HD Audio Controller—D27:F0)..................................................... 664

18.1.28MMD—MSI Message Data Register

(Intel® HD Audio Controller—D27:F0)..................................................... 664

18.1.30PXC—PCI Express* Capabilities Register

(Intel® HD Audio Controller—D27:F0)..................................................... 665

18.1.31DEVCAP—Device Capabilities Register

(Intel® HD Audio Controller—D27:F0)..................................................... 665

18.1.32DEVC—Device Control Register

(Intel® HD Audio Controller—D27:F0)..................................................... 666

18.1.33DEVS—Device Status Register

(Intel® HD Audio Controller—D27:F0)..................................................... 666

18.1.34VCCAP—Virtual Channel Enhanced Capability Header

(Intel® HD Audio Controller—D27:F0)..................................................... 667

18.1.35PVCCAP1—Port VC Capability Register 1

(Intel® HD Audio Controller—D27:F0)..................................................... 667

18.1.36PVCCAP2 — Port VC Capability Register 2

(Intel® HD Audio Controller—D27:F0)..................................................... 667

18.1.37PVCCTL — Port VC Control Register

(Intel® HD Audio Controller—D27:F0)..................................................... 668

18.1.38PVCSTS—Port VC Status Register

(Intel® HD Audio Controller—D27:F0)..................................................... 668

18 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

18.1.39VC0CAP—VC0 Resource Capability Register

(Intel® HD Audio Controller—D27:F0 ) ................... .. ... ............ .. ............. ..668

18.1.40VC0CTL—VC0 Resource Control Register

(Intel® HD Audio Controller—D27:F0) ................. .. .. ... ............ .. ............. ..669

18.1.41VC0STS—VC0 Resource Status Register

(Intel® HD Audio Controller—D27:F0) ................. .. .. ... ............ .. ............. ..669

18.1.42VCiCAP—VCi Resource Capability Register

(Intel® HD Audio Controller—D27:F0) ................. .. .. ... ............ .. ............. ..669

18.1.43VCiCTL—VCi Resource Control Register

(Intel® HD Audio Controller—D27:F0) ................. .. .. ... ............ .. ............. ..670

18.1.44VCiSTS—VCi Resource Status Register

(Intel® HD Audio Controller—D27:F0) ................. .. .. ... ............ .. ............. ..670

18.1.45RCCAP—Root Complex Link Declaration Enhanced

Capability Header Register (Intel® HD Audio Controller—D27:F0)................670

18.1.46ESD—Element Self Description Register

(Intel® HD Audio Controller—D27:F0 ) ................... .. ... ............ ............. .. ..671

18.1.47L1DESC—Link 1 Description Register

(Intel® HD Audio Controller—D27:F0) ................. .. .. ... ............ .. ............. ..671

18.1.48L1ADDL—Link 1 Lower Address Register

(Intel® HD Audio Controller—D27:F0) ................. .. .. ... ............ .. ............. ..671

18.1.49L1ADDU—Link 1 Upper Address Register

(Intel® HD Audio Controller—D27:F0) ................. .. .. ... ............ .. ............. ..671

18.2 Intel® HD Audio Memory Mapped Configuration

Registers (Intel® HD Audio— D27:F0)................................................................672

18.2.1 GCAP—Global Capabilities Register

(Intel® HD Audio Controller—D27:F0).....................................................675

18.2.2 VMIN—Minor Version Register

(Intel® HD Audio Controller—D27:F0).....................................................675

18.2.3 VMAJ—Major Version Register

(Intel® HD Audio Controller—D27:F0).....................................................676

18.2.4 OUTPAY—Output Payload Capability Register

(Intel® HD Audio Controller—D27:F0).....................................................676

18.2.5 INPAY—Input Payload Capability Register

(Intel® HD Audio Controller—D27:F0).....................................................676

18.2.6 GCTL—Global Control Register

(Intel® HD Audio Controller—D27:F0).....................................................677

18.2.8 STATESTS—State Change Status Register

(Intel® HD Audio Controller—D27:F0).....................................................678

18.2.9 GSTS—Global Status Register

(Intel® HD Audio Controller—D27:F0).....................................................678

18.2.11INSTRMPAY—Input Stream Payload Capability

(Intel® HD Audio Controller—D27:F0).....................................................679

18.2.12INTCTL—Interrupt Control Register

(Intel® High Definition Audio Controller—D27:F0).....................................679

18.2.13INTSTS—Interrupt Status Register

(Intel® HD Audio Controller—D27:F0).....................................................680

18.2.15SSYNC—Stream Synchronization Register

(Intel® HD Audio Controller—D27:F0).....................................................681

18.2.16CORBLBASE—CORB Lower Base Address Register

(Intel® HD Audio Controller—D27:F0).....................................................681

18.2.17CORBUBASE—CORB Upper Base Address Register

(Intel® HD Audio Controller—D27:F0).....................................................682

18.2.18CORBWP—COR B Wri te Poi nter Register

(Intel® HD Audio Controller—D27:F0).....................................................682

18.2.19CORBRP—CORB Read Pointer Register

(Intel® High Definition Audio Controller—D27:F0).....................................682

18.2.21CORBST—CORB Status Register

(Intel® HD Audio Controller—D27:F0).....................................................683

Intel® C600 Series Chipset and Intel® X79 Express Chipset 19

Datasheet

18.2.22CORBSIZE—CORB Size Register

Intel® HD Audio Controller—D27:F0using) .............................................. 683

18.2.24RIRBUBASE—RIRB Upper Base Addr ess Register

(Intel® HD Audio Controller—D27:F0) .................................................... 684

18.2.25RIRBWP—RIRB Write Pointer Register

(Intel® HD Audio Controller—D27:F0) .................................................... 684

18.2.27RIRBCT L—RIRB Control Register

(Intel® HD Audio Controller—D27:F0) .................................................... 685

18.2.29RIRBSIZE—RIRB Size Register

(Intel® HD Audio Controller—D27:F0) .................................................... 686

18.2.30IC—Immediate Command Register

(Intel® HD Audio Controller—D27:F0) .................................................... 686

18.2.31IR—Immediate Response Register

(Intel® HD Audio Controller—D27:F0) .................................................... 687

18.2.32ICS—Immediate Command Status Register

(Intel® HD Audio Controller—D27:F0) .................................................... 687

18.2.33DPLBASE—DMA Position Lower Base Address Register

(Intel® HD Audio Controller—D27:F0) .................................................... 687

18.2.34DPUBASE—DMA Position Upper Base Address Register

(Intel® HD Audio Controller—D27:F0) .................................................... 688

18.2.35SDCTL—Stream Descriptor Control Register

(Intel® HD Audio Controller—D27:F0) .................................................... 688

18.2.36SDSTS—Stream Descriptor Status Register

(Intel® HD Audio Controller—D27:F0) .................................................... 689

18.2.37SDLPIB—Stream Descriptor Link Position in Buffer

18.2.38SDCBL—Stream Descriptor Cyclic Buffer Length Register

(Intel® High Definition Audio Controller—D27:F0) .................................... 690

18.2.39SDLVI—Stream Descriptor Last Valid Index Register

(Intel® High Definition Audio Controller—D27:F0) .................................... 691

18.2.40SDFIFOW—Stream Descriptor FIFO Watermark Register

(Intel® HD Audio Controller—D27:F0) .................................................... 691

18.2.41ISDFIFOS—Stream Descriptor FIFO Size Register - Input

Streams (Intel® High Definition Audio Controller—D27:F0)........................ 692

18.2.42SDFIFOS—Stream Descriptor FIFO Size Register - Output

Streams (Intel® High Definition Audio Controller—D27:F0)........................ 692

18.2.43SDFMT—Stream Descriptor Format Register

(Intel® High Definition Audio Controller—D27:F0) .................................... 693

18.2.44SDBDPL—Stream Descriptor Buffer Descriptor List Pointer

Lower Base Address Register (Intel® High Definition

Audio Controller—D27:F0)..................................................................... 694

19 SMBus Controller Registers (D31:F3) .................................................................... 695

19.1 PCI Configuration Registers (SMBus—D31:F3)..................................................... 695

19.1.1 VID—Vendor Identification Register (SMBus—D31:F3)............................... 695

19.1.2 DID—Device Identification Register (SM Bus—D 31:F3)............... ................ 696

19.1.3 PCICMD—PCI Command Register (SMBus—D31:F3).................................. 696

19.1.4 PCISTS—PCI Status Register (SMBus—D31:F3)........................................ 697

19.1.5 RID—Revision Identification Register (SMBus—D31:F3)............................. 697

19.1.6 PI—Programming Interface Register (SMBus—D31:F3).............................. 698

19.1.7 SCC—Sub Class Code Register (SMBus—D31:F3)...................................... 698

19.1.8 BCC—Base Class Code Register (SMBus—D31:F3) .................................... 698

19.1.9 SMBMBAR0—D31_F3_SMBus Memory Base Address 0 (SMBus—D31:F3) ..... 698

19.1.10SMBMBAR1—D31_F3_SMBus Memory Base Address 1 (SMBus—D31:F3) ..... 699

19.1.11SMB_BASE—SMBus Base Address Register

(SMBus—D31:F3)................................................................................. 699

19.1.12SVID—Subsystem Vendor Identification Register

(SMBus—D31:F2/F4)............................................................................ 699

20 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

19.1.13SID—Subsystem Identification Register

(SMBus—D31:F2/F4).............................................................................699

19.1.15INT_PN—Interrupt Pin Register (SMBus—D31:F3).....................................700

19.1.16HOSTC—Host Configuration Register (SMBus—D3 1:F3)..............................700

19.2.2 HST_CNT—Host Control Register (SMBus—D31:F3)...................................703

19.2.3 HST_CMD—Host Comm and Reg iste r (SMBus—D31:F3)....... .. ............. .. ......704

19.2.4 XMIT_SLVA—Transmit Slave Address Register

(SMBus—D31:F3).................................................................................704

19.2.5 HST_D0—Host Data 0 Register (SMBus—D31:F3) .....................................704

19.2.6 HST_D1—Host Data 1 Register (SMBus—D31:F3) .....................................704

19.2.7 Host_BLOCK_DB—Host Block Data Byte Register

(SMBus—D31:F3).................................................................................705

19.2.8 PEC—Packet Error Check (PEC) Register

(SMBus—D31:F3).................................................................................705

19.2.9 RCV_SLVA—Receive Slave Address Register

(SMBus—D31:F3).................................................................................705

19.2.10SLV_DATA—Receive Slave Data Register (SMBus—D31:F3)........................706

19.2.11AUX_STS—Auxiliary Status Register (SMBus—D31:F3) ..............................706

19.2.12AUX_CTL—Auxiliary Control Register (SMBus—D31:F3) .............................706

19.2.13SMLINK_PIN_CTL—SMLink Pin Control Register

(SMBus—D31:F3).................................................................................707

19.2.14SMBus_PIN_CTL—SMBus Pin Control Register

(SMBus—D31:F3).................................................................................707

19.2.15SLV_STS—Slav e Status Re g ister (SM B us—D31:F3) ...................................708

19.2.16SLV_CMD—Slave Command Register (SMBus—D31:F3) ............... ..............708

19.2.17NOTIFY_DADDR—Notify Device Address Register

(SMBus—D31:F3).................................................................................709

19.2.19NOTIFY_DHIGH—Notify Data High Byte Register

(SMBus—D31:F3).................................................................................709

20 PCI Express* Configuration Registers ....................................................................711

20.1 PCI Express* Configuration Registers

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................................711

20.1.1 VID—Vendor Identification Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)...............................713

20.1.2 DID—Device Identification Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)...............................713

20.1.5 RID—Revision Identification Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)...............................715

20.1.7 SCC—Sub Class Code Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)...............................716

20.1.8 BCC—Base Class Code Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)...............................716

20.1.9 CLS—Cache Line Size Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)...............................716

20.1.10PLT—Primary Latency Timer Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)...............................716

20.1.11HEADTYP —He ad er Type Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)...............................717

20.1.12BNUM—Bus Number Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)...............................717

20.1.13SLT—Secondary Latency Timer

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)...............................717

20.1.14IOBL—I/O Base and Limit Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)...............................717

20.1.15SSTS—Secondary Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)...............................718

20.1.16MBL—Memory Base and Limit Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)...............................718

Intel® C600 Series Chipset and Intel® X79 Express Chipset 21

Datasheet

20.1.17PMBL—Prefetchable Memory Base and Limit Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)........... .................... 719

20.1.18PMBU32—Prefetchable Memory Base Upper 32 Bits

20.1.19PMLU32—Prefetchable Memory Limit Upper 32 Bits

20.1.20CAPP—Capabilities List Pointer Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)........... .................... 720

20.1.21INTR—Interrupt Information Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)........... .................... 720

20.1.22BCTRL—Bridge Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)........... .................... 721

20.1.23CLIST—Capabilities List Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 721

20.1.25DCAP—Device Capabilities Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 722

20.1.26DCTL—Device Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 722

20.1.27DSTS—Device Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 723

20.1.28LCAP—Link Capabilities Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 724

20.1.29LCTL—Link Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 726

20.1.30LSTS—Link Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 727

20.1.31SLCAP—Slot Capabilities Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 728

20.1.32SLCTL—Slot Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 728

20.1.33SLSTS—Slot Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 729

20.1.34RCTL—Root Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 730

20.1.35RSTS—Root Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 730

20.1.36DCAP2—Device Capabilities 2 Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 731

20.1.37DCTL2—Device Control 2 Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 731

20.1.39LSTS2—Link Status 2 Register

(PCI Express*— D28:F0/F1/F2/F3/F4/F5/F6/F7)....................................... 732

20.1.40MID—Message Signaled Interrupt Identifiers Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 732

20.1.41MC—Message Signaled Interrupt Message Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 733

20.1.42MA—Message Signaled Interrupt Message Address

20.1.43MD—Message Signaled Interrupt Message Data Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 733

20.1.44SVCAP—Subsyste m Vendor Capa bility Registe r

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 733

20.1.45SVID—Subsystem Vendor Identification Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 734

20.1.46PMCAP—Power Management Capability Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 734

20.1.47PMC—PCI Powe r Management Capabilities Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 734

22 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

20.1.49MPC2—Miscellaneous Port Configuration Register 2

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................735

20.1.50MPC—Miscellaneous Port Configuration Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................736

20.1.51SMSCS—SMI/SCI Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................738

20.1.52RPDCGEN—Root Port Dynamic Clock Gating Enable

(PCI Express-D28:F0/F1/F2/F3/F4/F5/F6/F7) ...........................................739

20.1.53PECR1—PCI Express* Configuration Register 1

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................739

20.1.55UES—Uncorrectable Error Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................740

20.1.57UEV — Uncorrectable Error Severity

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................742

20.1.58CES — Correctable Error Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................742

20.1.59CEM — Correctable Error Mask Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................743

20.1.60AECC — Advanced Error Capabilities and Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................743

20.1.61RES — Root Error Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................744

20.1.62PEETM — PCI Express* Extended Test Mode Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................744

21 High Precision Event Timer Registers.....................................................................745

21.1 Memory Mapped Registers ................................................................................745

21.1.1 GCAP_ID—General Capabilities and Identification Register .........................746

21.1.3 GINTR_STA—General Interrupt Status Register.........................................747

21.1.5 TIMn_CONF—Timer n Configuration and Capabilities Register .....................748

21.1.6 TIMn_COMP—Timer n Comparator Value Register .....................................750

21.1.7 TIMERn_PROCMSG_ROUT—

Timer n Processor Message Interrupt Rout Register...................... ... .. .. .. .. ..751

22 Serial Peripheral Interface (SPI) ...........................................................................753

22.1 Serial Peripheral Interface Memory Mapped Configuration Registers........... .............753

22.1.1 BFPR –BIOS Flash Primary Region Register

(SPI Memory Mapped Configuration Registers)..........................................754

22.1.3 HSFC—Hardware Sequencing Flash Control Register

(SPI Memory Mapped Configuration Registers)..........................................756

22.1.4 FADDR—Flash Address Register

(SPI Memory Mapped Configuration Registers)..........................................756

22.1.6 FDATAN—Flash Data [N] Register

(SPI Memory Mapped Configuration Registers)..........................................757

22.1.8 FREG0—Flash Region 0 (Flash Descriptor) Register

(SPI Memory Mapped Configuration Registers)..........................................758

22.1.10FREG2—Flash Region 2 (Intel® ME) Register

(SPI Memory Mapped Configuration Registers)..........................................759

22.1.11FREG3—Flash Region 3 (GbE) Register

(SPI Memory Mapped Configuration Registers)..........................................759

22.1.12FREG4—Flash Region 4 (Platform Data) Register

(SPI Memory Mapped Configuration Registers)..........................................760

22.1.13PR0—Protected Range 0 Register

(SPI Memory Mapped Configuration Registers)..........................................760

22.1.14PR1—Protected Range 1 Register

(SPI Memory Mapped Configuration Registers)..........................................761

22.1.15PR2—Protected Range 2 Register

(SPI Memory Mapped Configuration Registers)..........................................761

Intel® C600 Series Chipset and Intel® X79 Express Chipset 23

Datasheet

22.1.17PR4—Protected Range 4 Register

(SPI Memory Mapped Conf iguration Registers) .......................... ... ............ 762

22.1.19SSFC—Software Sequencing Flash Control Register

(SPI Memory Mapped Conf iguration Registers) .......................... ... ............ 764

22.1.20PREOP—Prefix Opcode Configuration Register

(SPI Memory Mapped Conf iguration Registers) .......................... ... ............ 765

22.1.21OPTYPE—Opcode Type Configuration Register

(SPI Memory Mapped Conf iguration Registers) .......................... ... ............ 765

22.1.22OPMENU—Opcode Menu Configuration Register

(SPI Memory Mapped Conf iguration Registers) .......................... ... ............ 766

22.1.23FDOC—Flash Descriptor Observability Control Register

(SPI Memory Mapped Conf iguration Registers) .......................... ... ............ 766

22.1.24FDOD—Flash Descriptor Observability Data Register

(SPI Memory Mapped Conf iguration Registers) .......................... ... ............ 767

22.1.25AFC—Additional Flash Control Register

(SPI Memory Mapped Conf iguration Registers) .......................... ... ............ 767

22.1.26LVSCC— Host Lower Vendor Specific Component Capabilities Register

(SPI Memory Mapped Conf iguration Registers) .......................... ... ............ 767

22.1.27UVSCC— Host Upper Vendor Specific Component Capabilities Register

(SPI Memory Mapped Conf iguration Registers) .......................... ... ............ 768

22.1.28FPB — Flash Partition Boundary

(SPI Memory Mapped Conf iguration Registers) .......................... ... ............ 769

22.1.29SRDL — Soft Reset Data Lock

(SPI Memory Mapped Conf iguration Registers) .......................... ... ............ 770

22.1.30SRDC — Soft Reset Data Control

(SPI Memory Mapped Conf iguration Registers) .......................... ... ............ 770

22.1.31SRD — Soft Reset Data

(SPI Memory Mapped Conf iguration Registers) .......................... ... ............ 770

22.2 Flash Descriptor Records.................................................................................. 770

22.4 GbE SPI Flash Program Registers....................................................................... 771

22.4.2 HSFS—Hardware Sequencing Flash Status Register

(GbE LAN Memory Mapped Configuration Registers).................................. 772

22.4.3 HSFC—Hardware Sequencing Flash Control Register

(GbE LAN Memory Mapped Configuration Registers).................................. 773

22.4.4 FADDR—Flash Address Register

(GbE LAN Memory Mapped Configuration Registers).................................. 773

22.4.6 FRAP—Flash Regions Access Permissions Register

(GbE LAN Memory Mapped Configuration Registers).................................. 774

22.4.8 FREG1—Flash Region 1 (BIOS Descriptor) Register

(GbE LAN Memory Mapped Configuration Registers).................................. 775

22.4.9 FREG2—Flash Region 2 (Intel® ME) Register

(GbE LAN Memory Mapped Configuration Registers).................................. 775

22.4.11PR0—Protected Range 0 Register

(GbE LAN Memory Mapped Configuration Registers).................................. 776

22.4.13SSFS—Software Sequencing Flash Status Register

(GbE LAN Memory Mapped Configuration Registers).................................. 777

22.4.14SSFC—Software Sequencing Flash Control Register

(GbE LAN Memory Mapped Configuration Registers).................................. 778

22.4.15PREOP—Prefix Opcode Configuration Register

(GbE LAN Memory Mapped Configuration Registers).................................. 779

22.4.16OPTYPE—Opcode Type Configuration Register

(GbE LAN Memory Mapped Configuration Registers).................................. 779

22.4.17OPMENU—Opcode Menu Configuration Register

(GbE LAN Memory Mapped Configuration Registers).................................. 780

23 Thermal Sensor Registers (D31:F6)....................................................................... 781

23.1 PCI Bus Configuration Registers ........................................................................ 781

23.1.1 VID—Vendor Identification Register ........................................................ 782

23.1.2 DID—Device Identification Registe r........... ............ ... ............ ............. .. .... 782

24 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

23.1.3 CMD—Command Register ......................................................................782

23.1.4 STS—Status Register ............................................................................783

23.1.5 RID—Revision Identification Register.......................................................783

23.1.6 PI— Programming Interf ace Reg i ste r........... .. .. ............. ............ .. .............783

23.1.7 SCC—Sub Class Code Re g i ster............. ... .. .. ............ ... ............ .. ............. ..784

23.1.8 BCC—Base Class Code Register ................ .. .. ............. .. ............ ............. ..784

23.1.9 CLS—Cache Line Size Register................................................................784

23.1.10LT—Latency Timer Register....................................................................784

23.1.11HTYPE—He ad er Type Register ......... .. .. ... ............ .. ............. .. ............. .. ....784

23.1.12TBAR—Thermal Base Register ................................................................785

23.1.13TBARH—Thermal Base High DWord Register.............................................785

23.1.14SVID—Subsystem Vendor ID Register .....................................................785

23.1.16CAP_PTR —Capabilities Pointer Register...................................................786

23.1.17Offset 3Ch – INTLN—Interrupt Li ne Reg iste r................ ............ .. ............. ..786

23.1.18INTPN—Interrupt Pin Register ................................................................786

23.1.19TBARB—BIOS Assigned Thermal Base Address Register .............................787

23.1.20TBARBH—BIOS Assigned Thermal Base High DWord Register ......................787

23.1.21PID—PCI Power Management Capability ID Register ..................................787

23.1.22PC—Power Management Capabilities Register ...........................................788

23.1.23PCS—Power Management Control And Status Register............ ............. .. ....788

23.2 Thermal Memory Mapped Configuration Registers

(Thermal Sensor – D31:F26).............................................................................789

23.2.1 TSIU—Thermal Sensor In Use Register ....................................................789

23.2.3 TSS—Thermal Sensor Status Register ......................................................790

23.2.4 TSTR — Thermal Sensor Thermometer Read Register ................................790

23.2.5 TSTTP—Thermal Sensor Temperature Trip Point Register ...........................791

23.2.6 TSCO—Thermal Sensor Catastrophic Lock-Down Register...........................791

23.2.7 TSES—Thermal Sensor Error Status Register............................................791

23.2.8 TSGPEN—Thermal Sensor General Purpose Event Enable Register...............792

23.2.9 TSPC—Thermal Sensor Policy Control Register..........................................793

23.2.10PTA—PCH Temperature Adjust Register ...................................................794

23.2.11TRC—Thermal Reporting Control Register.................................................794

23.2.12AE—Alert Enable Register ......................................................................795

23.2.13PTL—Processor Temperature Limit Register..............................................795

23.2.14PTV—Processor Temperature Value Register.............................................795

23.2.15TT—Thermal Throttling Register..............................................................795

23.2.16PHL—PCH Hot Level Register..................................................................796

23.2.17TSPIEN—Thermal Sensor PCI Interrupt Enable Register .............................796

23.2.18TSLOCK—Thermal Sensor Register Lock Control Reg ister .......... .. .. .............797

23.2.19TTC2—Thermal Compares 2 Register.......................................................797

23.2.20DTV—DIMM Temperature Values Register ................................................797

23.2.21ITV—Internal Temperature Values Register ..............................................798

24 Intel® Management Engine Subsystem Registers (D22:F[3:0]) .............................799

24.1 First Intel® Management Engine Interface (Intel MEI) Configuration Registers

(Intel MEI 1 — D22:F0) ....................................................................................799

24.1.1 PCI Configuration Registers (Intel MEI 1— D22:F0) ...................................799

24.1.2 MEI0_MBAR—MEI 1MMIO Registers (SRV/WS SKUs Only) ..........................808

24.2 Second Host Embedded Controller Interface (Intel MEI 2) Conf i gu r ation

Registers (Intel MEI 2—D22 : F1) .......................... .. ............ ... ............ ............. .. ..810

24.2.1 PCI Configuration Registers (Intel MEI 2 — D22:F0) ..................................810

24.2.2 MEI1_MBAR—Intel MEI 2MMIO Registers .................................................818

24.3 IDE Function for Remote Boot and Installations

PT IDER Registers (IDER — D22:F2)...................................................................820

24.3.1 PCI Configuration Registers (IDER—D22:f2).............................................820

24.3.2 IDER BAR0 Registers.............................................................................827

24.3.3 IDER BAR1 Registers.............................................................................836

Intel® C600 Series Chipset and Intel® X79 Express Chipset 25

Datasheet

24.3.4 IDER BAR4 Registers ............................................................................ 837

24.4 Serial Port for Remote Keyboard and Text (KT)

Redirection (KT — D22:F3)...................... .. ............. .. ............. .. ............. ............ 842

24.4.1 PCI Configuration Registers (KT — D22:F3) ............................................. 842

24.4.2 KT IO/ Memory Mapped Device Registers................................................. 848

25 PCI Express* UpStream Configuration Registers (PCH)

(SRV/WS SKUs only) ............................................................................................. 853

25.1 PCI Express* Upstream Configuration Registers (PCI Express*—D0:F0).................. 853

25.1.1 VID —Vendor Identification Register

(PCI Express*—D0:F0) ......................................................................... 855

25.1.2 DID—Device Identification Register

(PCI Express*—D0:F0) ......................................................................... 855

25.1.3 PCICMD—PCI Command Register

(PCI Express*—D0:F0) ......................................................................... 856

25.1.5 RID—Revision Identification Register

(PCI Express*—D0:F0) ......................................................................... 858

25.1.6 PI—Programming Interface Register

(PCI Express*—D0:F0) ......................................................................... 858

25.1.7 CLS—Cache Line Size Reg ister

(PCI Express*—D0:F0) ......................................................................... 858

25.1.8 PLT—Primary Latency Timer Register

(PCI Express*—D0:F0) ......................................................................... 858

25.1.10EXPPTMBAR_U—Express Port Memory Base Address

25.1.11PRIBUS—Primiary Bus Number Register

(PCI Express*—D0:F0........................................................................... 859

25.1.12SECBUS—Secondary Bus Number Register

(PCI Express*—D0:F0) ......................................................................... 860

25.1.13SUBBus—Subordinate Bus Number Register

(PCI Express*—D0:F0) ......................................................................... 860

25.1.14IOBL—I/O Base Register

(PCI Express*—D0:F0) ......................................................................... 860

25.1.15IOLIMIT—I/O Limit Register

(PCI Express*—D0:F0) ......................................................................... 860

25.1.16SSTS—Secondary Status Register (PCI Express*—D0:F0).......................... 861

25.1.18MEMLIMIT—Memory Limit Register

(PCI Express*—D0:F0) ......................................................................... 862

25.1.19PFBASE—Prefetchable Memory Base

(PCI Express*—D0:F0) ......................................................................... 862

25.1.20PFLIMIT—Prefetchable Limit Register

(PCI Express*—D0:F0) ......................................................................... 862

25.1.21PMBU32—Prefetchable Memory Base Upper 32 Bits

25.1.22PMLU32—Prefetchable Memory Limit Upper 32 Bits

25.1.23CAPP—Capabilities List Pointer Register

(PCI Express*—D0:F0) ......................................................................... 863

25.1.24INTR—Interrupt Information Register

(PCI Express*—D0:F0) ......................................................................... 863

25.1.25BCTRL—Bridge Control Register

(PCI Express*—D0:F0) ......................................................................... 864

25.1.26CLIST—Capabilities List Register

(PCI Express*—D0:F0) ......................................................................... 865

25.1.27XCAP—PCI Express* Capabilities Register

(PCI Express*—D0:F0) ......................................................................... 865

25.1.28DCAP—Device Capabilities Register

(PCI Express*—D0:F0) ......................................................................... 866

25.1.29DCTL—Device Control Register (PCI Express*—D0:F0).............................. 866

26 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

25.1.30DSTS—Device Status Register (PCI Express*—D0:F0) ...............................867

25.1.31LCAP—Link Capabilities Register

(PCI Express*—D0:F0)..........................................................................867

25.1.32LCTL—Link Control Register (PCI Express*—D:F0) ....................................868

25.1.33LSTS—Link Status Register

(PCI Express*—D0:F0)..........................................................................869

25.1.34DCAP2—Device Capabilities 2 Register

(PCI Express*—D0:F0)..........................................................................870

25.1.35DCTL2—Device Control 2 Register

(PCI Express*—D0:F0)..........................................................................871

25.1.36DEVSTS2—Device Status 2 Register

(PCI Express*—D0:F0)..........................................................................871

25.1.37L2—Link Control 2 Register (PCI Express*—D0:F0) ...................................872

25.1.38LINKSTS2—Link STatus2 Register

(PCI Express*—D0:F0)..........................................................................873

25.1.39PMCAP—Power Management Capability Register

(PCI Express*—D0:F0)..........................................................................873

25.1.40PMC—PCI Power Management Capabilities Register

(PCI Express*—D0:F0)..........................................................................873

25.1.41PMCSR—PCI Power Management Control and Status

25.1.42PMBSE—Power Management Bridge Support Extensions

25.1.43SVCAP—Subsystem Capability List Register

(PCI Express*—D0:F0)..........................................................................875

25.1.44SVID—Subsystem Vendor ID Register

(PCI Express*—D0:F0)..........................................................................875

25.1.45SVID—Subsystem ID Register

(PCI Express*—D0:F0)..........................................................................875

25.1.46AERCAPHDR—Advanced Error Reporting Capabilities

Header Register (PCI Express*—D0:F0)...................................................875

25.1.49UEV — Uncorrectable Error Severity

(PCI Express*—D0:F0)..........................................................................877

25.1.50CES—Correctable Error Status Register

(PCI Express*—D0:F0)..........................................................................878

25.1.51CEM—Correctable Error Mask Register

(PCI Express*—D0:F0)..........................................................................879

25.1.52AECC — Advanced Error Capabilities and Control Register

(PCI Express*—D0:F0)..........................................................................879

25.1.53AEHRDLOG [1–4]— Advanced Error Header Log

(PCI Express*—D0:F0)..........................................................................880

25.1.54ERRUNCDETMSK— Uncorrectable Error Detect Mask Register

(PCI Express*—D0:F0)..........................................................................880

25.1.55ERRCORDETMSK— Correctable Error Detect Mask Register

(PCI Express*—D0:F0)..........................................................................881

25.1.57MCSTCAP—Multicast Capability Register

(PCI Express*—D0:F0)..........................................................................882

25.1.58MCSTCTL—Multicast Control Register

(PCI Express*—D0:F0)..........................................................................882

25.1.60MCSTUBAR—Multicast Upper Base Address Register

(PCI Express*—D0:F0)..........................................................................883

25.1.61MCSTRCV—Multicast Receive Register

(PCI Express*—D0:F0)..........................................................................883

25.1.62MCSTRCV2—Multicast Receive 2 Register

(PCI Express*—D0:F0)..........................................................................883

25.1.64MCSTBLKALL2—Multicast Block All 2 Register

(PCI Express*—D0:F0)..........................................................................884

25.1.65MCSTBLKUT—Multicast Block Untranslated Register

(PCI Express*—D0:F0)..........................................................................884

Intel® C600 Series Chipset and Intel® X79 Express Chipset 27

Datasheet

25.1.66MCSTBLKUT2—Multicast Block Untranslated 2 Register

(PCI Express*—D0:F0) ......................................................................... 884

25.1.68MCSTUOLBAR—Multicast Upper Overlay Base Address

26 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers

(SRV/WS SKUs Only)............................................................................................. 887

26.1 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers

(PCI Express*—B0:D17:F0/Bn+1:D8:F0) ........................................................... 887

26.2 PCI Express* Virtual Root Port/ Virtual Switch Port Configuration Registers

(PCI Express*—B0:D17:F0/Bn+1:D8:F0) ........................................................... 887

26.2.1 VID —Vendor Identification Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 889

26.2.2 DID—Device Identification Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 889

26.2.6 PI—Programming Interface Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 892

26.2.7 CLS—Cache Line Size Reg ister

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 892

26.2.8 PLT—Primary Latency Timer Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 892

26.2.9 HEAD TYP—Header Type Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 893

26.2.10PRIBUS—Primiary Bus Number Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 893

26.2.11SECBUS—Secondary Bus Number Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 893

26.2.12SUBBus—Subordinate Bus Number Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 893

26.2.13IOBL—I/O Base Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 894

26.2.14IOBL—I/O Limit Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 894

26.2.15SSTS—Secondary Status Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 894

26.2.16MBL—Memory Base Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 895

26.2.17MBL—Memory Limit Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 895

26.2.19PMBL—Prefetchable Limit Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 896

26.2.20PMBU32—Prefetchable Memory Base Upper 32 Bits

26.2.21PMLU32—Prefetchable Memory Limit Upper 32 Bits

26.2.22CAPP—Capabilities List Pointer Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 897

26.2.23INTR—Interrupt Information Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 897

26.2.24BCTRL—Bridge Control Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 897

26.2.26XCAP—PCI Express* Capabilities Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 899

26.2.27DCAP—Device Capabilities Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 899

26.2.28DCTL—Device Control Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 900

26.2.29DSTS—Device Status Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 901

28 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

26.2.30LCAP—Link Capabilities Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D8:F0)...............901

26.2.31LCTL—Link Control Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D8:F0)...............902

26.2.32LSTS—Link Status Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D8:F0)...............903

26.2.33ROOTCTL—Root Control Register

(Virtual Root Port—B0:D17:F0)...............................................................903

26.2.34ROOTCAP—Root Capabilities Register

(Virtual Root Port—B0:D17:F0)...............................................................904

26.2.35ROOTSTS—Root Status Register

(Virtual Root Port—B0:D17:F0)...............................................................904

26.2.37DCTL2—Device Control 2 Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D8:F0)...............905

26.2.38DEVSTS2—Device Status 2 Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D8:F0)...............906

26.2.40LINKSTS2—Link STatus2 Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D8:F0)...............907

26.2.41PMCAP—Power Management Capability Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D8:F0)...............907

26.2.42PMC—PCI Power Management Capabilities Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D8:F0)...............907

26.2.43PMCSR—PCI Power Management Control and Status

26.2.44PMBSE—Power Management Bridge Support Extensions

26.2.45SVCAP—Subsystem Capability List Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D8:F0)...............909

26.2.46SVID—Subsystem Vendor ID Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D8:F0)...............909

26.2.47SVID—Subsystem ID Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D8:F0)...............909

26.2.48MSICAPLST—MSI Capability List Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D8:F0)...............909

26.2.49MSICTL—MSI Message Control Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D8:F0)...............910

26.2.51MSIDATA—MSI Message Data Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D8:F0)...............911

26.2.52AERCAPHDR—Advanced Error Reporting Capabilities

Header (Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D 8:F0 )....911

26.2.53UES—Uncorrectable Error Status Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D8:F0)...............912

26.2.54UEM—Uncorrectable Error Mask

(Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D8:F0)...............913

26.2.55UEV — Uncorrectable Error Severity

(Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D8:F0)...............914

26.2.56CES—Correctable Error Status Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D8:F0)...............915

26.2.57CEM—Correctable Error Mask Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D8:F0)...............915

26.2.58AECC—Advanced Error Capabilities and Control Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D8:F0)...............916

26.2.59AEHRDLOG [1-4]—Advanced Error Header Log

(Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D8:F0)...............916

26.2.61ROOTERRSTS—Root Error Status Register

(Virtual Root Port—B0:D17:F0)...............................................................917

26.2.63ACSCAPHDR—Access Control Services Extended Capabilities Header

(Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D8:F0)...............918

Intel® C600 Series Chipset and Intel® X79 Express Chipset 29

Datasheet

26.2.64ACSCAP— Access Control Services Capability Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 918

26.2.65ACSCAP—Access Control Services Capability Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 919

26.2.66ERRUNCDETMSK—Uncorrectable Error Detect Mask Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 919

26.2.67ERRCORDETMSK—Correctable Error Detect Mask Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Po rt—BN+1 :D 8:F0 ).......... .. .. 921

27 Integrated Device Fabric (IDF) SMBus Controller Function (SRV/WS SKUs Only) .. 923

27.1 IDF SMBus Registe rs.......... .. ........... .. .......... ........... .. ........... .. .......... .. ........... .. .. 923

27.1.1 SMBus Function Configuration Space Registers......................................... 923

27.1.2 PCI Standard Head er Reg i ste rs .................. .. .. ............. ............ ... ............ 924

27.1.3 PCI Express* Capability Structure........................................................... 929

27.1.4 Power Management Capability Structure.................................................. 940

27.1.5 MSI Capability Structure ....................................................................... 942

27.1.6 Implementation Specific Registers.......................................................... 943

27.1.7 Alternative Routing-ID Interpretation Extended Capability Structure............ 950

27.2 SMBus IO and Memory Space Registers.............................................................. 951

27.2.1 SMBus Function IO and MEM BAR Space Registers.................................... 951

30 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Figures

2-1 PCH Interface Signals Block Diagram.........................................................................52

2-2 Example External RTC Circuit ......... ... .. .. ............ .. ............. ............. .. ............. .. ..........79

4-1 PCH High-Level Clock Diagram (SRV/WS SKUs Only)...................................................92

4-2 PCH High-Level Clock Diagram (HEDT SKU Only) ........................................................93

5-1 Programming Model for Intel® C602, C602J, C604 Chipset SKUs................. .. ..............101

5-2 Programming Model for the Intel® C606, C608 Chipset SKUs......................................102

5-3 Generation of SERR# to Platform............................................................................108

5-4 LPC Interface Diagram ..........................................................................................117

5-5 PCH DMA Controller ..............................................................................................121

5-6 DMA Request Assertion through LDRQ#...................................................................124

5-7 TCO Legacy/Compatible Mode SMBus Configuration ..................................................167

5-8 Advanced TCO Mode .............................................................................................168

5-9 Serial Post over GPIO Reference Circuit ............. ......................................................170

5-10 Flow for Port Enable / Device Present Bits................................................................180

5-11 Serial Data Transmitted over the SGPIO Interface.....................................................184

5-12 Single SCU-4 Configuration....................................................................................186

5-13 Double SCU-4 Conf igu r ation.................. .. .. .. .. ............. .. ............. ............ .. ............. ..187

5-14 Storage Controller Block Diagram ...........................................................................190

5-15 RNC Sizes and Indexing Exampl e........... .. .. .. ............. ............ .. ............. .. ............. .. ..192

5-16 MSI-X Generation.................................................................................................199

5-17 Uncorrectable Error Signalling and Logging Flowchart ................................................201

5-18 SGPIO Bus Overview............. ............. .. ............ .. ............. ............. .. ............. .. ........205

5-19 SGPIO Repeating Bit Stream............................... ... ............ .. ............. .. ............. ......206

5-20 SLoad Signal........................................................................................................206

5-21 SDataOut Signal................... .. .. ............. .. ............. ............ .. ............. .. ............. .. ....207

5-22 SDataIn Signal............... .. .. .. .. ............. .. ............ ............. .. ............. .. ............. .. ......207

5-23 Clock Structure ....................................................................................................208

5-24 SGPIO Output OD0 Signal................... .. .. ............ ............. .. ............. .. ............. .. ......209

5-25 SGPIO Output OD1 Signal................... .. .. ............ ............. .. ............. .. ............. .. ......209

5-26 SGPIO Output OD2 Signal................... .. .. ............ ............. .. ............. .. ............. .. ......210

5-27 Output Signal Routing ............... .. .. ... ............ ............. .. ............. .. ............ .. .............213

5-28 SCU SGPIO Unit Pin Mapping..................................................................................214

5-29 EHCI with USB 2.0 with Rate Matching Hub..............................................................227

5-30 PCH Intel® Management Engine (Intel® ME) High-Level Block Diagram.......................254

5-31 Flash Descriptor Sections.......................................................................................257

6-1 PCH Ballout (Top View)..........................................................................................267

6-2 PCH Ballout (Top View - Upper Left)........................................................................268

6-3 PCH Ballout (Top View - Upper Right)......................................................................269

6-4 PCH Ballout (Top View - Lower Left)........................................................................270

6-5 PCH Ballout (Top View - Lower Right)......................................................................271

8-1 G3 w/RTC Loss to S4/S5 (With Deep S4/S5 Support) Timing Diagram .........................305

8-2 G3 w/RTC Loss to S4/S5 (Without Deep S4/S5 Support) Timing Diagram.....................305

8-3 S5 to S0 Timing Diagram.............................. .. ............. ............. .. ............ .. .............306

8-4 S3/M3 to S0 Timing Diagram .................................................................................307

8-5 S5/Moff - S5/M3 Timing Diagram............................................................................307

8-6 S0 to S5 Timing Diagram.............................. .. ............. ............. .. ............ .. .............308

8-7 S4/S5 to Deep S4/S5 to G3 w/ RTC Loss Timing Diagram .........................................309

8-8 DRAMPWROK Timing Diagram................................................................................309

8-9 Clock Cycle Time ..................................................................................................309

8-10 Transmitting Position (Data to Strobe)........... ..........................................................310

8-11 Clock Timing........................................................................................................310

8-12 Valid Delay from Rising Clock Edge .........................................................................310

8-13 Setup and Hold Time s ............. .. .. .. ... ............ .. ............. ............. .. ............ .. .............311

8-14 Float Delay ..........................................................................................................311

Intel® C600 Series Chipset and Intel® X79 Express Chipset 31

Datasheet

8-15 Pulse Width................. .. .......... .. ........... .. ........... .. .......... .. ........... .. ........... .......... .. 311

8-16 Output Enable Delay............................................................................................. 311

8-17 USB Rise and Fall Times........................................................................................ 312

8-18 USB Jitter ........................................................................................................... 313

8-19 USB EOP Width.................................................................................................... 313

8-20 SMBus/SMLink Transaction.................................................................................... 313

8-21 SMBus/SMLink Timeout......................................................................................... 314

8-22 SPI Timings......................................................................................................... 314

8-23 Intel® High Definition Audio Input and Output Timings.............................................. 315

8-24 Transmitting Position (Data to Strobe) .................................................................... 315

8-25 PCI Express* Transmitter Eye................................................................................ 316

8-26 PCI Express* Receiver Eye .................................................................................... 316

8-27 Measurement Points for Differential Waveforms........................................................ 317

8-28 PCH Test Load ............. .......... .. ........... .. .......... ... .......... .. ........... .. .......... ... .......... .. 318

Tables

1-1 Industry Specifications.............. .. .. .. ............ ... ............ ............. .. ............. .. ..........41

1-2 Intel® C600 Series Chipset and Intel® X79 Express Chipset SKUs............................50

2-1 Direct Media Interface Signals.............................................................................53

2-2 PCI Express* Signals .........................................................................................53

2-3 PCI Express* Uplink Signals................................................................................54

2-4 PCI Interface Signals .........................................................................................54

2-5 Serial ATA Interface Signals.............................. ............ .. ............. .. ............. ........56

2-6 SAS Interface Signals ........................................................................................58

2-7 LPC Interface Signals.........................................................................................60

2-8 Interrupt Signals...............................................................................................60

2-9 USB 2.0 Interface Signals..... .. ... .. ............ .. ............. ............. .. ............ ... ............ ..61

2-10 Power Management Interface Signals...................................................................62

2-11 Processor Interface Signals.................................................................................64

2-12 SM Bus Interface Signals....................................................................................65

2-13 System Management Interface Signals.................................................................65

2-14 SAS System Management Interface Signals ..........................................................65

2-15 Real Time Clock Interface...................................................................................66

2-16 Miscellaneous Sig n als .......... .. ... ............ .. ............. ............. .. ............ .. ............. .. ..66

2-17 Intel® High Definition Audio (Intel® HD Audio) Link Signals ............................ ....... 67

2-18 Serial Peripheral Interface (SPI) Signals . ..............................................................68

2-19 Thermal Signals ................................................................................................68

2-20 JTAG Signals ....................................................................................................68

2-21 Clock Interface Signals.......................................................................................69

2-22 General Purpose I/O Signals ...............................................................................70

2-23 GPIO Serial Expander Interface............ .. .. .. .. ... .. ............ ............. .. ............. .. ........73

2-24 Manageability Signals ........................................................................................73

2-25 Power and Ground Signals..................................................................................74

2-26 Functional Strap Definitions ................................................................................76

3-1 Integrated Pull-Up and Pull-Down Resistors ..........................................................81

3-2 Power Plane and States for Output and I/O Signals................................................83

3-3 Power Plane for Input Signals .............................................................................87

4-1 PCH Clock Inputs ..............................................................................................91

4-2 PCH Clock Outputs ............................................................................................92

4-3 PCH PLLs..........................................................................................................93

5-1 PCI Bridge Initiator Cycle Types ..........................................................................95

5-2 Type 1 Address Format ......................................................................................98

32 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5-3 Configuration Spaces Visible to Software in Intel® C602, C602J, C604

Chipset SKUs .................. .. ........... .. .......... .. ........... .. ........... .. .......... .. ........... ....101

5-4 Root Port and SCU Addressable Internal Spaces...................................................102

5-5 Configuration Spaces Visible to Software in the Intel® C606, C608 Chipse t SKUs.. .. ..103

5-6 Intel® C606, C608 Chipset SKUs Addressable Internal Spaces ...............................103

5-7 MSI versus PCI IRQ Actions...............................................................................106

5-8 LAN Mode Support...........................................................................................113

5-9 LPC Cycle Types Supported...............................................................................118

5-10 Start Field Bit Definitions ..................................................................................118

5-11 Cycle Type Bit Definitions .................................................................................119

5-12 Transfer Size Bit Defini tion............... .. .. ............. .. ............ ............. .. ............. .. ....119

5-13 SYNC Bit Definition .................. ............. .. ............. ............ ... ............ ............. .. ..119

5-14 DMA Transfer Siz e ............... .. .. ........... .. ........... .......... .. ........... .. .......... ... ..........123

5-15 Address Shifting in 16-Bit I/O DMA Transfers.......................................................123

5-16 Counter Operating Modes .................................................................................128

5-17 Interrupt Controller Core Connections.................................................................130

5-18 Interrupt Status Registers.................................................................................131

5-19 Content of Interrupt Vector Byte........................................................................131

5-20 APIC Interrupt Mapping1 ..................................................................................136

5-21 Stop Frame Explanation....................................................................................139

5-22 Data Frame Format..........................................................................................140

5-23 Configuration Bits Reset by RTCRST# Assertion...................................................142

5-24 INIT# Going Active..........................................................................................144

5-25 NMI Sources ...................................................................................................145

5-26 General Power States for Systems Using the PCH.................................................146

5-27 State Transition Rules for the PCH......................................................................147

5-28 System Power Plane.................... .. .......... .. ........... .. .......... ... .......... ........... .. ......148

5-29 Causes of Intel® Scalable Memory Interconnect (Intel® SMI) and SCI ...................149

5-30 Sleep Types....................................................................................................152

5-31 Causes of Wake Events................ .. ............ .. ............. ............. .. ............ ... ..........152

5-32 GPI Wake Events.............................................................................................153

5-33 Transitions Due to Power Failure........... .. .. .. .......................................................154

5-34 Supported Deep S4/S5 Policy Configurations.......................................................155

5-35 Deep S4/S5 Wake Events .................................................................................155

5-36 Transitions Due to Power Button........................................................................156

5-37 Transitions Due to RI# Signal................... .. .. ............. ............. .. ............ ... ..........157

5-38 Write Only Registers with Read Paths in ALT Access Mode .....................................159

5-39 PIC Reserved Bits Return Values........................................................................160

5-40 Register Write Accesses in ALT Access Mode............ .. .. .. .. ............. ............. .. ........161

5-41 SLP_LAN# Pin Behavior....................................................................................162

5-42 SUSWARN#/GPIO30 Steady State Pin Behavior ...................................................163

5-43 Causes of Host and Global Resets ......................................................................164

5-44 Event Transitions that Caus e Messages............ ...................................................167

5-45 Multi-Activity LED Message Type........................................................................183

5-46 Context Command Type ...................................................................................191

5-47 Completion Entry Format..................................................................................192

5-48 SGPIO Input Mapping.......................................................................................210

5-49 Legacy Replacement Routing.............................................................................215

5-50 Debug Port Behavior ................... .. .. .. .. ............. ............ .. ............. .. ............. .. ....222

5-51 I2C Block Read................................................................................................232

5-52 Enable for SMBALERT#......... .. .. ... .. ............ ............. .. ............. .. ............ ... ..........234

5-53 Enables for SMBus Slave Write and SMBus Host Events.........................................235

Intel® C600 Series Chipset and Intel® X79 Express Chipset 33

Datasheet

5-54 Enables for the Host Notify Command................................................................ 235

5-55 Slave Write Registers....................................................................................... 237

5-56 Command Types ............................................................................................. 237

5-57 Slave Read Cycle Format.................................................................................. 238

5-58 Data Values for Slave Read Registers................................................................. 238

5-59 Host Notify Format .......................................................................................... 241

5-60 I2C Write Commands to the Intel® Management Engine ....................................... 244

5-61 Block Read Command - Byte Definition .............................................................. 245

5-62 Region Size versus Erase Granularity of Flash Components ................................... 256

5-63 Region Access Control Table ............................................................................. 258

5-64 Hardware Sequencing Commands and Opcode Requirements ................................ 261

5-65 Flash Protection Mechanism Summary................................................................ 262

5-66 Recommended Pinout for 8-Pin Serial Flash Device .............................................. 263

5-67 Recommended Pinout for 16-Pin Serial Flash Device............................................. 263

6-1 PCH Ballout by Signal Name ............................................................................. 272

8-1 PCH Absolute Maximum Ratings ........................................................................ 283

8-2 PCH Power Supply Range ................................................................................. 284

8-3 Power Supply ICC Specifications by Domain (Intel® C602, C602J, C604

Chipset and Intel® X79 Express Chipset SKUs).................................................... 284

8-4 Power Supply ICC Specifications by Domain (Intel® C606, C608 Chipset SK Us)... ..... 285

8-5 DC Characteristic Input Signal Association .......................................................... 285

8-6 DC Input Characteristics................................................................................... 287

8-7 DC Characteristic Output Signal Association........................................................ 290

8-8 DC Output Characteristics . ............................................................................... 291

8-9 Other DC Characteristics .................................................................................. 292

8-10 PCI Express* and DMI Interface Timings ............................................................ 294

8-11 PCI Express* Uplink Interface Timings (Intel® C606, C608 Chipset SKUs Only) ....... 294

8-12 SAS Interface Timings (SRV/WS SKUs Only)....................................................... 295

8-13 Clock Timings ................................................................................................. 295

8-14 PCI Interface Timing........................................................................................ 297

8-15 Universal Serial Bus Timing .............................................................................. 297

8-16 SATA Interface Timi ng s............... .. .. .. ............. ............ .. ............. .. ............. .. ...... 298

8-17 SMBus and SMLink Timing................................................................................ 299

8-18 Intel® High Definition Audio Timing................................................................... 299

8-19 LPC Timing..................................................................................................... 299

8-20 Miscellaneous Timings........ ........... .. .......... .. ........... .. ........... .......... .. ........... .. .... 300

8-21 SPI Timings (20 MHz) .......... ........... .. .......... ... .......... .. ........... .......... .. ........... .. .. 300

8-22 SPI Timings (33 MHz) .......... ........... .. .......... ... .......... .. ........... .......... .. ........... .. .. 300

8-23 SPI Timings (50 MHz) .......... ........... .. .......... ... .......... .. ........... .......... .. ........... .. .. 301

8-24 SST Timings ................................................................................................... 301

8-25 PECI Timings .................................................................................................. 302

8-26 Power Sequencing and Reset Signal Timings....................................................... 302

9-1 PCI Devices and Functions for all PCH SKUs ........................................................ 320

9-2 PCI Devices and Functions for PCH Intel® C602, C602J, C604 Chipset and

Intel® X79 Express Chipset SKUs ...................................................................... 321

9-3 Additional PCI Devices and Functions for Intel® C606, C608 Chipset SKUs.............. 321

9-4 Additional PCI Devices and Functions for Intel® C608 Chipset SKU..................... .. .. 321

9-5 Fixed I/O Ranges Decoded by PCH..................................................................... 322

9-6 Variable I/O Decode Ranges ............................................................................. 324

9-7 Memory Decode Ranges from Processor P erspective............................................. 325

9-8 SPI Mode Address Swapping............................................................................. 327

10-1 Chipset Configuration Register Memory Map (Memory Space)................................ 329

34 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

11-1 PCI Bridge Register Address Map (PCI-PCI—D30:F0) ............................................365

12-1 Gigabit LAN Configuration Registers Address Map

(Gigabit LAN —D25:F0) ....................................................................................379

12-2 Gigabit LAN Capabilities and Status Registers Address Map

(Gigabit LAN —MBARA) ....................................................................................391

13-1 LPC Interface PCI Register Address Map (LPC I/F—D31:F0) ...................................395

13-2 DMA Registers..................... .. ........... .. .......... ... .......... .. ........... .......... .. ........... ..418

13-3 PIC Registers ..................................................................................................427

13-4 APIC Direct Registers .......................................................................................433

13-5 APIC Indirect Registers.....................................................................................433

13-6 RTC I/O Registers............................................................................................437

13-7 RTC (Standard) RAM Bank ................................................................................437

13-8 Processor Interface PCI Register Address Map .....................................................441

13-9 Power Manageme nt PCI Regi ste r Add re ss Map (PM —D3 1 : F0 )............................. .. ..443

13-10 APM Regi ste r Ma p................ ........... .. .......... .. ........... ........... .. .......... .. ........... .. ..450

13-11 ACPI and Legacy I/O Register Map. ....................................................................451

13-12 TCO I/O Register Address Map...........................................................................469

13-13 Registers to Control GPIO Address Map...............................................................475

13-14 Registers to Control GSX Address Map................................................................484

14-1 SATA Controller PCI Register Address Map (SATA–D31:F2)....................................487

14-2 Bus Master IDE I/O Register Address Map...........................................................511

14-3 AHCI Register Address Map...............................................................................519

14-4 Generic Host Controller Register Address Map......................................................519

14-5 Port [5:0] DMA Register Address Map.................................................................527

15-1 SATA Controller PCI Register Address Map (SATA–D31:F5)....................................541

15-2 Bus Master IDE I/O Register Address Map...........................................................556

16-3 Register Base Attribute Definitions .....................................................................563

16-4 Register Attribute Modifier Definitions.................................................................564

16-5 Register Domain Definitions ............... .. .. .. ............. .. ............. ............ .. ............. ..564

16-6 SCU PF PCI Configuration Registers....................................................................565

16-7 SCU VF PCI Configuration Registers....................................................................594

16-8 SGPIO Memory Mapped Registers ......................................................................614

17-1 USB EHCI PCI Register Address Map (USB EHCI—D29:F0, D26:F0) ........................621

17-2 Enhanced Host Controller Capability Registers .....................................................639

17-3 Enhanced Host Controller Operational Register Ad dress Map.......................... .. ......642

17-4 Debug Port Reg i ster Address Map ................. .. ... .. ............ .. ............. .. ............. .. ..652

18-5 Intel® High Definition Audio PCI Register Address Map (Intel HD Audio D27:F0).......655

18-6 Intel® HD Audio PCI Register Address Map

(Intel® HD Audio D27:F0).................... .......... ... .......... .. ........... .. .......... ... ..........672

19-1 SMBus Controller PCI Register Address Map (SMBus—D31:F3).............................. .695

19-2 SMBus I/O and Memory Mapped I/O Register Address Map. ...................................701

20-1 PCI Express* Configuration Registers Address Map

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/)..................................................711

21-1 Memory-Mapped Registers................................................................................745

22-1 Serial Peripheral Interface (SPI) Register Address Map

(SPI Memory Mapped Configuration Registers).....................................................753

22-2 Gigabit LAN SPI Flash Prog ram Register Address Map

(GbE LAN Memory Mapped Configuration Registers) .............................................771

23-1 Thermal Sensor Register Ad dr ess Ma p............. ... .. ............ ............. .. ............. .. ....781

23-2 Thermal Memory Mapped Configuration Register Address Map ...............................789

24-1 Intel MEI 1 Configuration Registers Address Map

(Intel MEI 1 —D22:F0).....................................................................................799

Intel® C600 Series Chipset and Intel® X79 Express Chipset 35

Datasheet

24-2 Intel MEI 1 MMIO Register Address Map ............................................................. 808

24-3 Intel MEI 2 Configuration Registers Address Map (Intel MEI 2—D22:F1).................. 810

24-4 Intel MEI 2 MMIO Register Address Map ............................................................. 818

24-5 IDE Function for remote boot and Installations PT IDER Registe r Add re ss Map......... 820

24-6 IDE BAR0 Register Address Map........................................................................ 827

24-7 IDER BAR1 Register Address Map ...................................................................... 836

24-8 IDER BAR4 Register Address Map ...................................................................... 837

24-9 Serial Port for Remote Keyboard and Text (KT) Redirection Register

Address Map................................................................................................... 842

24-10 KT IO/ Memory Mapped Device Register Address Map .......................................... 848

25-1 PCI Express* UpStream Configuration Registe rs Addre ss Map

(PCI Express*—D0:F0) .................................................................................... 853

27-2 SMBus PCI Function 3,4,5 Configuration Map ...................................................... 923

27-3 SMBus I/O and Memory Mapped I/O Register Address Map ................................... 951

36 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Revision History

Revision

Number Description Date

001 • Initial Release March 2012

002

•Added Intel

® X79 Express Chipset

• Minor Edits throughout for clarity

• Replace d SKU letter designators A /J/B/D/T with product numbers. Re ferences all of the

lettered SKUs were replaced with SRV/WS.

•Chapter 1

— Updated Table 1-2, Intel® C600 Series Chipset and Intel® X79 Express Chipset

SKUs

— Added note to Section 1.2.1, Access Control Services Clarification

— Updated Section 1.2.1 SPI Overview

•Chapter 2

— Updated PWRBTN# and SLP_SUS# descri ptions in Table 2-10.

— Updated RTCRST# description in Table 2-16.

— Added Note 13 to Table 2-22, General Purpose I/O Signals

— Updated Table 2-25, SAS Power Signal Connections

— Updated Section 2.28, Device and Revision ID Table

•Chapter 5

— Added Note 5 to Table 5-27, State Transition Rules for the PCH

— Updated Section 5.18.1.2, SCU Architectural Features, first bullet

— Added Note to Section 5.3.1 Valid PCI Express* uplink configuration

— Updat ed Table 5-29, Causes of Intel® S calable Me mory Inte rconnect (Intel ® SMI)

and SCI

— Updated Table 5-44, Event Transitions that Cause Messages

— Updated Section 5.14.7.1, PWRBTN# (Power Button)

— Added Note to Section 5.15.4, GPIO Registers Lockdown

— Updated Section 5.19, High Precision Event Timers Functional Description

— Updated Section 5.23.1, Thermal Sensor

— Updated Section 5.26.1.2.1, SPI Flash Regions

— Updated Section 5.27, Fan Control/Thermal Management

•Chapter 8

— Updated Table 8-4 and 8-5, Icc Value for RTC Well

— Updated Table 8-13, Clock Timings

— Updated Table 8-26, Power Sequencing and Reset Signal Timings

— Added notes to Figures 8-2 and 8-20

•Chapter 9

— Updated Table 9-7, Memory D ecode Ranges from Processor Perspe ctive

•Chapter 10

— Updated Table 10-1, Chipset Configuration Register Memory Map

— Updated 10.1.4, Function Level Reset Pending Status Register

— Updated 10.1.47, FDSW-Function Disable SUS Well

•Chapter 12

— Updated Table 12-1, Gigabit LAN Configuration Registers Address Map

•Chapter 13

— Updated Table 13-1, LPC Interface PCI Register Address Map

— Updated Section 13.8.3.7, SMI_EN—SMI Control and Enable Register

— Updated Section 13.8.3.11, UPRWC—USB Per-Port Registers Write Control Register

— Updated Table 13-13 Registers to Control GPIO Address Map

•Chapter 14

— Updated Table 14-1, SATA Controller PCI Register Address Map

— Updated Section 14.1.37, SGC-SATA General Configuration Register

•Chapter 15

— Updated Table 15-1, SATA Controller PCI Register Address Map

•Chapter 17

— Updated Section 17.1.20, PWR_CNTL_SIS Register

•Chapter 20

— Updated Table 20-1, PCI Express* Configuration Registers Address Map

— PECR2 — PCI Express* Configuration Register 2 (PCI Express—

D28:F0/F1/F2/F3/F4/F5/F6/F7) and PEC1 — PCI Express* Configuration R egister 1

have been removed as no BIOS programing is necessary.

March 2013

Intel® C600 Series Chipset and Intel® X79 Express Chipset 37

Datasheet

002

(cont)

•Chapter 22

— Updated Table 22-1, Serial Peripheral Interface (SPI) Register Address Map

— Updated Table 22-1, Gigabit LAN SPI Flash Program Register Address Map

•Chapter 23

— Updated Section 23.2.4, TSTR—Thermal Sensor Thermometer Read Register

•Chapter 24

— Updated Table 24-1, Intel MEI 1 Configuration Registers Address Map

•Chapter 25

— Updated Section 25.1.31, LCAP—Link Capabilities Register (PCI Express—D0:F0)

— Updated Section 25.1.33, LSTS—Link Status Register (PCI Express—D0:F0)

— Removed LINKCAP2 Register

— Updated Section 25.1.38, L2—Link Control 2 Register (PCI Express—D0:F0)

•Chapter 26

— Updated Section 26.2.30, LCAP—Link Capabilities Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D8:F0)

— Updated Section 26.2.321,LSTS—Link Status Register

(Virtual Root P ort—B0:D17:F0, Virtual Switch P ort—BN+1:D8:F0)

— Removed LINKCAP2 Register

— Updated Section 26.2.39, L2—Link Control 2 Register

(Virtual Root Port—B0:D17:F0, Virtual Switch Port—BN+1:D8:F0)

March 2013

Revision

Number Description Date

38 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Intel® C600 Series Chipset and Intel® X79 Express Chipset 39

Datasheet

Intel® C600 Series Chipset and Intel® X79

Express Chipset Features

• Direct Media Interface

— NEW: Up to 20 Gb/s each direction, full

duplex

— Lane reversal supported

— Transparent to software

• PCI Express* Root Ports

— 8 PCI Express* root ports

— NEW: Supports PCI Express* 2.0 running

at up to 5.0 GT/s

— P orts 1-4 and ports 5-8 can independently

be configured to support eight x1s, two

x4s, two x2s, and four x1s, or one x4 and

four x1 port widths.

— Module based hot-plug supported (that is,

ExpressCard*)

— Lane reversal supported on x4

configuration

• NEW: PCI Express* Uplink Port (SRV/WS

SKUs Only)

— SKU specific x4 PCI Express* upstream

port dedicated for SAS I/O

• NEW: Serial Attached SCSI (SAS) Ports

(SRV/WS SKUs Only)

— SKU specific up to eight 3 G b/s SAS ports

— Up to x4 SAS wide port configuration

— Independently configurable

— Compliant to SATA 3 Gb/s

— Automate d Out of Band (OOB) S ignaling &

Speed Negotiation

•SGPIO Ports

— New: 1 Serial GPIO controller for each 4

SAS ports (SRV/WS SKUs Only)

— Serial GPIO controller for SATA only ports

• Integrated Serial ATA Host Controller

— Up to six SATA ports

— NEW: Data transfer rates up to 6.0 Gb/s

(600 MB/s) on up to 2 ports.

— Data transfer rates up to 3.0 Gb/s

(300 MB/s) on up to 1.5 Gb/s

(150 MB/s) all ports.

— Integrated AHCI controller

• External SATA support

— 3.0 Gb/s / 1.5 Gb/s support

— Port Disable Capability

•Intel

® Rapid Storage Technology

enterprise

— Supports SAS as well as SATA ports

— Configures the Intel® C600 Series chipset

SAS ports as a RAID Controller supporting

RAID 0/1/5/10

— Configures the Intel® C600 Series chipset

SA T A ports as a RAID controller su pporting

RAID 0/1/5/10

•USB

— Two EHCI Host Controllers, supporting up

to fourteen external USB 2.0 ports

— New: Two USB 2.0 Rate Matching Hubs

(RMH) to replace functionality of UHCI

controllers

— Per-Port-Disable Capability

— Includes up to two USB 2.0 High-speed

Debug Ports

— Supports wake-up from sleeping states

S1-S4

— Suppo rts legacy Keybo ard/Mouse software

• Integrated Gigabit LAN Controller

— NEW: Connection utilizes PCI Express*

pins

— Integrated ASF Management Controller

— Network security with System Defense

— Supports IEEE 802.3

— 10/100/1000 Mbps Ethernet Support

— Jumbo Frame Support

• Power Management Logic

— Supports ACPI 4.0a

— ACPI-defined power states (processor

driven C states)

— ACPI Power Management Timer

—SMI# generation

— All registers readable/restor able for proper

resume from 0 V core well suspend states

— Support for APM-based legacy power

management for non-ACPI

implementations

• External Glue Integration

— Integrated Pull-up, Pull-down and Series

Termination resistors on processor I/F

— Integrated Pull-down and Series resistors

on USB

• Enhanced DMA Controller

— Two cascaded 8237 DMA controllers

— Supports LPC DMA

40 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Note: Not all features are available on all PCH SKUs. See Section 1.3 for more details.

•Intel

® High Definition Audio Interface

— PCI Express* endpoint

— Independent Bus Master logic for eight

general purpose streams: four input and

four output

— Support four external Codecs

— Supports variable length stream slots

— Supports multichannel, 32-bit sample

depth, 192 kHz sample rate output

— Provides mic array support

— Allows for non-48 kHz sampling output

• Support for ACPI Device States

— Four PWM signals and Eight TACH signals

• Simple Serial Transport (SST) 1.0 Bus and

Platform Environmental Control Interface

(PECI)

•PCI Bus Interface

— Supports PCI Rev 2.3 specification at

33 MHz

— Four available PCI REQ/G N T pairs (share d

with GPIO serial expander signals)

— Support for 64-bit addressing on PCI using

DAC protocol

•SMBus

— Interface speeds greater than 100 kbps

— SMBus/SMLink architecture provides

flexibility and optimizes the interface

performance

— Provides independent manageability bus

through SMLink interface

— Supports SMBus 2.0 Specification

— Host interface allows processor to

communicate using SMBus

— Slave interface allows an external

Microcontroller to communicate with PCH

— Compatible with most two-wire

components that are also I2C* compatible

— Up to 3 additional SMBus master

controllers

• High Precision Event Timers

— Advanced operating system in terrupt

scheduling

• Timers Based on 8254

— System timer, Refresh request, Speaker

tone output

• Real-Time Clock

— 256-byte battery-backed CMOS RAM

— Integrated oscillator components

— Lower Power DC/DC Converter

implementation

• System TCO Reduction Circuits

— Timers to generate SMI# and Reset upon

detection of system hang

— Timers to detect improper processor reset

— Integrated processor frequency strap logic

— Supports ability to disable external devices

• Interrupt Controller

— Supports up to eight PCI interrupt pins

— Supports PCI 2.3 Message Signaled

Interrupts

— Two cascaded 8259 with 15 interrupts

— Integrated I/O APIC capability with 24

interrupts

— Supports Processor System Bus interrupt

delivery

• Serial Peripheral Interface (SPI)

— Supports up to two SPI devices

— Supports 20 MHz, 33 MHz SPI devices

— Support up to two different erase

granularities

• Low Pin Count (LPC) I/F

— Supports two Master/DMA devices.

— Support for Security Device (Trusted

Platform Module) connected to LPC.

•GPIO

—Inversion, Open-Drain (not available on all

GPIOs),

—GPIO lock down

— NEW: Additional GPIOs using GPIO Serial

Expander

•JTAG

— Boundary Scan for testing during board

manufacturing

• Technologies supported

—Intel

® I/O Virtualization (VT-d) Support

(SRV/WS SKUs Only)

—Intel

® Trusted Execution Technology

Support

—Intel

® Anti-Theft Technology

—Intel

® Active Management Technology

with System Defense (SRV/WS SKUs Only)

— NEW: Network Outbreak Containment

Heuristics

• Miscellaneous

— Thermal sensor for die temp tracking

— 27x27 mm FCBGA package

— 901 pins (498 signals, 387 power and

ground)

— 1.1 V operation with 1.5 and 3.3 V I/O

— Five Integrated Voltage Regulators for

different power rails

— Firmware Hub I/F supports BIOS Memory

size up to 8 MBytes

Introduction

Intel® C600 Series Chipset and Intel® X79 Express Chipset 41

Datasheet

1 Introduction

1.1 About This Manual

This manual is intended for Original Equipment Manufacturers and BIOS vendors

creating Intel® C600 Series Chipset and Intel® X79 Express Chipset based products

(See Section 1.3 for currently defined SKUs).

Note: Throughout this document, the terms “Server/Workstation” and “Server/Workstation”

Only” refer to information that is applicable only to the Intel® C602 Chipset, Intel®

C602J Chipset, Intel® C604 Chipset, Intel® C606 Chipset, and Intel® C608 Chipset,

unless specifically noted otherwise. Server/Workstation is abbreviated SRV/WS

Note: Throughout this document, the terms “High End Desktop” and “High End Desktop”

Only” refer to information that is applicable only to the Intel® X79 Chipset, unless

specifically noted otherwise. High End Desktop is abbreviated HEDT.

Note: Throughout this manual, Platform Controller Hub (PCH) is used as a general term and

refers to all Intel® C600 Series Chipset and Intel® X79 Express Chipset SKUs, unless

specifically noted otherwise.

This manual assumes a working knowledge of the vocabulary and principles of

interfaces and architectures such as PCI Express*, USB, AHCI, SATA, Intel® High

Definition Audio (Intel® HD Audio), SMBus, PCI, ACPI and LPC. Although some details

of these features are described within this manual, refer to the individual industry

specifications listed in Table 1-1 for the complete details.

Table 1-1. Industry Specifications (Sheet 1 of 2)

Specification Location

PCI Express* Base Specification, Revision 1.1 http://www.pcisig.com/specifications

PCI Express* Base Specification, Revision 2.0 http://www.pcisig.com/specifications

PCI Express* Base Specification, Revision 3.0 (draft) http://www.pcisig.com/specifications

Low Pin Count Interface Specification, Revision 1.1 (LPC) http://developer.intel.com/design/chipsets/

industry/lpc.htm

System Management Bus Specification, Version 2.0

(SMBus) http://www.smbus.org/specs/

PCI Local Bus Specification, Revision 2.3 (PCI) http://www.pcisig.com/specifications

PCI Power Management Specification, Revision 1.2 http://www.pcisig.com/specifications

Universal Serial Bus Specification (USB), Revision 2.0 http://www.usb.org/developers/docs

Advanced Configuration and Power Interface, Version

4.0a (ACPI) http://www.acpi.info/spec.htm

Enhanced Host Controller Interface Specification for

Universal Serial Bus, Revision 1.0 (EHCI) http://developer.intel.com/technology/usb/

ehcispec.htm

Serial ATA Specification, Revision 3.0 http://www.serialata.org/specifications.asp

Serial ATA II: Extensions to Serial ATA 1.0, Revision 1.0 http://www.serialata.org/specifications.asp

Serial ATA II Cables and Connectors Volume 2 Gold http://www.serialata.org/specifications.asp

Serial Attached SCSI (SAS) revision 2.0r5 http://T10.org (T10 1760-D)

Alert Standard Format Specification, Version 2.0 http://www.dmtf.org/standards/documents/ASF/

DSP0136.pdf

Desktop and mobile Architecture for System Hardware

(DASH) Specification 1.1 http://www.dmtf.org/standards/

published_documents/DSP2014_1.1.0.pdf

Introduction

42 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Chapter 1. Introduction

Chapter 1 introduces the PCH and provides information on manual organization and

gives a general overview of the PCH.

Chapter 2. Signal Description

Chapter 2 provides a block diagram of the PCH and a detailed description of each

signal. Signals are arranged according to interface and details are provided as to the

drive characteristics (Input/Output, Open Drain, and so forth) of all signals.

Chapter 3. PCH Pin States

Chapter 3 provides a complete list of signals, their associated power well, their logic

level in each suspend state, and their logic level before and after reset.

Chapter 4. PCH and System Clock Domains

Chapter 4 provides a list of each clock domain associated with the PCH.

Chapter 5. Functional Description

Chapter 5 provides a detailed description of the functions in the PCH. All PCI buses,

devices and functions in this manual are abbreviated using the following nomenclature;

Bus:Device:Function. This manual abbreviates buses as Bn, devices as Dn, and

functions as Fn. For example Device 31 Function 0 is abbreviated as D31:F0, Bus 1

Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus number will not be

used, and can be considered to be Bus 0. Note that the PCH’s external PCI bus is

typically Bus 1, but may be assigned a different number depending upon system

configuration.

Chapter 6. Ballout Definition

Chapter 6 provides a table of each signal and its ball assignment in the PCH package.

Chapter 7. Package Information

Chapter 7 provides drawings of the physical dimensions and characteristics of the

676-mBGA package.

Chapter 8. Electrical Characteristics

Chapter 8 provides all AC and DC characteristics including detailed timing diagrams.

Chapter 9. Register and Memory Mappings

Chapter 9 provides an overview of the registers, fixed I/O ranges, variable I/O ranges

and memory ranges decoded by the PCH.

IEEE 802.3 Fast Ethernet http://standards.ieee.org/getieee802/

AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6) http://T13.org (T13 1410D)

IA-PC HPET (High Precision Event Timers) Specification,

Revision 1.0a

http://www.intel.com/content/www/us/en/

software-developers/software-developers-hpet-

spec-1-0a.html

TPM Specification 1.02, Level 2 Revision 103 http://www.trustedcomputinggroup.org/specs/

TPM

Intel® Virtualization Technology http://www.intel.com/technology/platform-

technology/virtualization/index.htm

SFF-8485 Specification for Serial GPIO (SGPIO) Bus,

Revisi on 0.7 ftp://ftp.seagate.com/sff/SFF-8485.PDF

Advanced Host Controller Interface specification for

Serial ATA, Revision 1.3 http://www.intel.com/content/www/us/en/io/

serial-ata/serial-ata-ahci-spec-rev1_3.html

Intel® High Definition Audio Specification, Revision 1.0a http://www.intel.com/content/www/us/en/

standards/standards-high-def-audio-specs-

general-technology.html

MultiProcessor Specification http://www.intel.com/design/pentium/datashts/

242016.HTM

Table 1-1. Industry Specifications (Sheet 2 of 2)

Specification Location

Introduction

Intel® C600 Series Chipset and Intel® X79 Express Chipset 43

Datasheet

Chapter 10. Chipset Configuration Registers

Chapter 10 provides a detailed description of all registers and base functionality that is

related to chipset configuration and not a specific interface (such as LPC, PCI, or PCI

Express). It contains the root complex register block, which describes the behavior of

the upstream internal link.

Chapter 11. PCI-to-PCI Bridge Registers

Chapter 11 provides a detailed description of all registers that reside in the PCI-to-PCI

bridge. This bridge resides at Device 30, Function 0 (D30:F0).

Chapter 12. Integrated LAN Controller Registers

Chapter 12 provides a detailed description of all registers that reside in the PCH’s

integrated LAN controller. The integrated LAN Controller resides at Device 25, Function

0 (D25:F0).

Chapter 13. LPC Bridge Registers

Chapter 13 provides a detailed description of all registers that reside in the LPC bridge.

This bridge resides at Device 31, Function 0 (D31:F0). This function contains registers

for many different units within the PCH including DMA, Timers, Interrupts, Processor

Interface, GPIO, Power Management, System Management and RTC.

Chapter 14. SATA Controller Registers

Chapter 14 provides a detailed description of all registers that reside in the SATA

controller #1. This controller resides at Device 31, Function 2 (D31:F2).

Chapter 15. SATA Controller Registers

Chapter 15 provides a detailed description of all registers that reside in the SATA

controller #2. This controller resides at Device 31, Function 5 (D31:F5).

Chapter 16. SAS Controller Registers (SRV/WS SKUs Only)

Chapter 16 provides a detailed description of all registers that reside in the SAS

controller. The controllers resides at Bus X, Device 0, Functions 0 (BX:D0:F0).

Chapter 17. EHCI Controller Registers

Chapter 17 provides a detailed description of all registers that reside in the two EHCI

host controllers. These controllers reside at Device 29, Function 7 (D29:F7) and Device

26, Function 7 (D26:F7).

Chapter 18. Intel® High Definition Audio Controller Registers

Chapter 18 provides a detailed de scription of all registers that re side in the Intel ® High

Definition Audio (Intel® HD Audio) controller. This controller reside s at Device 27,

Function 0 (D27:F0).

Chapter 19. SMBus Controller Registers

Chapter 19 provides a detailed description of all registers that reside in the SMBus

controller. This controller resides at Device 31, Function 3 (D31:F3).

Chapter 20. PCI Express* Port Controller Registers

Chapter 20 provides a detailed description of all registers that reside in the PCI

Express* controller. This controller resides at Device 28, Functions 0 to 5 (D30:F0-F5).

Chapter 21. High Precision Event Timers Registers

Chapter 21 provides a detailed description of all registers that reside in the multimedia

timer memory mapped register space.

Chapter 22. Serial Peripheral Interface Registers

Chapter 22 provides a detailed description of all registers that reside in the SPI

memory map p ed register space.

Chapter 23. Thermal Sensors

Chapter 23 provides a detailed description of all registers that reside in the thermal

sensors PCI configuration space. The registers reside at Device 31, Function 6

(D31:F6).

Introduction

44 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Chapter 24. Intel® Management Engine (Intel® ME)

Chapter 24 provides a detailed description of all registers that reside in the thermal

sensors PCI configuration space. The registers reside at Device 31, Function 6

(D31:F6).

Chapter 25. Upstream PCIe* Interface Registers (Intel® C606, C608 Chipset

SKUs Only)

Chapter 25 provides a detailed description of all registers that reside in the upstream

PCI Express* controller. This controller resides at Bus N, Device 0, Function 0

(BN:D0:F0).

Chapter 26. PCIe Virtual Root/Switch Port Interface Registers (SRV/WS SKUs

Only)

Chapter 26 provides a detailed description of all registers that reside in the virtual R oot

port (for Intel C602, C602J, C604 Chipset SKUs) or virtual switch port (for Intel C606,

C608 Chipset SKUs) of PCI Express* controller. For virtual root port, this controller

resides at Device 17, Function 0 (D17:F0). For virtual switch port, this controller

resides at Bus N+1, Device 8, Function 0 (BN+1:D8:F0).

Chapter 27. IDF SMBus Controller Registers (SRV/WS SKUs Only)

Chapter 27 provides a detailed description of all registers that reside in the SMBus

controllers that associated with SAS controller. These controllers reside at Bus X,

Device 0, Function 3, 4, 5 (BX:D0:F3/F4/F5)

1.2 Overview

The PCH provides extensive I/O support. Functions and capabilities include:

•PCI Express* Base Specification, Revision 2.0 support for up to eight ports with

transfers up to 5 GT/s.

• PCI Express* Uplink. (Availiable on specific SKUs Only)

•PCI Local Bus Specification, Revision 2.3 support for 33 MHz PCI operations

(supports up to four Req/Gnt pairs).

• ACPI Power Management Logic Support, Revision 4.0a

• Enhanced DMA controller, interrupt controller, and timer functions

• Integrated Serial Attached SCSI host contro llers at transfer r ate up to 3 Gb/s on up

to eight ports. (Available on specific SKUs Only)

• Integrated Serial AT A host controllers with independent DMA oper ation on up to six

ports.

• USB host interface with two EHCI high-speed USB 2.0 Host controllers and 2 rate

matching hubs provide support for support for up to fourteen USB 2.0 ports

• Integrated 10/100/1000 Gigabit Ethernet MAC with System Defense

•System Management Bus (SMBus) Specification, Version 2.0 with additional

support for I2C* devices

•Supports Intel

® High Definition Audio

•Supports Intel

® Rapid Storage Technology enterprise (Intel® RSTe)

•Supports Intel

® Active Management Technology (Intel® AMT). (Available on

specific SKUs Only)

•Supports Intel

® Virtualization Technology for Directed I/O (Intel ® VT-d). (Available

on specific SKUs Only)

•Supports Intel

® Trusted Execution Technology (Intel® TXT)

• Low Pin Count (LPC) interface

• Firmware Hub (FWH) interface support

• Serial Peripheral Interface (SPI) support

•Intel

® Anti-Theft Technology (Intel® AT)

•JTAG Boundary Scan support

Introduction

Intel® C600 Series Chipset and Intel® X79 Express Chipset 45

Datasheet

The PCH incorporates a variety of PCI devices and functions. Refer to Table 9-1 for

details.

1.2.1 Capability Overview

The following sub-sections provide an overview of the PCH capabilities.

Digital Media Interface (DMI)

Digital Media Interface (DMI) is the chip-to-chip connection between the processor and

PCH. This high-speed interface integrates advanced priority-based servicing allowing

for concurrent traffic and true isochronous transfer capabiliti es. Base functionality is

completely software-transparent, permitting current and legacy software to operate

normally.

PCI Express* Root Port

The PCH provides up to 8 PCI Express* Root Ports, supporting the PCI Express Base

Specification, Revision 2.0. Each Root Port x1 lane supports up to 5 Gb/s bandwidth in

each direction (10 Gb/s concurrent). PCI Express* Root Ports 1-4 or Ports 5-8 can

independently be configured to support four x1s, two x2s, one x2 and two x1s, or one

x4 port widths.

Note: Access Control Services (ACS)/Alternative Routing ID (ARI) are not supported on the

PCI Express* Root Port of the Intel® C600 series chipset, devices connected to these

ports may not support direct assignment or Single Root I/O Virtualization (SR-IOV).

PCI Express* Uplink (Available on specific SKUs Only)

The PCI Express* Uplink here is an amalgram of two functions, and Uplink port

connecting to a PCI Express* bus, and a virtual switch connecting the Uplink port to the

MFD below. The MFD contains the SAS controllers, and SMBus controllers. The uplink

can run at 5.0 Gt/s and 2.5 Gt/s, at x4, x2 and x1 configurations. However, because

the PCI Express* uplink will be connected to Intel(R) components, no 3rd party

devices, the expected/supported configuration is simply x4 as 1.0.

Note: PCI Express* Uplink is only available on specific PCH SKUs. See Section 1.3 for details

on SKU feature availability.

Serial Attached SCSI (SAS)/SATA Controller (SAS Available on specific

SKUs Only)

The PCH supports upto 8 SAS ports that are compliant with SAS 2.0 Specification and

all ports support rates up to 3.0 Gb/s. All 8 ports are also independently configurable

and compliant with SATA Gen2 and support data transfer rates of up to 3.0 Gb/s.

Note: SAS/SATA controller is only available on specific PCH SKUs. Certain SKUs are also

limited to support 4 of 8 SAS/SATA ports only. See Section 1.3 for details on SKU

feature availability.

Serial ATA (SATA) Controller

The PCH has two integrated SATA host controllers that support independent DMA

operation on up to six ports and supports data transfer rates of up to 6.0 Gb/s

(600 MB/s) on up to two ports (Port 0 and 1 Only) while all ports support rates up to

3.0 Gb/s (300 MB/s) and up to 1.5 Gb/s (150 MB/s). The SATA controller contains two

modes of operation – a legacy mode using I/O space, and an AHCI mode using memory

space. Software that uses legacy mode will not have AHCI capabilities.

Introduction

46 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

The PCH supports the Serial ATA Specification, Revision 3.0. The PCH also supports

several optional sections of the Serial ATA II: Extensions to Serial ATA 1.0

Specification, Revision 1.0 (AHCI support is required for some elements).

AHCI

The PCH provides hardware support for Advanced Host Controller Interface (AHCI), a

standardized programming interface for SATA host controllers. Platforms supporting

AHCI may take advantage of performance features such as no master/slave

designation for SATA devices—each device is treated as a master—and hardware-

assisted native command queuing. AHCI also provides usability enhancements such as

Hot-Plug. AHCI requires appropriate software support (for example, an AHCI driver)

and for some features, hardware support in the SATA device or additional platform

hardware.

Intel® Rapid Storage Technology enterprise (Intel® RSTe)

The PCH provides support for Intel® Rapid Storage Technology enterprise, providing

both AHCI (see above for details on AHCI) and integrated RAID functionality. The

industry-leading RAID capability provides high-performance RAID 0, 1, 5, and 10

functionality on up to 6 S A TA ports of the PCH. Matrix RAID support is provided to allow

multiple RAID levels to be combined on a single set of hard drives, such as RAID 0 and

RAID 1 on two disks. Other RAID features include hot-spare support, SMART alerting,

and RAID 0 auto replace. Software components include an Option ROM for pre-boot

configuration and boot functionality, a Microsoft Windows* compatible driver, and a

user interface for configuration and management of the RAID capability of the PCH.

Please see Section 1.3 for details on SKU feature availability.

PCI Interface

The PCH PCI interface provides a 33 MHz, Revision 2.3 implementation. The PCH

integrates a PCI arbiter that supports up to four external PCI bus masters in addition to

the internal PCH requests. This allows for combinations of up to four PCI down devices

and PCI slots.

Low Pin Count (LPC) Interface

The PCH implements an LPC Interface as described in the LPC 1.1 Specification. The

Low Pin Count (LPC) bridge function of the PCH resides in PCI Device 31:Function 0. In

addition to the LPC bridge interface function, D31:F0 contains other functional units

including DMA, interrupt controllers, timers, power management, system management,

GPIO, and RTC.

Serial Peripheral Interface (SPI)

The PCH provides an SPI Interface and is required to be used on the platform in order

to provide chipset configuration settings and Intel® Management Engine (Intel® ME)

firmware. If integrated Gigabit Ethernet MAC/PHY is implemented on the platform, the

interface is used for this device configuration settings. The interface may also be used

as the interface for the BIOS flash device or alternatively a FWH on LPC may be used.

The PCH supports up to two SPI flash devices using two chip select pins with speeds up

to 50 MHz.

Compatibility Modules (DMA Controller, Timer/Counters, Interrupt

Controller)

The DMA controller incorporates the logic of two 8237 DMA controllers, with seven

independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-

byte transfers, and channels 5–7 are hardwired to 16-bit, count -by-word tr ansfers. Any

two of the seven DMA channels can be programmed to support fast Type-F transfers.

Channel 4 is reserved as a generic bus master request.

Introduction

Intel® C600 Series Chipset and Intel® X79 Express Chipset 47

Datasheet

The PCH supports LPC DMA, which is similar to ISA DMA, through the PCH’s DMA

controller. LPC DMA is handled through the use of the LDRQ# lines from peripherals

and special encoding on LAD[3:0] from the host. Single, Demand, Verify, and

Increment mod es are su pp orted on the LPC interface.

The timer/counter block contains three counters that are equivalent in function to those

found in one 8254 programmable interval timer. These three counters are combined to

provide the system timer function, and speaker tone. The 14.31818 MHz oscillator

input provides the clock source for these three counters.

The PCHPCH provides an ISA -Compatible Progr ammable Interrupt Controller (PIC) that

incorporates the functionality of two, 8259 inte rrupt controllers. The two interrupt

controllers are cascaded so that 14 external and two internal interrupts are possible. In

addition, the PCH supports a serial interrupt scheme.

All of the registers in these modules can be read and restored. This is required to save

and restore system state after power has been removed and restored to the platform.

Advanced Programmable Interrupt Controller (APIC)

In addition to the standard ISA compatible Programmable Interrupt controller (PIC)

described in the previous section, the PCH incorporates the Advanced Programmable

Interrupt Controller (APIC).

Universal Serial Bus (USB) Controllers

The PCH has up to two Enhanced Host Controller Interface (EHCI) host controllers

that support USB high-speed signaling. High-speed USB 2.0 allows data transfers up to

480 Mb/s which is 40 times faster than full-speed USB. The PCH supports up to

fourteen USB 2.0 ports. All fourteen ports are high-speed, full-speed, and low-speed

capable.

Gigabit Ethernet Controller

The Gigabit Ethernet Controller provides a system interface using a PCI function. The

controller provides a full memory-mapped or IO mapped interface along with a 64-bit

address master support for systems using more than 4 GB of physical memory and

DMA (Direct Memory Addressing) mechanisms for high performance data tr ansfers. Its

bus master capabilities enable the component to process high-level commands and

perform multiple operations; this lowers processor utilization by off-loading

communication tasks from the processor. Two large configurable transmit and receive

FIFOs (up to 20 KB each) help prevent data underruns and overruns while waiting for

bus accesses. This enables the integrated LAN controller to transmit data with

minimum interfra me spacing (IFS).

The LAN controller can operate at multiple speeds (10/100/1000 MB/s) and in either

full duplex or half duplex mode. In full duplex mode the LAN controller adheres with the

IEEE 802.3x Flow Control Specification. Half duplex performance is enhanced by a

proprietary collision reduction mechanism. See Section 5.4 for details.

RTC

The PCH contains a Motorola MC146818B-compatible real-time clock with 256 bytes of

battery-backed RAM. The real-time clock performs two key functions: keeping track of

the time of day and sto ring system data, even when the system is powered down. The

RTC operates on a 32.768 KHz crystal and a 3 V battery.

The R TC also supports two lockable memory r anges. By setting bits in the configuration

space, two 8-byte ranges can be locked to read and write accesses. This prevents

unauthorized reading of passwords or other system security information.

Introduction

48 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

The RTC also supports a date alarm that allows for scheduling a wake up event up to

30 days in advance, rather than just 24 hours in advance.

GPIO

Various general purpose inputs and outputs are provided for custom system design.

The number of inputs and outputs varies depending on the PCH configuration.

Enhanced Power Management

The PCH’s power management functions include enhanced clock control and v a rious

low-power (suspend) states (for example, Suspend-to-RAM and Suspend-to-Disk). A

hardware-based thermal management circuit permits software-independent entrance

to low-power states. The PCH contains full support f or the Advanced Configuration and

Power Interface (ACPI) Specification, Re vision 4.0a.

Intel® Active Management Technology (Intel® AMT) (Available on

specific SKUs Only)

Intel® AMT is a fundamental component of Intel® vPro™ technology. Intel® AMT is a

set of advanced manageability features developed as a direct result of IT customer

feedback gained through Intel market research. With the advent of powerful tools like

the Intel® System Defense Utility, the extensive feature set of Intel® AMT easily

integrates into any network en vironment. See Section 1.3 for details on SKU feature

availability.

Manageability

In addition to Intel® AMT the PCH integrates several functions designed to manage the

system and lower the total cost of ownership (TCO) of the system. These system

management functions are designed to report errors, diagnose the system, and recover

from system lockups without the aid of an external microcontroller.

•TCO Timer. The PCH’s integrated programmable TCO timer is used to detect

system locks. The first expiration of the timer generates an SMI# that the system

can use to recover from a softw are lock. Th e second expir ation of the timer causes

a system reset to recover from a hardware lock.

•Processor Present Indicator. The PCH looks for the processor to fetch the first

instruction after reset. If the processor does not fetch the first instruction, the PCH

will reboot the system.

•ECC Error Reporting. When detecting an ECC error, the host controller has the

ability to send one of sev eral messages to the PCH. The host controller can instruct

the PCH to generate either an SMI#, NMI, SERR#, or TCO interrupt.

•Function Disable. Function Disable. The PCH provides the ability to disable most

integrated functions, including integr ated LAN, USB, LPC, Intel HD Audio, SA T A, PCI

Express, and SMBus. Once disabled, functions no longer decode I/O, memory, or

PCI configuration space. Also, no interrupts or power management events are

generated from the disabled functions.

•Intruder Detect. The PCH provides an input signal (INTRUDER#) that can be

attached to a switch that is activated by the system case being opened. The PCH

can be programmed to generate an SMI# or TCO interrupt due to an active

INTRUDER# signal.

Introduction

Intel® C600 Series Chipset and Intel® X79 Express Chipset 49

Datasheet

System Management Bus (SMBus 2.0)

The PCH contains an SMBus Host interface that allows the processor to communicate

with SMBus slaves. This interface is compatible with most I2C devices. Special I2C

commands are implemented.

The PCH’s SMBus host controller provides a mechanism for the processor to initiate

communications with SMBus peripherals (slaves). Also, the PCH supports slave

functionality, including the Host Notify protocol. Hence, the host controller supports

eight command protocols of the SMBus interface (see System Management Bus

(SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write

Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify.

The PCH’s SMBus also implements hardware-based Packet Error Checking for data

robustness and the Address Resolution Protocol (ARP) to dynamically provide address

to all SMBus devices.

Intel® HD Audio Controller

The Intel® High Definition Audio Specification defines a digital interface that can be

used to attach different types of codecs, such as audio and modem codecs. The PCH

Intel® HD Audio controller supports up to 4 codecs. The link can operate at either 3.3 V

or 1.5 V.

With the support of multi-channel audio stream, 32-bit sample depth, and sample rate

up to 192 kHz, the Intel® HD Audio controller provides audio quality that can deliver CE

levels of audio experience. On the input side, the PCH adds support for an array of

microphones.

Fan Speed Control

The PCH integrates four fan speed sensors (four TACH signals) and four fan speed

controllers (three Pulse Width Modulator signals), which enables monitoring and

controlling up to four fans on the system. With the new implementation of the single-

wire Simple Serial Transport (SST) 1.0 bus and Platform Environmental Control

Interface (PECI), the PCH provides an easy way to connect to SST-based thermal

sensors and access the processor thermal data.

Intel® Virtualization Technology for Directed I/O (Intel® VT-d) (Not

available on HEDT SKU)

The PCH provides hardware support for implementation of Intel® Virtualization

Technology with Directed I/O (Intel® VT-d). Intel® VT-d consists of technology

components that support the virtualization of platforms based on Intel® Architecture

Processors. Intel® VT-d 5 technology enables multiple operating systems and

applications to run in independent partitions. A partition behaves like a virtual machine

(VM) and provides isolation and protection across partitions. Each partition is allocated

its own subset of host physical memory.

JTAG Boundary-Scan

The PCH adds the industry standard JTAG interfa ce and enables Boundary-Scan in

place of the XOR chains used in previous generations of chipsets. Boundary-Scan can

be used to ensure device connectivity during the board manufacturing process. The

JTAG interface allows system manufacturers to improve efficiency by using industry

av ailable tools to test th e PCH on an assembled board. Since JTAG is a serial interface,

it eliminates the ne ed to create prob e points for every pin in an XOR ch ain. Thi s ease s

pin breakout and trace routing and simplifies the interface between the system and a

bed-of-nails tester.

Note: Contact your local Intel Field Sales Representative for additional information about

JTAG usage on the PCH.

Introduction

50 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Serial Over Lan (SOL) Function (Not available on HEDTSKU)

This function supports redirection of keyboard and text screens to a terminal window

on a remote console. The keyboard and text redirection enables the control of the client

machine through the network without the need to be physically near that machine. Text

and keyboard redirection allows the remote machine to control and configure a client

system. The SOL function emulates a standard PCI device and redirects the data from

the serial port to the management console using the integrated LAN.

IDE-R Function (Not available on HEDT SKU)

The IDE-R function is an IDE Redirection interface that provides client connection to

management device attached through IDE-R is only visible to software during a

management boot session. During normal boot session, the IDE-R controller does not

appear as a PCI present device.

1.3 Intel® C600 Series Chipset and Intel® X79

Express Chipset SKU Definition

Notes:

1. Contact your local Intel Field Sales Representative for currently av ailable Intel C600 Series Chipset and

Intel X79 Express Chipset SKUs.

2. Table above shows feature difference between Intel C600 Series Chipset and Intel X79 Express Chipset

SKUs. If a feature is not listed in the table it is considered a Base feature that is included in all SKUs.

Table 1-2. Intel® C600 Series Chipset and Intel® X79 Express Chipset SKUs

Product Number SATA 6G

Ports(#)

SCU

Ports(#)

PCIe*

Uplink SM Bus Intel®

AMT

Intel®

VT-D

Intel® C600 Series Chipset (Server/Workstation)

C602 24 (SATA

only) No 4 Yes Yes

C602J 20No4YesYes

C604 24No4YesYes

C606 2 8 Yes 5 Yes Yes

C608 2 8 Yes 6 Yes Yes

Intel® X79 Express Chipset (High End Desktop)

X79 2 No No 3 No No

Signal Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 51

Datasheet

2 Signal Description

This chapter provides a detailed description of each signal. The signals are arranged in

functional groups according to their associated interface.

The “#” symbol at the end of the signal name indicates that the active, or asserted

state occurs when the signal is at a low voltage level. When “#” is not present, the

signal is asserted when at the high voltage level.

The following notations are used to describe the signal type:

IInput Pin

O Output Pin

OD O Open Drain Output Pin.

I/OD Bi-directional Input/Open Drain Output Pin.

I/O Bi-directional Input / Output Pin.

CMOS CMOS buffers. 1.5 V tolerant.

COD CMOS Open Drain buffers. 3.3 V tolerant.

HVCMOS High Voltage CMOS buffers. 3.3 V tolerant.

AAnalog reference or output.

The “Type” for each signal is indicative of the functional operating mode of the signal.

Unless otherwise noted Section 3.2 or Section 3.3, a signal is considered to be in the

functional operating mode after RTCRST# deasserts for signals in the RTC well, after

RSMRST# deasserts for signals in the suspend well, and after PCH_PWROK asserts for

signals in the core well, after DPWROK asserts for Signals in the Deep Sleep well, after

APWROK asserts for Signals in the Active Sleep well.

Signal Description

52 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Figure 2-1. PCH Interface Signals Block Diagram

THRMTRIP#

SYS_RESET#

RSMRST#

SLP_S3#

SLP_S4#

SLP_S5#/GPIO63

SLP_A#

SLP_SUS#

PCH_PWROK

APWROK

PWRBTN#

RI#

WAKE#

GPIO61

SUSCLK/GPIO62

SUSACK#

SYS_PWROK

PLTRST#

SUSWARN#/SUSWRDNACK

BMBUSY#/GPIO0

STP_PCI#/GPIO34

ADR_COMPLETE

DRAMPWROK

LAN_PHY_PWR_CTRL

SLP_LAN#/GPIO29

AD[31:0]

C/BE[3:0]#

DEVSEL#

FRAME#

IRDY#

TRDY#

STOP#

PAR

PERR#

REQ0#

REQ1#/GPIO50

REQ2#/GPIO52

REQ3#/GPIO54

GNT0#

GNT1#/GPIO51

GNT2#/GPIO53

GNT3#/GPIO55

SERR#

PME#

CLKIN_PCILOOPBACK

PCIRST#

PLOCK#

PCI

Interface

PEG0_RXN[3:0], PEG_RXP[3:0]

PEG0_TXN[3:0], PEG0_TXP[3:0]

PEG0_RBIASP, PEG0RBIASN

PCIe Uplink

(PBG - D/T)

Power

Mgnt.

Interrupt

Interface

INIT3_3V#

RCIN#

A20GATE

PROCPWRGD

PM_SYNC;PM_SYNC2

Processor

Interface

USB2

SERIRQ

PIRQ[D:A]#

PIRQ[H:E]#/GPIO[5:2]

USB[13:0]P; USB[13:0]N

OC0#/GPIO59; OC1#/GPIO40

OC2#/GPIO41; OC3#/GPIO42

OC4#/GP IO43; OC 5#/GPIO 9

OC6#/GPIO10; OC7#/GPIO14

USBRBIAS

USBRBIAS#

RTCX1

RTCX2

CLKIN_DMI_P;CLKIN_DMI_N

CLKIN_SATA_[P:N]

CLKIN_DOT96P;CLKIN_DOT96N

REF14CLKIN

CLKIN_SAS0_P;CLKIN_SAS0_N

CLKIN_SAS1_P;CLKIN_SAS1_N

CLKIN_SPCIE0_P;CLKIN_SPCIE0_N

RTC

Clock

Inputs

Misc.

Signals

INTVRMEN

SPKR

SRTCRST#; RTCRST#

DSWODVREN

NMI#

SMI#

General

Purpose

I/O

GPIO[72,57,35,32 , 28, 27,1 5,8]

PWM[3:0]

TACH0/GPIO17; TACH1 /GP IO1

TACH2/GPIO6; TACH3/GPIO7

TACH4/GPIO68; TACH5/GPIO69

TACH6/GPIO70; TACH7/GPIO71

SST

PECI

INTRUDER#;

SML[0:1]DATA;SML[0:1]CLK;

SML0ALERT#/GPIO60

SML1ALERT#/GPIO74

MEM_LED/GPIO24;

DMI[3:0]TXP, DMI[3:0]TXN

DMI[ 3: 0] RX P , DM I [3 :0 ]RX N

DMI_ZCOMP, DMIRBIAS

DMI_IRCOMP

Direct

Media

Interface

LPC / FWH

Interface

SMBus

Interface

HDA_RST#

HDA_SYNC

HDA_BCLK

HDA_SDO

HDA_SDIN[3:0]

Intel®

High

Definition

Audio

System

Mgnt.

LAD[3:0

LFRAME#

LDRQ0#; LDRQ1#/GPIO23

SMBDATA; SMBCLK

SMBALERT#/GPIO11

SATA[5:0]TXP, SATA[5:0]TXN

SATA[5:0]R XP, SATA[5:0] RX N

SATAICOMPO

SATAICOMPI

SATALED#

SATA0GP/GPIO21

SATA1GP/GPIO19

SATA2GP/GPIO36

SATA3GP/GPIO37

SATA4GP/GPIO16

SATA5GP/GPIO49

SCLOCK/GPIO22

SLOAD/GPIO38

SDATAOUT0/GPIO39

SDATAOUT1/GPIO48

Serial ATA

Interface

PCI Expre ss*

Interface PETp[8:1], PETn[8:1]

PERp[8:1], PERn[8:1]

SPI

SPI_CS0#; SPI_CS1#

SPI_MISO

SPI_MOSI

SPI_CLK

JTAG*

Fan Speed

Control JTAGTCK

JTAGTMS

JTAGTDI

JTAGTDO

SAS[3:0]TXP;SAS[3:0]TXN;

SAS[3:0]RXP;SAS[3:0]RXN;

SAS[7:4]T XP; SAS[7:4]TX N; (PBG-D/T)

SAS[7:4]RXP;SAS[7:4]RXN;(PBG-D/T)

SAS_CLOCK1;SAS_LOAD1;

SAS_DATAIN1;SAS_DATAOUT1;

SAS_CLOCK2;SAS_LOAD2;

SAS_DATAIN2;SAS_DATAOUT2;

SAS_LED#

SAS_RBIASP0;SAS_RBIASN0;

SAS_RBIASP1;SAS_RBIASN1;

Serial

Attached

SCSI

Interface

SASSMBCLK0;

SASSMBDATA0;

SASSMBCLK1;

SASSMBDATA1;

SASSMBCLK2;

SASSMBDATA2;

SAS

SMBus

Signal Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 53

Datasheet

2.1 Direct Media Interface (DMI) to Host Controller

2.2 PCI Express*

Table 2-1. Direct Media Interface Signals

Name Type Description

DMI_TXP_0,

DMI_TXN_0 ODirect Media Interface Differential Transmit Pair 0

DMI_RXP_0,

DMI_RXN_0 IDirect Media Interface Differential Receive Pair 0

DMI_TXP_1,

DMI_TXN_1 ODirect Media Interface Differential Transmit Pair 1

DMI_RXP_1,

DMI_RXN_1 IDirect Media Interface Differential Receive Pair 1

DMI_TXP_2,

DMI_TXN_2 ODirect Media Interface Differential Transmit Pair 2

DMI_RXP_2,

DMI_RXN_2 IDirect Media Interface Differential Receive Pair 2

DMI_TXP_3,

DMI_TXN_3 ODirect Media Interface Differential Transmit Pair 3

DMI_RXP_3,

DMI_RXN_3 IDirect Media Interface Differential Receive Pair 3

DMI_ZCOMP IImpedance Compensation Input: Determines DMI input impedance.

DMI_IRCOMP OImpedance/Current Compensation Output: Determines DMI output

impedance and bias current.

DMIRBIAS I/O DMIRBIAS: Analog connection point for 750 Ω ±1% external precision resistor

Table 2-2. PCI Express* Signals

Name Type Description

PETp1, PETn1 OPCI Express* Differential Transmit Pair 1

PERp1, PERn1 IPCI Express Differential Receive Pair 1

PETp2, PETn2 OPCI Express Differential Transmit Pair 2

PERp2, PERn2 IPCI Express Differential Receive Pair 2

PETp3, PETn3 OPCI Express Differential Transmit Pair 3

PERp3, PERn3 IPCI Express Differential Receive Pair 3

PETp4, PETn4 OPCI Express Differential Transmit Pair 4

PERp4, PERn4 IPCI Express Differential Receive Pair 4

PETp5, PETn5 OPCI Express Differential Transmit Pair 5

PERp5, PERn5 IPCI Express Differential Receive Pair 5

PETp6, PETn6 OPCI Express Differential Transmit Pair 6

PERp6, PERn6 IPCI Express Differential Receive Pair 6

PETp7, PETn7 OPCI Express Differential Transmit Pair 7

PERp7, PERn7 IPCI Express Differential Receive Pair 7

PETp8, PETn8 OPCI Express Differential Transmit Pair 8

PERp8, PERn8 IPCI Express Differential Receive Pair 8

Signal Description

54 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

2.3 PCI Express* Uplink (Intel® C606, C608 Chipset

SKUs Only)

Note: These signals are not used on the HEDT SKU PCH and should be no connects.

2.4 PCI Interface

Table 2-3. PCI Express* Uplink Signals

Name Type Description

PEG0_Tp[3:0],

PEG0_Tn[3:0] OPCI Express* Uplink Differential Transmit Pairs

PEG0_Rp[3:0],

PEG0_Rn[3:0] IPCI Express* Uplink Differential Receive Pairs

PEG0_RBIASP,

PEG0_RBIASN IAnalog connection points for an external resistor. Used to set transmit

currents and internal load resistors

Table 2-4. PCI Interface Signals (Sheet 1 of 3)

Name Type Description

AD[31:0] I/O

PCI Address/Data: AD[31:0] is a multiplexed address and data bus. Durin g

the first clock of a transactio n, AD[31:0] contain a physical address (32 bits).

During subsequent clocks, AD[31:0] contain data. The PCH will drive all 0s on

AD[31:0] during the address phase of all PCI Special Cycles.

C/BE[3:0]# I/O

Bus Command and Byte Enables: The command and byte enable signals

are multiplexed on th e same PCI pins. Duri ng the address phase o f a

transaction, C/BE[3:0]# define the bus command. During the data phase C/

BE[3:0]# define the Byte Enables.

All command encodings not shown are reserved. The PCH does not decode

reserved values, and therefore will not respond if a PCI master generates a

cycle using one of th e reserved values.

DEVSEL# I/O

Device Select: The PCH asserts DEVSEL# to claim a PCI transaction. As an

output, the PCH asserts DEV SEL# when a PCI master peripher al attempts an

access to an internal PCH address or an address destined for DMI (main

memory or graph ics). A s an inpu t, DEVS EL# indicat es the response to a PCH -

initiated transaction on the PCI bus. DEVSEL# is tri-stated from the leading

edge of PLTRST#. DEVSEL# remains tri-stated by the PCH until driven by a

target device.

FRAME# I/O

Cycle Frame: The current initiator drives FRAME# to indicate the beginning

and duration of a PCI transaction. While the initiator asserts FRAME#, data

transfers continue. When the initiator negates FRAME#, the transaction is in

the final data phase. FRAME# is an input to the PCH when the PCH is the

target, and FRAME# is an output from the PCH when the PCH is the initiator.

FRAME# remains tri-stated by the PCH until driven by an initiator.

C/BE[3:0]# Command Type

0000b Interrupt Acknowledge

0001b Special Cycle

0010b I/O Read

0011b I/O Write

0110b Memory Read

0111b Memory Write

1010b Configuration Read

1011b Configuration Write

1100b Memory Read Multiple

1110b Memory Read Line

1111b Memory Write and Invalidate

Signal Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 55

Datasheet

IRDY# I/O

Initiator Ready: IRDY# indicates the PCH's ability, as an initiator, to

complete the current data phase of the transaction. It is used in conjunction

with TRDY#. A data phase is completed on any cl ock both IRDY# and TRDY #

are sampled assert ed. During a write, IRD Y# indicates the PCH has valid data

present on AD[31:0]. During a read, it indicates the PCH is prepared to latch

data. IRDY# is an input to the PCH when the PCH is the target and an output

from the PCH when the PCH is an initiator. IRDY# remains tri-stated by the

PCH until driven by an initiator.

TRDY# I/O

Target Ready: TRDY# indicates the PCH's ability as a target to complete the

current data phase of the transaction. TRDY# is used in conjunction with

IRDY#. A data phase is comple ted when both TRD Y# and IRDY# are sampled

asserted. During a read, TRDY# indicates that the PCH, as a target, has

placed valid data on AD[31:0]. During a wr ite, TRDY# indicates the PCH, as a

target is prepared to latch data. TRDY# is an input to the PCH when the PCH

is the initiator and an output from the PCH when the PCH is a target. TRDY#

is tri-stated from the leading edge of PLTRST#. TRDY# remains tri-stated by

the PCH until driven by a target.

STOP# I/O

Stop: STOP# indicates that the PCH, as a target, is requesting the initiator to

stop the current transactio n. STOP# causes the PCH, as an initiator, to stop

the current transaction. STOP# is an output when the PCH is a target and an

input when the PCH is an initiator.

PAR I/O

Calculated/Checked Parity: PAR uses “even” parity calculated on 36 bits,

AD[31:0] plus C/BE[3:0]#. “Even” parity means that the PCH counts the

number of ones within the 36 bits plus PAR and the sum is always even. The

PCH always calculates PAR on 36 bits regardless of the valid byte enables.

The PCH generates PAR for address and data phases and only ensures PAR to

be valid one PCI clock after the corresponding address or data phase. The

PCH drives and tri-states P AR identically to the AD[31:0] lines except that the

PCH delays P AR by exactly one PCI clock. P AR is an output dur ing the address

phase (delayed one clock) for all PCH initiated transactions. PAR is an output

during the data phase (delayed one clock) w hen the PCH is the initiator of a

PCI write transaction, and when it is the target of a read transaction. PCH

checks parity when it is the target of a PCI write transaction. If a parity error

is detected, the PCH will set the appropriate internal status bits, and has the

option to generate an NM I# or SMI#.

PERR# I/O

Parity Error: An external PCI device drives PERR# when it receives data that

has a parity error. The PCH drives PERR# when it detects a parity error. The

PCH can either generate an NMI# or SMI# upon detecting a parity error

(either detected internally or reported using the PERR# signal).

REQ0#

REQ1#/ GPIO50 /

GSXCLK

REQ2#/ GPIO52 /

GSXSLOAD

REQ3#/GPIO54 /

GSXRESET#

PCI Requests: The PCH supports up to 4 masters on the PCI bus.

REQ[3:1]# pins can instead be used as GPIO.

REQ[3:1]# pins can also be use as GSX signals. (See Section 2.23 for

details.)

Notes: External pull-up resistor is required. When used as native

functionality, the pull-up resistor may be to either 3.3 V o r 5.0 V per

PCI specification. When used as GPIO or not used at all, the pull-up

resistor should be to the Vcc3_3 rail

GNT0#

GNT1#/ GPIO51 /

GSXDOUT

GNT2#/ GPIO53 /

GSXDIN

GNT3#/GPIO55

PCI Grants: The PCH supports up to 4 masters on the PCI bus.

GNT[3:1]# pins can instead be used as GPIO.

GNT[2:1]# pins can also be use as GSX signals. (See Section 2.23 for

details.)

Pull-up resistors are n ot required on thes e signals. If pull-ups are used , they

should be tied to the Vcc3_3 power rail.

Note: GNT[3:1]#/GPIO[55,53,51] are sampled as a functional strap. See

Section 2.26.1 for details.

PCIRST# OPCI Reset: This is the Secondary PCI Bus reset signal. It is a logical OR of

the primary interface PLTRST# signal and the state of the Secondary Bus

Reset bit of the Bridge Control register (D30:F0:3Eh, bit 6).

PLOCK# I/O

PCI Lock: This signal ind icates an exclusive bus operation and m ay require

multiple transactions to complete. PCH asserts PLOCK# when it performs

non-exclusive transactions on the PCI bus. PLOCK# is ignored when PCI

masters are granted the bus.

SERR# I/OD System Error: SERR# can be pulsed active by an y PCI device that detects a

system error condition. Upon sampling SERR# active, the PCH has the abili ty

to generate an NMI, SMI#, or interrupt.

Table 2-4. PCI Interface Signals (Sheet 2 of 3)

Name Type Description

Signal Description

56 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

2.5 Serial ATA Interface

PME# I/OD

PCI Power Management Event: PCI peripherals drive PME# to wake the

system from low-power stat es S1–S5. PM E# assertion can also be enab led to

generate an SCI from the S0 state. In some cases the PCH may drive PME#

active due to an internal wake event. The PCH will not drive PME# high, but it

will be pulled up to VccSus3_3 by an internal pull-up resistor.

Table 2-5. Serial ATA Interface Signals (Sheet 1 of 2)

Name Type Description

SATA0TXP

SATA0TXN O

Serial ATA 0 Differential Transmit Pairs: These are outbound high-speed

differential signals to Port 0.

In compatible mode, SATA Port 0 is the primary master of SATA Controller 1.

Supports up to 6 Gb/s, 3 Gb/s, and 1.5 Gb/s.

SATA0RXP

SATA0RXN I

Serial ATA 0 Differential Receive Pair: These are inbound high-speed

differential signals from Port 0.

In compatible mode, SATA Port 0 is the primary master of SATA Controller 1.

Supports up to 6 Gb/s, 3 Gb/s, and 1.5 Gb/s.

SATA1TXP

SATA1TXN O

Serial ATA 1 Differential Transmit Pair: These are outbound high-speed

differential signals to Port 1.

In compatible mode, SAT A Port 1 is the secondary master of SATA Controller 1.

Supports up to 6 Gb/s, 3 Gb/s, and 1.5 Gb/s.

SATA1RXP

SATA1RXN I

Serial ATA 1 Differential Receive Pair: These are inbound high-speed

differential signals from Port 1.

In compatible mode, SAT A Port 1 is the secondary master of SATA Controller 1.

Supports up to 6 Gb/s, 3 Gb/s, and 1.5 Gb/s.

SATA2TXP

SATA2TXN O

Serial ATA 2 Differential Transmit Pair: These are outbound high-speed

differential signals to Port 2.

In compatible mode, SATA Port 2 is the primary slave of SATA Controller 1.

Supports up to 3 Gb/s and 1.5 Gb/s.

SATA2RXP

SATA2RXN I

Serial ATA 2 Differential Receive Pair: These are inbound high-speed

differential signals from Port 2.

In compatible mode, SATA Port 2 is the primary slave of SATA Controller 1

Supports up to 3 Gb/s and 1.5 Gb/s.

SATA3TXP

SATA3TXN O

Serial ATA 3 Differential Transmit Pair: These are outbound high-speed

differential signals to Port 3

In compatible mode, SATA Port 3 is the secondary slave of SATA Controller 1

Supports up to 3 Gb/s and 1.5 Gb/s.

SATA3RXP

SATA3RXN I

Serial ATA 3 Differential Receive Pair: These are inbound high-speed

differential signals from Port 3

In compatible mode, SATA Port 3 is the secondary slave of SATA Controller 1

Supports up to 3 Gb/s and 1.5 Gb/s.

SATA4TXP

SATA4TXN O

Serial ATA 4 Differential Transmit Pair: These are outbound high-speed

differential signals to Port 4.

In compatible mode, SATA Port 4 is the primary master of SATA Controller 2.

Supports up to 3 Gb/s and 1.5 Gb/s.

SATA4RXP

SATA4RXN I

Serial ATA 4 Differential Receive Pair: These are inbound high-speed

differential signals from Port 4.

In compatible mode, SATA Port 4 is the primary master of SATA Controller 2.

Supports up to 3 Gb/s and 1.5 Gb/s.

SATA5TXP

SATA5TXN O

Serial ATA 5 Differential Transmit Pair: These are outbound high-speed

differential signals to Port 5.

In compatible mode, SAT A Port 5 is the secondary master of SATA Controller 2.

Supports up to 3 Gb/s and 1.5 Gb/s.

Table 2-4. PCI Interface Signals (Sheet 3 of 3)

Name Type Description

Signal Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 57

Datasheet

SATA5RXP

SATA5RXN I

Serial ATA 5 Differential Receive Pair: These are inbound high-speed

differential signals from Port 5.

In compatible mode, SAT A P ort 5 is the secon dary master of SAT A Controller 2.

Supports up to 3 Gb/s and 1.5 Gb/s.

SATAICOMPO OSerial ATA Compensation Output: Connected to an external precision

resistor to VccCore. Must be connected to SATAICOMPI on the board.

SATAICOMPI ISerial ATA Compensation Input: Connected to SATAICOMPO on the

board.

SATA0GP /

GPIO21 I

Serial ATA 0 General Purpose: This is an input pin which can be configured

as an interlock switch corresponding to SAT A Port 0. When used as an interlock

switch status indication, this signal should be drive to ‘0’ to indicate that the

switch is closed and to ‘1’ to indicate that the switch is open.

If interlock switches are not required, this pin can be configured as GPIO21.

SATA1GP /

GPIO19 ISerial ATA 1 General Purpose: Same function as SATA0GP, except for SATA

Port 1.

If interlock switches are not required, this pin can be configured as GPIO19.

SATA2GP /

GPIO36 ISerial ATA 2 General Purpose: Same function as SATA0GP, except for SATA

Port 2.

If interlock switches are not required, this pin can be configured as GPIO36.

SATA3GP /

GPIO37 ISerial ATA 3 General Purpose: Same function as SATA0GP, except for SATA

Port 3.

If interlock switches are not required, this pin can be configured as GPIO37.

SATA4GP /

GPIO16 ISerial ATA 4 General Purpose: Same function as SATA0GP, except for SATA

Port 4.

If interlock switches are not required, this pin can be configured as GPIO16.

SATA5GP /

GPIO49 /

TEMP_ALERT# I

Serial ATA 5 General Purpose: Same function as SATA0GP, except for SATA

Port 5.

If interlock switches are not required, this pin can be configured as GPIO49 or

TEMP_ALERT#.

SATALED# OD O

Serial ATA LED: This signal is an open-drain output pin driven during SATA

command activity. It is to be connected to external circuitry that can provide

the current to drive a platform LED. When active, the LED is on. When tri-

stated, the LED is off. An external pull-up resistor to Vcc3_3 is required.

SCLOCK/GPIO22 O D O

SGPIO Reference Clock: The SATA controller uses rising edges of this clock

to transmit serial data, and the target uses the falling edge of this clock to

latch data. The SCLOCK frequency supported is 32 kHz.

If SGPIO interface is not used, this signal can be used as a GPIO22.

SLOAD/GPIO38 OD O

SGPIO Load: The controller drives a ‘1’ at the rising edge of SCLOCK to

indicate either the start or end of a bit stream. A 4-bit vendor specific pattern

will be transmitted right after the signal assertion.

If SGPIO interface is not used, this signal can be used as a GPIO.

SDATAOUT0/

GPIO39

SDATAOUT1/

GPIO48

OD O SGPIO Dataout: Driven by the controller to indicate the drive status in the

following sequence: drive 0, 1, 2, 3, 4, 5, 0, 1, 2...

If SGPIO interface is not used, the signals can be used as GPIO.

SATA3RBIAS I/O DMI RBIAS: Analog connection point for an external precision resistor.

SATA3COMPI IImpedance Compensation Input: Connected to a 50 ohm (1%) precision

external pull-up resistor to vccsata3.

SATA3COMPO OImpedance/Current Compensation Output: Connected to a 50 ohm (1%)

precision external pull-up resistor.to vccsata3.

Table 2-5. Serial ATA Interface Signals (Sheet 2 of 2)

Name Type Description

Signal Description

58 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

2.6 SAS Interface (SRV/WS SKUs Only)

Note: These signals are not used on the HEDT SKU.

Table 2-6. SAS Interface Signals (Sheet 1 of 2)

Name Type Description

SAS0TXP

SAS0TXN O

SAS/SATA 0 Differential Transmit Pairs: These are outbound high-

speed differential signals to Port 0.

Note: On Intel C602 Chipset SKU, work as SATA port only.

Note: On HEDT SKU, these signals should be no connects.

SAS0RXP

SAS0RXN I

SAS/SATA 0 Differential Receive Pair: These are inbound high-speed

differential signals from Port 0.

Note: On Intel C602 Chipset, work as SATA port only.

Note: On HEDT SKU, these signals should be no connects.

SAS1TXP

SAS1TXN O

SAS/SATA 1 Differential Transmit Pairs: These are outbound high-

speed differential signals to Port 1.

Note: On Intel C602 Chipset, work as SATA port only.

Note: On HEDT SKU, these signals should be no connects.

SAS1RXP

SAS1RXN I

SAS/SATA 1 Differential Receive Pair: These are inbound high-speed

differential signals from Port 1.

Note: On Intel C602 Chipset, work as SATA port only.

Note: On HEDT SKU, these signals should be no connects.

SAS2TXP

SAS2TXN O

SAS/SATA 2 Differential Transmit Pairs: These are outbound high-

speed differential signals to Port 2.

Note: On Intel C602 Chipset, work as SATA port only.

Note: On HEDT SKU, these signals should be no connects.

SAS2RXP

SAS2RXN I

SAS/SATA 2 Differential Receive Pair: These are inbound high-speed

differential signals from Port 2.

Note: On Intel C602 Chipset, work as SATA only.

Note: On HEDT SKU, these signals should be no connects.

SAS3TXP

SAS3TXN O

SAS/SATA 3 Differential Transmit Pairs: These are outbound high-

speed differential signals to Port 3.

Note: On Intel C602 Chipset, work as SATA port only.

Note: On HEDT SKU, these signals should be no connects.

SAS3RXP

SAS3RXN I

SAS/SATA 3 Differential Receive Pair: These are inbound high-speed

differential signals from Port 3.

Note: On Intel C602 Chipset, work as SATA port only.

Note: On HEDT SKU, these signals should be no connects.

SAS4TXP

SAS4TXN

(Intel® C606, C608

Chipset SKUs Only)

OSAS 4 Differential Transmit Pairs: These are outbound hi gh-speed

differential signals to Port 4.

Note: On HEDT SKU, these signals should be no connects.

SAS4RXP

SAS4RXN

(Intel® C606, C608

Chipset SKUs Only)

ISAS 4 Differential Receive Pair: These are inbound high-speed

differential signals from Port 4.

Note: On HEDT SKU, these signals should be no connects.

SAS5TXP

SAS5TXN

(Intel® C606, C608

Chipset SKUs Only)

OSAS 5 Differential Transmit Pairs: These are outbound hi gh-speed

differential signals to Port 5.

Note: On HEDT SKU, these signals should be no connects.

SAS5RXP

SAS5RXN

(Intel® C606, C608

Chipset SKUs Only)

ISAS 5 Differential Receive Pair: These are inbound high-speed

differential signals from Port 5.

Note: On HEDT SKU, these signals should be no connects.

SAS6TXP

SAS6TXN

(Intel® C606, C608

Chipset SKUs Only)

OSAS 6 Differential Transmit Pairs: These are outbound hi gh-speed

differential signals to Port 6.

Note: On HEDT SKU, these signals should be no connects.

SAS6RXP

SAS6RXN

(Intel® C606, C608

Chipset SKUs Only)

ISAS 6 Differential Receive Pair: These are inbound high-speed

differential signals from Port 6.

Note: On HEDT SKU, these signals should be no connects.

Signal Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 59

Datasheet

SAS7TXP

SAS7TXN

(Intel® C606, C608

Chipset SKUs Only)

OSAS 7 Differential Transmit Pairs: These are outbound high-speed

differential signals to Port 7.

Note: On HEDT SKU, these signals should be no connects.

SAS7RXP

SAS7RXN

(Intel® C606, C608

Chipset SKUs Only)

ISAS 7 Differential Receive Pair: These are inbound high-speed

differential signals from Port 7.

Note: On HEDT SKU, these signals should be no connects.

SAS_CLOCK1 OSCU SGPIO reference clock

Note: On HEDT SKU, this signal should be no connect.

SAS_LOAD1 OSCU SGPIO load

Note: On HEDT SKU, this signal should be no connect.

SAS_DATAIN1 OSCU SGPIO data in

Note: On HEDT SKU, this signal should be no connect.

SAS_DATAOUT1 OSCU SGPIO data out

Note: On HEDT SKU, this signal should be no connect.

SAS_CLOCK2

(Intel® C606, C608

Chipset SKUs Only) OUsed in Intel® C606, C608 Chipset SKUs Only

Note: On HEDT SKU, this signal should be no connect.

SAS_LOAD2

(Intel® C606, C608

Chipset SKUs Only) OUsed in Intel® C606, C608 Chipset SKUs Only

Note: On HEDT SKU, this signal should be no connect.

SAS_DATAIN2

(Intel® C606, C608

Chipset SKUs Only) OUsed in Intel® C606, C608 Chipset SKUs Only

Note: On HEDT SKU, these signals should be no connects.

SAS_DATAOUT2

(Intel® C606, C608

Chipset SKUs Only) OUsed in Intel® C606, C608 Chipset SKUs Only

Note: On HEDT SKU, this signal should be no connect.

SAS_LED# OOpen drain pin used to control the Front Panel LED.

Note: On HEDT SKU, this signal should be no connect.

SAS_RBIASP0 I

Analog connection points for an external resistor. Used to set transmit

internal loads and currents.

Notes: On HEDT SKU, this signal tied to SAS_RBIASN0 through a

6.0 KΩ ±1% resistor. SAS_RBIAS NO should be connected to VSS

at the resistor.

SAS_RBIASN0 I

Analog connection points for an external resistor. Used to set transmit

internal loads and currents.

Note: On HEDT SKU, this signal tied to SAS_RBIASN0 through a

6.0 KΩ ±1% resistor. SAS_RBIAS NO should be connected to VSS

at the resistor.

SAS_RBIASP1

(Intel® C606, C608

Chipset SKUs Only) IAnalog connection points for an external resistor. Used to set transmit

internal loads and currents.

Note: On HEDT SKU, this signal should be no connect.

SAS_RBIASN1

(Intel® C606, C608

Chipset SKUs Only) IAnalog connection points for an external resistor. Used to set transmit

internal loads and currents.

Note: On HEDT SKU, this signal should be no connect.

Table 2-6. SAS Interface Signals (Sheet 2 of 2)

Name Type Description

Signal Description

60 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

2.7 LPC Interface

2.8 Interrupt Interface

Note: PIRQ Interrupts can only be shared if it is configured as level sensitive. They cannot be

shared if configured as edge triggered.

Table 2-7. LPC Interface Signals

Name Type Description

LAD[3:0] I/O LPC Multiplexed Command, Address, Data: For LAD[3:0], internal pull-ups are

provided.

LFRAME# OLPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort.

LDRQ0#,

LDRQ1# /

GPIO23 I

LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to request DMA or

bus master access. These signals are typically connected to an external Super I/O

device. An internal pull-up resistor is provided on these signals.

LDRQ1# may optionally be used as GPIO.

Table 2-8. Interrupt Signals

Name Type Description

SERIRQ I/OD Serial Interrupt Request: This pin implements the serial interrupt protocol.

PIRQ[D:A]# I/OD

PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can be routed

to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in Section 5.9.6.

Each PIRQx# line has a separate Route Control register.

In APIC mode, these signals are connecte d to the internal I/O APIC in the

following fashion: PIRQA# is connected to IRQ16, PIRQB# to IRQ17, PIRQC# to

IRQ18, and PIRQD# to IRQ19. This frees the legacy interrupts.

These signals are 5 V tolerant.

PIRQ[H:E]# /

GPIO[5:2] I/OD

PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can be routed

to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in Section 5.9.6.

Each PIRQx# line has a separate Route Control register.

In APIC mode, these signals are connecte d to the internal I/O APIC in the

following fashion: PIRQE# is connected to IRQ20, PIRQF# to IRQ21, PIRQG# to

IRQ22, and PIRQH# to IRQ23. This frees the legacy interrupts. If not needed for

interrupts, these signals can be used as GPIO.

These signals are 5 V tolerant.

Signal Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 61

Datasheet

2.9 USB 2.0 Interface

Table 2-9. USB 2.0 Interface Signals (Sheet 1 of 2)

Name Type Description

USBP0P,

USBP0N,

USBP1P,

USBP1N

I/O

Universal Serial Bus Port [1:0] Differential: These differential pairs are

used to transmit Data/Ad dress/Command signals for ports 0 and 1. These por ts

can be routed to EHCI controller #1.

Note: No external resisto rs are required on these signals. The PCH integr ates

15 kΩ pull-downs and provides an output dr iver impedance of 45 Ω

which requires no external series resistor.

USBP2P,

USBP2N,

USBP3P,

USBP3N

I/O

Universal Serial Bus Port [3:2] Differential: These differential pairs are

used to tr ans mit data/ad dr es s/co mmand sig nals for ports 2 and 3. These ports

can be routed to EHCI controller #1.

Note: No external resisto rs are required on these signals. The PCH integr ates

15 kΩ pull-downs and provides an output dr iver impedance of 45 Ω

which requires no external series resistor.

USBP4P,

USBP4N,

USBP5P,

USBP5N

I/O

Universal Serial Bus Port [5:4] Differential: These differential pairs are

used to transmit Data/Ad dress/Command signals for ports 4 and 5. These por ts

can be routed to EHCI controller #1.

Note: No external resisto rs are required on these signals. The PCH integr ates

15 kΩ pull-downs and provides an output dr iver impedance of 45 Ω

which requires no external series resistor.

USBP6P,

USBP6N,

USBP7P,

USBP7N

I/O

Universal Serial Bus Port [7:6] Differential: These differential pairs are

used to transmit Data/Ad dress/Command signals for ports 6 and 7. These por ts

can be routed to EHCI controller #1.

Note: No external resisto rs are required on these signals. The PCH integr ates

15 kΩ pull-downs and provides an output dr iver impedance of 45 Ω

which requires no external series resistor.

USBP8P,

USBP8N,

USBP9P,

USBP9N

I/O

Universal Serial Bus Port [9:8] Differential: These differential pairs are

used to transmit Data/Ad dress/Command signals for ports 8 and 9. These por ts

can be routed to EHCI controller #2.

Note: No external resisto rs are required on these signals. The PCH integr ates

15 kΩ pull-downs and provides an output dr iver impedance of 45 Ω

which requires no external series resistor.

USBP10P,

USBP10N,

USBP11P,

USBP11N

I/O

Universal Serial Bus Port [11:10] Differential: These differential pairs are

used to transmit Data/Address/Command signals for ports 10 and 11. These

ports can be routed to EHCI controller #2.

Note: No external resisto rs are required on these signals. The PCH integr ates

15 kΩ pull-downs and provides an output dr iver impedance of 45 Ω

which requires no external series resistor.

USBP12P,

USBP12N,

USBP13P,

USBP13N

I/O

Universal Serial Bus Port [13:12] Differential: These differential pairs are

used to transmit Data/Address/Command signals for ports 13 and 12. These

ports can be routed to EHCI controller #2.

Note: No external resisto rs are required on these signals. The PCH integr ates

15 kΩ pull-downs and provides an output dr iver impedance of 45 Ω

which requires no external series resistor.

Signal Description

62 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

2.10 Power Management Interface

Note: Upon entry to S5 due to a power button override, if Deep S4/S5 is enabled and

conditions are met per Section 5.14.6.6, the system will transition to Deep S4/S5.

OC0# / GPIO59

OC1# / GPIO40

OC2# / GPIO41

OC3# / GPIO42

OC4# / GPIO43

OC5# / GPIO9

OC6# / GPIO10

OC7# / GPIO14

Overcurrent Indicators: These signals set corresponding bits in the USB

controllers to indicate that an overcurrent condition has occurred.

OC[7:0]# may optionally be used as GPIOs.

Notes:

1. OC# pins are not 5 V tolerant.

2. OC# pins must be shared between ports

3. OC#[3:0] can only be used for EHCI controller #1

4. OC#[4:7] can only be used for EHCI controller #2

USBRBIAS OUSB Resistor Bias: Analog connection point for an external resistor. Used to

set transmit currents and internal load resistors.

USBRBIAS# IUSB Resistor Bias Complement: Analog connection point for an external

resistor. Used to set transmit currents and internal load resistors.

Table 2-10. Power Management Interface Signals (Sheet 1 of 3)

Name Type Description

APWROK IActive Sleep Well (ASW) Power OK: When asserted, indicates that power to

the ASW sub-system is stable.

BMBUSY#

/ GPIO0 I

Bus Master Busy: Generic bus master activity indication driven into the PCH.

Can be configured to set the PM1_STS.BM_STS bit. Can also be configured to

assert indications transmitted from the PCH to the Processor using the

PM_SYNC pin.

DPWROK IDPWROK: Power OK Indication for the VccDSW3_3 voltage rail. This input is

tied together with RSMRST# on platforms that do not support Deep S4/S5.

This signal is in the RTC well.

DRAMPWROK OD O

DRAM Power OK: This signal should connect to the Processor’s

SM_DRAMPWROK pin. The PCH asserts this pin to indicate when D RAM power is

stable.

This pin requires an external pull-up.

LAN_PHY_PWR_

CTRL / GPIO12 O

LAN PHY Power Control: LAN_PHY_PWR_CTRL should be connected to

LAN_DISABLE_N on the PHY. The PCH will drive LAN_PHY_PWR_CTRL low to put

the PHY into a low power state when functionality is not needed.

Note: LAN_PHY_PWR_CTRL can only be driven low if SLP_LAN# is

deasserted. Signal can instead be used as GPIO12.

PLTRST# O

Platform Reset: The PCH asserts PLTRST# to reset devices on the platform

(for example, SIO, FWH, LAN, Processor, etc.). The PCH asserts PLTRST# during

power-up and when S/W initiates a hard reset sequence through the Reset

Control register (I/O R egister CF9h). The PCH drives PL TRST# activ e a minimum

of 1 ms when initiated through the Reset Control register (I/O Register CF9h).

Note: PLTRST# is in the VccSus3_3 well.

PWRBTN# I

Power Button: The Power Button will cause SMI# or SCI to indicate a system

request to go to a sleep state. If the system is already in a sleep state, this

signal will cause a wake ev ent. If PWRBTN# is pressed for more than 4 seconds,

this will cause an unconditional transition (power button override) to the S5

state. Override will occur even if the system is in the S1–S4 states. This signal

has an internal pull-up resistor and has an internal 16 ms de-bounce on the

input. This signal is in the DSW well.

Note: Upon entry to S5 due to a power button override, if Deep S4/S5 is

enabled and conditions are met per Section 5.14.6.6, the system will

transition to Deep S4/S5.

Table 2-9. USB 2.0 Interface Signals (Sheet 2 of 2)

Name Type Description

Signal Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 63

Datasheet

PCH_PWROK I

Power OK: When asserted, PCH_PWROK is an indication to PCH that all of its

core powerrails has been stable for at least 10 ms. PCH_PWROK can be driven

asynchronously. When PCH_PWROK is negated, the PCH asserts PLTRST#.

Note: It is required that the powerrails associated with PCI/PCIe* (typically

the 3.3 V, 5 V, and 12 V core well rails) hav e been valid for 99 ms prior

to PCH_PWROK assertion in order to comply with the 100 ms PCI 2.3/

PCIe 1.1 specification on PLTRST# deassertion. PCH_PWROK must not

glitch, even if RSMRST# is low.

RI# IRing Indicate: This signal is an input from a modem. It can be enabled as a

wake event, and this is preserved across power failures.

RSMRST# I

Resume Well Reset: This signal is used for resetting the resume power plane

logic. This signal must remain asserted for at least 10 ms after the suspend

power wells are valid. When deasserted, this signal is an indication that the

suspend power wells are stable.

SLP_A# OSLP_A#: Used to control power to the active sleep well (ASW) of the PCH.

SLP_LAN# /

GPIO29 O

LAN Sub-System Sleep Control: When SLP_LAN# is deasserted it indicates

that the PHY device must be powered. When SLP_LAN# is asserted, power can

be shut off to the PHY device. SLP_LAN# will always be deasserted in S0 and

anytime SLP_A# is deasserted.

A SLP_LAN#/GPIO Select Soft-Strap can be used for systems NOT using

SLP_LAN# functionality to revert to GPIO29 usage. When soft-strap is 0

(default), pin function will be SLP_LAN#. When soft-strap is set to 1, the pin

returns to its regular GPIO mode.

The pin behavior is summarized in Section 5.14.9.4

SLP_S3# OS3 Sleep Control: SLP_S3# is for power plane control. This signal shuts off

power to all non-critical systems when in S3 (Suspend T o RAM), S4 (Suspend to

Disk), or S5 (Soft Off) states.

SLP_S4# O

S4 Sleep Control: Power plane control. Shuts power to non-critical systems

when in the S4 (Suspend to Disk) or S5 (Soft Off) state. This pin must be used

to control the DRAM power in order to use the PCH’s DRAM power-cycling

feature.

Note: This pin must be used to control the DRAM power in order to use the

PCH’ s DRA M power -cyc ling featu re. R e fer to Section 5.14.9.2 for details

SLP_S5# /

GPIO63 OS5 Sleep Control: SLP_S5# is for power plane control. This signal is used to

shut power off to all non-critical systems when in the S5 (Soft Off) states.

Pin may also be used as GPIO63.

SLP_SUS# O

Deep S4/S5 Indication: When asserted (low), this signal indi cates PCH is

in Deep S4/S5 state where internal Sus power is shut off for enhanced power

saving. When deasserted (high), this signal indicates exit from Deep S4/S5

state and Sus power can be applied to PCH.

If Deep S4/S5 is not supported, then this pin can be left unconnected.

This pin is in the DSW power well.

SUSACK# I

SUSACK#: If Deep S4/S5 is supported, the EC must change SUSACK# to

match SUSWAR N# once the EC has completed the preparations dis cussed in the

description for the SUSWARN# pin.

Note: SUSWARN# must only change in response to SUSACK# if Deep S4/S5

is supported by the platform.

This pin is in the Sus power well.

SUSCLK /GPIO62 O Suspend Clock: This clock is an output of the RTC generator circuit to use by

other chips for refresh clock.

Pin may also be used as GPIO62.

Table 2-10. Power Management Interface Signals (Sheet 2 of 3)

Name Type Description

Signal Description

64 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

2.11 Processor Interface

SUSWARN#

GPIO30 / O

SUSWARN#: This pin asserts low when the PCH is planning to enter the Deep

S4/S5 power state and remove Suspend p ower (using SLP_SUS#). The EC must

observe edges on this pin, preparing for SUS well power loss on a falling edge

and preparing for SUS well related activity (host/Intel ME wakes and runtime

events) on a rising edge. S USACK# should be asserted within a minimal amount

of time from SUSWARN# assertion, as no wake events are supported if

SUSWARN# is asserted, but SUSACK# is not asserted. Pla tforms supportin g

Deep S4/S5, but not wishing to participate in the handshake during wake and

Deep S4/S5 entry may tie SUSACK# to SUSWARN#.

This pin may be muxed with a GPIO for u se in systems that do n ot support Deep

S4/S5.

Reset type: RSMRST#

This signal is muxed with GPIO30

SYS_PWROK I

System Power OK: This generic power good input to the PCH is driven and

utilized in a platform-specific manner. While PCH_PWROK always indicates that

the CORE well of the PCH is stable, SYS_PWROK is used to inform the PCH that

power is stable to some other system component(s) and the system is ready to

start the exit from reset.

SYS_RESET# ISystem Reset: This pin forces an internal reset after being debounced. The

PCH will reset immediately if the SMBus is idle; otherwise, it will wait up to

25 ms ± 2 ms for the SMBus to idle before forcing a reset on the system.

WAKE# IPCI Express* Wake Event: Sideband wake si gnal on PCI Expre ss asse rted by

components requesting wake up.

ADR_COMPLETE O This pin is not used for server designs.

Table 2-11. Processor Interface Signals

Name Type Description

RCIN# I

Keyboard Controller Reset CPU: The keyboard controller can generate

INIT# to the processor. This saves the external OR gate with the PCH’s other

sources of INIT#. When the PCH detects the assertion of this signal, INIT# is

generated for 16 PCI clocks.

Note: The PCH will ignore RCIN# assertion during transitions to the S3, S4,

and S5 states.

A20GATE IA20 Gate: Functionality reserved. A20M# functionality is not supported.

PROCPWRGD OProcessor Power Good: This signal should be connected to the processor’s

PWRGOOD input to indicate when the processor power is valid.

PM_SYNC OPower Management Sync: Provides state information from the PCH to the

Processor relevant to C-state transitions.

PM_SYNC2 OPower Management Sync 2: Provides state information from the PCH to the

Processor relevant to C-state transitions. Used only in a 4 -socket system.

THRMTRIP# I

Thermal Trip: When low, this signal indicates that a thermal trip from the

processor occurred, and the PCH will immediately transition to a S5 state. The

PCH will not wait for the processor stop grant cycle since the processor has

overheated.

Table 2-10. Power Management Interface Signals (Sheet 3 of 3)

Name Type Description

Signal Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 65

Datasheet

2.12 SMBus Interface

2.13 System Management Interface

2.14 SAS System Management Interface (SRV/WS

SKUs Only)

Note: These signals are not used on the HEDT SKU. Theses signals should be no connects on

HEDT platform designs.

Table 2-12. SM Bus Interface Signals

Name Type Description

SMBDATA I/OD SMBus Data: External pull-up resistor is required.

SMBCLK I/OD SMBus Clock: External pull-up resistor is required.

SMBALERT# /

GPIO11 ISMBus Alert: This signal is used to wake the system or generate SMI#.

This signal may be used as GPIO11.

Table 2-13. System Management Interface Signals

Name Type Description

INTRUDER# IIntruder Detect: This signal ca n be set to disable sys t em if box detected

open. This signal’s status is readable; thus, it can be used like a GPI if the

Intruder Detection is not needed.

SML0DATA I/OD System Management Link 0 Data: SMBus link to external PHY. External pull-

up is required.

SML0CLK I/OD System Management Link 0 Clock: SMBus link to external PHY. External

pull-up is required.

SML0ALERT# /

GPIO60 / O OD SMLink Alert 0: Output of the integrated LAN controller to external PHY.

External pull-up resistor is required.

This signal can instead be used as a GPIO60.

SML1ALERT# /

PCHHOT#/GPIO74 O OD

PCHHOT#: This signal is used to indicate a PCH temperature out of bounds

condition to an external EC, when PCH temperature is greater than value

programmed by BIOS. An external pull-up resistor is required on this signal.

Note: A soft-strap determines the native function SML1ALERT# or PCHHOT#

usage. When soft-strap is 0, function is SML1ALERT#, when soft-strap

is 1, function is PCHHOT#.

SML1CLK / GPIO58 I/OD System Management Link 1 Clock: SMBus link to optional Embedded

Controller or BMC. External pull-up resistor is required.

SML1DATA /

GPIO75 I/OD System Management Link 1 Data: SMBus link to optional Embedded

Controller or BMC. External pull-up resistor is required.

Table 2-14. SAS System Management Interface Signals (Sheet 1 of 2)

Name Type Description

SASSMBDATA0 I/O SAS dedicated SMBus Master data

SASSMBCLK0 O SAS dedicated SMBus Master Clock

SASSMBDATA1

(Intel® C606, C608 Chipset

SKUs Only) I/O SAS dedicat ed SMBus Master data

Signal Description

66 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

2.15 Real Time Clock Interface

2.16 Miscellaneous Signals

SASSMBCL0K1

(Intel® C606, C608 Chipset

SKUs Only) O SAS dedicated SMBus Master Clock

SASSMBDATA2

(Intel® C608 Chipset SKUs

Only) I/O SAS dedicated SMBus Master data

SASSMBCLK2

(Intel® C608 Chipset SKUs

Only) O SAS dedicated SMBus Master Clock

Table 2-15. Real Time Clock Interface

Name Type Description

RTCX1 Special Crystal Input 1: This signal is connected to the 32.768 kHz crystal. If no

external crystal is used, then RTCX1 can be driven with the desired clock rate.

RTCX2 Special Crystal Input 2: This signal is connected to the 32.768 kHz crystal. If no

external crystal is used, then RTCX2 should be left floating.

Table 2-16. Miscellaneous Signals (Sheet 1 of 2)

Name Type Description

INTVRMEN I

Internal Voltage Regulator Enable: This signal enables the internal 1.5 V

regulators.

This signal must be always pulled-up to VccRTC.

Note: See VccCore signal description for behavior when INTVRMEN is

sampled low (external VR mode).

DSWODVREN IDeep Sleep Well Internal Voltage Regulator Enable: This signal enables

the internal Deep Sleep 1.1 V regulators.

This signal must be always pulled up to VccRTC.

SPKR O

Speaker: The SPKR signal is the out put of c ounter 2 and is internal ly “ANDed”

with Port 61h bit 1 to provide Speaker Data Enable. This signal drives an

external speaker driver device, which in turn drives the system speaker. Upon

PLTRST#, its output state is 0.

Note: SPKR is sampled as a functional strap. See Section 2.26.1 for more

details. There is a weak integrated pull-down resistor on SPKR pin.

RTCRST# I

RTC Reset: When asserted, this signal resets register bits in the RTC well.

Notes:

1. Unless CMOS is being cleared (o nly to be done in the G3 po wer state),

the RTCRST# input must always be h igh when all other RTC power

planes are on.

2. In the case where the RTC battery is dead or mis sing on the plat form,

the RTCRST# pin must rise before the DPWROK pin.

SRTCRST# I

Secondary RTC Reset: This signal resets the manageability register bits in

the RTC well when the RTC battery is removed.

Notes:

1. The SRTCRST# input must always be high when all other RTC power

planes are on.

2. In the case where the RTC battery is dead or mis sing on the plat form,

the SRTCRST# pin must rise before the DPWROK pin.

Table 2-14. SAS System Management Interface Signals (Sheet 2 of 2)

Name Type Description

Signal Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 67

Datasheet

2.17 Intel® High Definition Audio (Intel® HD Audio)

Link

SML1ALERT#/

PCHHOT#/

GPIO74

PCHHOT#: This signal is used to indicate a PCH temperature out of bounds

condition to an external EC, when PCH temperature is greater than value

programmed by BIOS. An external pull-up resistor is required on this signal.

Note: A soft-str ap determine s the native function SML1ALE R T# or PCHHO T#

usage. When soft -strap is 0, function is SML1ALERT#, when soft -s tr ap

is 1, function is PCHHOT#.

INIT3_3V# OInitialization 3.3 V: INIT3_3V# is asserted by the PCH for 16 PCI clocks to

reset the processor. This signal is intended for Firmware Hub.

NMI#/

GPIO35 ONon-Maskable Interrupt: NMI# is used to force a non-Maskable interrupt to

the process or.

Note: The NMI # function is enabled using softstrap

SMI# /

GPIO20 O

System Management Interrupt: SMI# is an active low output synchronous

to PCICLK. It is asserted by the PCH in response to one of many enabled

hardware or software events.

Note: The SMI# function is enabled using softstrap

Table 2-17. Intel® High Definition Audio (Intel® HD Audio) Link Signals

Name Type Description

HDA_RST# OIntel HD Audio Reset: Master hardware reset to external codec(s).

HDA_SYNC O

Intel HD Audio Sync: 48 kHz fixed rate sample sync to the codec(s).

Also used to enco de the stream number.

Note: This signal is sampled as a functional s trap. See Section 2.26.1 for

more details. There is a weak integrated pull-down resistor on this

pin.

HDA_BCLK OIntel HD Audio Bit Clock Output: 24.000 MHz serial data clock

generated by th e Intel High Definition Audio c ontroller (the PCH). This

signal has a weak internal pull-down resistor.

HDA_SDO O

Intel HD Audio Serial Data Out: Serial TDM data output to the codec(s ).

This serial output is double-pumped for a bit r ate of 48 Mb/s for Intel High

Definition Audio.

Note: This signal is sampled as a functional s trap. See Section 2.26.1 for

more details. There is a weak integrated pull-down resistor on this

pin.

HDA_SDIN[3:0] I

Intel HD Audio Serial Data In [3:0]: Serial TDM data inputs from the

codecs. The se rial input is s ingle-pumped for a bit r ate of 24 Mb/s for Intel

High Definition Audio. These signals have integrated pull-down resistors,

which are always enabled.

Note: During enumer ation, the PCH will drive this signal. During normal

operation, the CODEC will drive it.

Table 2-16. Miscellaneous Signals (Sheet 2 of 2)

Name Type Description

Signal Description

68 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

2.18 Serial Peripheral Interface (SPI)

2.19 Thermal Signals

2.20 JTAG Signals

Note: JTAG Pin definitions are from IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE

Std. 1149.1-2001)

Table 2-18. Serial Peripheral Interface (SPI) Signals

Name Type Description

SPI_CS0# OSPI Chip Select 0: Used as the SPI bus request signal.

SPI_CS1# OSPI Chip Select 1: Used as the SPI bus request signal.

SPI_MISO ISPI Master IN Slave OUT: Data input pin for PCH.

SPI_MOSI I/O SPI Master OUT Slave IN: Data output pin for PCH.

SPI_CLK OSPI Clock: SPI clock signal, during idle the bus owner will drive the clock

signal low. 17.86 MHz and 31.25.

Table 2-19. Thermal Signals

Signal Name Type Description

PWM[3:0] OD O

Fan Pulse Width Modulation Outputs: Pulse Width Modulated duty cycle

output signal that is used for Intel® Quiet System Technology (Intel® QST).

When controlling a 3-wire fan, this signal controls a power transistor that, in

turn, controls power to the fan. When controlling a 4-wire fan, this signal is

connected to the “Control” signal on the fan. The polarity of this signal is

programmable. The output default is low.

These signals are 5 V tolerant.

TACH0 / GPIO17

TACH1 / GPIO1

TACH2 / GPIO6

TACH3 / GPIO7

TACH4 / GPIO68

TACH5 / GPIO69

TACH6 / GPIO70

TACH7 / GPIO71

IFan Tachometer Inputs: Tachometer pulse input signal that is used to

measure fan speed. This signal is connected to the “Sense” signal on the fan.

Can instead be used as a GPIO.

SST I/O Simple Serial Transport: Singl e-wire, serial bus. Connect to SST comp liant

devices such as SST thermal sensors or voltage sensors.

PECI I/O Platform Environment Control Interface: Single-wire, serial bus. Connect

to correspon ding pin of the processor for accessing processor di gita l

thermometer.

Table 2-20. JTAG Signals

Name Type Description

JTAG_TCK ITest Clock Input (TCK): The test clock input provides the clock for the JTAG test

logic.

JTAG_TMS I

Test Mode Select (TMS): The signal is decoded by the Test Access Port (TAP)

controller to control test operations.

JTAG_TDI I

Test Data Input (TDI): Serial test instructions and data are received by the test

logic at TDI.

JTAG_TDO OD Test Data Output (TDO): TDO is the serial output for test instructions and data

from the test logic defined in this standard.

Signal Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 69

Datasheet

2.21 Clock Signals

Table 2-21. Clock Interface Signals

Name Type Description

CLKIN_DMI_P,

CLKIN_DMI_N I100 MHz differential reference clock from CK420BQ (or CK505 on HEDT

platforms) and used by DMI.

CLKIN_SATA_P,

CLKIN_SATA_N I100 MHz differential reference clock from CK420BQ (or CK505 on HEDT

platforms), provided separately from CLKIN_DMI, for use only as a

100 MHz source for SATA.

CLKIN_DOT96P,

CLKIN_DOT96N I96 MHz differential reference clock from CK420BQ (or CK505 on HEDT

platforms).

REFCLK14IN ISingle-ended 14.31818 MHz reference clock driven by CK420BQ (or

CK505 on HEDT platforms). Used for 8254 Timer, ACPI Timer and HPET.

CLKIN_SAS0_P,

CLKIN_SAS0_N I

100 MHz differential reference clock from CK420BQ. Used for SAS

differential clock.

Note: For HEDT SKU, these signals must be tied to the 100 MHz

reference clock

CLKIN_SAS1_P,

CLKIN_SAS1_N

(Intel® C606, C608

Chipset SKUs Only)

I100 MHz differential reference clock from CK420BQ. Used for SAS

differential clock.

CLKIN_SPCIE0_P,

CLKIN_SPCIE0_N

(Intel® C606, C608

Chipset SKUs Only)

I Upstream PCIe* Switch Port differential reference clock.

CLKIN_PCI IPCI Clock: This is a 33 MHz clock feedback input to reduce skew

between PCH PCI clock and clock observed by connected PCI devices.

Signal Description

70 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

2.22 General Purpose I/O Signals

1. GPIO Configuration registers within the Core Well are reset whenever PCH_PWROK

is deasserted.

2. GPIO Configuration registers within the Suspend Well are reset when RSMRS T# is

asserted, CF9h reset (06h or 0Eh) event occurs, or SYS_RESET# is asserted.

However, CF9h reset and SYS_RESET# events can be masked from resetting the

Suspend well GPIO by programming appropriate GPIO Reset Select

(GPIO_RST_SEL) registers.

3. GPIO24 is an exception to the other GPIO Signals in the Suspend Well and is not

reset by CF9h reset (06h or 0Eh).

Table 2-22. General Purpose I/O Signals (Sheet 1 of 3)

Name Type Toler-

ance

Power

Well Default

Blink

Capa-

bility

Glitch

Protection

during

Power-On

Sequence

GPI

Event

Support

Description

GPIO75 I/O 3.3 V Suspend Native No No No Multiplexed with SML1DATA (Note 10)

GPIO74 I/O 3.3 V Suspend Native No No No Multiplexed with SML1ALERT#/

PCHHOT# (Note 10)

GPIO73 I/O 3.3 V Suspend GPI No No No Unmultiplexed

GPIO72 I/O 3.3 V Suspend Native No No No

Unmultiplexed (note 4)

This signal must no t be low prior to

ASW well being valid; Requires pull-up

resistor.

GPIO71 I/O 3.3 V Core Native No No No Multiplexed with Tach7

GPIO70 I/O 3.3 V Core Native No No No Multiplexed with Tach6

GPIO69 I/O 3.3 V Core GPI No No No Multiplexed with Tach5

GPIO68 I/O 3.3 V Core GPI No No No Multiplexed with Tach4

GPIO67 I/O 3.3 V Core GPO No No No Unmultiplexed

GPIO66 I/O 3.3 V Core GPO No No No Unmultiplexed

GPIO65 I/O 3.3 V Core GPO No No No Unmultiplexed

GPIO64 I/O 3.3 V Core GPO No No No Unmultiplexed

GPIO63 I/O 3.3 V Suspend Native No Yes No Multiplexed with SLP_S5#

GPIO62 I/O 3.3 V Suspend Native No No No Multiplexed with SUSCLK

GPIO61 I/O 3.3 V S uspend GPO No Yes No Unmultiplexed (note 4)

GPIO60 I/O 3.3 V Suspend Native No No No Multiplexed with SML0ALERT#

GPIO59 I/O 3.3 V Suspend Native No No No Multiplexed with OC0#

(Note 10)

GPIO58 I/O 3.3 V Suspend Native No No No Multiplexed with SML1CLK

GPIO57 I/O 3.3 V S uspend GPI No Yes No Unmultiplexed

GPIO56 I/O 3.3 V Suspend GPI No No No Unmultiplexed

GPIO55 I/O 3.3 V Core Native No No No Multiplexed with GNT3#

GPIO54 I/O 5.0 V Core Native No No No Multiplexed with REQ3#/

GSXRESET#.(Note 10)

GPIO53 I/O 3.3 V Core Native No No No Multiplexed with GNT2#/GSXDIN

GPIO52 I/O 5.0 V Core Native No No No Multiplexed with REQ2#/GSXSLOAD.

(Note 10)

GPIO51 I/O 3.3 V Core Native No No No Multiplexed with GNT1#/GSXDOUT

GPIO50 I/O 5.0 V Core Native No No No Multiplexed with REQ1#/GSXCLK.

(Note 10)

Signal Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 71

Datasheet

GPIO49 I/O 3.3 V Core GPI No No No Multiplexed with SATA5GP and

TEMP_ALERT#

GPIO48 I/O 3.3 V Core GPI No No No Multiplexed with SDATAOUT1.

GPIO47 I/O 3.3 V Suspend GPI No No No Unmultiplexed

GPIO46 I/O 3.3 V Suspend GPI No No No Unmultiplexed

GPIO45 I/O 3.3 V Suspend GPI No No No Unmultiplexed

GPIO44 I/O 3.3 V Suspend GPI No No No Unmultiplexed

GPIO[43:40] I/O 3.3 V Suspend Native No No No Multiplexed with OC[4:1]#. (Note 10)

GPIO39 I/O 3.3 V Core GPI No No No Multiplexed with SDATAOUT0.

GPIO38 I/O 3.3 V Core GPI No No No Multiplexed with SLOAD.

GPIO37 I/O 3.3 V Core GPI No No No Multiplexed with SATA3GP.

GPIO36 I/O 3.3 V Core GPI No No No Multiplexed with SATA2GP.

GPIO35 I/O 3.3 V Core GPO No No No Multiplexed with NMI#.

GPIO34 I/O 3.3 V Core GPI No No No Unmultiplexed (Note 4)

GPIO33 I/O 3.3 V Core GPO No No No Unmultiplexed (Note 4)

GPIO32 I/O 3.3 V Core GPO No No No Unmultiplexed (Note 4)

GPIO31 I/O 3.3 V DSW GPI Yes Yes No Unmultiplexed (Note 4)

GPIO30 I/O 3.3 V Suspend Native Yes Yes No Multiplexed with SUSWARN#.

Can be used as SUSWARN# and

GPIO30 only.

GPIO29 I/O 3.3 V Suspend Native Yes Yes No

Multiplexed with SLP_LAN#

Pin usage as GPIO is determined by

SLP_LAN#/GPIO Select Soft-

strap.(Note 9)

Soft-strap value is not preserved for

this signal in the Sx/Moff state and the

pin will return to its native functionalit y

(SLP_LAN#)

GPIO28 I/O 3.3 V Suspend GPO Yes No No Unmultiplexed

GPIO27 I/O 3.3 V DSW11 GPI Yes No No

Unmultiplexed

Can be configured as wake input to

allow wakes from Deep S4/S5. This

GPIO has no GPIO functionality in the

Deep S4/S5 states other than wake

from Deep S4/S5 if this option has

been configured.

GPIO26 I/O 3.3 V Suspend GPO Yes No No Unmultiplexed

GPIO25 I/O 3.3 V Suspend GPO Yes No No Unmultiplexed

GPIO24 I/O 3.3 V Suspend GPO Yes Yes No

Unmultiplexed

Note: GPIO24 configuration register

bits are cleared by RSMRST#

and are not c l ea red by CF9h

reset event.

GPIO23 I/O 3.3 V Core Native Yes No No Multiplexed with LDRQ1#.

GPIO22 I/O 3.3 V Core GPI Yes No No Multiplexed with SCLOCK

GPIO21 I/O 3.3 V Core GPI Yes No No Multiplexed with SATA0GP

GPIO20 I/O 3.3 V Core GPO Yes No No Multiplexed with SMI#

GPIO19 I/O 3.3 V Core GPI Yes No No Multiplexed with SATA1GP

Table 2-22. General Purpose I/O Signals (Sheet 2 of 3)

Name Type Toler-

ance

Power

Well Default

Blink

Capa-

bility

Glitch

Protection

during

Power-On

Sequence

GPI

Event

Support

Description

Signal Description

72 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Notes:

1. All GPIOs can be configured as either input or output.

2. GPI[15:0] can be configured to ca use a SMI# or SCI. A GPI can be routed to either an SMI# or an SCI,

but not both.

3. Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO signals are

not driven high into powered-down planes. Also, external devices should not be driving powered down

GPIOs high. Some GPIOs may be conn ected to pins on devices that exist in the core well. If these GPIOs

are outputs, there is a dan ger that a loss of core power (PCH_PWROK low) or a Power Button Override

event will result in the PCH driving a pin to a logic 1 to another device that is powered down.

4. The functionality that is multiplexed with the GPIO is not used in the PCH.

5. When this signal is configured as GPO the output stage is an open drain.

6. GPIO18 will toggle at a frequency of approximately 1 Hz when the signal is programmed as a GPIO

(when configured as an output) by BIOS.

7. For GPIOs where GPIO vs. Native Mode is configured using SPI Soft Strap, the corresponding

GPIO_USE_SEL bits for these GPIOs have no effect. The GPIO_USE_SEL bits for these GPIOs may

change to reflect the Soft-Strap configuration even though GPIO Lockdown Enable (GLE) bit is set.

8. These pins are used as Functional straps. See Section 2.26.1 for more details.

9. Once Soft-strap is set to GPIO mode, this pin will default to GP Input. When Soft-strap is SLP_LAN#

usage and if Host BIOS does not configure as GP Output for SLP_LAN# control, SLP_LAN# behavior will

be based on the setting of the RTC backed SLP_LAN# Default Bit(D31:F0:A4h:Bit 8).

10. When the multiplexed GPIO is used as GPIO functionality, care should be taken to ensure the signal is

stable in its inactive state of the native functionality, immediately after reset until it is initialized to GPIO

functionality.

11. GPIO functionality is only available when the Suspend well is powered although pin is in DSW.

12. GPIO will assume its native functionality until the soft strap is loade d after which time the functionality

will be determined by the soft strap setting.

13. GPIO13 is powered by VccSusHDA (either 3.3 V or 1.5 V). V oltage tole rance on the si gnal is the same as

VccSusHDA.

GPIO18 I/O 3.3 V Core GPO Yes

(Note

6) No No Unmultiplexed

GPIO17 I/O 3.3 V Core GPI Yes No No Multiplexed with TACH0.

GPIO16 I/O 3.3 V Core GPI Yes No No Multiplexed with SATA4GP.

GPIO15 I/O 3.3 V S uspend GPO Yes No Ye s2 Unmultiplexed

GPIO14 I/O 3.3 V Suspend Native Yes No Yes2 Multiplexed with OC7#

GPIO13 I/O 3.3 V

1.5 V Suspend GPI Yes No Yes2

Unmultiplexed (Note 4, 13)

Note: GPIO13 is powered by

VccSusHDA (either 3.3 V or

1.5 V). Voltage tolerance on

the signal is the same as

VccSusHDA.

GPIO12 I/O 3.3 V Suspend Native Yes No Ye s2

Multiplexed with LAN_PHY_PWR_CTRL.

GPIO / Native functionality controlled

using soft strap

(Note 7, 12)

GPIO11 I/O 3.3 V Suspend Native Yes No Yes2 Multiplexed with SMBALERT#. (Note

10)

GPIO10 I/O 3.3 V Suspend Native Yes No Yes2 Multiplexed with OC6# (Note 10)

GPIO9 I/O 3.3 V Suspend Native Yes No Yes2 Multiplexed with OC5# (Note 10)

GPIO8 I/O 3.3 V Suspend GPO Yes No Yes2 Unmultiplexed

GPIO[7:6] I/O 3.3 V Core GPI Yes No Yes2 Multiplexed with TACH[3:2].

GPIO[5:2] I/OD 5 V Core GPI Yes No Yes2 Multiplexed with PIRQ[H:E]# (Note 5).

GPIO1 I/O 3.3 V Core GPI Yes No Yes2 Multiplexed with TACH1.

GPIO0 I/O 3.3 V Core GPI Yes No Yes2 Multiplexed with BMBUSY#

Table 2-22. General Purpose I/O Signals (Sheet 3 of 3)

Name Type Toler-

ance

Power

Well Default

Blink

Capa-

bility

Glitch

Protection

during

Power-On

Sequence

GPI

Event

Support

Description

Signal Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 73

Datasheet

2.23 GPIO Serial Expander Signals

Note: GSX (GPIO Serial Expander) signal functions are enabled using softstrap.

2.24 Manageability Signals

The following signals can be optionally utilized by PCH Intel ME supported applications

and appropriately configured by Intel ME firmware. When configured and utilized as a

Manageability function, the associated host GPIO functionality is no longer available. If

the Manageability function is not utilized in a platform, the signal can be used as a host

General Purpose I/O or a native function.

Table 2-23. GPIO Serial Expander Interface

Name Type Description

GSXCLK OGPIO Serial Expansion clock input.

GSXCLK may optionally be used as REQ1# or GPIO50

GSXSLOAD O

GPIO Serial Expansion data load select.

GSXSLOAD may optionally be used as RE Q2# or GPIO52

GSXSRESET# O

GPIO Serial Expansion reset.

GSXSRESET# may optionally be used as REQ3# or GPIO54

GSXDOUT O

GPIO Serial Expansion serial data out.

GSXDOUT may optionally be used as GNT1# or GPIO51

GSXDIN I

GPIO Serial Expansion serial data in.

GSXDIN may optionally be used as GNT2# or GPIO53

Table 2-24. Manageability Signals (Sheet 1 of 2)

Name Type Description

MGPIO0/

PROC_MISSING/

GPIO24 I/O

MGPIO0 can be used to connect to upgrade ROM. It is also used to

indicate Processor Missing to the Intel® Management Engine (Intel®

ME).

Note: This signal is in the Suspend power well.

MGPIO1/GPIO30 I/O MGPIO1 can be used as an alternative for MGPIO2 or MGPIO5 when

neither pins are available for Intel ME.

Note: This signal is in the Suspend power well.

MGPIO2 / GPIO31 I/O MGPIO2 can be used as a SMBALERT# signal from PSU to PCH

Note: This signal is in the Suspend power well.

MGPIO3 / SLP_LA N#

/ GPIO29 I/O Intel ME General Purpose I/O 3.

Note: This signal is in the Suspend power well.

MGPIO4 /

SML0ALERT# / GPIO60 I/O MGPIO4 can be used as an alternative for MGPIO2 or MGPIO5 when

neither pins are available for Intel ME.

Note: This signal is in the Suspend power well.

MGPIO5 / GPIO57 I/O

MGPIO5 can be used as Intel ME firmware recovery mode strap.

MGPIO5 can be used as an alternative for MGPIO2 when it is not

available for Intel ME.

Note: This signal is in the Suspend power well.

MGPIO6 / GPIO27 I/O MGPIO6 can be used as an alternative for MGPIO2 or MGPIO5 when

neither pins are available for Intel ME.

Note: This signal is in the Deep S4/S5(DSW) power well.

MGPIO7 / GPIO28 I/O MGPIO7 can be used as an alternative for MGPIO2 or MGPIO5 when

neither pins are available for Intel ME.

Note: This signal is in the Suspend power well.

MGPIO8 /

SML1ALERT# / GPIO74 I/O MGPIO8 can be used as an alternative for MGPIO2 or MGPIO5 when

neither pins are available for Intel ME.

Note: This signal is in the Suspend power well.

Signal Description

74 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Note: SLP_LAN#/GPIO29 may also be configured by Intel ME FW in Sx/Moff. Please refer to SLP_LAN#/

GPIO29 signal description for details.

2.25 Power and Ground Signals

MGPIO9 / SA TA4GP /

GPIO16 I/O Intel ME General Purpose I/O 9.

Note: This signal is in the Core power well.

MGPIO10/

TEMP_ALERT/

SATA5GP / GPIO49 I/O

Used as an alert (active low) to indicate to the external controller (for

example, EC or SIO) that temperatures are out of range for the PCH or

Graphics/Memory Controller or the processor core.

Note: This signal is in the Core power well.

MGPIO11 / SML1CLK

/ GPIO58 I/O ME General Purpose I/O 11.

Note: This signal is in the Suspend power well.

MGPIO12 /

SML1DATA / GPIO75 I/O ME General Purpose I/O 12.

Note: This signal is in the Suspend power well.

Table 2-24. Manageability Signals (Sheet 2 of 2)

Name Type Description

Table 2-25. Power and Ground Signals (Sheet 1 of 2)

Name Description

DcpRTC Decoupling: This signal is for RTC decoupling only. This signal requires decoupling.

DcpSST Decoupling: Internally generated 1.5 V powered off of Suspend Well. This signal

requires decoupling. Decoupling is required even if this feature is not used.

DcpSus 1.1 V Suspend well supply that is supplied internally by Internal VRs.

DcpSusByp Internally generated 1.1 V Deep S4/S5 well power. This rail should not be supplied

externally.

Note: No decoupling capacitors should be used on this rail.

V5REF Reference for 5 V tolerance on core well inputs. This power may be sh ut off in S3, S4, S5

or G3 states.

V5REF_Sus Reference for 5 V tolerance on suspend well inputs. This power is not expected to be shut

off unless the system is unplugged.

VccCore

1.1 V supply for core well logic. This power may be shut off in S3, S4, S5 or G3 states.

Note: In external VR mode (INTVRMEN sampled low), the voltage level of VccCore may

be indeterminate while DcpSus (1.1 V Suspend Well Powe r) supply ramps and

prior to PWROK assertion.

VccIO 1.1 V supply for core well I/O buffers. This power may be shut off in S3, S4, S5 or G3

states.

Vcc3_3 3.3 V supply for core well I/O buffers. This power may be shut off in S3, S4, S5 or G3

states.

VccASW 1.1 V supply for Active Sle ep Well. This plane must be on in S0 and other times the Intel

ME is used or integrated LAN is used.

VccDMI

Power supply for DMI.

1.0 to 1.1 V based on the processo r VT T v oltage. Please refer to the respectiv e processo r

documentation to find the appropriate voltage level.

VccRTC

3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well. This power is not

expected to be shut off unless the RTC battery is removed or completely drained.

Note: Implementations should not attempt to clear CMOS by using a jumper to pull

VccRTC low. Clearing CMOS in a PCH based platform can be done by using a

jumper on RTCRST# or GPI.

VccSus3_3 3.3 V supply for suspend well I/O buffers. This power may be shut off in the Deep S4/S5

or G3 states.

VccAUBG 3.3 V supply for suspend well USB reference.

Note: This pin may require external filtering.

VccAUPLL 1.1 V supply for core well USB PLL.

Note: This pin may require external filtering.

Signal Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 75

Datasheet

VccSusHDA Suspend supply for Intel HD Audio. This pin can be either 1.5 or 3.3 V.

VccVRM 1.5 V / 1.8 V supply for internal PLL and VRMs

VccDFTERM 1.8 V or 3.3 V supply for DF_TVS. Can be pulled up to 1.8 V or 3.3 V core.

VccAPLLSATA

1.1 V Analog power supply for SATA. This signal is used for the analog power for SATA.

This requires an LC filter and is supplied by the core well. Must be powered even if SATA

is not used.

Note: This pin can be left as no connect in On-Die VR enabled mode (default).

VccAPLLEXP 1.1 V Analog Power for DMI. This power is supplied by the core well. This requires an LC

filter.

Note: This pin can be left as no connect in On-Die VR enabled mode (default).

VccAPLLDMI2 1.1 V Analog Power for internal PLL. This power is supplied by the core well. This requires

an LC filter.

Note: This pin can be left as no connect in On-Die VR enabled mode (default).

V_PROC_IO Powered by the same supply as the processor I/O voltage. This supply is used to drive

the processo r interface signals. Please refer to the respective processor documentation to

find the appropriate voltage level.

VccDSW3_3 3.3 V supply for Deep Sleep wells. If platform does not support Deep S4/S5, then tie to

VccSus3_3.

VccSPI 3.3 V supply for SPI controller logic. This must be powered when VccASW is powered.

Note: This rail can be optionally powered on 3.3-V Suspend power (VccSus3_3) based

on platform needs.

VccXUS

1.1 V supply for PCI Express Uplink switch wells. Can be tied to Vss for Intel® C602, C604

Chipset SKUs.

Note: This signal is not used on HEDT SKU and can be tied to VSS or VCC, but must be

tied to the same power plane as VccSCUS.

VccSCUS

1.1 V supply for SAS switch wells. Can be tied to Vss for Intel® C602, C602J, C604

Chipset SKUs.

Note: This signal is not used on HEDT SKU and can be tied to VSS or VCC, but must be

tied to the same power plane as VccXUS.

VccPLLSAS0 1.1 V supply for x4 SAS port. This requires an LC filter and is supplied by the core well.

Note: This signal must be connected on all SKUs.

VccPLLSAS1 1.1 V supply for x4 SAS port. This requires an LC filter and is supplied by the core well.

Note: This signal is not used on Intel® C602, C602J, C604 Chipset and Intel® X79

Express Chipset SKUs.

VccPLLEXPU

(Intel® C606,

C608 Chipset

SKUs Only)

1.1 V supply for PCI Express Uplink. This requires an LC filter and is supplied by the core

well.

Note: Must be tied to Vss if VccXUS is tied to Vss o n Intel® C602, C602J, C604 Chipset

and Intel® X79 Express Chipset SKUs.

VccRBIAS_SAS0 1.1 V supply for x4 SAS port RBIAS. This is supplied by the core well.

Note: This signal must be connected on all SKUs.

VccRBIAS_SAS1 1.1 V supply for x4 SAS port RBIAS. This is supplied by the core well.

Note: This signal is not used on Intel® C602, C602J, C604 Chipset and Intel® X79

Express Chipset SKUs.

VccRBIAS_PU

(Intel® C606,

C608 Chipset

SKUs Only)

1.1 V supply for PCI Express Uplink RBIAS. This is supplied by the core well.

Note: Must be tied to Vss if VccXUS is tied to Vss o n Intel® C602, C602J, C604 Chipset

and Intel® X79 Express Chipset SKUs.

VccSAS1_5 1.5 V supply for x4 SAS port. This is supplied by the core well.

Note: This signal must be connected on all SKUs.

Vss Grounds.

Table 2-25. Power and Ground Signals (Sheet 2 of 2)

Name Description

Signal Description

76 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

2.26 Pin Straps

2.26.1 Functional Straps

The following signals are used for static configuration. They are sampled at the rising

edge of PCH_PWROK to select configurations (except as noted), and then revert later to

their normal usage. To invok e the associated mode, the signal should be driven at least

four PCI clocks prior to the time it is sampled.

PCH has implemented Soft Straps. Soft Straps are used to configure specific functions

within the PCH and processor very early in the boot process before BIOS or SW

intervention. When Descriptor Mode is enabled, the PCH will read Soft Strap data out of

the SPI device prior to the de-assertion of reset to both the Intel ME and the Host

system.

Table 2-26. Functional Strap Definitions (Sheet 1 of 3)

Signal Usage When

Sampled Comment

SPKR No Reboot Rising edge of

PCH_PWROK

The signal has a weak internal pull-down.

Note: The internal pull-down is disabled after

PLTRST# de-asserts. If the signal is

sampled high, this indicates

that the system is strapped to the “No Reboot”

mode (PCH will disable the TCO Timer system

reboot feature). The status of this strap is

readable using the NO REBOOT bit (Chipset

Config Registers: Offset 3410h:bit 5).

INIT3_3V# Reserved Rising edge of

PCH_PWROK

This signal has a weak internal pull-up.

Note: The internal pull-up is disabled after

PLTRST# de-asserts.

Note: This signal should n ot be pulled low

GNT3#/GPIO55 Top-Block

Swap Override Rising edge of

PCH_PWROK

The signal has a weak internal pull-up. If the

signal is sampled low, this indicates that the

system i s strapped to the “Top-Block Swap”

mode.

The status of this strap is readable using the Top

Swap bit (Chipset Config Registers:Offset

3414h:bit 0).

Notes:

1. The internal pull-up is disabled after

PLTRST# deasserts.

2. Software will not be able to c lear the Top

Swap bit until the system is rebooted

without GNT3#/GPIO55 being pulled

down.

INTVRMEN Integrated 1.1 V

VRM Enable /

Disable Always Integrated 1.1 V VRMs is enabled when high

Note: This signal should always be pulled high.

Signal Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 77

Datasheet

GNT1#/GPIO51 Boot BIOS Strap bit

[1]

BBS[1]

Rising edge of

PCH_PWROK

This Signal has a weak internal pull-up.

Note: The internal pull-up is disabled after

PCIRST# de-asserts.

This field determines the destination of accesses

to the BIOS memory range. Also controllable

using Boot BIOS Destination bit (Chipset Config

Registers:Offset 3410h:bit 11). This s trap is u sed

in conjunction with Boot BIOS Destination

Selection 0 strap.

Note: If option 00 LPC is selected BIOS may

still be placed on LPC, but all platforms

with PCH require SPI flash connected

directly to the PCH's SPI bus with a valid

descriptor in order to boot.

Note: Booting to PCI is intended for debut/

testing only. Boot BIOS Destination

Select to LPC/PCI by functional strap or

using Boot BIOS Destination Bit will not

affect SPI accesses initiated by Intel ME

or Integrated GbE LAN.

SAT A1GP/

GPIO19

Boot BIOS Strap

bit[0]

BBS[0]

Rising edge of

PCH_PWROK

This Signal has a weak internal pull-up.

Note: The internal pull-up is disabled after

PCIRST# de-asserts. This field

determines the destination of accesses to

the BIOS memory range. Also

controllable using Boot BIOS Destination

bit (Chipset Config Registers:Offset

3410h:bit 10). This strap is used in

conjunction with Boot BIOS Destination

Selection 1 strap.

Note: If option 00 LPC is selected BIOS may

still be placed on LPC, but all platforms

with PCH require SPI flash connected

directly to the PCH's SPI bus with a valid

descriptor in order to boot.

Note: Booting to PCI is intended for debut/

testing only. Boot BIOS Destination

Select to LPC/PCI by functional strap or

using Boot BIOS Destination Bit will not

affect SPI accesses initiated by Intel ME

or Integrated GbE LAN.

GNT2#/ GPIO53 DMI AC Coupling Rising edge of

PCH_PWROK

This Signal has a weak internal pull-up.

Note: The internal pull-up is disabled after

PLTRST# de-asserts.

Tying this strap low enables DMI full voltage AC

coupling.

Table 2-26. Functional Strap Definitions (Sheet 2 of 3)

Signal Usage When

Sampled Comment

Bit11 Bit 10 Boot BIOS

Destination

01 Reserved

10 PCI

11 SPI

00 LPC

Bit11 Bit 10 Boot BIOS

Destination

01 Reserved

10 PCI

11 SPI

00 LPC

Signal Description

78 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

HDA_SDO

Flash Descriptor

Security Override/

Intel ME Debug

Mode

Rising edge of

PCH_PWROK

Signal has a weak internal pull-down.

If strap is sampled low, the security measures

defined in the Flash Descriptor will be in effect

(default). If sampled high, the Flash Descriptor

Security will be overridden.

This strap should only be asserted high using

external pull-up in manufacturing/debug

environments ONLY.

Note: The weak internal pull-down is disabled

after PLTRST# de-asserts.

Note: Asserting the HDA_SDO high on the

rising edge of PCH_PWROK will also halt

Intel ME after chipset bring up and

disable runtime Intel ME features. This is

a debug mode and must not be asserted

after manufacturing/debug.

DF_TVS DMI Tx /Rx

Termination

Voltage

Rising edge of

PCH_PWROK

This signal has a weak internal pull-down.

Note: The internal pull-down is disabled after

PLTRST# de-asserts.

GPIO28 On-Die PLL Voltage

Regulator Rising edge of

RSMRST# pin

This signal has a weak internal pull-up.

The On-Die PLL voltage regulator is enabled when

sampled high. When sampled low the On-Die PLL

Vo ltage Regulator is disabled.

Note: The internal pull-up is disabled after

RSMRST# deasserts.

HDA_SYNC On-Die PLL V oltage

Regulator Voltage

Select

Rising edge of

RSMRST# pin

This signal has a weak internal pull-down.

On Die PLL VR is supplied by 1.5 V from VccVRM

when sampled high, 1.8 V from VccVRM when

sampled low.

GPIO15 TLS Confidentiality Rising edge of

RSMRST# pin

Low = Intel ME Crypto Transport Layer Secu rity

(TLS) cipher suite with no confidentiality

High = Intel ME Crypto TLS cipher suite with

confidentiality

This signal has a weak internal pull down.

Notes:

1. A strong pull up may be needed for GPIO

functionality.

2. This signal mus t be pulled up to sup po rt

Intel RPAT and Intel AMT with TLS. Intel

ME configuration par ameters also need to

be set correctly to enable TLS.

DSWODVREN Deep S4/S5 Well

On-Die Voltage

Regulator Enable Always If strap is sampled high, the integrated Deep S4/

S5 Well (DSW) On-Die VR mode is enabled.

SATA2GP/GPIO36 Reserved Rising edge of

PWROK

This signal has a weak internal pull-down.

Note: The internal pull-down is disabled after

PLTRST# de-asserts.

Note: This signal should n ot be pulled high

when strap is sampled.

Table 2-26. Functional Strap Definitions (Sheet 3 of 3)

Signal Usage When

Sampled Comment

Signal Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 79

Datasheet

2.27 External RTC Circuitry

The PCH implements an internal oscillator circuit that is sensitive to step voltage

changes in VccRTC. Figure 2-2 shows an example schematic recommended to ensure

correct operation of the PCH RTC.

Notes:

1. The exact capacitor values for C1 and C2 must be based on the crystal maker recommendations.

2. Reference designators are arbitrarily assigned.

3. For platforms not supporting Deep S4/S5, the VccDSW3_3 pins will be connected to the VccSus3_3

pins.

4. Vbatt is voltage provided by the RTC battery (for example, coin cell).

5. VccRTC, RTCX1, RTCX2, RTCRST#, and SRTCRST# are PCH pins.

6. VccRTC powers PCH RTC well.

7. RTCX1 is the input to the internal oscillator.

8. RTCX2 is the amplified feedback for the external crystal.

Figure 2-2. Example External RTC Circuit

32.768 KH z

Xtal 10MΩ

VCCRTC

RTCX2

RTCX1

Vbatt

1uF

1 KΩ

VccDS W3_3

(see note 3 )

C1 C2

RTCRST#

1.0 uF

20 KΩ

0.1uF

SRTCRST#

20 KΩ

1.0 uF

Schottky Diodes

Signal Description

80 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

PCH Pin States

Intel® C600 Series Chipset and Intel® X79 Express Chipset 81

Datasheet

3 PCH Pin States

3.1 Integrated Pull-Ups and Pull-Downs

Notes:

1. Simulation data shows that these resistor values can range from 10 kΩ to 40 kΩ.

2. Simulation data shows that these resistor values can range from 9 kΩ to 50 kΩ.

3. Simulation data shows that these resistor values can range from 15 kΩ to 40 kΩ.

Table 3-1. Integrated Pull-Up and Pull-Down Resistors

Signal Resistor Nominal Notes

GPIO[67:64] Pull-down 20K 1, 10

GPIO15 Pull-down 20K 3

HDA_SDIN[3:0] Pull-down 20K 2

HDA_SYNC, HDA_SDO Pull-down 20K 2, 5

GNT[3:1]#/GPIO[55,53,51], Pull-up 20K 3, 6, 7

GPIO8 Pull-up 20K 3, 12

LAD[3:0]# Pull-up 20K 3

LDRQ0#, LDRQ1# / GPIO23 Pull-up 20K 3

DF_TVS Pull-down 20k 8

PME# Pull-up 20K 3

INIT3_3V# Pull-up 20K 3

PWRBTN# Pull-up 20K 3

SPI_MOSI Pull-down 20K 3, 5

SPI_MISO Pull-up 20K 3

SPKR Pull-down 20K 3, 9

TACH[7:0]/GPIO[71:68,7,6,1,17] Pull-up 20K 3 (only on TACH[7:0])

USB[13:0] [P,N] Pull-down 20K 4

GPIO72 Pull-up 20K 3

GPIO27 Pull-up 20K 3, 14

JTAG_TDI, JTAG_TMS Pull-up 20K 1, 11

JTAG_TCK Pull-down 20K 1, 11

GPIO28 Pull-up 20K 3, 12

SATA [3:2]GP/GPIO[37:36] Pull-down 20K 3, 9

GPIO31/MGPIO2 Pull-down 20K 3, 15

GPIO44 Pull-up 20K 1, 12

SST Pull-down 10K 16

GPIO46 Pull-up 20K 1, 12

SATA1GP/GPIO19 Pull-up 20K 3, 9

SUSACK# Pull-up 20K 3

PECI Pull-down 350 17

SASSMBCLK0, SASSMBDATA0 Pull-up 20K 3

SASSMBCLK1, SASSMBDATA1 Pull-up 20K 3

SASSMBCLK2, SASSMBDATA2 Pull-up 20K 3

PCH Pin States

82 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

4. Simulation data shows that these resistor values can range from 14.25 kΩ to 24.8 kΩ

5. The pull-up or pull-down on this signal is only enabled at boot/reset for strapping functio n.

6. The pull-up on this signal is not enabled when PCIRST# is high.

7. The pull-up on this signal is not enabled when PCH_PWROK is low.

8. Simulation data shows that these resistor values can range from 15 kΩ to 31 kΩ.

9. The Pull-up or pull down is not active when PLTRST# is NOT asserted.

10. The pull-down is enabled when PCH_PWROK is low.

11. External termination is also required on these signals for JTAG enabling.

12. Pull-up is disabled after RSMRST# is deasserted.

13. Not applicable for PCH.

14. Pull-up is enabled only in Deep-S4/5 state.

15. Pull-down is enabled only in Deep-S4/5 state.

16. When the interface is in BUS IDLE, the Internal Pull-down of 10K is enabled. In normal transmission, a

400 ohm pull down takes effect, the signal will be override to logic 1 with pull-up resistor (37 ohms) to

VCC 1.5 V.

17. This is a 350-Ω normal pull-down, signal will be overridden to logic 1 with pull-up resistor (31 Ω) to VCC

1.1 V.

3.2 Output and I/O Signals Planes and States

Table 3.2 shows the power plane associated with the output and I/O signals, as well as

the state at various times. Within the table, the following terms are used:

“High-Z” Tri-state. PCH not driving the signal high or low.

“High” PCH is driving the signal to a logic 1.

“Low” PCH is driving the signal to a logic 0.

“Defined” Driven to a level that is defined by the function or external pull-

up/pull-down resistor (will be high or low).

“Undefined” PCH is driving the signal, but the value is indeterminate.

“Running” Clock is toggling or signal is transitioning because function not

stopping.

“Off” The power plane is off; PCH is not driving when configured as an

output or sampling when configured as an input.

“Input” PCH is sampling and signal state determined by external driver.

Note: Signal levels are the same in S4 and S5, except as noted.

PCH suspend well signal states are indeterminate and undefined and may glitch prior to

RSMRST# deassertion. This does not apply to SLP_S3#, SLP_S4# and SLP_S5#. These

signals are determinate and defined prior to RSMRST# deassertion.

PCH core well signal states are indeterminate and undef ined and ma y glitch prior to

PCH_PWROK assertion. This does not apply to THRMTR IP# . This signal is dete rminate

and defined prior to PCH_PWROK assertion.

DSW indicates PCH Deep Sleep Well.This state provides a few wake events and critical

context context to allow system to draw minimal power in S4 or S5 states.

ASW indicates PCH Active Sleep W ell. This power well contains functionality associated

with active usage models while the host system is in Sx.

PCH Pin States

Intel® C600 Series Chipset and Intel® X79 Express Chipset 83

Datasheet

Table 3-2. Power Plane and States for Output and I/O Signals (Sheet 1 of 4)

Signal Name Power

Plane

During

Reset2Immediately

after Reset2S0/S1 S3 S4/S5

PCI Express

PET[8:1]p, PET[8:1]n Core Low Low4Defined OFF OFF

DMI

DMI_TXP[3:0], DMI_TXN[3:0] Core Low Low Defined Off Off

PCI Bus

AD[31:0] Core Low Low Low Off Off

C/BE[3:0]# Core Low Low Low Off Off

DEVSEL# Core High-Z High-Z High-Z Off Off

FRAME# Core High-Z High-Z High-Z Off Off

GNT0#7, GNT[3:1]#7/

GPIO[55, 53, 51] Core High High High Off Off

IRDY#, TRDY# Core High-Z High-Z High-Z Off Off

PAR Core Low Low Low Off Off

PCIRST# Suspend Low High High Low Low

PERR# Core High-Z High-Z High-Z Off Off

PLOCK# Core High-Z High-Z High-Z Off Off

STOP# Core High-Z High-Z High-Z Off Off

LPC/FWH Interface

LAD[3:0] Core High High High Off Off

LFRAME# Core High High High Off Off

INIT3_3V#7Core High High High Off Off

SATA Interface

SATA[5:0]TXP, SATA [5:0]TXN Core High-Z High-Z Defined Off Off

SATALED# Core High-Z High-Z Defined Off Off

SATAICOMPO Core High High Defined Off Off

SCLOCK/GPIO22 Core High-Z (Input) High-Z (Input) Defined Off Off

SLOAD/GPIO38 Core High-Z (Input) High-Z (Input) Defined Off Off

SDATAOUT[1:0]/GPIO[48,39] Core High-Z High-Z High-Z Off Off

SATA3RBIAS Core Terminated to

Vss Terminated to Vss Terminated

to Vss Off Off

SATA3ICOMPO Core High-Z High-Z High-Z Off Off

SATA3RCOMPO Core High-Z High-Z High-Z Off Off

Interrupts

PIRQ[A:D]#, Core High-Z High-Z High-Z Off Off

PIRQ[H:E]# /

GPIO[5:2] Core High-Z (Input) High-Z (Input) Defined Off Off

SERIRQ Core High-Z High-Z High-Z Off Off

USB Interface

USB[13:0][P,N] Suspend Low Low Defined Defined Defined

PCH Pin States

84 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

USBRBIAS Suspend High-Z High-Z High High High

Power Management

LAN_PHY_PWR_CTRL10/

GPIO12 Suspend Low Low Defined Defined Defined

PLTRST# Suspend Low High High Low Low

SLP_A#5Suspend Low High High Defined Defined

SLP_S3# Suspend Low High High Low Low

SLP_S4# Suspend Low High High High Defined

SLP_S5#/GPIO63 Suspend Low High High High Defined2

SLP_SUS# DSW Low High High High High

SUSCLK Suspend Low Running

DRAMPWROK Suspend Low High-Z High-Z High-Z Low

PM_SYNC Core Low Low Defined Off Off

PM_SYNC2 Core Low Low Defined Off Off

SLP_LAN#/GPIO298

SLP_LA N# (using soft-strap)

GPIO29 (using soft-strap) Suspend Low

High-z

Low8

High-z

High

High-z

Defined

High-z

Defined

High-z

Processor Interface

PROCPWRGD Processor Low High High Off Off

SMBus Interface

SMBCLK, SMBDATA Suspend High-Z High-Z Defined Defined Defined

SAS SMBus Interface

SASSMBCLK0, SASSMBDATA0 CORE H i gh-Z High-Z Defined Off Off

SAS SMBus Interface (Intel® C606, C608 Chipset SKUs Only)

SASSMBCLK1, SASSMBDATA1 CORE H i gh-Z High-Z Defined Off Off

SAS SMBus Interface (Intel® C608 Chipset SKU Only)

SASSMBCLK2, SASSMBDATA2 CORE H i gh-Z High-Z Defined Off Off

System Management Interface

SML0ALERT# / GPIO60 Suspend High-Z High-Z12 Defined Defined Defined

SML0DATA Suspend High-Z High-Z Defined Defined Defined

SML0CLK Suspend High-Z High-Z Defined Defined Defined

GPIO58/SML1CLK Suspend High-Z High-Z Defined Defined Defined

SML1ALERT#/PCH_HOT#/

GPIO74 Suspend High-Z High-Z Defined Defined Defined

SML1DATA/GPIO75 Suspend High-Z High-Z Defined Defined Defined

Miscellaneous Signals

SPKR7Core Low Low Defined Off Off

JTAG_TDO Suspend High-Z High-Z High-Z High-Z High-Z

Intel® HD Audio Interface

HDA_RST# Suspend Low Low3Defined Low Low

Table 3-2. Power Plane and States for Output and I/O Signals (Sheet 2 of 4)

Signal Name Power

Plane

During

Reset2Immediately

after Reset2S0/S1 S3 S4/S5

PCH Pin States

Intel® C600 Series Chipset and Intel® X79 Express Chipset 85

Datasheet

HDA_SDO7 Suspend Low Low Defined Low Low

HDA_SYNC7 Suspend Low Low Defined Low Low

HDA_BCLK13 Suspend Low Low Low Low Low

UnMultiplexed GPIO Signals

GPIO8 Suspend High High Defined Defined Defined

GPIO157Suspend Low Low Defined Defined Defined

GPIO24 Suspend Low Low Defined Defined Defined

GPIO27(Non-Deep S4/S5

mode) DSW High-Z High-Z High-Z High-Z High-Z

GPIO27(Deep S4/S5 mode) DSW High-Z High-Z High-Z High-Z High-Z

GPIO2812 Suspend High Low Low Low Low

GPIO32 Core High High Defined Off Off

GPIO57 Suspend High-Z (Input) High-Z (Input) Defined Defined Defined

GPIO729Suspend High High Defined Defined Defined

Multiplexed GPIO Signals used as GPIO only

GPIO0 Core High-Z (Input) High-Z (Input) Defined Off Off

GPIO139, 14 Suspend High-Z High-Z High-Z High-Z High-Z

GPIO20 Core High-Z (Input) High-Z (Input) Defined Off Off

GPIO309Suspend High-Z (Input) High-Z (Input) Defined Defined Defined

GPIO319 (Non Deep-S4/S5

mode) DSW High-Z (Input) High-Z (Input) Defined Defined Defined

GPIO319 (Deep-S4/S5 mode) DSW High-Z (Input) High-Z (Input) Defined Defined Defined

GPIO339Core High High High Off Off

GPIO34 Core High-Z (Input) High-Z (Input) Defined Off Off

GPIO35/NMI# Core Low Low Defined Off Off

GPIO[46:44] Suspend High-Z (Input) High-Z (Input) Defined Defined Defined

GPIO61 Suspend Low High High Low Low

SPI Interface

SPI_CS0# ASW High12 High Defined Defined Defined

SPI_CS1# ASW High12 High Defined Defined Defined

SPI_MOSI ASW Low12 Low Defined Defined Defined

SPI_CLK ASW Low12 Low Running Defined Defined

Thermal Reporting

PWM[3:0] Core Low Low Defined Off Off

SST Suspend Low Low Defined Off Off

PECI Processor Low Low Defined Off Off

SAS Interface (SRV/WS SKUs Only)

SAS[3:0]TXN, SAS[3:0]TXP CORE High-Z High-Z Defined Off Off

SAS_CLOCK1 COR E High-Z (Input) High-Z (Input) Defined Off Off

SAS_LOAD1 CORE High-Z (Input) High-Z (Input) Defined Off Off

SAS_DATAIN1 CORE High-Z (Inp ut) Hig h-Z (Input) Defined Off Off

Table 3-2. Power Plane and States for Output and I/O Signals (Sheet 3 of 4)

Signal Name Power

Plane

During

Reset2Immediately

after Reset2S0/S1 S3 S4/S5

PCH Pin States

86 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Notes:

1. The states of Core and processor sign als are ev aluated at the times During PLTRST# and Immediately after PLTRST#. The

states of the Suspend signals are evaluated at the times During RSMRST# and Immediately after RSMRST#, with an

exception to GPIO signals; refer to Section 2.23 for more details on GPIO state after reset. The states of the HDA signals

are evaluated at the times During HDA_RST# and Immediately after HDA_RST#

2. SLP_S5# sign als will be high in the S4 state and low in the S5 state.

3. Low until Intel H D Audio C ontroller R eset bit se t (D27:F0:Offset HDBAR+08h:bit 0), at which time HDA_RST# will be High

and HDA_BIT_CLK will be Running.

4. PETp/n[8:1] low until port is enabled by software.

5. The SLP_A# state will be determined by Intel ME Policies.

6. The state of signals in S3-5 will be defined by Intel ME Policies.

7. This signal is sampled as a functional strap during reset. Refer to Functional straps definition table for usage.

8. SLP_LAN# behavio r after reset is dependent on val ue of SLP_LAN# default v alue bit. A soft -strap is used to select between

SLP_LAN# and GPIO usage. When strap is set to 0 (default), pin is used as SLP_LAN#, when soft-strap is set to 1, pin is

used as GPIO29.

9. Native functionality multiplexed with these GPIOs are not utilized in PCH.

10. Native/GPIO functionality controlled using soft straps. Default to Native functionality until soft straps are loaded.

11. State of the pins depend on the source of VccASW power.

12. Pin is t ri-stated prior to APWROK assertion during Rese t.

13. When Controller Reset Bit of Global Control Register (D27:F0 Offset HDBAR 08h bit 0) gets set, this pin will start toggling.

14. GPIO13 is powered by VccSusHDA (either 3.3 V or 1.5 V). Voltage tolerance on the signal is the same as VccSusHDA.

SAS_DATAOUT1 CORE High-Z High-Z High-Z Off Off

SAS_RBIASN0, SAS_RBIASP0 Core Terminated to

Vss Terminated to Vss Terminated

to Vss Off Off

SAS Interface (Intel® C606, C608 Chipset SKUs Only)

SAS[7:4]TXN, SAS[7:4]TXP CORE High-Z Hig h-Z Defined Off Off

SAS_CLOCK2 CORE High-Z (Input) High-Z (Input) Defined Off Off

SAS_LOAD2 CORE High-Z (Input) High-Z (Input) Defined Off Off

SAS_DATAIN2 CORE High-Z (Input) High-Z (Input) Defined Off Off

SAS_DATAOUT2 CORE High-Z High-Z High-Z Off Off

SAS_RBIASN1, SAS_RBIASP1 Core Terminated to

Vss Terminated to Vss Terminated

to Vss Off Off

PCIe* Uplink (Intel® C606, C608 Chipset SKUs Only)

PEG0_TXN_[3:0],

PEG0_TXP_[3:0] CORE High-Z Defined Defined Off Off

PEG0_RBIASN, PEG_RBIASP Core Terminated to

Vss Terminated to Vss Terminated

to Vss Off Off

Table 3-2. Power Plane and States for Output and I/O Signals (Sheet 4 of 4)

Signal Name Power

Plane

During

Reset2Immediately

after Reset2S0/S1 S3 S4/S5

PCH Pin States

Intel® C600 Series Chipset and Intel® X79 Express Chipset 87

Datasheet

3.3 Power Planes for Input Signals

Table 3-3 shows the power plane associated with each input signal, as well as what

device drives the signal at various times. Valid states include:

High

Low

Static: Will be high or low, but will not change

Driven: Will be high or low, and is allowed to change

Running: For input clocks

PCH suspend well signal states are indeterminate and undefined and may glitch prior to

RSMRST# deassertion. This does not apply to SLP_S3#, SLP_S4# and SLP_S5#. These

signals are determinate and defined prior to RSMRST# deassertion.

PCH core well signal states are indeterminate and undefined and may glitch prior to

PCH_PWROK assertion. This does not apply to FERR# and THRMTRIP#. These signals

are determinate and defined prior to PCH_PWROK assertion.

Table 3-3. Power Plane for Input Signals (Sheet 1 of 3)

Signal Name Power Well Driver During Reset S0/S1 S3 S4/S5

DMI

DMI_RXP[3:0],

DMI_RXN[3:0] Core Processor Driven Off Off

PCI Express

PER[8:1]p,

PER[8:1]n Core PCI Express* Device Driven Off Off

PCI Bus

REQ0#,

REQ1# / GPIO50 1

REQ2# / GPIO521

REQ3# / GPIO541

Core External Pull-up Driven Off Off

PME# Suspend Internal Pull-up Driven Driven Driven

SERR# Core P CI Bus Peripherals Driven Off Off

LPC Interface

LDRQ0# Core LPC Devices Driven Off Off

LDRQ1# / GPIO231Core LPC Devices Driven Off Off

SATA Interface

SATA[5:0]RXP,

SATA[5:0]RXN Core SATA Drive Driven Off Off

SATAICOMPI Core High-Z Driven Off Off

SATA[5:4]GP/

GPIO[49,16]1Core External Device or External

Pull-up/Pull-down Driven Off Off

SATA0GP / GPIO[ 21]1Core External Device or External

Pull-up/Pull-down Driven Off Off

SATA1GP/GPIO19 Core Internal Pull-up Driven Off Off

SATA[3:2]GP/

GPIO[37:36] Core Internal Pull-down Driven Off Off

SATA3COMPI Core External Pull-up Driven Off Off

PCH Pin States

88 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

USB Interface

OC[7:0]#/

GPIO[14,10,9,43:40,5

9]1Suspend External Pull-ups Driven Driven Driven

USBRBIAS# Suspend External Pull-down Driven Driven Driven

Power Management

APWROK Suspend External Circuit High Driven Driven

PWRBTN# DSW Internal Pull-up Driven Driven Driven

PCH_PWROK RTC External Circuit Driven Driven Driven

DPWROK RTC External Circuit Driven Driven Driven

RI# Suspend Serial Port Buffer Driven Driven Driven

RSMRST# RTC External RC Circuit High High High

SYS_RESET# Core External Circuit Driven Off Off

SYS_PWROK Suspend External Circuit High Driven Driven

THRMTRIP# Core

(Processor) External Thermal Sensor Driven Off Off

WAKE# Suspend External Pull-up Driven Driven Driven

Processor Interface

A20GATE Core External Micro controller or

Pull-up Static Off Off

RCIN# Core External Micro controller High Off Off

System Management Interface

SMBALERT# / GPIO11 Su spend External Pull-up Driven Driven Driven

INTRUDER# RTC External Switch Driven Driven Driven

JTAG Interface

JTAG_TDI3Suspend Internal Pull-up High High High

JTAG_TMS3Suspend Internal Pull-up High High High

JTAG_TCK3Suspend Internal Pull down Low Low Low

Miscellaneous Signals

INTVRMEN2RTC External Pull-up Hig h High High

RTC RST# RTC External RC Circuit High High High

SRTCRST# RTC External RC Circuit High High High

Clock Interface

CLKIN_SATA_N,

CLKIN_SATA_P Core Clock Generator Running Off Off

CLKIN_DOT_96P,

CLKIN_DOT_96N Core Clock Generator Running Off Off

CLKIN_PCI Core Clock Generator Running Off Off

CLKIN_SAS0_N,

CLKIN_SAS0_P Core Clock Generator Running Off Off

REFCLK14IN Core Clock Generator Running Off Off

Table 3-3. Power Plane for Input Signals (Sheet 2 of 3)

Signal Name Power Well Driver During Reset S0/S1 S3 S4/S5

PCH Pin States

Intel® C600 Series Chipset and Intel® X79 Express Chipset 89

Datasheet

Notes:

1. These signals can be configured as outputs in GPIO mode.

2. This signal is sampled as a functional strap during Reset. Refer to Functional straps definition table for

usage.

3. External termination is also required for JTAG enabling.

Clock Interface (Intel® C606, C608 Chipset SKUs Only)

CLKIN_SPCIE0_N,

CLKIN_SPCIE0_P Core Clock Generator Running Off Off

CLKIN_SAS1_N,

CLKIN_SAS1_P Core Clock Generator Running Off Off

Intel® HD Audio Interface

HDA_SDIN[3:0] Suspend Internal Pull-down Driven Low Low

SPI Interface

SPI_MISO ASW Internal Pull-up Driven Driven Driven

Thermal Control

TACH[7:0]/

GPIO[71:68,7,6,1,17]1Core Internal Pull-up Driven Off Off

SAS Interface

SAS[3:0]RXP,

SAS[3:0]RXN Core Internal Pull-down Driven Off Off

SAS Interface (Intel® C606, C608 Chipset SKUs Only)

SAS[7:4]RXP,

SAS[7:4]RXN Core Internal Pull-down Driven Off Off

PCIe3 Uplink (Intel® C606, C608 Chipset SKUs Only)

PEG0_RXN_[3:0],

PEG0_RXP_[3:0] CORE High-Z Defined Defined Off

Table 3-3. Power Plane for Input Signals (Sheet 3 of 3)

Signal Name Power Well Driver During Reset S0/S1 S3 S4/S5

PCH Pin States

90 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

System Clock Domains

Intel® C600 Series Chipset and Intel® X79 Express Chipset 91

Datasheet

4System Clock Domains

The PCH uses clock source inputs provided by CK420BQ (SRV/WS SKUs Only) or CK505

(HEDT SKU Only), external clock chips. The inputs to PCH include:

• 100 MHz differential, PCI Express 2.0 spec compliant, SSC capable

• 100 MHz differential isolated for SATA, SSC capable

• 1 00 MHz differential isol ated for SAS, non SSC (SRV/WS SKU s Only)

• 100 MHz differential for PCIe Uplink ports, SSC capable

• 96 MHz differential, non SSC

• 14.318 MHz single-ended non SSC

4.1 System Clock Domains

Table 4-1 shows the system clock input to the PCH. Table 4-1 shows system clock

domains generated by the PCH.

Table 4-1. PCH Clock Inputs

Signal Frequency Usage

CLKIN_DMI_P,

CLKIN_DMI_N 100 MHz

100 MHz differential reference clock from CK420BQ (SRV/WS SKUs

Only) or CK505 (HEDT SKU Only).

Used for DMI an d PCIe 2.0 when cl ock isolation is disabled.

Used for DMI only when clock isolation is enabled

CLKIN_SATA_P,

CLKIN_SATA_N 100 MHz 100 MHz differential reference clock from CK420BQ (SRV/WS SKUs

Only) or CK505 (HEDT SKU Only).

Used for SATA.

CLKIN_DOT96_P,

CLKIN_DOT96_N 96 MHz 96 MHz differential reference clock from CK420BQ (SRV/WS SKUs

Only) or CK505 (HEDT SKU Only).

CLKIN_PCI 33.3 MHz 33.3 MHZ PCI reference clock

REFCLK14IN 14.31818

MHz

Single-ended 14.31818 MHz reference clock from CK420BQ (SRV/WS

SKUs Only) or CK505 (HEDT SKU Only). Used for 8254 Timer, ACPI

Timer a nd HPET.

RTCX1 32.768 KHz Reference input for RTC Oscillator

RTCX2 32.768 KHz See above

CLKIN_SAS0_P,

CLKIN_SAS0_N 100 MHz 100 MHz differential reference clock from CK420BQ (SRV/WS SKUs

Only).

Used as SAS clock for SCU0 (SAS Controller U nit) and SCU1.

CLKIN_SAS1_P,

CLKIN_SAS1_N 100 MHz

100 MHz differential reference clock from CK420BQ (SRV/WS SKUs

Only).

Used as supplemental clock source for SCU1 in Intel® C606, C608

Chipset SKUs.

CLKIN_SPCIE0_P,

CLKIN_SPCIE0_N 100 MHz 100 MHz differential reference clock from CK420BQ (SRV/WS SKUs

Only).

Used as upstream PCIe Uplink switch port clock reference

System Clock Domains

92 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Figure 4-1 and Figure 4-2 show the high level block diagram of PCH clocking.

Table 4-2. PCH Clock Outputs

Signal Frequency Usage

GP22_SCLOCK 32.768 KHz SCLOCK is SATA SGPIO Reference Clock.

Can also be used as GPIO22

SUSCLK_GP62 32.768 KHz SUSCLK is a suspend clock output from RTC generator circuit.

Can also be used as GPIO62

SPI_CLK 17.86 MHz/

20.83 MHz/

31.25 MHz SPI Flash clock output

Figure 4-1. PCH High-Level Clock Diagram (SRV/WS SKUs Only)

The image cannot be displayed. Your computer may not have enough mem ory to open the image,

or the image may have been corrupted. Restart your computer, and then open the file again. If the

red x still appears, you may have to delete the image and then insert it again.

The im age

ca nnot be

displayed. Your

computer may

not ha ve en ou gh

memory to open

the image, or

the image may

Processor

Patsburg

USB PLL

(USB 2.0/1.0)

USB PLL

(USB 2.0/1.0)

SATA

PLL

SATA

PLL

Legacy

14 M

Legacy

14 M

DMI

25 M

Xtal

SATA

100 M

SAS

100 M

DOT96

REF14

DMI

PCIe

100 M

RTC

32.768 M

RTC

32.768 M

SPI

SAS

PLL

SAS

PLL

PCIe Uplink

100 M

PCIe Gen3

PLL

PCIe Gen3

PLL

PCIe 2.0

CK420BQ

DB1900Z

Int

OSC

PCIe Gen2

PLL

PCIe Gen2

PLL

DMI

The image cannot be displayed. Your computer may not have enough mem ory to open the image,

or the image may have been corrupted. Restart your computer, and then open the file again. If the

red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough mem ory to open the image,

or the image may have been corrupted. Restart your computer, and then open the file again. If the

red x still appears, you may have to delete the image and then insert it again.

The im age

ca nnot be

displayed. Your

computer may

not ha ve en ou gh

memory to open

the image, or

the image may

The im age

ca nnot be

displayed. Your

computer may

not ha ve en ou gh

memory to open

the image, or

the image may

Processor

PCH

USB PLL

(USB 2.0/1.0)

USB PLL

(USB 2.0/1.0)

SATA

PLL

SATA

PLL

Legacy

14 M

Legacy

14 M

DMI

25 M

Xtal

25 M

Xtal

SATA

100 M

SAS

100 M

DOT96

REF14

DMI

PCIe Uplink

100 M

RTC

32.768 M

RTC

32.768 M

SPI

SAS

PLL

SAS

PLL

PCIe

100 M

PCIe Gen3

PLL

PCIe Uplink

PLL

PCIe 2.0

CK420BQ

DB1900Z

Int

OSC

PCIe Gen2

PLL

PCIe Gen2

PLL

DMI

System Clock Domains

Intel® C600 Series Chipset and Intel® X79 Express Chipset 93

Datasheet

4.2 Functional Blocks

Table 4-3 describes the PLLs on the PCH and the clock domains that are driv en from the

PLLs.

Figure 4-2. PCH High-Level Clock Diagram (HEDT SKU Only)

FLASH

PCH

CLKIN_DMI

CLKIN_DOT96

CLKIN_SATA

CLKIN_SAS

SPI_CLK

SRC8

SRC3

CK505

DOT96

SRC6

SRC7

SRC5 PCIex1 Slot –Off PBG

PCIex1 Slot – Off PBG

PCI Slot – Off PBG

PCI4

CLKIN_CPY

Gea r S hift

PLL

DB1200GS

1:1

PLL

CLKIN_PEG_Upstream

PCI_IN

PCI3

Slot SRC

PCI CLK

100MHz

Clock Sou rc e

Non SSC

SRC4

Table 4-3. PCH PLLs (Sheet 1 of 2)

PLL Outputs Frequency Description/Usage

DMI PLL 2.5 GHz/625 MHz/250 MHz

Source clock is 100 MHz from CK420BQ (SRV/WS SKUs

Only) or CK505 (HEDT SKU Only).

The PLL resource to generate the DMI port clocks when

clock isolation is enabled. Uses CLKIN_DMI input.

This PLL is shut down when clock isolation is disabled.

Resides in core power well and is not powered in S3 and

below states.

PCIe2 PLL 2.5 GHz/625 MHz/250 MHz

Source clock is 100 MHz from CK420BQ (SRV/WS SKUs

Only) or CK505 (HEDT SKU Only).

PCIe2 PLL drives clocks to PCIe 2.0 ports, Intel ME/VE

engines2 (in S0 state) and the NAND interface logic2 (in

S0 state). It is also used to supply DMI clocks when clock

isolation is disabled.

Can be configured to use CLKIN_DMI (when clock

isolation is disabled) or optional CLKIN_CPY input (when

clock isolation is enabled).

Resides in core power well and is not powered in S3 and

below states.

SATA PLL 3.0 GHz/1.5 GHz/

300 MHz/150 MHz

Source clock is 100 MHz from CK420BQ (SRV/WS SKUs

Only) or CK505 (HEDT SKU Only).

This PLL generates clocks for SATA Gen2 and SATA Gen3

ports.

Uses CLKIN_SATA input.

Resides in core power well and is not powered in S3 and

below states.

System Clock Domains

94 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

USB PLL 24 MHz/48 MHz/240 MHz/

480 MHz

Source clock is 96 MHz from CK420BQ (SRV/WS SKUs

Only) or CK505 (HEDT SKU Only). Uses CLKIN_DOT96

input.

Used for USB 2.0/1.0 logic.

Resides in core power well and is not powered in S3 and

below states.

PCIe Uplink PLL

(SRV/WS SKUs

Only) 4.0 GHz/500 MHz/250 MHz

Source clock is 100 MHz from CK420BQ (SRV/WS SKUs

Only) or CK505 (HEDT SKU Only).

There are two PCIe Uplink PLLs in PCH. They gen erate

clocks for PCIe Uplink ports.

Uses CLKIN_SPCIE0 input.

Resides in core power well and is not powered in S3 and

below states.

SAS PLL (SRV/WS

SKUs Only) 3.0 GHz/1.5 GHz

Source clock is 100 MHz from CK420BQ (SRV/WS SKUs

Only).

For Intel® C602, C602J, C604 Chipset SKUs, the SAS PLL

generates all the required SAS clocks. It uses

CLKIN_SAS0 input.

For Intel® C606, C608 Chipset SKUs, ther e are two SAS

PLLs and each SCU (SAS Controller Unit) has one SAS PLL

to provide SAS clocks for it. They use CLKIN_SAS[1:0] as

inputs, where CLKIN_SAS0 is used for the first SCU and

CLKIN_SAS1 for the s econd SCU.

Resides in core power well and is not powered in S3 and

below states.

Table 4-3. PCH PLLs (Sheet 2 of 2)

PLL Outputs Frequency Description/Usage

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 95

Datasheet

5 Functional Description

This chapter describes the functions and interfaces of the PCH.

5.1 PCI-to-PCI Bridge (D30:F0)

The PCI-to-PCI bridge resides in PCI Device 30, Function 0 on bus #0. This portion of

the PCH implements the buffering and control logic between PCI and Direct Media

Interface (DMI). The arbitration for the PCI bus is handled by this PCI device. The PCI

decoder in this device must decode the ranges for the DMI. All register contents are

lost when core well power is removed.

DMI is the chip-to-chip connection between the Processor and PCH. This high-speed

interface integrates advanced priority-based servicing allowing for concurrent traffic

and true isochronous transfer capabilities. Base functionality is completely software

transparent permitting current and legacy software to operate normally. New for PCH

the DMI interface operates at 5.0 GT/s.

To provide for true isochronous transfers and configurable Quality of Service (QoS)

transactions, the PCH supports two virtual channels on DMI — VC0 and VC1. These two

channels provide a fixed arbitration scheme where VC1 is always the highest priority.

VC0 is the default conduit of traffic for DMI and is always enabled. VC1 must be

specifically enabled and configured at both ends of the DMI link (that is, the PCH and

processor).

Configuration registers for DMI, virtual channel support, and DMI active state power

management (ASPM) are in the RCRB space in the Chipset Config Registers

(Chapter 10.1).

DMI is also capable of operating in the AC terminated mode for servers. A hardware

strap is used to configure DMI in AC terminated mode, see Section 2.26 for details.

5.1.1 PCI Bus Interface

The PCH PCI interface supports PCI Local Bus Specification, Revision 2.3, at 33 MHz.

The PCH integrates a PCI arbiter that supports up to four external PCI bus masters in

addition to the internal PCH requests.

See Section 5.2 for alternative methods for supporting PCI devices.

5.1.2 PCI Bridge As an Initiator

The bridge initiates cycles on the PCI bus when granted by the PCI arbiter. The bridge

generates the cycle types shown in Table 5-1.

Table 5-1. PCI Bridge Initiator Cycle Types

Command C/BE# Notes

I/O Read/Write 2h/3h Non-posted

Memory Read/Write 6h/7h Writes are posted

Configuration Read/Write Ah/Bh Non-posted

Special Cycles 1h Posted

Functional Description

96 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.1.2.1 Memory Reads and Writes

The bridge bursts memory writes on PCI that are received as a single packet from DMI.

5.1.2.2 I/O Reads and Writes

The bridge generates single DW I/O read and write cycles. When the cycle completes

on the PCI bus, the bridge generates a corresponding completion on DMI. If the cycle is

retried, the cycle is kept in the down bound queue and may be passed by a postable

cycle.

5.1.2.3 Configuration Reads and Writes

The bridge generates single DW configuration read and write cycles. When the cycle

completes on the PCI bus, the bridge generates a corresponding completion. If the

cycle is retried, the cycle is kept in the down bound queue and may be passed by a

postable cycle.

5.1.2.4 Locked Cycles

The bridge propagates locks from DMI per the PCI Local Bus Specification. The PCI

bridge implements bus lock, which means the arbiter will not grant to an y agent except

DMI while locked.

If a locked read results in a target or master abort, the lock is not established (as per

the PCI Local Bus Specification). Agents north of the PCH must not forward a

subsequent locked read to the bridge if they see the first one finish with a failed

completion.

5.1.2.5 Target / Master Aborts

When a cycle initiated by the bridge is master/target aborted, the bridge will not re-

attempt the same cycle. Fo r multiple DW cycles, the bridge increments the address and

attempts the next DW of the transaction. For all non-postable cycles, a target abort

response packet is returned for each DW that w as master or target aborted on PCI. The

bridge drops posted writes that abort.

5.1.2.6 Secondary Master Latency Timer

The bridge implem ents a Master Late ncy Ti me r usi ng the SMLT register which, upon

expiration, causes the deassertion of FRAME# at the next legal clock edge when there

is another active request to use the PCI bus.

5.1.2.7 Dual Address Cycle (DAC)

The bridge will issue full 64-bit dual address cycles for device memory-mapped

registers above 4 GB.

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 97

Datasheet

5.1.2.8 Memory and I/O Decode to PCI

The PCI bridge in the PCH is a subtractive decode agent, which follows the following

rules when forwarding a cycle from DMI to the PCI interface:

• The PCI bridge will positively decode any memory/IO address within its window

registers, assuming PCICMD.MSE (D30:F0:Offset 04h:bit 1) is set for memory

windows and PCICMD.IOSE (D30:F0:Offset 04h:bit 0) is set for I/O windows.

• The PCI bridge will subtractively decode any 64-bit memory address not claimed

by another agent, assuming PCICMD.MSE (D30:F0:Offset 04h:bit 1) is set.

• The PCI bridge will subtractively decode any 16-bit I/O address not claimed by

another agent assuming PCICMD.IOSE (D30:F0:Offset 04h:bit 0) is set.

• If BCTRL.IE (D 30:F0:Offset 3Eh:bit 2) is set, the PCI bridge will not positively

forward from primary to secondary called out ranges in the I/O window per PCI

Local Bus Specification (I/O transactions addressing the last 768 bytes in each,

1 KB block: offsets 100h to 3FFh). The PCI bridge will still take them subtractively

assuming the above rules.

• If BCTRL.VGA E (D30:F0:Offset 3Eh:bit 3) is set, the PCI bridge will positively

forward from primary to secondary I/O and memory ranges as called out in the PCI

Bridge Specification, assuming the above rules are met.

5.1.3 Parity Error Detection and Generation

PCI parity errors can be detected and reported. The following behavioral rules apply:

• When a parity error is detected on PCI, the bridge sets the SECSTS.DPE

(D30:F0:Offset 1Eh:Bit 15).

• If the bridge is a master and BCTRL.PERE (D30:F0:Offset 3Eh:Bit 0) is set and one

of the parity errors defined below is detected on PCI, then the bridge will set

SECSTS.DPD (D30:F0:Offset 1Eh:Bit 8) and will also generate an internal SERR#.

— During a write cycle, the PERR# signal is active, or

— A data parity error is detected while performing a read cycle

• If an address or command parity error is detected on PCI and PCICMD.SEE

(D30:F0:Offset 04h:bit 8), BCTRL.PERE, and BCTRL.SEE (D30:F0:Offset 3Eh:Bit 1)

are all set, the bridge will set PSTS.SSE (D30:F0:Offset 06h:Bit 14) and generate

an internal SERR#.

• If the PSTS.SSE is set because of an address parity error and the PCICMD.SEE is

set, the bridge will generate an internal SERR#.

• When bad parity is detected from DMI, bad parity will be driven on all data from the

bridge.

• When an address parity error is detected on PCI, the PCI bridge will never claim the

cycle. This is a slight deviation from the PCI bridge spec, which says that a cycle

should be claimed if BCTRL.PERE is not set. However, DMI does not have a concept

of address parity error, so claiming the cycle could result in the rest of the system

seeing a bad transaction as a good transaction.

Functional Description

98 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.1.4 PCIRST#

The PCIRST# pin is generated under two conditions:

•PLTRST# active

• BCTRL.SBR (D30:F0:Offset 3Eh:Bit 6) set to 1

The PCIRST# pin is in the suspend well. PCIRST# shou ld be tied to PCI bus agents, but

not other agents in the system.

5.1.5 Peer Cycles

The PCI bridge may be the initiator of peer cycles. Peer cycles include memory, I/O,

and configuration cycle types. Peer cycles are only allowed through VC0, and are

enabled with the following bits:

• BPC.PDE (D30 :F0:Offset 4Ch:Bit 2) – Memory and I/O cycles

• BPC.CDE (D30:F0:Offset 4Ch:Bit 1) – Configuration cycles

When enabled for peer for one of the above cycle types, the PCI bridge will perform a

peer decode to see if a peer agent can receive the cycle. When not enabled, memory

cycles (posted and/or non-posted) are sent to DMI, and I/O and/or configuration cycles

are not claimed.

Configuration cycles hav e special considerations. Under the PCI Local Bus Specification,

these cycles are not allowed to be forwarded upstream through a bridge. However, to

enable things such as manageability, BPC.CDE can be set. When set, type 1 cycles are

allowed into the part. The address format of the type 1 cycle is slightly different from a

standard PCI configuration cy cle to allow addressing of extended PCI space. The format

is shown as in Table 5-2:

Note: The PCH’s USB controllers cannot perform peer-to-peer traffic.

5.1.6 PCI-to-PCI Bridge Model

From a software perspective, the PCH contains a PCI-to-P CI bridge. This bridge

connects DMI to the PCI bus. By using the PCI-to-PCI bridge software model, the PCH

can have its decode ranges programmed by existing plug-and-play software such that

PCI ranges do not conflict with graphics aperture ranges in the Host controller.

Table 5-2. Type 1 Address Format

Bits Definition

31:27 Reserved (same as the PCI Local Bus Specification)

26:24 Extended Configur ation Ad dress – allows address ing of up to 4K. These

bits are combined with Bits 7:2 to get the full register.

23:16 Bus Number (same as the PCI Local Bus Specification)

15:11 Device Number (same as the PCI Local Bus Specification)

10:8 Function Number (same as the PCI Local Bus Specification)

7:2 Register (same as the PCI Local Bus Specification)

0 Must be 1 to indicate a type 1 cycle. Type 0 cycles are not decoded.

Functional Description

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Datasheet

5.1.7 IDSEL to Device Number Mapping

When addressing devices on the external PCI bus (with the PCI slots), the PCH asserts

one address signal as an IDSEL. When accessing Device 0, the PCH asserts AD16.

When accessing Device 1, the PCH asserts AD17. This mapping continues all the way

up to Device 15 where the PCH asse rts AD31 . Note that the PCH internal functions

(Intel High Definition Audio, USB, SATA and PCI Bridge) are enumerated like they are

off of a separate PCI bus (DMI) from the external PCI bus.

5.1.8 Standard PCI Bus Configuration Mechanism

The PCI Bus defines a slot based “configuration space” that allows each device to

contain up to eight functions with each function containing up to 256, 8-bit

configuration registers. The PCI Local Bus Specification, Revision 2.3 defines two bus

cycles to access the PCI configuration space: Configuration Read and Configuration

Write. Memory and I/O spaces are supported directly by the processor. Configuration

space is supported by a mapping mechanism implemented within the PCH. The PCI

Local Bus Specification, Revision 2.3 defines two mechanisms to access configuration

space, Mechanism 1 and Mechanism 2. The PCH only supports Mechanis m 1.

Warning: Configuration writes to internal devices, when the devices are disabled, are illegal and

may cause undefined results.

5.2 PCI Legacy Mode

PCH may optionally use PCIe-to-PCI bridges to enable external PCI I/O devices. To be

able to use PCIe-to-PCI brid ges and attached legacy PCI devices, the PCH provides PCI

Legacy Mode. PCI Legacy Mode allows both the PCI Express* root port and PCIe-to-PCI

bridge look like subtractive PCI-to-PCI bridges. This allows the PCI Express* root port

to subtractively decode and forward legacy cycles to the bridge, and the PCIe-to-PCI

bridge continues forwarding legacy cy cles to downstream PCI devices. F or designs that

would like to utilize PCI Legacy Mode, BIOS must program registers in the PCI-to-PCI

bridge (Device 30:Function 0) and in the desired PCI Express* Root Port (Device

28:Functions 0-7) to enable subtractive decode.

Note: Software must ensure that only one PCH device is enabled for Subtractive decode at a

time.

Functional Description

100 Intel® C600 Series Chipset and Intel® X79 Express Chipset

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5.3 PCI Express*

The PCH contains up to 8 PCI Express* root ports and one uplink port. All versions of

the PCH contain the 8 root ports. The Intel® C606, C608 Chipset SKUs contain a x4

uplink port while the Intel® C602, C602J, C604 Chipset and Intel® X79 Express Chipset

SKUs do not. The purpose of the uplink port is to provide a direct path for the SAS

controllers, SGPIO used by the SAS controllers, and SMBus ports to the processor/

memory without having to be multiplexed onto the DMI bus and sharing bandwidth

with the rest of the component. The uplink port is not connected to the downstream

root ports (Section 5.3.2).

In all configurations, the SMBus, SGPIO and SAS (SRV/WS SKUs Only) controllers are

part of a multifunction device. In the Intel® C602, C602J, C604 Chipset SKUs, the SCU,

SGPIO and SMBus controllers are connected to a virtual root port that is connected to

the PCH’s backbone. This is Device 31 off of Bus0. For the Intel® C606, C608 Chipset,

the SCU, SGPIo, and SMBus devices are connected through a virtual switch to the

uplink port.

5.3.1 PCI Express* UpLink Port (Bn:D0:F0) (SRV/WS SKUs

Only)

The PCI Express* Uplink here is an amalgram of two functions, an uplink port

connecting to a PCI Express* bus, and a virtual switch connecting the uplink port to the

MFD (Multi-Function Device) below. The MFD contains the SAS controllers, and SMBus

controllers. This uplink has the following capabilities:

• X4 link width at Gen1 speed

• MSI Interrupt Messaging

• ASPM support for L1 states

• No ISOC support

Because the PCI Express* uplink will be connected to Intel components, not 3rd party

devices, the expected/supported configuration is simply x4 as Gen1.

Note: The only valid configuration for the PCI Express* uplink is a x4 operating at Gen1

speeds. Any other configurations or speeds are out of spec and not supported.

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 101

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5.3.1.1 Programming Model and Addressing for the Intel® C602, C602J, C604

Chipset SKUs

5.3.1.1.1 Programming Model for Intel® C602, C602J, C604 Chipset SKUs

The functions of the integrated MFD are exposed to software through a Root Port

connected off the PCH internal fabric since there is no PCI Express* uplink in the Intel®

C602, C602J, C604 Chipset SKUs. There is no physical PCI Express* link between the

root port and the MFD so the link is “virtual”. Software will discover a virtual root port

with an attached multi-function end point device. Figure 5-1 shows how the virtual

Root Port and the Multi-Function Device as seen by software.

Table 5-3 displays the functions visible to software for the Intel® C602, C602J, C604

Chipset SKUs.

Figure 5-1. Programming Model for Intel® C602, C602J, C604 Chipset SKUs

PCI Express

Endpoint

Multi-

Function

Device

Virtual Root

Port

Virtual PCI to

PCI Bridge

Function #0

PC I B u s #0 P CH In te rn al F a b ric)

Device #0

Function #0

Device #17

PCI Bus #X (Internal Fabric )

Note:

The SAS Controller Unit supports SR-IOV.

Table 5-3. Configuration Spaces Visible to Software in Intel® C602, C602J, C604

Chipset SKUs

Function PCI Bus Number PCI Device Number

PCIe

Function

Number

Note: Virtual Root Port1

1. The current Bus/Device/Function of virtual root port is TBD.

0170

SAS Controller Unit 0 X2

2. X is a Bus number greater than Bus 0 assigned by Software.

Multi-function Glue unit X 0 1

SMBus Controller 0 Unit X 0 3

Functional Description

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5.3.1.1.2 Address Space for Intel® C602, C602J, C604 Chipset SKUs

Table 5-4 provides a summary of all the addressable spaces within Root Port and the

MFD as seen from PCI Bus 0. A detailed description of these spaces follows in later

sections.

5.3.1.2 Programming Model and Addressing for the Intel® C606, C608 Chipset

SKUs

The functions of the integrated MFD are exposed similarly to software through a

downstream switch port. Again there is no physical PCI Express* link so the link is

“virtual” between the downstream switch port and the MFD.

5.3.1.3 Programming Model for the Intel® C606, C608 Chipset SKUs

The Intel® C606, C608 Chipset SKUs contain a PCI Express* switch. The Intel® C606,

C608 Chipset SKUs contains a x4 uplink and a “virtual” switch port that serves as the

connection for the integrated MFD shown in Figure 5-2. Software will discov er a virtual

switch port with an attached multi-function end point device. The PCI Express* switch

is compliant to the PCI Express Base specification 2.0.

Table 5-4. Root Port and SCU Addressable Internal Spaces

Addressable Space

Virtual Root Port Config Space

SCU Config Space(s), SCU Memory Space, SCU I/O Space

SMBus 0 Config Space, SMBus 0 Memory Space, SMBus 0 I/O Space

SMbus 1 Config Space, SMBus 1 Memory Space, SMBus 1 I/O Space

Figure 5-2. Programming Model for the Intel® C606, C608 Chipset SKUs

V irtu a l P CI to

PC I Bridge

PCI Express

Upstream

Port

Bus #N

Function #0

PCI Bus #N

(P CIE L in k)

In te rn a l PC I Bu s # N+ 1

V irtu a l P CI to

PC I Bridge

Virtual

Switch Port

Device #8

Function #0

Device #0

SCU

0/1

PCI Bus #X

(Internal bus)

SMBus

0/1/2 NVSRAM

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 103

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Table 5-5 shows that configuration spaces visible to software fo r the Intel® C606, C608

Chipset SKUs.

5.3.1.4 Address Space for Intel® C606, C608 Chipset SKUs

Table 5-6 provides a summary of all addressable spaces within the Intel® C606, C608

Chipset SKUs.

5.3.1.5 Power Management

The uplink PCI Express* port will support Active State Power Management (ASPM). The

states supported are L0s and L1. ASPM is a hardware only fo rm of power management.

Software does not cause/force the link to go into L1. HW will enter these states based

upon the state of the devices downstream. If the MFD devices are all in D3 hot, then

the link can go into L3 depending on the capability programmed for both the Uplink and

to what the Uplink is connected.

5.3.1.6 Error Handling

The PCIe uplink supports the full AER (Advanced Error Reporting) error handling. It’s

use, however, is somewhat more controlled or restricted here. A lot of the error

handling is there to handle communication/interface errors between the root port and

an unknown device downstream. In this case, both ends of the PCI Express* link are

known (Intel® Xeon® processor E5-1600/E5-2600 product families and the PCH). The

endpoints for this link are the devices within PCH.

Table 5-5. Configuration Spaces Visible to Software in the Intel® C606, C608 Chipset

SKUs

Function PCI Bus Number PCI Device Number

PCIe

Function

Number

PCIe Upstream N 0 0

Virtual Switch Port N+1 8 0

SAS Controller Unit 0/1 X1

1. X is a value greater than N+1 assigned by the BIOS.

Multi-Function Glue X 0 1

SMBus Controller 0 X 0 3

SMBus Controller 1 X 0 4

SMBus Controller 2 (Inte l®

C608 Chipset SKU Only) X05

Table 5-6. Intel® C606, C608 Chipset SKUs Addressable Internal Spaces

Addressable Space

PCIe Upstream Port Config Space

PCIe Upstream Port Memory Space

Point-to-Point Fabric Config Space

Multi-Function Glue Config Space

SAS Controller Config Space

SAS Controller Memory Space

SAS Controller I/O Space

SMBus Controller 0-2 Config Space (only 2 for Intel® C606 Chipset SKU)

SMBus Controller 0-2 Memory Space (only 2 for Intel® C606 Chipset SKU)

SMBus Controller 0-2 IO Space (only 2 for Intel® C606 Chipset SKU)

Functional Description

104 Intel® C600 Series Chipset and Intel® X79 Express Chipset

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5.3.1.6.1 Poisoned TLP

If the upstream port receives a TLP with the EP bit set from the processor, it will set the

Detected Data Parity Error bit of the Primary Status register and the Poisoned TLP

Status bit of the Uncorrectable Error Status register. The Upstream port will send the

appropriate error message to the root. If the chip detects a data parity error from data

coming from the MFD, it will set the same bits for the downstream port and send the

same error messages.

5.3.1.6.2 Unsupported Request

When the upstream port receives a non-posted transaction (IO/Mem/Cfg) that did not

match the address/ID range programmed in the upstream port, the upstream port will

set the Unsupported Request Error Status of its Uncorrectable Error Status Register and

send an ERR_NONF AT AL message or ERR_COR message as an Advisory Non-Fatal error.

5.3.1.6.3 Completion Timeout

While the upstream port will not create completion timeouts (it only passes through

packets), the SCU at the end could generate a completion timeout if it doesn’t get an

response back from the CPU in the necessary time.

5.3.1.6.4 Completer Abort

If the downstream port receives an inbound (to the memory) non-posted request from

the MFD with an ACS violation, it will return a CA status to the MFD. In addition it will

log the ACS violation in it’s Uncorrectable Error Status Register and send an

ERR_NONFATAL or ERR_COR message as an Advisory Non-Fatal error to the root port.

5.3.1.6.5 Unexpected completion

The upstream port will generate this error if it receives a completion with a routing ID

that does not contain a bus number within the programmed valid r ange. The upstream

port will set the Unexpected Completion bit of it’s Uncorrectable Error Status Register

and send an ERR_COR messages as an Advisory Non-Fatal Error to the root port.

5.3.1.6.6 Receiver overflow

When a port detects a receiver overflow error, the port will set bit the Re ceiver Overflow

bit in the Uncorrectable Error Status Register and send an ERR_FATAL message to the

root complex.

5.3.1.6.7 Flow Control Protocol Error

When a port detects a flow control protocol error, the port will set the Flow Control

Protocol Error bit in the Uncorrectable Error Status Register and send an ERR_FATAL

message to the root complex.

5.3.1.6.8 Malformed Packet

When a port receives a malformed TLP, the port will set the Malformed TLP Status bit in

its Uncorrectable Error Status Register and send an ERR_FATAL message to the root

complex.

5.3.1.6.9 Error Message Forwarding

Error messages (ERR_COR, ERR_NONFATAL , ERR_FATAL) that are received from the

MFD are forwarded from the secondary to the primary side only if the SERR# Enable bit

in the Bridge Control Register is set. The error messages are forwarded by the primary

side when either the SERR# Enable bit is set in the Command Register or the

appropriate bit(s) are set in the Device Control Register. Note that the error messages

do not have any effect on the Advanced Error Reporting bits.

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 105

Datasheet

5.3.1.6.10 Poisoned Data Forwarding

When a transaction (request and completion) with bad data (poisoned TLP) enters an

ingress port, the transaction will be forwarded to an egress port as a poisoned TLP.

Similarly, a transaction whose data is corrupted while flowing through the switch fabric

will be poisoned by the egress port. The switch internal fabric supports parity on the

data bus.

5.3.1.6.11 PWROK Reset Mechanism

All the voltage sources in the system are tracked by a system component that asserts

the PWROK signal only after all the voltages have been stable for some predetermined

time. The switch receives the PWROK signal as an asynchronous input, meaning that

there is no assumed relationship between the assertion or the de-assertion of PWROK

and the reference clock. While the PWROK is de-asserted, the switch holds all logic in

reset.

The PWROK reset clears all internal state machines and logic, and initializes all

registers to their default states, including “sticky” error bits that are persistent through

all other reset classes. To eliminate potential system-reliability problems, all devices

are also required to either tri-state their outputs or to drive them to safe levels during

such a power-on reset.

Refer to the PCI Express Specification, Revision 2.0 for details of the relationship

between PWROK assertion and the stability of the clocks and power at the inputs of the

switch.

5.3.1.6.12 Fundamental Reset Mechanism

As soon as the system is up and running, a full system reset may be required to

recover from system-error conditions related to various device or subsystem failures.

Fundamental reset mechanism is a warm-reset mechanism that accomplishes this

recovery without clearing the “sticky” error-status bits which track the cause of the

error conditions of the device or subsystem. It is equivalent to receiving a PERST#

which results in a return to initial conditions.

5.3.1.6.13 PCI Express Reset Mechanism

There is no reset signal on the PCI Express, and all reset communication is in-band.

The upstream PCI Express device communicates the fact that it is entering and coming

out of a reset using messages. The switch responds by also going through a reset. In

accordance with the PCI Express protocol, this incoming message is asynchronous to

the reference cl ock. When the uPCIe bridg e is put in reset, it communicates that fact to

the dPCIe bridges. Each dPCIe then sends Hot Reset indication on its link and reset

their non-PRST and non-sticky registers. As long as the uPCIe is in reset, the dPCIe

links are kept in reset. For example, if the dPCIe link comes out of reset and sees that

the uPCIe bridge is in reset, it immediately sends a Hot Reset in-band indication and

resets itself.

5.3.1.6.14 Software PCI Reset (SBR—Secondary Bus Reset)

This reset is initiated by a write to the bridge control registers and resets only the

particular dPCIe segment or hierarchy south of the function receiving the SBR. This

reset can be used for various reasons includin g recovering from error conditions on the

secondary bus, to redo enumeration, and so forth. This reset is synchronous to the

clock domain in which it is used. The SBR is strictly restricted to the particular segment

and affects neither the other segments nor the rest of the switch logic. For the dPCIe

ports, SBR is strictly restricted to the particular segment and affects neither the other

segments nor the rest of the switch logic. For uPCIe, SBR affects all the downstream

PCI Express* segments and resets all the dPCIe register except for sticky bits.

Functional Description

106 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Note that the dPCIe segment resets on the SBR bit be ing set and comes out of reset

when the SBR bit is cleared.

5.3.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7)

There are eight root ports av ailable in the PCH. Th e root po rts are compliant to the PCI

Express 2.0 specification running at 5 GT/s. The ports all reside in Device 28, and take

Function 0 – 7. Port 1 is Function 0, Port 2 is Function 1, Port 3 is Function 2, Port 4 is

Function 3, Port 5 is Function 4, Port 6 is Function 5, Port 7 is function 6, and Port 8 is

Function 7.

PCI Express* Root Ports 1-4 or Ports 5-8 can independently be configured as four x1s,

two x2s, one x2 and two x1s, or one x4 port widths.The port configuration is set by soft

straps in the Flash Descriptor.

Note: This section assumes the default PCI Express* Function Number-to-Root Port mappin g

is used. Function numbers for a given root port are assignable through the “Root Port

Function Number and Hide for PCI Express* Root P orts” registers (RCBA+0404h).

5.3.2.1 Interrupt Generation

The root port generates interrupts on behalf of Hot-Plug and power management

events, when enabled. These interrupts can either be pin based , or can be MSIs, when

enabled.

When an interrupt is generated using the legacy pin, the pin is internally routed to the

PCH interrupt controllers. The pin that is driven is based upon the setting of the chipset

configuration registers. Specifically, the chipset configuration registers used are the

D28IP (Base address + 310Ch) and D28IR (Base address + 3146h) registers.

Table 5-7 summarizes interrupt behavior for MSI and wire-modes. In the table “bits”

refers to the Hot-Plug and PME inte rrupt bits.

Table 5-7. MSI versus PCI IRQ Actions

Interrupt Register Wire-Mode Action MSI Action

All bits 0 Wire inactive No action

One or more bits set to 1 Wire active Send message

One or more bits set to 1, new bit gets set to 1 Wire active Send message

One or more bits set to 1, software clears some (but not all) bits Wire active Send message

One or more bits set to 1, software clears all bits Wire inactive No action

Software clear s one or more b its, and one o r more bi ts are set on th e

same clock Wire active Send message

Functional Description

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Datasheet

5.3.2.2 Power Management

5.3.2.2.1 S3/S4/S5 Support

Software initiates the transition to S3/S4/S5 by performing an IO write to the Power

Management Control register in the PCH. After the IO write completion has been

returned to the processor, each root port will send a PME_Turn_Off TLP (Transaction

Layer Packet) message on its downstream link. The device attached to the link will

eventually respond with a PME_TO_Ack TLP message followed by sending a

PM_Enter_L23 DLLP (Data Link Layer Packet) request to enter the L2/L3 Ready state.

When all of the PCH root ports links are in the L2/L3 Ready state, the PCH power

management control logic will proceed with the entry into

S3/S4/S5.

Prior to entering S3, software is required to put each device into D3HOT. When a device

is put into D3HOT it will initiate entry into a L1 link state by sending a PM_Enter_L1

DLLP. Thus under normal operating conditions when the root ports sends the

PME_Turn_Off message the link will be in state L1. However, when the root port is

instructed to send the PME_Turn_Off message, it will send it whether or not the link

was in L1. Endpoints attached to the PCH can make no assumptions about the state of

the link prior to receiving a PME_Turn_Off message.

Note: The PME_Turn_Off TLP messaging flow is also issued during a host reset with and

without power cycle. Refer to Table 5-43 for a list of host reset resources.

5.3.2.2.2 Resuming from Suspended State

The root port contains enough circuitry in the suspend well to detect a wake event

through the WA KE# signal and to wake the system. When WAKE# is detected asserted,

an internal signal is sent to the power management controller of the PCH to cause the

system to wake up. This internal message is not logged in any register, nor is an

interrupt/GPE generated due to it.

5.3.2.2.3 Device Initiated PM_PME Message

When the system has returned to a working state from a previous low power state, a

device requesting service will send a PM_PME message continuously, until acknowledge

by the root port. The root port will take different actions depending upon whether this

is the first PM_PME has been received, or whether a previous message has been

received but not yet serviced by the operating system.

If this is the first message received (RSTS.PS - D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset

60h:Bit 16 is cleared), the root port will set RSTS.PS, and log the PME Requester ID

into RSTS.RID (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 60h:Bits 15:0). If an interrupt is

enabled using RCTL.PIE (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 5Ch:Bit 3), an interrupt

will be generated. This interrupt can be either a pin or an MSI if MSI is enabled using

MC.MSIE (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 82h:bit 0). See Section 5.3.2.2.4 for

Intel® Scalable Memory Interconnect (Intel® SMI)/SCI generation.

If this is a subsequent message received (RSTS.PS is already set), the root port will set

RSTS.PP (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 60h:Bit 17) and log the PME Requester

ID from the message in a hidden register. No other action will be taken.

When the first PME event is cleared by softw are clearing RSTS.PS , the root port will set

RSTS.PS, clear RSTS.PP, and move the requester ID from the hidden register into

RSTS.RID.

If RCTL.PIE is set, an interrupt will be gener ated. If RCTL.PIE is not set, a message will

be sent to the power management controller so that a GPE can be set. If messages

have been logged (RSTS.PS is set), and RCTL.PIE is later written from a 0 to a 1, and

Functional Description

108 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

interrupt will be generated. This last condition handles the case where the message

was received prior to the operating system re-enabling interrupts after resuming from

a low power state.

5.3.2.2.4 Intel® Scalable Memory Interconnect (Intel® SMI)/SCI Generation

Interrupts for power management events are not supported on legacy operating

systems. To support power management on non-PCI Express* aware operating

systems, PM events can be routed to generate SCI. To generate SCI, MPC.PMCE must

be set. When set, a power management event will cause SMSCS.PMCS (D28:F0/F1/F2/

F3/F4/F5/F6/F7:Offset DCh:Bit 31) to be set.

Additionally, BIOS workarounds for power management can be supported by setting

MPC.PMME (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset D8h:Bit 0). When this bit is set,

power management events will set SMSCS.PMMS (D28:F0/F1/F2/F3/F4/F5/F6/

F7:Offset DCh:Bit 0), and SMI# will be generated. This bit will be set regardless of

whether interrupts or SCI is enabled. The SMI# may occur concurrently with an

interrupt or SCI.

5.3.2.3 SERR# Generation

SERR# may be generated using two paths – through PCI mechanisms involving bits in

the PCI header, or through PCI Express* mechanisms involving bits in the PCI Express*

capability structure.

5.3.2.4 Hot-Plug

Each root port implements a Hot-Plug controller which performs the following:

• Messages to turn on/off/blink LEDs

• Presence and attention button detection

• Interrupt generation

The root port only allows Hot-Plug with modules (for example, ExpressCard*). Edge-

connector based Hot-Plug is not supported.

5.3.2.4.1 Presence Detection

When a module is plugged in and power is supplied, the physical layer will detect the

presence of the device, and the root port sets SLSTS.PDS (D28:F0/F1/F2/F3/F4/

F5:Offset 5Ah:Bit 6) and SLSTS.PDC (D28:F0/F1/F2/F3:Offset 6h:Bit 3). If SLCTL.PDE

(D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 58h:Bit 3) and SLCTL.HPE (D28:F0/F1/F2/F3/

F4/F5/F6/F7:Offset 58h:Bit 5) are both set, the root port will also generate an

interrupt.

Figure 5-3. Generation of SERR# to Platform

PSTS.SSE

SERR#

PCICMD.SEE

Secondary Parity Error

Primary Parity Error

Secondary SERR#

Correctable SERR#

Fatal SERR#

Non-Fatal SERR#

PCI

PCI Express

Functional Description

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When a module is removed (using the physical layer detection), the root port clears

SLSTS.PDS and sets SLSTS.PDC. If SLCTL.PDE and SLCTL.HPE are both set, the root

port will also generate an interrupt.

5.3.2.4.2 Message Generation

When system software writes to SLCTL.AIC (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset

58h:Bits 7:6) or SLCTL.PIC (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 58h:Bits 9:8), the

root port will send a message down the link to change the state of LEDs on the module.

Writes to these fields are non-postable cycles, and the resulting message is a postable

cycle. When receiving one of these writes, the root port performs the following:

• Changes the state in the register.

• Generates a completion into the upstream queue.

• Formulates a message for the downstream port if the field is written to regardless

of if the field changed.

• Generates the message on the downstream port.

• When the last message of a command is transmitted, sets SLSTS.CCE (D28:F0/F1/

F2/F3/F4/F5/F6/F7:Offset 58h:Bit 4) to indicate the command has completed. If

SLCTL.CCE and SLCTL.HPE (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 58h:Bit 5) are

set, the root port generates an interrupt.

The command completed register (SLSTS.CC) applies only to commands issued by

software to control the Atten tion Indicator (SLCTL.AIC), Power Indicator (SLCTL.PIC),

or Power Controller (SLCTL.PCC). However, writes to other parts of the Slot Control

Hence, any write to the Slot Control Register is considered a command and if enabled,

will result in a command complete interrupt. The only exception to this rule is a write to

disable the command complete interrupt which will not result in a command complete

interrupt.

A single write to the Slot Control register is considered to be a single command, and

hence receives a single command complete, even if the write affects more than one

field in the Slot Control Register.

5.3.2.4.3 Attention Button Detection

When an attached device is ejected, an attention button could be pressed by the user.

This attention button press will result in a the PCI Express* message

“Attention_Button_Pressed” from the device. Upon receiving this message, the root

port will set SLSTS.ABP (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 5Ah:Bit 0).

If SLCTL.ABE (D28:F0/F1/F2/F3/F4/F5:Offset 58h:bit 0) and SLCTL.HPE (D28:F0/F1/

F2/F3/F4/F5/F6/F7:Offset 58h:Bit 5) are set, the Hot-Plug controller will also generate

an interrupt. The interrupt is generated on an edge-event. F or example, if SLSTS.ABP is

already set, a new interrupt will not be generated.

Functional Description

110 Intel® C600 Series Chipset and Intel® X79 Express Chipset

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5.3.2.4.4 Intel® SMI/SCI Generation

Interrupts for Hot-Plug events are not supported on legacy operating systems. To

support Hot-Plug on non-PCI Express* aware operating systems, Hot-Plug events can

be routed to generate SCI. To generate SCI, MPC.HPCE (D28:F0/F1/F2/F3/F4/F5/F6/

F7:Offset D8h:Bit 30) must be set. When set, enabled Hot-Plug events will cause

SMSCS.HPCS (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset DCh:Bit 30) to be set.

Additionally, BIOS workarounds for Hot-Plug can be supported by setting MPC.HPME

(D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset D8h:Bit 1). When this bit is set, Hot -Plug events

can cause Intel SMI status bits in SMSCS to be set. Supported Hot -Plug events and

their corresponding SMSCS bit are:

• Command Completed - SCSCS.HPCCM (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset

DCh:Bit 3)

• Pre sence Detect Changed - SMSCS.HPPDM (D28:F0/F1/F2/F3/F4/F 5/F6/F7:Offset

DCh:Bit 1)

• Attention Button Pressed - SMSCS.HPABM (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset

DCh:Bit 2)

• Link Active State Changed - SMSCS.HPLAS (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset

DCh:Bit 4)

When any of these bits are set, SMI# will be generated. These bits are set regardless of

whether interrupts or SCI is enabled for Hot-Plug events. The SMI# may occur

concurrently with an interrupt or SCI.

5.4 Gigabit Ethernet Controller (B0:D25:F0)

The PCH integr ates a Gigabit Ethernet (GbE) controller. The integrated GbE controller is

compatible with the Intel® 82579 Platform LAN Connect device. The integrated GbE

controller provides two interfaces for 10/100/1000 Mb/s and manageability operation:

• Based on PCI Express* - A high-speed SerDes interface usi ng PCI Express*

electrical signaling at half speed while keeping the logical protocol for active state

operation mode.

• System Management Bus (SMBus) – A very low speed connection for low power

state mode for manageability communication only. At this low power state mode

the Ethernet link speed is reduced to 10 Mb/s.

The Intel 82579 can be connected to any available downstream PCI Express* port in

the PCH. The Intel 82579 Phy only runs at a speed of 1250 Mb/s, which is 1/2 of the

gen1 2.5 Gb/s PCI Expr ess* freque ncy. Each of the PCI Express* root ports in the PCH

chipset have the ability to run at the 1250 Mb/s rate. There is no need to implement a

mechanism to detect that the Intel 82579 LAN device is connected. The port

configuration (if any), attached to the Intel 82579 LAN device, is pre-loaded from the

SPI flash. The selected port adjusts the transmitter to run at the 1250 Mb/s rate and

does not need to be PCI Express* compliant.

Note: For more detailed information about Intel 82579 LAN Connect device, refer to Intel®

82579 Gigabit Ethernet PHY Datasheet.

Note: PCIe validation tools cannot be used for electrical validation of this interface; however,

PCIe layout rules apply for on-board routing.

The integrated GbE controller operates at full-duplex at all supported speeds or half-

duplex at 10/100 Mb/s. It also adheres to the IEEE 802.3x Flow Control Specification.

Note: GbE operation (1000 Mb/s) is only supported in S0 mode. In Sx modes, SMBus is the

only active bus and is used to support manageability/remote wake-up functionality.

Functional Description

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The integrated GbE controller provides a system interface using a PCI Express*

function. A full memory-mapped or I/O-mapped interface is provided to the software,

along with DMA mechanisms for high performance data transfer.

The integrated GbE controller features are:

•Network Features

— Compliant with the 1 Gb/s Ethernet 802.3 802.3u 802.3ab specifications

— Multi-speed operation: 10/100/1000 Mb/s

— Full-duplex operation at 10/100/1000 Mb/s: Half-duplex at 10/100 Mb/s

— Flow control support compliant with the 802.3X specification

— VLAN support compliant with the 802.3q specification

— MAC address filters: perfect match unicast filters; multicast hash filtering,

broadcast filter and promiscuous mode

— PCI Express/SMBus interface to GbE PHYs

• Host Interface Features

— 64-bit address master support for systems using more than 4 GB of physical

memory

— Programmable host memory receive buffers (256 Bytes to 16 KB)

— Intelligent interrupt generation features to enhance driver performance

— Descriptor ring management hardw are for transmit and receive

— Software controlled reset (resets everything except the configuration space)

— Message Signaled Interrupts

• Performance Features

— Configur able receive and transmit data FIFO, progr ammable in 1 KB increments

— TCP segmentation capability compatible with Windows NT* 5.x off loading

features

— Fragmented UDP checksum offload for packet reassembly

— IPv4 and IPv6 checksum offload support (receive, transmit, and TCP

segmentation offload)

— Split header support to eliminate payload copy from user space to host space

— Receive Side Scaling (RSS) with two hardware receive queues

— Supports 9018 bytes of jumbo packets

— Packet buffer size 32k bytes

— LinkSec offload compliant with 802.3ae specification

— TimeSync offload compliant with 802.1as specification

• Intel Virtualization Technology Features (SRV/WS SKUs Only)

— Warm function reset – function level reset (FLR)

—VMDq1

• Power Management Features

— Magic Packet wake-up enable with unique MAC address

— ACPI register set and power down functionality supporting D0 and D3 states

— Full wake up support (APM, ACPI)

— MAC power down at Sx, DMoff with an d with out WoL

Functional Description

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5.4.1 GbE PCI Express Bus Interface

The GbE controller has a PCI Express* interface to the host processor and host

memory. The following sections detail the bus transactions.

5.4.1.1 Transaction Layer

The upper layer of the host architecture is the transaction layer. The transaction layer

connects to the device core using an implementation specific protocol. Through this

core-to-transaction-layer protocol, the application-specific parts of the device interact

with the subsystem and transmit and receive requests to or from the remote agent,

respectively.

5.4.1.2 Data Alignment

5.4.1.2.1 4-KB Boundary

PCI requests must never specify an address/length combination that causes a memory

space access to cross a 4 KB boundary. It is hardware’ s responsibility to break requests

into 4 KB-aligned requests (if needed). This does not pose any requirement on

software. However, if software allocates a buffer across a 4-KB boundary, hardware

issues multiple requests for the buffer. Software should consider aligning buffers to 4

KB boundary in cases where it improves performance.

The alignment to the 4-KB boundaries is done in the core. The transaction layer does

not do any alignment according to these boundaries.

5.4.1.2.2 64 Bytes

PCI requests are multiples of 64 bytes and aligned to make better use of memory

controller resources. W rites, however, can be on any boundary and can cross a 64-byte

alignment boundary.

5.4.1.3 Configuration Request Retry Status

The integrated GbE controller might have a dela y in initialization due to an NVM read. If

the NVM configuration read operation is not completed and the device receives a

configuration request, the device responds with a configuration request retry

completion status to terminate the request, and thus effectively stalls the configuration

request until such time that the sub-system has completed local initialization and is

ready to communicate with the host.

Functional Description

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5.4.2 Error Events and Error Reporting

5.4.2.1 Data Parity Error

The PCI host bus does not provide parity protection, but it does forward parity errors

from bridges. The integrated GbE controller recognizes parity errors through the

internal bus interface and sets the Parity Error bit in PCI configuration space. If parity

errors are enabled in configuration space, a system error is indicated on the PCI host

bus. The offending cycle with a parity error is dropped and not processed by the

integrated GbE controller.

5.4.2.2 Completion with Unsuccessful Completion Status

A completion with unsuccessful completion status (any status other than 000) is

dropped and not processed by the integrated GbE controller. Furthermore, the request

that corresponds to the unsuccessful completion is not retried. When this unsuccessful

completion status is received, the System Error bit in the PCI configur ation space is set.

If the system errors are enabled in configuration space, a system error is indicated on

the PCI host bus.

5.4.3 Ethernet Interface

The integrated GbE controller provides a complete CSMA/CD function supporting IEEE

802.3 (10 Mb/s), 802.3u (100 Mb/s) implementations. It also supports the IEEE 802.3z

and 802.3ab (1000 Mb/s) implementations . The device performs all of the functions

required for transmission, reception, and collision handling called out in the standards.

The mode used to communicate between the PCH and the Intel 82579 PHY supports

10/100/1000 Mb/s operation, with both half- and full-duplex operation at 10/100 Mb/s,

and full-duplex operation at 1000 Mb/s.

5.4.3.1 Intel® 82579 LAN PHY Interface

The integrated GbE controller and the Intel 82579 PHY communicate through the PCIe

and SMBus interfaces. All integrated GbE controller configuration is performed using

device control registers mapped into system memory or I/O space. The Intel 82579

device is configured using the PCI Express* or SMBus interface.

The integrated GbE controller supports various modes as listed in Table 5-8.

5.4.4 PCI Power Management

The integrated GbE controller supports the Adv anced Configuration and Power Interface

(ACPI) specification as well as Advanced Power Management (APM). This enables the

network-related activity (using an internal host wake signal) to wake up the host. For

example, from Sx (S3-S5) to S0.

The integrated GbE controller contains power management registers for PCI and

supports D0 and D3 states. PCIe transactions are only allowed in the D0 state, except

for host accesses to the integrated GbE controller’s PCI configuration registers.

Table 5-8. LAN Mode Support

Mode System State Interface Active Connections

Normal 10/100/1000 Mb/s S0 PCI Express* or

SMBus1

1. GbE operation is not supported in Sx states.

Intel 82579

Manageability and Remote Wake-up S x SMBus Intel 82579

Functional Description

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5.4.4.1 Wake Up

The integrated GbE controller supports two types of wake-up mechanisms:

1. Advanced Power Management (APM) Wake Up

2. ACPI Power Management Wake Up

Both mechanisms use an internal logic signal to wake the system up. The wake-up

steps are as follows:

1. Host wake event occurs (note that packet is not delivered to host).

2. The Intel 82579 receives a WoL packet/link status change.

3. The Intel 82579 wakes up the integrated GbE controller using an SMBus message.

4. The integr ated GbE controller sets the PME_STATUS bit.

5. System wakes from Sx state to S0 state.

6. The host LAN function is transitioned to D0.

7. The host clears the PME_STATUS bit.

5.4.4.1.1 Advanced Power Management Wake Up

Advanced Power Management Wake Up or APM Wake Up was previously known as

W ake on LAN (W oL). It is a feature that has existed in the 10/100 Mb/s NICs for sever al

generations. The basic premise is to receive a broadcast or unicast packet with an

explicit data pattern and then to assert a signal to wake up the system. In earlier

generations, this was accomplished by using a special signal that ran across a cable to

a defined connector on the motherboard. The NIC would assert the signal for

approximately 50 ms to signal a wake up. The integrated GbE controller uses (if

configured to) an in-band PM_PME message for this.

At power up, the integr ated GbE controller reads the APM Enable bits from the NVM PCI

Init Control Word into the APM Enable (APME) bits of the Wake Up Control (WUC)

When APM wake up is enabled, the integrated GbE controller checks all incoming

packets for Magic Packets.

Once the integrated GbE controller receives a matching Magic Packet, it:

• Sets the Magic Packet Received bit in the Wake Up Status (WUS) register.

• Sets the PME_Status bit in the Power Management Control/Status Register

(PMCSR).

APM wake up is supported in all power states and only disabled if a subsequent NVM

read results in the APM Wake Up bit being cleared or the software explicitly writes a 0b

to the APM Wake Up (APM) bit of the WUC register.

Note: APM wake up settings will be restored to NVM default by the PCH when LAN connected

Device (PHY) power is turned off and subsequently rest ored . Som e ex amp l e host WOL

flows are:

• When system transitions to G3 after WOL is disabled from the BIOS, APM host WOL

would get enabled.

• Anytime power to the LAN Connected Device (PHY) is cycled while in S4/S5 after

WOL is disabled from the BIOS, APM host WOL would get enabled. Anytime power

to the LAN Connected Device (PHY) is cycled while in S3, APM host WOL

configuration is lost.

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 115

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5.4.4.1.2 ACPI Power Management Wake Up

The integrated GbE controller supports ACPI Power Management based Wake ups. It

can generate system wake-up events from three sources:

• Receiving a Magic Packet.

• Receiving a Network Wake Up Packet.

• Detecting a link change of state.

Activating ACPI Power Management Wakeup requires the following steps:

• The software device driver programs the Wake Up Filter Control (WUFC) register to

indicate the packets it needs to wake up from and supplies the necessary data to

the IPv4 Address Table (IP4AT) and the Flexible Filter Mask Table (FFMT), Flexible

Filter Length Table (FFLT), and the Flexible Filter Value Table (FFVT). It can also set

the Link Status Change Wake Up Enable (LNKC) bit in the Wake Up Filter Control

(WUFC) register to cause wake up when the link changes state.

• The operating system (at configuration time) writes a 1b to the PME_EN bit of the

Power Management Control/Status Register (PMCSR.8).

Normally, after enabling wake up, the operating system writes a 11b to the lower two

bits of the PMCSR to put the integrated GbE controller into low-power mode.

Once wake up is enabled, the integrated GbE controller monitors incoming packets,

first filtering them according to its standard address filtering method, then filtering

them with all of the enabled wake-up filters. If a packet passes both the standard

address filtering and at least one of the enabled wake-up filters, the integrated GbE

controller:

• Sets the PME_Status bit in the PMCSR

• Sets one or more of the Received bits in the Wake Up Status (WUS) register. (More

than one bit is set if a packet matches more than one filter.)

If enabled, a link state change wake up causes similar results, setting the Link Status

Changed (LNKC) bit in the Wake Up Status (WUS) register when the link goes up or

down.

After receiving a wake -up packet, the integrated GbE controller ignores any subsequent

wake-up packets until the software device driver clears all of the Received bits in the

Wake Up Status (WUS) register. It also ignores link change events until the software

device driver clears the Link Status Changed (LNKC) bit in the Wake Up Status (WUS)

Note: ACPI wake up settings are not preserv ed when the LAN Connected Device (PHY) power

is turned off and subsequently restored. Some example host WOL flows are:

• Anytime power to the LAN Connected Device (PHY) is cycled while in S3 or S4,

ACPI host WOL configuration is lost.

5.4.5 Configurable LEDs

The integrated GbE controller supports three controllable and configurable LEDs that

are driven from the Intel 82579 LAN device. Each of the three LED outputs can be

individually configured to select the particular event, state, or activity, which is

indicated on that output. In addition, each LED can be individually configured for output

polarity as well as for blinking versus non-blinking (steady-state) indication.

The configuration fo r LED outputs is specified using the LEDCTL register. Furthermore,

the hardware-default configuration for all the LED outputs, can be specified using NVM

fields, thereby supporting LED displays configurable to a particular OEM preference.

Functional Description

116 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Each of the three LEDs might be configured to use o ne of a variety of sources for output

indication. The MODE bits control the LED source:

• LINK_100/1000 is asserted when link is established at either 100 or 1000 Mb/s.

• LINK_10/1000 is asserted when link is established at either 10 or 1000 Mb/s.

• LINK_UP is asserted when any speed link is established and maintained.

• ACTIVITY is asserted when link is established and packets are being tr ansmitted or

received.

• LINK/ACTIVITY is asserted when link is established AND there is NO transmit or

receive activity.

• LINK_10 is asserted when a 10 Mb/p s link is established and maintained.

• LINK_100 is asserted when a 100 Mb/s link is established and maintained.

• LINK_1000 is asserted when a 1000 Mb/s link is established and maintained.

• FULL_DUPLEX is asserted when the link is configured for full duplex operation.

• COLLISION is asserted when a collision is observed.

• PAUSED is asserted when the device's transmitter is flow controlled.

• LED_ON is always asserted; LED_OFF is always deasserted.

The IVRT bits enable the LED source to be inverted before being output or observed by

the blink-control logic. LED outputs are assumed to normally be connected to the

negative side (cathode) of an external LED.

The BLINK bits control whether the LED should be blinked while the LED source is

asserted, and the blinking frequency (either 200 ms on and 200 ms off or 83 ms on and

83 ms off). The blink control can be especially useful for ensuring that certain events,

such as ACTIVITY indication, cause LED transitions, which are sufficiently visible to a

human eye. The same blinking rate is shared by all LEDs.

5.4.6 Function Level Reset Support (FLR) (SRV/WS SKUs Only)

The integrated GbE controller supports FLR capability. FLR capability can be used in

conjunction with Intel Virtualization Technology. FLR allows an operating system in a

Virtual Machine to have complete control over a device, including its initialization,

without interfering with the rest of the platform. The device provides a software

interface that enables the operating system to reset the entire device as if a PCI reset

was asserted.

5.4.6.1 FLR Steps

5.4.6.1.1 FLR Initialization

1. FLR is initiated by software by writing a 1b to the Initiate FLR bit.

2. All subsequent requests targeting the function is not claimed and will be master

abort immediate on the bus. This includes any configuration, I/O or memory cycles,

however, the function must continue to accept completions targeting the function.

5.4.6.1.2 FLR Operation

Function resets all configuration, I/O and memory registers of the function except

those indicated otherwise and resets all internal states of the function to the default or

initial condition.

5.4.6.1.3 FLR Completion

The Initiate FLR bit is reset (cleared) when the FLR reset completes. This bit can be

used to indicate to the software that the FLR reset completed.

Note: From the time the Initiate FLR bit is written to 1b, software must wait at least 100 ms

before accessing the function.

Functional Description

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5.5 LPC Bridge (with System and Management

Functions) (D31:F0)

The LPC bridge function of the PCH resides in PCI Device 31:Function 0. In addition to

the LPC bridge function, D31:F0 contains other functional units including DMA,

Interrupt controllers, Timers, Power Management, System Management, GPIO, and

RTC. In this chapter, registers and functions associated with other functional units

(power managemen t, GP IO, USB, and so forth) are described in their resp ec ti v e

sections.

Note: The LPC bridge cannot be configured as a subtractive decode agent.

5.5.1 LPC Interface

The PCH implements an LPC interface as described in the Low Pin Count Interface

Specification, Revision 1.1. The LPC interface to the PCH is shown in Figure 5-4. Note

that the PCH implements all of the signals that are shown as optional, but peripherals

are not required to do so.

Figure 5-4. LPC Interface Diagram

PCH

LPC Device

PCI Bus

PCI

CLK PCI

RST# PCI

SERIRQ PCI

PME#

LAD [3:0]

LFRAME#

LD RQ[1 :0 ]#

(Optional)

LSMI#

(Optional)

GPI

Functional Description

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Datasheet

5.5.1.1 LPC Cycle Types

The PCH implements all of the cycle types described in the Low Pin Count Interface

Specification, Revision 1.1. Table 5-9 shows the cycle types supported by the PCH.

Notes:

1. The PCH provides a sing le generic memory range (LGMR) for decoding memory cycles and forwarding

them as LPC Memory cycles on the LPC bus. The LGMR memory decode range is 64 KB in size and can

be defined as being anywhere in the 4 GB memory space. This range needs to be configured by BIOS

during POST to provide the necessary memory resources. BIOS should advertise the LPC Generic

Memory Range as Reserved to the OS in order to avoid resource conflict. For larger transfers, the PCH

performs multiple 8-bit transfers. If the cycle is not claimed by any peripheral, it is subsequently

aborted, and the PCH returns a value of all 1s to the processor. This is done to maintain compatibility

with ISA memory cycles where pull-up resistors would keep the bus high if no device responds.

2. Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer can be to any

address. However, the 2-byte transfer must be word-aligned (that is, with an address where A0=0). A

DWord transfer must be DWord-aligned (that is, with an address where A1 and A0 are both 0).

5.5.1.2 Start Field Definition

Note: All other encodings are RESERVED.

Table 5-9. LPC Cycle Types Supported

Cycle Type Comment

Memory Read 1 byte only. (See Note 1 below)

Memory Write 1 byte only. (See Note 1 below)

I/O Read 1 byte only. The PCH breaks up 16- and 32-bit processor cycles into multiple 8-bit

transfers.

I/O Write 1 byte only. The PCH breaks up 16- and 32-bit processor cycles into multiple 8-bit

transfers.

DMA Read Can be 1, or 2 bytes

DMA Write Can be 1, or 2 bytes

Bus Master Read Can be 1, 2, or 4 bytes. (See Note 2 below)

Bus Master Write Can be 1, 2, or 4 bytes. (See Note 2 below)

Table 5-10. Start Field Bit Definitions

Bits[3:0]

Encoding Definition

0000 Start of cycle for a generic target

0010 Grant for bus master 0

0011 Grant for bus master 1

1111 Stop/Abort: End of a cycle for a target.

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5.5.1.3 Cycle Type / Direction (CYCTYPE + DIR)

The PCH always drives Bit 0 of this field to 0. Peripherals running bus master cycles

must also drive Bit 0 to 0. Table 5-11 shows the valid bit encodings.

5.5.1.4 Size

Bits[3:2] are reserved. The PCH always drives them to 00. Peripherals running bus

master cycles are also supposed to drive 00 for Bits 3:2; however, the PCH ignores

those bits. Bits[1:0] are encoded as listed in Table 5-12.

5.5.1.5 SYNC

Valid values for the SYNC field are shown in Table 5-13.

Notes:

1. All other combinations are RESERVED.

2. If the LPC controller receives any SYNC returned from the device other than short (0101), long wait

(0110), or ready (0000) when running a FWH cycle, indeterminate results may occur. A FWH device is

not allowed to assert an Error SYNC.

Table 5-11. Cycle Type Bit Definitions

Bits[3:2] Bit1 Definition

00 0 I/O Read

00 1 I/O Write

01 0 Memory Read

01 1 Memory Read

10 0 DMA Read

10 1 DMA Write

11 x Reserved. If a peripheral performing a bus master cycle generates this value, the

PCH aborts the cycle.

Table 5-12. Transfer Size Bit Definition

Bits[1:0] Size

00 8-bit transfer (1 byte)

01 16-bit transfer (2 bytes)

10 Reserved. The PCH never drives this combination. If a peripher al running a bus master cy cle

drives this combination, the PCH may abort the transfer.

11 32-bit transfer (4 bytes)

Table 5-13. SYNC Bit Definition

Bits[3:0] Indication

0000 Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA request

deassertion and no more transfers desired for that channel.

0101 Short Wait: Part indicating wait-states. For bus master cycles, the PCH does not use this

encoding. Inst ead, the PCH uses the Long Wa it encoding (see next encoding below).

0110 Long Wait: Part indicating wait-states, and many wait-states will be added. This encoding

driven by the PCH for bus master cycles, rather than the Short Wait (0101 ).

1001 Ready More (Used only by peripheral for DMA cycle): SYNC achieved with no error and

more D MA transfer s desired to continue after this transfer. This value is valid only on DMA

transfers and is not allowed for any other type of cycle.

1010

Error: Sync achieved with error. This is generally used to replace the SERR# or IOCHK#

signal on the PCI/ISA bus. It indicates that the data is to be transferred, but there is a

serious error in this transfer. For DMA transfers, this not only indicates an error, but also

indicates DMA request deassertion and no more transfers desired for that channel.

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5.5.1.6 SYNC Time-Out

There are several error cases that can occur on the LPC interface. The PCH responds as

defined in section 4.2.1.9 of the Low Pin Count Interface Specification, Revision 1.1 to

the stimuli described therein. There may be other peripheral failure conditions;

however, these are not handled by the PCH.

5.5.1.7 SYNC Error Indication

The PCH responds as defined in section 4.2.1.10 of the Low Pin Count Interface

Specification, Revision 1.1.

Upon recognizing the SYNC field indicating an error, the PCH treats this as a SERR by

reporting this into the Device 31 Error Reporting Logic.

5.5.1.8 LFRAME# Usage

The PCH follows the usage of LFRAME# as defined in the Low Pin Count Interface

Specification, Revision 1.1.

The PCH performs an abort for the following cases (possible failure cases):

• The PCH starts a Memory, I/O, or DMA cycle, but no device drives a valid SYNC

after four consecutive clocks.

• The PCH starts a Memory, I/O, or DMA cycle, and the peripheral drives an invalid

SYNC pattern.

• A peripheral drives an illegal address when performing bus master cycles.

• A peripheral drives an invalid value.

5.5.1.9 I/O Cycles

For I/O cycles targeting registers specified in the PCH’s decode ranges, the PCH

performs I/O cycles as defined in the Low Pin Count Interface Specification, Revision

1.1. These are 8-bit transfers. If the processor attempts a 16-bit or 32-bit tr ansfer, the

PCH breaks the cycle up into multiple 8-bit transfe rs to consecutive I/O addresses.

Note: If the cycle is not claimed by any peripheral (and subsequently aborted), the PCH

returns a value of all 1s (FFh) to the processor. This is to maintain compatibility with

ISA I/O cycles where pull-up resistors would keep the bus high if no device responds.

5.5.1.10 Bus Master Cycles

The PCH supports Bus Master cycles and requests (using LDRQ#) as defined in the Low

Pin Count Interface Specification, Revision 1.1. The PCH has two LDRQ# inputs, and

thus supports two separate bus master devices. It uses the associated ST ART fields for

Bus Master 0 (0010b) or Bus Master 1 (0011b).

Note: The PCH does not support LPC Bus Masters performing I/O cycles. LPC Bus Masters

should only perform memory read or memory write cycles.

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5.5.1.11 Configuration and PCH Implications

LPC I/F Decoders

To allow the I/O cycles and memory mapped cycles to go to the LPC interface, the PCH

includes several decoders. During configur ation, the PCH must be programmed with the

same decode ranges as the peripher al. The decoders are programmed using the Device

31:Function 0 configuration space.

Note: The PCH cannot accept PCI write cycles from PCI -to-PCI bridges or devices with similar

characteristics (specifically those with a “Retry Read” feature which is enabled) to an

LPC device if there is an outstanding LPC read cycle towards the same PCI device or

bridge. These cycles are not part of normal system operation, but may be encountered

as part of platform validation testing using custom test fixtures.

Bus Master Device Mapping and START Fields

Bus Masters must have a un ique START field. In the case of the PCH that supports two

LPC bus masters, it drives 0010 for the START field for grants to Bus Master 0

(requested using LDRQ0#) and 0011 for grants to Bus Master 1 (requested using

LDRQ1#.). Thus, no registers are needed to configure the START fields for a particular

bus master.

5.6 DMA Operation (D31:F0)

The PCH supports LPC DMA using the PCH’s DMA controller. The DMA controller has

registers that are fixed in the lower 64 KB of I/O space. The DMA controller is

configured using registers in the PCI configuration space. These registers allow

configuration of the channels for use by LPC DMA.

The DMA circuitry incorporates the functionality of two 8237 DMA controllers with

seven independently programmable channels (Figure 5-5). DMA Controller 1 (DMA-1)

corresponds to DMA Channels 0–3 and DMA Controller 2 (DMA-2) corresponds to

Channels 5–7. DMA Channel 4 is used to cascade the two controllers and defaults to

cascade mode in the DMA Channel Mode (DCM ) Register. Channel 4 is not available for

any other purpose. In addition to accepting requests from DMA slaves, the DMA

controller also responds to requests that software initiates. Software may initiate a

DMA service request by setting any bit in the DMA Channel Request Register to a 1.

Each DMA channel is hardwired to the compatible settings for DMA device size:

Channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and Channels [7:5]

are hardwired to 16-bit, count-by-words (address shifted) transfers.

The PCH provides 24-bit addressing in compliance with the ISA-Compatible

specification. Each channel includes a 16-bit ISA-Compatibl e Current Register which

holds the 16 least-significant bits of the 24-bit address, an ISA-Compatible Page

The DMA controller also features refresh address generation, and auto-initialization

following a DMA termination.

Figure 5-5. PCH DMA Controller

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

DMA-1 DMA-2

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5.6.1 Channel Priority

For priority resolution, the DMA consists of two logical channel groups: Channels 0–3

and Channels 4–7. Each group may be in either fixed or rotate mode, as determined by

the DMA Command Register.

DMA I/O slaves normally assert their DREQ line to arbitrate for DMA service. However,

a software request for DMA service can be presented through each channel's DMA

Request Register. A software request is subject to the same prioritization as any

hardware request. See the detailed register description for Request Register

programming information in Section 13.2.

5.6.1.1 Fixed Priority

The initial fixed priority structure is as follows:

The fixed priority ordering is 0, 1, 2, 3, 5, 6, and 7. In this scheme, channel 0 has the

highest priority, and Channel 7 has the lowest priority. Channels [3:0] of DMA-1

assume the priority position of Channel 4 in DMA-2, thus taking priority over Channels

5, 6, and 7.

5.6.1.2 Rotating Priority

Rotation allows for “fairness” in priority resolution. The priority chain rotates so that the

last channel serviced is assigned the lowest priority in the channel group (0–3, 5–7).

Channels 0–3 rotate as a group of 4. They are always placed between Channel 5 and

Channel 7 in the priority list.

Channel 5–7 rotate as part of a group of 4. That is, Channels (5–7) form the first three

positions in the rotation, while Channel Group (0–3) comprises the fourth position in

the arbitration.

5.6.2 Address Compatibility Mode

When the DMA is operating, the addresses do not increment or decrement through the

High and Low P age Registers. Therefore, if a 24-bit address is 01FFFFh and increments,

the next address is 010000h, not 020000h. Similarly, if a 24-bit address is 020000h

and decrements, the next address is 02FFFFh, not 01FFFFh. However, when the DMA is

operating in 16-bit mode, the addresses still do not increment or decrement through

the High and Low Page Registers but the page boundary is now 128 K. Therefore, if a

24-bit address is 01FFFEh and increments, the next address is 000000h, not

0100000h. Similarly, if a 24-bit address is 020000h and decrements, the next address

is 03FFFEh, not 02FFFEh. This is compatible with the 8237 and Page Register

implementation used in the PC-AT. This mode is set after CPURST is valid.

5.6.3 Summary of DMA Transfer Sizes

Table 5-14 lists each of the DMA device transfer sizes. The column labeled “Current

Byte/Word Count Register” indicates that the register contents represents either the

number of bytes to transfer or the number of 16-bit words to transfer. The column

labeled “Current Address Increment/Decrement” indicates the number added to or

taken from the Current Address register after each DMA transfer cycle. The DMA

Channel Mode Register determines if the Current Address Register will be incremented

or decremented.

High priority Low priority

0, 1, 2, 3 5, 6, 7

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5.6.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words

The PCH maintains compatibility with the implementation of the DMA in the PC AT that

used the 8237. The DMA shifts the addresses for transfers to/from a 16-bit device

count-by-words.

Note: The least significant bit of the Low Page Register is dropped in 16-bit shifted mode.

When programming the Current Address Register (when the DMA channel is in this

mode), the Current Address must be programmed to an even address with the address

value shifted right by one bit.

The address shifting is shown in Table 5-15.

Note: The least significant bit of the Page Register is dropped in 16-bit shifted mode.

5.6.4 Autoinitialize

By programming a bit in the DMA Channel Mode Re gister, a channel may be set up as

an autoinitialize channel. When a channel undergoes autoinitialization, the original

values of the Current Page, Current Address and Current Byte/Word Count Registers

are automatically restored from the Base Page, Address, and Byte/Word Count

Registers of that channel following TC. The Base Registers are loaded simultaneously

with the Current Registers by the microprocessor when the DMA channel is

programmed and remain unchanged throughout the DMA service. The mask bit is not

set when the channel is in autoinitialize. Following autoinitialize, the channel is ready to

perform another DMA service, without processor intervention, as soon as a v alid DRE Q

is detected.

5.6.5 Software Commands

There are three additional special software commands that the DMA controller can

execute. The three software commands are:

• Clear Byte Pointer Flip-Flop

•Master Clear

• Clear Mask Register

They do not depend on any specific bit pattern on the data bus.

Table 5-14. DMA Transfer Size

DMA Device Date Size And Word Count Current Byte/Word

Count Register

Current Address

Increment/Decrement

8-Bit I/O, Count By Bytes Bytes 1

16-Bit I/O, Count By Words (Address Shifted) Words 1

Table 5-15. Address Shifting in 16-Bit I/O DMA Transfers

Output

Address

8-Bit I/O Programmed Address

(Ch 0–3)

16-Bit I/O Programmed

Address (Ch 5–7)

(Shifted)

A[16:1]

A[23:17]

A[16:1]

A[23:17]

A[15:0]

A[23:17]

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5.7 LPC DMA

DMA on LPC is handled through the use of the LDRQ# lines from peripherals and

special encodings on LAD[3:0] from the host. Single, Demand, Verify, and Increment

modes are supported on the LPC inter fac e. Channe l s 0–3 ar e 8- b i t chann els. Channe l s

5–7 are 16-bit channels. Channel 4 is reserved as a generic bus master request.

5.7.1 Asserting DMA Requests

Peripherals that need DMA service encode their requested channel number on the

LDRQ# signal. To simplify the protocol, each peripheral on the LPC I/F has its own

dedicated LDRQ# signal (they may not be shared between two separate peripherals).

The PCH has two LDRQ# inputs, allowing at least two devices to support DMA or bus

mastering.

LDRQ# is synchronous with LCLK (PCI clock). As shown in Figure 5-6, the peripheral

uses the following serial encoding sequence:

• Peripheral starts the sequence by asserting LDRQ# low (start bit). LDRQ# is high

during idle conditions.

• The next three bits contain the encoded DMA channel number (MSB first).

• The next bit (ACT) indicates whether the request for the indicated DMA channel is

active or inactive. The ACT bit is 1 (high) to indicate if it is active and 0 (low) if it is

inactive. The case where ACT is low is rare, and is only used to indicate that a

previous request for that channel is being abandoned.

• After the active/inactive indication, the LDRQ# signal must go high for at least 1

clock. After that one clock, LDRQ# signal can be brought low to the next encoding

sequence.

If another DMA channel also needs to request a transfer, another sequence can be sent

on LDRQ#. For example, if an encoded request is sent for Channel 2, and then Channel

3 needs a transfer before the cycle for Channel 2 is run on the interface, the peripheral

can send the encoded request for Channel 3. This allows multiple DMA agents behind

an I/O device to request use of the LPC interface, and the I/O device does not need to

self-arbitrate before sending the message.

5.7.2 Abandoning DMA Requests

DMA Requests can be deasserted in two fashions: on error conditions by sending an

LDRQ# message with the ‘ ACT’ bit set to 0, or normally through a SYNC field during the

DMA transfer. This section describes boundary conditions where the DMA request needs

to be removed prior to a data transfer.

There may be some special cases where the peripheral desires to abandon a DMA

transfer. The most likely case of this occurring is due to a floppy disk controller which

has overrun or underrun its FIFO, or software stopping a device prematurely.

Figure 5-6. DMA Request Assertion through LDRQ#

Start MSB LSB ACT Start

LCLK

LDRQ#

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In these cases, the peripheral wishes to stop further DMA activity. It may do so by

sending an LDRQ# message with the ACT bit as 0. However, since the DMA requ est was

seen by the PCH, there is no assurance that the cycle has not been granted and will

shortly run on LPC. Therefore, peripherals must take into account that a DMA cycle may

still occur. The peripheral can choose not to respond to this cycle, in which case the

host will abort it, or it can choose to complete the cycle normally with any r andom data.

This method of DMA deassertion should be prevented whenever possible, to limit

boundary conditions both on the PCH and the peripheral.

5.7.3 General Flow of DMA Transfers

Arbitration for DMA channels is performed through the 8237 within the host. Once the

host has won arbitration on behalf of a DMA channel assigned to LPC, it asserts

LFRAME# on the LPC I/F and begins the DMA transfer. The general flow for a basic DMA

transfer is as follows:

1. The PCH starts transfer by asserting 0000b on LAD[3:0] with LFRAME# asserted.

2. The PCH asserts ‘cycle type’ of DMA, direction based on DMA transfer direction.

3. The PCH asserts channel number and, if applicable, terminal count.

4. The PCH indicates the size of the transfer: 8 or 16 bits.

5. If a DMA read…

— The PCH drives the first 8 bits of data and turns the bus around.

— The peripheral acknowledges the data with a valid SYNC.

— If a 16-bit transfer, the process is repeated for the next 8 bits.

6. If a DMA write:

— The PCH turns the bus around and waits for data.

— The peripheral indicates data ready through SYNC and transfers the first byte.

— If a 16-bit transfer, the peripheral indicates data ready and transfers the next

byte.

7. The peripheral turns around the bus.

5.7.4 Terminal Count

Terminal count is communicated through LAD[3] on the same clock that DMA channel is

communicated on LAD[2:0]. This field is the CHANNEL field. Terminal count indicates

the last byte of transfer, based upon the size of the transfer.

F or example, on an 8-bit transfer size (SIZE field is 00b), if the TC bit is set, then this is

the last byte. On a 16-bit transfer (SIZE field is 01b), if the TC bit is set, then the

second byte is the last byte. The peripheral, therefore, must internalize the T C bit when

the CHANNEL field is communicated, and only signal TC when the last byte of that

transfer size has been transferred.

5.7.5 Verify Mode

Verify mode is supported on the LPC interface. A verify transfer to the peripheral is

similar to a DMA write, where the peripheral is transferring data to main memory. The

indication from the host is the same as a DMA write, so the peripheral will be driving

data onto the LPC interface. However, the host will not transfer this data into main

memory.

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5.7.6 DMA Request Deassertion

An end of transfer is communicated to the PCH through a special SYNC field

transmitted by the peripheral. An LPC device must not attempt to signal the end of a

transfer by deasserting LDREQ#. If a DMA transfer is several bytes (for example, a

transfer from a demand mode device) the PCH needs to know when to deassert the

DMA request based on the data currently being transferred.

The DMA agent uses a SYNC encoding on each byte of data being transferred, which

indicates to the PCH whether this is the last byte of transfer or if more bytes are

requested. To indicate the last byte of transfer, the periph eral uses a SYNC value of

0000b (ready with no error), or 1010b (ready with error). These encodings tell the PCH

that this is the last piece of data transferred on a DMA read (PCH to peripheral), or

the byte that follows is the last piece of data transferred on a DMA write (peripheral to

the PCH).

When the PCH sees one of these two encodings, it ends the DMA transfer after this byte

and deasserts the DMA request to the 8237. Therefore, if the PCH indicated a 16-bi t

transfer, the peripheral can end the transfer after one byte by indicating a SYNC value

of 0000b or 1010b. The PCH does not attempt to transfer the second byte, and

deasserts the DMA request internally.

If the peripheral indicates a 0000b or 1010b SYNC pattern on the last byte of the

indicated size, then the PCH only deasserts the DMA request to the 8237 since it does

not need to end the transfer.

If the peripheral wishes to keep the DMA request active, then it uses a SYNC value of

1001b (ready plus more data). This tells the 8237 that more data bytes are requested

after the current byte has been transferred, so the PCH keeps the DMA request active

to the 8237. Therefore, on an 8-bit transfer size, if the peripheral indicates a SYNC

value of 1001b to the PCH, the data will be transferred and the DMA request will remain

active to the 8237. At a later time, the PCH will then come back with another START–

CYCTYPE–CHANNEL–SIZE, and so forth, combination to initiate another transfer to the

peripheral.

The peripheral must not assume that the next START indication from the PCH is

another grant to the peripheral if it had indicated a SYNC value of 1001b. On a single

mode DMA device, the 8237 will re-arbitrate after every transfer. Only demand mode

DMA devices can be assured that they will receive the next START indication from the

PCH.

Note: Indicating a 0000b or 1010b encoding on the SYNC field of an odd byte of a 16-bit

channel (first byte of a 16-bit transfer) is an error condition.

Note: The host stops the transfer on the LPC bus as indicated, fills the upper byte with

random data on DMA writes (peripher al to memory), and indicates to the 8237 that the

DMA transfer occurred, incrementing the 8237’s address and decrementing its byte

count.

5.7.7 SYNC Field / LDRQ# Rules

Since DMA transfers on LPC are requested through an LDRQ# assertion message, and

are ended through a SYNC field during the DMA transfer, the peripheral must obey the

following rule when initiating back-to-back transfers from a DMA channel.

The peripheral must not assert another message for eight LCLKs after a deassertion is

indicated through the SYNC field. This is needed to allow the 8237, that typically runs

off a much slower internal clock, to see a message deasserted before it is re-asserted

so that it can arbitrate to the next agent.

Under default operation, the host only performs 8-bit transfers on 8-bit channels and

16-bit transfers on 16-bit channels.

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The method by which this communication between host and peripher al through system

BIOS is performed is beyond the scope of this specification. Since the LPC host and LPC

peripheral are motherboard devices, no “plug-n-play” registry is required.

The peripheral must not assume that the host is able to perform transfer sizes that are

larger than the size allowed for the DMA channel, and be willing to accept a SIZE field

that is smaller than what it may currently have buffered.

To that end, it is recommended that future devices that may appear on the LPC bus,

that require higher bandwidth than 8-bit or 16-bit DMA allow, do so with a bus

mastering interface and not rely on the 8237.

5.8 8254 Timers (D31:F0)

The PCH contains three counters that have fixed uses. All registers and functions

associated with the 8254 timers are in the core well. The 8254 unit is clocked by a

14.31818 MHz clock.

Counter 0, System Timer

This counter functions as the system timer by controlling the state of IRQ0 and is

typically programmed for Mode 3 operation. The counter produces a square wave with

a period equal to the product of the counter period (838 ns) and the initial count value.

The counter loads the initial count value 1 counter period after software writes the

count value to the counter I/O address. The counter initially asserts IRQ0 and

decrements the count value by two each counter period. The counter negates IRQ0

when the count value reaches 0. It then reloads the initial count value and again

decrements the initial count value by two each counter period. The counter then

asserts IRQ0 when the count value reaches 0, reloads the initial count value, and

repeats the cycle, alternately asserting and negating IRQ0.

Counter 1, Refresh Request Signal

This counter provides the refresh request signal and is typically programmed for Mode

2 operation and only impacts the period of the REF_TOGGLE bit in Port 61. The initial

count value is loaded one counter period after being written to the counter I/O address.

The REF_TOGGLE bit will have a square wa ve behavior (alternate between 0 and 1) and

will toggle at a rate based on the value in the counter. Programming the counter to

anything other than Mode 2 will result in undefined behavior for the REF_TOGGLE bit.

Counter 2, Speaker Tone

This counter provides the speaker tone and is typically programmed for Mode 3

operation. The counter provides a speaker frequency equal to the counter clock

frequency (1.193 MHz) divided by the initial count value. The speaker must be enabled

by a write to port 061h (see NMI Status and Control ports).

5.8.1 Timer Programming

The counter/timers are programmed in the following fashion:

1. Write a control word to select a counter.

2. Write an initial count for that counter.

3. Load the least and/or most significant bytes (as required by Control W ord Bits 5, 4)

of the 16-bit counter.

4. Repeat with other counters.

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Only two conventions need to be observed when programming the counters. First, for

each counter, the control word must be written before the initial count is written.

Second, the initial count must follow the count format specified in the control word

(least significant byte only, most significant byte only, or least significant byte and then

most significant byte).

A new initial count may be written to a counter at any time without affecting the

counter's programmed mode. Counting is af fected as described in the mode definitions.

The new count must follow the programmed count format.

If a counter is programmed to read/write two-byte counts, the following precaution

applies: A program must not transfer control between writing the first and second byte

to another routine which also writes into that same counter. Otherwise, the counter will

be loaded with an incorrect count.

The Control Word Register at port 43h controls the operation of all three counters.

Several commands are available:

•Control Word Command. Specifies which counter to read or write, the operating

mode, and the count format (binary or BCD).

•Counter Latch Command. Latches the current count so that it can be read by the

system. The countdown process continues.

•Read Back Command. Reads the count value, programmed mode, the current

state of the OUT pins, and the state of the Null Count Flag of the selected counter.

Table 5-16 lists the six operating modes for the interval counters.

5.8.2 Reading from the Interval Timer

It is often desirable to read the value of a counter without disturbing the count in

progress. There are three methods for reading the counters: a simple read operation,

counter Latch command, and the Read-Back command. Each is explained below.

With the simple read and counter latch command methods, the count must be read

according to the programmed format; specifically, if the counter is programmed for two

byte counts, two bytes must be read. The two bytes do not have to be read one right

after the other. Read, write, or programming operations for other counters may be

inserted between them.

Table 5-16. Counter Operating Modes

Mode Function Description

0 Out signal on end of count (=0) Output is 0. When count goes to 0, output goes to 1 and

stays at 1 until counter is reprogrammed.

1 Hardware retriggerable one-shot Output is 0. When count goes to 0, output goes to 1 for

one clock time.

2 Rate generator (divide by n counter) Output is 1. Output goes to 0 for one clock time, then

back to 1 and counter is reloaded.

3 Square wave output Output is 1. Output goes to 0 when counter rolls over , and

counter is reloaded. Output goes to 1 when counter rolls

over, and counter is reloaded, and so forth.

4 Software triggered strobe Output is 1. Output goes to 0 when count expires for one

clock t ime.

5 Hardware triggered strobe Output is 1. Output goes to 0 when count expires for one

clock t ime.

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5.8.2.1 Simple Read

The first method is to perform a simple read operation. The counter is selected through

port 40h (Counter 0), 41h (Counter 1), or 42h (Counter 2).

Note: Performing a direct read from the counter does not return a determinate value,

because the counting process is asynchronous to read oper ations. However, in the case

of Counter 2, the count can be stopped by writing to the GATE bit in Port 61h.

5.8.2.2 Counter Latch Command

The Counter Latch command, written to Port 43h, latches the count of a specific

counter at the time the command is received. This command is used to ensure that the

count read from the counter is accurate, particularly when reading a two-byte count.

The count value is then read from each counter’ s Count register as was programmed by

the Control register.

The count is held in the latch until it is read or the counter is reprogrammed. The count

is then unlatched. This allows reading the contents of the counters on the fly without

affecting counting in progress. Multiple Counter Latch Commands may be used to latch

more than one counter. Counter Latch commands do not affect the programmed mode

of the counter in any way.

If a Counter is latched and then, some time later, latched again before the count is

read, the second Counter Latch command is ignored. The count read is the count at the

time the first Counter Latch command was issued.

5.8.2.3 Read Back Command

The Read Back command, written to Port 43h, latches the count value, programmed

mode, and current states of the OUT pin and Null Count flag of the selected counter or

counters. The value of the counter and its status may then be read by I/O access to the

counter address.

The Read Back command may be used to latch multiple counter outputs at one time.

This single command is functionally equiv alent to sever al counter latch commands, o ne

for each counter latched. Each counter's latched count is held until it is read or

reprogrammed. Once read, a counter is unlatched. The other counters remain latched

until they are read. If multiple count Read Back commands are issued to the same

counter without reading the count, all but the first are ignored.

The Read Back command may additionally be used to latch status information of

selected counters. The status of a counter is accessed by a read from that counter's

I/O port address. If multiple counter status latch operations are performed without

reading the status, all but the first are ignored.

Both count and status of the selected counters may be latched simultaneously. This is

functionally the same as issuing two consecutive, separate Read Back commands. If

multiple count and/or status Read Back commands are issued to the same counters

without any intervening reads, all but the first are ignored.

If both count and status of a counter are latched, the first read operation from that

counter returns the latched status, regardless of which was latched first. The next one

or two reads, depending on wheth er the co unter is programmed for one or two type

counts, returns the latched count. Subsequent reads return unlatched count.

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5.9 8259 Interrupt Controllers (PIC) (D31:F0)

The PCH incorporates the functionality of two 8259 interrupt controllers that provide

system interrupts for the ISA compatible interrupts. These interrupts are: system

timer, keyboard controller, serial ports, parallel ports, floppy disk,mouse, and DMA

channels. In addition, this interrupt controller can support the PCI based interrupts, by

mapping the PCI interrupt onto the compatible ISA interrupt line. Each 8259 core

supports eight interrupts, numbered 0–7. Table 5-17 shows how the cores are

connected.

The PCH cascades the slave controller onto the master controller through master

controller interrupt input 2. This means there are only 15 possible interrupts for the

PCH’s PIC.

Interrupts can individually be programmed to be edge or level, except for IRQ0, IRQ2,

IRQ8, and IRQ13.

Note: Active-low interrupt sources (for example, the PIRQ#s) are inverted inside the PCH. In

the following descriptions of the 8259s, the interrupt levels are in reference to the

signals at the internal interface of the 8259s, after the required inversions have

occurred. Therefore, the term “high” indicates “active,” which means “low” on an

originating PIRQ#.

Table 5-17. Interrupt Controller Core Connections

8259 8259

Input

Typical Interrupt

Source Connected Pin / Function

Master

0 Internal Internal Timer / Counter 0 output / HPET #0

1 Keyboard IRQ1 using SERIRQ

2 Internal Slave controller INTR output

3 Serial Port A IRQ3 using SERIRQ, PIRQ#

4 Serial Port B IRQ4 using SERIRQ, PIRQ#

5 Parallel Port / Generic IRQ5 using SERIRQ, PIRQ#

6 Floppy Disk IRQ6 using SERIRQ, PIRQ#

7 Parallel Port / Generic IRQ7 using SERIRQ, PIRQ#

Slave

0 Internal Real Time Clock Internal RTC / HPET #1

1 Generic IRQ9 using SERIRQ, SCI, TCO, or PIRQ#

2 Generic IRQ10 using SERIRQ, SCI, TCO, or PIRQ#

3 Generic IRQ11 using SERIRQ, SCI, TCO, or PIRQ#, or HPET #2

4 PS/2 Mouse IRQ12 using SERIRQ, SCI, TCO, or PIRQ#, or HPET #3

5 Internal State Machine output based on processor FERR#

assertion. May optionally b e used for SCI or TCO interrupt

if FERR# not needed.

6 SATA SATA Primary (legacy mode), or using SERIRQ or PIRQ#

7 SATA SAT A Secondary (legacy mode) or using SERIRQ or PIRQ#

Functional Description

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5.9.1 Interrupt Handling

5.9.1.1 Generating Interrupts

The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each

interrupt level. These bits are used to determine the interrupt vector returned, and

status of any other pending interrupts. Table 5-18 defines the IRR, ISR, and IMR.

5.9.1.2 Acknowledging Interrupts

The processor generates an interrupt acknowledge cycle that is translated by the host

bridge into a PCI Interrupt Acknowledge Cycle to the PCH. The PIC translates this

command into two internal INTA# pulses expected by the 8259 cores. The PIC uses the

first internal INT A# pulse to freez e the state of the interrupts for priority resolution. On

the second INTA# pulse, the master or slave sends the interrupt vector to the

processor with the acknowledged interrupt code. This code is based upon bits [7:3] of

the corresponding ICW2 register, combined with three bits representing the interrupt

within that controller.

5.9.1.3 Hardware/Software Interrupt Sequence

1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or

seen high in level mode, setting the corresponding IRR bit.

2. The PIC sends INTR active to the processor if an asserted interrupt is not masked.

3. The processor acknowledges the INTR and responds with an interrupt acknowledge

cycle. The cycle is translated into a PCI interrupt acknowledge cycle by the host

bridge. This command is broadcast over PCI by the PCH.

4. Upon observing its own interrupt acknowledge cycle on PCI, the PCH converts it

into the two cycles that the internal 8259 pair can respond to. Each cycle appears

as an interrupt acknowledge pulse on the internal INTA# pin of the cascaded

interrupt controllers.

Table 5-18. Interrupt Status Registers

Bit Description

IRR Interrupt Request Register. This bit is set on a low to high transition of the inte rrupt lin e in edge

mode, and by an active high level in level mode. This bit is set whether or not the interrupt is

masked. However, a masked interrupt will not generate INTR.

ISR Interrupt Service Register. This bit is set, and the corresponding IRR bit cleared, when an

interrupt acknowledge cycle is seen, and the vector returned is for that interrupt.

IMR Interrupt Mask Register. This bit determines whether an interrupt is masked. Masked interrupts

will not generate INTR.

Table 5-19. Content of Interrupt Vector Byte

Master, Slave Interrupt Bits [7:3] Bits [2:0]

IRQ7,15

ICW2[7:3]

111

IRQ6,14 110

IRQ5,13 101

IRQ4,12 100

IRQ3,11 011

IRQ2,10 010

IRQ1,9 001

IRQ0,8 000

Functional Description

132 Intel® C600 Series Chipset and Intel® X79 Express Chipset

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5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR

bit is set and the corresponding IRR bit is reset. On the trailing edge of the first

pulse, a slave identification code is broadcast by the master to the slave on a

private, internal three bit wide bus. The slave controller uses these bits to

determine if it must respond with an interrupt vector during the second INTA#

pulse.

6. Upon receiving the second internally generated INTA# pulse, the PIC returns the

interrupt vector. If no interrupt request is present because the request was too

short in duration, the PIC returns vector 7 from the master controller.

7. This completes the interrupt cycle. In Automatic End of Interrupt (AEOI) mode the

ISR bit is reset at the end of the second INTA# pulse. Otherwise, the ISR bit

remains set until an appropriate EOI command is issued at the end of the interrupt

subroutine.

5.9.2 Initialization Command Words (ICWx)

Before operation can begin, each 8259 must be initialized. In the PCH, this is a four

byte sequence. The four initialization command words are referred to by their

acronyms: ICW1, ICW2, ICW3, and ICW4.

The base address for each 8259 initialization command word is a fixed location in the

I/O memory space: 20h for the master controller, and A0h for the slave controller.

5.9.2.1 ICW1

An I/O write to the master or sla ve controller base address with data bit 4 equal to 1 is

interpreted as a write to ICW1. Upon sensing this write, the PCH PIC expects three

more byte writes to 21h for the master controller, or A1h for the slave controller, to

complete the ICW sequence.

A write to ICW1 starts the initialization sequence during which the following

automatically occur:

1. Following initialization, an interrupt request (IRQ) input must make a low-to-high

transition to generate an interrupt.

2. The Interrupt Mas k Register is cleared.

3. IRQ7 input is assigned priority 7.

4. The slave mode address is set to 7.

5. Special mask mode is cleared and Status Read is set to IRR.

5.9.2.2 ICW2

The second write in the sequence (ICW2) is programmed to provide bits [7:3] of the

interrupt vector that will be released during an interrupt acknowledge. A different base

is selected for each interrupt controller.

5.9.2.3 ICW3

The third write in the sequence (ICW3) has a different meaning for each controller.

• For the master controller, ICW3 is used to indicate which IRQ input line is used to

cascade the slave con troller. Within the PCH, IRQ2 is used. Therefore, bit 2 of ICW3

on the master controller is set to a 1, and the other bits are set to 0s.

• For the slave controller, ICW3 is the slave identification code used during an

interrupt acknowledge cycle. On interrupt acknowledge cycles, the master

controller broadcasts a code to the slave controller if the cascaded interrupt won

arbitration on the master controller. The slave controller compares this

identification code to the value stored in its ICW3, and if it matches, the slave

controller assumes responsibility for broadcasting the interrupt vector.

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5.9.2.4 ICW4

The final write in the sequence (ICW4) must be programmed for both controllers. At

the very least, bit 0 must be set to a 1 to indicate that the controllers are operating in

an Intel Architecture-based system.

5.9.3 Operation Command Words (OCW)

These command words reprogram the Interrupt controller to operate in various

interrupt modes.

• OCW1 masks and unmasks interrupt lines.

• OCW2 controls the rotation of interrupt priorities when in rotating priority mode,

and controls the EOI function.

• OCW3 sets up ISR/IRR reads, enables/disables the special mask mode (SMM), and

enables/disables polled interrupt mode.

5.9.4 Modes of Operation

5.9.4.1 Fully Nested Mode

In this mode, interrupt requests are ordered in priority from 0 through 7, with 0 being

the highest. When an interrupt is acknowledged, the highest priority request is

determined and its vector placed on the bus. Additionally, the ISR for the interrupt is

set. This ISR bit remains set until: the processor issues an EOI command immediately

before returning from the service routine; or if in AEOI mode, on the trailing edge of

the second INTA#. While the ISR bit is set, all further interrupts of the same or lower

priority are inhibited, while higher levels generate another interrupt. Interrupt priorities

can be changed in the rotating priority mode.

5.9.4.2 Special Fully-Nested Mode

This mode is used in the case of a system where cascading is used, and the priority has

to be conserved within each slave. In this case, the special fully-nested mode is

programmed to the master controller. This mode is similar to the fully-nested mode

with the following exceptions:

• When an interrupt request from a certain slave is in service, this slav e is not locked

out from the master's priority logic and further interr upt requests from higher

priority interrupts within the slave are recognized by the master and initiate

interrupts to the processor. In the normal-nested mode, a slave is masked out

when its request is in service.

• When exiting the Interrupt Service routine, software has to check whether the

interrupt serviced was the only one from that slave. This is done by sending a Non-

Specific EOI command to the slave and then reading its ISR. If it is 0, a non-

specific EOI can also be sent to the master.

5.9.4.3 Automatic Rotation Mode (Equal Priority Devices)

In some applications, there are a number of interrupting devices of equal priority.

Automatic rotation mode provides for a sequential 8-way rotation. In this mode, a

device receives the lowest priority after being serviced. In the worst case, a device

requesting an interrupt has to wait until each of seven other devices are serviced at

most once.

There are two ways to accomplish automatic rotation using OCW2; the Rotation on

Non-Specific EOI Command (R=1, SL=0, EOI=1) and the rotate in automatic EOI mode

which is set by (R=1, SL=0, EO I=0).

Functional Description

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5.9.4.4 Specific Rotation Mode (Specific Priority)

Software can change interrupt priorities by programming the bottom priority. For

example, if IRQ5 is programmed as the bottom priority device, then IRQ6 is the highest

priority device. The Set Priority Command is issued in OCW2 to accomplish this, where:

R=1, SL=1, and LO–L2 is the binary priority level code of the bottom priority device.

In this mode, internal status is updated by software control during OCW2. However, it

is independent of the EOI command. Priority changes can be executed during an EOI

command by using the Rotate on Specific EOI Command in OCW2 (R=1, SL=1, EOI=1

and LO–L2=IRQ level to receive bottom priority.

5.9.4.5 Poll Mode

Poll mode can be used to conserve space in the interrupt vector table. Multiple

interrupts that can be serviced by one inter rupt serv ice routine do not need separate

vectors if the service routine uses the poll command. Poll mode can also be used to

expand the number of interrupts. The polling interrupt service routine can call the

appropriate service routine, instead of providing the interrupt vectors in the vector

table. In this mode, the INTR output is not used and the microprocessor internal

Interrupt Enable flip-flop is reset, disabling its interrupt input. Service to devices is

achieved by software using a Poll command.

The Poll command is issued by setting P=1 in OCW3. The PIC treats its next I/O read as

an interrupt acknowledge, sets the appropriate ISR bit if there is a request, and reads

the priority level. Interrupts are frozen from the OCW3 write to the I/O read. The byte

returned during the I/O read contains a 1 in bit 7 if there is an interrupt, and the binary

code of the highest priority level in bits 2:0.

5.9.4.6 Edge and Level Triggered Mode

In ISA systems this mode is programmed using bit 3 in ICW1, which sets level or edge

for the entire controller. In the PCH, this bit is disabled and a new register for edge and

level triggered mode selection, per interrupt input, is included. This is the Edge/Level

control Registers ELCR1 and ELCR2.

If an ELCR bit is 0, an interrupt request will be recognized by a low-to-high transition

on the corresponding IRQ input. The IRQ input can remain high without generating

another interrupt. If an ELCR bit is 1, an interrupt request will be recognized by a high

level on the corresponding IRQ input and there is no need for an edge detection. The

interrupt request must be removed before the EOI command is issued to prevent a

second interrupt from occurring.

In both the edge and level triggered modes, the IRQ inputs must remain active until

after the falling edge of the first internal INTA#. If the IRQ input goes inactive before

this time, a default IRQ7 vector is returned.

5.9.4.7 End of Interrupt (EOI) Operations

An EOI can occur in one of two fashions: by a command word write issued to the PIC

before returning from a service routine, the EOI command; or automatically when AEOI

bit in ICW4 is set to 1.

5.9.4.8 Normal End of Interrupt

In normal EOI, software writes an EOI command before leaving the interrupt service

routine to mark the interrupt as completed. There are two forms of EOI commands:

Specific and Non-Specific. When a Non-Specific EOI command is issued, the PIC clears

the highest ISR bit of those that are set to 1. Non-Specific EOI is the normal mode of

operation of the PIC within the PCH, as the interrupt being serviced currently is the

interrupt entered with the interrupt acknowledge. When the PIC is operated in modes

Functional Description

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that preserve the fully nested structure, software can determine which ISR bit to clear

by issuing a Specific EOI. An ISR bit that is masked is not cleared by a Non-Specific EOI

if the PIC is in the special mask mode. An EOI command must be issued for both the

master and slave controller.

5.9.4.9 Automatic End of Interrupt Mode

In this mode, the PIC automatically performs a Non-Specific EOI operation at the

trailing edge of the last interrupt acknowledge pulse. From a system standpoint, this

mode should be used only when a nested mu lti-level interrupt structure is not required

within a single PIC. The AEOI mode can only be used in the master controller and not

the slave controller.

5.9.5 Masking Interrupts

5.9.5.1 Masking on an Individual Interrupt Request

Each interrupt request can be masked individually by the Interrupt Mask Register

(IMR). This register is programmed through OCW1. Each bit in the IMR masks one

interrupt channel. Masking IRQ2 on the master controller masks all requests for service

from the slave controller.

5.9.5.2 Special Mask Mode

Some applications may require an interrupt service routine to dynamically alter the

system priority structure during its execution under softw are control. For example, the

routine may wish to inhibit lower priority requests for a portion of its execution but

enable some of them for another portion.

The special mask mode enables all interrupts not masked by a bit set in the Mask

issuing an EOI to clear the ISR bit, the interrupt controller inhibits all lower priority

requests. In the special mask mode, any interrupts may be selectively enabled by

loading the Mask Register with the appropriate pattern. The special mask mode is set

by OCW3 where: SSMM=1, SMM=1, and cleared where SSMM=1, SMM=0.

5.9.6 Steering PCI Interrupts

The PCH can be programmed to allow PIRQA#-PIRQH# to be routed internally to

interrupts 3–7, 9–12, 14 or 15. The assignment is programmable through the PIRQx

Route Control registers, located at 60–63h and 68–6Bh in Device 31:Function 0. One or

more PIRQx# lines can be routed to the same IRQx input. If interrupt steering is not

required, the Route registers can be programmed to disable steering.

The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts

on a PCI board to share a single line across the connector. When a PIRQx# is routed to

specified IRQ line, software must change the IRQ's corresponding ELCR bit to level

sensitive mode. The PCH internally inv erts the PIRQx# line to send an active high level

to the PIC. When a PCI interrupt is routed onto the PIC, the selected IRQ can no longer

be used by an active high device (through SERIRQ). However, active low interrupts can

share their interrupt with PCI interrupts.

Internal sources of the PIRQs, including SCI and TCO interrupts, cause the external

PIRQ to be asserted. The PCH receives the PIRQ input, like all of the other external

sources, and routes it accordingly.

Functional Description

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5.10 Advanced Programmable Interrupt Controller

(APIC) (D31:F0)

In addition to the standard ISA-compatible PIC described in the previous chapter, the

PCH incorporates the APIC. While the standard interrupt controller is intended for use

in a uni-processor system, APIC can be used in either a uni-processor or multi-

processor system.

5.10.1 Interrupt Handling

The I/O APIC handles interrupts very differently than the 8259. Briefly, these

differences are:

•Method of Interrupt Transmission. The I/O APIC transmits interrupts through

memory writes on the normal datapath to the processor, and interrupts are handled

without the need for the processor to run an interrupt acknowledge cycle.

•Interrupt Priority. The priority of interrupts in the I/O APIC is independent of the

interrupt number. For example, interrupt 10 can be given a higher priority than

interrupt 3.

•More Interrupts. The I/O APIC in the PCH supports a total of 24 interrupts.

•Multiple Interrupt Controllers. The I/O APIC architecture allows for multiple I/O

APIC devices in the system with their own interrupt vectors.

5.10.2 Interrupt Mapping

The I/O APIC within the PCH supports 24 APIC interrupts. Each interrupt has its own

unique vector assigned by software. The interrupt vectors are mapped as follows, and

match “Config 6” of the Multi-Processor Specification.

Table 5-20. APIC Interrupt Mapping1 (Sheet 1 of 2)

IRQ # Using

SERIRQ

Direct

from Pin

Using PCI

Message Internal Modules

0 No No No Cascade from 8259 #1

1Yes No Yes

2 No No No 8254 Counter 0, HPET #0 (legacy mode)

3Yes No Yes

4Yes No Yes

5Yes No Yes

6Yes No Yes

7Yes No Yes

8No No NoRTC, HPET #1 (legacy mode)

9 Yes No Yes Option for SCI, TCO

10 Yes No Yes Option for SCI, TCO

11 Yes No Yes HPET #2, Option for SCI, TCO (Note2)

12 Yes No Yes HPET #3 (Note 3)

13 No No No FERR# logic

14 Yes No Yes SATA Primary (legacy mode)

15 Yes No Yes SATA Secondary (legacy mode)

16 PIRQA# PIRQA#

Yes Internal devices are routable; see Section 10.1.20

though Section 10.1.29.

17 PIRQB# PIRQB#

18 PIRQC# PIRQC#

19 PIRQD# PIRQD#

Functional Description

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Notes:

1. When programming the polarity of internal interrupt sources on the APIC, interrupts 0 through 15

receive active-high internal interrupt sour ces, while interrupts 16 through 23 receiv e active-low internal

interrupt sources.

2. If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared with any other devices to

ensure the proper operation of HPET #2. PCH hardware does not prevent sharing of IRQ 11.

3. If IRQ 12 is used for HPET #3, software should ensure IRQ 12 is not shared with any other devices to

ensure the proper operation of HPET #3. PCH hardware does not prevent sharing of IRQ 12.

4. PIRQ[E:H]# are Multiplexed with GPIO pins. Interrupts PIRQ[E:H]# will not be exposed if they are

configured as GPIOs.

5.10.3 PCI / PCI Express* Message-Based Interrupts

When external devices through PCI / PCI Express* wish to generate an interrupt, they

will send the message defined in the PCI Express* Base Specification, Revision 1.0a for

generating INTA# - INTD#. These will be translated internal assertions/deassertions of

INTA# - INTD#.

5.10.4 IOxAPIC Address Remapping (SRV/WS SKUs Only)

To support Intel Virtualization Te chnology, interrupt messages are required to go

through similar address remapping as any other memory request. Address remapping

allows for domain isolation for interrupts, so a device assigned in one domain is not

allowed to generate an interrupt to another domain.

The address remapping is based on the Bus: Device: Function field associated with the

requests. The internal APIC is required to initiate the interrupt message using a unique

Bus: Device: function.

The PCH allows BIOS to program the unique Bus: Device: Function address for the

internal APIC. This address field does not change the APIC functionality and the APIC is

not promoted as a stand-alone PCI device. See Device 31: Function 0 Offset 6Ch for

additional information.

5.10.5 External Interrupt Controller Support

The PCH supports external APICs off of PCI Express* ports, and does not support APICs

on the PCI bus. The EOI special cycle is only forw arded to PCI Express* ports.

20 N/A PIRQE#4

Yes Option for SCI, TCO, HPET #0,1,2, 3. Other internal

devices are routable; see Section 10.1.20 though

Section 10.1.29.

21 N/A PIRQF#4

22 N/A PIRQG#4

23 N/A PIRQH#4

Table 5-20. APIC Interrupt Mapping1 (Sheet 2 of 2)

IRQ # Using

SERIRQ

Direct

from Pin

Using PCI

Message Internal Modules

Functional Description

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Datasheet

5.11 Serial Interrupt (D31:F0)

The PCH supports a serial IRQ scheme. This allows a single signal to be used to report

interrupt requests. The signal used to tra nsmit this information is shared between the

host, the PCH, and all peripherals that support serial interrupts. The signal line,

SERIRQ, is synchronous to PCI clock, and follows the sustained tri-state protocol that is

used by all PCI signals. This means that if a device has driven SERIRQ low, it will first

drive it high synchronous to PCI clock and release it the following PCI clock. The serial

IRQ protocol defines this sustained tri-state signaling in the following fashion:

•S – Sample Phase. Signal driven low

•R – Recovery Phase. Signal driven high

•T – Turn-around Phase. Signal released

The PCH supports a message for 21 serial interrupts. These represent the 15 ISA

interrupts (IRQ0–1, 3–15), the four PCI interrupts, and the control signals SMI# and

IOCHK#. The serial IRQ protocol does not support the additional APIC interrupts (20–

23).

Note: When the SATA controller is configured for leg a cy IDE mode, IRQ14 and IRQ15 are

expected to behave as ISA legacy interrupts, which cannot be shared (that is, through

the Serial Interrupt pin). If IRQ14 and IRQ15 are shared with Serial Interrupt pin then

abnormal system behavior may occur. For example, IRQ14/15 may not be detected by

PCH's interrupt controller. When the SA TA controller is not running in Native IDE mode,

IRQ14 and IRQ15 are used as special interrupts. If the SATA controller is in native

modes, these interrupts can be mapped to other devices accordingly.

5.11.1 Start Frame

The serial IRQ protocol has two modes of operation which affect the start frame. These

two modes are: Continuous, where the PCH is solely responsible for generating the

start frame; and Quiet, where a serial IRQ peripheral is responsible for beginning the

start frame.

The mode that must first be entered when enabling the serial IRQ protocol is

continuous mode. In this mode, the PCH asserts the start frame. This start frame is 4,

6, or 8 PCI clocks wide based upon the Serial IRQ Control Register, bits 1:0 at 64h in

Device 31:Function 0 configuration space. This is a polling mode.

When the serial IRQ stream enters quiet mode (signaled in the Stop Frame), the

SERIRQ line remains inactive and pulled up between the Stop and Start Frame until a

peripheral drives the SERIRQ signal low. The PCH senses the line low and continues to

drive it low for the remainder of the Start Frame. Since the first PCI clock of the start

frame w as driven by the peripheral in this mode, the PCH drives the SERIRQ line low for

1 PCI clock less than in continuous mode. This mode of operation allows for a quiet,

and therefore lower power, operation.

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5.11.2 Data Frames

Once the Start frame has been initiated, all of the SERIRQ peripherals must start

counting frames based on the rising edge of SERIRQ. Each of the IRQ/DAT A fr ames has

exactly 3 phases of 1 clock each:

•Sample Phase. During this phase, the SERIRQ device drives SERIRQ low if the

corresponding interrupt signal is low. If the corresponding interrupt is high, then

the SERIRQ devices tri-state the SERIRQ signal. The SERIRQ line remains high due

to pull-up resistors (there is no internal pull-up resistor on this signal, an external

pull-up resistor is required). A low level during the IRQ0–1 and IRQ2–15 frames

indicates that an active-high ISA interrupt is not being requested, but a low level

during the PCI INT[A:D], SMI#, and IOCHK# frame indicates that an active-low

interrupt is being requested.

•Recovery Phase. During this phase, the device drives the SERIRQ line high if in

the Sample Phase it was driven low. If it was not driven in the sample phase, it is

tri-stated in this phase.

•Turn-around Phase. The device tri-states the SERIRQ line.

5.11.3 Stop Frame

After all data frames, a Stop Frame is driven by the PCH. The SERIRQ signal is driven

low by the PCH for 2 or 3 PCI clocks. The number of clocks is determined by the

SERIRQ configuration register. The number of clocks determines the next mode:

5.11.4 Specific Interrupts Not Supported using SERIRQ

There are three interrupts seen through the serial stream that are not supported by the

PCH. These interrupts are generated internally, and are not shar able with other devices

within the system. These interrupts are:

• IRQ0. Heartbeat interrupt generated off of the internal 8254 counter 0.

• IRQ8#. RTC interrupt can only be generated internally.

• IRQ13. Floating point error interrupt generated off of the processor assertion of

FERR#.

The PCH ignores the state of these interrupts in the serial stream, and does not adjust

their level based on the level seen in the serial stream.

Table 5-21. Stop Frame Explanation

Stop Frame Width Next Mode

2 PCI clocks Quiet Mode. Any SERIRQ device may initiate a Start Frame

3 PCI clocks Continuous Mode. Only the host () may initiate a Start Frame

Functional Description

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5.11.5 Data Frame Format

Table 5-22 shows the format of the data frames. For the PCI interrupts (A–D), the

output from the PCH is AND’d with the PCI input signal. This way, the interrupt can be

signaled using both the PCI interrupt input signal and using the SERIRQ signal (they

are shared).

5.12 Real Time Clock (D31:F0)

The R eal Time Clock (RT C) module provides a battery backed-up da te and time keeping

device with two banks of static RAM with 128 bytes each, although the first bank has

114 bytes for general purpose usage. Three interrupt features are available: time of

day alarm with once a second to once a month range, periodic rates of 122 µs to

500 ms, and end of update cycle notification. Seconds, minutes, hours, days, day of

week, month, and year are counted. Daylight savings compensation is no longer

supported. The hour is represented in twelve or twenty-four hour format, and data can

be represented in B CD or binary format. The design is functionally compatible with the

Motorola MS146818B. The time keeping comes from a 32.768 kHz oscillating source,

which is divided to achieve an update every second. The lower 14 bytes on the lower

RAM block has very specific functions. The first ten are for time and date information.

The next four (0Ah to 0Dh) are registers, which configure and report RTC functions.

The time and calendar data should match the data mode (BCD or binary) and hour

mode (12 or 24 hour) as selected in register B. It is up to the programmer to make

sure that data stored in these locations is within the reasonable values ranges and

represents a possible date and time. The exception to these ranges is to store a value

Table 5-22. Data Frame Format

Data

Frame # Interrupt Clocks Past

Start Frame Comment

1 IRQ0 2 Ignored. IRQ0 can only be generated using the internal 8524

2IRQ1 5

3 SMI# 8 Causes SMI# if low. Will set the SERIRQ_SMI_STS bit.

4IRQ3 11

5IRQ4 14

6IRQ5 17

7IRQ6 20

8IRQ7 23

9 IRQ8 26 Ignored. IRQ8# can only be generated internally.

10 IRQ9 29

11 IRQ10 32

12 IRQ11 35

13 IRQ12 38

14 IRQ13 41 Ignored. IRQ13 can only be generated from FERR#

15 IRQ14 44 Not attached to SATA logic

16 IRQ15 47 Not attached to SATA logic

17 IO CHCK# 50 Same as ISA IOCHCK# going active.

18 PCI INTA# 53 Drive PIRQA#

19 PCI INTB# 56 Drive PIRQB#

20 PCI INTC# 59 Drive PIRQC#

21 PCI INTD# 62 Drive PIRQD#

Functional Description

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of C0–FFh in the Alarm bytes to indicate a don’t care situation. All Alarm conditions

must match to trigger an Alarm Flag, which could trigger an Alarm Interrupt if enabled.

The SET bit must be 1 while programming these locations to avoid clashes with an

update cycle. Access to time and date information is done throu gh the RAM locations. If

a RAM read from the ten time and date bytes is attem pted during an update cycle, the

value read do not necessarily represent the true contents of those locations. Any RAM

writes under the same conditions are ignored.

Note: The leap year determination for adding a 29th day to February does not take into

account the end-of-the-century exceptions. The logic simply assumes that all years

divisible by 4 are leap years. According to the R oy al Observ atory Greenwich, years that

are divisible by 100 are typically not leap years. In every fourth century (years divisible

by 400, like 2000), the 100-y ear-exception is over-ridden and a leap- year occurs. Note

that the year 2100 will be the first time in which the current RT C implementation would

incorrectly calculate the leap-year.

The PCH does not implement month/year alarms.

5.12.1 Update Cycles

An update cycle occurs once a second, if the SET bit of register B is not asserted and

the divide chain is properly configured. During this procedure, the stored time and date

are incremented, overflow is checked, a matching alarm condition is checked, and the

time and date are rewritten to the RAM locations. The update cycle will start at least

488 µs after the UIP bit of register A is asserted, and the entire cycle does not take

more than 1984 µs to complete. The time and date RAM locations (0–9) are

disconnected from the external bus during this time.

To avoid update and data corruption conditions, external RAM access to these locations

can safely occur at two times. When a updated-ended interrupt is detected, almost 999

ms is available to read and write the valid time and date data. If the UIP bit of Register

A is detected to be low, there is at least 488 µs before the update cycle begins.

Warning: The overflow conditions for leap y ears adjustments are based on more than one date or

time item. To ensure proper operation when adjusting the time, the new time and data

values should be set at least two seconds before leap year occurs.

5.12.2 Interrupts

The real-time clock interrupt is internally routed within the PCH both to the I/O APIC

and the 8259. It is mapped to interrupt vector 8. This interrupt does not leave the PCH,

nor is it shared with any other interrupt. IRQ8# from the SERIRQ stream is ignored.

However, the High Performance Event Timers can also be mapped to IRQ8#; in this

case, the RTC interrupt is blocked.

5.12.3 Lockable RAM Ranges

The RTC battery-backed RAM supports two 8-byte ranges that can be locked using the

configuration space. If the locking bits are set, the corresponding r ange in the RAM will

not be readable or writable. A write cycle to those locations will have no effect. A read

cycle to those locations will not return the location’s actual value (resultant value is

undefined).

Once a range is locked, the range can be unlocked only by a hard reset, which will

invoke the BIOS and allow it to relock the RAM range .

Functional Description

142 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.12.4 Century Rollover

The PCH detects a rollover when the Year byte (R TC I/O space, index Cffset 09h)

transitions form 99 to 00. Upon detecting the rollover, the PCH sets the

NEWCENTURY_STS bit (TCOBASE + 04h, bit 7). If the system is in an S0 state, this

causes an SMI#. The SMI# handler can update registers in the RTC RAM that are

associated with century value. If the system is in a sleep state (S1–S5) when the

century rollover occurs, the PCH also sets the NEWCENTURY_STS bit, but no SMI# is

generated. When the system resumes from the sleep state, BIOS should check the

NEWCENTURY_STS bit and update the century value in the RTC RAM.

5.12.5 Clearing Battery-Backed RTC RAM

Clearing CMOS RAM in an PCH-based platform can be done by using a jumper on

RTCRST# or GPI. Implementations should not attempt to clear CMOS by using a

jumper to pull VccRTC low.

Using RTCRST# to Clear CMOS

A jumper on RTCRST# can be used to clear CMOS values, as well as reset to default,

the state of those configuration bits that reside in the RTC power well. When the

RTCRST# is strapped to ground, the RTC_PWR_STS bit (D31:F0:A4h bit 2) will be set

and those configuration bits in the RTC power well will be set to their default state.

BIOS can monitor the state of this bit, and manually clear the R TC CMOS arr ay once the

system is booted. The normal position would cause R T CRST# to be pulled up through a

weak pull-up resistor. Table 5-23 shows which bits are set to their default state when

RTCRST# is asserted. This RT CRST# jumper technique allows the jumper to be mov ed

and then replaced—all while the system is powered off. Then, once booted, the

RTC_PWR_STS can be detected in the set state.

Table 5-23. Configuration Bits Reset by RTCRST# Assertion (Sheet 1 of 2)

Bit Name Register Location Bit(s) Default

State

Alarm Interrupt Enable

(AIE)

Configuration)

(RTC_REGB) I/O space (RTC Index + 0Bh) 5 X

Alarm Flag (AF) Register C (Flag

SWSMI_RATE_SEL General PM

Configurat ion 3 R egist er

GEN_PMCON_3 D31:F0:A4h 7:6 0

SLP_S4# Minimum

Assertion Width

General PM

Configurat ion 3 R egist er

GEN_PMCON_3 D31:F0:A4h 5:4 0

SLP_S4# Assertion

Stretch Enable

General PM

Configurat ion 3 R egist er

GEN_PMCON_3 D31:F0:A4h 3 0

RTC Power Status

(RTC_PWR_STS)

General PM

Configurat ion 3 R egist er

GEN_PMCON_3 D31:F0:A4h 2 0

Power Failure (PWR_FLR) General PM

Configurat ion 3 R egist er

(GEN_PMCON_3) D31:F0:A4h 1 0

AFTERG3_EN General PM

Configurat ion 3 R egist er

GEN_PMCON_3 D31:F0:A4h 0 0

Power Button Override

Status (PRBTNOR_STS)

Power Manageme nt 1

Status Register

(PM1_STS) PMBase + 00h 11 0

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 143

Datasheet

Using a GPI to Clear CMOS

A jumper on a GPI can also be used to clear CMOS values. BIOS would detect the

setting of this GPI on system boot-up, and manually clear the CMOS array.

Note: The GPI strap technique to clear CMOS requires multiple steps to implement. The

system is booted with the jumper in new position, then powered back down. The

jumper is replaced back to the normal position, then the system is rebooted again.

Warning: Do not implement a jumper on VccRTC to clear CMOS.

5.13 Processor Interface (D31:F0)

The PCH interfaces to the processor with following pin-based signals other than DMI:

• Standard Outputs to processor: PROCPWRGD, PM_SYNC, PM_SYNC2, PECI

• Standard Input from processor: THRMTRIP#

Most PCH outputs to the processor use standard buffers. The PCH has separate

V_PROC_IO signals that are pulled up at the system level to the processor voltage, and

thus determines VOH for the outputs to the processor.

The following Processor interface legacy pins were removed from the PCH:

• IGNNE#, STPCLK#, DPSLP#, are DPRSLPVR are no longer required on PCH based

systems.

• SMI#, NMI, INIT#, INTR, FERR#: Functionality has been replaced by in-band

Virtual Legacy Wire (VLW) messages. See Section 5.13.3.

RTC Event Enable

(RTC_EN)

Power Management 1

Enable Register

(PM1_EN) PMBase + 02h 10 0

Sleep Type (SLP_TYP) Power Management 1

Control (PM1_CNT) PMBase + 04h 12:10 0

PME_EN General Pu rpose Event 0

Enables Register

(GPE0_EN) PMBase + 2Ch 11 0

BATLOW_EN General Purpose Event 0

Enables Register

(GPE0_EN) PMBase + 2Ch 10 0

RI_EN General Purpose Ev ent 0

Enables Register

(GPE0_EN) PMBase + 2Ch 8 0

NEWCENTURY_STS TCO1 Status Register

(TCO1_STS) TCOBase + 04h 7 0

Intruder Detect

(INTRD_DET) TCO2 Status Register

(TCO2_STS) TCOBase + 06h 0 0

Top Swap (TS) Backed Up Control

Registers:Offset 3414h 0X

Table 5-23. Configuration Bits Reset by RTCRST# Assertion (Sheet 2 of 2)

Bit Name Register Location Bit(s) Default

State

Functional Description

144 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.13.1 Processor Interface Signals and VLW Messages

This section describes each of the signals that interface between the PCH and the

processor(s). Note that the behavior of some signals may vary during processor reset,

as the signals are used for frequency strapping.

5.13.1.1 INIT (Initialization)

The INIT# VL W Message is asserted based on any one of several events described in

Table 5-24. When any of these events occur, INIT# is asserted for 16 PCI clocks, then

driven high.

Note: INIT3_3V# is functionally identical to INIT# VLW but it is a physical signal at 3.3 V.

5.13.1.2 FERR# (Numeric Coprocessor Error)

The PCH supports the coprocessor error function with the FERR# message. The

function is enabled using the CEN bit. If FERR# is driven active by the processor, IRQ13

goes active (internally). When it detects a write to the COPROC_ERR register (I/O

remains active until FERR# is driven inactive. IGNNE# is never driven active unless

FERR# is active.

Note: IGNNE# – Ignore Numeric Error is now internally generated by the processor.

Table 5-24. INIT# Going Active

Cause of INIT3_3V# Going Active Comment

Shutdown special cy cle fro m pr oce sso r o bse rv e d

on PCH-Processor interconnect. INIT assertion based on value of Shutdown Policy Select

PORT92 write, where INIT_NOW (bit 0)

transitions from a 0 to a 1.

PORTCF9 write, where SYS_RST (bit 1) was a 0

and RST_CPU (bit 2) transitions from 0 to 1.

RCIN# input signal goes low. RCIN# is expected

to be driven by the extern al microcontroller

(KBC).

0 to 1 transition on RCIN# must occur before the PCH will

arm INIT3_3V# to be generated again.

Note: RCIN# signal is expected to be low during S3, S4,

and S5 states. Transition on the RCIN# signal in

those states (or the transition to thos e states) may

not necessarily cause the INIT3_3V# signal to be

generated to the processor.

Processor BIST To enter BIST, software sets CPU_BIST_EN bit and then

does a full processor reset usin g the CF9 register.

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 145

Datasheet

5.13.1.3 NMI (Non-Maskable Interrupt)

Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in

Table 5-25.

5.13.1.4 Processor Power Good (PROCPWRGD)

This signal is connected to the processor’s PRWGOOD input to indicate when the

processor power is valid.

5.13.2 Dual-Processor Issues

5.13.2.1 Usage Differences

In dual-processor designs, some of the processor signals are unused or used differently

than for uniprocessor designs.

• FERR# is generally not used, but still supported.

• I/O APIC and SMI# are assumed to be used.

5.13.3 Virtual Legacy Wire (VLW) Messages

The PCH supports VLW messages as alternative method of conveying the status of the

following legacy sideband interface signals to the Processor:

• INTR, SMI#, INIT#, NMI

Note: IGNNE# VLW message is not required to be generated by the PCH as it is internally

emulated by the Processor.

VLW are inbound messages to the Processor. They are communicated using Vendor

Defined Message over the DMI link.

Legacy processor signals can only be delivered using VLW in PCH. Delivery of legacy

processor signals (INTR, SMI#, INIT# or NMI) using I/O APIC controller is not

supported.

Table 5-25. NMI Sources

Cause of NMI Comment

SERR# goes active (either internally, externally

using SERR# signal, or using message from

Processor)

Can instead be routed to generate an SCI, through the

NMI2SCI_EN bit (Device 31:Function 0, TCO Base + 08h,

bit 11).

IOCHK# goes active using SERIRQ# stream

(ISA system Error)

Can instead be routed to generate an SCI, through the

NMI2SCI_EN bit (Device 31:Function 0, TCO Base + 08h,

bit 11).

SECSTS Register Device 31: Function F0 Offset

1Eh, bit 8. This is enabled by the Parity Error Response Bit (PER) at

Device 30: Function 0 Offset 04, bit 6.

DEV_STS R egister Device 31: Function F0 Offse t

06h, bit 8 This is enabled by the Parity Error Response Bit (PER) at

Device 30: Function 0 Offset 04, bit 6.

GPIO[15:0] when configured as a General

Purpose input and routed as NMI (by

GPIO_ROUT at Device 31: Function 0 Offset B8)

This is enabled by GPI NMI Enable (GPI_NMI_EN) bits at

Device 31: Function 0 Offset: GPIOBASE + 28h bits 15:0

Functional Description

146 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.14 Power Management

5.14.1 Features

• Support for Advanced Configuration and Power Interface, Version 3.0b (ACPI)

providing power and thermal management

— ACPI 24-Bit Timer SCI and SMI# Generation

• PCI PME# signal for Wake Up from Low-Power states

• System Sleep State Control

— ACPI S3 state — Suspend to RAM (STR)

— ACPI S4 state — Suspend-to-Disk (STD)

— ACPI G2/S5 state — Soft Off (SOFF)

— Power Failure Detection and Recovery

— Deep S4/S5

• Intel ME Power Management Support

— Wake events from the Intel ME (enabled from all S-States including

Catastrophic S5 conditions)

5.14.2 PCH and System Power States

Table 5-26 shows the power states defined for PCH-based platforms. The state names

generally match the corresponding ACPI states.

Table 5-26. General Power States for Systems Using the PCH

State/

Substates Legacy Name / Description

G0/S0/C0 Full On: Processor operating. Individual devices may be shut down or be placed into lower

power states to save power.

G0/S0/Cx

Cx State: Cx states are processor power states within the S0 system state that provide for

various levels of power savings. The Processor initiates C-state entry and exit while

interacting with the PCH through DMI messaging. The PCH will base its behavior on the

Processor state.

G1/S1 S1: PCH provides the S1 messages and the S0 messages on a wake event. It is much

preferred for systems to use C-states than S1.

G1/S3 Suspend-To-RAM (STR): The system conte xt is maintained in system DRAM, but power is

shut off to non-critical circuits. Memory is retained and refreshes continue. All external

clocks stop except RTC.

G1/S4 Suspend-To-Disk (STD): The context of the syste m is maintained on the disk. All power is

then shut off to the system except for the logic required to resume.

G2/S5 Soft Off (SOFF): System context is not maintained. All power is shut off except for the logic

required to restart. A full boot is required when waking.

Deep S4/S5

Deep S4/S5: An optional low power state where sys tem context may or may not be

maintained depending upon entry condition. All power is shut off except for minimal logic

that allows exiting Deep S4/S5. If Deep S4/S5 state was entered from S4 state, then the

resume path will place system back into S4. If Deep S4/S5 state was entered from S5 state,

then the resume path will place system back into S5.

Mechanical OFF (MOFF): System context not maintained. All power is shut off except for

the RTC. No “Wake” events are possible. This state occurs if the user turns off a mechanical

switch or if the system power supply is at a level that is insufficient to power the “waking”

logic. When system po we r returns, tran sition will depend on the state just prior to the entry

to G3 and the AFTERG3 bit in the GEN_PMCON_3 register (D31:F0, offset A4). Refer to

Table 5-33 for more details.

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 147

Datasheet

Table 5-27 shows the transitions rules among the various states. Note that transitions

among the various states may appear to temporarily transition through intermediate

states. For example, in going from S0 to S3, it may appear to pass through the G1/S1

states. These intermediate transitions and states are not listed in the table.

Notes:

1. Some wake events can be preserved through power failure.

2. Includes all other applicable types of events that force the host into and stay in G2/S5.

3. If the system was in G1/S4 before G3 entry, then the system will go to S0/C0 or G1/S4.

4. Upon entry to S5 due to a power button override, if Deep S4/S5 is enabled and conditions are met per

Section 5.14.6.6 the system will transition to Deep S4/S5.

5. Upon entry to S5 due to a power button override, if Deep S4/S5 is enabled and conditions are met per

section 5.13.7.6, the system will transition to Deep S4/S5.

Table 5-27. State Transition Rules for the PCH

Present

State Transition Trigger Next State

G0/S0/C0

•DMI Msg

•SLP_EN bit set

• Power Button Override22

• Mechanical Off/Power Failure

•G0/S0/Cx

• G1/Sx or G2/S5 state

•G2/S5

•G3

G0/S0/Cx •DMI Msg

• Power Button Override2

• Mechanical Off/Power Failure

•G0/S0/C0

•G2/S5

•G3

G1/S1 or

G1/S3

•Any Enabled Wake Event

• Power Button Override2

• Mechanical Off/Power Failure

•G0/S0/C0

•G2/S5

•G3

G1/S4

• Any Enabled Wake Event • G0/S0/C0

• Power Button Override2•G2/S5

• Conditions met as described in

Section 5.14.6.6.1 and

Section 5.14.6.6.2 •Deep S4/S5

• Mechanical Off/Power Failure • G3

G2/S5

• Any Enabled Wake Event • G0/S0/C02

• Conditions met as described in

Section 5.14.6.6.1 and

Section 5.14.6.6.2 •Deep S4/S5

• Mechanical Off/Power Failure • G3

G2/Deep

S4/S5 •Any Enabled Wake Event

• Mechanical Off/Power Failure

•G0/S0/C0

• G1/S4 or G2/S5 (see Section 5.14.6.6.2)

•G3

G3 • Power Re turns • Optional to go to S0/C0 (reboot) or G2/S5

(stay off until power button pressed or other

wake event). (See Note 1)

Functional Description

148 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.14.3 System Power Planes

The system has several independent power planes, as described in Table 5-28. Note

that when a particular power plane is shut off, it should go to a 0 V level.

5.14.4 SMI#/SCI Generation

Upon any enabled Intel SMI event taking place while the End of Intel SMI (EOS) bit is

set, the PCH will clear the EOS bit and assert Intel SMI to the processor, which will

cause it to enter SMM space. Intel SMI assertion is performed using a Virtual Legacy

Wire (VLW) message. Prior system generations (those based upon legacy processors)

used an actual SMI# pin.

Once the Intel SMI VL W has been delivered, the PCH takes n o action on behalf of active

Intel SMI events until Host software sets the En d of Intel SMI (EOS) bit. At that point, if

any Intel SMI events are still active, the PCH will send another Intel SMI VLW.

The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating

system. In non-APIC systems (which is the default), the SCI IRQ is routed to one of the

8259 interrupts (IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed

to level mode for that interrupt.

In systems using the APIC, the SCI can be routed to interrupts 9, 10, 11, 20, 21, 22, or

23. The interrupt polarity changes depending on whether it is on an interrupt shareable

with a PIRQ or not (see Section 13.1.14). The interrupt remains asserted until all SCI

sources are removed.

Table 5-29 shows which events can cause an Intel SMI and SCI. Note that some events

can be programmed to cause eith er an Intel SMI or SCI. The usage of the even t for SCI

(instead of Intel SMI) is typically associated with an ACPI-based system. Each Intel SMI

or SCI source has a corresponding enable and status bit.

Table 5-28. System Power Plane

Plane Controlled

By Description

Processor SLP_S3#

signal The SLP_S3# signal can be used to cut the power to the processor

completely.

Main SLP_S3#

signal

When SLP_S3# goes active, power can be shut off to any cir cuit not required

to wake the system from the S3 state. Since the S3 state requires that the

memory cont ext be pr eserv ed, powe r must be retained to the main memory.

The processor, devices on the PCI bus, LPC I/F, and graphics will typically be

shut off when the Main power plane is off, although there may be small

subsections powered.

Memory

SLP_S4#

signal

SLP_S5#

signal

When SLP_S4# goes active, power can be shut off to any cir cuit not required

to wake the system from the S4. Since the memory context does not need

to be preserved in the S4 state, the power to the memory can also be shut

down.

When SLP_S5# goes active, power can be shut off to any cir cuit not required

to wake the system from the S5 state. Since the memory context does not

need to be preser ved in the S5 state, the power to the memory can also be

shut.

Intel ME SLP_A# This signal is asserted when the manageability platform goes to MOff.

Depending on the platform, this pin may be used to control the Intel ME

power planes, LAN subsystem power, and the SPI flash power.

LAN SLP_LAN# This signal is asserted in Sx/Moff when both host and Intel ME WOL are not

supported. This signal can be use to control power to the Intel GbE PHY.

Suspend SLP_SUS# This signal that the Sus rails externally can be shut off for enhanced power

saving.

DEVICE[n] GPIO Individual subsystems may have their own power plane . For example, GPIO

signals may be used to control the pow er to disk driv es, audio amplifier s, or

the display screen.

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 149

Datasheet

Table 5-29. Causes of Intel® Scalable Memory Interconnect (Intel® SMI) and SCI (Sheet

1 of 2)

Cause SCI SMI Additional Enables Where Reported

PME# Yes Yes PME_EN=1 PME_STS

PME_B0 (Internal, Bus 0, PME-Capable

Agents) Yes Yes PME_B0_EN=1 PME_B0_STS

PCI Express* PME Messages Yes Yes PCI_EXP_EN=1

(Not enabled for SMI) PCI_EXP_STS

PCI Express* Hot-Plug Message Yes Yes HOT_PLUG_EN=1

(Not enabled for SMI) HOT_PLUG_STS

Power Button Press Yes Yes PWRBTN_EN=1 PWRBTN_STS

Power Button O verride (Note 7) Yes No None PRBTNOR_STS

RTC Alarm Yes Yes RTC_EN=1 RTC_STS

Ring Indicate Yes Yes RI_EN=1 RI_STS

USB#1 wakes Yes Yes USB1_EN=1 USB1_STS

USB#2 wakes Yes Yes INTEL_USB2_EN=1 INTEL_USB2_STS

USB#3 wakes Yes Yes USB3_EN=1 USB3_STS

USB#4 wakes Yes Yes USB4_EN=1 USB4_STS

USB#5 wakes Yes Yes USB5_EN=1 USB5_STS

USB#6 wakes Yes Yes USB6_EN=1 USB6_STS

USB#9wakes Yes Yes USB9_EN=1 USB9_STS

ACPI Timer overflow (2.34 sec.) Yes Yes TMROF_EN=1 TMROF_STS

Any GPI[15 :0] Yes Yes

GPI[x]_Route=10; GPI[x]_EN=1

(SCI)

GPI[x]_Route=01;

ALT_GPI_SMI[x]_EN=1 (SMI)

GPI[x]_STS

ALT_GPI_SMI[x]_STS

GPIO[27] Yes Yes GP27_EN=1 GP27_STS

TCO SCI Logic Yes No TCOSCI_EN=1 TCOSCI_STS

TCO SCI message from MCH Yes Yes none MCHSCI_STS

MCHSMI_STS

TCO SMI Logic No Yes TCO_EN=1 TCO_STS

TCO SMI — Year 2000 Rollover No Yes none NEWCENTURY_STS

TCO SMI — TCO TIMEROUT No Yes none TIMEOUT

TCO SMI — OS writes to TCO_DAT_IN

TCO SMI — Message from processor No Yes none DMISMI_STS

TCO SMI — NMI occurred (and NMIs

mapped to SMI) No Yes NMI2SMI_EN=1 NMI2SMI_STS

TCO SMI — INTRUDER# signal goes

active No Yes INTRD_SEL=10 INTRD_DET

TCO SMI — Change of the BIOSWE

(D31:F0:DCh, bit 0) bit from 0 to 1 No Yes BCLE=1 BIOSWR_STS

TCO SMI — Write atte mpted to BIOS No Yes BC.WPD =0 (Write Protect Disable) BIOSWR_STS

NMI (and NMI’s mapped to SMI)

See NMI section for causes of NMI No Yes NMI2SMI_EN=1 TCO_STS_NMI2SMI_STS

BIOS_RLS written to Yes No GBL_EN=1 GBL_STS

GBL_RLS written to No Yes BIOS_EN=1 BIOS_STS

Write to B2h register No Yes APMC_EN = 1 APM_STS

Functional Description

150 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Notes:

1. SCI_EN must be 1 to enable SCI, except for BIOS_RLS. SCI_EN must be 0 to enable SMI.

2. SCI can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in APIC mode).

3. GBL_SMI_EN must be 1 to enable SMI.

4. EOS must be written to 1 to re-enable Intel SMI for the next 1.

5. PCH must have Intel SMI fully enabled when PCH is also enabled to trap cycles. If Intel SMI is not

enabled in conjunction with the trap enabling, then hardware behavior is undefined.

6. Only GPI[15:0] may generate an Intel SMI or SCI.

7. When a power button override first occurs, the system will transition immediately to S5. The SCI will

only occur after the next wake to S0 if the residual status bit (PRBTNOR_STS) is not cleared prior to

setting SCI_EN.

8. GBL_STS being set will cause an SCI, even if the SCI_EN bit is not set. Software must take great care

not to set the BIOS_RLS bit (which causes GBL_STS to be set) if the SCI handler is not in place.

Periodic timer expires No Yes PERIODIC_EN=1 PERIODIC_STS

64 ms timer expires No Yes SWSMI_TMR_EN=1 SWSMI_TMR_STS

Enhanced USB Legacy Support Event No Yes LEGACY_USB2_EN = 1 LEGACY_USB2_STS

Enhanced USB Intel Specific Event No Yes INTEL_USB2_EN = 1 INTEL_USB2_STS

Serial IRQ Intel SMI reported No Yes none SERIRQ_SMI_STS

Device monitors match address in its

range No Yes See DEVTRAP_STS register

description DEVTRAP_STS

SMBus Host Controller No Yes SMB_SMI_EN

Host Controller Enabled SMBus host status reg.

SMBus Slave Intel SMI message No Yes none SMBUS_SMI_STS

SMBus SMBALERT# signal active No Yes none SMBUS_SMI_STS

SMBus Host Notify message received No Yes HOST_NOTIFY_INTREN SMBUS_SMI_STS

HOST_NOTIFY_STS

Access microcontroller 62h/66h No Yes MCSMI_EN MCSMI_STS

SLP_EN bit written to 1 No Yes SLP_SMI_EN=1 SLP_SMI_STS

SPI Command Completed No Yes See SPI section SPI_STS

Software Generated GPE Yes Yes S WGPE_EN=1 SWGPE_STS

USB Per-Port Registers Write Enable bit

changes to 1 No Yes INTEL_USB2_EN=1,

Write_Enable_SMI_Enable=1 INTEL_USB2_STS, Write

Enable Status

GPIO Lockdown Enable bit changes

from ‘1’ to ‘0’ No Yes GPIO_UNLOCK_SMI_EN=1 GPIO_UNLOCK_SMI_STS

VE Host Interface Yes Yes VEHCI_SCI_EN = 1

VEHCI_SMI_EN = 1 VEHCI_SCI_STS

VEHCI_SMI_STS

VE Intel ME Interface Yes Yes VEMCI_SCI_EN = 1

VEMCI_SMI_EN = 1 VEMCI_SCI_STS

VEMCI_SMI_STS

Intel ME Interface Yes Yes ME_SCI_EN = 1

ME_SMI_EN = 1 ME_SCI_STS

ME_SMI_STS

Classic USB Legacy logic (Port 64/60

rd/wr, End of pass-through) No Yes LEGACY_USB_EN = 1 LEGACY_USB_STS

RTC Update-in-pro gr ess No Yes see I/O Trap Register section RTC_UIP_SMI_STS

Table 5-29. Causes of Intel® Scalable Memory Interconnect (Intel® SMI) and SCI (Sheet

2 of 2)

Cause SCI SMI Additional Enables Where Reported

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 151

Datasheet

5.14.4.1 PCI Express* SCI

PCI Express* ports and the Processor (using DMI) have the ability to cause PME using

messages. When a PME message is received, PCH will set the PCI_EXP_STS bit. If the

PCI_EXP_EN bit is also set, the PCH can cause an SCI using the GPE1_STS register.

5.14.4.2 PCI Express* Hot-Plug

PCI Express* has a Hot-Plug mechanism and is capable of generating a SCI using the

GPE1 register. It is also capable of generating an Intel SMI. However, it is not capable of

generating a wak e ev ent.

5.14.5 C-States

PCH-based systems implement C-states by having the Processor control the states. The

chipset exchanges messages with the Processor as part of the C-state flow, but the

chipset does not directly control any of the Processor impacts of C-states, such as

voltage levels or Processor clocking. In addition to the new messages, the PCH also

provides additional information to the Processor using a sideband pin (PM_SYNC). All of

the legacy C-state related pins (STPCLK#, STP_CPU#, DPRS LP#, DPRSLPVR#, and so

forth) do not exist on PCH.

5.14.6 Sleep States

5.14.6.1 Sleep State Overview

The PCH directly supports different sleep states (S1–S5), which are entered by

methods such as setting the SLP_EN bit, or due to a Power Button press. The entry to

the Sleep states is based on several assumptions:

• The G3 state cannot be entered using any software mechanism. The G3 state

indicates a complete loss of power.

5.14.6.2 Initiating Sleep State

Sleep states (S1–S5) are initiated by:

• Masking interrupts, turning off all bus master enable bits, setting the desired type

in the SLP_TYP field, and then setting the SLP_EN bit. The hardw are then attempts

to gracefully put the system into the corresponding Sleep state.

• Pressing the PWRBTN# Signal for more than 4 seconds to cause a Power Button

Override event. In this case the transition to the S5 state is less graceful, since

there are no dependencies on DMI messages from the processor or on clocks other

than the RTC clock.

• Assertion of the THRMTRIP# signal will cause a transition to the S5 state. This can

occur when system is in S0 or S1 state.

• Shutdown by integrated manageability functions (ASF/Intel AMT)

• Internal watchdog timer timeout events

Functional Description

152 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.14.6.3 Exiting Sleep States

Sleep states (S1–S5) are exited based on Wake events. The Wake events forces the

system to a full on state (S0), although some non-critical subsystems might still be

shut off and have to be brought back manually. For example, the hard disk ma y be shut

off during a sleep state, and have to be enabled using a GPIO pin before it can be used.

Upon exit from software entered sleep states (that is, those initiated using the SLP_EN

bit) the WAK_STS bit is set. The possible causes of W ake Events (and their restrictions)

are shown in Table 5-31.

Table 5-30. Sleep Types

Sleep Type Comment

S1 System lowers the processor’s power consumption. No snooping is possible in this state.

S3 Asserts SLP_S3#. The SLP_S3# signal controls the power to non-critical circuits. Power is

only retained to devices needed to wake from this sleeping state, as well as to the memory.

S4 Asserts SLP_S3# and SLP_S4#. The SLP_S4# signal shuts off the power to the memory

subsystem. Only devices needed to wake from this state should be powered.

S5 Same power state as S4. asserts SLP_S3#, SLP_S4# and SLP_S5#.

Table 5-31. Causes of Wake Events (Sheet 1 of 2)

Cause How Enabled Wake from

S1, Sx

Wake from

Deep S4/S5

Wake from

S1, Sx After

Power Loss

(Note 1)

Wake from

“Reset” Types

(Note 2)

RTC Alarm Set RTC_EN bit in PM1_EN

Power Button Always enabled as Wake event. Y Y Y Y

GPI[15:0]

GPE0_EN register

Note: GPI’s that are in the

core well are not

capable of waking the

system from sleep

states when the core

well is not powered.

GPIO27 Set GP27_EN in GPE0_EN

LAN Will use PME#. Wake enable set

with LAN logic. YY

RI# Set RI_EN bit in GPE0_EN

Intel® High

Definition

Audio

Event sets PME_B0_STS bit;

PM_B0_EN must be enabled.

Can not wake from S5 state if it

was entered due to power failure

or power button override.

Primary PME# PME_B0_EN bit in GPE0_EN

Secondary

PME# Set PME_EN bit in GPE0_EN

PCI_EXP_WAK

E# PCI_EXP_WAKE bit. (Note 3) Y Y

SA TA Set PM E_EN bit in GPE0_EN

PCI_EXP PME

Message

Must use the PCI Express*

WAKE# pin rather than

messages for wake from S3, S4,

or S5.

S1 S1

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 153

Datasheet

Notes:

1. This column represents what the PCH would honor as wake events but there may be enabling

dependencies on the device side which are not enabled after a power loss.

2. Reset Types include: Power Button ov erride, Intel ME initiated power button override, Intel ME initiated

host partition reset with power down, Intel ME Watchdog Timer, SMBus unconditional power down,

Processor thermal trip, PCH catastrophic temperature event.

3. When the WAKE# pin is active and the PCI Express* device is enabled to wak e the system, the PCH wi ll

wake the platform.

4. SATA can only trigger a wake event in S1, but if PME is asserted prior to S3/S4/S5 entry and software

does not clear the PME_B0_STS, a wake event would still result.

It is important to understand that the various GPIs hav e different levels of functionality

when used as wake events. The GPIs that reside in the core power well can only

generate wake events from sleep states where the core well is powered. Also, only

certain GPIs are “ACPI Compliant,” meaning that their Status and Enable bits reside in

ACPI I/O space. Table 5-32 summarizes the use of GPIs as wake events.

The latency to exit the various Sleep states varies greatly and is heavily dependent on

power supply design, so much so that the exit latencies due to the PCH are

insignificant.

5.14.6.4 PCI Express* WAKE# Signal and PME Event Message

PCI Express* ports can wake the platform from any sleep state (S1, S3, S4, or S5)

using the WAKE# pin. WAKE# is treated as a wake event, but does not cause any bits

to go active in the GPE_STS register.

PCI Express* ports and the processor (using DMI) have the ability to cause PME using

messages. When a PME message is received, PCH will set the PCI_EXP_STS bit.

SMBALERT# Always enabled as Wake event. Y Y Y

SMBus Slave

Wake Message

(01h)

Wake/SMI# command always

enabled as a Wake event.

Note: SMBus Slave Message

can wake the system

from S1–S5, as well as

from S5 due to Power

Button Override.

YYY

SMBus Host

Notify

message

received

HOST_NOTIFY_WKEN bit SMBus

Slave Command register.

Reported in the SMB_WAK_STS

bit in the GPEO_STS register.

YYY

Intel® ME

Non-Maskable

Wake Always enabled as a wake ev ent. Y Y Y

Integrated

WOL Enable

Override

WOL Enable Override bit (in

Configuration Space). YYY

Table 5-31. Causes of Wake Events (Sheet 2 of 2)

Cause How Enabled Wake from

S1, Sx

Wake from

Deep S4/S5

Wake from

S1, Sx After

Power Loss

(Note 1)

Wake from

“Reset” Types

(Note 2)

Table 5-32. GPI Wake Events

GPI Power Well Wake From Notes

GPI[7:0] C ore S1 ACPI Compliant

GPI[15:8] Suspend S1–S5 ACPI Compliant

Functional Description

154 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.14.6.5 Sx-G3-Sx, Handling Power Failures

Depending on when the power failure occurs and how the system is designed, different

transitions could occur due to a power failure.

The AFTERG3_EN bit provides the ability to program whether or not the system should

boot once power returns after a power loss event. If the policy is to not boot, the

system remains in an S5 state (unless previously in S4). There are only three possible

events that will wake the system after a power failure.

1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low

(G3 state), the PWRBTN_STS bit is reset. When the PCH exits G3 after power

returns (RSMRST# goes high), the PWRBTN# signal is already high (because VCC-

standby goes high before RSMRST# goes high) and the PWRBTN_STS bit is 0.

2. RI#: RI# does not have an internal pull-up. Therefore, if this signal is enabled as a

wake event, it is important to keep this signal powered during the power loss

event. If this signal goes low (active), when power return s the RI_STS bit is set and

the system interprets that as a wake event.

3. RTC Alarm: The RT C_EN bit is in the R T C well and is preserved after a power loss.

Like PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low.

The PCH monitors both PCH_PWROK and RSMRST# to detect for power failures. If

PCH_PWROK goes low, the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is

set.

Note: Although PME_EN is in the RTC well, this signal cannot wake the system after a power

loss. PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#.

Notes:

1. Entry state to Deep S4/S5 is preserve d through G3 allowing resume from Deep S4/S5 to take

appropriate path (that is, return to S4 or S5).

5.14.6.6 Deep S4/S5

To minimize power consumption while in S4/S5, the PCH supports a lower power, lower

featured version of these power states known as Deep S4/S5. In these Deep S4/S5

states, the Suspend wells are powered off, while the new Deep S4/S5 Well (DSW)

remains powered. A limited set of wake events are supported by the logic located in the

DSW.

Table 5-33. Transitions Due to Power Failure

State at Power Failure AFTERG3_EN bit Transition When Power Returns

S0, S1, S3 1

0S5

S4 1

0S4

S5 1

0S5

Deep S4/S5 1

0Deep S4/S51

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 155

Datasheet

5.14.6.6.1 Entry Into Deep S4/S5

A combination of conditions is required for entry into Deep S4/S5.

All of the following must be met:

— Intel ME in Moff

— AND ((DPS4_EN_AC AND S4) OR (DPS5_EN_AC AND S5))

The PCH also performs a SUSWARN#/SUSACK# handshake to ensure the platform is

ready to enter Deep S4/S5. The PCH asserts SUSW ARN# as notification that it is about

to enter Deep S4/S5. Before the PCH proceeds and asserts SLP_SUS#, the PCH waits

for SUSACK# to assert.

5.14.6.6.2 Exit from Deep S4/S5

While in Deep S4/S5, the PCH monitors and responds to a limited set of wake events

(RTC Alarm, Power Button, and GPIO27). Upon sensing an enabled Deep S4/S5 wake

event, the PCH brings up the Suspend well by deasserting SLP_SUS#.

5.14.7 Event Input Signals and Their Usage

The PCH has various input signals that trigger specific events. This section describes

those signals and how they should be used.

5.14.7.1 PWRBTN# (Power Button)

The PCH PWRBTN# signal operates as a “Fixed Power Button” as described in the

Advanced Configuration and Power Interface, Version 2.0b. PWRBTN# signal has a 16

ms de-bounce on the input. The state transition descriptions are included in Table 5-36.

Note that the transitions start as soon as the PWRBTN# is pressed (but after the

debounce logic), and does not depend on when the Power Button is released.

Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width

(if enabled), the Po wer Button is not a wak e event. R e fer to the following P ower Button

Override Function section for further detail.

Table 5-34. Supported Deep S4/S5 Policy Configurations

Configuration DPS4_EN_DC DPS4_EN_AC DPS5_EN_DC DPS5_EN_AC

1: Enabled in S5 0011

2: Enabled in S4 and S5 1111

3: Deep S4 / S5 disabled 0000

Table 5-35. Deep S4/S5 Wake Events

Event Enable

RTC Alarm RTC_DS_WAKE_DIS (RCBA+3318h:Bit 21)

Power Button Always enabled

GPIO27 GPIO27_EN (PMBASE+28h:Bit 35)

Functional Description

156 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Power Button Override Function

If PWRBTN# is observ ed active for at least four consecutive seconds, the state machine

unconditionally transitions to the G2/S5 state or Deep S4/S5, regardless of present

state (S0–S4), even if the PCH PWROK is not active. In this case, the transition to the

G2/S5 state or Deep S4/S5 does not depend on any particular response from the

processor (such as, a DMI Messages), nor any similar dependency from any other

subsystem.

The PWRBTN# status is readable to check if the button is currently being pressed or

has been released. The status is taken after the de-bounce, and is readable using the

PWRBTN_LVL bit.

Note: The 4-second PWRBTN# assertion should only be used if a system lock-up has

occurred. The 4-second timer starts counting when the PCH is in a S0 state. If the

PWRBTN# signal is asserted and held active when the system is in a suspend state

(S1–S5), the assertion causes a wake event. Once the system has resumed to the S0

state, the 4-second timer starts.

Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width

(if enabled by D31:F0:A4h Bit 3), the Power Button is not a wake event. As a result, it

is conceivable that the user will press and continue to hold the P ower Button waiting for

the system to awak e. Since a 4-second press of the Power Button is already defined as

an Unconditional Power down, the power button timer will be forced to inactive while

the power-cycle timer is in progress. Once the power-cycle timer has expired, the

Power Button awakes the system. Once the minimum SLP_S4# power cycle expires,

the Power Button must be pressed for another 4 to 5 seconds to create the Override

condition.

Sleep Button

The Advanced Configuration and Power Interface, Version 2.0b defines an optional

Sleep button. It differs from the power button in that it only is a request to go from S0

to S1–S4 (not S5). Also , in an S5 state, the Power Button can wak e the system, but the

Sleep Button cannot.

Although the PCH does not include a specific signal designated as a Sleep Button, one

of the GPIO signals can be used to create a “Control Method” Sleep Button. See the

Advanced Configuration and Power Interface, Version 2.0b for implementation details.

Table 5-36. Transitions Due to Power Button

Present

State Event Transition/Action Comment

S0/Cx PWRBTN# goes low Intel SMI or SCI generated

(depending on SCI_EN,

PWRBTN_EN and GLB_SMI_EN)

Software typically initiates a

Sleep state

S1–S5 PWRBTN# goes low Wake Event. Transitions to S0

state Standard wakeup

G3 PWRBTN# pressed None No effect since no power

Not latched nor detected

S0–S4 PWRBTN# held low for

at least 4 consecutive

seconds

Unconditional transition to S5

state and if Deep S4/S5 is

enabled and conditions are met

per Section 5.14.6.6, the

system will then transition to

Deep S4/S5.

No dependence on processor

(DMI Messages) or any other

subsystem

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 157

Datasheet

5.14.7.2 RI# (Ring Indicator)

The Ring Indicator can cause a wake event (if enabled) from the S1–S5 states.

Table 5-37 shows when the wake event is gener ated or ignored in different states. If in

the G0/S0/Cx states, the PCH generates an interrupt based on RI# active, and the

interrupt will be set up as a Break event.

Note: Filtering/Debounce on RI# will not be done in PCH. Can be in modem or external.

5.14.7.3 PME# (PCI Power Management Event)

The PME# signal comes from a PCI device to request that the system be restarted. The

PME# signal can generate an SMI#, SCI, or optionally a Wake event. The event occurs

when the PME# signal goes from high to low. No event is caused when it goes from low

to high.

There is also an internal PME_B0 bit. This is separate from the external PME# signal

and can cause the same effect.

5.14.7.4 SYS_RESET# Signal

When the SYS_RESET# pin is detected as active after the 16 ms debounce logic, the

PCH attempts to perform a “gra ceful” reset, by waiting up to 25 ms for the SMBus to go

idle. If the SMBus is idle when the pin is detected active, the reset occurs immediately;

otherwise, the counter starts. If at any point during the count the SMBus goes idle the

reset occurs. If, however, the counter expires and the SMBus is still active, a reset is

forced upon the system even though activity is still occurring.

Once the reset is asserted, it remains asserted for 5 to 6 ms regardless of whether the

SYS_RESET# input remains asserted or not. It cannot occur again until SYS_RESET#

has been detected inactive after the debounce logic, and the system is back to a full S0

state with PLTRST# inactive. Note that if bit 3 of the CF9h I/O register is set then

SYS_RESET# will result in a full power cycle reset.

5.14.7.5 THRMTRIP# Signal

If THRMTRIP# goes active, the processor is indicating an overheat condition, and the

PCH immediately transitions to an S5 state, driving SLP_S3#, SLP_S4#, SLP_S5# low ,

and setting the CTS bit. The transition looks like a power button override.

When a THRMTRIP# event occurs, the PCH will power down immediately without

following the normal S0 -> S5 path. The PCH will immediately drive SLP_S3#,

SLP_S4#, and SLP _S5# low after sampling THRMTRIP# active.

If the processor is running extremely hot and is heating up, it is possible (although v ery

unlikely) that components around it, such as the PCH, are no longer executing cycles

properly. Therefore, if THRMTRIP# goes active, and the PCH is relying on state machine

logic to perform the power down, the state machine may not be working, and the

system will not power down.

The PCH provides filtering for short low glitches on the THRMTRIP# signal in order to

prevent erroneous system shut downs from noise. Glitches shorter than 25 nsec are

ignored.

Table 5-37. Transitions Due to RI# Signal

Present State Event RI_EN Event

S0 RI# Active X Ignored

S1–S5 RI# Active 0

1Ignored

Wake Event

Functional Description

158 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

During boot, THRMTRIP# is ignored until SLP_S3#, PCH_PWROK, and PLTRST# are all

‘1’. During entry into a powered-down state (due to S3, S4, S5 entry, power cycle

reset, etc.) THRMTRIP# is ignored until either SLP_S3# = 0, or PCH_PWROK = 0, or

SYS_PWROK= 0.

Note: A thermal trip event will:

• Clear the PWRBTN_STS bit

• Clear all the GPE0_EN register bits

• Clear the SMB_WAK_STS bit only if SMB_SAK_STS was set due to SMBus slave

receiving message and not set due to SMBAlert

5.14.8 ALT Access Mode

Before entering a low power state, several registers from powered down parts may

need to be saved. In the majority of cases, this is not an issue, as registers have read

and write paths. However, several of the ISA compatible registers are either read only

or write only. To get data out of write-only registers, and to restore data into read-only

registers, the PCH implements an ALT access mode.

If the ALT access mode is entered and exited after reading the registers of the PCH

timer (8254), the timer starts counting faster (13.5 ms). The following steps listed

below can cause problems:

1. BIOS enters ALT access mode for reading the PCH timer related registers.

2. BIOS exits ALT access mode.

3. BIOS continues through the execution of other needed steps and passes control to

the operating system.

After getting control in step #3, if the operating system does not reprogr am the system

timer again, the timer ticks may be happening faster than expected. For example

Microsoft MS-DOS* and its associated software assume that the system timer is

running at 54.6 ms and as a result the time-outs in the software may be happening

faster than expected.

Operating systems (for example, Microsoft Windows* 98 and Windows* 2000)

reprogram the system timer and therefore do not encounter this problem.

For other operating systems (for example, Microsoft MS-DOS*) the BIOS should

restore the timer back to 54.6 ms before pa ssing control to the operating system. If the

BIOS is entering ALT access mode before entering the suspend state it is not necessary

to restore the timer contents after the exit from ALT access mode.

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 159

Datasheet

5.14.8.1 Write Only Registers with Read Paths in ALT Access Mode

The registers described in Table 5-38 have read paths in ALT access mode. The access

number field in the table indicates which register will be returned per access to that

port.

Table 5-38. Write Only Registers with Read Paths in ALT Access Mode (Sheet 1 of 2)

Restore Data Restore Data

I/O

Addr

# of

Rds Access Data I/O

Addr

# of

Rds Access Data

00h 2 1DMA Chan 0 base address low

byte

40h 7

1 Timer Counter 0 status, bits [5:0]

2DMA Chan 0 base address high

byte 2Timer Counter 0 base count low

byte

01h 2 1 DMA Chan 0 base count low byte 3 Timer Counter 0 base count high

byte

2 DMA Chan 0 base count high b yte 4 Timer Counter 1 base count low

byte

02h 2 1DMA Chan 1 base address low

byte 5Timer Counter 1 base count high

byte

2DMA Chan 1 base address high

byte 6Timer Counter 2 base count low

byte

03h 2 1 DMA Chan 1 base count low byte 7 Timer Counter 2 base count high

byte

2 DMA Chan 1 base count high byte 41h 1 Timer Counter 1 status, bits [5:0]

04h 2 1DMA Chan 2 base address low

byte 42h 1 Timer Counter 2 status, bits [5:0]

2DMA Chan 2 base address high

byte 70h 1 Bit 7 = NMI Enable,

Bits [6:0] = RTC Address

05h 2 1 DMA Chan 2 base count low byte C4h 2 1 DMA Chan 5 base address low byte

2 DMA Chan 2 base count high b yte 2 DMA Chan 5 base address high

byte

06h 2 1DMA Chan 3 base address low

byte C6h 2 1 DMA Chan 5 base count low byte

2DMA Chan 3 base address high

byte 2 DMA Chan 5 bas e count high byte

07h 2 1 DMA Chan 3 base count low byte C8h 2 1 DMA Chan 6 base address low byte

2 DMA Chan 3 base count high b yte 2 DMA Chan 6 base address high

byte

08h 6

1 DMA Chan 0–3 Command2

CAh 2 1 DMA Chan 6 base count low byte

2 DMA Chan 0–3 Request 2 DMA Chan 6 base count high byte

3DMA Chan 0 Mode:

Bits(1:0) = 00 CCh 2 1 DMA Chan 7 base address low byte

4DMA Chan 1 Mode:

Bits(1:0) = 01 2DMA Chan 7 base address high

byte

5DMA Chan 2 Mode:

Bits(1:0) = 10 CEh 2 1 DMA Chan 7 base count low byte

6DMA Chan 3 Mode: Bits(1:0) =

11. 2 DMA Chan 7 base count high byte

Functional Description

160 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Notes:

1. The OCW1 register must be read before entering ALT access mode.

2. Bits 5, 3, 1, and 0 return 0.

5.14.8.2 PIC Reserved Bits

Many bits within the PIC are reserved, and must ha ve certain values written in order for

the PIC to operate properly. Therefore , there is no need to return these values in ALT

access mode. When reading PIC registers from 20h and A0h, the reserved bits shall

return the values listed in Table 5-39.

20h 12

1 PIC ICW2 of Master controller

D0h 6

1 DMA Chan 4–7 Command2

2 PIC ICW3 of Master controller 2 DMA Chan 4–7 Request

3 PIC ICW4 of Master controller 3 DMA Chan 4 Mode: Bits(1:0) = 00

4 PIC OCW1 of Master controller14 DMA Chan 5 Mode: Bits(1:0) = 01

5 PIC OCW2 of Master controller 5 DMA Chan 6 Mode: Bits(1:0) = 10

6 PIC OCW3 of Master controller 6 DMA Chan 7 Mode: Bits(1:0) = 11.

7 PIC ICW2 of Slave controller

8 PIC ICW3 of Slave controller

9 PIC ICW4 of Slave controller

10 PIC OCW1 of Slave controller1

11 PIC OCW2 of Slave controller

12 PIC OCW3 of Slave controller

Table 5-38. Write Only Registers with Read Paths in ALT Access Mode (Sheet 2 of 2)

Restore Data Restore Data

I/O

Addr

# of

Rds Access Data I/O

Addr

# of

Rds Access Data

Table 5-39. PIC Reserved Bits Return Values

PIC Reserved Bits Value Returned

ICW2(2:0) 000

ICW4(7:5) 000

ICW4(3:2) 00

ICW4(0) 0

OCW2(4:3) 00

OCW3(7) 0

OCW3(5) Reflects bit 6

OCW3(4:3) 01

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 161

Datasheet

5.14.8.3 Read Only Registers with Write Paths in ALT Access Mode

The registers described in Table 5-40 have write paths to them in ALT access mode.

Software restores these values after returning from a powered down state. These

registers must be handled special by software. When in normal mode, writing to the

base address/count register also writes to the current address/count register.

Therefore, the base address/count must be written first, then the part is put into ALT

access mode and the current address/count register is written.

5.14.9 System Power Supplies, Planes, and Signals

5.14.9.1 Power Plane Control with SLP_S3#,

SLP_S4#, SLP_S5#, SLP_A# and SLP_LAN#

The SLP_S3# output signal can be used to cut power to the system core supply, since it

only goes active for the Suspend-to-RAM state (typically mapped to ACPI S3). Power

must be maintained to the PCH suspend well, and to any other circuits that need to

generate Wake signals from the Suspend-to-RAM state. During S3 (Suspend-to-RAM)

all signals attached to powered down plans will be tri-stated or driv en low, unless they

are pulled using a pull-up resistor.

Cutting power to the core may be done using the power supply, or by external FETs on

the motherboard.

The SLP_S4# or SLP_S5# output signal can be used to cut power to the system core

supply, as we ll as power to the system memory, since the context of the system is

saved on the disk. Cutting power to the memory may be done using the power supply,

or by external FETs on the motherboard.

The SLP_S4# output signal is used to re move power to additional subsystems that are

powered during SLP_S3#.

SLP_S5# output signal can be used to cut power to the system core supply, as well as

power to the system memory, since the context of the system is saved on the disk.

Cutting power to the memory may be done u sing the power supply, or by external FETs

on the motherboard.

SLP_A# output signal can be used to cut power to the Intel ME, Clock chip and SPI

flash on a platform that supports the M3 state (for example, certain power policies in

Intel AMT).

SLP_LAN# output signal can be used to cut power to the external Intel 82579 Gbe PHY

device.

5.14.9.2 SLP_S4# and Suspend-To-RAM Sequencing

The system memory suspend voltage regulator is controlled by the Glue logic. The

SLP_S4# signal should be used to remove power to system memory rather than the

SLP_S5# signal. The SLP_S4# logic in the PCH provides a mechanism to fully cycle the

power to the DRAM and/or detect if the power is not cycled for a minimum time.

Note: To utilize the minimum DRAM power-down feature that is enabled by the SLP_S4#

Assertion Stretch Enable bit (D31:F0:A4h bit 3), the DRAM power must be controlled

by the SLP_S4# signal.

Table 5-40. Register Write Accesses in ALT Access Mode

I/O Address Register Write Value

08h DMA Status Register for channels 0–3.

D0h DMA Status Register for channels 4–7.

Functional Description

162 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.14.9.3 PCH_PWROK Signal

When asserted, PCH_PWROK is an indication to the PCH that its core well power rails

have been powered and stable. PCH_PWROK can be driven asynchronously. When

PCH_PWROK is low, the PCH asynchronously asserts PLTR ST#. PCH_PWROK must not

glitch, even if RSMRST# is low.

It is required that the power associated with PCI/PCIe have been va lid for 99 ms prior

to PCH_PWROK assertion in order to comply with the 100 ms PCI 2.3 / PCIe 1.1

specification on PLTRST# deassertion.

Note: SYS_RESET# is recommended for implementing the system reset button. This saves

external logic that is needed if the PCH_PWROK input is used. Additionally, it allows for

better handling of the SMBus and processor resets and avoids improperly reporting

power failures.

5.14.9.4 SLP_LAN# Pin Behavior

The following table summarizes SLP_LAN# pin behavior.

5.14.9.5 RTCRST# and SRTCRST#

RTCRST# is used to reset PCH registers in the RTC Well to their default value. If a

jumper is used on this pin, it should only be pulled low when system is in the G3 state

and then replaced to the default jumper position. Upon booting, BIOS should recognize

that RTCRST# was asserted and clear internal PCH registers accordingly. It is

imperative that this signal not be pulled low in the S0 to S5 states.

SR TC RST# is used to reset portions of the Intel Management Engine and should not be

connected to a jumper or button on the platform. The only time this signal gets

asserted (driven low in combination with RTCRST#) should be when the coin cell

battery is removed or not installed and the platform is in the G3 state. Pulling this

signal low independently (without RTCRST# also being driven low) may cause the

platform to enter an indeterminate state. Similar to RTCRST#, it is imperative that

SRTCRST# not be pulled low in the S0 to S5 states.

See Figure 2-2 which demonstrates the proper circuit connection of these pins.

Table 5-41. SLP_LAN# Pin Behavior

Pin Functionality

(Determined by

soft strap)

SLP_LAN Default

Value Bit

GPIO29 Input /

Output

(Determined by

GP_IO_SEL bit)

Pin Value In S0 or

Value in S3-S5/

Moff

SLP_LAN#

0 (Default) In (Default) 1 0

Out 1 Depends on GPIO29

output data value

1In (Default) 1 1

Out 1 Depends on GPIO29

output data value

GPIO29

0 (Default) In Z (tri-state) 0

1 In Z (tri-state) 1

N/A Out Depends on GPIO29

output da ta value Depends on GPIO29

output data value

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 163

Datasheet

5.14.9.6 SUSWARN#/GPIO30 Pin Behavior

Table 5-42 summarize SUSWARN#/GP IO3 0 pin behavior.

Notes:

1. If entering Deep S4/S5, pin will assert and become undriven (“Off”) when suspend well drops upon Deep S4/S5 entry.

5.14.10 Legacy Power Management Theory of Operation

Instead of relying on ACPI software, legacy power management uses BIOS and various

hardware mechanisms. The scheme relies on the concept of detecting when individual

subsystems are idle, detecting when the whole system is idle, and detecting when

accesses are attempted to idle subsystems.

However, the operating system is assumed to be at least APM enabled. Without APM

calls, there is no quick way to know when the system is idle between keystrokes. The

PCH does not support burst modes.

5.14.10.1 APM Power Management

The PCH has a timer that, when enabled by the 1MIN_EN bit in the Intel SMI Control

and Enable register, generates an Intel SMI once per minute. The Intel SMI handler can

check for system activity by reading the DEVTRAP_STS register. If none of the system

bits are set, the Intel SMI handler can increment a software counter. When the counter

reaches a sufficient number of consecutive minutes with no activity, the Intel SMI

handler can then put the system into a lower power state.

If there is activity, various bits in the DEVTRAP_STS register will be set. Software clears

the bits by writing a 1 to the bit position.

The DEVTRAP_STS register allows for monitoring various internal devices, or Super I/O

devices (SP, PP, FDC) on LPC or PCI, keyboard controller accesses, or audio functions

on LPC or PCI. Other PCI activity can be monitored by checking the PCI interrupts.

5.14.11 Reset Behavior

When a reset is triggered, the PCH will send a warning message to the Processor to

allow the Processor to attempt to complete any outstanding memory cycles and put

memory into a safe state before the platform is reset. When the Processor is ready, it

will send an acknowledge message to the PCH. Once the message is received the PCH

asserts PLTRST#.

The PCH does not require an acknowledge message from the processor to trigger

PLTRST#. A global reset will occur after 4 seconds if an acknowledge from the

processor is not received.

When the PCH causes a reset by asserting PLTRST# its output signals will go to their

reset states as defined in Chapter 3.

Table 5-42. SUSWARN#/GPIO30 Steady State Pin Behavior

Deep S4/S5

(Supported/Not-

Supported)

GPIO30 Input/

Output

(Determine by

GP_IO_SEL bit)

Pin Value in

Sx/Moff

Pin Value in

Sx/M3

Pin Value in

Deep S4/

SUSWARN# Suppo rted Native 1 1 (Note 1) 1 Off

GPIO30

Don't Care IN H igh-Z High-Z High-Z Off

Don't Care OUT Depends on

GPIO30 output

data value

Depends on

GPIO30 output

data value

Depends on

GPIO30

output data

value

Off

Functional Description

164 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

A reset in which the host platform is reset and PLTRST# is asserted is called a Host

Reset or Host Partition Reset. Depending on the trigger a host reset may also result in

power cycling see Table 5-43 for details. If a host reset is triggered and the PCH times

out before receiving an acknowledge message from the Processor a Global Reset with

power cycle will occur.

A reset in which the host and Intel ME partitions of the platform are reset is called a

Global Reset. During a Global Reset, all PCH functionality is reset except RTC Power

W ell backed information and Suspend well status, configur ation, and functional logic for

controlling and reporting the reset. Intel ME and Host power back up after the power

cycle period.

Straight to S5 is another reset type where all power wells that are controlled by the

SLP_S3#, SLP_S4#, and SLP_A# pins, as well as SLP_S5# and SLP_LAN# (if pins are

not configured as GPIOs), are turned off. All PCH functionality is reset except RTC

Power Well backed information and Suspend well status, configuration, and functional

logic for controlling and reporting the reset. The host stays there until a valid wake

event occurs.

Table 5-43 shows the various reset triggers:

Table 5-43. Causes of Host and Global Resets (Sheet 1 of 2)

Trigger

Host Reset

without

Power

Cycle1

Host Reset

with

Power

Cycle2

Global Reset

with

Power

Cycle3

Straight to

S56 (Host

Stays

there)

Write of 0Eh to CF9h (RST_CNT Register) No Yes No (Note 4)

Write of 06h to CF9h (RST_CNT Register) Yes No No (Note 4)

SYS_RESET# Asserted and CF9h (RST_CNT

SMBus Slave Message received for Reset with

Power Cycle No Yes No (Note 4)

SMBus Slave Message received for R eset without

Power Cycle Yes No No (Note 4)

SMBus Slave Message received for unconditional

Power Down No No No Yes

TCO Watchdog Timer reaches zero two times Yes No No (Note 4)

Power Failure: PWROK signal goes inactive in

S0/S1 or DPWROK drops No No Yes

SYS_PWROK Failure: SYS_PWROK signal goes

inactive in S0/S1 No No Yes

Processor Thermal Trip (THRMTRIP#) causes

transition to S5 and reset asserts No No No Yes

PCH internal thermal sensors signals a

catastrophic temperature condition No No No Yes

Power Button 4 second override causes

transition to S5 and reset asserts No No No Yes

Special shutdown cycle from processor causes

CF9h-like PLTRST# and CF9h (RST_CNT

Special shutdown cycle from processor causes

CF9h-like PLTRST# and CF9h (RST_CNT

Intel ME Triggered Host Reset without power

cycle Yes No No (Note 4)

Intel ME Triggered Host Reset with power cycle No Yes No (Note 4)

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 165

Datasheet

5.15 System Management (D31:F0)

The PCH provides various functions to make a system easier to manage and to lower

the Total Cost of Ownership (TCO) of the system. Features and functions can be

augmented using external A/D converters and GPIO, as well as an external

microcontroller.

The following features and functions are supported by the PCH:

• Processor present detection

— Detects if processor fails to fetch the first instruction after reset

• Various Error detection (such as ECC Errors) indicated by host controller

— Can generate SMI#, SCI, SERR, NMI, or TCO interrupt

• Intruder Detect input

— Can generate TCO interrupt or SMI# when the system cover is removed

— INTRUDER# allowed to go active in any power state, including G3

• Detection of bad BIOS Flash (FWH or Flash on SPI) programming

— Detects if data on first read is FFh (indicates that BIOS flash is not

programmed)

• Ability to hide a PCI device

— Allows software to hide a PCI device in terms of configuration space through

the use of a device hide register. (See Section 10.1.45)

Note: Voltage ID from the processor can be read using GPI signals.

Intel ME Triggered Power Button Override No No No Yes

Intel ME Watchdog Timer Timeout No No No Yes

Intel ME Triggered Global Reset No No Yes

Intel ME Triggered Host Reset with power down

(host stays there) No Yes (Note 5) No (Note 4)

PLTRST# Entry Time-out No No Yes

S3/4/5 Entry Timeout No No No Yes

PROCPWRGD Stuck Low No No Yes

Power Management Watchdog Timer No No No Yes

Intel ME Hardware Uncorrectable Error No No No Yes

Notes:

1. The PCH drops this type of reset request if received while the system is in S3/S4/S5.

2. PCH does not drop this type of reset request if received while system is in a software-entered S3/S4/

S5 state. However, the PCH is allowed to perform the reset without executing the RESET_WARN

protocol in these states.

3. The PCH does not send warning message to processor, reset occurs without delay.

4. Trigger will result in Global Reset with power cycle if the acknowledge message is not received by the

PCH.

5. The PCH waits for enabled wake event to complete reset.

6. Upon entry to S5, if Deep S4/S5 is enabled and conditions are met per Section 5.14.6.6, the system

will transition to Deep S4/S5.

Table 5-43. Causes of Host and Global Resets (Sheet 2 of 2)

Trigger

Host Reset

without

Power

Cycle1

Host Reset

with

Power

Cycle2

Global Reset

with

Power

Cycle3

Straight to

S56 (Host

Stays

there)

Functional Description

166 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.15.1 Theory of Operation

The System Management functions are designed to allow the system to diagnose failing

subsystems. The intent of this logic is that some of the system management

functionality can be provided without the aid of an external microcontroller.

5.15.1.1 Detecting a System Lockup

When the processor is reset, it is expected to fetch its first instruction. If the processor

fails to fetch the first instruction after reset, the TCO timer times out twice and the PCH

asserts PLTRST#.

5.15.1.2 Handling an Intruder

The PCH has an input signal, INTRUDER#, that can be attached to a switch that is

activated by the system’ s case being open. This input has a two R TC clock debounce. If

INTRUDER# goes active (after the debouncer), this will set the INTRD_DET bit in the

TCO2_STS register. The INTRD_SEL bits in the TCO_CNT register can enable the PCH to

cause an SMI# or interrupt. The BIOS or interrupt handler can then cause a transition

to the S5 state by writing to the SLP_EN bit.

The software can also directly read the status of the INTRUDER# signal (high or low) by

clearing and then reading the INTRD_DET bit. This allows the signal to be used as a GPI

if the intruder function is not required.

If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written

as a 1, then the INTRD_DET signal will go to a 0 when INTRUDER# input signal goes

inactive. Note that this is slightly different than a classic sticky bit, since most sticky

bits would remain active indefinitely when the signal goes active and would

immediately go inactive when a 1 is written to the bit.

Note: The INTRD_DET bit resides in the PCH’ s R T C well, and is set and cleared synchronou sly

with the RTC clock. Thus, when software attempts to clear INTRD_DET (by writing a 1

to the bit location) there may be as much as two R T C clocks (about 65 µs) delay before

the bit is actually cleared. Also, the INTRUDER# signal should be asserted for a

minimum of 1 ms to ensure that the INTRD_DET bit will be set.

Note: If the INTRUDER# signal is still active when software attempts to clear the INTRD_DET

bit, the bit remains set and the Intel SMI is generated again immediately. The Intel SMI

handler can clear the INTRD_SEL bits to avoid further Intel SMIs. However, if the

INTRUDER# signal goes inactive and then active again, there will not be further Intel

SMIs, since the INTRD_SEL bits would select that no SMI# be generated.

5.15.1.3 Detecting Improper Flash Programming

The PCH can detect the case where the BIOS flash is not programmed. This results in

the first instruction fetched to have a value of FFh. If this occurs, the PCH sets the

BAD_BIOS bit. The BIOS flash may reside in FWH or flash on the SPI bus.

5.15.1.4 Heartbeat and Event Reporting using SMLink/SMBus (SRV/WS SKUs

Only)

Heartbeat and event reporting using SMLink/SMBus is no longer supported. The Intel

AMT logic in PCH can be p rogr ammed to gener a te an interrupt to the Intel ME when an

event occurs. The Intel ME will poll the TCO registers to gather appropriate bits to send

the event message to the Gigabit Ethernet controller, if Intel ME is programmed to do

so.

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 167

Datasheet

5.15.2 TCO Modes

5.15.2.1 TCO Legacy/Compatible Mode

In TCO Legacy/Compatible mode, only the host SMBus is utilized. The TCO Slave is

connected to the host SMBus internally by default. In this mode, the Intel ME SMBus

controllers are not used and should be disabled by soft strap.

In TCO Legacy/Compatible mode the PCH can function directly with an external LAN

controller or equivalent external LAN controller to report messages to a network

management console without the aid of the system processor. This is crucial in cases

where the processor is malfunctioning or cannot function due to being in a low-power

state. Table 5-44 includes a list of events that will report messages to the network

management console.

Note: The GPIO11/SMBALERT# pin will trigger an event message (when enabled by the

GPIO11_ALERT_DISABLE bit) regardless of whether it is configured as a GPI or not.

Figure 5-7. TCO Legacy/Compatible Mode SMBus Configuration

Host SMBus

TCO Slave

SPD

(Slave) uCtrl

Legacy Sensors

(Master or Slave

with ALERT)

TCO Legacy/Compatible Mode

SMBus

Intel ME SMBus

Controller 3 X

XPCI/PCIe*

Device

3rd Party

NIC

PCH

Intel ME SMBus

Controller 1

Intel ME SMBus

Controller 2

Table 5-44. Event Transitions that Cause Messages

Event Assertion? Deassertion? Comments

INTRUDER# pin yes no Must be in “S1 or hung S0” state

THRM# pin yes yes

Must be in “S1 or hung S0” state. Note that

the THRM# pin is isolated when the core

power is off, thus preventing this event in S3-

S5.

Watchdog Timer Expired yes no (NA) “S1 or hung S0” state entered

GPIO[11]/SMBALERT#

pin yes yes Must be in “S1 or hung S0” state

BATLOW# yes yes Must be in “S1 or hung S0” state

Functional Description

168 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.15.2.2 Advanced TCO Mode

PCH supports the Advanced TCO mode in which SMLink0 and SMLink1 are used in

addition to the host SMBus. See Figure 5-8 for more details. In this mode, the Intel ME

SMBus controllers must be enabled by soft strap (*TCO Slave Select) in the flash

descriptor.

The SMLink0 is dedicated to integrated LAN use and when an Intel PHY 82579 is

connected to SMLink0, a soft strap must be set to indicate that the PHY is connected to

SMLink0. The interface will be running at the frequency of 300 KHz - 400 KHz

depending on different factors such as board routing or bus loading when the F ast Mode

is enabled using a soft strap.

Note: With Intel SPS FW, the SMLink0 can also be used with BMC. However, this precludes

use of the Intel PHY 82579.

SMLink1 is dedicated to Embedded Controller (EC) or Baseboard Management

Controller (BMC) use. In the case where a BMC is connected to SMLink1, the BMC

communicates with Intel ME through Intel ME SMBus connected to SMLink1. The host

and TCO slave communicated with BMC through SMBus.

Figure 5-8. Advanced TCO Mode

Host SMBus

TCO S lave

SPD

(Slave)

Legacy Sensors

(Master or Slave

with ALERT)

Advanced TC O M ode

SMBus

SMLink0

Inte l M E S M Bu s

Controller 3 EC or

BMC

In t el

82579

SMLink1

PCH

Inte l M E S M B u s

C on troller 2

Inte l M E S M B u s

C on troller 1 P C I/P C Ie*

Device

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 169

Datasheet

5.16 General Purpose I/O (D31:F0)

The PCH contains up to 70 General Purpose Input/Output (GPIO) signals. Each GPIO

can be configured as an input or output signal. The number of inputs and outputs

varies depen ding on the configur ation. Below is a brief summary of new GPIO features.

— Capability to mask Suspend well GPIOs from CF9h events configured using

GP_RST_SEL registers)

— Added capability to program GPIO prior to switching to output

5.16.1 Power Wells

Some GPIOs exist in the suspend power plane. Care must be taken to make sure GPIO

signals are not driven high into powered-down planes. Some PCH GPIOs may be

connected to pins on devices that exist in the core well. If these GPIOs are outputs,

there is a danger that a loss of core power (PCH_PWROK low) or a Power Button

Override event results in PCH driving a pin to a logic 1 to another device that is

powered down.

5.16.2 SMI# SCI and NMI Routing

The routing bits for GPIO[15:0] allow an input to be routed to SMI#, SCI, NMI or

neither. Note that a bit can be routed to either an SMI# or an SCI, but not both.

5.16.3 Triggering

GPIO[15:0] have “sticky” bits on the input. Refer to the GPE0_STS register and the

ALT_GPI_SMI_STS register. As long as the signal goes active for at least 2 clock cycles,

the PCH keeps the sticky status bit active. The active level can be selected in the

GP_INV register. This does not apply to GPI_NMI_STS residing in GPIO IO space.

If the system is in an S0 or an S1 state, the GPI inputs are sampled at 33 MHz, so the

signal only needs to be active for about 60 ns to be latched. In the S3–S5 states, the

GPI inputs are sampled at 32.768 kHz, and thus must be active for at least 61

microseconds to be latched.

Note: GPIs that are in the core well are not capable of waking the system from sleep states

where the core well is not powered.

If the input signal is still active when the latch is cleared, it will again be set. Another

edge trigger is not required. This makes these signals “level” triggered inputs.

5.16.4 GPIO Registers Lockdown

The following GPIO registers are locked down when the GPIO Lockdown Enable (GLE)

bit is set. The GLE bit resides in D31:F0:GPIO Control (GC) register.

• Offset 00h: GPIO_USE_SEL[31:0]

• Offset 04h: GP_IO_SEL[31:0]

• Offset 0Ch: GP_LVL[31:0]

• Offset 28h: GPI_NMI_EN[15:0]

• Offset 2Ch: GPI_INV[31:0]

• Offset 30h: GPIO_USE_SEL2[63:32]

• Offset 34h: GPI_IO_SEL2[63:32]

• Offset 38h: GP_LVL2[6 3:32]

• Offset 40h: GPIO_USE_SEL3[95:64]

Functional Description

170 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

• Offset 44h: GPI_IO_SEL3[95:64]

• Offset 48h: GP_LVL3[95:64]

• Offset 60h: GP_RST_ SEL[31:0]

• Offset 64h: GP_RST_ SEL2[63:32]

• Offset 68h: GP_RST_ SEL3[95:64]

Once these registers are locked down, they become Read-Only registers and any

software writes to these registers will have no effect. To unlock the registers, the GPIO

Lockdown Enable (GLE) bit is required to be cleared to ‘0’. When the GLE bit changes

from a ‘1’ to a ‘0’ a System Management Interrupt (SMI#) is generated if enabled.

Once the GPIO_UNLOCK_SMI bit is set, it can not be changed until a PLTRST# occurs.

This ensures that only BIOS can change the GPIO configuration. If the GLE bit is

cleared by unauthorized software, BIOS will set the GLE bit again when the SMI# is

triggered and these registers will continue to be locked down.

5.16.5 Serial POST Codes over GPIO

PCH adds the extended capability allowing system software to serialize POST or other

messages on GPIO. This capability negates the requirement for dedicated diagnostic

LEDs on the platform. Additionally, based on the newer BTX form factors, the PCI bus

as a target for POST codes is increasingly difficult to support as the total number of PCI

devices supported are decreasing.

5.16.5.1 Theory of Operation

For the PCH generation POST code serialization logic will be shared with GPIO. These

GPIOs will likely be shared with LED control offered by the Super I/O (SIO) component.

Figure 5-9 shows a likely configuration.

The anticipated usage model is that either the PCH or the SIO can drive a pin low to

turn off an LED. In the case of the power LED, the SIO would normally leave its

corresponding pin in a high-Z state to allow the LED to turn on. In this state, the PCH

can blink the LED by driving its corresponding pin low and subsequently tri-stating the

buffer. The I/O buffer should not drive a ‘1’ when configured for this functionality and

should be capable of sinking 24 mA of current.

Figure 5-9. Serial Post over GPIO Reference Circuit

SIO

VccSus3_3

LED

Note: The pull-up value is based on the brightness required.

PCH

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 171

Datasheet

An external optical sensing device can detect the on/off state of the LED. By externally

post-processing the information from the optical device, the serial bit stream can be

recovered. The hardware will supply a ‘sync’ byte before the actual data transmission

to allow external detection of the transmit frequency. The frequency of transmission

should be limited to 1 transition every 1 μs to ensure the detector can reliably sample

the on/off state of the LED. To allow flexibility in pull-up resistor values for power

optimization, the frequency of the transmissi on is programmable using the DRS field in

the GP_GB_CMDSTS register.

The serial bit stream is Manchester encoded. This choice of transmission ensures that a

transition will be seen on every clock. The 1 or 0 data is based on the transmission

happening during the high or low phase of the clock.

As the clock will be encoded within the data stream, hardware must ensure that the

Z-0 and 0-Z transitions are glitch-free. Driving the pin directly from a flop or through

glitch-free logic are possible methods to meet the glitch-free requirement.

A simplified hardware/software register interface provides control and status

information to track the activity of this block. Software enabling the serial blink

capability should implement an algorithm referenced below to send the serialized

message on the enabl ed GPIO.

1. R ead the Go/Busy status bit in the GP_GB_CMDSTS register and verify it is cleared.

This will ensure that the GPIO is idled and a previously requested message is still

not in progress.

2. Wr ite the data to serialize into the GP_GB_DATA register.

3. W rite the DLS and DRS values into the GP_GB_CMDSTS register and set the Go bit.

This may be accomplished using a single write.

The reference diagram shows the LEDs being powered from the suspend supply. By

providing a generic capability that can be used both in the main and the suspend power

planes maximum flexibility can be achieved. A key point to make is that the PCH will

not unintentionally drive the LED control pin low unless a serialization is in progress.

System board connections utilizing this serialization capability are required to use the

same power plane controlling the LED as the GPIO pin. Otherwise, the PCH GPIO may

float low during the message and prevent the LED from being controlled from the SIO.

The hardware will only be serializing messages when the core power well is powered

and the processor is operational.

Care should be taken to prevent the PCH from driving an activ e ‘1’ on a pin sharing the

serial LED capability. Since the SIO could be driving the line to 0, having the PCH drive

a 1 would create a high current path. A recommendation to avoid this condition

involves choosing a GPIO defaulting to an input. The GP_SER_BLINK register should be

set first before changing the direction of the pin to an output. This sequence ensures

the open-drain capability of the buffer is properly configured before enabling the pin as

an output.

5.16.5.2 Serial Message Format

In order to serialize the data onto the GPIO, an initial state of high-Z is assumed. The

SIO is required to have its LED control pin in a high-Z state as well to allow PCH to blink

the LED (refer to the reference diagram).

The three components of the serial message include the sync, data, and idle fields. The

sync field is 7 bits of ‘1’ data followed by 1 bit of ‘0’ data. Starting from the high-Z state

(LED on) provides external hardware a known initial condition and a known pattern. In

case one or more of the leading 1 sync bits are lost, the 1s followed by 0 provide a

clear indication of ‘end of sync’. This pattern will be used to ‘lock’ external sampling

logic to the encoded clock.

The data field is shifted out with the highest byte first (MSB). Within each byte, the

most significant bit is shifted first (MSb).

Functional Description

172 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

The idle field is enforced by the hardware and is at least 2 bit times long. The hardware

will not clear the Busy and Go bits until this idle time is met. Supporting the idle time in

hardware prev ents time-based coun ting in BIOS as the hardware is immediately ready

for the next serial code when the Go bit is cleared. Note that the idle state is

represented as a high-Z condition on the pin. If the last transmitted bit is a 1, retu rning

to the idle state will result in a final 0-1 transition on the output Manchester data. Two

full bit times of idle correspond to a count of 4 time intervals (the width of the time

interval is controlled by the DRS field).

The following waveform shows a 1-byte serial write with a data byte of 5Ah. The

internal clock and bit position are for reference purposes only. The Manchester D i s the

resultant data generated and serialized onto the GPIO. Since the buffer is operating in

open-drain mode the transitions are from high-Z to 0 and back.

5.16.6 GPIO Serial Expander (GSX)

5.16.6.1 Overview

There are a finite number of GPIOs available to be used in the PCH and servers

frequently runs out of GPIOs. To help alleviate this issue, a new capability has been

added to the PCH, the GPIO Serial Expander. This is a new interface that uses external

serial-to-parallel and parallel-to-serial expander chips to provide up to 64 additional

general purpose I/O signals in steps of 8 while only consuming 5 PCH’s I/O pins.

5.16.6.2 Configuration

GSX uses 5 signals, Clock (GSXCLK), Dataout (GSXSDOUT), Datain (GSXSDIN), Reset

(GSXSRESET#) and Load (GSXSLOAD). These signals are multiplexed onto PCI Grant

and PCI Request signals. A soft strap is used to configure whether GS X is enabled or

not. There is no hardstrap configuration or post-boot BIOS setting to change this.

Note: All GSX native functions are determined by GPIO Serial Expander Enable soft strap.

Software MUST NOT program the GPIO53/GSXDIN pin to GPIO mode by setting

GPIO_USE_SEL[53] bit when GSX is enabled through soft strap. GPIO mode will

override GSX operational mode and possible cause board contention on GPIO53 if the

platform had planned to use this pin as GSXDIN. It is also recommend that

GPIO_IO_SEL[53] be set to 1 when operating in GSX mode as added protection against

board contention.

5.16.6.3 Operation

When the soft straps for the PCH are read, the multiplexed signals become GSX only

signals and can not be used as PCI signals or general purpose I/O signals. Coming out

of reset, the GSXSRESET# signal automatically gets asserted to clear the outputs. This

signal stays active until the first cycle to program/upload data.

Software is required to set up the appropriate registers. It defines how many output

registers and input registers there are. The max number of combined registers is 8 as

the maximum GPIOs are 64. The registers can be any mix and match of input and

I nt ernal C l ock

M anchest e r D

8-bit sync field

(1111_1110)

Bit 7 0123456

5A data byte 2 clk

idle

Functional Description

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output. For example, you could have 64 outputs and no inputs, 64 inputs and no

outputs, 8 inputs and 56 outputs, and so forth. Also, it ’s not required to add up to a

maximum of 64 I/O. The GSX bus could also support only 8 inputs and 8 outputs, for

example.

After resetting the GSX bus with a write to IOERST, software will load up the CxGPOL VL

and CxGPOL VL_DW1 registers with data to be written out to the serial to par allel output

expanders (how many bits are programmed, is dependent upon how many outputs are

defined in the capabilities register). A write to the START (ST) bit will cause the

serialization process to begin. First all the output bits are shifted out to the serial to

parallel buffers. Then GSXSLOAD goes high to latch in and enable the output of the

buffers. At the same time, GSXSLOAD latches in the data into the parallel-to-serial

buffers and that data is read into the input buffers (CxGPILVL and CxGPILVL_DW1).

Once the START bit is set, the serialization process starts running continuously...

writing out the co nte nts of the CxGP OLVL registers and programming the contents of

the CxGPILVL registers. Clearing this bit (writing a “0” to it) will stop the process but

only on an atomic boundary. That is HW will finish serializing the output and finishing

reading in the serial data if it began the cycle.

There are two read only bits to help software with the programming of the CxGPOLVL

registers and the reading of the CxGPILVL registers. RUNNING (RUN) is set to a “1” as

long as the HW is in the process of writing out and reading in data. BUSY (BSY) is a “1”

as long as the CxGPOLVL data has not been completely written out at least once. For

software to mak e sure that data is not in the middle of being updated, it needs to wait

until RUNNING is a “0”. SW will program START to a “0” and wait for RUNNING to be a

“0” before it knows it’s safe to load in new data to the output buffers, or read data from

the input buffers without fear of data being updated in the middle of the cycle.

Functional Description

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5.17 SATA Host Controller (D31:F2, F5)

The SATA function in the PCH has three modes of operation to support different

operating system conditions. In the case of Native IDE enabled oper ating systems, the

PCH uses two controllers to enable all six ports of the bus. The first controller (Device

31: Function 2) supports ports 0 -3 and the second controller (Device 31: Function 5)

supports ports 4 and 5. When using a legacy operating system, only one controller

(Device 31: Function 2) is available that supports ports 0 - 3. In AHCI or RAID mode,

only one controller (Device 31: Function 2) is utilized enabling all six ports and the

second controller (Device 31: Function 5) shall be disabled.

The MAP register Section 15.1.28 provides the ability to share PCI functions. When

sharing is enabled, all decode of I/O is done through the SATA registers. Device 31,

Function 1 (IDE controller) is hidden by software writing to the Function Disable

The PCH SATA controllers feature six sets of interface signals (ports) that can be

independently enabled or disabled (they cannot be tri-stated or driven low). Each

interface is supported by an independent DMA controller.

The PCH SATA controllers interact with an attached mass storage device through a

(when AHCI/RAID disabled). The host software follows existing standards and

conventions when accessing the register interface and follows standard command

protocol conventions.

Note: SATA interface transfer rates are independent of UDMA mode settings. SATA interface

transfer rates will operate at the bus’s maximum speed, regardless of the UDMA mode

reported by the SATA device or the system BIOS.

5.17.1 SATA 6 Gb/s Support

The PCH supports SATA 6 Gb/s transfers with all capable SATA devices. SATA 6 Gb/s

supports s available on PCH Ports 0 and 1 only.

Note: PCH ports 0 and 1 also supports SATA 1.5 Gb/s and 3.0 Gb/s device transfers, while

ports 2-5 only support SATA 1.5 Gb/s and 3.0 Gb/s device transfers.

5.17.2 SATA Feature Support

Feature PCH

(AHCI/RAID Disabled)

PCH

(AHCI/RAID Enabled)

Native Command Queuing (NCQ) N/A Supported

Auto Activate for DMA N/A Supported

Hot-Plug Support N/A Supported

Asynchronous Signal Recovery N/A Supported

3 Gb/s Transfer Rate Supported Supported

ATAPI Asynchronous Notification N/A Supported

Host & Link Initiated Power

Management N/A Supported

Staggered Spin-Up Supported Supported

Command Completion Coalescing N/A N/A

External SATA N/A Sup ported

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5.17.3 Theory of Operation

5.17.3.1 Standard ATA Emulation

The PCH contains a set of registers that shadow the contents of the legacy IDE

registers. The behavior of the Command and Control Block registers, PIO, and DMA

data transfers, resets, and interrupts are all emulated.

Note: The PCH will assert INTR when the master device completes the EDD command

regardless of the command completion status of the slave device. If the master

completes EDD first, an INTR is generated and BSY will remain '1' until the slave

completes the command. If the slave completes EDD first, BSY will be '0' when the

master completes the EDD command and asserts INTR. Software must wait for busy to

clear (0) before completing an EDD command, as required by the ATA5 through ATA7

(T13) industry standards.

5.17.3.2 48-Bit LBA Operation

The SATA host controller supports 48-bit LBA through the host-to-device register FIS

when accesses are performed using writes to the task file. The S A TA host controller will

ensure that the correct data is put into the correct byte of the host-to-device FIS.

There are special considerations when reading from the task file to support 48-bit LBA

operation. Software may need to read all 16-bits. Since the registers are only 8-bits

wide and act as a FIFO, a bit must be set in the device/control register, which is at

offset 3F6h for primary and 376h for secondary (or their native counterparts).

If software clears bit 7 of the control register before performing a read, the last item

written will be returned from the FIFO. If software sets bit 7 of the control register

before performing a read, the first item written will be returned from the FIFO.

Feature Description

Native Command Queuing (NCQ) Allows the device to reorder commands for more efficient data transfers

Auto Activate for DMA Collapses a DMA Setup then DMA Activate sequence into a DMA Setup

only

Hot Plug Support Allows for device detection without power being applied and ability to

connect and disconnect devices without prior notification to the system

Asynchronous Signal Recovery Provides a recovery from a loss of signal or establishing communication

after hot plug

6 Gb/s Transfer Rate Capable of data transfers up to 6Gb/s

ATAPI Asynchronous Notification A mechanism for a device to send a notification to the host that the

device requires attention

Host & Link Initiated Power

Management Capability for the host controller or device to request P artial and Slumber

interface power states

Staggered Spin-Up Enables the host the ability to spin up hard drives sequentially to prev ent

power load problems on boot

Command Completion Coalescing Reduces interrupt and completion overhead by allowing a specified

number of commands to complete and then generating an interrupt to

process the commands

External SATA Technology that allows for an outside the box connection of up to 2

meters (when using the cable defined in SATA-IO)

Functional Description

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5.17.4 SATA Swap Bay Support

The PCH provides for basic SAT A swap bay support using the PSC register configuration

bits and power management flows. A device can be powered down by software and the

port can then be disabled, allowing removal and insertion of a new device.

Note: This SATA swap bay operation requires board hardware (implementation specific),

BIOS, and operating system support.

5.17.5 Hot-Plug Operation

PCH supports Hot-Plug Surprise removal and Insertion Notification. An internal SATA

port with a Mechanical Presence Switch can support PARTIAL and SLUMBER with Hot

Plug Enabled. Software can take advantage of power savings in the low power states

while enabling hot-plug operation. Refer to chapter 7 of the AHCI specification for

details.

5.17.6 Function Level Reset Support (FLR) (SRV/WS SKUs Only)

The SATA Host Controller supports the Function Level Reset (FLR) capability. The FLR

capability can be used in conjunction with Intel Virtualization Technology. FLR allows an

Operating System in a Virtual Machine to have complete control over a device,

including its initialization, without interfering with the rest of the platform. The device

provides a software interface that enables the Operating System to reset the whole

device as if a PCI reset was asserted.

5.17.6.1 FLR Steps

5.17.6.1.1 FLR Initialization

1. A FLR is initiated by software writing a ‘1’ to the Initiate FLR bit.

2. All subsequent requests targeting the Function will not be claimed and will be

Master Abort Immediate on the bus. This includes any configuration, I/O or

Memory cycles, however, the Function shall continue to accept completions

targeting the Function.

5.17.6.1.2 FLR Operation

The Function will Reset all configuration, I/O and memory registers of the Function

except those indicated otherwise and reset all internal states of the Function to the

default or initial condition.

5.17.6.1.3 FLR Completion

The Initiate FLR bit is reset (cleared) when the FLR reset is completed. This bit can be

used to indicate to the software that the FLR reset is completed.

Note: From the time Initiate FLR bit is written to '1' software must wait at least 100 ms

before accessing the function.

Functional Description

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5.17.7 Intel® Rapid Storage Technology Enterprise Configuration

The Intel® Rapid Storage Technology enterprise (Intel® RSTe) offers several diverse

options for RAID (redundant array of independent disks) to meet the needs of the end

user. AHCI support provides higher performance and alleviates disk bottlenecks by

taking advantage of the independent DMA engines that each SATA port offers in PCH.

• RAID Level 0 performance scaling up to 4 drives, enabling higher throughput for

data intensive applications such as video editing.

• Data redundancy is offered through RAID Level 1, which performs mirroring.

• RAID Level 10 provides high levels of storage performance with increased data

protection, combining the fault-tolerance of RAID Level 1 with the performance of

RAID Level 0. By striping RAID Level 1 segments, high I/O rates can be achieved

on systems that require both performance and fault-tolerance. RAID Level 10

requires 4 hard drives, and provides the capacity of two drives.

• RAID Level 5 provides highly efficient storage while maintaining fault-tolerance on

3 or more drives. By striping parity, and rotating it across all disks, fault tolerance

of any single driv e is achieved while only consuming 1 drive worth of capacity. That

is, a 3 drive RAID 5 has the capacity of 2 drives, or a 4 drive RAID 5 has the

capacity of 3 drives. RAID 5 has high read transaction rates, with a medium write

rate. RAID 5 is well suited for applications that require high amounts of storage

while maintaining fault tolerance.

By using the PCH’s built -in Intel Rapid Storage Technology, there is no loss of additional

PCIe/system resources or add-in card slot/motherboard space footprint used compared

to when a discrete RAID controller is implemented.

Intel Rapid Storage Technology enterprise functionality requires the following items:

1. PCH SKU enabled for Intel Rapid Storage Technology enterpri se (see Section 1.3)

2. Intel Rapid Storage Manager RAID Option ROM must be on the platform

3. Intel Rapid Storage Manager drivers, most recent revision.

4. At least two SATA hard disk drives (minimum depends on RAID configuration).

Intel Rapid Storage Technology enterprise is not available in the following

configurations:

1. The SATA controller is in compatible mode.

2. The SATA controller is programmed in RAID mode, but the AIE bit (D31:F2:Offset

9Ch bit 7) is set to 1.

5.17.7.1 Intel Rapid Storage Technology Manager RAID Option ROM

The Intel Rapid Storage Technology Manager RAID Option ROM is a standard PnP

Option ROM that is easily integrated into any System BIOS. When in place, it provides

the following three primary functions:

• Provides a text mode user interface that allows the user to manage the RAID

configuration on the system in a pre-oper ating system environment. Its feature set

is kept simple to keep size to a minimum, but allows the user to create and delete

RAID volumes and select recovery options when problems occur.

• Provides boot support when using a RAID volume as a boot disk. It does this by

providing Int13 services when a RAID volume needs to be accessed by MS-DOS

applications (such as NTLDR) and by exporting the RAID volumes to the System

BIOS for selection in the boot order.

• At each boot up, prov ides the user with a status of the RAID volumes and the

option to enter the user interface by pressing CTRL-I.

Functional Description

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5.17.8 Power Management Operation

Power management of the PCH SATA controller and ports will cover operations of the

host controller and the SATA wire.

5.17.8.1 Power State Mappings

The D0 PCI power management state for device is supported by the PCH SATA

controller.

SATA devices may also have multiple power states. From parallel ATA, three device

states are supported through ACPI. They are:

•D0 – device is working and instantly available.

•D1 – device enters when it receives a ST ANDBY IMMEDIA TE command. Exit latency

from this state is in seconds

•D3 – from the SATA device’s perspective, no different than a D1 state, in that it is

entered using the STANDBY IMMEDIATE command. However, an ACPI method is

also called which will reset the device and then cut its power.

Each of these device states are subsets of the host controller’s D0 state.

Finally, SAT A defines three PHY layer pow er states, which have no equivalent mappings

to parallel ATA. They are:

•PHY READY – PHY logic and PLL are both on and active

•Partial – PHY logic is powered, but in a reduced state. Exit latency is no longer

than 10 ns

•Slumber – PHY logic is powered, but in a reduced state. Exit latency can be up to

10 ms.

Since these states have much lower exit latency than the ACPI D1 and D3 states, the

SATA controller defines these states as sub-states of the device D0 state.

5.17.8.2 Power State Transitions

5.17.8.2.1 Partial and Slumber State Entry/Exit

The partial and slumber states save interface power when the interface is idle. The

SATA controller defines PHY layer power management (as performed using primitives)

as a driver operation from the host side, and a device proprietary mechanism on the

device side. The SAT A controller accepts device transition t ypes, but does not issue any

transitions as a host. All received requests from a SATA device will be ACKed.

When an operation is performed to the SATA controller such that it needs to use the

SATA cable, the controller must check whether the link is in the Partial or Slumber

states, and if so, must issue a COM_WAKE to bring the link back online. Similarly, the

SATA device must perform the same action.

5.17.8.2.2 Device D1, D3 States

These states are entered after some period of time when software has determined that

no commands will be sent to this device for some time. The mechanism for putting a

device in these states does not involve any work on the host controller, other then

sending commands over the interface to the device. Th e command most likely to be

used in ATA/ATAPI is the “STANDBY IMMEDIATE” command.

Functional Description

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5.17.8.2.3 Host Controller D3HOT State

After the interface and device have been put into a low power state, the SATA host

controller may be put into a low power state. This is performed using the PCI power

management registers in configuration space. There are two very important aspects to

note when using PCI power manageme nt.

1. When the power state is D3, only accesses to configuration space are allowed. Any

attempt to access the memory or I/O spaces will result in master abort.

2. When the power state is D3, no interrupts may be generated, even if they are

enabled. If an interrupt status bit is pending when the controller transitions to D0,

an interrupt may be generated.

When the controller is put into D3, it is assumed that software has properly shut down

the device and d isable d the ports. Ther efore, there is no need to sustain an y v alues on

the port wires. The interface will be treated as if no device is present on the cable, and

power will be minimized.

When returning from a D3 state, an internal reset will not be performed.

5.17.8.2.4 Non-AHCI Mode PME# Generation

When in non-AHCI mode (legacy mode) of operation, the SATA cont roller does not

generate PME#. This includes attach events (since the port must be disabled), or

interlock switch events (using the SATAGP pins).

5.17.8.3 Intel® Scalable Memory Interconnect (Intel® SMI) Trapping (APM)

Device 31:Function2:Offset C0h (see Section 14.1.41) control for generating SMI# on

accesses to the IDE I/O spaces. These bits map to the legacy ranges (1F0–1F7h, 3F6h,

170–177h, and 376h) and native IDE ranges defined by PCMDBA, PCTLBA, SCMDBA an

SCTLBA. If the SATA controller is in legacy mode and is using these addresses,

accesses to one of these ranges with the appropriate bit set causes the cycle to not be

forwarded to the SATA controller, and for an SMI# to be generated. If an access to the

Bus-Master IDE registers occurs while trapping is enabled for the device being

accessed, then the register is updated, an SMI# is generated, and the device activity

status bits (Section 14.1.42) are updated indicating that a trap occurred.

5.17.9 SATA Device Presence

In legacy mode, the SATA controller does not generate interrupts based on hot plug/

unplug events. However, the SA TA PHY does know when a device is connected (if not in

a partial or slumber state), and it s beneficial to communicate this information to host

software as this will greatly reduce boot times and resume times.

The flow used to indicate SATA device presence is shown in Figure 5-10. The ‘PxE’ bit

refers to PCS. P[3:0]E bits, depending on the port being checked and the ‘PxP’ bits refer

to the PCS. P[3:0] P bits, depend ing on the p ort being check ed. If the PCS/PxP bit is set

a device is present, if the bit is cleared a device is not present. If a port is disabled,

software can check to see if a new device is connected by periodically re-enabling the

port and observing if a device is present, if a device is not present it can disable the

port and check again later. If a port remains enabled, software can periodically poll

PCS.PxP to see if a new device is connected.

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5.17.10 SATA LED

The SATALED# output is driven whenever the BSY bit is set in any SATA port. The

SATALED# is an active-low open-drain output. When SATALED# is low, the LED should

be active. When SATALED# is high, the LED should be inactive.

5.17.11 AHCI Operation

The PCH provides hardware support for Advanced Host Controller Interface (AHCI), a

programming interface for SATA host controllers developed through a joint industry

effort. AHCI defines transactions between the S A T A controller and software and enables

advanced perform a nce and usability with SATA. Platforms supporting AHCI may take

advantage of performance features such as no master/slave designation for SATA

devices—each device is treated as a master—and hardware assisted native command

queuing. AHCI also provides usability enhancements such as Hot-Plug. AHCI requires

appropriate software support (such as, an AHCI driver) and for some features,

hardware support in the SATA device or additional platform hardware.

The PCH supports all of the mandatory features of the Serial ATA Advanced Host

Controller Interface Specification, Revision 1.2 and many optional features, such as

hardware assisted native command queuing, aggressive power management, LED

indicator support, and Hot-Plug through the use of interlock switch support (additional

platform hardware and software may be re quired depending upon the implementation).

Note: For reliable device removal notification while in AHCI operation without the use of

interlock switches (surprise removal), interface power management should be disabled

for the associated port. See Section 7.3.1 of the AHCI Specification for more

information.

Figure 5-10. Flow for Port Enable / Device Present Bits

Functional Description

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5.17.12 SGPIO Signals

The SGPIO signals, in accordance to the SFF-8485 specification, support per-port LED

signaling. These signals are not related to SATALED#, which allows for simplified

indication of SATA command activity. The SGPIO group interfaces with an external

controller chip that fetches and serializes the data for driving across the SGPIO bus.

The output signals then control the LEDs. This feature is only v alid in AHCI/RAID mode.

Intel does not validate all possible usage cases of this feature. Customers should

validate their specific design implementation on their own platforms.

5.17.12.1 Mechanism

The enclosure management for SATA Controller 1 (Device 31: Function 2) involves

sending messages that control LEDs in the enclosure. The messages for this function

are stored after the normal registers in the AHCI BAR, at Offset 580h bytes for PCH

from the beginning of the AHCI BAR as specified by the EM_LOC global register

(Section 14.4.1.6).

Software creates messages for transmission in the enclosure management message

buffer. The data in the message buffer should not be changed if CTL.TM bit is set by

software to transmit an update message. Software should only update the message

buffer when CTL.TM bit is cleared by hardware otherwise the message transmitted will

be indeterminate. Software then writes a register to cause hardware to transmit the

message or take appropriate action based on the message content. The software

should only create message types supported by the controller, which is LED messages

for PCH. If the software creates other non LED message types (such as SAF-TE, SES-

2), the SGPIO interface may hang and the result is indeterminate.

During reset all SGPIO pins will be in tri-state state. The interface will continue to be in

tri-state state after reset until the first transmission occurs when software programs

the message buffer and sets the transmit bit CTL.TM. The SATA Host controller will

initiate the transmission by driving SCLOCK and at the same time drive the SLOAD to

‘0’ prior to the actual bit stream transmission. The Host will drive SLOAD low for at

least 5 SCLOCK then only start the bit stre am by driving the SLOAD to high. SLOAD will

be driven high for 1 SCLOCK follow by vendor specific pattern that is default to “0000”

if software has yet to program the value. A total of 21-bit stream from 7 ports (Port0,

Port1, Port2, Port3, Port4 Port5 and Port6) of 3-bit per port LED message will be

transmitted on SDATA O UT0 pin after the SLOAD is driven high for 1 SCLOCK. Only 3

ports (Port4, Port5 and Port6) of 9 bit total LED message follow by 12 bits of tri-state

value will be transmitted out on SDATAOUT1 pin.

All the default LED message values will be high prior to software setting them, except

the Activity LED message that is configured to be hardware driven that will be

generated based on the activity from the respective port. All the LED message values

will be driven to ‘1’ for the port that is unimplemented as indicated in the Port

Implemented register regardless of the software programmed value through the

message buffer.

There are 2 different ways of resetting PCH SGPIO interface, asynchronous reset and

synchronous reset. Asynchronous reset is caused by platform reset to cause the SGPIO

interface to be tri-state asynchronously. Synchronous reset is caused by setting the

CTL.RESET bit, clearing the GHC.AE bit or HBA reset, where Host Controller will

complete the existing full bit stream tr ansmission then only tri-state all the SGPIO pins.

After the reset, both synchronous and asynchronous, the SGPIO pins will stay tri-

stated.

Note: PCH Host Controller does not ensure that it will cause the target SGPIO device or

controller to be reset. Software is responsible to keep PCH SGPIO interface in tri-state

for 2 second in order to cause a reset on the target of the SGPIO interface.

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5.17.12.2 Message Format

Messages shall be constructed with a one DW ord header that describes the message to

be sent followed by the actual message contents. The first DWord shall be constructed

as follows:

The SAF-TE, SES-2, and SGPIO message formats are defined in the corresponding

specifications, respectively. The LED message type is defined in Section 5.17.12.3. It is

the responsibility of software to ensure the content of the message format is correct. If

the message type is not progr ammed as 'LED' for this controller, the controller shall not

take any action to update its LEDs. Note that for LED message type, the message size

is always consisted of 4 bytes.

Bit Description

31:28 Reserved

27:24

Message Type (MTYPE): Specifies the type of the message.

The message types are:

0h = LED

1h = SAF-TE

2h = SES-2

3h = SGPIO (register based interface)

All other values reserved

23:16

Data Size (DSIZE): Specifies the data siz e in by tes. If the message (enclosure servi ces co mmand)

has a data buffer that is ass ociated with it that is tr ansferred, the siz e of that data buffer is specified

in this field. If there is no separate data buffer, this field shall have a value of ‘0’. The data directly

follows the message in the message buffer. For PCH, this value should always be ‘0’.

15:8 Message Size (MSIZE): Specifies the size of the message in bytes. The message size does not

include th e one DWord header. A value of ‘0’ is invalid. For PCH, the message size is always 4 bytes.

7:0 Reserved

Functional Description

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5.17.12.3 LED Message Type

The LED message type specifies the status of up to three LEDs. Typically, the usage for

these LEDs is activity, fault, and locate. Not all implementations necessarily contain all

LEDs (for example, some implementations may not have a locate LED). The message

identifies the HBA port number and the Port Multiplier port number that the slot status

applies to. If a Port Multiplier is not in use with a particular device, the Port Multiplier

port number shall be ‘0’. The format of the LED message type is defined in Table 5-45.

The LEDs shall retain their values until there is a following update for that particular

slot.

Table 5-45. Multi-Activity LED Message Type

Byte Description

3-2

Value (VAL): This field describes the state of each LED for a particular location. There are three

LEDs that may be supported by the HBA. Each LED has 3 bits of control.

LED values are:

000b - LED shall be off

001b - LED shall be solid on as perceived by human eye

All other values reserved

The LED bit locations are:

Bits 2:0 - Activity LED (may be driven by hardware)

Bits 5:3 - Vendor Specific LED (such as, locate)

Bits 8:6 - Vendor Specific LED (such as, fault)

Bits 15:9 - Reserved

Vendor specific message is:

Bit 3:0 - Vendor Specific Pattern

Bit 15:4 - Reserved

Note: If Activity LED Hardware Driven (ATTR.ALHD) bit is set, host will output the hardware LED

value sampled internally and will ignore software written activity value on bit [2:0]. Since

PCH Enclosure Management does not support port multiplier based LED message, the LED

message will be generated independently based on respective port’s operation activity.

Ve ndor specific LED values Locate (Bits 5:3) and Fault (Bits 8:6) always are driven by

software.

Port Multiplier Information: Specifies slot specific information related to Port Multiplier.

Bits 3:0 specify t he Port Multiplier port number for the slot th at re qu ires the s tatus update. If a Port

Multiplier is not attached to the device in the affected slot, the Port Multiplier port number shall be

'0'. Bits 7:4 are reserved. PCH does not support LED messages for devices behind a Port MUltiplier.

This byte should be 0.

HBA Information: Specifies slot specific information related to the HBA.

Bits 4:0 - HBA port number for the slot that requires the status update.

Bit 5 - If set to '1', Value is a vendor specific message that applies t o the entire enc losure . If cleared

to '0', Value applies to the port specified in bits 4:0.

Bits 7:6 - Reserved

Functional Description

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Datasheet

5.17.12.4 SGPIO Waveform

5.17.13 External SATA

PCH supports external SATA. External SATA utilizes the SATA interface outside of the

system box. The usage model for this feature must comply with the Serial ATA II

Cables and Connectors Volume 2 Gold specification at www.sata-io.org. Intel validates

two configurations:

1. The cable-up solution involves an internal SATA cable that connects to the SATA

motherboard connector and spans to a back panel PCI bracket with an eSATA

connector. A se parate eSATA cable is required to connect an eSATA device.

2. The back-panel solution involves running a trace to the I/O back panel and

connecting a device using an external SATA connector on the board.

Figure 5-11. Serial Data Transmitted over the SGPIO Interface

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 185

Datasheet

5.18 SAS/SATA Controller Overview (SAS is for SRV/WS SKUs

Only)

Note: SAS is not available on HEDT.

5.18.1 SCU Features

5.18.1.1 Other Relevant Documents

• ISO/IEC 14776-372, SCSI Enclosure Services-2 (SES-2) (INCITS T10/1559-D)

• ISO/IEC 14776-453, SCSI Primary Commands-4 (SPC-4)

• ISO/IEC 14776-322, SCSI Block Commands-3 (SBC-3)

• ISO/IEC 14776-413, SCSI Architecture Model-4 (SAM-4)

• ISO/IEC 14776-971, AT Attachment with Packet Interface-7 Volume 1 (ATA/ATAPI-

7 V1) (ANSI INCITS 397-2005)

• ISO/IEC 14776-971, AT Attachment with Packet Interface-7 Volume 3 (ATA/ATAPI-

7 V3)(Serial ATA) (ANSI INCITS 397-2005)

• Serial Attached SCSI (SAS) [ANSI INCITS 376-2003]

• Serial Attached SCSI (SAS) revision 2.0r5

• Serial ATA: Data Link Interface revision 2.5

5.18.1.2 SCU Architectural Features

The Storage Controller Unit is a stand alone I/O controller that supports Serial Attached

SCSI (SAS) and Serial ATA (SATA) by incorporating dedicated messaging unit, DMA

engines, frame buffering and protocol controllers to execute I/O requests. The Storage

Controller Unit (SCU) supports execution of I/O requests for multiple modes of

operations such as SSP, STP and SMP initiator and SATA host operations. Each of four

SCU protocol engines can operate independently in any of the modes and can also

execute SAS wide port operations. The SCU incorpor ates the follo w in g features :

•Protocol Engine Group

— SSP, SMP, STP Initiator mode

—SATA Host mode

— SATA Port Selector (PS), Native Command Queueing (NCQ) supported

— Automated Out Of Band (OOB) signaling

— Automated Speed Negotiation (SN)

— Automated Transport Layer

—Automated Link Layer

— 1.5 Gbps and 3.0 Gbps Li nk operations for SAS and SATA

— Link Level Power Management

— Automated task scheduling

—Wide Ports up to x4

•Storage DMA Engine

— Automated Scatter Gather List processing

—Intel

® Block Protection Technology Context management

• End to End data path protection

* using Parity, ECC and BPT

Functional Description

186 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.18.1.3 Features Excluded in Current SCU Architecture

• STP Host/SATA Target functions

•SSP Target Mode

• SMP Target Mode

• Bi-Directional SCSI commands support.

• Multiple Task Priority Level - only support Normal and High.

• Full Staggered spin-up in SATA devices (only support partial power on staggered

spinup for SATA devices)

• SAS Connection Multiplexing

5.18.2 SCU Configurations

5.18.2.1 SCU Configurations and Numbering Conventions

There are two distinct configurations of the SCU:

•Single SCU-4

•Double SCU-4

The Single SCU-4 is shown in Figure 5-12.

The single SCU-4 app ears to the Driver as SCU[0]. There is a single Protocol Engi ne

Group, PEG[0]. Within this Protocol Engine Group there are four Protocol Engines,

PE[3:0], which connect to Phy[3:0]. There are four Port Task Schedulers (PTS), some

of which are disabled depending on how the Driver configures it for Wide Port. Note

that although the figure shows the SCU connecting to a SAS/SATA Domain, this could

be direct-attached SAS or SATA disks.

The next configuration is a Dual SCU-4, as shown in Figure 5-13.

Figure 5-12. Single SCU-4 Configuration

SMU

SDMA

FBMCU

TxBuf

RxBuf

Port Task

Scheduler

Group

Scheduler

Scheduler Scheduler

Scheduler

Transport

Layer [3:0] Link

Layer [3:0]

Host

Storage

Controller

Unit [0]

Protocol

Engine

Group[0]

IHSPI

[3:0]

Protocol

Engine[3:0] A

EPhy

[3:0]

SAS / SATA

Domain

Context

RAM

RNC_RAM

TC_RAM

Functional Description

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Datasheet

The Dual SCU-4 appears to the Driver as SCU[0] + SCU[1] behind a common PCIe

function. Both SCUs are mapped behind a common set of PCIe BARs. Each SCU

contains a single PEG. Note that on SCU[1] the Phys are numbered 4 thru 7 and the

PEG is numbered as PEG[0].

The Intel C602 Chipset SKU includes a single SCU-4 to provide 4 ports of SATA.

The I ntel C 604 Chipset SKU includes a s ingle SCU- 4 to provide 4 ports of SATA/SAS.

The Intel C606, C608 Chipset SKUs includes a Dual SCU-4 that provides 8 ports of

SATA/SAS.

5.18.2.1.1 Run-Time Configurations

In addition to the other types of configurations, the Driver will be able to change the

run-time configuration of the SCU. These allow the driver to configure a subset of

features.

At a high level these are:

Protocol Support: Each link can be configured to support SSP, SMP, STP, or SATA.

Wide Port Configuration:The PTS is con figured to support Wide Ports.

Transport Layer Retry: Support of TLR can be disabled for the part as a whole.

Figure 5-13. Double SCU-4 Configuration

SMU

SDMA

FBMCU

TxBuf

RxBuf

Por t Tas k

Scheduler

Group

Scheduler

Scheduler Scheduler

Scheduler

Transport

Layer [3:0] Link

Layer [3:0]

Host

Interface

Storage

Controller

Unit [ 0 ]

Protocol

Engine

Group[0]

IHSPI

[3:0]

Protocol

Engine[3:0]

EPhy

[3:0]

SAS / SATA

Domain

Context

RAM

RNC_RAM

TC_RAM

SMU

SDMA

FBMCU

TxBuf

RxBuf

Por t Tas k

Scheduler

Group

Scheduler

Scheduler Scheduler

Scheduler

Transport

Layer [3:0] Link

Layer [3:0]

Host

Interface

Storage

Controller

Unit [1]

Protocol

Engine

Group[0]

IHSPI

[3:0]

Protocol

Engine[3:0]

EPhy

[7:4]

SAS / SATA

Domain

Context

RAM

RNC_RAM

TC_RAM

Common,

Shared or

Mirrored

Config

Registers

Functional Description

188 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.18.3 Storage Controller Unit (SCU) Architecture

The SCU Architecture can be divided into 4 major layers:

• Host Queue/Memory Communication Interface whic h inc lud es the Storage

Messaging Unit (SMU) and the Storage DMA (SD M A) functional blocks

• Port Task Scheduler Group which includes 4 Port Task Schedulers, Port

Configuration Switch, Task Schedule RAM and Remote Node Schedule RAM

• 4 Transport Layer functional blocks which are part of the Protocol Engine Group

• 4 Link Layer functional blocks which are part of the Protocol Engine Group

The Protocol Engine Group also includes the Context RAM Memory Controller (CRAMC)

with Task Context (TC RAM) and Remote Node Context RAM (RNC RAM).

The Frame Buffer Memory Controller Unit (FBMCU) with SRAM are used by the

Transport Layer functional blocks for Tx and Rx frames buffers storage.

The term “Task” is use d t hroughout this document. Following description clarifies the

kinds of Tasks the SCU supports. A Task can be one of the following types

(TaskType):

IORead: A request to perform an I/O Read as an initiator.

IOWrite: A request to perform an I/O Write as an initiator.

TaskMgmt: A request to perform a task management function, that is, a

non-I/O task (initiator).

RawFrame: A raw frame where the entire header is provided by the Driver.

Primitive: A request to send a primitive outside of a connection.

In addition to the TaskType, each Task will define the Protocol to use. Four different

Protocol types are supported for a task:

SMP: SMP supported for initiator.

SSP: SSP supported for initiator

STP/SATA: STP and SATA use the same protocol type, only initiator/host

mode is supported.

None: Used for sending primitives.

The TaskType ‘Primitive’ will support sending the following:

• NOTIFY(POWER FAIL)

•BROADCAST(SES)

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 189

Datasheet

5.18.3.1 SCU Theory of Operation

The SCU Architectural terms and Definitions referenced in this document are defined

below:

• Task - a job issued by the driver to SCU to request SCU to perform some amount of

work described with the associated task context information.

• Local Port - a communication entity that contains one or more Transport Layer

(TL)/Link Layer (LL) pairs that are associated with a single PTS.

• Remote Node - a SAS or S ATA device which can be communicated to using an SCU

local port including SSP Initiator, Expande r, SMP Initiator and SATA Device.

• Index - a SCU internal addressing mechanism used to refer to data structure,

memory, PTS or TL.

— Remote Node Index (RNi) - an index used by SCU to reference to data

structure RNC associated to a remote device which can be communicated

through the SCU port.

— Task Context Index (TCi) - an index used by the TL/SDMA to reference to data

structure TC that contains all the information associated with the task

execution.

• Context - it is a data structure that usually resides in memory that contains all the

necessary information for the functional block that is using the context to perform

it’s function..

— Task Context (T C) - a data structure that contains all the necessary information

for SCU to execute a task.

— Remote Node Context (RNC) - a data structure that contains all the necessary

information about the characteristic of the remote node for SCU to manage

connection and task execution.

When the SCU is initialized and configured by the driver after power up and topology

discovery, the driver assigns a task to the SCU in the form of a Task Context in a host

work queue in host memory. The Task Context contains all the necessary information

for the SCU to execute the entire task until completion or until terminated with an error

posted in the host completion queue in host memory.

The host driver will notify the Storage Messaging Unit (SMU) when a task is ready. The

SMU will inform the Storage DMA Engine (SDMA) to fetch the Task Context (TC) from

the host memory. The SDMA will load the TC into TC RAM as indexed by the T Ci and at

the same time transfer the Task Schedule portion of the context within the TC to the

P ort Task Scheduler (PTS). The Port Task Scheduler will link the task to the task list that

is associated with the task under the corresponding Remote Node.

The Port Task Scheduler will schedule the tasks based on a round robin algorithm.

When a task is assigned to a Transport Layer function block, the TL will fetch the Task

Context associated with the assigned task from the TC RAM using the CRAMC after the

Link Layer Connection Manager establishes a connection to the remote node.

The Link Layer is responsible for Link Initialization, Connection Management, Data

Encoding/Decoding, Basic Frame Validation, elasticity-FIFO, Link Level Flow Control,

Frame CRC-Generation/Verification, Data Scrambling/De-Scrambling, Primitive

Sequence Management, Frame Building and Remote Node Context Management.

The SAS Port Layer functions (such as wide port mapping) are managed by the Port

Task Scheduler.

Functional Description

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Datasheet

5.18.3.2 SCU Functional Block Overview

The functional blocks of the SCU are detailed in the following sub-sections.

5.18.3.2.1 SMU Overview

The SMU (Storage Messaging Unit) provides th e interface of the SCU to the Driver. The

major functions of the SMU are as follows:

• Allow the Driver to initiate new TCs to the SCU, the SMU then requests that the

SDMA perform the actual DMA of the TCs

• Manage the completion queue (which contains Task Completions, Unsolicited Frame

Notifications, and Event Notifications)

• Provide the locations in Host Memory to the TL where to put Unsolicited Frame

payload and headers

• Provide a means for all units to pass Event Notifications to the Driver

• Allow the Driver to post new RNCs to the SCU

• Coalesce interrupts to allow more efficient Driver use

Figure 5-14. Storage Controller Block Diagram

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 191

Datasheet

In general the SMU is responsible for determining where in Host Memory a particular

data element is stored and passes requests so that the SDMA can transfer between

Host Memory and the appropriate internal data structure. Note that Host Memory is

either system memory or RAID cache memory, depending on the usage model.

5.18.3.2.1.1 Memory Mapped Register (MMR) Interface

The Memory Mapped Registers provide a way for the Driver to configure parameters

throughout the SCU. The entire memory mapped register space is claimed by the SMU.

Each PCI Function within the SMU consumes memory space for SMU control/status and

the MSI-X Table and Pending Bit Array. These registers are mapped into PCI Memory

Space through the Base Address Registers (SCUPBAR0, SRIOVBAR0).

5.18.3.2.1.2 Post Context Queue

The “Post Context Queue” is used to pass new Tasks and Remote Node Contexts (TCs

and RNCs) from the Driver to the SDMA. The value written includes the Context

command Type, Protocol Engine Group Index (PEGi), Local Port Index (LPi) and Context

Index (TCi/RNi).

The valid Context commands are specified in Table 5-46.

The Post_TC, Abort_TC, and Dump_TC commands all reference a Task Context index

(TCi) and are referred to collectively as TC Commands. When posting a TC Command,

the Driver will identify the Protocol Engine Group, Local Port, and provide a Task

Context index (TCi).

The Post_RNC, Dump_RNC, and Post_I_T_Nexus commands all reference a Remote

Node index (RNi) and are referred to collectively as RNC Commands. When posting a

RNC Command, the Driver will identify the Protocol Engine Group, Local Port, and

provide a Remote Node Index (RNi). The Post_RNC_32/96 commands will result in an

RNC data transfer from host memory to the RNC_RAM. The Dump_RNC_32/96

commands will result in an RNC data tr ansf er from the RNC_RAM to host memo ry. The

other commands operate on RNCs in the RNC_RAM but do not result in a data transfer

to/from host memory.

Table 5-46. Context Command Type

Context Command Type

Task Context Commands

Post_TC

Post_TC_Abort

Dump_TC

Remote Node Context Commands1

1. The RNC commands can only be posted through function 0.

Post_RNC_32

Post_RNC_96

Post_RNC_Invalidate

Dump_RNC_32

Dump_RNC_96

Post_RNC_Suspend

Post_RNC_Resume

Post_I_T_Nexus_Loss_Timer_Enable

Post_I_T_Nexus_Loss_Timer_Disable

Functional Description

192 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Each Task Context is 256 bytes in size and is laid out in contiguous memory space

A Remote Node Context is either 32 or 96 Bytes in size and will be laid out on 32 Byte

aligned address offsets. The RNi indicates the starting address of the RNC in multiples

of 32-bytes regardless of whether it is a 32-byte of 96-byte context. See Figure 5-15 as

an example.

5.18.3.2.1.3 Completion Queue

The Completion Queue is located in host memory and is used as a circular queue for

posting completions back to the Driver. After receiving notification from the other SCU

units, the SMU puts a Completion Entry into the Completion Queue by directly issuing a

32-bit write. The Completion Entry can be one of the types shown in Table 5-47.

Every completion entry contains a Cycle bit “C”, a Type field “T” and a Protocol Engine

Group index (PEGi).

Figure 5-15. RNC Sizes and Indexing Example

RNi = 0

RNi = 1

RNi = 2

RNi = 3

RNi = 4

RNi = 5

RNi = 6

RNi = 7

RNi = 8

RNi = 9

RNi = 10

RNi = 11

RNi = 0

RNi = 3

RNi = 6

RNi = 9

RNi = 2

RNi = 6

32 Bytes

96 Bytes

RNi = 9

RNi = 10

RNi = 11

RNi = 0

RNi = 1

Uniform

32 Byte

RNC

Uniform

96 Byte

RNC

Mixed

32/96 Byte

RNC

Offset 288

(9x32)

RNi = 5

Table 5-47. Completion Entry Format

10Type

C T = 0 Status PEGi LPi TCi Task Completion

C T = 1 S tatus Command PEGi LPi TCi/RNi SDMA (CDMA) Completion

C T = 2 UFi PEi RNi Unsolicited Frame Notification

C T = 3 Notification Code PEGi LPi/PEi1

1. Events from the Transport and Link Layers will use PEi, events from the PTSG will use LPi

TCi Critical Notification

(such as, I_T_Nexus Time Out)

CT = 4

2. Type 4-7 are considered Events and will be discarded if there is no room in the Completion Queue for

Events.

Event Code PEGi LPi/PEi TCi/RNi Event Notification

(can get dropped)

C T = 5 Status Command PEGi LPi TCi/RNi SMU (PCQ) Events

C T = 6 Status RegisterOffset/AM SMU Generated Events

CT = 7 Reserved Reserved

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 193

Datasheet

5.18.3.2.2 SDMA Overview

The SDMA (Storage DMA Unit) consists of two DMA channels: the Context DMA (CDMA)

and the Payload DMA (PDMA). The CDMA consists of a CDMA Descriptor Manager

(CDMA DM) and a CD MA Engine, and th e PDMA consists of a PDMA Descriptor Manager

(PDMA DM) and a PDMA Engine. Each DMA Engine consists of a Receive DMA Engine

(writing to host memory) and a Transmit DMA Engine (reading from host memory).

Note that in this document the term host memory is used to imply a memory

subsystem outside of the SCU.

The CDMA and PDMA Engines operate on descriptors. A descriptor describes a single

DMA Engine operation between a host memory buffer and an SCU unit. The maximum

DMA length that a descriptor can describe is up to 256 bytes and 1024 byte s for the

CDMA and PDMA respectively. The CDMA or PDMA Descriptor Manag er determines the

DMA request type and generates a single descriptor or multiple descriptors with the

proper source address, destination address and transfer length to define the DMA

transfer oper ation either for receiving data (writing to host memory) or transmitting

data (reading from host memory). Note that based on how the host memory buffers

are described by the Scatter-Gather List (SGL), a single DMA request issued to the

PDMA Descriptor Manager may yield multiple descriptors.

When the CDMA or PDMA Engine operation is completed, the result of the opera tion is

written to the Completion RAM of the CDMA or PDMA Engine for inspection and

processing of the completion DWord by the CDMA or PDMA Descriptor Manager.

5.18.3.2.2.1 Intel® Block Protection Technology Unit

An Intel Block Protection Technology Unit (BGU) is integrated on the Host output data

path of the PDMA Engine to perform block guard operations on data from the Frame

Buffer Memory Controller Unit (FBMCU)-to-Host. Similarly, a BGU is integrated on the

FBMCU output data path of the PDMA Engine to perform block guard operations on data

from Host-to-FBMCU. Each BGU is capable of the Generation, Stripping, Updating, and

Verification of the Data Integrity fields (DIF) that can be embedded into the data

streams.

5.18.3.2.3 SMCU Overview

The Storage Controller Unit integrates two identical high performance, multi-ported

SRAM Memory Controller units (SMCU). The first SMCU, called Frame Buffer Memory

Controller Unit (FBMCU), is used to provide access to the on-chip frame buffer SRAM

Memory. The second SMCU, called Context RAM Controller (CRAMC), is used to provide

access to the on-chip context SRAM memory.

The SRAM Memory Controller supports:

• Error Correction Code (ECC)

— Single-bit error correction, multi-bit error detection

— 7-bit ECC across every DW data

• Read-modify-write when the byte enables for D W data to write are n ot all asserted.

• 256-bit wide SRAM Memory Interface with ECC protection

• 10 Read and 10 Write, Memory Port Interfaces (MPI)

— Each MPI is 128-bit wide with data parity protection

• Two request arbiters

— One for Read and one for W rite requests

•One MMR interface

— Decodes and accepts any MMR requests targeting the SMCU’s MMR space

• Interleav e read and w rite re ques ts in e very other SRAM memory clock to minimize

SRAM read latency

Functional Description

194 Intel® C600 Series Chipset and Intel® X79 Express Chipset

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The SRAM interface provid es a direct connection to a high bandwidth and reliable

memory subsystem. An 7-bit Error Correction Code (ECC) across every 32-bit word

improves system reliability.

5.18.3.2.4 Port Task Scheduler Overview

The key functions of the PTSG are to schedule outbound tasks to the appropriate

protocol engine to be executed by transport layer and post status to the driver through

SMU when the task is completed; manage SAS Port Layer functions, such as wide port

management and I_T Nexus Loss timeout management; handle other functions like

task timeout, task abortion, local port suspension, remote node suspension, etc.

Each PTSG includes the following major functional blocks:

• 4 Port Task Schedulers (PTS) - PTS schedules tasks to be executed by the TLs of

the configured port.

• 1 Port Configuration Switch (PCS) - This switch is configured by the Driver by

progr ammin g the MMRs through SMU after link initialization to map the PEs to a

particular PTS based on the information that was exchanged by the Identify

Address Frames.

• 1 Event Timeout Manager (ETM) - The Event Timeout Manager is responsible for

checking any active task that has timed out and also monitoring the I_T Nexus

timeout situation for the active remote node.

• 1 Task Schedule Context RAM (TSC RAM) - this memory is used by all the PTSs

within the PTSG to store TSCs for task scheduling.

• 1 Remote Node Schedule Context RAM (RNSC RAM) - this memory is used by all

the PTSs within the PTSG to store RNSCs for remote node scheduling.

The PTSG also manages the SAS port layer function that handles the SAS Wide Port

functionality. The PTS will ensure that the order of IO command frames sent to the

target port (as an initiator) will be the same order as the tasks issued by the driver

unless it is a high priority new command task.

5.18.3.2.5 Transport Layer Overview

The transport layer consists of five major sub-modules in the SCU. They are:

• Transport Layer Back End (TLBE)

The Transport Layer Back End provides a shared interface between the SDMA and

core TL blocks, and acts as a central arbiter for all Event Notifications within the

Protocol Engine Group (PEG).

• SSP Transport Layer Group (SSP TL)

• SMP Transport Layer Group (SMP TL)

• STP/SATA Transport Layer Group (STP TL)

• Transport Layer Front End (TLFE)

The Transport Layer Front End (TLFE) is located between the transport layers and

link layers. Its main function is to provide Context RAM access arbitration between

Transport and Link layer logic.

5.18.3.2.6 Link Layer Overview

The SCU Protocol engine (PE) supports SSP, SMP, STP and SATA Link Layer protocol

operations through a combination of protocol specific functions and common protocol

functions. The link layer manages frame transmission, frame reception, encoding/

decoding of characters, connection management, primitive sequence detection and

processing, and the protocol link flow control. The PE implements a common link layer

architecture that enables each link to operate with any of the supported protocols

based on OOB and connection assignments. The PE also implements a common

Connection manager used to manage SSP, SMP and STP connections automatically. The

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 195

Datasheet

link layer for each protocol engine also has common Out of Band sequence and Speed

Negotiation controls to perform SAS or SAT A operations. The PE link layers interfaces to

a common Frame Transmit and Frame Receive DMA controller that manages the

movement of frame data to FBMCU and from the AFE.

5.18.3.2.6.1 PE Link Layer Features

The following list of link layer functions are executed by the PE Link Layer.

• Out of Band sequence handling

•Speed Negotiation

• Frame Transmission

•Frame Reception

• Primitive Generation/Detection

— SAS Primitive sequences

— SATA Primitive sequences

•8b10b ENDEC

— SAS char acters

— SATA characters

• Scrambling/de-scrambling

—SSP, SMP

—STP, SATA

• SSP Link Layer functionality

—Initiator

• SMP Link Layer functionality

—Initiator

• STP/SATA Host Link Layer state machine

• SAS Link Connection Control

• Rate Matching

•Flow Control

—SSP

—SATA

• Frame Buffer data storage/retrieval

• 1.5/3.0 Link rate support

5.18.3.2.6.2 PE Link Layer Theory of Operation

After the SCU has been brought out of reset and the protocol transceivers have been

initialized the PE link layer is prepared to start oper ations. The device driver will enable

each protocol engine individually, this enable will start the automated link layer

operations for Out of Band (OOB) sequences and Speed Negotiation (SN) to perform

the Phy Reset Sequence. The OOB/SN manager will perform SAS OOB functions to

detect if a SAS device or a SATA device is present. The OOB/SN manager also provides

the mechanism for the device driver to initiate the transmission of the protocol based

Port Selector switching sequence. The OOB/SN manager will further conduct SAS or

SATA speed negotiation dependent upon the detection of a SAS PHY or SATA PHY.

Link initialization can be initiated independently for each protocol engine by the device

driver through a dedicated link initialization control register.

Functional Description

196 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.18.3.2.7 Staggered Spin-Up Control

The SCU needs supports Staggered Spin-Up as a feature, under the control of the

Driver. This allows the Driver to stagger when drives are spun-up, thus avoiding any

power surges that might overload a power supply.

The process for handling Staggered Spin-Up for a nominal start-up procedure is as

follows:

1. The Driver starts all links

2. On SATA links (detected by OOB), the LL will default to the SATA SPINUP HOLD

state.

3. On SAS links, the LL completes the entire start-up sequence. By default, the LL will

not send NOTIFY(ENABLE SPINUP) primitives.

4. The Driver walks through each link every X seconds (an OEM configured

paramete r), and sets LL registers to either start sending NOTIFY(ENABLE SPINUP)

or release the link from the SPINUP HOLD state, depending on whether the link is

SAS or SATA.

5.18.3.2.8 Discovery

The discovery process begins after Link Initialization is complete. The Driver is

responsible for discovering all SA S devices in the domain (determining the device type,

SAS address, and supported protocols), and configuring the devices if necessary (that

is, expander routing tables).

5.18.3.2.9 Port Configuration /SAS Address

After power up, the driver will assign the SAS address - usually the same local SAS

address (unless SCU is programmed to be SATA direct attached only) to all the links in

the Local SAS Address register in the Connection Manager.

5.18.4 SCU Physical Layer/PHY Overview

5.18.4.1 Introduction

The physical layer (Phy) integrated with the SCU is a four-port SAS/SATA transceiver

(called the Storage Phy - SPhy) supporting 1.5 Gbps and 3.0 Gbps with an Analog front-

end (AFE) and a Digital interface block (DIF). The PCH supports either a single

instantiation of the Sphy or a dual instantiation of the SPh y. The DIF block contains the

registers that control several aspects of the AFE.

5.18.4.2 SPhy Functionality & Features

SPhy Features

• Link rates of 1.5 Gbps and 3.0 Gbps.

• Meets SAS and SATA industry electrical requirements at all of the supported rates.

• BER of less than 1 x 10 -15

• 40-to-1 bit serializer and 1-to-40 bit de-serializer with embedded clock extraction.

• Independent transceiver operation with respect to protocol and data rate.

• Independent transmit and receive data rate s on a per-transceiver basis; this mode

is not part of normal SAS/SATA signaling, but it is utilized during speed negotiation.

• On-chip termination.

• Independent reset and power-down/enable controls for each receiver and each

transmitter.

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 197

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• OOB envelope detection with programmable threshold of OOB burst envelope

amplitude on a per-transceiver basis.

• Control for putting the transmitter into a DC idle state on a per-transceiver basis.

• Several loop-back modes: far-end retimed (in protocol engine), far-end digital (in

DIF), near-end analog (in AFE), and external analog (outside the package on the

PC board)

• 40-bit data path for each receiver and tr an smitter

• Comma sequence detection and notification for the protocol engine to manage the

link

• Disabling and enabling of comma sequence detection

• Spread-Spectrum Clocking (SSC) transmission is available on a per-transceiver

basis for SATA. SSC i s not available for SAS

• Controls for entering and exiting SAS and SATA Partial and Slumber power

management states on a per-transceiver basis

5.18.4.2.1 OOB Burst Detection and Control

In order to support the SAS and SATA protocol signaling requirements, the protocol

engine has ability to select OOB burst amplitude detection levels.

5.18.4.2.2 Transmit Amplitude Control

The transmitter control block supports the SAS and SATA protocol signaling

requirements by providing the protocol engine the ability to select transmitter

amplitude transmission levels on a per-transmitter basis using the register interface

and the table-based look-up structure of the transmitter.

5.18.4.2.3 Common Mode Voltage Control

The transmitter control block supports a function that allows the protocol engine to

individually place each transmitter into a DC idle state. The transmitter will place the

transmitter output driver into DC idle condition until the protocol engine or dictates a

transition into a new state.

5.18.4.2.4 Tx/Rx Bit Rate Selection

The transceivers support 1.5, and 3.0 Gbps by providing independent transmitter and

receiver rate selection control in each transceiver. This control also provides the ability

to transmit at one bit rate and receive data at a different bit rate.

5.18.4.2.5 Comma Detection Enable/Disable

The AFE receiver control block provides control to enable/disable notification to the

protocol engine that it has detected a comma sequence in the de-serialized bit stream.

This control also enables/disables the DW ord alignment functions in the receiver control

block allowing data to be transferred without interruption.

5.18.4.2.6 Reset and Power-Down

The SPhy supports the ability to reset and power-down each transceiver unit

independently.

5.18.4.2.7 Power Management States

The SATA power management states of Partial and Slumber are supported.

Functional Description

198 Intel® C600 Series Chipset and Intel® X79 Express Chipset

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5.18.4.2.8 Tx/Rx Data Loop Back Modes

The DIF block supports several modes and controls to loop-back data within the

transceiv er, thereby enabling the data stream between the transmitter and receiv er to

be connected to each other. The digital wr ap back, near end analog loop-back, far end

retimed loop-back, and far end digital loop-back capabilities are contained locally to

each transceiver; the external analog loop-back may occur between transceivers

depending upon HVM testing requirements. The DIF block supports controls to enable

implementation of a far-end retimed loop back mode within the SAS/SATA protocol

engine.

5.18.4.2.9 Reference Clocking Requirements

The AFE common block develops the PLL output clocks for each of the transceiver

blocks from a differential off-chip oscillator. The crystal oscillator shall be 100 MHz and

shall not have spread-spectrum clocking (SSC). The SPhy could share this reference

clock with any other interfaces on the same product as long as they do not require S SC.

5.18.5 Interrupts and Interrupt Coalescing

There are two types of interrupts:

Completion Queue Interrupt:

This interrupt can occur whenever the completion queue is not

empty. This interrupt is coalesced as explained below.

Error Interrupt: This interrupt indicates one or more error conditions have

occurred which will impact the Driver and SCU operation. This

causes an immediate interrupt.

5.18.5.1 Interrupts

The SMU implements support for both Legacy INTx interrupts and MSI -X interrupts.For

a multi-function device, including an IOV aware device, the interrupt logic is replicated

per function.

5.18.5.1.1 Legacy Interrupts

PCI Express implements a legacy INTx virtual wire interrupt signaling mechanism that

uses the Assert_INTx / Deassert_INTx semantics to convey the level sensitiv e nature of

traditional INTx# interrupt pins.

The “SCU PF Interrupt Pin Register (SCUPIPR)”, (see Section 16.2.1.22)specifies which

interrupt line is used for the normal runtime interrupt.

5.18.5.1.2 MSI-X Capability

If a host processor enables Message-Signaled Interrupts (MSI-X), the SMU is

responsible to signal interrupt to the host using a PCI write instead of generating an

Assert_INTx PCI Express* message.

The Interrupt Disable bit in the PCI Command Register does not affect the generation

of MSI-X interrupts.

Functional Description

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Datasheet

To signal an Interrupt with MSI-X enabled, a memory write transaction will be created

using the Message Address and the Message Data of the associated entry.

5.18.6 SMU Error and Event Generation

The SMU is the only unit that will generate the Error interrupt. All other SCU units will

signal detected ‘errors’ using an ‘Event Notification’.

5.18.6.1 Event Generation

For most errors, the SMU will generate an Ev ent Notification using the affected Address

Modifier to direct the event to the appropriate Completion Queue. Some events are

directed to the physical function (PF) and are indicated in the description.

The SMU generates the following errors:

• Uncorrectable Error on read of PCQ (Uncorr_PCQ_Rd)

This Event is generated by the Post Context Queue(PCQ) processing logic

• Invalid Context Command Error (Invalid_Context_Cmd)

This Event is generated by the Post Context Queue processing logic and is the

result of an Invalid Context Command, an index out of range, or an RNC command

by a Virtual Function.

• Parity Error Detected on write to SMU (Uncorr_Reg_Wr)

This error is detected by the MMR interface logic and is the result of receiving a

PCIe poisoned TLP, or the result of internal parity corruption.

• Uncorrectable error on read of HTTLBAR, HTTUBAR, and TCR or MSI-X MT_MLAR,

MT_MUAR, and MT_MDR (Uncorr_Reg_Rd)

Above registers are implemented in a RAM and a double-bit ECC error during a

read of the Host Task Table or MSI-X registers will result in an event notification.

The SMU also receives status information from the PCIe Interface and converts it to an

event notification:

• Function Level Reset (Function_Level_Reset)

This is an indication that the Initiate FLR bit has been set in the PCIe Configuration

Space of a VF. When a rising edge is detected on the FLR signal from the PCIe

Configuration Space, the SMU will:

— Generate a Critical Notification to the physical function (PF). Note that an FLR

to the PF will not generate an Event Notification.

This event will also trigger the Function Level reset mechanism defined in

Section 5.18.9.

Figure 5-16. MSI-X Generation

SMU

MSI-X Message

Edge Detect

Logic

Pending Bit Array

MSI-X Message

Generation

MSI-X Enable

Error Inte rr u p t

No r mal Interrupt

Function Mask

Per Vector Mask

Functional Description

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5.18.6.2 Error Interrupt

• Uncorrectable Error on read of CQLBAR, or CQUBAR.

Above registers are implemented in a RAM and a double-bit ECC error during a read

of the Completion Queue BAR can not be signalled as an event.

• Completion Queue Suspended

This condition should not occur under normal operations and is likely the result of a

progr amming error.

5.18.7 Host Interface Error Conditions

The SCU adheres to the error conditions defined within the PCI Express* specification

for both requester and completer operation.

IOSF (PCH’s On-Chip System Fabric) and PCI Express* error conditions cause the SCU

to log header information and to set status bits to inform error handling code of the

exact cause of the error condition. PCI Express* classifies errors as Correctable or

Uncorrectable. Since all PCI Express* Correctable errors are link related (and the SCU

does not contain a link) the SCU does not detect any PCI Express* Correctable errors

(all errors are detected as Uncorrectable).

The following is a simplified summary of the flow . The entire flow is outlined in detail in

Figure 5-17.

First determine the Severity of the Uncorrectable error (Fatal or Non-Fatal). The

Severity of each error type is defined by the programming of bits in the “SCU PF PCI

Express* Uncorrectable Error Severity (SCU P I ERRUNC SEV)” register. (see

Section 16.2.5.4)

•Fatal:

Log (if enabled).

Send ERR_FATAL message (if enabled).

•Non-Fatal: Determine whether the error can be considered Advisory or not. This is

done in an SCU implementation-specific manner. Errors are generally considered

Advisory if the other party in the transaction is better suited to handling/reporting

the error (such as, Unsupported Request) in a non-posted transaction (in this case

the original requester will receive UR in the completion status and can decide what

the appropriate error recovery/reporting mechanism should be).

—Advisory:

Log (if enabled).

Send ERR_COR message (if enabled).

—Non-Advisory:

Log (if enabled).

Send ERR_NONFATAL message (if enabled).

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 201

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Figure 5-17. Uncorrectable Error Signalling and Logging Flowchart

Advisory?

Set corresponding bit in

Uncorrectable Erro r Status Reg [VF i **]

Masked in

Uncorrectable Error

Mask Reg [PF]?

If First Error Pointer [VFi **] not valid, update First

Error Pointer [VFi **] and Header Log Reg [VFi **]

Severity?

Send ERR_FATAL Msg Send ERR_NONFATAL Msg

END

END END

Set Correctable Error Detected bit in

Device Status Reg [VFi **]

Set Advisory-Non-Fatal bit in

Correctable Error Status R eg [VFi **]

Advisory

Masked in

Correctable Error

Mask Reg [PF]?

(Error is UR AND

DCR.URRE= 0) or

Unaffiliated ?

DCR.CERE = 1?

END

Yes

Yes Yes

Yes

Yes Yes

Uncorrectable E rror De t e ct e d

Severity?

Non-Fatal

Fatal

Non-FatalFatal

Set corresponding bit in

Uncorrectable Error Status reg [VFi **]

Masked in

Uncorrectable Error

Mask Reg [PF]?

(CMD.SERR_EN = 1 or

DCR.NERE) = ?

(CMD.SERR_EN = 1 or

DCR.FERE) = ?

(Error is UR AN D

DCR.URRE = 0 AND

CMD.SERR_EN = 0) or

Unaffili ated ?

Send ERR_COR Msg

Yes

Set Non-Fa ta l Er ro r D ete cted bit in

Device Status Reg [VFi **]

Set Fatal Error Detected bit in

Device Status Reg [VFi **]

If UR, set Unsupported Request Detected bit in

Device Status Reg [VFi **]

Determine the severity according to

Unco rrectabl e Error Se v er ity Reg [P F ]

If First E r ro r Po in te r [ V Fi ** ] no t v alid, up dat e F i rs t

Error Pointer [VFi **] and Header Log Reg [VFi **]

Note: [VFi **]

Unaffiliated: Use the [PF]

Affiliated : Use appropriate [VFi]

Functional Description

202 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

The following sections detail all error conditions on the PCI Express/IOSF.

5.18.7.1 Unaffiliated Errors (Non-Function-Specific Errors)

Unaffiliated errors are those which cannot be unambiguously associated with a single

function. for example, a Memory tr ansaction which misses all of the Memory BARs of all

of the functions (PFs and VFs) in the endpoint.

5.18.7.1.1 Malformed

Note that per the PCI Express* specification all malformed TLPs are treated as

unaffiliated errors. The following checks are made to detect malformed TLPs.

• Data Payload exceeds the length specified by the value in the Max_Payload_Size

field of the Device Control Register.

— This error will be detected by the Integrated Device Fabric (IDF).

• Transactions having reserved combinations of Fmt and Type Field, that is, all

commands not in the following set:

— MRd32, MRd64, LTM Rd32, LTMRd64, MRdLk32, MRdLk64,

MWr32, MWr64, LTMWr32, LTMWr64,

IORd, IOWr,

CfgRd0, CfgWr0, CfgRd1, CfgWr 1,

Msg, MsgD,

Cpl, CplD, CplLk, CpDLk

— The SCU instead handles this as an Unexpected Completion.

5.18.7.1.2 Unaffiliated Unsupported Requests (UR)

The following checks are made to detect unaffiliated Unsupported Requests:

• Memory or IO transactions which fail to match any of the active Memory or I/O

BARs.

• Configuration requests which fail to target a valid function.

• Certain types of Messages which go unclaimed as stated in the rules in

Section 5.18.8.

5.18.7.1.3 Unaffiliated Unexpected Completions

The following checks are made to detect unaffiliated Unexpected Completions:

• Completions in which the Requester ID (Bus#, Dev# Fn#) does not target an y valid

function (PF or VF).

5.18.7.2 Affiliated Errors (Function-Specific Errors)

Affiliated errors are those which can be unambiguously associated with a single

function. F or example, a Memory transaction which hits a Memory BAR of a function (PF

or VF) in the endpoint but violates the programming model of that function. Affiliated

cases are handled entirely by the endpoint.

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 203

Datasheet

5.18.7.2.1 Affiliated Unsupported Requests (UR)

The following checks are made to detect affiliated Unsupported Requests:

• Certain types of Messages which are claimed but treated as UR as stated in the

rules in Section 5.18.8.

• Poisoned I/O or Configuration write request (EP bit set).

• Configuration write with an IOSF data parity error.

• Memory or I/O transaction while in a non-D0 power state.

• MRdLk32/64, LTMrd32/64, LTMwr32/6 4 transactions.

5.18.7.2.2 Completer Abort (CA)

Completer Aborts are transactions which violate the programming model of the SCU.

The following checks are made to detect Completer Aborts:

• Memory transactions which target the Memory Controllers and which cross a 16B

aligned boundary.

• Memory transactions which target the MSI-X table and which cross a 16B aligned

boundary.

• Memory transactions which target registers and wh ich cross a 4B aligned boundary.

These requests must first have passed the Malformed TLP checks as well as the

Unsupported Request checks.

5.18.7.2.3 Affiliated Unexpected Completions

Completions are considered affiliated when the Requester ID (Bus#, Dev# Fn#) targets

a valid function (PF or VF). The following checks are made to detect affiliated

Unexpected Completions. In all the following error cases the completion data is

discarded (not sent to the SDMA).

• The Tag does not match that of any outstanding non-posted request performed by

the SCU as the Initiator.

• TC /= 0.

• The Status of a completion without data is other than Successful, CA or UR.

• Locked Completions (CplLk, CplDLk).

• Completion with data for which the length exc e ed s th e remaining length expecte d

for the outstanding non-posted request.

5.18.7.2.4 Poisoned Completion or Poisoned Posted Memory Write

A completion or posted memory transaction is considered poisoned if the EP bit is set.

• Poisoned Completions are passed through to the SDMA with bad parity.

• Poisoned Memory Writes are passed through to the SMU with bad parity.

Poisoned TLPs received for I/O or Configuration Writes are treated as URs.

5.18.7.2.5 Completion Timeout

A completion timeout occurs when an outstanding non-posted request initiated by the

SCU fails to receive all of its completion data within the completion timeout period

(16 ms to 32 ms).

Functional Description

204 Intel® C600 Series Chipset and Intel® X79 Express Chipset

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5.18.7.3 Data Parity Error on the Integrated Device Fabric (IDF)

Data parity will be forwarded to the internal units (SMU or SDMA). The SCU will indicate

the error to the SCU driver.

5.18.8 Host Interface Messages Received

The following sections describe how the SCU handles PCI-Express messages as a

target. Any message which goes unclaimed by all enabled functions on the Integrated

Device Fabric (IDF) will be logged in all enabled physical functions as an unaffiliated

Unexpected Request (UR) with the exception of PME_TO.

5.18.8.1 Messages Routed by ID

• If the Routing ID (RID) fails to match any enabled SCU fu nction (PF or VF) then the

SCU will not claim the transaction.

• If the RID matches one of the enabled SCU functions, then the transaction will be

claimed and:

— Type-1 Vendor Defined Messages (VDMs) are silently dropped.

— Others are dropped and are logged as UR.

5.18.8.2 Messages Routed by Broadcast

• Type-1 VDMs are claimed and silently dropped.

• UNLOCK is claimed and silently dropped.

•PME_TO is not claimed.

• Others are claimed, dropped and are logged as UR.

5.18.8.3 All other Messages

All other message formats are not claimed by the SCU.

5.18.9 Reset

5.18.9.1 Fundamental Reset

Fundamental Reset is a hardw are mechanism for setting or returning the PCI Express*

Port states and all MMR registers to their default condition. The fundamental reset can

be generated through:

•Primary Reset, or

• Secondary Bus Reset

5.18.9.2 Function Level Reset (FLR)

Function level reset is initiated by a configuration write which sets the Initiate FLR bit in

“SCU VF PCI Express* Device Control R egister x (SCU V I EXP DCTL x)” (VF, see

Section 16.3.3.5) or “SCU PF PCI Express* Device Control Register

(SCUPIEXPDCTL)” (PF, see Section 16.2.4.5). An FLR to a VF resets only that VF.

Other VFs and the PF are unaffected (SR-IOV continues to operate).

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 205

Datasheet

5.18.9.2.1 Function Level Reset (Virtual Function)

When the Initiate FLR bit is set, in the “SCU VF PCI Express* Device Control Register x

(SCU V I EXP DCTL x)” (VF, see Section 16.3.3.5) the SMU will reset a subset of the VF

MMR registers and generate an Event Notification to the master Driver in the physical

function (PF) indicating that it should abort all outstanding tasks and re-initialize the

VF.

5.18.9.2.2 Function Level Reset (Physical Function)

When the Initiate FLR bit is set, in the “SCU PF PCI Express* Device Control Register

(SCUPIEXPDCTL)” (PF, see Section 16.2.4.5) a hardware reset is asserted to all of

the SCU (except for the IOSF interface). Therefore, the SMU, SDMA, and PEG are all

reset.

5.18.10 SGPIO

5.18.10.1 Overview

This chapter describes the Serial General Purpose Input Output (SGPIO) Unit that is

used in the Storage Controller Unit (SCU). The SCU is organized into Protocol Engine

Groups (PEGs). Each Protocol Engine Group (PEG) can support up to four Protocol

Engines (PEs). Each PEG supports one SGPIO unit. The SGPIO unit also provides a

feature that allows two PEGs to use a single SGPIO unit. However, this feature is only

valid in SGPIO (serial) mode of operation. Therefore, the SGPIO unit can support up to

eight devices.

The SGPIO is a serial bus consisting of four signals: SClock, SLoad, SDataOut, and

SDataIn. The SGPIO is used to serialize general purpose I/O signals. The SGPIO defines

communication between an initiator and a target. The target typically converts output

signals into multiple parallel LED signals and provides inputs from general purpose

inputs. Figure 5-1 shows th e SGPIO bus. A target typically consists of multiple devices,

and SGPIO protocol allows each device on the target to support up to three output and

three input signals.

The SGPIO interface on the SCU can support up to eight devices (drives) on the target

end. Each device can control up to three outpu t bits and three input bits. Therefore, the

SGPIO interface on the SCU can support up to twenty-four input signals and twenty-

four output signals.

Figure 5-18. SGPIO Bus Overview

Initiator

SClock

SLoad

SDataOut

SDataIn

Target

Device

Functional Description

206 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.18.10.2 Theory of Operation

The SGPIO is used to serialize general purpose I/O signals. For example, the initiator

may want to drive multiple LEDs on the target, and thus do so by sampling and

serializing the parallel initiator LED signals at a fix ed sampling rate dictated by the low-

to-high transition of the SLoad signal. Note that SClock is a free-running clock. The

receiver (initiator or target) would then take the bit samples from the bit stream and

converts them into parallel LED signals.

Figure 5-19 shows the input and output bit streams relative to SClock and SLoad

signals. Note that the SGPIO interface sends a repeating bit stream on SDataOut and

receives a repeating bit stream SDataIn. The bit stream is restarted each time the

SLoad signal is set high. Note that the example in Figure 5-19 shows four drives and

five drives. The bit stream need not be the same length every time.

5.18.10.2.1 SGPIO SClock Output Signal

SClock is a free-running clock running at a fix ed frequency of up to 100 KHz. The rising

edge of SClock is used to transmit SLoad, SDataOut, and SDataIn. The falling edge of

SClock is used to latch SLoad, SDataOut, and SDataIn.

5.18.10.2.2 SGPIO SLoad Output Signal

The initiator shall repeatedly send SDataOut bits and receives SDataIn bits. The SLoad

signal indicates when the bit stream is ending or being restarted. After SLoad is

asserted (set to 1), the next four bits positions on SLoad contain a vendor-specific

pattern. Following the vendor-specific pattern, the initiator shall set the SLoad to 0 until

it wants to restart the bits stream.

Figure 5-19. SGPIO Repeating Bit Stream

SClock

SLoad

SDataOut

SDataIn

Drive 0 Drive 1 Drive 2 Drive 3 Drive 0 Drive 1 Drive 2 Drive 3 Drive 4

Bit Stream Bit Stream

Figure 5-20. SLoad Signal

0's

Bit 0

Vendor-Specific Bit 1

Vendor-Specific Bit 2

Vendor-Specific Bit 3

Vendor-Specific

1 Vendor-Specific

….

Functional Description

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Datasheet

5.18.10.2.3 SDataOut

The SDataOut signal carries output bits associated with devices on the target. For

example, on the SCU the SGPIO can drive up to three bits per device and up to eight

devices on the target, thus is able to control twenty-four outputs on the target. The

SDataOut signal carries the 3-bit outputs for each device in the same order in each

repeated bit stream.

5.18.10.2.4 SGPIO SDataIn Signal

The SDataIn signal carries input bits associated with devices on the target. For

example, on the SCU the SGPIO can receive up to three bits per device and up to eight

devices on the target, thus is able to receive twenty-four inputs from the target. The

SDataIn signal carries the 3-bit inputs for each device in the same order in each

repeated bit stream.

5.18.10.3 Clock Requirements

The SCU generates and drives three clock signals that are used to run the various

blocks of the SGPIO units.

• SClock - is the output clock of the SGPIO interface and runs at a either 49.9 KHz or

99.8 KHz.

• Load Clock - this clock is used internally to load the internal latches. This clock runs

at 1/12 or 1/24 the SClock rate.

• Blink Generator Clock - this clock is used to drive the blink generator. This clock

runs at 1/12500 of the SClock rate.

Figure 5-23 shows the clock structure.

Figure 5-21. SDataOut Signal

De vice 0

Bit0

De vice 0

Device 0

Bit1 Device 0

Bit2 Device1

Bit0

De vice 1

Device1

Bit1 Device1

Bit2

De vice N-1

Bit1 Device N-1

Bit2

….De vice N-1

Bit0

Figure 5-22. SDataIn Signal

De vice 0

Bit1 Device 0

Bit2 Device 1

Bit0

Device 1

De vice 1

Bit1 Device 1

Bit2

De vice N-1

Device N-1

Bit1 Device N-1

Bit2

….De vice N-1

Bit0

De vice 0

Bit0

Functional Description

208 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.18.10.4 Output Signals

The SGPIO unit can support up to eight drives, and each drive can support up to three

output signals. This allows the SGPIO unit to be able to drive up to twenty-four output

signals.

The SGPIO supports the following output signals:

•Fixed High

•PE Activity, PE Status, or Reserved

• Two programmable Blinks (A and B)

In addition the outputs can be optionally inverted.

Each output bit can be independently selected using the “SGPIO Output Data Select

“SGPIO Output Data Select Register[0:7]”.

Figure 5-24, Figure 5-25, and Figure 5-26 respectively show the three output signals

supported per drive (OD0, OD1, and OD2) and the supported output signal selections.

Figure 5-23. Clock Structure

1/1503

Drives Latches

Blink Rate

Generator

8 Hz

SClock

150 MHz 99.8 KHz

1/24

1/12500

49.9 KHz

1/2

1/12 Bit 2 of SGICR x

Bit 1 of SGICRx

Functional Description

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Figure 5-24. SGPIO Output OD0 Signal

Figure 5-25. SGPIO Output OD1 Signal

Output Signal (OD0)

Fixed High

FSENG Activity

Programmab l e Pattern A

Programmab l e Pattern B

Inverting

Logic

(XOR)

Control bit 2 in SGODSR[0:7]x

Control bits[1:0] in SGODSR[0:7]x

JOG Logic C ontrol bit 3 in SGODSR[0:7]x

Pre-Conditioning Logic

Output Signal ( OD1)

Fixed High

FSENG Status

Programmab l e Pattern A

Programmab l e Pattern B

Inverting

Logic

(XOR)

Control bit 6 in SGODSR[0:7]x

Control bits[5:4] in SGODSR[0:7]x

JOG Logic C ontrol bit 7 in SGODSR[0:7]x

Pre-Conditioning Logic

Functional Description

210 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.18.10.5 SCU Input Signals

Each SCU PEG (Protocol Engine Group) supports one SGPIO unit. And each PEG can

support up to four PEs (Protocol Engines). The SGPIO unit is designed to accommodate

up to two PEGs (eight PEs). For example, the SGPIO unit can support eight sets of

drives inputs. Note that each drive input set supports three inputs OD[2:0]. The lower

four sets of drive inputs are driven by the local PEG, whereas the upper four sets of

drive inputs are driven by the other PEG (or other SCU). Each PE drives two signals:

activity (PE_ACT) and status (PE_STA T). Each PE_ACT/PE_STA T pair is driv en to one of

the SGPIO unit drive inputs. These PE activity and status signals can be selected as

optional output signals of the SGPIO unit that can be driven serially on the SDataOut

pin or on the direct LED signals. Refer to Figure 5-24 and Figure 5-25 for the output

selections. Table 5-48 shows how the input signals are mapped to the ODx inputs of the

SGPIO unit.

Figure 5-26. SGPIO Output OD2 Signal

Output Signal (OD2)

Fixed High

Reserved

Programmab l e Pattern A

Programmab l e Pattern B

Inverting

Logic

(XOR)

Control bit 10 in SGO D SR[0:7]x

Control bits[9:8] in SGODSR[0:7]x

JOG Logic Control bit 11 in SGODSR[0:7]x

Pre-Conditioning Logic

Table 5-48. SGPIO Input Mapping (Sheet 1 of 2)

Input Signals SGPIOx Inputs Input Signals SGPIOx Inputs

Fixed High

Drive0.OD0

Fixed High

Drive4.OD0

PE Activity [0] Other PEG, PE Activity [0]

Programmable Pattern A Programmable Pattern A

Programmable Pattern B Programmable Pattern B

Fixed High

Drive0.OD1

Fixed High

Drive4.OD1

PE Status [0] Other PEG, PE Status [0]

Programmable Pattern A Programmable Pattern A

Programmable Pattern B Programmable Pattern B

Functional Description

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Fixed High

Drive0.OD2

Fixed High

Drive4.OD2

Reserved Reserved

Programmable Pattern A Programmable Pattern A

Programmable Pattern B Programmable Pattern B

Fixed High

Drive1.OD0

Fixed High

Drive5.OD0

PE Activity [1] Other PEG, PE Activity [1]

Programmable Pattern A Programmable Pattern A

Programmable Pattern B Programmable Pattern B

Fixed High

Drive1.OD1

Fixed High

Drive5.OD1

PE Status [1] Other PEG, PE Status [1]

Programmable Pattern A Programmable Pattern A

Programmable Pattern B Programmable Pattern B

Fixed High

Drive1.OD2

Fixed High

Drive5.OD2

Reserved Reserved

Programmable Pattern A Programmable Pattern A

Programmable Pattern B Programmable Pattern B

Fixed High

Drive2.OD0

Fixed High

Drive6.OD0

PE Activity [2] Other PEG, PE Activity [2]

Programmable Pattern A Programmable Pattern A

Programmable Pattern B Programmable Pattern B

Fixed High

Drive2.OD1

Fixed High

Drive6.OD1

PE Status [2] Other PEG, PE Status [2]

Programmable Pattern A Programmable Pattern A

Programmable Pattern B Programmable Pattern B

Fixed High

Drive2.OD2

Fixed High

Drive6.OD2

Reserved Reserved

Programmable Pattern A Programmable Pattern A

Programmable Pattern B Programmable Pattern B

Fixed High

Drive3.OD0

Fixed High

Drive7.OD0

PE Activity [3] Other PEG, PE Activity [3]

Programmable Pattern A Programmable Pattern A

Programmable Pattern B Programmable Pattern B

Fixed High

Drive3.OD1

Fixed High

Drive7.OD1

PE Status [3] Other PEG, PE Status [3]

Programmable Pattern A Programmable Pattern A

Programmable Pattern B Programmable Pattern B

Fixed High

Drive3.OD2

Fixed High

Drive7.OD2

Reserved Reserved

Programmable Pattern A Programmable Pattern A

Programmable Pattern B Programmable Pattern B

Table 5-48. SGPIO Input Mapping (Sheet 2 of 2)

Input Signals SGPIOx Inputs Input Signals SGPIOx Inputs

Functional Description

212 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.18.10.5.1 JOG Requirements

The jog feature is optional and is controlled by the “SGPIO Output Data Select

signal is detected low for about 4 seconds it will be forced high for a 250 ms duration.

5.18.10.5.2 SCU Drive Pre-Conditioning Requirements

All the SCU activity and status signals are pre-conditioned when entering the SGPIO

units. The pre-conditioning logic monitors for any short pulse or any high frequency

input signal and ensures that the input signal is stretched and held high for at least

125 ms.

5.18.10.5.3 Programmable Blink Patterns

Each of the SGPIO output signal supports two programmable blink patterns that can be

selected using the “SGPIO Output Data Select Register[0:7]”. The blink rate generator

is clocked using an 8 Hz clock and allows the user to program a low and a high duration

time using two 4-bit fields located in the “SGPIO Programmable Blink Register. The

shortest low/high duration time that can be program is 125 milliseconds and the

longest low/high duration time that can be programmed is 2 seconds. The shortest

blink rate period is 250 milliseconds and the longest blink rate period is 4 seconds.

5.18.10.6 SGPIO Serializer Modes of Operations

The SGPIO serializer supports the following modes simultaneously:

• Direct (parallel) LED mode (up to 8 LEDs; Drives[3:0], OD[1:0])

• SGPIO (serial) mode (up to 24 LEDs; Drives[7:0], OD[2:0])

The SGPIO serializer requires up to 8 pins to support the direct drive mode and 4 pins

to support the serial mode of operation.

A Drive-Position multiplexer block provides the abilit y to route any input Driv e number

to any output Drive number before being driven to the shift register and to the direct

LED signals (refer to Figure 5-27). Note, all three signals of a Drive are routed

simultaneously.

Note that the SGPIO unit can support up to 3 LEDs per PE and up to eight PEs in SGPIO

(serial) mode. However, the Direct parallel LED mode can only support 2 LEDs per PE

and four PEs.

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 213

Datasheet

5.18.10.7 Serial Pin Multiplexing

The SGPIO unit’s serial pins also support a Direct (parallel) Activity LED mode.

Figure 5-28 shows how the SGPIO unit signals are used and multiplexed. Bit 0 of the

“SGPIO Interface Control Register” is used to select between the SGPIO (serial) mode

and the direct Activity LED (parallel) mode, and by default bit 0 selects the parallel

mode.

Figure 5-27. Output Signal Routing

OD0

Multiplexer Block (Drive Position Selector)

24x (8 -to -1 )

Not e 1 : Only OD0 a n d O D1 o f th e low e r fo ur s e ts o f t he Multiplexer

B lo ck ou tp u ts a re dr ive n t o t he Direc t L E D p ins.

Input 7 Input 0

Bit 23 Bit 22 Bit 21 Bit 1 Bit 0Bit 2

OD1

Control bits from SGSDRx

Shift Register

OD1OD2OD0OD1OD2 OD0

Input 3

Bit 10 Bit 9Bit 11

OD1OD2

OD0

Inp ut 4

Bit 13 Bit 12Bit 14

OD1OD2

Output 0

OD1 OD0OD2

Output 3

OD1 OD0OD2

Output 4

OD1 OD0OD2

Output 7

OD1 OD0OD2

To SDa taOut

Bit 23 Bit 22 Bit 21 Bit 1 Bit 0Bit 2Bit 10 Bit 9Bit 11Bit 13 Bit 12Bit 14

OD0

OD1

To Direct

LED Signals

Bit 23 Bit 22 B it 21 Bit 1 Bit 0Bit 2Bit 10 Bit 9Bit 11Bit 13 Bit 12Bit 14

Other PEG PE3 PE0PE3Other PEG PE0

Not e 2 : T h e M u ltip le x er B loc k o n ly allo w s s te er ing a n en tire Input X set

to a n O u tp ut Y se t.

Functional Description

214 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.19 High Precision Event Timers (HPET)

This function provides a set of timers that can be used by the operating system. The

timers are defined such that in the future, the operating system may be able to assign

specific timers to be used directly by specific applications. Each timer can be configured

to cause a separate interrupt.

PCH provides eight timers. The timers are implemented as a single counter, and each

timer has its own comparator and value register. The counter increases monotonically.

Each individual timer can generate an interrupt when the value in its value register

matches the value in the main counter.

The registers associated with these timers are mapped to a memory space (much like

the I/O APIC). However, it is not implemented as a standard PCI function. The BIOS

reports to the operating system the location of the register space. The hardware can

support an assignable decode space; however, the BIOS sets this space prior to

handing it over to the operating system. It is not expected that the operating system

will move the location of these timers once it is set by the BIOS.

5.19.1 Timer Accuracy

1. The timers are accurate over any 1 ms period to within 0.05% of the time specified

in the timer resolution fields.

2. Within any 100 microsecond period, the time r reports a time that is up to two ticks

too early or too late. Each tick is less than or equal to 100 ns, so this represents an

error of less than 0.2%.

3. The timer is monotonic. It does not return the same value on two consecutive

reads (unless the counter has rolled over and reached the same value).

Figure 5-28. SCU SGPIO Unit Pin Mapping

S_AC T [2] / S_A _D A TA IN

S_ACT[3] / S_A_DATA O UT

S_ACT[0] / S_A_CLOCK

S_ACT[1] / S_A_LOAD

SDATAOUT

SLOAD

SCLOCK

ACT[3]

ACT[1]

ACT[0]

ACT[2]

Control bit 0 of the

SGICCR0 R egister

ACT[2]

SDATAOUT

STAT[1]

SLOAD

ACT[0]

SCLOCK

STAT[0]

STAT[3]

STAT[2]

ACT[1]

ACT[3]

PE_STAT[1]

PE_STAT[0]

PE_STAT[3]

PE_STAT[2]

PE_ACT[1]

PE_ACT[0]

PE_ACT[3]

PE_ACT[2]

SGPIO Unit

Dr4 OD1 in

Dr5 OD1 in

Dr6 OD1 in

Dr7 OD1 in

Dr4 OD0 in

Dr5 OD0 in

Dr6 OD0 in

Dr7 OD0 in

Dr0 OD1 in

Dr1 OD1 in

Dr2 OD1 in

Dr3 OD1 in

Dr0 OD0 in

Dr1 OD0 in

Dr2 OD0 in

Dr3 OD0 in

Dr1 OD0 out

Dr2 OD1 out

Dr1 OD1 out

Dr0 OD1 out

Dr2 OD0 out

Dr0 OD0 out

Dr3 OD1 out

Dr3 OD0 out

Other PEG/SCU Signals

Default Mapping of input to output for Direct LED

Direct LED Signals

PE_STAT[1]

PE_STAT[0]

PE_STAT[3]

PE_STAT[2]

PE_ACT[1]

PE_ACT[0]

PE_ACT[3]

PE_ACT[2]

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 215

Datasheet

The main counter is clocked by the 14.31818 MHz clock, synchronized into the

66.666 MHz domain. This results in a non-uniform duty cycle on the synchronized

clock, but does have the correct av erage period. The accur acy of the main counter is as

accurate as the 14.31818 MHz clock.

5.19.2 Interrupt Mapping

The interrupts associated with the various timers have several interrupt mapping

options. When reprogramming the HPET interrupt routing scheme (LEG_RT_CNF bit in

the General Conf iguration R egister), a spurious interrupt may occur. This is because the

other source of the interrupt (8254 timer) may be asserted. Software should mask

interrupts prior to clearing the LEG_RT_CNF bit.

Mapping Option #1 (Legacy Replacement Option)

In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is set. This forces the

mapping found in Table 5-49.

Note: The Legacy Option does not preclude delivery of IRQ0/IRQ8 using processor message interrupts.

Mapping Option #2 (Standard Option)

In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is 0. Each timer has its

own routing control. The interrupts can be routed to various interrupts in the 8259 or

I/O APIC. A capabilities field indicates which interrupts are valid options for routing. If a

timer is set for edge-triggered mode, the timers should not be share with any PCI

interrupts.

For the PCH, the only supported interrupt values are as follows:

Timer 0 and 1: IRQ20, 21, 22 & 23 (I/O APIC only).

Timer 2: IRQ11 (8259 or I/O APIC) and IRQ20, 21, 22 & 23 (I/O APIC only).

Timer 3: IRQ12 (8259 or I/O APIC) and IRQ 20, 21, 22 & 23 (I/O APIC only).

Interrupts from Timer 4, 5, 6, 7 can only be delivered using processor message

interrupts.

Mapping Option #3 (Processor Message Option)

In this case, the interrupts are mapped directly to processor messages without going to

the 8259 or I/O (x) APIC. To use this mode, the interrupt must be configured to edge-

triggered mode. The Tn_PROCMSG_EN_CNF bit must be set to enable this mode.

When the interrupt is delivered to the processor, the message is delivered to the

address indicated in the Tn_PROCMSG_INT_ADDR field. The data va l ue for the write

cycle is specified in the Tn_PROCMSG_INT_VAL field.

Table 5-49. Legacy Replacement Routing

Timer 8259 Mapping APIC Mapping Comment

0 IRQ0 IRQ2 In this case, the 8254 timer will not

cause any interrupts

1 IRQ8 IRQ8 In this case, the RTC will not cause any

interrupts.

2 & 3 Per IRQ Routing

Field. Per IRQ Rou ting Field

4, 5, 6, 7 not available not available

Functional Description

216 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Notes:

1. The processor message interrupt delivery option has HIGHER priority and is

mutually exclusive to the standard interrupt delivery option. Thus, if the

Tn_PROCMSG_EN_CNF bit is set, the interrupts will be delivered directly to the

processor rather than via the APIC or 8259.

2. The processor message interrupt delivery can be used even when the legacy

mapping is used.

3. The IA-PC HPET Specification uses the term “FSB Interrupt” to describe these type

of interrupts.

5.19.3 Periodic versus Non-Periodic Modes

Non-Periodic Mode

Timer 0 is configurable to 32 (default) or 64-bit mode, whereas Timers 1:7 only

support 32-bit mode (See Section 21.1.5).

Warning: Software must be careful when programming the comparator registers. If the value

written to the register is not sufficiently far in the future, then the counter may pass

the value before it reaches the register and the interrupt will be missed. The BIOS

should pass a data structure to the OS to indicate that the OS should not attempt to

program the periodic timer to a rate faster than 5 microseconds.

All of the timers support non-periodic mode.

Refer to Section 2.3.9.2.1 of the IA-PC HPET Specification for more details of this

mode.

Periodic Mode

Timer 0 is the only timer that supports periodic mode. R efer to Section 2.3.9.2.2 of the

IA-PC HPET Specification for more details of this mode.

If the software resets the main counter, the value in the comparator’s value register

needs to reset as well. This can be done by setting the TIMERn_VAL_SET_CNF bit.

Again, to avoid race conditions, this should be done with the main counter halted. The

following usage model is expected:

1. Software clears the ENABLE_CNF bit to pre v e n t an y i nterrupts

2. Software Clears the main counter by writing a value of 00h to it.

3. Software sets the TIMER0_VAL_SET_CN F bi t.

4. Software writes the new value in the TIMER0_COMPARATOR_VAL register

5. Software sets the ENABLE_CNF bit to enable interrupts.

The Timer 0 Comparator Value register cannot be programmed reliably by a single

64-bit write in a 32-bit environment except if only the periodic rate is being changed

during run-time. If the actual Timer 0 Comparator Value needs to be reinitialized, then

the following software solution will always work regardless of the environment:

1. Set TIMER0_VAL_SET_CNF bit

2. Set the lower 32 bits of the Timer0 Comparator Value register

3. Set TIMER0_VAL_SET_CNF bit

4. Set the upper 32 bits of the Timer0 Comparator Value register

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 217

Datasheet

5.19.4 Enabling the Timers

The BIOS or operating system PnP code should route the interrupts. This includes the

Legacy Rout bit, Interrupt Rout bit (for each timer), and interrupt type (to select the

edge or level type for each timer)

The Device Driver code should do the following for an available timer:

1. Set the Overall Enable bit (Offset 10h, bit 0).

2. Set the timer type field (selects one-shot or periodic).

3. Set the interrupt enable

4. Set the comparator value

5.19.5 Interrupt Levels

Interrupts directed to the internal 8259s are active high. See Section 5.10 for

information regarding the polarity programming of the I/O APIC for detecting internal

interrupts.

If the interrupts are mapped to the 8259 or I/O APIC and set for level-triggered mode,

they can be shared with PCI interrupts. They may be shared although it’s unlikely for

the operating system to attempt to do this.

If more than one timer is configured to share the same IRQ (using the

TIMERn_INT_ROUT_CNF fields), then the software must configure the timers to level-

triggered mode. Edge-triggered interrupts cannot be shared.

5.19.6 Handling Interrupts

Section 2.4.6 of the IA-PC HPET Specification describes Handling Interrupts.

5.19.7 Issues Related to 64-Bit Timers with 32-Bit Processors

Section 2.4.7 of the IA-PC HPET Specification describes Issues Related to 64-Bit Timers

with 32-Bit Processors.

5.20 USB EHCI Host Controllers (D29:F0 and D26:F0)

The PCH contains two Enhanced Host Controller Interface (EHCI) host controllers which

support up to fourteen USB 2.0 high-speed root ports. USB 2.0 allows data transfers up

to 480 Mb/s. USB 2.0 based Debug Port is also implemented in the PCH.

5.20.1 EHC Initialization

The following descriptions step through the expected PCH Enhanced Host Controller

(EHC) initialization sequence in chronological order, beginning with a complete power

cycle in which the suspend well and core well have been off.

5.20.1.1 BIOS Initialization

BIOS performs a number of platform customization steps after the core well has

powered up. Contact your Intel Field Representative for additional PCH BIOS

information.

Functional Description

218 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.20.1.2 Driver Initialization

See Chapter 4 of the Enhanced Host Controller Interface Specification for Universal

Serial Bus, Revis ion 1. 0.

5.20.1.3 EHC Resets

In addition to the standard PCH hardware resets, portions of the EHC are reset by the

HCRESET bit and the tr ansition from the D3 HOT device power management state to the

D0 state. The effects of each of these resets are:

If the detailed register descriptions give exceptions to these rules, those exceptions

override these rules. This summary is provid ed to help explain the reasons for the reset

policies.

5.20.2 Data Structures in Main Memory

See Section 3 and Appendix B of the Enhanced Host Controller Interface Specification

for Universal Serial Bus, Revision 1.0 for details.

5.20.3 USB 2.0 Enhanced Host Controller DMA

The PCH USB 2.0 EHC implements three sources of USB packets. They are, in order of

priority on USB during each microframe:

1. The USB 2.0 Debug Port (see Section USB 2.0 Based Debug Port),

2. The Periodic DMA engine, and

3. The Asy nc hronous DM A engine.

The PCH alwa ys performs any currently-pending debug port tr an saction at the

beginning of a microframe, followed by any pending periodic traffic for the current

microframe. If there is time left in the microframe, then the EHC performs any pending

asynchronous traffic until the end of the microframe (EOF1). Note that the debug port

traffic is only presented on Port 1 and Port 9, while the other ports are idle during this

time.

5.20.4 Data Encoding and Bit Stuffing

See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0.

5.20.5 Packet Formats

See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0.

Reset Does Reset Does not Reset Comments

HCRESET bit set.

Memory space registers

except Structural

Parameter s (which is

written by BIOS).

Configuration

registers.

The HCRESET must only affect

registers that the EHCI driver

controls. PCI Configuration space

and BIOS-programmed parameters

can not be reset.

Software writes the

Device Power State

from D3HOT (11b) to

D0 (00b).

Core well registers

(except BIOS-

programmed registers ).

Suspend well

registers; BIOS-

programmed core

well registers.

The D3-to-D0 transition must not

cause wake information (suspend

well) to be lost. It also must not clear

BIOS-programmed registers because

BIOS may not be invoked following

the D3-to-D0 transition.

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 219

Datasheet

The PCH EHCI allows entrance to USB test modes, as defined in the USB 2.0

specification, including Test J, Test Packet, etc. However note that the PCH Test Packet

test mode interpacket gap timing may not meet the USB 2.0 specification.

5.20.6 USB 2.0 Interrupts and Error Conditions

Section 4 of the Enhanced Host Controller Interface Specification for Universal Serial

Bus, Revision 1.0 goes into detail on the EHC interrupts and the error conditions that

cause them. All error conditions that the EHC detects can be reported through the EHCI

Interrupt status bits. Only PCH-specific interrupt and error-reporting behavior is

documented in this section. The EHCI Interrupts Section must be read first, followed by

this section of the datasheet to fully comprehend the EHC interrupt and error-reporting

functionality.

• Based on the EHC Buffer sizes and buffer management policies, the Data Buffer

Error can never occur on the PCH.

• Master Abort and Target Abort responses from hub interface on EHC-i nitiat ed read

packets will be treated as Fatal Host Errors. The EHC halts when these conditions

are encountered.

• The PCH may assert the interrupts which are based on the interrupt threshold as

soon as the status for the last complete transaction in the interrupt interval has

been posted in the internal write buffers. The requirement in the Enhanced Host

Controller Interface Specification for Universal Serial Bus, Revision 1.0 (that the

status is written to memory) is met internally, even though the write may not be

seen on DMI before the interrupt is asserted.

• Since the PCH supports the 1024-element Frame List size, the Frame List Rollover

interrupt occurs every 1024 milliseconds.

• The PCH delivers interrupts using PIRQH#.

• The PCH does no t modify the CERR count on an Interrupt IN when the “Do

Complete-Split” execution criteria are not met.

• For complete-split transactions in the P eriodic list, the “Missed Microfr ame” bit does

not get set on a control-structure-fetch that fails the late-start test. If subsequent

accesses to that control structure do not fail the late-start test, then the “Missed

Microframe” bit will get set and written back.

5.20.6.1 Aborts on USB 2.0-Initiated Memory Reads

If a read initiated by the EHC is aborted, the EHC treats it as a fatal host error. The

following actions are taken when this occurs:

• The Host System Error status bit is set

• The DMA engines are halted after completing up to one more transaction on the

USB interface

• If enabled (by the Host System Error Enable), then an interrupt is generated

• If the status is Master Abort, then the Received Master Abort bit in configuration

space is set

• If the status is Target Abort, then the Received Target Abort bit in configuration

space is set

• If enabled (by the SERR Enable bit in the function’ s configuration space), then the

Signaled System Error bit in configuration bit is set.

Functional Description

220 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.20.7 USB 2.0 Power Management

5.20.7.1 Pause Feature

This feature allows platforms to dynamically enter low-power states during brief

periods when the system is idle (that is, between keystrokes). This is useful for

enabling power management features in the PCH. The policies for entering these states

typically are based on the recent history of system bus activity to incrementally enter

deeper power management states. Normally, when the EHC is enabled, it regularly

accesses main memory while tra versing the DMA schedules looking for work to do; this

activity is viewed by the power management software as a non-idle system, thus

preventing the power managed states to be entered. Suspending all of the enabled

ports can prevent the memory accesses from occurring, but there is an inherent

latency overhead with entering and exiting the suspended state on the USB ports that

makes this unacceptable for the purpose of dynamic power management. As a result,

the EHCI software drivers are allowed to pause the EHC DMA engines when it knows

that the traffic patterns of the attached devices can afford the delay. The pause only

prevents the EHC from generating memory accesses; the SOF packets continue to be

generated on the USB ports (unlike the suspended state).

5.20.7.2 Suspend Feature

The Enhanced Host Controller Interface (EHCI) For Universal Serial Bus Specification,

Section 4.3 describes the details of Port Suspend and Resume.

5.20.7.3 ACPI Device States

The USB 2.0 function only supports the D0 and D3 PCI Power Management states.

Notes regarding the PCH implementation of the Device States:

1. The EHC hardware does not inherently consume any more power when it is in the

D0 state than it does in the D3 state. However, software is required to suspend or

disable all ports prior to entering the D3 state such that the maximum power

consumption is reduced.

2. In the D0 state, all implemented EHC features are enabled.

3. In the D3 state, accesses to the EHC memory-mapped I/O r ange will master abort.

Note that, since the Debug Port uses the same memory range, the Debug Port is

only operational when the EHC is in the D0 state.

4. In the D3 state, the EHC interrupt must never assert for any reason. The internal

PME# signal is used to signal wake events, and so forth.

5. When the Device Power State field is written to D0 from D3, an internal reset is

generated. See section EHC Resets for general rules on the effects of this reset.

6. Attempts to write any o ther value into the Device Power State field other than 00b

(D0 state) and 11b (D3 state) will complete normally without changing the current

value in this field.

5.20.7.4 ACPI System States

The EHC behavior as it relates to other power management states in the system is

summarized in the following list:

— The System is always in the S0 state when the EHC is in the D0 st ate. However,

when the EHC is in the D3 state, the system may be in any power management

state (including S0).

— When in D0, the Pause feature (See Section 5.20.7.1) enables dynamic

processor low-power states to be entered.

— The PLL in the EH C is di sabl ed wh en enteri ng the S 3/S4/S5 states ( core pow er

turns off).

— All core well logic is reset in the S3/S4/S5 states.

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 221

Datasheet

5.20.8 USB 2.0 Legacy Keyboard Operation

The PCH must support the possibility of a keyboard downstream from either a full-

speed/low-speed or a high-speed port. The description of the legacy k eyboard support

is unchanged from USB 1.1.

— The EHC provides the basic ability to generate SMIs on an interrupt event,

along with more sophisticated control of the generation of Intel SMIs.

5.20.9 USB 2.0 Based Debug Port

The PCH supports the elimination of the legacy COM ports by providing the ability for

new debugger software to interact with devices on a USB 2.0 port.

High-level restrictions and features are:

• Operational before USB 2.0 drivers are loaded.

• Functions even when the port is disabled.

• Allows normal system USB 2.0 traffic in a system that may only have one USB port.

• Debug Port device (DPD) must be high-speed capable and connect directly to Port 1

and Port 9 on PCH systems (such as, the DPD cannot be connected to

P ort 1/P ort 9 through a hub . When a DPD is detected the PCH EHCI will bypass the

integrated Rate Matching Hub and connect directly to the port and the DPD).

• Debug Port FIFO always makes forward progress (a bad status on USB is simply

presented back to software).

• The Debug Port FIFO is only given one USB access per microframe.

The Debug port facilitates operating system and device driver debug. It allows the

software to communicate with an external console using a USB 2.0 connection.

Because the interface to this link does not go through the normal USB 2.0 stack, it

allows communication with the external console during cases where the operating

system is not loaded, the USB 2.0 software is broken, or where the USB 2.0 software is

being debugged. Specific features of this implementation of a debug port are:

• Only works with an external USB 2.0 debug device (console)

• Implemented for a specific port on the host controller

• Operational anytime the port is not suspended AND the host controller is in D0

power state.

• Capability is interrupted when port is driving USB RESET

5.20.9.1 Theory of Operation

There are two operational modes for the USB debug port:

1. Mode 1 is when the USB port is in a disabled state from the viewpoint of a standard

host controller driver. In Mode 1, the Debug P ort controller is required to generate a

“keepalive” packets less than 2 ms apart to keep the attached debug device from

suspending. The keepalive packet should be a standalone 32-bit SYNC field.

2. Mode 2 is when the host controller is running (that is, host controller’s Run/Stop#

bit is 1). In Mode 2, the normal transmission of SOF packets will keep the debug

device from suspending.

Functional Description

222 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Behavioral Rules

1. In both modes 1 and 2, the Debug Port controller must check for software

requested debug transactions at least every 125 microseconds.

2. If the debug port is enabled by the debug driver, and the standard host controller

driver resets the USB port, USB debug transactions are held off for the duration of

the reset and until after the first SOF is sent.

3. If the standard host controller driver suspends the USB port, then USB debug

transactions are held off for the dur ation of the suspend/resume sequence and until

after the first SOF is sent.

4. The ENA B LED_CNT bit in the debug register space is independent of the similar

port control bit in the associated Port Status and Control register.

Table 5-50 shows the debug port behavior related to the state of bits in the debug

registers as well as bits in the associated Port Status and Control register.

5.20.9.1.1 OUT Transactions

An Out transaction sends data to the debug device. It can occur only when the

following are true:

• The debug port is enabled

• The debug software sets the GO_CNT bit

• The WRITE_READ#_CNT bit is set

The sequence of the transaction is:

1. Software sets the appropriate values in th e foll owi ng bits:

— USB_ADDRESS_CNF

—USB_ENDPOINT_CNF

— DATA_BUFFER[63:0]

— TOKEN_PID_CNT[7:0]

—SEND_PID_CNT[15:8]

Table 5-50. Debug Port Behavior

OWNER_CNT ENABLED_CT Port

Enable

Run /

Stop Suspend Debug Port Behavior

0XXXX

Debug port is not being used. Normal

operation.

10XXX

Debug port is not being used. Normal

operation.

1100X

Debug port in Mode 1. SYNC keepalives

sent plus debug traffic

1101X

Debug port in Mode 2. SOF (and only

SOF) is sent as keepalive. Debug traffic

is also sent. Note that no other normal

traffic is sent out this port, because the

port is not enabled.

11100

Invalid. Host controller driver should

never put controller into this state

(enabled, not running and not

suspended).

1 1 1 0 1 Por t is sus pe nded. No de bug traffic sent.

11110

Debug port in Mode 2. Debug traffic is

interspersed with normal traffic.

1 1 1 1 1 Por t is sus pe nded. No de bug traffic sent.

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—DATA_LEN_CNT

— WRITE_READ#_CNT: (Note: This will always be 1 for OUT transactions.)

— GO_CNT: (note: this will always be 1 to initiate the transaction)

2. The debug port controller sends a token packet consisting of:

—SYNC

— TOKEN_PID_CNT field

— USB_ADDRESS_CNT field

—USB_ENDPOINT_CNT field

— 5-bit CRC field

3. After sending the token packet, the debug port controller sends a data packet

consisting of:

—SYNC

— SEND_PID_CNT field

— The number of data bytes indicated in DATA_LEN_CNT from the DATA_BUFFER

— 16-bit CRC

Note: A DATA_LEN_CNT value of 0 is valid in which case no data bytes would be included in

the packet.

4. After sending the data packet, the controller waits for a handshake response from

the debug device.

• If a handshake is received, the debug port controller:

— a. Places the received PID in the RECEIVED_PID_STS field

— b. Resets the ERROR_GOOD#_ STS bit

— c. Sets the DONE_STS bit

• If no handshake PID is received, the debug port controller:

— a. Sets the EXCEPTION_STS field to 001b

— b. Sets the ERROR_GOOD#_STS bit

— c. Sets the DONE_STS bit

5.20.9.1.2 IN Transactions

An IN transaction receives data from the debug device. It can occur only when the

following are true:

• The debug port is enabled

• The debug software sets the GO_CNT bit

• The WRITE_READ#_CNT bit is reset

The sequence of the transaction is:

1. Software sets the appropriate values in the following bits:

—USB_ADDRESS_CNF

—USB_ENDPOINT_CNF

— TOKEN_PID_CNT[7:0]

—DATA_LEN_CNT

— WRITE_READ#_CNT: (Note: This will always be 0 for IN transactions.)

— GO_CNT: (Note: This will always be 1 to initiate the transaction.)

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2. The debug port controller sends a token packet consisting of:

—SYNC

— TOKEN_PID _CNT field

— USB_ADDRESS_CNT field

— USB_ENDPOINT_CNT field

— 5-bit CRC field.

3. After sending the token pack et, the debug port con troller waits for a response from

the debug device.

If a response is received:

— The received PID is placed into the RECEIVED_PID_STS field

— Any subsequent bytes are placed into the DATA _BUFFER

— The DATA_LEN_CNT field is updated to show the number of bytes that were

received after the PID.

4. If a valid packet was received from the device that was one byte in length

(indicating it was a handshake packet), then the debug port controller:

— Resets the ERROR_GOOD#_STS bit

— Sets the DONE_STS bit

5. If a valid packet was received from the device that was more than one byte in

length (indicating it was a data packet), then the debug port controller:

— Transmits an ACK handshake packet

— Resets the ERROR_GOOD#_STS bit

— Sets the DONE_STS bit

6. If no valid packet is received, then the debug port controller:

— Sets the EXCEPTION_STS field to 001b

— Sets the ERROR_GOOD#_STS bit

— Sets the DONE_STS bit.

5.20.9.1.3 Debug Software

Enabling the Debug Port

There are two mutually exclusive conditions that debug software must address as part

of its startup processing:

• The EHCI has been initialized by system software

• The EHCI has not been initialized by system software

Debug software can determine the current ‘initialized’ state of the EHCI by examining

the Configure Flag in the EHCI USB 2.0 Command Register. If this flag is set, then

system software has initialized the EHCI. Otherwise the EHCI should not be considered

initialized. Debug software will initialize the debug port registers depending on the

state of the EHCI. However, before this can be accomplished, debug software must

determine which root USB port is designated as the debug port.

Determining the Debug Port

Debug software can easily determine which USB root port has been designated as the

debug port by examining bits 20:23 of the EHCI Host Controller Structural Parameters

is, 0001=port 1).

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Debug Software Startup with Non-Initialized EHCI

Debug software can attempt to use the debug port if after setting the OWNER_CNT bit,

the Current Connect Status bit in the appropriate (See Determining the Debug Port

Presence) PORTSC register is set. If the Current Connect Status bit is not set, then

debug software may choose to terminate or it may choose to wait until a device is

connected.

If a device is connected to the port, then debug software must reset/enable the port.

Debug software does this by setting and then clearing the Port Reset bit the PORTSC

clearing the Port Reset bit. Due to possible delays, this bit may not change to 0

immediately; reset is complete when this bit reads as 0. Software must not continue

until this bit reads 0.

If a high-speed device is attached, the EHCI will automatically set the Port Enabled/

Disabled bit in the PORTSC register and the debug software can proceed. Debug

software should set the ENABLED_CNT bit in the Debug Port Control/Status register,

and then reset (clear) the Port Enabled/Disabled bit in the POR TSC register (so that the

system host controller driver does not see an enabled port when it is first loaded).

Debug Software Startup with Initialized EHCI

Debug software can attempt to use the debug port if the Current Connect Status bit in

the appropriate (See Determining the Debug Port) PORTSC register is set. If the

Current Connect Status bit is not set, then debug software may choose to terminate or

it may choose to wait until a device is connected.

If a device is connected, then debug software must set the OWNER_CNT bit and then

the ENABLED_CNT bit in the Debug Port Control/Status register.

Determining Debug Peripheral Presence

After enabling the debug port functionality, debug software can determine if a debug

peripheral is attached by attempting to send data to the debug peripheral. If all

attempts result in an error (Exception bits in the Debug Port Control/Status register

indicates a Transaction Error), then the attached device is not a debug peripheral. If the

debug port peripheral is not present, then debug software may choose to terminate or

it may choose to wait until a debug peripheral is connected.

5.20.10 EHCI Caching

EHCI Caching is a power management feature in the USB (EHCI) host controllers which

enables the controller to execute the schedules entirely in cache and eliminates the

need for the DMA engine to access memory when the schedule is idle. EHCI caching

allows the processor to maintain longer C-state residency times and provides

substantial system power savings.

5.20.11 USB Pre-Fetch Based Pause

The Pre-Fetch Based Pause is a power management feature in USB (EHCI) host

controllers to ensure maximum C3/C4 processor power state time with C2 popup. This

feature applies to the period schedule, and works by allowing the DMA engine to

identify periods of idleness and preventing the DMA engine from accessing memory

when the periodic schedule is idle. Typically in the presence of periodic devices with

multiple millisecond poll periods, the periodic schedule will be idle for several frames

between polls.

The USB Pre-Fetch Based Pause feature is disabled by setting bit 4 of EHCI

Configuration Register Section 17.2.1.

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5.20.12 Function Level Reset Support (FLR) (SRV/WS SKUs Only)

The USB EHCI Controllers support the Function Level Reset (FLR) capability. The FLR

capability can be used in conjunction with Intel Virtualization Technology. FLR allows an

Operating System in a Virtual Machine to have complete control over a device,

including its initialization, without interfering with the rest of the platform. The device

provides a software interface that enables the Operating System to reset the whole

device as if a PCI reset was asserted.

5.20.12.1 FLR Steps

5.20.12.1.1 FLR Initialization

1. A FLR is initiated by software writing a ‘1’ to the Initiate FLR bit.

2. All subsequent requests targeting the Function will not be claimed and will be

Master Abort Immediate on the bus. This includes any configuration, I/O or

Memory cycles, however, the Function shall continue to accept completions

targeting the Function.

5.20.12.1.2 FLR Operation

The Function will Reset all configuration, I/O and memory registers of the Function

except those indicated otherwise and reset all internal states of the Function to the

default or initial condition.

5.20.12.1.3 FLR Completion

The Initiate FLR bit is reset (cleared) when the FLR reset is completed. This bit can be

used to indicate to the software that the FLR reset is completed.

Note: From the time Initiate FLR bit is written to 1, software must wait at least 100 ms before

accessing the function.

5.20.13 USB Overcurrent Protection

The PCH has implemented programmable USB Overcurrent signals. The PCH provides a

total of 8 overcurrent pins to be shared across the 14 ports.

Four overcurrent signals have been allocated to the ports in each USB Device:

• OC[3:0]# for Device 29 (Ports 0-7)

• OC[7:4]# for Device 26 (Ports 8-13)

Each pin is mapped to one or more ports by setting bits in the USBOCM1 an d USBOCM2

registers.See Section 10.1.52 and Section 10.1.53. It is system BIOS’ responsibility to

ensure that each port is mapped to only one over current pin. Operation with more

than one overcurrent pin mapped to a port is undefined. It is expected that multiple

ports are mapped to a single overcurrent pin, however they should be connected at the

port and not at the PCH pin. Shorting these pins together may lead to reduced test

capabilities. By default, two ports are routed to each of the OC[6:0]# pins. OC7# is not

used by default.

Notes:

1. All USB ports routed out of the package must have Overcurrent protection. It is

system BIOS responsibility to ensure all used ports have OC protection

2. USB P orts that are unused on the system (n ot routed out from the package) should

not have OC pins assigned to them.

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5.21 Integrated USB 2.0 Rate Matching Hub

5.21.1 Overview

The PCH has integrated two USB 2.0 Rate Matching Hubs (RMH). One hub is con nected

to each of the EHCI controllers as shown in the figure below. The Hubs convert low and

full-speed traffic into high-speed traffic. The RMHs will appear to software like an

external hub is connected to Port 0 of each EHCI controller. In addition, port 1 of each

of the RMHs is muxed with Port 1 of the EHCI controllers and is able to bypass the RMH

for use as the Debug Port.

The hub operates like any USB 2.0 Discrete Hub and will consume one tier of hubs

allowed by the USB 2.0 Spec. section 4.1.1. A maximum of four additional non-root

hubs can be supported on any of the PCH USB Ports. The RMH will report the following

Vendor ID = 8087h and Product ID = 0024h.

5.21.2 Architecture

A hub consists of three components: the Hub Repeater, the Hub Controller, and the

Transaction Translator.

1. The Hub Repeater is responsible for connectivity setup and tear-down. It also

supports exception handling, such as bus fault detection and recovery and connect/

disconnect detect.

2. The Hub Controller provides the mechanism for host-to-hub communication. Hub-

specific status and control commands permit the host to configure a hub and to

monitor and control its individual downstream facing ports.

3. The Transaction Translator (TT) responds to high-speed split transactions and

translates them to full-/low-speed transactions with full-/low-speed devices

attached on downstream facing ports. There is 1 TT per RMH in PCH.

See chapter 11 of the USB 2.0 Specification for more details on the architecture of the

hubs.

Figure 5-29. EHCI with USB 2.0 with Rate Matching Hub

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5.22 SMBus Controller

Depending on the SKU, the PCH contains two kinds of SMBus Controllers – the Host

SMbus Controller and the IDF (Integrated Device Fabric) SMbus Controller.

Note: The IDF (Integrated Device Fabric) SMbus Controller is not available on the HEDT SKU.

5.22.1 Host SMBus Controller(D31:F3)

The PCH provides an System Management Bus (SMBus) 2.0 host controller as well as

an SMBus Slave Interface. The host controller provides a mechanism for the pro cessor

to initiate communications with SMBus peripherals (slav es). The PCH is also capable of

operating in a mode in which it can communicate with I2C compatible devices.

The PCH can perform SMBus messages with either packet error checking (PEC) enabled

or disabled. The actual PEC calculation and checking is performed in hardware by the

PCH.

The Slave Interface allows an external master to read from or write to the PCH. Write

cycles can be used to cause certain events or pass messages, and the read cycles can

be used to determine the state of v arious status bits. The PCH’ s internal host controller

cannot access the PCH’s internal Slave Interface.

The PCH SMBus logic exists in Device 31:Function 3 configuration space, and consists

of a transmit data path, and host controller. The transmit data path provides the data

flow logic needed to implement the seven different SMBus command protocols and is

controlled by the host controller. The PCH SMBus controller logic is clocked by RTC

clock.

The SMBus Address Resolution Protocol (ARP) is supported by using the existing host

controller commands through software, except for the new Host Notify command

(which is actually a received message).

The programming model of the host controller is combined into two portions: a PCI

configuration portion, and a system I/O mapped portion. All static configuration, such

as the I/O base address, is done using the PCI configuration space. Real-time

programming of the Host interface is done in system I/O space.

The PCH SMBus host controller checks for parity errors as a target. If an error is

detected, the detected parity error bit in the PCI Status Register (Device 31:Function

3:Offset 06h:bit 15) is set. If bit 6 and bit 8 of the PCI Command Register (Device

31:Function 3:Offset 04h) are set, an SERR# is generated and the signaled SERR# bit

in the PCI Status Register (bit 14) is set.

5.22.2 IDF SMbus Controllers (Bus x:Device 0:Function 3,4,5)

(SRV/WS SKUs Only)

There are three additional host SMBus functions in the Integrated Device Function

(function 3, 4, and 5) for a total of potentially 4 h ost accessible controllers on the PCH.

Host software will have the ability to use a number of the host SMBus controllers

depending on the PCH SKUs.

The IDF SMBus controllers are similar to the host SMBus in their operations and

programming interface. The primary difference is that the IDF SMBus controllers are

PCI Express* function that support message signalled interrupts.

The IDF SMBus controllers are SMBus 2.0 compliant devices supporting all protocols

defined in the SMBus specification: Quick, Byte, Word, Block, and process call. The

controllers also support an I2C mode to communicate with I2C compatible devices.

SMBus messages can be sent either with PEC enabled or disabled though the actual

PEC calculation and checking is performed by software.

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5.22.3 Host Controller

The SMBus host controller is used to send commands to other SMBus slave devices.

Software sets up the host controller with an address, command, and, for writes, data

and optional PEC; and then tells the controller to start. When the controller has finished

transmitting data on writes, or receiving data on reads, it generates an SMI# or

interrupt, if enabled.

The host controller supports 8 command protocols of the SMBus interface (see System

Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte,

Re ceive Byte, W rite Byte/Word, Read Byte/Word, Process Call, Block R ead/Write, Block

Write–Block Read Process Call, and Host Notify.

The SMBus host controller requires that the various data and command fields be setup

for the type of command to be sent. When softw are sets the ST AR T bit, the SMBus Host

controller performs the requested transaction, and interrupts the processor (or

generates an SMI#) when the transaction is completed. Once a START command has

been issued, the values of the “active registers” (Host Control, Host Command,

Transmit Slave Address, Data 0, Data 1) should not be changed or read until the

interrupt status message (INTR) has been set (indicating the completion of the

command). Any register values needed for computation purposes should be saved prior

to issuing of a new command, as the SMBus host controller updates all registers while

completing the new command.

The PCH supports the System Management Bus (SMBus) Specification, Version 2.0.

Slave functionality, including the Host Notify protocol, is available on the SMBus pins.

The SMLink and SMBus signals can be tied together externally depending on TCO mode

used. Refer to section 5.14.2 for more details.

Using the SMB host controller to send commands to the PCH’s SMB slave port is not

supported.

5.22.3.1 Command Protocols

In all of the following commands, the Host Status Register (offset 00h) is used to

determine the progress of the command. While the command is in operation, the

HOST_BUSY bit is set. If the command completes successfully, the INTR bit will be set

in the Host Status Register. If the device does not respond with an acknowledge, and

the transaction times out, the DEV_ERR bit is set. If software sets the KILL bit in the

Host Control Register while the command is running, the transaction will stop and the

FAILED bit will be set.

Quick Command

When progr ammed for a Quick Comman d, the Transmit Slav e Address R egis ter is sent.

The PEC byte is never appended to the Quick Protocol. Software should force the

PEC_EN bit to 0 when performing the Quick Command. Software must force the

I2C_EN bit to 0 when running this command. See section 5.5.1 of the System

Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol.

Send Byte / Receive Byte

For the Send Byte command, the Transmit Slave Address and Device Command

Registers are sent

For the Receive Byte command, the Transmit Slave Address Register is sent. The data

received is stored in the DAT A0 register. Software must force the I2C_EN bit to 0 when

running this command.

The Receive Byte is similar to a Send Byte, the only difference is the direction of data

transfer. See sections 5.5.2 and 5.5.3 of the System Management Bus (SMBus)

Specification, Version 2.0 for the format of the protocol.

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Write Byte/Word

The first byte of a Write Byte/W ord access is the command code. The next 1 or 2 bytes

are the data to be written. When programmed for a Write Byte/Word command, the

Transmit Slave Address, Device Command, and Data0 Registers are sent. In addition,

the Data1 Register is sent on a W rite Word command. Software must force the I2C_EN

bit to 0 when running this command. See section 5.5.4 of the System Management Bus

(SMBus) Specification, Version 2.0 for the format of the protocol.

Read Byte/Word

Reading data is slightly more complicated than writing data. First the PCH must write a

command to the slave device. Then it must follow that command with a repeated start

condition to denote a read from that device's address. The slave then returns 1 or 2

bytes of data. Software must force the I2C_EN bit to 0 when running this command.

When programmed for the read byte/word command, the Transmit Slave Address and

Device Command R egisters are sent. Data is received into the DAT A0 on the read byte,

and the DAT0 and DATA1 registers on the read word. See section 5.5.5 of the System

Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol.

Process Call

The process call is so named because a command sends data and waits for the slave to

return a value dependent on that data. The protocol is simply a W rite Word followed by

a Read Word, but without a second command or stop condition.

When programmed for the Process Call com mand, the PCH transmits the Transmit

Slave Address, Host Command, DATA0 and DATA1 registers. Data received from the

device is stored in the DATA0 and DATA1 registers. The Process Call command with

I2C_EN set and the PEC_EN bit set produces undefined results. Software must force

either I2C_EN or PEC_EN to 0 when running this command. See section 5.5.6 of the

System Management Bus (SMBus) Specification, Version 2.0 for the format of the

protocol.

Note: For process call command, the value written into bit 0 of the Transmit Slave Address

Note: If the I2C_EN bit is set, the protocol sequence changes slightly: the Command Code

(bits 18:11 in the bit sequence) are not sent - as a result, the slave will not

acknowledge (bit 19 in the sequence).

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Block Read/Write

The PCH contains a 32-byte buffer for read and write data which can be enabled by

setting bit 1 of the Auxiliary Control register at offset 0Dh in I/O space, as opposed to a

single byte of buffering. This 32-byte buffer is filled with write data before

transmission, and filled with read data on reception. In the PCH, the interrupt is

generated only after a transmission or reception of 32 bytes, or when the entire byte

count has been transmitted/received.

Note: When operating in I2C mode (I2C_EN bit is set), the PCH will never use the 32-byte

buffer for any bloc k commands.

The byte count field is transmitted but ignored by the PCH as software will end the

transfer after all bytes it cares about have been sent or received.

For a Block Write, software must either force the I2C_EN bit or both the PEC_EN and

AAC bits to 0 when running this command.

The block write begins with a slave address and a write condition. After the command

code the PCH issues a byte count describing how many more bytes will follow in the

message. If a slave had 20 bytes to send, the first byte would be the number 20 (14h),

followed by 20 bytes of data. The byte count may not be 0. A Block Read or Write is

allowed to transfer a maximum of 32 data bytes.

When programmed for a block write command, the Transmit Slave Address, Device

Command, and Data0 (count) registers are sent. Data is then sent from the Block Data

Byte register; the total data sent being the v alue stored in the Data0 R egister. On block

read commands, the first byte received is stored in the Data0 register, and the

remaining bytes are stored in the Block Data Byte register. See section 5.5.7 of the

System Management Bus (SMBus) Specification, Version 2.0 for the format of the

protocol.

Note: For Block Write, if the I2C_EN bit is set, the format of the command changes slightly.

The PCH will still send the number of bytes (on writes) or receive the number of bytes

(on reads) indicated in the DATA0 register. However, it will not send the contents of the

DATA0 register as part of the message. Also, the Block Write protocol sequence

changes slightly: the Byte Count (bits 27:20 in the bit sequence) are not sent - as a

result, the slave will not acknowledge (bit 28 in the sequence).

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I2C Read

This command allows the PCH to perform block reads to certain I2C devices, such as

serial E2PROMs. The SMBus Block Read supports the 7-bit addressing mode only.

However, this does not allow access to devices using the I2C “Combined Format” that

has data bytes after the address. Typically these data bytes correspond to an offset

(address) within the serial memory chips.

Note: This command is supported independent of the setting of the I2C_EN bit. The I2C Read

command with the PEC_EN bit set produces undefined results. Software must force

both the PEC_EN and AAC bit to 0 when running this command.

For I2C Read command, the value written into bit 0 of the Transmit Slave Address

The format that is used for the command is shown in Table 5-51.

The PCH will continue reading data from the peripheral until the NAK is received.

Table 5-51. I2C Block Read

Bit Description

1Start

8:2 Slave Address — 7 bits

9Write

10 Acknowledge from slave

18:11 Send DATA1 register

19 Acknowledge from slave

20 Repeated Start

27:21 Slave Address — 7 bits

28 Read

29 Acknowledge from slave

37:30 Data byte 1 from slave — 8 bits

38 Acknowledge

46:39 Data byte 2 from slave — 8 bits

47 Acknowledge

– Data bytes from slave / Acknowledge

– Data byte N from slave — 8 bits

– NOT Acknowledge

–Stop

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Block Write–Block Read Process Call

The block write-block read process call is a two-part message. The call begins with a

slave address and a write condition. After the command code the host issues a write

byte count (M) that describes how many more bytes will be written in the first part of

the message. If a master has 6 bytes to send, the byte count field will have the value 6

(0000 0110b), followed by the 6 bytes of data. The write byte count (M) cannot be 0.

The second part of the message is a block of read data beginning with a repeated start

condition followed by the slave address and a Read bit. The next byte is the read byte

count (N), which may differ from the write byte count (M). The read byte count (N)

cannot be 0.

The combined data payload must not exceed 32 bytes. The byte length restrictions of

this process call are summarized as follows:

•M ≥ 1 byte

•N ≥ 1 byte

•M + N ≤ 32 bytes

The read byte count does not include the PEC byte. The PEC is computed on the total

message beginning with the first slave address and using the normal PEC

computational rules. It is highly recommended that a PEC byte be used with the Block

Write-Block Read Process Call. Software must do a read to the command register

(offset 2h) to reset the 32 byte buffer pointer prior to reading the block data register.

Note that there is no STOP condition before the repeated START condition, and that a

NACK signifies the end of the read transfer.

Note: E32B bit in the Auxiliary Control register must be set when using this protocol.

See section 5.5.8 of the System Management Bus (SMBus) Specification, Version 2.0

for the format of the protocol.

5.22.4 Bus Arbitration

Several masters may attempt to get on the bus at the same time by driving the

SMBDATA line low to signal a start condition. The PCH continuously monitors the

SMBDATA line. When the PCH is attempting to drive the bus to a 1 by letting go of the

SMBDA TA line, and it samples SMBDA TA low, th en some other master is driving the bus

and the PCH will stop transferring data.

If the PCH sees that it has lost arbitration, the condition is called a collision. The PCH

will set the BUS_ERR bit in the Host Status Register, and if enabled, generate an

interrupt or SMI#. The processor is responsible for restarting the transaction.

When the PCH is a SMBus master, it drives the clock. When the PCH is sending address

or command as an SMBus master, or data bytes as a master on writes, it drives data

relative to the clock it is also driving. It will not start toggling the clock until the start or

stop condition meets proper setup and hold time. The PCH will also ensure minimum

time between SMBus transactions as a master.

Note: The PCH supports the same arbitration protocol for both the SMBus and the Sys tem

Management (SMLink) interfaces.

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5.22.5 Bus Timing

5.22.5.1 Clock Stretching

Some devices may not be able to handle their clock toggling at the r ate that the PCH as

an SMBus master would like. They have the ca pability of stretching the low time of the

clock. When the PCH attempts to release the clock (allowing the clock to go high), the

clock will remain low for an extended period of time.

The PCH monitors the SMBus clock line after it releases the bus to determine whether

to enable the counter for the high time of the clock. While the bus is still low, the high

time counter must not be enabled. Similarly, the low period of the clock can be

stretched by an SMBus master if it is not ready to send or receive data.

5.22.5.2 Bus Time Out (PCH as SMBus Master)

If there is an error in the transaction, such that an SMBus device does not signal an

acknowledge, or holds the clock lower than the allowed time-out time, the transaction

will time out. The PCH will discard the cycle and set the DEV_ERR bit. The time out

minimum is 25 ms (800 RTC clocks). The time-out counter inside the PCH will start

after the last bit of data is transferred by the PCH and it is waiting for a response.

The 25 ms timeout counter will not count under the following conditions:

1. BYTE_DONE_STATUS bit (SMBus I/O Offset 00h, bit 7) is set

2. The SECOND_TO_STS bit (TCO I/O Offset 06h, bit 1) is not set (this indicates that

the system has not locked up).

5.22.6 Interrupts / SMI#

The PCH SMBus controller uses PIRQB# as its interrupt pin. However, the system can

alternatively be set up to generate SMI# instead of an interrupt, by setting the

SMBUS_SMI_EN bit (Device 31:Function 0:Offset 40h:bit 1).

Table 5-53 and Table 5-54 specify how the various enable bits in the SMBus function

control the generation of the interrupt, Host and Sla v e SMI, and Wake internal signals.

The rows in the tables are additive, which means that if more than one row is true for a

particular scenario then the Results for all of the activated rows will occur.

Table 5-52. Enable for SMBALERT#

Event

INTREN (Host

Control I/O

02h, Bit 0)

SMB_SMI_EN

(Host

Configuration

D31:F3:Offset 40h,

Bit 1)

SMBALERT_DIS

(Slave Command I/

O Register, Offset

11h, Bit 2)

Result

SMBALERT#

asserted low

(always

reported in

Host Status

XX XWake generated

X1 0

Slave SMI# generated

(SMBUS_SMI_STS)

10 0Interrupt generated

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 235

Datasheet

5.22.7 SMBALERT#

SMBALER T# is multiplexed with GPIO[11]. When enable and the signal is asserted, The

PCH can generate an interrupt, an SMI#, or a wake event from S1–S5.

5.22.8 SMBus CRC Generation and Checking

If the AAC bit is set in the Auxiliary Control register, the PCH automatically calculates

and drives CRC at the end of the transmitted pack et for write cycles, and will check the

CRC for read cycles. It will not transmit the contents of the PEC register for CRC. The

PEC bit must not be set in the Host Control register if this bit is set, or unspecified

behavior will result.

If the read cycle results in a CRC error, the DEV_ERR bit and the CRCE bit in the

Auxiliary Status register at offset 0Ch will be set.

Table 5-53. Enables for SMBus Slave Write and SMBus Host Events

Event

INTREN (Host

Control I/O Register,

Offset 02h, Bit 0)

SMB_SMI_EN (Host

Configuration Register,

D31:F3:Offset 40h,

Bit1)

Event

Slave Write to Wake/

SMI# Command XX

Wake generated when asleep.

Slave SMI# gen erated when

awake (SMBUS_SMI_STS).

Slave Write to

SMLINK_SLAVE_SMI

Command XX

Slave SMI# gen erated when in

the S0 state (SMBUS_SMI_STS)

Any combination of

Host Status Register

[4:1] asserted

0XNone

1 0 Interrupt generated

11Host SMI# generated

Table 5-54. Enables for the Host Notify Command

HOST_NOTIFY_INTRE

N (Slave Control I/O

Bit 0)

SMB_SMI_EN (Host

Config Register,

D31:F3:Off40h, Bit 1)

HOST_NOTIFY_WKEN

(Slave Control I/O

Result

0X 0None

XX 1Wake generated

10 XInterrupt generated

11 X

Slave SMI# generated

(SMBUS_SMI_STS)

Functional Description

236 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.22.9 SMBus Slave Interface

The PCH’s SMBus Slave interface is accessed using the SMBus. The SMBus slave logic

will not generate or handle receiving the PEC byte and will only act as a Legacy Alerting

Protocol device. The slave interface allows the PCH to decode cycles, and allows an

external microcontroller to perform specific actions. Key features and capabilities

include:

• Supports decode of three types of messages: Byte Write, Byte Read, and Host

Notify.

• Receive Slave Address register: This is the address that the PCH decodes. A default

value is provided so that the slave interface can be used without the processor

having to program this register.

• Receive Slave Data register in the SMBus I/O space that includes the data written

by the external microcontroller.

• Registers that the external microcontroller can read to get the state of the PCH.

• Status bits to indicate that the SMBus slave logic caused an interrupt or SMI# due

to the reception of a message that matched the slave address.

— Bit 0 of the Slave Status Register for the Host Notify command

— Bit 16 of the Intel SMI Status Register Section 13.8.3.8 for all others

Note: The external microcontroller should not attempt to access the PCH’s SMBus slave logic

until either:

— 800 milliseconds after both: RTCRST# is high and RSMRST# is high, OR

— The PLTRST# de-asserts

If a master leaves the clock and data bits of the SMBus interface at 1 for 50 µs or more

in the middle of a cycle, the PCH slav e logic's behavior is undefined. This is interpreted

as an unexpected idle and should be avoided when performing management activities

to the slave logic.

Note: When an external microcontroller accesses the SMBus Slave Interface over the SMBus

a translation in the address is needed to accommodate the least significant bit used for

read/write control. For example, if the PCH slave address (RCV_SLVA) is left at 44h

(default), the external micro controller would use an address of 88h/89h (write/read).

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 237

Datasheet

5.22.9.1 Format of Slave Write Cycle

The external master performs Byte W rite commands to the PCH SMBus Slave I/F. The

“Command” field (bits 11:18) indicate which register is being accessed. The Data field

(bits 20:27) indicate the value that should be written to that register.

Table 5-55 has the values associated with the registers.

Note: The external microcontroller is res ponsible to make sure that it does no t update the contents of the data

byte registers until they have been read by the system processor. The PCH overwrites the old value with

any new va lue received. A r ace condit ion is possible where the new value is being written to the register

just at the time it is being read. PCH will not attempt to c ov er this r ac e condition (that is, unpredictable

results in this case).

Table 5-55. Slave Write Registers

0 Command Register. See Table 5-56 below for legal values written to this register.

1–3 Reserved

4 Data Message Byte 0

5 Data Message Byte 1

6–7 Reserved

8 Reserved

9–FFh Reserved

Table 5-56. Command Types

Command

Type Description

0 Reserved

WAKE/SMI#. This command wakes the system if it is not already awak e. If system is already

awake, an SMI# is genera ted.

Note: The SMB_WAK_STS bit will be set by this command, even if the system is already

awake. The Intel SMI handler should then clear this bit.

2Unconditional Powerdown. This command sets the PWRBTNOR_STS bit, and has the same

effect as the Powerbutton Override occurring.

3HARD RESET WITHOUT CYCLING: This command causes a hard reset of the system (does

not include cy cling of the power su pply). This is equivalent to a write to the CF9h register with

bits 2:1 set to 1, but bit 3 set to 0.

4HARD RESET SYSTEM. This command causes a hard reset of the sys tem (includi ng cycl ing of

the power supply). This is equivalent to a write to the CF9h register with bits 3:1 set to 1.

Disable the TCO Messages. This command will disable the PCH from sending Heartbeat and

Event messages (as described in Section 5.15). Once this command has been executed,

Heartbeat and E vent message repor ting can only be re-en abled by assertion and deassertion of

the RSM RST# si gnal.

6WD RELOAD: Reload watchdog timer.

7 Reserved

SMLINK_SLV_SMI. When PCH detects this command type while in the S0 state, it sets the

SMLINK_SLV_SMI_STS bit. This command should only be used if the system is in an S0 state.

If the message is received during S1–S5 states, the PCH acknowledges it, b ut the

SMLINK_SLV_SMI_STS bit does not get set.

Note: It is possible that the system transitions out of the S0 state at the same time that th e

SMLINK_SLV_SMI command is received. In this case, the SMLINK_SLV_SMI _STS bit

may get set but not serviced before the system goes to sleep. Once the system

returns to S0, the Intel SMI associated with this bit would then be generated. Software

must be able to handle this scenario.

9-FFh Reserved.

Functional Description

238 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.22.9.2 Format of Read Command

The external master performs Byte Read commands to the PCH SMBus Slave interface.

The “Command” field (bits 18:11) indicate which register is being accessed. The Data

field (bits 30:37) contain the value that should be read from that register.

Table 5-57. Slave Read Cycle Format

Bit Description Driven by Comment

1 Start External Microcontroller

2-8 Slave Address - 7 bits External Microcontroller Must match value in Receive Slave

Address register

9 Write External Microcontroller Always 0

10 ACK PCH

11-18 Command code – 8 bits External Microcontroller Indicates which register is being

accessed. See Table 5-58 below for list

of implemented registers.

19 ACK PCH

20 Repeated Start External Microcontroller

21-27 Slave Address - 7 bits External Microcontroller Must match value in Receive Slave

Address register

28 Read External Microcontroller Always 1

29 ACK PCH

30-37 Data Byte PCH Value depends on register being

accessed. Table 5-58 below for list of

implemented registers.

38 NOT ACK External Mic rocontroller

39 Stop External Microcontroller

Table 5-58. Data Values for Slave Read Registers (Sheet 1 of 2)

07:0

Reserved for capabilities indication. Should always return 00h. Future chips may

return another value to indicate different capabilities.

12:0 System Power State

000 = S0 001 = S1 010 = Reserved 011 = S3

100 = S4 101 = S5 110 = Reserved 111 = Reserved

7:3 Reserved

23:0 Reserved

7:4 Reserved

35:0 Watchdog Timer current value Note that Watchdog Timer has 10 bits, but this

field is only 6 bits. If the current value is greater than 3Fh, PCH will always report

3Fh in this field.

7:6 Reserved

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 239

Datasheet

01 = The Intruder Detect (INTRD_DET) bit is set. This indicates that the system

cover has probably been opened.

11 = BTI Temperature Event occurred. This bit will be set if the PCH’s THRM# input

signal is active. Else this bit will read “0.”

2 DOA Processor Status. This bit will be 1 to indicate that the processor is dead

31 = SECOND_TO_STS bit set. This bit will be set after the second time-out

(SECOND_TO_STS bit) of the Watchdog Timer occurs.

6:4 Reserved. Will always be 0, but software should ignore.

Reflects the value of the GPIO[11]/SMBALERT# pin (and is dependent upon the

value of the GPI_INV[11] bit. If the GPI_INV[11] bit is 1, then the value in this bit

equals the level of the GPI[11]/SMBALERT# pin

(high = 1, low = 0).

If the GPI_INV[11] bit is 0, then the value of this bit will equal the inverse of the

level of the GPIO[11]/SMBALERT# pin (high = 0, low = 1).

0 FWH bad bit. This bit will be 1 to indicate that the FWH read returned FFh, which

indicates that it is probably blank.

1 Reserved

2SYS_PWROK Power Failure Status: This bit will be 1 if the SYSPWR_FLR bit in the

GEN_PMCON_2 register is set.

INIT3_3V# due to receiving Shutdown message: This event is visi ble f rom the

reception of the shutdown message until a platform reset is done if the Shutdown

Policy Select bit (SPS) is configured to drive INIT3_3V#. When the SPS bit is

configured to generate PLTRST# based on shutdown, this register bit will always

return 0.

Events on signal will not create a event message

4Reserved

5POWER_OK_BAD: Indicates the failure core power well ramp during boot/resume.

This bit will be active if the SLP_S3# pin is de-asserted and PCH_PWROK pin is not

asserted.

6Thermal Trip: This bit will shadow the state of processor Thermal Trip status bit

(CTS) (16.2.1.2, GEN_PMCON_2, bit 3). Events on signal will not create a event

message

7Reserved: Default value is “X”

Note: Software should not expect a consistent value when this bit is read through

SMBUS/SMLink.

67:0

Contents of the Message 1 register. Refer to Section 13.9.8 for the description of this

77:0

Contents of the Message 2 register. Refer to Section 13.9.8 for the description of this

87:0

Contents of the TCO_WDCNT register. Refer to Section 13.9.9 for the description of

this registe r.

9 7:0 Seconds of the RTC

A 7:0 Minutes of the RTC

B7:0Hours of the RTC

C 7:0 “Day of Week” of the RTC

D 7:0 “Day of Month” of the RTC

E 7:0 Month of the RTC

F7:0Year of the RTC

10h–FFh 7:0 Reserved

Table 5-58. Data Values for Slave Read Registers (Sheet 2 of 2)

Functional Description

240 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Behavioral Notes

According to SMBus protocol, Read and Write messages always begin with a Start bit –

Address– Write bit sequence. When the PCH detects that the address matches the

value in the Receive Slave Address register, it will assume that the protocol is always

followed and ignore the Write bit (bit 9) and signal an Acknowledge during bit 10. In

other words, if a Start –Address–Read occurs (which is illegal for SMBus Read or Write

protocol), and the address matches the PCH’ s Slave Address, the PCH will still grab the

cycle.

Also according to SMBus protocol, a Read cycle contains a Repeated Start–Address–

Read sequence beginning at bit 20. Once again, if the Address matches the PCH’s

Receive Slave Address, it will assume that the protocol is followed, ignore bit 28, and

proceed with the Slave Read cycle.

Note: An external microcontroller must not attempt to access the PCH’s SMBus Slave logic

until at least 1 second after both RTCRST# and RSMRST# are de-asserted (high).

5.22.9.3 Slave Read of RTC Time Bytes

The PCH SMBus slave interface allows external SMBus master to read the internal R TC’ s

time byte registers.

The R T C time bytes are internally latched by the PCH’s hardware whenever RT C time is

not changing and SMBus is idle. This ensures that the time byte delivered to the slave

read is always v alid and it does not change when the read is still in progress on the bus.

The RTC time will change whenever hardware update is in progress, or there is a

software write to the RTC time bytes.

The PCH SMBus slave interface only supports Byte R ead operation. The external SMBus

master will read the RTC time bytes one after another. It is software’s responsibility to

check and manage the possible time rollover when subsequent time bytes are read.

For example, assuming the RTC time is 11 hours: 59 minutes: 59 seconds. When the

external SMBus master reads the hour as 11, then proceeds to read the minute, it is

possible that the rollover happens between the reads and the minute is read as 0. This

results in 11 hours: 0 minute instead of the correct time of 12 hours: 0 minutes. Unless

it is certain that rollover will not occur, software is required to detect the possible time

rollover by reading multiple times such that the read time bytes can be adjusted

accordingly if needed.

5.22.9.4 Format of Host Notify Command

The PCH tracks and responds to the standard Host Notify command as specified in the

System Management Bus (SMBus) Specification, Version 2.0. The host address for this

command is fixed to 0001000b. If the PCH already has data for a previously-received

host notify command which has not been serviced yet by the host software (as

indicated by the HOST_NOTIFY_STS bit), then it will NACK following the host address

byte of the protocol. This allows the host to communicate non-acceptance to the

master and retain the host notify address and data values for the previous cycle until

host software completely services the interrupt.

Note: Host software must always clear the HOST_NOTIFY_STS bit after completing any

necessary reads of the address and data registers.

Table 5-59 shows the Host Notify format.

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 241

Datasheet

5.23 Thermal Management

5.23.1 Thermal Sensor

The PCH incorporates one on-die Digital thermal sensor (DTS) for thermal

management. The thermal sensor can provide PCH temperature information to an EC

or SIO device that can be used to determine how to control the fans.

This thermal sensor is located near the DMI interface. The on-die thermal sensor is

placed as close as possible to the hottest on-die location to reduce thermal gradients

and to reduce the error on the sensor trip thresholds. The thermal Sensor trip points

may be programmed to generate various interrupts including SCI, Intel SMI, PCI and

other General Purpose events.

5.23.1.1 Internal Thermal Sensor Operation

The internal thermal sensor reports four trip points: Aux2, Aux, Hot and Catastrophic

trip points in the order of increasing temperature.

Aux, Aux2 Temperature Trip Points

These trip points may be set dynamically if desired and provides an interrupt to ACPI

(or other software) when it is crossed in either direction. These auxiliary temperature

trip points do not automatically cause any hardware throttling but may be used by

software to trigger interru pts. This trip point is set below the Hot temperature trip point

and responses are separately programmable from the hot temperature settings, in

order to provide incrementally more aggressiv e actions. Aux and Aux2 trip points are

fully Software programmable during system run-time. Aux2 trip point is set below the

Aux temper ature trip point.

Table 5-59. Host Notify Format

Bit Description Driven By Comment

1 Start External Master

8:2 SMB Host Address — 7 bits External Master Always 0001_000

9 Write External Master Always 0

10 ACK (or NACK) PCH PCH NACKs if HOST_NOTIFY_STS is 1

17:11 Device Address – 7 bits External Master Indicates the address of the master; loaded

into the Notify Device Address Register

18 Unused — Always 0 External Master 7-bit-only address; this bit is inserted to

complete the byte

19 ACK PCH

27:20 Data Byte Low — 8 bits External Master Loaded into the Notify Data Low Byte

28 ACK PCH

36:29 Data Byte High — 8 bits External Master Loaded into the Notify Data High Byte

37 ACK PCH

38 Stop External Master

Functional Description

242 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Hot Temperature Trip Point

This trip point may be set dynamically if desired and provides an interrupt to ACPI (or

other software) when it is crossed in either direction. Software could optionally set this

as an Interrupt when the temperature exceeds this level setting. Hot trip does not

provide any default hardware based thermal throttling, and is available only as a

customer configurable interrupt when Tj,max has been reached.

Catastrophic Trip Point

This trip point is set at the temperature at which the PCH must be shut down

immediately without any software support. The catastrophic trip point must correspond

to a temperature ensured to be functional in order for the interrupt generation and

Hardware response. Hardware response using THERMTRIP# would be an unconditional

transition to S5. The catastrophic transition to the S5 state does not enforce a

minimum time in the S5 state. It is assumed that the S5 residence and the reboot

sequence cools down the system. If the catastrophic condition remains when the

catastrophic power down enable bit is set by BIOS, then the system will re-enter S5.

Thermometer Mode

The thermometer is implemented using a counter that starts at 0 and increments

during each sample point until the comparator indicates the temperature is above the

current value. The value of the counter is loaded into a read-only register (Thermal

Sensor Thermometer Read) when the comparator first trips.

5.23.1.1.1 Recommended Programming for Available Trip Points

There may be a ±2°C offset due to thermal gradient between the hot-spot and the

location of the thermal sensor. Trip points should be programmed to account for this

temperature offset between the hot-spot Tj,max and the thermal sensor.

Aux Trip Points should be programmed for software and firmware control using

interrupts.

Hot Trip Point should be set to throttle at 108°C (Tj,max) due to DTS trim accuracy

adjustments. Hot trip points should also be programmed for a software response.

Catastrophic Trip Point should be set to halt operation to a void maximum Tj of about

120°C.

Note: Crossing a trip point in either direction may generate several types of interrupts. Each

trip point has a register that can be programmed to select the type of interrupt to be

generated. Crossing a trip point is implemente d as edge detection on each trip point to

generate the interrupts.

5.23.1.1.2 Thermal Sensor Accuracy (Taccuracy)

Taccuracy for PCH is ±5 °C in the temperature range 90°C to 120°C. Taccuracy is ±10 °C

for temperatures from 45 °C - 90 °C. PCH may not operate above +108 °C. This value

is based on product characterization and is not ensured by manufacturing test.

Software has the ability to program the Tcat, Thot, and Taux trip points, but these trip

points should be selected with consideration for the thermal sensor accuracy and the

quality of the platform thermal solution. Overly conservative (unnecessarily low)

temperature settings may unnecessarily degrade performance due to frequent

throttling, while overly aggressive (dangerously high) temperature settings may fail to

protect the part against permanent thermal damage.

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 243

Datasheet

5.23.2 Thermal Reporting Over System Management Link 1

Interface (SMLink1)

SMLink1 interface in the PCH is the SMBus link to an optional external controller. A

SMBus protocol is defined on the PCH to allow compatible devices such as Embedded

Controller (EC) or SIO to obtain system thermal data from sensors integrated into

components on the system using the SMLink1 interface. The sensors that can be

monitored using the SMLink1 include those in the processor, PCH, and DIMMs with

sensors implemented. This solution allows an external device or controller to use the

system thermal data for system thermal management.

Note: To enable Thermal Reporting, the Thermal Data Reporting enable and processor/PCH/

DIMM temper ature read enables ha ve to be set in the Thermal R eporting Control (TRC)

There are 2 uses for the PCH's thermal reporting capability:

1. To provide system thermal data to an external controller. The controller can

manage the fans and other cooling elements based on this data. In addition, the

PCH can be programmed by setting appropriate bits in the Alert Enable (AE)

Re gister (See Section 23.2 for details on this register) to alert the controller when a

device has gone outside of its temperature limits. The alert causes the assertion of

the PCH’s TEMP_ALERT# (SATA5GP/GPIO49/TE MP_ALERT#) signal. See

Section 5.23.2.6 for more details.

2. To provide an interface between the external controller and host software. This

software interface has no direct affect on the PCH's thermal collection. It is strictly

a software interface to pass information or data.

The PCH responds to thermal requests only when the system is in S0 or S1. Once the

PCH has been programmed, it will start responding to a request while the system is in

S0 or S1.

To implement this thermal reporting capability, the platform is required to have

appropriate Intel ME firmware, BIOS support, and compatible devices that support the

SMBus protocol.

5.23.2.1 Supported Addresses

The PCH supports 2 addresses: I2C Address for writes and Block Read Address for

reads. These addresses need to be distinct.

5.23.2.1.1 I2C* Address

This address is used for writes to the PCH.

• The address is set by soft straps which are values stored in SPI flash and are

defined by the OEM. The address can be set to any value the platform requires.

• This address supports all the writes listed in Table 5-60 below.

• SMBus reads by the external controller to this address are not allowed and result in

indeterminate behavior.

Functional Description

244 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.23.2.1.2 Block Read Address

This address is used for reads from the PCH.

• The address is set by soft straps or BIOS. It can be set to any value the platform

requires.

• This address only supports SMBus Block Read command and not Byte or Word

Read.

• The Block Read command is supported as defined in the SMBus 2.0 specification,

with the command being 40h, and the byte count being provided by the PCH

following the block read format in the SMBus spec.

• Writes are not allowed to this address, and result in indeterminate behavior.

• Packet Error Code (PEC) may be enabled or not, which is set up by BIOS.

5.23.2.2 I2C Write Commands to the Intel® Management Engine

Table 5-60 lists the write commands supported by the Intel ME.

All bits in the write commands must be written to the PCH or the operation will be

aborted. F or example, for 6-bytes write commands, all 48 bits must be written or the

operation will be aborted.

The command format follows the Block Write format of the SMBus specification.

Table 5-60. I2C Write Commands to the Intel® Management Engine

Transaction Slave

Addr

Data

Byte0

(Commd)

Data

Byte 1

(Byte

Count)

Data

Byte 2

Data

Byte 3

Data

Byte 4

Data

Byte 5

Data

Byte 6

Data

Byte 7

Write Processor

Temp Limits I2C 42h 4h Lower

Limit

[15:8]

Lower

Limit

[7:0]

Upper

Limit

[15:8]

Upper

Limit

[7:0]

Write PCH

Temp Limits I2C 44h 2h Lower

Limit

[7:0]

Upper

Limit

[7:0]

Write DIMM

Temp Limits I2C 45h 2h Lower

Limit

[7:0]

Upper

Limit

[7:0]

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 245

Datasheet

5.23.2.3 Block Read Command

The external controller may read thermal information from the PCH using the SMBus

Block Read Command. Byte-read and Word-read SMBus commands are not supported.

Note that the reads use a different address than the writes.

The command format follows the Block Read format of the SMBus spec.

The PCH and external controller are set up by BIOS with the length of the read that is

supported by the platform. The device must always do reads of the lengths set up by

BIOS.

The PCH supports any one of the following lengths: 2, 4, 5, 9, 10, 14 or 20 bytes. The

data always comes in the order described in Table 5-61, where 0 is the first byte

received in time on the SMBus.

Table 5-61. Block Read Command - Byte Definition

Byte Description

Byte 0

Processor Package temperature, in absolute degrees Celsius (C) It is a single byte for

the highest temperature between the 2 components. This is not relative to some max

or limit, but is the maximum in absolute degrees.

If the processor temperature collection has errors, this field will be FFh.

Read value represents bits [7:0] of PTV (Processor Temperature Value)

Byte 1

The PCH temp in degrees C.

FFh indicates error condition.

Read value represents bits [7:0] of ITV (Internal Temperature Values)

Note: Requires TRC (Thermal Reporting Control) Register bit [5] to be enabled. Please

see Section 23.2.

Byte 4:2 Reserved

Byte 5

Thermal Sensor (TS) on DIMM 0

If DIMM not populated, or if there is no TS on DIMM, value will be 0h

Read value represents bits[7:0] of DTV (DIMM Temperature Values) Register described

in Section 23.2.

Note: Requires TRC (Thermal Reporting Control) Register bit [0] to be enabled. Please

see Section 23.2.

Byte 6

Thermal Sensor (TS) on DIMM 1

If DIMM not populated, or if there is no TS on DIMM, value will be 0h

Read v alue re present s bits[15:8 ] of D TV (DIMM Temperature Values) Register described

in Section 23.2.

Note: Requires TRC (Thermal Reporting Control) Register bit [1] to be enabled. Please

see Section 23.2.

Byte 7

Thermal Sensor (TS) on DIMM 2

If DIMM not populated, or if there is no TS on DIMM, value will be 0h

Read value represents bits[23:16] of DTV (DIMM Temperature Values) Register

described in Section 23.2.

Note: Requires TRC (Thermal Reporting Control) Register bit [2] to be enabled. Please

see Section 23.2.

Byte 8

Thermal Sensor (TS) on DIMM 3

If DIMM not populated, or if there is no TS on DIMM, value will be 0h

Read value represents bits[31:24] of DTV (DIMM Temperature Values) Register

described in Section 23.2.

Note: Requires TRC (Thermal Reporting Control) Register bit [3] to be enabled.

Byte 9

Sequence number. Can be used to check if PCH's FW or HW is hung. See

Section 5.23.2.9 for usage.

This byte is updated every time the collected data is updated

Note: Read value represents bi ts[23:16] of ITV (Internal Temperature Values)

Byte 19:10 Reserved

Functional Description

246 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

A 2-byte read would provide both the PCH and processor temperature. A device that

wants DIMM information would read 9 bytes.

5.23.2.4 Read Data Format

For each of the data fields an ERROR Code is listed below. This code indicates that the

PCH failed in its access to the device. This would be for the case where the read

returned no data, or some illegal value. In general that would mean the device is

broken. The EC can treat the device that failed the read as broken or with some fail-

safe mechanism.

5.23.2.4.1 PCH and DIMM Temperature

The temperature readings for the PCH, DIMM are 8-bit unsigned values from 0–255.

The minimum granularit y supported by the internal thermal sensor is 1°C. Thus, there

are no fractional values for the PCH or DIMM temperatures.

Note the sensors used within the components do not support values below 0 degrees,

so this field is treated as 8 bits (0-255) absolute and not 2's complement (-128 to 127).

Devices that are not present or that are disabled will be set to 0h. Devices that have a

failed reading (that is, the read from the device did not return any legal value) will be

set to FFh. A failed reading means that the attempt to read that device returned a

failure. The failure could have been from a bus failure or that the device itself had an

internal failure. For instance, a system may only have one DIMM and it would report

only that one value, and the values for the other DIMM's would all be 00h.

5.23.2.5 Thermal Data Update Rate

The temperature values are updated every 200 ms in the PCH, so reading more often

than that simply returns the same data multiple times. Also, the data may be up to

200 ms old if the external controller reads the data right before the next update

window.

5.23.2.6 Temperature Comparator and Alert

The PCH has the ability to alert the external controller when temperatures are out of

range. This is done using the PCH’s TEMP_ALERT# signal. The alert is a simple

comparator. If any device's temperature is outside the limit r ange for that device, then

the signal is asserted (electrical low). Note that this alert does not use the

SML1ALERT#.

The PCH supports 3 r ang e s :

1. Processor Package range - upper and lower limit (8 bits each, in degrees C).

2. PCH range - upper and lower limit (8 bits each, in degrees C) for PCH temperature.

3. DIMM range - upper and lower limit (8 bits each, in degrees C), applies to all

DIMM's (up to 4 supported) that are enabled. Disabled (unpopulated) DIMMs do

not participate in the thermal compares.

The comparator checks if the device is within the specified range, including the limits.

For example, a device that is at 100 degrees when the upper limit is 100 will not trigger

the alert. Likewise, a device that is at 70 degrees when the lower limit is 70 will not

trigger the alert.

The compares are done only on devices that have been enabled by BIOS for checking.

Since BIOS knows how many DIMM's and processors are in the system, it enables the

checking only for those devices that are physically present.

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The compares are done in firmware, so all the compares are executed in one software

loop and at the end, if there is any out of bound temperature, the PCH’ s TEMP_ALER T#

signal is asserted.

When the external controller sees the TEMP_ALERT# signal low, it knows some device

is out of range. It can read the temperatures and then change the limits for the

devices. Note that it may take up to 250 ms before the actual writes cause the signal

to change state. F or instance if the PCH is at 105 degrees and the limit is 100, the alert

is triggered. If the controller changes the limits to 110, the TEMP_ALERT# signal may

remain low until the next thermal sampling window (every 200 ms) occurs and only

then go high, assuming the PCH was still within its limits.

At boot, the controller can monitor the TEMP_ALERT# signal state. When BIOS has

finished all the initialization and enabled the temperature comparators, the

TEMP_ALER T# signal will be asserted since the default state of the limit registers is 0h;

hence, when the PCH first reads temperatures, they will be out of range. This is the

positive indication that the external controller may now read thermal information and

get valid data. If the TEMP_ALERT# signal is enabled and not asserted within 30

seconds after PLTRST#, the external controller should assume there is a fatal error and

handle accordingly. In general the TEMP_ALERT# signal will assert within 1-4 seconds,

depending on the actual BIOS implementation and flow.

Note: The TEMP_ALERT# assertion is only valid when PLTRST# is deasserted. The controller

should mask the state of this signal when PLTRST# is asserted. Since the controller

may be powered even when the PCH and the rest of the platform are not, the signal

may glitch as power is being asserted, thus the controller should wait until PLTRST#

has deasserted before monitoring the signal.

5.23.2.6.1 Special Conditions

The external controller should have a graceful means of handling the following:

1. TEMP_ALERT# asserts, and the controller reads PCH, but all temperature values

are within limits.

In this case, the controller should assume that by the time the co ntroller could read

the data, it had changed and moved back within the limits.

2. External controller writes new values to temperature limits, but TEMP_ALERT# is

still asserted after several hundred msecs. When read, the values are back within

limits.

In this case, the controller should treat this as case where the temperature

changed and caused TEMP_ALERT# assertion, and then changed again to be back

within limits.

3. There is the case where the external controller writes an update to the limit

thermal registers. The limit change will only take affect when the write completes

and the Intel ME can process this change. If the Intel ME is already in the process

of collecting data and doing the compares, then it will continue to use the old limits

during this round of compares, and then use the new limits in the next compare

window.

4. Each SMBus write to change the limits is an atomic operation, but is distinct in

itself. Therefore the external controller could write PCH limit, and then write DIMM

limit. In the middle of those 2 writes, the thermal collecting procedure could be

called by the Intel ME, so that the comparisons for the limits are done with the new

PCH limits but the old DIMM limits.

Note: The limit writes are done when the SMBus write is complete; therefore, the limits are

updated atomically with respect to the thermal updates and compares. There is never a

case where the compares and the thermal update are interrupted in the middle by the

write of new limits. The thermal updates and compares are done as one non-

interruptible routine, and then the limit writes would change the limit value outside of

that routine.

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5.23.2.7 BIOS Set Up

In order for the PCH to properly report temperature and enable alerts, the BIOS must

configure the PCH at boot or from suspend/resume state by writing the following

information to the PCH MMIO space. This information is NOT configurable using the

external controller.

• Enables for each of the possible thermal alerts (PCH and DIMM). Note that each

DIMM is enabled individually.

• Enables for reading DIMM and PCH temperatures. Note that each can be enabled

individually.

• SMBus address to use for each DIMM.

Setting up the temperature calculation equations.

5.23.2.8 SMBus Rules

The PCH may NACK an incoming SMBus transaction. In certain cases the PCH will NACK

the address, and in other cases it will NACK the command depending on internal

conditions (for example, errors, busy condition s). Given that most of the cases are due

to internal conditions, the external controller must alias a NACK of the command and a

NACK of the address to the same behavior. The controller must not try to make any

determination of the reason for the NACK, based on the type of NACK (command vs.

address).

The PCH will NACK when it is enabled but busy. The external controller is required to

retry up to 3 times when they are NACK'ed to determine if the FW is busy with a data

update. When the data values are being updated by the Intel ME, it will force this NACK

to occur so that the data is atomically updated to the external controller. In reality if

there is a NACK because of the PCH being busy, in almost all cases the next read will

succeed since the update internally takes very little time.

The only long delay where there can be a NACK is if the internal Intel ME engine is

reset. This is due to some extreme error condition and is therefore rare. In this case

the NACK may occur for up to 30 seconds. After that, the external controller must

assume that the PCH will never return good data. Even in the best of cases, when this

internal reset occurs, it will always be a second or 2 to re-enable responding.

5.23.2.8.1 During Block Read

On the Block Read, the PCH will respect the NACK and Stop indications from the

external controller, but will consider this an error case. It will recover from this case

and correctly handle the next SMBus request.

The PCH will honor STOP during the block read command and cease providing data. On

the next Block Read, the data will start with byte 0 again. However, this is not a

recommended usage except for 'emergency cases'. In general the external controller

should read the entire length of data that was originally programmed.

5.23.2.8.2 Block Read Special Handling

On the Block Read, the PCH will respect the NACK and Stop indications from the

external controller, but will consider this an error case. It will recover from this case

and correctly handle the next SMBus request.

The PCH will honor STOP during the block read command and cease providing data. On

the next Block Read, the data will start with byte 0 again. However, this is not a

recommended usage except for 'emergency cases'. In general the external controller

should read the entire length of data that was originally programmed.

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5.23.2.9 Case for Considerations

Below are some corner cases and some possible actions that the external controller

could take.

Note that a 1-byte sequence number is available to the data read by the external

controller. Each time the PCH updates the thermal information it will increment the

sequence number. The external controller can use this value as an indication that the

thermal FW is actually operating. Note that the sequence number will roll over to 00h

when it reaches FFh.

1. Power on:

The PCH will not respond to any SMBus activity (on SMLink1 interface) until it has

loaded the thermal Firmware (FW), which in general would take 1-4 seconds.

During this period the PCH will NACK any SMBus transaction from the external

controller.

The load should take 1-4 seconds, but the external controller should design for 30

seconds based on long delays for S4 resume which takes longer than normal power

up. This would be an extreme case, but for larger memory footprints and non-

optimized recovery times, 30 seconds is a safe number to use for the timeout.

Recover/Failsafe: if PCH has not responded within 30 seconds, the external

controller can assume that the system has had a major error and the external

controller should ramp the fans to some reasonably high value.

The only recover from this is an internal reset on the PCH, which is not visible to

the external controller. Therefore the external controller might choose to poll every

10-60 seconds (some fairly long period) hereafter to see if the PCH's thermal

reporting has come alive.

2. PCH's Thermal FW hangs and requires an internal reset which is not visible to the

external controller.

The PCH will NACK any SMBus transaction from the external controller. The PCH

may not be able to respond for up to 30 seconds while the FW is being reset and

reconfigured.

The external controller could choose to poll every 1-10 seconds to see if the

thermal FW has been successfully reset and is now providing data.

General recov ery for this case is about 1 second, but 30 seconds should be used by

the external controller at the timeout.

Recovery/Failsafe: same as in case #1.

3. Fatal PCH error, causes a global reset of all components.

When there is a fatal PCH error, a global reset may occur, and then case #1

applies.

The external controller can observe, if desired, PLTRST# assertion as an

indication of this event.

4. PCH thermal FW fails or is hung, but no reset occurs

The sequence number will not be updated, so the external controller knows to go to

failsafe after some number of reads (8 or so) return the same sequence number.

The external controller could choose to poll every 1-10 seconds to see if the

thermal FW has been successfully reset and working again.

In the absence of other errors, the updates for the sequence num ber shou ld n ev e r

be longer than 400 ms, so the number of reads needed to indicate that there is a

hang should be at around 2 seconds. But when there is an error, the sequence

number may not get updated for seconds. In the case that the external controller

sees a NACK from the PCH, then it should restart its sequence counter, or otherwise

be aware that the NACK condition needs to be factored into the sequence number

usage.

The use of sequence numbers is not required, but is provided as a means to ensure

correct PCH FW operation.

5. When PCH updates the Block Read data structure, the external controller gets a

NACK during this period.

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To ensure atomicity of the SMBus data read with respect to the data itself, when

the data buffer is being updated, the PCH will NACK the Block R ead transaction.

The update is only a few micro-seconds, so very short in terms of SMBus polling

time; therefore, the next read should be successful. The external controller should

attempt 3 reads to handle this condition before moving on.

If the Block read has started (that is, the address is ACK'ed) then the entire read

will complete successfully, and the PCH will update the data only after the SMBus

read has completed.

6. System is going from S0 to S3/4/5. Note that the thermal monitoring FW is fully

operational if the system is in S0/S1, so the following only applies to S3/4/5.

When the PCH detects the OS request to go to S3/4/5, it will take the SMLink1

controller offline as part of the system preparation. The external controller will see

a period where its transactions are getting NACK'ed, and then see SLP_S3# assert.

This period is relatively short (a couple of seconds depending on how long all the

devices take to place themselves into the D3 state), and would be far less than the

30 second limit mentioned above.

7. TEMP_ALERT# - Since there can be an internal reset, the TEMP_ALERT# may get

asserted after the reset. The external controller must accept this assertion and

handle it.

5.23.2.9.1 Example Algorithm for Handling Transaction

One algorithm for the transaction handling could be summarized as follows. This is just

an example to illustrate the above rules. There could be other algorithms that can

achieve the same results.

1. P erform SMBus transaction.

2. If ACK, then continue

3. If NACK

a. Try again for 2 more times, in case the PCH is busy updating data.

b. If 3 successive transactions receive NACK, then

• Ramp fans, assuming some general long reset or failure

• Try every 1-10 seconds to see if SMBus transactions are now working

• If they start then return to step 1

• If they continue to fail, then stay in this step and poll, but keep the fans

ramped up or implement some other failure recovery mechanism.

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5.24 Intel® High Definition Audio (Intel® HD Audio)

Overview (D27:F0)

The PCH’ s Intel® High Definition Audio (Intel® HD Audio) controller communicates with

the external codec(s) over the Intel High Definition Audio serial link. The controller

consists of a set of DMA engines that are used to move samples of digitally encoded

data between system memory and an external codec(s). The PCH implements four

output DMA engines and 4 input DMA engines. The output DMA engines move digital

data from system memory to a D-A converter in a codec. PCH implements a single

Serial Data Output signal (HDA_SDOUT) that is connected to all external codecs. The

input DMA engines move digital data from the A-D converter in the codec to system

memory. The PCH implements four Serial Digital Input signals (HDA_SDI[3:0])

supporting up to four codecs.

Audio software renders outbound and processes inbound data to/from buffers in

system memory. The location of individual buffers is described by a Buffer Descriptor

List (BDL) that is fetched and processed by the controller. The data in the buffers is

arranged in a predefined format. The output DMA engines fetch the digital data from

memory and reformat it based on the programmed sample rate, bit/sample and

number of channels. The data from the output DMA engines is then combined and

serially sent to the external codecs over the Intel High Definition Audio link. The input

DMA engines receive data from the codecs ov er the Intel High Definition Audio link and

format the data based on the programmable attributes for that stream. The data is

then written to memory in the predefined format for software to process. Each DMA

engine moves one stream of data. A single codec can accept or generate multiple

streams of data, one for each A-D or D-A converter in the codec. Multiple codecs can

accept the same output stream processed by a single DMA engine.

Codec commands and responses are also transported to and from the codecs using

DMA engines.

The PCH HD audio controller support s the Function Level Reset (FLR).

5.25 PCH Intel® Management Engine Firmware

The PCH offers different firmware options depending on the design (server or

workstation) and platform usage models. In all cases, SPI Flash is required to connect

to PCH to load the Intel ME FW. Please also see platform specific PDG for detailed HW

requirements.

5.25.1 Intel® Server Platform Services Firmware

Intel® Server Platform Services FW is for server platforms. It comes in four flavors.

5.25.1.1 Silicon Enabling

This option provides the fundamental Intel ME FW functions required to boot a server

design. In addition it provides following functions:

• Power management controller (PMC) patching to provide a way of applying future

enhancements or fixes to PMC

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5.25.1.2 Intel® Intelligent Power Node Manager 2.0

Intel® Intelligent Power Node Manager 2.0 is a platform power reporting and capping

technology, which provides an enhanced set of features, as compared to its previous

version.

— Intel Intelligent Power Node Manager 2.0 supports multiple power policies for

multiple power domains, including thermal policies.

— The enhanced algorithms provide shor ter response times, enhanced dynamic

range of power control, and reliable and uninterrupted power capping even

during OS or BMC failure.

— By using an intelligent algorithm system, system performance is improv ed for a

given power limit.

— Power supply optimization technology reduces cost or improve efficiency of

power supplies.

— Server platform services is an accompanying function that provides access to

PECI information by the BMC - critical selected information is available for

efficient aggregated access by the BMC without losing the access to any other

information available in a raw format.

5.25.1.3 Manageability Controller (MC) Compliant with Data Center

Management Interface (DCMI) Specification

This option provides a building block infrastr ucture for OEMs to configure and adopt the

manageability controller according to their platform design needs without spending

development or engineering time for server manageability. MC also provides an ability

to interface with external Service Processors for advanced manageability requirements.

Hardware features supported:

• Four PWM and Eight TACHS providing maximum of four Thermal zones with two

TACHS per zone

• 12 GPIO dedicated for the Manageability Controller for LED and other controls

• Three SMBus Transports, two dedicated and one shared with Host

• SST, PECI and MEI transports

• Either Side-band SMBus Intel LOMs or Integrated MAC to external PHY

• LM75/TMP75 Thermal Sensors

• PMBus for Power Instrumentation and Control

Manageability Features supported:

• 128 Sensors capable to be configurable as I2C, PECI, S ST, GPIO, PMBus and Virtual

Sensors.

• Up to 32 individually configurable actions based on the Sensors such as Fan Speed

Control, LED Controls and any other custom build control mechanisms derived from

the sensors.

• Piece-wise, Clamped algorithms for Fan Speed Control configurable through PIA.

• All commands of DCMI 1.5 including all DCMI 1.0 features.

• Additional IPMI commands for Chassis, Sensor, Storage, and Transport for

Provisioning and Configuration for OEMs.

• IPMB communication to external Server Processors for Platform Events and Alerts.

• Well documented BIOS to MC interaction.

• Both the simple DCMI-compliant power management interface as well as the full

Intel Intelligent Power Node Manager 2.0 interface for provisioning and data

security.

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Security Features:

• Security is provided for manufacturing data, user configuration and

provisioning data through encryption using CBC-128 and xRC4.

• RMCP+ authentication and integrity algorithms support includes MD5, SHA1, and

SHA-256.

• Capable of providing PSK and RSA certificate verification

5.25.1.4 Combined Intel® Intelligent Power Node Manager 2.0 and

Management Controller Compliant with DCMI

A fourth SPS FW option combines both Intel Intelligent Power Node Manager 2.0 and

DCMI features.

5.25.2 Intel® AMT 7.0 (SRV/WS SKUs Only)

Intel Active Management Technology is a set of advanced manageability features

developed to meet the evolving demands placed on IT to manage a network

infrastructure. Intel AMT reduces the Total Cost of Ownership (TCO) for IT management

through features such as asset tracking, remote manageability, and robust policy-

based security, resulting in fewer desk-side visits and reduced incident support

durations. Intel AMT extends the manageability capability for IT through Out Of Band

(OOB), allowing asset information, remote diagnostics, recovery, and contain

capabilities to be available on client systems even when they are in a low power, or

“off” state, or in situations when the operating system is hung.

In 2005, Intel developed a set of manageability services called Intel Active

Management Technology (Intel AMT). To increase features and reduce cost in 2006

Intel integrated the operating environment for AMT to run on all Intel chipsets:

• A microcontroller and support HW was integrated in the MCH (North Bridge)

• Additional support HW resided in ICH (South Bridge)

This embedded operating environment is called the Intel Management Engine (Intel

ME). In 2008 Intel integrated an additional microcontroller called the Virtualization

Engine (VE). In 2009 with platform repartitioning, Intel ME and VE HW was designed to

reside in PCH. Key properties of Intel ME:

• Connectivity

— Integration into I/O subsystem of PCH

— Delivers advanced I/O functions

•Security

— More secure (Intel root of trust) and isolated execution

— Increased security of flash file system

• Modularity and Partitioning

— OSV, VMM and SW Independence

— Respond rapidly to competitive changes

•Power

— Always On Always Connected

— Advanced functions in low power S3-S4-S5 operation

— OS independent PM & thermal heuristics

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Intel ME FW provides a variety of services that range from low-level hardware

initialization and provisioning to high-level end-user software based IT manageability

services. One of Intel ME FW’s most established and recognizable features is Intel

Active Management Technology.

5.25.3 Intel® Management Engine Requirements

Intel ME is a platform-level solution that utilizes multiple system components including:

• The Intel ME is the general purpose controller that resides in PCH. It operates in

parallel to and is resource-isolated from the host processor.

• The flash device stores Intel ME firmware (FW) code that is executed by the Intel

ME for its operations. In M0, the highest power state for Intel ME, this code is

loaded from flash into DRAM and cached in secure and isolated SRAM. Code that

resides in DRAM is stored in 16 MB of unified memory architecture (UMA) memory

taken off the highest order rank in channel 0. PCH controls the flash device through

the SPI interface and internal logic.

• In order to interface with DRAM, the Intel ME utilizes the integrated memory

controller (IMC) present in the processor. DM I serves as the interface for

communication between the IMC and Intel ME. This interfacing occurs in only M0

power state. In the lower Intel ME power state, M3, code is executed exclusively

from secure and isolated Intel ME local RAM.

• The LAN controller embedded in PCH as well as Intel Gigabit Platform LAN Connect

device are required for Intel AMT network connectivity. (SRV/WS SKUs Only)

• BIOS to provide asset detection and POST diagnostics (BIOS and Intel ME FW can

optionally share same flash memory device).

• An ISV software package - such as LANDesk*, Altiris, or Microsoft SMS* can be

used to take advantage of Intel AMT’s platform manageability capabilities. (SRV/

WS SKUs Only)

Figure 5-30. PCH Intel® Management Engine (Intel® ME) High-Level Block Diagram

Intel® QPI

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5.26 Serial Peripheral Interface (SPI)

The Serial Peripheral Interface (SPI) is a 4-pin interface that provides a lower-cost

alternative for system flash versus the Firmware Hub on the LPC bus.

The 4-pin SPI interface consists of clock (CLK), master data out (Master Out Slave In

(MOSI)), master data in (Master In Slave Out (MISO)) and an active low chip select

(SPI_CS[1:0]#).

The PCH supports up to two SPI flash devices using two separate Chip Select pins. Each

SPI flash device can be up to 16 MB. The PCH SPI interface supports 20 MHz, 33 MHz

and 50 MHz SPI devices. A SPI Flash device on with Chip Select 0 with a valid

descriptor MUST be attached directly to the PCH.

Communication on the SPI bus is done with a Master – Slave protocol. The Slave is

connected to the PCH and i s imp lemented as a tri-state bus.

Note: If Boot BIOS Strap =”00” LPC is selected as the location for BIOS. BIOS may still be

placed on LPC, but all platforms with PCH requires SPI flash connected directly to the

PCH's SPI bus with a valid descriptor connected to Chip Select 0 in order to boot. R efer

to Section 2.26 for details of Boot BIOS strap settings.

Note: When SPI is selected by the Boot BIOS Destination Strap and a SPI device is detected

by the PCH, LPC based BIOS flash is disabled.

5.26.1 SPI Supported Feature Overview

SPI Flash on the PCH has two operational modes, descriptor and non-descriptor.

5.26.1.1 Non-Descriptor Mode

Non-Descriptor Mode is not supported as a valid flash descriptor is required for all PCH

Platforms.

5.26.1.2 Descriptor Mode

Descriptor Mode is required for all SKUs of PCH. It enables many new features of the

chipset:

• Integrated Gigabit Ethernet and Host processor for Gigabit Ethernet Software

• Intel Active Management Technology (SRV/WS SKUs Only)

• Intel ME Firmware

• PCI Express* root port configuration

• Supports up to two SPI components using two separate chip select pins

— 1 SPI Flash and 1 user authentication device.

• Hardware enforced security restricting master accesses to different regions

• Chipset Soft Strap regions provides the ability to use Flash NVM as an alternative to

hardware pull-up/pull-down resistors for PCH and Processor

• Supports the SPI Fast Read instruction and frequencies of up to 50 MHz

• Support Single Input, Dual Output Fast read

• Uses standardized Flash Instruction Set

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5.26.1.2.1 SPI Flash Regions

In Descriptor Mode the Flash is divided into five separate regions:

Only three masters can access the four regions: Host processor running BIOS code,

Integrated Gi gabit Ethernet and Host processor running Gigabit Etherne t Software, and

Intel Management Engine. The Flash Descriptor and Intel ME region are the only

required regions. The Flash Descriptor has to be in Region 0 and Region 0 must be

located in the first sector of Device 0 (offset 10).

Flash Region Sizes

SPI flash space requirements differ by platform and configuration. The Flash Descriptor

requires one 4 KB or larger block. GbE requires two 4 KB or larger blocks. The amount

of flash space consumed is dependent on the erase granularity of the flash part and the

platform requirements for the Intel ME and BIOS regions. The Intel ME region contains

firmware to support Intel Active Management Technology, and other Intel ME

capabilities.

5.26.2 Flash Descriptor

The maximum size of the Flash Descriptor is 4 KB. If the block/sector size of the SPI

flash device is greater than 4 KB, the flash descriptor will only use the first 4 KB of the

first block. The flash descriptor requires its own block at the bottom of memory (00h).

The information stored in the Flash Descriptor can only be written during the

manufacturing process as its read/write permissions must be set to R ead only when the

computer leaves the manufacturing floor.

The Flash Descriptor is made up of eleven sections (see Figure 5-31).

Region Content

0 Flash Descriptor

1BIOS

2Intel ME

3 Gigabit Ethernet

4Platform Data

Table 5-62. Region Size versus Erase Granularity of Flash Components

Region Size with 4 KB

Blocks Size with 8 KB Blocks Size with 64 KB Blocks

Descriptor 4 KB 8 KB 64 KB

GbE 8 KB 16 KB 128 KB

BIOS Varies by Platform Varies by Platform Varies by Platform

ME Varies by Platform Varies by Platform Varies by Platform

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1. The Flash signature selects Descriptor Mode as well as verifies if the flash is

programmed and functioning. The data at the bottom of the flash (offset 10h) must

be 0FF0A55Ah in order to be in Descriptor mode.

2. The Descriptor map has pointers to the other five descriptor sections as well as the

size of each.

3. The component section has information about the SPI flash in the system

including: the number of components, density of each, illegal instructions (such as

chip erase), and frequencies for read, fast read and write/erase instructions.

4. The Region section points to the three other regions as well as the size of each

region.

Figure 5-31. Flash Descriptor Sections

Descriptor

MAP

Component

Signature

Region

Master

PCH Soft

Straps

10h

4KB

Intel Management

Engine VSCC

Table

Descriptor

Upper MAP

OEM Section

Reserved

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5. The master region contains the security settings for the flash, granting read/write

permissions for each region and identifying each master by a requestor ID. See

Section 5.26.2.1 for more information.

6 & 7. The Processor and PCH chipset soft strap sections contain Processor and PCH

configurable parameters.

8. The Reserved region between the top of the Processor strap section and the

bottom of the OEM Section is reserved for future chipset usages.

9.The Descriptor Upper MAP determines the length and base address of the Intel ME

VSCC Table.

10.The Intel ME VSCC Table holds the JEDEC ID and the VSCC information of the

entire SPI Flash supported by the NVM image.

11.OEM Section is 256 Bytes reserved at the top of the Flash Descriptor for use by

OEM.

5.26.2.1 Descriptor Master Region

The master region defines read and write access setting for each region of the SPI

device. The master region recognizes three masters: BIOS, Gigabit Ethernet, and Intel

ME. Each master is only allowed to do direct reads of its primary regions.

5.26.3 Flash Access

There are two types of flash accesses:

Direct Access:

• Masters are allowed to do direct read only of their primary region.

— Gigabit Ethernet region can only be directly accessed by the Gigabit Ethernet

controller. Gigabit Ethernet software must use Program R egisters to access the

Gigabit Ethernet region.

• Master's Host or Intel ME virtual read address is converted into the SPI Flash Linear

Address (FLA) using the Flash Descriptor Region Base/Limit registers.

Progra m Register Access:

• Program Register Accesses are not allowed to cross a 4 KB boundary and can not

issue a command that might extend across two components.

• Software programs the FLA corresponding to the region desired.

— Software must read the devices Primary R egion Base/Limit address to create a

FLA.

Table 5-63. Region Access Control Table

Master Read/Write Access

Region Processor and BIOS Intel® ME GbE Controller

Descriptor N/A N/A N/A

BIOS Processor and BIOS can

always read from and

write to BIOS Region Read / Write Read / Write

Intel ME Read / Write Intel ME can always read

from and write to Intel

ME Region Read / Write

Gigabit Ethernet Read / Write Read / Write GbE software can always

read from and write to

GbE region

Platform Data Region N/A N/A N/A

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 259

Datasheet

5.26.3.1 Direct Access Security

• Requester ID of the device must match that of the primary Requester ID in the

Master Section

• Calculated Flash Linear Address must fall between primary region base/limit

• Direct Write not allowed

• Direct Read Cache contents are reset to 0's on a read from a different master

— Supports the same cache flush mechanism in ICH7 which includes Program

5.26.3.2 Register Access Security

• Only primary region masters can access the registers.

Note: Processor running Gigabit Ethernet software can access Gigabit Ethernet registers.

• Masters are only allowed to read or write those regions they have read/write

permission.

• Using the Flash Region Access Permissions, one master can give another master

read/write permissions to their area.

• Using the five Protected Range registers, each master can add separate read/write

protection above that granted in the Flash Descriptor for their own accesses.

— Example: BIOS may want to protect different regions of BIOS from being

erased.

— Ranges can extend across region boundaries.

5.26.4 Serial Flash Device Compatibility Requirements

A variety of serial flash devices exist in the mark et. For a serial flash device to be

compatible with the PCH SPI bus, it must meet the minimum requirements detailed in

the following sections.

Note: Depending on the SKU, PCH platforms require Intel ME firmware.

Note: The HEDT SKU only supports the fundamental Intel ME function.

5.26.4.1 PCH SPI Based BIOS Requirements

A serial flash device must meet the following minimum requirements when used

explicitly for system BIOS storage.

• Erase size capability of at least one of the following: 64 Kbytes, 8 Kbytes, 4 Kbytes,

or 256 bytes.

• Device must support multiple writes to a page without requiring a preceding erase

cycle (Refer to Section 5.26.5)

• Serial flash device must ignore the upper address bits such that an address of

FFFFFFh aliases to the top of the flash memory.

• SPI Compatible Mode 0 support (clock phase is 0 and data is latched on the rising

edge of the clock).

• If the device receives a command that is not supported or incomplete (less than 8

bits), the device must complete the cycle gracefully without any impact on the flash

content.

• An erase command (page, sector, block, chip, etc.) must set all bits inside the

designated area (page, sector, block, chip, and so forth) to 1 (Fh).

Functional Description

260 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

• Status Register bit 0 must be set to 1 when a write, erase or write to status register

is in progress and cleared to 0 when a write or erase is NOT in progress.

• Devices requiring the Write Enable command must automatically clear the Write

Enable Latch at the end of Data Program instructions.

• Byte write must be supported. The flexibility to perform a write between 1 byte to

64 bytes is recommended.

• Hardware Sequencing requirements are optional in BIOS only platforms.

• SPI flash parts that do not meet Hardware sequencing command set requirements

may work in BIOS only platforms using software sequencing.

5.26.4.2 Integrated LAN Firmware SPI Flash Requirements

A serial flash device that will be used for system BIOS and Integrated LAN or

Integrated LAN only must meet all the SPI Based BIOS Requirements plus:

• Hardware sequencing.

• 4, 8, or 64 KB erase capability must be supported.

5.26.4.2.1 SPI Flash Unlocking Requirements for Integrated LAN

BIOS must ensure there is no SPI flas h based read/write/erase protection on the GbE

region. GbE firmware and drivers for the integrated LAN need to be able to read, write

and erase the GbE region at all times.

5.26.4.3 Intel® Management Engine (Intel® ME) Firmware SPI Flash

Requirements

Intel ME Firmware must meet the SPI flash based BIOS Requirements plus:

• Hardware sequencing.

• Flash part must be uniform 4 KB erasable block throughout the entire device or

have 64 KB blocks with the first block (lowest address) divided into 4 KB or 8 KB

blocks.

• Write protection scheme must meet SPI flash unlocking requirements for Intel ME.

5.26.4.3.1 SPI Flash Unlocking Requirements for Intel® ME

Flash devices must be globally unlocked (read, write and erase access on the Intel ME

region) from power on by writing 00h to the flash’s status register to disable write

protection.

If the status register must be unprotected, it must use the enable write status register

command 50h or write enable 06h.

Opcode 01h (write to status register) must then be used to write a single byte of 00h

into the status register. This must unlock the entire part. If the SPI flash’s status

If bits [5:2] return a non zero values, the Intel ME firmwar e will send a write of 00h to

the status register. This must keep the flash part unlocked.

If there is no need to execute a write enable on the status register, then opcodes 06h

and 50h must be ignored.

After global unlock, BIOS has the ability to lock down small sections of the flash as long

as they do not involve the Intel ME or GbE region.

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 261

Datasheet

5.26.4.4 Hardware Sequencing Requirements

Table 5-64 contains a list of commands and the associated opcodes that a SPI-based

serial flash device must support in order to be compatible with hardware sequencing.

5.26.4.4.1 Single Input, Dual Output Fast Read

The PCH now supports the functionality of a single in put, dual output fast read. Opcode

and address phase are shifted in serially to the serial flash SI (Serial In) pin. Data is

read out after 8 clocks (dummy bits or wait states) from the both the SI and SO pin

effectively doubling the through put of each fast read output. In order to enable this

functionality, both Single Input Dual Output Fast Read Supported and Fast Read

supported must be enabled.

5.26.4.4.2 JEDEC ID

Since each serial flash device may have unique capabilities and commands, the JEDEC

ID is the necessary mechanism for identifying the device so the uniqueness of the

device can be comprehended by the controller (master). The JEDEC ID uses the opcode

9Fh and a specified implementation and usage model. This JEDEC Standard

Manufacturer and Device ID read method is defined in Standard JESD21-C, PRN03-NV.

5.26.5 Multiple Page Write Usage Model

The system BIOS and Intel ME firmware usage models require that the serial flash

device support multiple writes to a page (minimum of 512 writes) without requiring a

preceding erase command. BIOS commonly uses capabilities such as counters that are

used for error logging and system boot progress logging. These counters are typically

implemented by using byte-writes to ‘increment’ the bits within a page that have been

designated as the counter. The Intel ME firmware usage model requires the capability

for multiple data updates within any given page. These data updates occur using byte-

writes without executing a preceding erase to the given page. Both the BIOS and Intel

ME firmware multiple page write usage models apply to sequential and non-sequential

data writes.

Note: This usage model requirement is based on any given bit only being written once from a

‘1’ to a ‘0’without requiring the preceding erase. An er ase would be required to change

bits back to the 1 state.

Table 5-64. Hardware Sequencing Commands and Opcode Requirements

Commands Opcode Notes

Write to Status Register 01h Writes a byte to SPI flash’s status register. Enable Write to

Status Register command must be run prior to this command.

Program Data 02h Single byte or 64 byte write as determined by flash part

capabilities and software.

Read Data 03h

Write Disable 04h

Read Status 05h Outputs contents of SPI flash’s status register

Write Enable 06h

Fast Read 0Bh

Enable Write to Status

status register

Erase Program-

mable 256B, 4 Kbyte, 8 Kbyte or 64 Kbyte

Full Chip Erase C7h

JEDEC ID 9Fh See Section 5.26.4.4.1.

Functional Description

262 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.26.5.1 Soft Flash Protection

There are two types of flash protection that are not defined in the flash descriptor

supported by PCH:

1. BIOS Range Write Protection

2. SMI#-Based Global Write Protection

Both mechanisms are logically OR’d toget her such that if any of the mechanisms

indicate that the access should be blocked, then it is blocked. Table 5-65 provides a

summary of the mechanisms.

A blocked command will appear to software to finish, except that the Blocked Access

status bit is set in this case.

5.26.5.2 BIOS Range Write Protection

The PCH provides a method for blocking writes to specific ranges in the SPI flash when

the Protected BIOS Ranges are enabled. This is achieved by checking the Opcode type

information (which can be locked down by the initial Boot BIOS) and the address of the

requested command against the base and limit fields of a Write Protected BIOS range.

Note: Once BIOS has locked down the Protected BIOS Range registers, this mechanism

remains in place until the next system reset.

5.26.5.3 SMI# Based Global Write Protection

The PCH provides a method for blocking writes to the SPI flash when the Write

Protected bit is cleared (that is, protected). This is achieved by checking the Opcode

type information (which can be locked down by the initial Boot BIOS) of the requested

command.

The Write Protect and Lock Enable bits interact in the same manner for SPI BIOS as

they do for the FWH BIOS.

5.26.6 Flash Device Configurations

The PCH-based platform must have a SPI flash connected directly to the PCH with a

valid descriptor and Intel ME Firmware. BIOS may be stored in other locations such as

Firmware Hub. Note this will not avoid the direct SPI flash connected to PCH

requirement.

Table 5-65. Flash Protection Mechanism Summary

Mechanism Accesses

Blocked

Range

Specific?

Reset-Override

or SMI#-

Override?

Equivalent Function on FWH

BIOS Range

Write Protection Writes Yes Reset Override FWH Sector Protection

Write Protect Writes No SMI# Override Same as Write Protect in Intel

ICHs for FWH

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 263

Datasheet

5.26.7 SPI Flash Device Recommended Pinout

The table below contains the recommended serial flash device pin-out for an 8-pin

device. Use of the recommended pin-out on an 8-pin device reduces complexities

involved with designing the serial flash device onto a motherboard and allows for

support of a common footprint usage model (refer to Section 5.26.8.1).

Although an 8-pin device is preferred over a 16-pin device due to footprint

compatibility, the following table contains the recommended serial flash device pin-out

for a 16-pin SOIC.

5.26.8 Serial Flash Device Package

5.26.8.1 Common Footprint Usage Model

In order to minimize platform motherboard redesign and to enable platform Bill of

Material (BOM) selectability, many PC System OEM’s design their motherboard with a

single common footprint. This common footprint allows population of a soldered down

device or a socket that accepts a leadless device. This enables the board manufacturer

to support, using selection of the appropriate BOM, either of these solutions on the

same system without requiring any board redesign.

The common footprint usage model is desirable during system debug and by flash

content developers since the leadless device can be easily removed and reprogrammed

without damage to device leads. When the board and flash content is mature for high-

volume production, both the socketed leadless solution and the soldered down leaded

solution are available through BOM selection.

Table 5-66. Recommended Pinout for 8-Pin Serial Flash Device

Pin # Signal

1Chips Select

2 Data Output

3Write Protect

4 Ground

5 Data Input

6 Serial Clock

7Hold / Reset

8Supply Voltage

Table 5-67. Recommended Pinout for 16-Pin Serial Flash Device

Pin # Signal Pin # Signal

1 Hold / Reset 9 Write Protect

2 Supply Voltage 10 Ground

3 No Connect 11 No Connect

4 No Connect 12 No Connect

5 No Connect 13 No Connect

6 No Connect 14 No Connect

7 Chip Select 15 Serial Data In

8 Serial Data Out 16 Serial Clock

Functional Description

264 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.26.8.2 Serial Flash Device Package Recommendations

It is highly recommended that the common footprint usage model be supported. An

example of how this can be accomplished is as follows:

• The recommended pinout for 8-pin serial flash devices is used (refer to

Section 5.26.7).

• The 8-pin device is supported in either an 8-contact VDFPN (6x5 mm ML P) package

or an 8-contact WSON (5x6 mm) package. These packages can fit into a socket

that is land pattern compatible with the wide body SO8 package.

• The 8-pin device is supported in the SO8 (150 mil) and in the wide-body SO8

(200 mil) packages.

The 16-pin device is supported in the SO16 (300 mil) package.

5.27 Fan Control/Thermal Management

The PCH implements 4 PWM and 8 TACH signals for integrated fan speed control.

Note: Integrated fan speed control functionality requires a correctly configured system,

including an appropriate processor, P CH with Intel® ME, Intel® ME Firmware, and

system BIOS support. (SRV/WS SKUs only)

5.27.1 PWM Outputs

This signal is driven as open-drain. An external pull-up resistor is integrated into the

fan to provide the rising edge of the PWM output signal. The PWM output is driven low

during reset, which represents 0% duty cycle to the fans. After reset de-assertion, the

PWM output will continue to be driven low until one of the following occurs:

• The internal PWM control register is programmed to a non-zero value by the

appropriate firmware.

• The watchdog timer expires (enabled and set at 4 seconds by default).

• The polarity of the signal is inverted by firmware.

Note that if a PWM output will be programmed to inverted polarity for a particular fan,

then the low voltage driven during reset represents 100% duty cycle to the fan.

5.27.2 TACH Inputs

This signal is driven as an open-collector or open-drain output from the fan. An

external pull-up is expected to be implemented on the motherboard to provide the

rising edge of the T ACH input. This signal has analog hysteresis and digital filtering due

to the potentially slow rise and fall times. This signal has a weak internal pull-up

resistor to keep the input buffer from floating if the TACH input is not connected to a

fan.

Functional Description

Intel® C600 Series Chipset and Intel® X79 Express Chipset 265

Datasheet

5.28 Feature Capability Mechanism

A set of registers is included in the PCH LPC Interface (Device 31, Function 0, offset

E0h - EBh) that allows the system software or BIOS to easily determine the features

supported by PCH. These registers can be accessed through LPC PCI configuration

space, thus allowing for convenient single point access mechanism for chipset feature

detection.

This set of registers consists of:

Capability ID (FDCAP)

Capability Length (FDLEN)

Capability Version and Vendor-Specific Capability ID (FDVER)

Feature Vector (FVECT)

5.29 Intel® Virtualization Technology (SRV/WS SKUs

Only)

Intel® Virtualization Technology (Intel® VT) makes a single system appear as multiple

independent systems to software. This allows for multiple, independent operating

systems to be running simultaneously on a single system. Intel VT comprises

technology components to support virtualization of platforms based on Intel

architecture microprocessors and chipsets. The first revision of this technology (Intel

VT for IA-32 Intel® Architecture [Intel VT-x]) added hardware support in the processor

to improve the virtualization performance and robustness. The second revision of this

specification (Intel VT for Directed I/O [Intel VT-d]) adds chipset hardware

implementation to improve I/O performance and robustness.

The Intel VT-d spec and other Intel VT documents can be referenced here: http://

www.intel.com/technology/platform-technology/virtualization/index.htm

5.29.1 Intel® Virtualization Technology (Intel® VT) for Directed

I/O (Intel® VT-d) Objectives

The key Intel VT-d objectives are domain based isolation and hardware based

virtualization. A domain can be abstractly defined as an isolated environment in a

platform to which a subset of host physical memory is allocated. Virtualization allows

for the creation of one or more partitions on a single system. This could be multiple

partitions in the same OS or there can be multiple oper ating system instances running

on the same system offering benefits such a s system consolidation, legacy migration,

activity partitioning or security.

5.29.2 Intel® VT-d features supported on PCH

• The following devices and functions support FLR in PCH:

— High Definition Audio (Device 27: Function 0)

— SATA Host Controller #1 (Device 31: Function 2)

— SATA Host Controller #2 (Device 31: Function 5)

— USB2 (EHCI) Host Controller #1(Device 29: Function 0)

— USB2 (EHCI) Host Controller #2(Device 26: Function 0)

— GbE Lan Host Controller (Device 25: Function 0)

• Interrupt virtualization support for IOxAPIC

• Virtualization Support for HPETs

Functional Description

266 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

5.29.3 Support for Function Level Reset (FLR) in PCH

Intel VT -d allows system software (VMM/OS) to assign I/O devices to multiple domains.

The system software, then, requires wa ys to reset I/O devices or their functions within,

as it assigns/re-assigns I/O devices from one domain to another. The reset capability is

required to ensure the devices have undergone proper re-initialization and are not

keeping the stale state. A standard ability to reset I/O devices is also useful for the

VMM in case where a guest domain with assigned devices has become unresponsive or

has crashed.

PCI Express* defines a form of device hot reset which can be initiated through the

Bridge Control register of the root/switch port to which the device is attached.

However, the hot reset cannot be applied selectively to specific device functions. Also,

no similar standard functionality exists for resetting root-complex integrated devices.

Current reset limitations can be addressed through a function level reset (FLR)

mechanism that allows software to independently reset spe cific device functions.

5.29.4 Virtualization Support for PCH’s IOxAPIC

The Intel VT-d architecture extension requires Interrupt Messages to go through the

similar Address Remapping as any other memory requests. This is to allow domain

isolation for interrupts such that a device assigned in one domain is not allowed to

generate interrupts to another domain.

The Address Remapping for Intel VT-d is based on the Bus:Device:Function field

associated with the requests. Hence, it is required for the internal IOxAPIC to initiate

the Interrupt Messages using a unique Bus:Device:Function.

PCH supports BIOS programmable unique Bus:Device:F unction for the internal

IOxAPIC. The Bus:Device:Function field does not change the IOxAPIC functionality in

anyway, nor promoting IOxAPIC as a stand-alone PCI device. The field is only used by

the IOxAPIC in the following:

• As the Requestor ID when initiating Interrupt Messages to the CPU

• As the Completer ID when responding to the reads targeting the IOxAPIC’s

Memory-Mapped I/O registers

5.29.5 Virtualization Support for High Precision Event Timer

(HPET)

The Intel VT-d architecture extension requires Interrupt Messages to go through the

similar Address Remapping as any other memory requests. This is to allow domain

isolation for interrupts such that a device assigned in one domain is not allowed to

generate interrupts to another domain.

The Address Remapping for Intel VT-d is based on the Bus:Device:Function field

associated with the requests. Hence, it is required for the HPET to initiate processor

message interrupts using unique Bus:Device:Function.

PCH supports BIOS programmable unique Bus:Device:F unction for each of the HPET

timers. The Bus:Device:Function field does not change the HPET functionality in

anyway, nor promoting it as a stand-alone PCI device. The field is only used by the

HPET timer in the following:

• As the Requestor ID when initiating processor message interrupts to the Processor

• As the Completer ID when responding to the reads targeting its Memory-Mapped

registers

The registers for the programmable Bus:Device:Function for HPET timer 7:0 reside

under the Device 31:Function 0 LPC Bridge’s configuration space.

Intel® C600 Series Chipset and Intel® X79 Express Chipset 267

Datasheet

PCH Ballout Definition

6PCH Ballout Definition

This chapter contains the PCH ballout information.

Note: Not all listed signals are used on all PCH SKUs. See Chapter 2, “Signal Description” for

details.

Figure 6-1 shows the ballout from a top of the package view. Figure 6-2, Figure 6-3,

Figure 6-4, Figure 6-5 show the ballout zoomed in from a top of package quadrant

view.

Figure 6-1. PCH Ballout (Top View)

393837363534333231302928272625242322212019181716151413121110987654321

AW VSS VSS VSS CLKI N_SAS1P VSS SAS2TXN VSS SAS0TXN VSS SAS_ RBIASN_0 VSS HDA_RST# VSS AD_11 VSS PWM0 VSS AD_0 VSS AD_9 VSS SAS_CLOCK2 VSS PEG0_RP_3 VSS VSS VSS AW

AV NC_3 TP15 CLKIN_ SAS1N SAS3TXN SAS2TXP SAS1TXN SAS0TXP CL KIN_SAS0P SAS_ RBIASP_0 GPIO13 LAD_1 PWM1 TACH0 /GPI O17 STOP# PIRQC# HDA_SYNC LAD_0 AD_5 AD_25 REFCLK14IN SAS_LOAD2 SAS_DATAO UT1 P E G0_RN_3 P E G0_RP_2 PEG0_RN_1 NC_4 AV

AU TP14 TP13 TP17 VSS SAS3TXP VSS SAS1TXP VSS CLKIN_SAS0N VSS AD_8 VSS AD_17 VSS C/BE3# VSS LAD_3 VSS

G NT1#/G PIO 51/G SXDO UT

VSS AD_7 VSS SAS_DATAIN2 VSS PEG0_RN_2 VSS PEG0_RP_1 PEG0_RN_0 TP10 AU

AT TP16 GPIO33 PEG0_RP_0 TP8 AT

AR TP18 LDRQ1#/ G PIO 23 AD_3 REQ 1#/ G PI O 50/ G SXCLK AD_28 SAS7RXP SAS6RXP SAS5RXP SAS4R XP SAS3R XP SAS2RXP SAS1 RXN SAS0R XN PIRQA# PIRQD# PIRQH# /GPIO5 PLOCK# PWM2 TRDY# SAS_ DATAO UT2 SAS_LE D# PE G0_TN_3 PEG0_TP_2 PEG0_TN_1 VSS VCCXUS AR

AP VSS VSS AD_4 SAS7RXN SAS6RXN SAS3RXN SAS2R XN LDRQ0# IRDY# NC_1 AD_13 PE G0_TP_3 PEG0_TN_2 PEG0_TN_0 TP9 AP

AN SAS5TXN SAS4TXN SAS4TXP VSS AD_20 GNT0# VSS VSS SAS5R XN SAS4RXN VSS VSS SAS1RXP SAS0RXP VSS VSS SERR# AD_2 VSS VSS SAS_LOAD1 VCCXU S VSS VSS PEG0_TP_1 PEG0_TP_0 TP7 CLKI N_SPCI E0N AN

AM SAS5TXP TACH7 / GPIO71 VSS VSS C/BE0# AD_15 VSS VSS AD_16 AD_24 VSS VSS PERR# AD_12 VSS VSS SASSMBDATA2 VSS VSS VSS CL KI N_SPCI E0P AM

AL VSS SAS6TXN VSS LAD_2 AD_27 C/BE2# AD_14 AD_30 TP11 REQ0# SAS_RBIASP_ 1 SAS_RBIASN_1 PIRQF#/GPIO3 AD_22 TACH1 /GPIO1 C/BE1# GPIO64 GPIO66 SASSMBCLK2 SASSMBDATA0 VSS SAS_DATAIN1 SAS_CLOCK1 VSS PEG0 _RBIASN PEG0_ RBIASP VSS PETN8 VSS AL

AK SAS7TXN SAS6TXP

REQ 2#/G PI O 52/ G SXSLO A

AD_21 PAR AD_23 CLKIN_PCI

EQ 3#/ G PIO 54/ G SXSRESET

GPIO65 GPIO67 PETP8 PETN7 AK

AJ VSS SAS7TXP VSS TA CH3/ GPIO7 G NT2#/G PIO 53/ G SXDIN VSS DEVSEL# PIRQB# VSS VccIO VccIO VccIO VSS VccRBI AS_ SAS1 VccSAS1_5 Vc cPL LSAS0 VSS vcc3_3 VSS VCCXUS VCCXUS VCCRBIAS_ PU SASSM BCLK0 VSS PERN8 PERP8 VSS PERN4 PERP4 VSS PETP7 VSS AJ

AH HDA_ SDIN_ 2 HDA_ SDIN_ 3 HDA_ SDI N_0 VccIO VccIO VccIO VSS VccRBI AS_SAS1 VccSAS1_5 Vcc PLL SAS0 VSS vcc3_3 VSS VCCXUS VCCXUS SASSM BCLK1 SASSM BDATA1 VSS PERP7 PERN7 VSS PERN3 PERP3 PETP6 PETN6 PETN5 AH

AG HDA_ SDIN_ 1 PWM3 T ACH4/GPIO6 8 VSS AD_19 AD_29 AD_18 PETP5 AG

AF VSS USBP_7 VSS LFRAME# T ACH6 /GPI O70 VSS PIRQE#/GPIO2 FRAME# GNT3#/GPIO55 VccIO VccIO VccIO VccIO Vc cPL LSAS1 VccSAS1_5 VccRBI AS_SAS0 VSS VSS VCCXUS VCCXUS Vcc PLL EXPU VCCXUS VCCXUS VSS PERP6 PERN6 VSS PERN2 PERP2 VSS PETN4 VSS AF

AE USBP_6 USBN_7 VSS VSS VSS VccIO VSS VSS VSS VSS VSS VSS VSS VSS VCCXUS VccIO VSS PERP5 PERN5 VSS PERP1 PERN1 PETP4 PETN3 AE

AD VSS USBN_6 VSS USBP_ 10 USBN_10 VSS AD_26 VSS V5REF Vc c ASW VccASW Vc c ASW VccSCUS Vc c SC U S Vc c SCUS vccCore vccCore vccCore vccCore vccCore VCCXUS VSS PETP3 VSS AD

AC USBP_5 USBP_11 USBN_11 VSS AD_10 vcc3_3 vcc3_3 VccASW Vc c ASW VccASW Vcc SC U S Vc c SC U S Vc cSC U S vccCore vccCore vccCore vccCore vccCore VCCXUS VccIO VccIO VSS VccIO VccIO VSS Reserved Reserved PETN2 AC

AB USBP_4 USBN_4 USBN_5 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VccIO VccIO VSS VccIO VccIO VSS Reserved Reserved PETP2 PETP1 PETN1 AB

AA VSS USBP_3 VSS USBP_1 2 U SBN _12 VSS PIRQG#/GPIO4 AD_31 AD_1 VSS Reserved VSS AA

YUSBP_1 USBN_3 USBP_13 USBN_1 3 VSS T ACH5/ GPIO6 9 TACH2 /GPI O6 AD_6 VccIO VccIO VccIO Vc c ASW Vc c ASW Vc cASW vccCore vccCore vccCore vccCore vccCore VccIO VccIO VccIO VSS VccIO VCCAPLLDMI2 VSS CL KIN_ GND0_ N CL KIN_ GND0_ P Reserved Reserved Y

WVSS USBN_1 VSS vccsus3_3 vccsus3_3 vccsus3_3 Vcc ASW Vc c ASW Vc cASW vccCore vccCore vccCore vccCore vccCore VccIO VccIO VccIO VSS VSS VSS VSS TP2 TP1 VSS Reserved VSS W

VUSBP_2 USBP_9 USBN_9 VSS USBRBIASn HDA_SDO HDA_BCLK VSS VSS VSS VccASW VSS VSS VSS VSS VSS VSS VSS VSS DMI_TXN_0 V

UUSBP_0 USBN_0 USBN_2 USBP_8 USBN_8 VSS USBRBIASp VSS VccAUBG V5REF_Sus Vc c ASW V ccSusHDA VccASW VccASW Vcc ASW vccCore vccCore vccCore vccCore DcpSus DcpSus DMI_ZCOMP DM I _RCOM P VSS DMIRBIAS TP3 VSS DMI_RXP_0 DMI_RXN_0 DMI_TXP_0 DMI_TXP_1 DMI_TXN_1 U

TVSS VSS Vcc ASW VccASW vccsus3_3 Vcc ASW Vc c ASW Vc cASW vccCore vccCore vccCore vccCore VccIO vccsus3_3 VccIO VccIO VSS VSS Vcc3_3 VSS DMI_RXN_1 DMI_RXP_1 VSS VSS T

RDSWODVRE N RTCRST# DPWROK RTCX1 PCH_PWROK VSS CL KIN_ DOT9 6N CL KI N_DOT9 6 P VSS VSS VSS vccsus3_3 VSS VSS vcc3_3 VSS VSS VSS VSS VSS VSS DMI_TXP_2 DMI_TXN_2 DMI_TXN_3 R

PSRTCRST# RTCX2 INTRUDER# VSS TP23 TP24 VSS VccIO TP4 VSS TP5 Vcc APLLEXP VSS DMI_RXP _2 DMI_RXN_2 DMI_TXP_3 P

NVSS

W ARN#/ S USPW RDNACK/ G PIO

VSS VccDSW 3_3 DcpSus vccSPI VccIO VccIO vcc3_3 VccIO VSS VccDFTERM V ccDFTERM vccCore vccCore NC_10 NC_21 VSS NC_6 NC_17 VSS DMI_RXN_3 DMI_RXP_3 VSS VSS VSS N

MSLP_SUS# OC2#/GPIO41 OC1#/GPIO40 GPIO27 INTVRMEN VSS TP6 RSMRST# VSS DcpRTC VSS VccAUPLL VccIO VSS VSS Vcc APLL SATA VccIO VccDFTERM VSS VSS VSS VSS CLKI N_DM I _P CLKI N_ DM I_ N M

LOC5#/GPIO9 VSS vccRTC DcpSusB yp DcpSST vcc3_3 VccIO VSS VccVRM VccIO VccDFTERM VccVRM V_PROC_IO VccDMI Reserved Reserved VSS NC_20 NC_9 VSS NC_12 NC_16 VSS VSS L

KSM L1DATA/ G PI O 7 5 OC7#/GPIO14 SML1CLK/G PIO 58 OC3#/GPIO42 OC0#/GPIO59 GPIO 31/ M G PI O 2 PWRBTN# OC6#/GPIO10 SDATAO UT0/ G PI O 39 SPI_MOSI SPI_CS0# SATAICOMPI Reserved Reserved Reserved Reserved NC_24 NC_5 NC_14 K

JGPIO25 WAKE# SST SM L1 ALERT#/ G PI O 7 4 SM BAL ERT#/ G PI O 11 OC4#/GPIO43 DRAMPWROK GPIO57 GPIO44 SATA0 G P/ G PI O 21 SPI_MISO SPI_CS1# TP21 SATAICOMPO SATA3 COMPO vccCore Reserved Reserved Reserved PROCPWRGD TH RMTRIPB P M_S YNC Reserved NC_15 J

HVSS SMBDATA ADR_CO M PLETE SM L0ALERT#/G PI O 60 SUSAC K# SLP_LAN#/ G PI O 29 GPIO56 SATA4G P/ G PI O 16 SATA5G P/ G PI O 49 TS_VSS2 TS_VSS4 Reserved Reserved PM_SYNC2 VSS NC_19 VSS H

GRI# SMBC LK SML0DATA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC_18 NC_22 G

LAN

PHY

PW R

CTRL/ G PI O 1

GPIO8 VSS SML0C LK GPIO24 APWR OK GPIO26 SLP_S3 # TP12 SCLO CK/ G PI O 22 GPIO34 SM I#/GPIO2 0 SA TA5RXP SATA 4RX P S ATA3RXP S A TA2RXP S A TA1RX P SA TA0RX P Reserved Reserved R eserved Reserved Reserved Reserved Reserved VSS NC_8 VSS F

EGPIO72 SLP_A# GPIO61 PLTRST# PC IR ST# SLP_S4# GPIO15 JTA G_TDI SDATAO UT1/ G PI O 48 GPIO45 BM BUSY#/ G PI O 0 SATA5RXN SATA4RXN SATA3RXN SATA2RXN SATA1RXN SATA0RXN TS_VSS1 TS_VSS3 Reserved Reserved Reserved Reserved PECI NC_11 NC_7 E

DVSS GPIO46 NC_13 VSS D

CJTAG_TMS PME# SUSCLK/ G PI O 6 2 VSS SYS_ PWROK INIT3_3V # SYS_ RESET# VSS SATA3G P/ G PI O 37 VSS SATA2 G P/ G PI O 36 VSS SERIRQ VSS SATA4TXP VSS SATA2TXP VSS SATA3COMPI VSS SATA1TXP VSS Reserved VSS DF_TVS VSS Reserved NC_23 VSS C

BNC_2 SLP_S5 #/ G PI O 63 GPIO73 GPIO47 NMI#/GPIO35 GPIO18 RCIN# SATALED# A20GATE GPIO32 SPI_C LK SATA5TXP SATA4TXN SATA3TXP SATA2TXN CLKIN_SATA_ N TP22 SATA3RRBIAS SATA1TXN SATA0TXP TP19 VSS Reserved Reserved Reserved CHIP_ DET ECT# B

AJTAG_TCK VSS JTAG_TDO GPIO28 VSS S L OAD /GP IO3 8 VSS SPKR VSS SATA1G P/ G PI O 19 VSS SATA5TXN VSS SATA3TXN VSS CLKIN_ SATA_P VSS TP20 VSS SATA0TXN VSS VSS VSS Reserved VSS VSS VSS A

393837363534333231302928272625242322212019181716151413121110987654321

PCH Ballout Definition

268 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Figure 6-2. PCH Ballout (Top View - Upper Left)

39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

AW VSS VSS VSS CLKIN_SAS1P VSS SAS2TXN VSS SAS0TXN VSS SAS_RBIASN_0 VSS HDA_RST# VSS

AV NC_3 TP15 CLKIN_SAS1N SAS3TXN SAS2TXP SAS1TXN SAS0TXP CLKIN_SAS0P SAS_RBIASP_0 GPIO13 LAD_1 PWM1 TACH0/GPIO17

AU TP14 TP13 TP17 VSS SAS3TXP VSS SAS1TXP VSS CLKIN_SAS0N VSS AD_8 VSS AD_17 VSS

AT TP16 GPIO33

AR TP18 LDRQ 1#/ G PI O 23 AD_3 REQ1#/GPIO50/GSXCLK AD_28 SAS7RXP SAS6RXP SAS5RXP SAS4RXP SAS3RXP SAS2RXP SAS1RXN SAS0RXN

AP VSS VSS AD_4 SAS7RXN SAS6RXN SAS3RXN SAS2RXN

AN SAS5TXN SAS4TXN SAS4TXP VSS AD_20 GNT0# VSS VSS SAS5RXN SAS4RXN VSS VSS SAS1RXP SAS0RXP

AM SAS5TXP TACH7/GPIO71 VSS VSS C/BE0# AD_15 VSS VSS AD_16 AD_24 VSS VSS

AL VSS SAS6TXN VSS LAD_2 AD_27 C/BE2# AD_14 AD_30 TP11 REQ0# SAS_RBIASP_1 SAS_RBIASN_1 PIRQF#/GPIO3 AD_22

AK SAS7TXN SAS6TXP

REQ2#/GPIO52/GSXSLOA

AD_21 PAR AD_23 CLKIN_PCI

EQ 3#/G PIO 54/ G SXSRESET

AJ VSS SAS7TXP VSS TACH3 /GPIO7 GNT2#/GPIO53/GSXDIN VSS DEVSEL# PIRQB# VSS VccIO VccIO VccIO VSS VccRBI AS_SAS1 VccSAS1_5

AH HDA_ SDIN_2 HDA_SDIN_3 HDA_SDIN_0 VccIO VccIO VccIO VSS VccRBI AS_SAS1 VccSAS1_5

AG HDA_ SDIN_1 PWM3 TACH4/GPIO68 VSS AD_19 AD_29 AD_18

AF VSS USBP_7 VSS LFRAME# TACH6 /GPIO70 VSS PIRQE#/GPIO2 FRAME# GNT 3 # /GP IO5 5 VccIO VccIO VccIO VccIO VccPLLSAS1 VccSAS1_5

AE USBP_6 USBN_7 VSS VSS VSS VccIO VSS VSS

AD VSS USBN_6 VSS USBP_10 USBN_10 VSS AD_26 VSS V5REF VccASW VccASW VccASW VccSCUS VccSCUS VccSCUS

AC USBP_5 USBP_11 USBN_11 VSS AD_10 vcc3_3 vcc3_3 VccASW VccASW VccASW VccSCUS VccSCUS VccSCUS

AB USBP_4 USBN_4 USBN_5 VSS VSS VSS VSS VSS VSS

AA VSS USBP_3 VSS USBP_12 USBN_12 VSS P IRQG# / GP IO4 AD_31 AD_1

YUSBP_1 USBN_3 USBP_13 USBN_13 VSS TACH5/GPIO69 TACH2/GPIO6 AD_6 VccIO VccIO VccIO VccASW VccASW VccASW

WVSS USBN_1 VSS vccsus3_3 vccsus3_3 vccsus3_3 VccASW VccASW VccASW

VUSBP_2 USBP_9 USBN_9 VSS USBRBIASn HDA_SDO HDA_BCLK VSS VSS VSS VccASW VSS VSS

UUSBP_0 USBN_0 USBN_2 USBP_8 USBN_8 VSS USBRBIASp VSS VccAUBG V5REF_Sus VccASW VccSusHDA Vcc ASW Vc cASW VccASW

Intel® C600 Series Chipset and Intel® X79 Express Chipset 269

Datasheet

PCH Ballout Definition

Figure 6-3. PCH Ballout (Top View - Upper Right)

2019181716151413121110987654321

AD_11 VSS PWM0 VSS AD_0 VSS AD_9 VSS SAS_CLOCK2 VSS PEG0_RP_3 VSS VSS VSS AW

STOP# PIRQC# HDA_SYNC LAD_0 AD_5 AD_25 REFCLK14IN SAS_LOAD2 SAS_DATAO UT1 PEG0_RN_3 PEG0_RP_2 PEG0_RN_1 NC_4 AV

C/BE3# VSS LAD_3 VSS GNT1#/GPIO51/GSXDOUT VSS AD_7 VSS SAS_DATAIN2 VSS PEG0_RN_2 VSS PEG0_RP_1 PEG0_RN_0 TP10 AU

PE G0_RP_0 TP8 AT

PIRQA# PIRQD# PIRQH#/GPIO5 PLOCK# PWM2 TRDY# SAS_ DATAO UT2 SAS_LED# PEG0_TN_3 PEG0_TP_2 PEG0_TN_1 VSS VCCXUS AR

LDRQ0# IRDY# NC_1 AD_13 PEG0_TP_3 PEG0_TN_2 PEG0_TN_0 TP9 AP

VSS VSS SERR# AD_2 VSS VSS SAS_LOAD1 VCCXUS VSS VSS PEG0_TP_1 PEG0_TP_0 TP7 CL KI N_ SPCI E0 N AN

PERR# AD_12 VSS VSS SASSMBDATA2 VSS VSS VSS CLKI N_ SPCI E0P AM

TACH1/GPIO1 C/BE1# GPIO64 GPIO66 SASSMBCLK2 SASSMBDATA0 VSS SAS_DATAIN1 SAS_CLOCK1 VSS PEG0_RBIASN PEG0_RBIASP VSS PETN8 VSS AL

GPIO65 GPIO67 PETP8 PETN7 AK

VccPLLSAS0 VSS vcc3_3 VSS VCCXUS VCCXUS VCCRBIAS_PU SASSM BCLK0 VSS PERN8 PERP8 VSS PERN4 PERP4 VSS PETP7 VSS AJ

VccPLLSAS0 VSS vcc3_3 VSS VCCXUS VCCXUS SASSMBCLK1 SASSMBDATA1 VSS PERP7 PERN7 VSS PERN3 PERP3 PETP6 PETN6 PETN5 AH

PETP5 AG

VccRBI AS_SAS0 VSS VSS VCCXUS VCCXUS Vcc PLLEXPU VCCXUS VCCXUS VSS PERP6 PERN6 VSS PERN2 PERP2 VSS PETN4 VSS AF

VSS VSS VSS VSS VSS VSS VCCXUS VccIO VSS PERP5 PERN5 VSS PERP1 PERN1 PETP4 PETN3 AE

vccCore vccCore vccCore vccCore vccCore VCCXUS VSS PETP3 VSS AD

vccCore vccCore vccCore vccCore vccCore VCCXUS VccIO VccIO VSS VccIO VccIO VSS Reserved Reserved PETN2 AC

VSS VSS VSS VSS VSS VSS VccIO VccIO VSS VccIO VccIO VSS Reserved Reserved PETP2 PETP1 PETN1 AB

VSS Reserved VSS AA

vccCore vccCore vccCore vccCore vccCore VccIO VccIO VccIO VSS VccIO VCCAPLLDMI2 VSS CLKIN_GND0_ N CLKIN_ GND0_P Reserved Reserved Y

vccCore vccCore vccCore vccCore vccCore VccIO VccIO VccIO VSS VSS VSS VSS TP2 TP1 VSS Reserved VSS W

VSS VSS VSS VSS VSS VSS DMI_TXN_0 V

vccCore vccCore vccCore vccCore DcpSus DcpSus DMI_ZCOMP DM I _RCOM P VSS DMIRBIAS TP3 VSS DMI_RXP_0 DMI_RXN_0 DMI_TXP_0 DMI_TXP_1 DMI_TXN_1 U

PCH Ballout Definition

270 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Figure 6-4. PCH Ballout (Top View - Lower Left)

UUSBP_0 USBN_0 USBN_2 USBP_8 USBN_8 VSS USBRBIASp VSS VccAUBG V5REF_Sus Vc cASW VccSusHDA VccASW Vc cASW Vcc ASW

TVSS VSS Vc cASW VccASW vccsus3_3 Vcc ASW VccASW VccASW

RDSWODVREN RTCRST# DPWROK RTCX1 PCH_PWROK VSS CLKIN_DOT96 N CLKIN_DOT96 P VSS VSS VSS vccsus3_3 VSS VSS vcc3_3

PSRTCRST# RTCX2 INTRUDER# VSS TP23 TP24 VSS

NVSS

W ARN#/ SUSPW RDNACK/ G PI O

VSS VccDSW3_3 DcpSus vccSPI VccIO VccIO vcc3_3

MSLP_SUS# OC2#/GPIO41 OC1#/GPIO40 GPIO27 INTVRMEN VSS TP6 RSMRST# VSS DcpRTC VSS VccAUPLL VccIO VSS VSS

LOC5#/GPIO9 VSS vccRTC DcpSusByp DcpSST vcc3_3 VccIO VSS

KSM L1DATA/ G PI O 75 OC7#/GPIO14 SML1CLK/G PI O 58 OC3 # / GPI O4 2 OC0 # / GPI O5 9 GPIO31/MGPIO2 PWRBTN# OC6#/GPIO10 SDATAO UT0/ G PI O 39 SPI_MOSI

JGPIO25 WAKE# SST SM L1 ALERT# / G PI O 7 4 SM BAL ERT#/ G PI O 11 OC4 # / GPI O4 3 DRAM P WROK GPIO57 GPIO44 SATA0G P/ G PI O 2 1 SPI_MISO SPI_CS1#

HVSS SMBDATA ADR_CO M PLETE SM L0 ALERT#/ G PI O 60 SUSACK# SLP_LAN#/ G PI O 2 9 GPIO56 SATA4G P/ G PI O 1 6 SATA5G P/ G PI O 49

GRI# SMBCLK SML0DATA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

LAN

PHY

PW R

CTRL/ G PI O 1

GPIO8 VSS SML0CLK GPIO24 APWROK GPIO26 SLP_S3# TP12 SCLOCK/ G PI O 22 GPIO34 SM I#/GPIO20 SATA5RXP SATA4RXP

EGPIO72 SLP_A# GPIO61 PLTRST# PCIRST# SLP_S4# GPIO15 JTAG_TDI SDATAO UT1/ G PI O 48 GPIO45 BM BUSY#/ G PI O 0 SATA5RXN SATA4RXN

DVSS GPIO46

CJTAG_TMS PME# SUSCLK/ G PI O 62 VSS SYS_PWROK INIT3_3V# SYS_RESET# VSS SATA3G P/ G PI O 37 VSS SATA2G P/ G PI O 3 6 VSS SERIRQ VSS

BNC_2 SLP_S5# / G PI O 63 GPIO73 GPIO47 NM I# /GPIO35 GPIO18 RCIN# SATALED# A20GATE GPIO32 SPI_CLK SATA5TXP SATA4TXN

AJTAG_TCK VSS JTAG_TDO GPIO28 VSS S L OAD/ GPI O3 8 VSS SPKR VSS SATA1 G P/ G PI O 19 VSS SATA5TXN VSS

39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

Intel® C600 Series Chipset and Intel® X79 Express Chipset 271

Datasheet

PCH Ballout Definition

Figure 6-5. PCH Ballout (Top View - Lower Right)

vccCore vccCore vccCore vccCore DcpSus DcpSus DMI_ZCOMP DMI_RCOMP VSS DMIRBIAS TP3 VSS DMI_RXP_0 DMI_RXN_0 DMI_TXP_0 DMI_TXP_1 DMI_TXN_1 U

vccCore vccCore vccCore vccCore VccIO vccsus3_3 VccIO VccIO VSS VSS Vcc3_3 VSS DMI_RXN_1 DMI_RXP_1 VSS VSS T

VSS VSS VSS VSS VSS VSS DMI_TXP_2 DMI_TXN_2 DMI_TXN_3 R

VccIO TP4 VSS TP5 Vc cAPLLEXP VSS DMI_RXP_2 DMI_RXN_2 DMI_TXP_3 P

VccIO VSS VccDFTERM VccDFTERM vccCore vccCore NC_10 NC_21 VSS NC_6 NC_17 VSS DMI_RXN_3 DMI_RXP_3 VSS VSS VSS N

Vcc APLLSATA VccIO VccDFTERM VSS VSS VSS VSS CLKIN_ DMI _P CLKIN_DMI _N M

VccVRM VccIO VccDFTERM VccVRM V_PROC_IO VccDMI Reserved Reserved VSS NC_20 NC_9 VSS NC_12 NC_16 VSS VSS L

SPI_CS0# SATAICOMPI Reserved Reserved Reserved Reserved NC_24 NC_5 NC_14 K

TP21 SATAICOMPO SATA3COMPO vccCore Reserved Reserved Reserved PROCPWRGD THRMTRIPB PM_SYNC Reserved NC_15 J

TS_VSS2 TS_VSS4 Reserved Reserved PM_SYNC2 VSS NC_19 VSS H

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC_18 NC_22 G

SATA3RXP SATA2RXP SATA1RXP SATA0RXP Reserved Reserved Reserved Reserved Reserved Reserved Reserved VSS NC_8 VSS F

SATA3RXN SATA2RXN SATA1RXN SATA0RXN TS_VSS1 TS_VSS3 Reserved Reserved Reserved Reserved PECI NC_11 NC_7 E

NC_13 VSS D

SATA4TXP VSS SATA2TXP VSS SATA3COMPI VSS SATA1TXP VSS Reserved VSS DF_TVS VSS Reserved NC_23 VSS C

SATA3TXP SATA2TXN CLKIN_SATA_N TP22 SATA3RRBIAS SATA1TXN SATA0TXP TP19 VSS Reserved Reserved Reserved CHIP_DETECT# B

SATA3TXN VSS CLKIN_SATA_P VSS TP20 VSS SATA0TXN VSS VSS VSS Reserved VSS VSS VSS A

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

272 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

PCH Ballout Definition

Table 6-1. PCH Ballout by

Signal Name

(Sheet 1 of 25)

PCH Ball Name Ball #

A20GATE B26

AD0 AW15

AD1 AA30

AD10 AC32

AD11 AW20

AD12 AM18

AD13 AP12

AD14 AL31

AD15 AM30

AD16 AM25

AD17 AU22

AD18 AG30

AD19 AG32

AD2 AN15

AD20 AN34

AD21 AK33

AD22 AL21

AD23 AK27

AD24 AM24

AD25 AV13

AD26 AD32

AD27 AL34

AD28 AR33

AD29 AG31

AD3 AR36

AD30 AL30

AD31 AA31

AD4 AP36

AD5 AV14

AD6 Y30

AD7 AU12

AD8 AU25

AD9 AW12

ADR_COMPLETE H37

APWROK F33

BMBUSY#/ GPIO0 E24

C/BE0# AM31

C/BE1# AL18

C/BE2# AL33

C/BE3# AU20

CHIP_DETECT# B2

CLKIN_DMI_N M1

CLKIN_DMI_P M2

CLKIN_DOT_96N R32

CLKIN_DOT_96P R31

CLKIN_GND0_N Y5

CLKIN_GND0_P Y4

CLKIN_PCI AK22

CLKIN_SAS0_N AU28

CLKIN_SAS0_P AV27

CLKIN_SAS1_N AV33

CLKIN_SAS1_P AW33

CLKIN_SATA_N B17

CLKIN_SATA_P A17

CLKIN_SPCIE0_N AN1

CLKIN_SPCIE0_P AM2

DcpRTC M28

DcpSST L25

DcpSus U15

DcpSus U16

DcpSus N26

DcpSusByp L26

DEVSEL# AJ32

DF_TVS C7

DMI_IRCOMP U12

DMI_RXN_0 U5

DMI_RXN_1 T6

DMI_RXN_2 P4

DMI_RXN_3 N5

DMI_RXP_0 U6

DMI_RXP_1 T5

DMI_RXP_2 P5

DMI_RXP_3 N4

Table 6-1. PCH Ballout by

Signal Name

(Sheet 2 of 25)

PCH Ball Name Ball #

DMI_TXN_0 V2

DMI_TXN_1 U1

DMI_TXN_2 R2

DMI_TXN_3 R1

DMI_TXP_0 U3

DMI_TXP_1 U2

DMI_TXP_2 R3

DMI_TXP_3 P2

DMI_ZCOMP U13

DMIRBIAS U9

DPWROK R37

DRAMPWROK J28

DSWODVREN R39

FRAME# AF31

GNT0# AN33

GNT1# / GPIO51 /

GSXDOUT AU15

GNT2# / GPIO53 /

GSXDIN AJ34

GNT3# / GPIO55 AF30

GPIO13 AV24

GPIO15 E30

GPIO18 B29

GPIO24 F34

GPIO25 J38

GPIO26 F31

GPIO27 M35

GPIO28 A33

GPIO31/MGPIO2 K33

GPIO32 B24

GPIO33 AT37

GPIO34 F25

GPIO44 J25

GPIO45 E25

GPIO46 D37

GPIO47 B32

GPIO56 H27

Table 6-1. PCH Ballout by

Signal Name

(Sheet 3 of 25)

PCH Ball Name Ball #

Intel® C600 Series Chipset and Intel® X79 Express Chipset 273

Datasheet

PCH Ballout Definition

GPIO57 J27

GPIO64 AL16

GPIO65 AK16

GPIO66 AL15

GPIO67 AK15

GPIO72 E38

GPIO73 B33

GPIO8 F38

HDA_BCLK V29

HDA_RST# AW22

HDA_SDIN0 AH37

HDA_SDIN1 AG38

HDA_SDIN2 AH39

HDA_SDIN3 AH38

HDA_SDO V30

HDA_SYNC AV17

INIT3_3V# C31

INTRUDER# P34

INTVRMEN M34

IRDY# AP18

JTAG_TCK A37

JTAG_TDI E28

JTAG_TDO A34

JTAG_TMS C39

LAD0 AV15

LAD1 AV23

LAD2 AL36

LAD3 AU17

LAN_PHY_PWR_CT

RL / GPIO12 F39

LDRQ0# AP19

LDRQ1# / GPIO2 3 AR37

LFRAME# AF36

NC_1 AP13

NC_2 B38

NC_3 AV38

NC_4 AV2

Table 6-1. PCH Ballout by

Signal Name

(Sheet 4 of 25)

PCH Ball Name Ball #

NMI#/GPIO35 B31

NC_5 K2

NC_6 N9

NC_7 E2

NC_8 F2

NC_9 L8

NC_10 N12

NC_11 E3

NC_12 L6

NC_13 D3

NC_14 K1

NC_15 J2

NC_16 L5

NC_17 N8

NC_18 G3

NC_19 H2

NC_20 L9

NC_21 N11

NC_22 G1

NC_23 C3

NC_24 K3

OC0# / GPIO59 K34

OC1# / GPIO40 M37

OC2# / GPIO41 M38

OC3# / GPIO42 K36

OC4# / GPIO43 J30

OC5# / GPIO9 L39

OC6# / GPIO10 K30

OC7# / GPIO14 K38

PAR AK28

PCH_PWROK R34

PCIRST# E33

PECI E4

PEG0_RBIASN AL5

PEG0_RBIASP AL4

PEG0_RN0 AU3

Table 6-1. PCH Ballout by

Signal Name

(Sheet 5 of 25)

PCH Ball Name Ball #

PEG0_RN1 AV5

PEG0_RN2 AU7

PEG0_RN3 AV8

PEG0_RP0 AT3

PEG0_RP1 AU5

PEG0_RP2 AV6

PEG0_RP3 AW7

PEG0_TN0 AP3

PEG0_TN1 AR4

PEG0_TN2 AP6

PEG0_TN3 AR7

PEG0_TP0 AN3

PEG0_TP1 AN4

PEG0_TP2 AR6

PEG0_TP3 AP7

PERn1 AE4

PERn2 AF5

PERn3 AH6

PERn4 AJ6

PERn5 AE8

PERn6 AF8

PERn7 AH8

PERn8 AJ9

PERp1 AE5

PERp2 AF4

PERp3 AH5

PERp4 AJ5

PERp5 AE9

PERp6 AF9

PERp7 AH9

PERp8 AJ8

PERR# AM19

PETn1 AB1

PETn2 AC2

PETn3 AE1

PETn4 AF2

Table 6-1. PCH Ballout by

Signal Name

(Sheet 6 of 25)

PCH Ball Name Ball #

274 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

PCH Ballout Definition

PETn5 AH1

PETn6 AH2

PETn7 AK1

PETn8 AL2

PETp1 AB2

PETp2 AB3

PETp3 AD2

PETp4 AE3

PETp5 AG2

PETp6 AH3

PETp7 AJ2

PETp8 AK3

PIRQA# AR19

PIRQB# AJ30

PIRQC# AV18

PIRQD# AR18

PIRQE# / GPIO2 AF32

PIRQF# / GPIO3 AL22

PIRQG# / GPIO4 AA32

PIRQH# / GPIO5 AR16

PLOCK# AR15

PLTRST# E34

PM_SYNC J6

PM_SYNC2 H4

PME# C37

PROCPWRGD J9

PWM0 AW17

PWM1 AV22

PWM2 AR13

PWM3 AG36

PWRBTN# K31

RCIN# B28

REFCLK14IN AV12

REQ0# AL27

REQ1# / GPIO50 /

GSXCLK AR34

Table 6-1. PCH Ballout by

Signal Name

(Sheet 7 of 25)

PCH Ball Name Ball #

REQ2# / GPIO52 /

GSXSLOAD AK34

REQ3# / GPIO54 /

GSXSRESET# AK21

Reserved A7

Reserved AA2

Reserved AB5

Reserved AB6

Reserved AC5

Reserved AC6

Reserved B5

Reserved B6

Reserved B8

Reserved C10

Reserved C5

Reserved E10

Reserved E6

Reserved E7

Reserved E9

Reserved F10

Reserved F12

Reserved F13

Reserved F4

Reserved F6

Reserved F7

Reserved F9

Reserved H10

Reserved H9

Reserved J10

Reserved J12

Reserved J13

Reserved J4

Reserved K12

Reserved K13

Reserved K6

Reserved K7

Reserved L12

Table 6-1. PCH Ballout by

Signal Name

(Sheet 8 of 25)

PCH Ball Name Ball #

Reserved L13

Reserved W2

Reserved Y1

Reserved Y3

RI# G39

RSMRST# M30

RTCRST# R38

RTCX1 R36

RTCX2 P36

SAS0RXN AR21

SAS1RXN AR22

SAS2RXN AP24

SAS3RXN AP25

SAS4RXN AN27

SAS5RXN AN28

SAS6RXN AP30

SAS7RXN AP31

SAS0RXP AN21

SAS1RXP AN22

SAS2RXP AR24

SAS3RXP AR25

SAS4RXP AR27

SAS5RXP AR28

SAS6RXP AR30

SAS7RXP AR31

SAS0TXN AW28

SAS1TXN AV29

SAS2TXN AW30

SAS3TXN AV32

SAS4TXN AN38

SAS5TXN AN39

SAS6TXN AL38

SAS7TXN AK39

SAS0TXP AV28

SAS1TXP AU30

SAS2TXP AV31

SAS3TXP AU33

Table 6-1. PCH Ballout by

Signal Name

(Sheet 9 of 25)

PCH Ball Name Ball #

Intel® C600 Series Chipset and Intel® X79 Express Chipset 275

Datasheet

PCH Ballout Definition

SAS4TXP AN37

SAS5TXP AM38

SAS6TXP AK37

SAS7TXP AJ38

SAS_CLOCK1 AL8

SAS_LOAD1 AN10

SAS_DATAIN1 AL9

SAS_DATAOUT1 AV9

SAS_CLOCK2 AW10

SAS_LOAD2 AV10

SAS_DATAIN2 AU10

SAS_DATAOUT2 AR10

SAS_LED# AR9

SAS_RBIASN0 AW25

SAS_RBIASN1 AL24

SAS_RBIASP0 AV26

SAS_RBIASP1 AL25

SASSMBCLK0 AJ12

SASSMBCLK1 AH13

SASSMBCLK2 AL13

SASSMBDATA0 AL11

SASSMBDATA1 AH12

SASSMBDATA2 AM13

SATA0RXN E15

SATA1RXN E16

SATA2RXN E18

SATA3RXN E19

SATA4RXN E21

SATA5RXN E22

SATA0RXP F15

SATA1RXP F16

SATA2RXP F18

SATA3RXP F19

SATA4RXP F21

SATA5RXP F22

SATA0TXN A12

Table 6-1. PCH Ballout by

Signal Name

(Sheet 10 of 25)

PCH Ball Name Ball #

SATA1TXN B13

SATA2TXN B18

SATA3TXN A20

SATA4TXN B21

SATA5TXN A22

SATA0TXP B12

SATA1TXP C12

SATA2TXP C17

SATA3TXP B19

SATA4TXP C20

SATA5TXP B22

SATA0GP / GPIO21 J24

SATA1GP / GPIO19 A25

SATA2GP / GPIO36 C25

SATA3GP / GPIO37 C28

SA T A4GP / GPIO16 H22

SA T A5GP / GPIO49

/ TEMP_ALERT# H21

SATAICOMPI K18

SATAICOMPO J18

SATALED# B27

SCLOCK / GPIO22 F27

SDATAOUT0 /

GPIO39 K25

SDATAOUT1 /

GPIO48 E27

SATA3RBIAS B14

SATA3COMPI C15

SATA3COMPO J16

SERIRQ C22

SERR# AN16

SLOAD / GPIO38 A30

SLP_A# E37

SLP_LAN# /

GPIO29 H28

SLP_S3# F30

SLP_S4# E31

SLP_S5# / GPIO63 B35

Table 6-1. PCH Ballout by

Signal Name

(Sheet 11 of 25)

PCH Ball Name Ball #

SLP_SUS# M39

SMBALERT# /

GPIO11 J31

SMBCLK G37

SMBDATA H38

SMI# / GPIO20 F24

SML0ALERT# /

GPIO60 H34

SML0CLK F36

SML0DATA G36

SML1ALERT# /

GPIO74 J33

SML1CLK / GPIO58 K37

SML1DATA /

GPIO75 K39

SPI_CLK B23

SPI_CS0# K19

SPI_CS1# J21

SPI_MISO J22

SPI_MOSI K24

SPKR A28

SRTCRST# P38

SST J34

STOP# AV19

SUSACK# H33

SUSWARN# /

GPIO30 N38

GPIO61 E36

SUSCLK / GPIO62 C35

SYS_PWROK C33

SYS_RESET# C30

TACH0 / GPIO17 AV21

TACH1 / GPIO1 AL19

TACH2 / GPIO6 Y31

TACH3 / GPIO7 AJ35

TACH4 / GPIO68 AG34

TACH5 / GPIO69 Y32

TACH6 / GPIO70 AF34

Table 6-1. PCH Ballout by

Signal Name

(Sheet 12 of 25)

PCH Ball Name Ball #

276 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

PCH Ballout Definition

TACH7 / GPIO71 AM36

THRMTRIP# J7

TP1 W4

TP10 AU1

TP11 AL28

TP12 F28

TP13 AU37

TP14 AU39

TP15 AV35

TP16 AT39

TP17 AU35

TP18 AR38

TP19 B10

TP2 W5

TP20 A15

TP21 J19

TP22 B15

TP23 P32

TP24 P31

TP3 U8

TP4 P11

TP5 P9

TP6 M32

TP7 AN2

TP8 AT1

TP9 AP1

TRDY# AR12

TS_VSS1 E13

TS_VSS2 H16

TS_VSS3 E12

TS_VSS4 H15

USBP0N U38

USBP0P U39

USBP10N AD34

USBP10P AD35

USBP11N AC34

USBP11P AC35

Table 6-1. PCH Ballout by

Signal Name

(Sheet 13 of 25)

PCH Ball Name Ball #

USBP12N AA34

USBP12P AA36

USBP13N Y34

USBP13P Y36

USBP1N W38

USBP1P Y39

USBP2N U37

USBP2P V38

USBP3N Y37

USBP3P AA38

USBP4N AB38

USBP4P AB39

USBP5N AB37

USBP5P AC38

USBP6N AD38

USBP6P AE39

USBP7N AE37

USBP7P AF38

USBP8N U34

USBP8P U35

USBP9N V34

USBP9P V35

USBRBIAS U32

USBRBIAS# V32

V_PROC_IO L16

V5REF AD29

V5REF_Sus U28

Vcc3_3 R22

Vcc3_3 N22

Vcc3_3 AJ18

Vcc3_3 AH18

Vcc3_3 AC30

Vcc3_3 AC29

Vcc3_3 T8

Vcc3_3 L24

VccCore AD20

VccCore AD19

Table 6-1. PCH Ballout by

Signal Name

(Sheet 14 of 25)

PCH Ball Name Ball #

VccCore AD18

VccCore AD17

VccCore AD16

VccCore AC20

VccCore AC19

VccCore AC18

VccCore AC17

VccCore AC16

VccCore Y20

VccCore Y19

VccCore Y18

VccCore Y17

VccCore Y16

VccCore W20

VccCore W19

VccCore W18

VccCore W17

VccCore W16

VccCore U20

VccCore U19

VccCore U18

VccCore U17

VccCore T20

VccCore T19

VccCore T18

VccCore T17

VccCore N16

VccCore N15

VccCore J15

VccDFTERM N18

VccDFTERM N17

VccDFTERM M18

VccDFTERM L18

VccDMI L15

VccDSW3_3 N28

VccIO AE11

VccIO AC13

Table 6-1. PCH Ballout by

Signal Name

(Sheet 15 of 25)

PCH Ball Name Ball #

Intel® C600 Series Chipset and Intel® X79 Express Chipset 277

Datasheet

PCH Ballout Definition

VccIO AC12

VccIO AC9

VccIO AC8

VccIO AB13

VccIO AB12

VccIO AB9

VccIO AB8

VccIO Y15

VccIO Y12

VccIO Y11

VccIO Y9

VccIO W15

VccIO W12

VccIO W11

VccIO T13

VccIO T12

VccIO T16

VccIO P12

VccIO N24

VccIO N23

VccIO M24

VccIO L23

VccIO Y28

VccIO Y26

VccIO Y25

VccIO N20

VccIO M19

VccIO L19

VccAUPLL M25

VccRBIAS_SAS0 AF20

VccRBIAS_SAS1 AJ23

VccRBIAS_SAS1 AH23

VccIO AJ28

VccIO AJ26

VccIO AJ25

VccIO AH28

Table 6-1. PCH Ballout by

Signal Name

(Sheet 16 of 25)

PCH Ball Name Ball #

VccIO AH26

VccIO AH25

VccIO AF28

VccIO AF26

VccIO AF25

VccIO AF24

VccIO AE24

VccSCUS AC22

VccSCUS AC23

VccSCUS AC24

VccSCUS AD22

VccSCUS AD23

VccSCUS AD24

VccXUS AR2

VccXUS AN9

VccRBIAS_PU AJ13

VccXUS AJ16

VccXUS AJ15

VccXUS AH16

VccXUS AH15

VccXUS AF17

VccXUS AF16

VccXUS AF12

VccXUS AF11

VccXUS AC15

VccXUS AD15

VccXUS AE12

VccASW AD28

VccASW AD26

VccASW AD25

VccASW AC28

VccASW AC26

VccASW AC25

VccASW Y24

VccASW Y23

VccASW Y22

Table 6-1. PCH Ballout by

Signal Name

(Sheet 17 of 25)

PCH Ball Name Ball #

VccASW W24

VccASW W23

VccASW W22

VccASW V24

VccASW U24

VccASW U23

VccASW U22

VccASW T24

VccASW T23

VccASW T22

VccASW U26

VccASW T28

VccASW T26

VccAPLLDMI2 Y8

VccAPLLEXP P8

VccAPLLSATA M20

VccPLLSAS0 AJ20

VccPLLSAS0 AH20

VccPLLSAS1 AF23

VccPLLEXPU AF15

VccRTC L28

VccSAS1_5 AJ22

VccSAS1_5 AH22

VccSAS1_5 AF22

VccSPI N25

VccSus3_3 T25

VccSus3_3 R25

VccSus3_3 W28

VccSus3_3 W26

VccSus3_3 W25

VccAUBG U29

VccSus3_3 T15

VccSusHDA U25

VccVRM L17

VccVRM L20

Vss (0) AW37

Table 6-1. PCH Ballout by

Signal Name

(Sheet 18 of 25)

PCH Ball Name Ball #

278 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

PCH Ballout Definition

Vss AW36

Vss AW34

Vss AW31

Vss AW29

Vss AW26

Vss AW24

Vss AW21

Vss AW19

Vss AW16

Vss (10) AW13

Vss AW11

Vss AW8

Vss AW6

Vss AW4

Vss AW3

Vss AU34

Vss AU31

Vss AU29

Vss AU26

Vss (20) AU24

Vss AU21

Vss AU19

Vss AU16

Vss AU13

Vss AU11

Vss AU8

Vss AU6

Vss AR3

Vss AP39

Vss (30) AP37

Vss AN36

Vss AN31

Vss AN30

Vss AN25

Vss AN24

Vss AN19

Vss AN18

Table 6-1. PCH Ballout by

Signal Name

(Sheet 19 of 25)

PCH Ball Name Ball #

Vss AN13

Vss AN12

Vss (40) AN7

Vss AN6

Vss AM34

Vss AM33

Vss AM28

Vss AM27

Vss AM22

Vss AM21

Vss AM16

Vss AM15

Vss (50) AM10

Vss AM9

Vss AM4

Vss AL39

Vss AL37

Vss AL10

Vss AL6

Vss AL3

Vss AL1

Vss AJ39

Vss (60) AJ37

Vss AJ33

Vss AJ29

Vss AJ24

Vss AJ19

Vss AJ17

Vss AJ11

Vss AJ7

Vss AJ3

Vss AJ1

Vss (70) AH24

Vss AH19

Vss AH17

Vss AH11

Vss AH7

Table 6-1. PCH Ballout by

Signal Name

(Sheet 20 of 25)

PCH Ball Name Ball #

Vss AG33

Vss AF39

Vss AF37

Vss AF33

Vss AF19

Vss (80) AF18

Vss AF10

Vss AF6

Vss AF3

Vss AF1

Vss AE28

Vss AE26

Vss AE25

Vss AE23

Vss AE22

Vss (90) AE20

Vss AE19

Vss AE18

Vss AE17

Vss AE16

Vss AE15

Vss AE10

Vss AE6

Vss AD39

Vss AD37

Vss (100) AD33

Vss AD30

Vss AD3

Vss AD1

Vss AC33

Vss AC11

Vss AC7

Vss AB28

Vss AB26

Vss AB25

Vss (110) AB24

Vss AB23

Table 6-1. PCH Ballout by

Signal Name

(Sheet 21 of 25)

PCH Ball Name Ball #

Intel® C600 Series Chipset and Intel® X79 Express Chipset 279

Datasheet

PCH Ballout Definition

Vss AB22

Vss AB20

Vss AB19

Vss AB18

Vss AB17

Vss AB16

Vss AB15

Vss AB11

Vss (120) AB7

Vss AA39

Vss AA37

Vss AA33

Vss AA3

Vss AA1

Vss Y33

Vss Y10

Vss Y6

Vss W39

Vss (130) W37

Vss W10

Vss W6

Vss W3

Vss W1

Vss V33

Vss V28

Vss V26

Vss V25

Vss V23

Vss (140) V22

Vss V20

Vss V19

Vss V18

Vss V17

Vss V16

Vss V15

Vss U33

Table 6-1. PCH Ballout by

Signal Name

(Sheet 22 of 25)

PCH Ball Name Ball #

Vss U11

Vss U7

Vss (150) T39

Vss T37

Vss T11

Vss T7

Vss T3

Vss T1

Vss R33

Vss R30

Vss R28

Vss R26

Vss (160) R24

Vss R23

Vss R20

Vss R19

Vss R18

Vss R17

Vss R16

Vss R15

Vss P33

Vss P30

Vss (170) P10

Vss P6

Vss N39

Vss N37

Vss N19

Vss N10

Vss N6

Vss N3

Vss N1

Vss M33

Vss (180) M29

Vss M26

Vss M22

Vss M17

Table 6-1. PCH Ballout by

Signal Name

(Sheet 23 of 25)

PCH Ball Name Ball #

Vss M16

Vss M15

Vss L37

Vss L22

Vss L11

Vss L7

Vss (190) L3

Vss L1

Vss H39

Vss H3

Vss H1

Vss G34

Vss G33

Vss G31

Vss G30

Vss G28

Vss (200) G27

Vss G25

Vss G24

Vss G22

Vss G21

Vss G19

Vss G18

Vss G16

Vss G15

Vss G13

Vss (210) G12

Vss G10

Vss G9

Vss G7

Vss G6

Vss G4

Vss F37

Vss F3

Vss F1

Vss D39

Table 6-1. PCH Ballout by

Signal Name

(Sheet 24 of 25)

PCH Ball Name Ball #

280 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

PCH Ballout Definition

Vss (220) D1

Vss C34

Vss C29

Vss C26

Vss C24

Vss C21

Vss C19

Vss C16

Vss C13

Vss C11

Vss (230) C8

Vss C1

Vss A36

Vss A31

Vss A29

Vss A26

Vss A24

Vss A21

Vss A19

Vss (240 ) A16

Vss A13

Vss A11

Vss A8

Vss A6

Vss A4

Vss A3

Vss T9

Vss U30

Vss M23

Vss (250) W9

Vss W8

Vss N2

Vss M3

Vss B9

Vss A10

WAKE# J36

Table 6-1. PCH Ballout by

Signal Name

(Sheet 25 of 25)

PCH Ball Name Ball #

Package Information

Intel® C600 Series Chipset and Intel® X79 Express Chipset 281

Datasheet

7 Package Information

Refer to the Intel® C600 Series Chipset Thermal and Mechanical Design Guidelines or

Intel® X79 Express Chipset Thermal and Mechanical Design Guidelines document for

PCH package information.

Package Information

282 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Electrical Characteristics

Intel® C600 Series Chipset and Intel® X79 Express Chipset 283

Datasheet

8 Electrical Characteristics

This chapter contains the DC and AC characteristics for the PCH. AC timing diagrams

are included.

8.1 Thermal Specifications

Refer to the Intel® C600 Series Chipset Thermal and Mechanical Design Guidelines or

Intel® X79 Express Chipset Thermal and Mechanical Design Guidelines document for

PCH package information.

8.2 Absolute Maximum Ratings

Table 8-1 specifies absolute maximum and minimum ratings. At conditions outside

functional operation condition limits, but within absolute maximum and minimum

ratings, neither functionality nor long-term reliability can be expected. If a device is

returned to conditions within functional operation limits after having been subjected to

conditions outside these limits (but within the absolute maximum and minimum

ratings) the device may be functional, but with its lifetime degraded depending on

exposure to conditions exceeding the functional operation condition limits.

At conditions exceeding absolute max imum and minimum r atings, neither functionality

nor long-term reliability can be expected. Moreover, if a device is subjected to these

conditions for any length of time, it will either not function or its reliability will be

severely degraded when returned to conditions within the functional operating

condition limits.

Although the PCH contains protective circuitry to resist damage from Electrostatic

Discharge (ESD), precautions should always be taken to avoid high static voltages or

electric fields.

Table 8-1. PCH Absolute Maximum Ratings

Parameter Maximum Limits

Voltage on any 5 V Tolerant Pin with respect to Ground (V5REF = 5 V) -0.5 to V5REF + 0.5 V

Voltage on any 3.3 V Pin with respect to Ground -0.5 to Vcc3_3 + 0.4 V

Voltage on any 1.8 V Tolerant Pin with respect to Ground -0.5 to VccVRM + 0.5 V

Voltage on any 1.5 V Pin with respect to Ground -0.5 to VccVRM + 0.5 V

Voltage on any 1.1 V Tolerant Pin with respect to Ground -0.5 to VccIO + 0.5 V

1.1 V Supply Vo ltage with respect to VSS -0.5 to 1.3 V

1.8 V Supply Vo ltage with respect to VSS -0.5 to 1.98 V

3.3 V Supply Vo ltage with respect to VSS -0.5 to 3.7 V

5.0 V Supply Vo ltage with respect to VSS -0.5 to 5.5 V

V_PROC_IO Supply Voltage with respect to VSS -0.5 to 1.3 V

1.1 V Supply Voltage for the analog PLL with respect to VSS -0.5 to 1.3 V

1.5 V Supply Voltage for the analog PLL with respect to VSS -0.5 to 1.65 V

1.8 V Supply Voltage for the analog PLL with respect to VSS -0.5 to 1.98 V

Electrical Characteristics

284 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

8.3 PCH Power Supply Range

8.4 General DC Characteristics

ICC values in Table 8-3 and Table 8-4 specifications have been validated using post-

silicon measurements. These values are provided primarily for sizing platform VR

solutions.

Notes:

1. Vcc includes VccIO, VccCORE, and so forth, that are in the 1.1 V core well and typically supplied by a common VR source.

2. VccVRM can optionally be used in 1.8 V mode.

3. Iccmax currents define the operational maximums which must be provided by platform power delivery VR and traces

(activity on worst-case 3-sigma manufacturing units).

4. TDC currents represent steady-state consumption, by supply rail, for Full Feature TDP specifications. (Max) defines

platform thermal solution necessary to support 3-sigma manufacturing variance,

5. TDC (Typ) is representative consumption of vo lume units at Full-Feature TDP configuration.

6. Sx Idle current is representative consumption of volume units at full idle (including Intel ME)

7. G3 state shown to provide an estimate of battery life

8. Icc (RTC) data is taken with VccRTC at 3.0 V while the system in a mechanical off (G3) state at room temperature.

Table 8-2. PCH Power Supply Range

Power Supply Minimum Nominal Maximum

1.0 V 0.95 V 1.00 V 1.05 V

1.05 V 0.998 V 1.05 V 1.10 V

1.1 V 1.05 V 1.10 V 1.16 V

1.5 V 1.43 V 1.50 V 1.58 V

1.8 V 1.71 V 1.80 V 1.89 V

3.3 V 3.14 V 3.30 V 3.47 V

5 V 4.75 V 5.00 V 5.25 V

Table 8-3. Power Supply ICC Specifications by Domain (Intel® C602, C602J, C604

Chipset and Intel® X79 Express Chipset SKUs)

Voltage Rail Voltage

(V)

S0 Iccmax

Current3

(A)

TDC MAX4

(A)

TDC

Typical5 (A)

Sx Iccmax

Current3

(A)

Sx Idle

Current6

(A)

V5REF 5 1 (mA) 1 (mA) 1 (mA) - - -

V5REF_Sus 5 1 (mA) 1 (mA) 1 (mA) < 1 (mA) < 1 (mA) -

Vcc3_3 3.3 0.17 0.02 0.02 - - -

VccSus3_3 3.3 0.08 0.04 0.03 0.15 0.05 -

Vcc11.1 7.95 5.55 4.05 - - -

VccASW 1.1 1.5 1.0 0.5 0.8 0.4 -

VccDSW 3.3 0.002 < 1 (mA) < 1 (mA) < 1 (mA) < 1 (mA) -

VccSAS 1.5 0.15 0.13 0.13 - - -

VccVRM21.5 0.2 0.12 0.11 - - -

V_PROC_IO 1.0 - 1.1 1(mA) 1(mA) 1(mA) - - -

VccDMI 1.0 - 1.1 0.057 0.057 0.045 -

VccRTC - - - - - - 6 uA 7,8

Electrical Characteristics

Intel® C600 Series Chipset and Intel® X79 Express Chipset 285

Datasheet

Notes:

1. Vcc includes VccIO, VccCORE, and so forth, that are in the 1.1 V core well & typically supplied by a common VR source.

2. VccVRM can optionally be used in 1.8 V mode.

3. Iccmax currents define the operational maximums which must be provided by platform power delivery VR and traces

(peak activity on worst-case 3-sigma manufacturing units).

4. TDC currents represent steady-state consumption, by supply rail, for Full Feature TDP specifications. (Max) defines

platform thermal solution necessary to support 3-sigma manufacturing variance,

5. TDC (Typ) is representative consumption of volume units at Full-Feature TDP configuration.

6. Sx Idle current is representative consumption of volume units at full idle (includes Intel Management Engine)

7. G3 state shown to provide an estimate of battery life

8. Icc (RTC) data is taken with VccRTC at 3.0 V while the system in a mechanical off (G3) state at room temperature.

Table 8-4. Power Supply ICC Specifications by Domain (Intel® C606, C608 Chipset SKUs)

Voltage Rail Voltage

S0 Iccmax

Current3

(A)

TDC MAX4

(A)

TDC

Typical5

(A)

Sx Iccmax

Current3

(A)

Sx Idle

Current6

(A)

V5REF 5 1 (mA) 1 (mA) 1 (mA) - - -

V5REF_Sus 5 1 (mA) 1 (mA) 1 (mA) < 1 (mA) < 1 (mA) -

Vcc3_3 3.3 0.17 0.02 0.02 - - -

VccSus3_3 3.3 0.08 0.04 0.03 0.15 0.05 -

Vcc11.1 11.55 8.7 6.7 - - -

VccASW 1.1 1.5 1.0 0.46 0.8 0.4 -

VccDSW 3.3 0.002 < 1 (mA) < 1 (mA) < 1 (mA) < 1 (mA) -

VccSAS 1.5 0.28 0.26 0.26 - - -

VccVRM21.5 0.16 0.12 0.11 - - -

V_PROC_IO 1.0 - 1.1 1(mA) 1(mA) 1(mA) - - -

VccDMI 1.0 - 1.1 0.057 0.057 0.045 -

VccRTC ------

6 uA 7,8

Table 8-5. DC Characteristic Input Signal Association (Sheet 1 of 3)

Symbol Associated Signals

VIH1/VIL1

(5 V Tolerant)

PCI Signals: AD[31:0], C/BE[3:0]#, DEVSEL#, FRAME#, IRDY#, PAR, PERR#,

PLOCK#, REQ[3:0]#, SERR#, STOP#, TRDY#

Interrupt Signals: PIRQ[D:A]#, PIRQ[H:E]#

GPIO Signals: GPIO[54, 52, 50, 5:2]

GSX Signals:GSXDIN

VIMIN2-Gen3i/

VIMAX2-Gen3i SATA Signals: SATA[1:0]RX[P,N] (6.0 Gb/s internal SATA)

VIH3/VIL3

Clock Signals: REFCLK14IN

Power Management Signals: PWRBTN#, RI#, SYS_RESET#, WAKE#, SUSACK#.

GPIO Signals: GPIO[71:68, 63:61, 57, 48, 39, 38, 34, 32, 31, 30, 29, 24, 22, 17, 7,

6, 1]

Thermal/Fan Control Signals: TACH[7:0]

VIH4/VIL4

Clock Signals: CLKIN_PCI

Processor Signals:A20GATE

PCI Signals: PME#

Interrupt Signals: SERIRQ

SATA Signals: SATA[5:0]GP

SPI Signals: SPI_MISO

Strap Signals: SPKR, GNT[3:1]#, (Strap purposes only)

LPC Signals: LAD[3:0], LDRQ0#, LDRQ1#,

GPIO Signals: GPIO[73, 72, 67:64, 59, 56, 55, 53, 51, 49, 47:40, 37, 36, 35, 33, 28,

27, 26, 25, 23, 21, 20, 19, 18, 16, 15, 14, 12, 10, 9, 8, 0]

USB Signals: OC[7:0]#

Electrical Characteristics

286 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

VIH5/VIL5

SMBus Signals: SMBCLK, SMBDATA, SMBALE RT#

SAS SMBus Signals (SRV/WS SKUs Only): SASSMBCLK0, SASSMBDATA0,

SASSMBCLK1, SASSMBDATA1, SASSMBCLK2, SASSMBDATA2,

System Management Signals: SML[1:0]CLK, SML[1:0]DATA

GPIO Signals: GPIO[75, 74, 60, 58, 11 ]

VIH6/VIL6 JTAG Signals: JTAG_TDI, JTAG_TMS, JTAG_TCK

VIH7/VIL7 Processor Signals: THRMTRIP#

VIMIN8Gen1/

VIMAX8Gen1,

VIMIN8Gen2/

VIMAX8Gen2,

PCI Express* Data RX Signals: PER[p,n][8:1] (2.5 GT/s and 5.0 GT/s)

VIH9/VIL9 Real Time Clock Signals: RTCX1

VIMIN10 -Gen1i/

VIMAX10-Gen1i SATA Signals: SATA[5:0]RX[P,N] (1.5 Gb /s internal SATA)

VIMIN10 -Gen1m/

VIMAX10-Gen1m SATA Signals: SATA[5:0]RX[P,N] (1.5 Gb/s external SATA)

VIMIN10 -Gen2i/

VIMAX10-Gen2i SATA Signals: SATA[5:0]RX[P,N] (3.0 Gb /s internal SATA)

VIMIN10 -Gen2m/

VIMAX10-Gen2m SATA Signals: SATA[5:0]RX[P,N] (3.0 Gb/s external SATA)

VIH11/VIL11

Intel® High Definition Audio Signals: HDA_SDIN[3:0] (3.3V Mode)

Strap Signals: HDA_SDOUT, HDA_SYNC (Strap purposes only)

GPIO Signals: GPIO13

Note: See VIL_HDA/VIH_HDA for High Definition Audio Low Voltage Mode

VIH12 (Absolute

Maximum) / VIL12

(Absolute

Minimum) /

Vclk_in_cross(abs)

Clock Signals: CLKIN_DMI_[P,N], CLKIN_DOT96[P,N], CLKIN_SATA_[P,N]

VIH13/VIL13 Miscellaneous Signals: RTCRST#

VIH14/VIL14

Power Management Signals: PCH_PWROK, RSMRST#, DPWROK

System Management Signals: INTRUDER#

Miscellaneous Signals: INTVRMEN, SRTC RST#

VIH15/VIL15 Processor Interface: RCIN#

Power management Signals: SYS_PWROK, APWROK

VIMIN16/VIMAX16

(SRV/WS SKUs

Only) SAS Signals: SAS[7:0]RX[P,N] (1.5 Gb/s)

VIMIN17/VIMAX17

(SRV/WS SKUs

Only) SAS Signals: SAS[7:0]RX[P,N] (3.0 Gb/s)

VIMIN18/VIMAX18

(Intel® C606, C608

Chipset SKUs Only) PCI Express* Uplink RX Signals: PEG0_R[p,n][3:0]

VDI / VCM / VSE

(5V Tolerant) USB Signals: USBP[13:0][P,N] (Low-speed and Full-speed)

VHSSQ / VHSDSC /

VHSCM

(5 V Tolerant)

USB Signals: USBP[13:0][P,N] (in High-speed Mode)

Table 8-5. DC Characteristic Input Signal Association (Sheet 2 of 3)

Symbol Associated Signals

Electrical Characteristics

Intel® C600 Series Chipset and Intel® X79 Express Chipset 287

Datasheet

VIH_HDA /

VIL_HDA

Intel High Definition Audio Signals: HDA_SDIN[3:0]

Strap Signals: HDA_SDOUT, HDA_SYNC (Strap purposes only)

Note: Only applies when running in Low Voltage Mode (1.5 V)

VIH_SST/VIL_SST Thermal Reporting Signals: SST

VIH_PECI/VIL_PECI Thermal Reporting Signals: PECI

VIH_SASCLK/

VIL_SASCLK

Vcm_sas

(SRV/WS SKUs

Only)

SAS Clocks:CLKIN_SAS0[P,N], CLKIN_SAS1[P,N]

VIH_UPCLK/

VIL_UPCLK

Vcm_up

(SRV/WS SKUs

Only)

PCIe* Uplink Clock:CLKIN_SPCIE0[P,N]

Table 8-6. DC Input Characteristics (Sheet 1 of 3)

Symbol Parameter Min Max Unit Notes

VIL1 Input Low Voltage –0.5 0.3 x 3.3 V V 9

VIH1 Input High Voltage 0.5 x 3.3 V V5REF + 0.5 V 9

VIMIN2-Gen3i Minimum Input Voltage - 6.0 Gb/s SATA 240 — mVdiffp-p 5

VIMAX2-

Gen3i Maximum Input Vo ltage - 6.0 Gb/s SATA — 1000 mVdiffp-p 5

VIL3 Input Low Voltage –0.5 0.8 V

VIH3 Input High Voltage 2.0 3.3 V + 0.5 V 9

VIL4 Input Low Voltage –0.5 0.3 x 3.3 V V 9

VIH4 Input High Voltage 0.5 x 3.3 V) 3.3 V + 0.5 V 9

VIL5 Input Low Voltage –0.5 0.8 V

VIH5 Input High Voltage 2.1 3.3 V + 0.5 V 9

VIL6 Input Low Voltage -0.5 0.35 V 10

VIH6 Input High Voltage 0.75 1.1 V + 0.5 V 10

VIL7 Input Low Voltage 0 0.51 x V_PROC_IO V

VIH7 Input High Voltage 0.81 x V_PROC_IO V_PROC_IO V

VIMIN8Gen1 Minimum Input Voltage 175 — mVdiffp-p 4

VIMAX8Gen1 Maximum Input Voltage — 1200 mVdiffp-p 4

VIMIN8Gen2 Minimum Input Voltage 100 — mVdiffp-p 4

VIMAX8Gen2 Maximum Input Voltage — 1200 mVdiffp-p 4

VIL9 Input Low Voltage –0.5 0.10 V

VIH9 Input High Voltage 0.50 1.2 V

VIMIN10- Gen1i Minimum Input Voltage - 1.5 Gb/s

internal SATA 325 — mVdiffp-p 5

VIMAX10-Gen1i Maximum Input Voltage - 1.5 Gb/s

internal SATA — 600 mVdiffp-p 5

Table 8-5. DC Characteristic Input Signal Association (Sheet 3 of 3)

Symbol Associated Signals

Electrical Characteristics

288 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

VIMIN10-

Gen1m Minimum Input V oltage - 1.5 Gb/s eSATA 240 — mVdiffp-p 5

VIMAX10-

Gen1m Maximum Input Voltage - 1.5 Gb/s

eSATA — 600 mVdiffp-p 5

VIMIN10-Gen2i Minimum Input Voltage - 3.0 Gb/s

internal SATA 275 — mVdiffp-p 5

VIMAX10-Gen2i Maximum Input Voltage - 3.0 Gb/s

internal SATA — 750 mVdiffp-p 5

VIMIN10-

Gen2m Minimum Input V oltage - 3.0 Gb/s eSATA 240 — mVdiffp-p 5

VIMAX10-

Gen2m Maximum Input Voltage - 3.0 Gb/s

eSATA — 750 mVdiffp-p 5

VIL11 Input Low Voltage –0.5 0.35 x 3.3 V V 9

VIH11 Input High Voltage 0.65 x 3.3 V 3.3 + 0.5 V V 9

VIL12 (Absolute

Minimum) Input Low Voltage -0.3 V

VIH12 (Absolute

Maximum) Input High Vo ltage 1.150 V

VIL13 Input Low Voltage –0.5 0.78 V

VIH13 Input High Voltage 2.3 VccRTC + 0.5 V 6

VIL14 Input Low Voltage –0.5 0.78 V

VIH14 Input High Voltage 2.0 VccRTC + 0.5 V 6

VIL15 Input Low Voltage –0.5 0.8 V 9

VIH15 Input High Voltage 2.1 3.3 V + 0.5 V 9

VIMIN16

(SRV/WS SKUs

Only) Minimum Input Voltage - 1.5 Gb/s SAS 325 — mVdiffp-p

VIMAX16

(SRV/WS SKUs

Only) Maximum Input Vo ltage - 1.5 Gb/s SAS — 1600 mVdiffp-p

VIMIN17

(SRV/WS SKUs

Only) Minimum Input Voltage - 3.0 Gb/s SAS 275 — mVdiffp-p

VIMAX17

(SRV/WS SKUs

Only) Maximum Input Vo ltage - 3.0 Gb/s SAS — 1600 mVdiffp-p

VIMIN18

(SRV/WS SKUs

Only) Minimum Input Voltage - PCIe Uplink 15 — mVdiffp-p

VIMAX18

(SRV/WS SKUs

Only) Maximum Input Vo ltage - PCIe Uplink — 1200 mVdiffp-p

Vclk_in_cross(a

bs) Absolute Crossing Point 0.250 0.550 V 11

Vcross-delta Vcross variation 140 mV 11

VDI Differential Input Sensitivity 0.2 — V 1,3

VCM Differential Common Mode Range 0.8 2.5 V 2,3

VSE Single-Ended Receiver Threshold 0.8 2.0 V 3

VHSSQ HS Squelch Detection Threshold 100 150 mV

VHSDSC HS Disconnect Detection Threshold 525 625 mV

Table 8-6. DC Input Characteristics (Sheet 2 of 3)

Symbol Parameter Min Max Unit Notes

Electrical Characteristics

Intel® C600 Series Chipset and Intel® X79 Express Chipset 289

Datasheet

Notes:

1. VDI = | USBPx[P] – USBPx[N]

2. Includes VDI range

3. Applies to Low-Speed/Full-Speed USB

4. PCI Express* mVdiff p-p = 2*|PETp[x] - PETn[x]|

5. SATA Vdiff, RX (VIMAX10/MIN10) is measured at the SATA connector on the receiver side (generally, the motherboard

connector), where SATA mVdiff p-p = 2*|SATA[x]RXP - SATA[x]RXN|

6. VccRTC is the voltage applied to the VccRTC well of the PCH. When the system is in a G3 state, this is generally supplied

by the coin cell battery, but for S5 and greater, this is generally VccSus3_3.

7. This is an AC Characteristic that represents transient values for these signals

8. Applies to Hogh-Speed USB 2.0.

9. 3.3 V refers to VccSus3_3 for signals in the suspend well and to Vcc3_3 for signals in the core well. See Table 3-2, or

Table 3-3 for signal and power well association.

10. 1.1 V refers to VccIO or VccCore for signals in the core well and to VccASW for signals in the Active Sleep well. See

Table 3-2 or Table 3-3 for signal and power well association.

11. The Vcross and Vcro ss d elta s pec are not ap plic able to SAS and PCIE Uplink due to t he pre sen ce of AC cou plin g cap acito r.

OEM’s are encouraged to use vendor parts that meet Vcross and Vcross delta spec specified in the vendor datasheet on

their respective test boards.

12. The SAS and Uplink r eceivers are more sensit ive to th e low end edge rate value 1 V/ns. Failures of edge rate spec on the

higher side i.e failures of edge rate reported more than 4V/ns are acceptable up to 6V/ns and these high side failures up

to 6V/ns are not required to be reported.

13. The rising edge of CLKIN_SAS[0/1]_DN is equal to the falling edge of CLKIN_SAS[0/1]_DP.

VHSCM HS Data Signaling Common Mode

Voltage Range –50 500 mV

VIL_HDA Input Low Voltage 0 0.4 x Vcc_HDA V

VIH_HDA Input High Voltage 0.6 x Vcc_HDA) 1.5 V

VIL_SST Input Low Voltage -0.3 0.4 V

VIH_SST Input High Vo ltage 1.1 1.5 V

VIL_PECI Input Low Voltage -0.15 0.275 x V_PROC_IO V

VIH_PECI Input High Voltage 0.725 x V_PROC_IO V_PROC_IO + 0.15 V

VIH_SASCLK

(SRV/WS SKUs

Only)

Differential Input High Voltage - SAS

Clocks 150 — mV

VIH_SASCLK

(SRV/WS SKUs

Only)

Differential Input Low Voltage - SAS

Clocks — -150 mV

ERRefclk-

diffRrise,

ERRefclk-diff-

Fall

Differential Rising and falling edge rates 1 4 V/ns 12,13

VRB-diff Differential ringback voltage -100 100 mV

VIL_UPCLK

(SRV/WS SKUs

Only)

Differential Input High Voltage - SAS

Clocks 150 — mV

VIL_UPCLK

(SRV/WS SKUs

Only)

Differential Input Low Voltage - SAS

Clocks — -150 mV

ERRefclk-

diffRrise,

ERRefclk-diff-

Fall

Differential Rising and falling edge rates 1 4 V/ns 12,13

VRB-diff Differential ringback voltage -100 100 mV

Table 8-6. DC Input Characteristics (Sheet 3 of 3)

Symbol Parameter Min Max Unit Notes

Electrical Characteristics

290 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Table 8-7. DC Characteristic Output Signal Association (Sheet 1 of 2)

Symbol Associated Signals

VOH1/VOL1 Processor Signal: PM_SYNC, PM_SYNC2, PROCPWRGD

VOH2/VOL2

LPC Signals: LAD[3:0], LFRAME#, INIT3_3V#

Power Management Signal: LAN_PHY_PWR_CTRL

PCI Signals: AD[31:0], C/BE[3:0], DEVSEL#, FRAME#, IRDY#, PAR, PCIRST #,

GNT[3:0]#, PME#(1)

Interrupt Signals: PIRQ[D:A], PIRQ[H:E]#(1)

GPIO Signals: GPIO[73, 72, 59, 56, 55:50, 49, 47:44 43:40, 37, 36, 35, 33, 28, 27,

26, 25, 23, 21, 20, 19, 18, 16, 15, 14, 13, 12, 10, 9, 8, 5:2, 0]

SPI Signals: SPI_CS0#, SPI_CS1#, SPI_MOSI, SPI_CLK

GSX Signals: GSCLK, GSXSLOAD, GSXSRESET#, GSXDOUT

Miscellaneous Signals: SPKR

VOH3/VOL3

SMBus Signals: SMBCLK(1), SMBDATA(1)

System Management Signals: SML[1:0]CLK(1), SML[1:0]DATA(1), SML0ALERT#,

SML1ALERT#

GPIO Signals: GPIO[75, 74, 60, 58, 11]

VOH4/VOL4

Power Management Signals: SLP_S3#, SLP_S4#, SLP_S5#, SLP_A#, SLP_LAN#,

SUSCLK, DRAMPWROK, SLP_SUS#

SATA Signals: SATALED#, SCLOCK, SLOAD, SDATAOUT0, SDATAOUT1

SAS SGPIO Signals (SRV/WS SKUs Only): SAS_LED#, SAS_ CLOCK1,

SAS_LOAD1, SAS_ DATAIN1, SAS_DATAOUT1, SAS_CLOCK2, SAS_LOAD2,

SAS_DATAIN2, SAS_DATAOUT2

GPIO Signals: GPIO[71:68, 63:61, 57, 48, 39, 38, 34, 32, 31, 30, 29, 24, 22, 17, 7,

6, 1]

Interrupt Signals: SERIRQ

ADR Signal: ADR_COMPLETE

VOH5/VOL5 USB Signals: USBP[13:0][P,N] in Low-speed and Full-speed Modes

VOMIN6 -Gen3i/

VOMAX6-Gen3i SATA Signals: SATA [1:0]TX[P,N] (6.0 Gb/s Internal SATA)

VOMIN7 -Gen1i,m/

VOMAX7-Gen1i,m SATA Signals: SATA[5:0]TX[P,N] (1.5 Gb/s Internal and External SATA)

VOMIN7 -Gen2i,m/

VOMAX7-Gen2i,m SATA Signals: SATA[5:0]TX[P,N] (3.0 Gb/s Internal and External SATA)

VOMIN8-PCIeGen12/

VOMAX8-PCIeGen12 PCI Express* Data TX Signals: PET[p,n][8:1] (Gen 1 and Gen 2)

VOH9/VOL9 Power Management Signal: PLTRST#

VOMIN10/VOMAX10

(SRV/WS SKUs Only) SAS Signals: SAS[7:0]TX[P,N] (SAS-1.1)

VOMIN11/VOMAX11

(SRV/WS SKUs Only) SAS Signals: SAS[7:0]TX[P,N] (SAS-2.0)

VOMIN12/VOMAX12

(Intel® C606, C608

Chipset SKUs Only) PCI Express* Uplink TX Signals:PEG0_T[p,n][3:0]

VHSOI

VHSOH

VHSOL

VCHIRPJ

VCHIRPK

USB Signals: USBP[13:0][P:N] in High-speed Mode

VOH_HDA/VOL_HDA Intel High Definition Audio Signals: HDA_RST#, HDA_SDOUT, HDA_SYNC,

HDA_BCLK

VOL_JTAG JTAG Signals: JTAG_TDO

VOH_PCICLK/

VOL_PCICLK GPIO Signals: [67:64]

VOL_SGPIO SGPIO Signals: SCLOCK, SLOAD, SDATAOUT0, SDATAOUT1

Electrical Characteristics

Intel® C600 Series Chipset and Intel® X79 Express Chipset 291

Datasheet

Note:

1. These signals are open-drain.

VOH_PWM/

VOL_PWM Thermal Control Signals: PWM[3:0]1

VOH_SST/VOL_SST SST signal: SST

VOH_PECI/VOL_PECI PECI signal: PECI

Table 8-7. DC Characteristic Output Signal Association (Sheet 2 of 2)

Symbol Associated Signals

Table 8-8. DC Output Characteristics (Sheet 1 of 2)

Symbol Parameter Min Max Unit IOL / IOH Notes

VOL1 Output Low Voltage — 0.255 V 3 mA

VOH1 Output High Voltage V_PROC_IO - 0.3 V_PROC_IO V -3 mA

VOL2 Output Low Voltage — 0.1 x 3.3 V V 1.5 mA 7

VOH2 Output High Voltage 0.9 x 3.3 V 3.3 V -0.5 mA 7

VOL3 Output Low Voltage 0 0.4 V

VOH3 Output High Voltage 3.3 V - 0.5 — V 4 mA 1, 7

VOL4 Output Low Voltage — 0.4 V 6 mA

VOH4 Output High Voltage 3.3 V- 0.5 3.3 V V -2 mA 7

VOL5 Output Low Voltage — 0.4 V 5 mA

VOH5 Output High Voltage 3.3 V – 0.5 — V -2 mA 7

VOMIN6-Gen3i Minimum Output Voltage 200 — mVdiff

p-p 3

VOMAX6-Gen3i Maximum Output

Voltage — 900 mVdiff

p-p 3

VOMIN7-Gen1i,m Minimum Output Voltage 400 — mVdiff

p-p 3

VOMAX7-Gen1i,m Maximum Output

Voltage — 600 mVdiff

p-p 3

VOMIN7-Gen2i,m Minimum Output Voltage 400 — mVdiff

p-p 3

VOMAX7-Gen2i,m Maximum Output

Voltage — 700 mVdiff

p-p 3

VOMIN8-PCIeGen12 Output Low Voltage 800 — mVdiff

p-p 2

VOMAX8-PCIeGen12 Output High Voltage — 1200 mVdiff

p-p 2

VOL9 Output Low Voltage — 0.1 x 3.3 V V 1.5 mA 7

VOH9 Output High Voltage 0.9 x 3.3 V 3.3 V -2.0 mA 7

VOMIN10 Minimum Output Voltage 800 — mVdiff

p-p

VOMAX10 Maximum Output

Voltage — 1600 mVdiff

p-p

VOMIN11 Minimum Output Voltage 850 — mVdiff

p-p

VOMAX11 Maximum Output

Voltage — 1200 mVdiff

p-p

VOMIN12 Minimum Output Voltage 250 — mVdiff

p-p

Electrical Characteristics

292 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Notes:

1. The SERR#, PIRQ[H: A], SMBDA T A, SMBC LK, SML[1:0]CLK, SML[1:0]DA T A, SML[1:0]’ALER T# and PWM[3:0] signal has an

open-drain driver and SATALED# has an open-collector driver, and the VOH spec does not apply. This signal must have

external pull up resistor.

2. PCI Express* mVdiff p-p = 2*|PETp[x] – PETn[x]|

3. SATA Vdiff, tx (VOMIN7/VOMAX7) is measured at the SATA connector on the transmit side (generally, the motherboard

connector), where SATA mVdiff p-p = 2*|SATA[x]TXP – SATA[x]TXN|

4. Maximum Iol for PROCPWRGD is 12mA for short durations (<500 m S per 1.5 s) and 9 mA for long durati ons.

5. For INIT3_3V only, for low current devices, the following applies: VOL5 Max is 0.15 V at an IOL5 of 2 mA.

6. 3.3 V refers to VccSus3_3 for signals in the suspend well, to Vcc3_3 for signals in the core well and to VccDSW3_3 for

those signals in the D eep Sleep well. See Table 3-2 or Table 3-3 for signal and power well association.

7. 3.3 V refers to VccSus3_3 for signals in the suspend well an d to Vcc3_3 for sign als in the core well and to VccDSW3_3 for

signals in the ME well. See Table 3-2, or Table 3-3 for signal and power well association.

VOMAX12 Maximum Output

Voltage — 1200 mVdiff

p-p

VHSOI HS Idle Level –10.0 10.0 mV

VHSOH HS Data Signaling High 360 440 mV

VHSOL HS Data Signaling Low –10.0 10.0 mV

VCHIRPJ Chirp J Level 700 1100 mV

VCHIRPK Chirp K Level –900 –500 mV

VOL_HDA Output Low Voltage — 0.1 x VccSusHDA V 1.5 mA

VOH_HDA Output High Voltage 0.9 x VccSusHDA — V -0.5 mA

VOL_PWM Output Low Voltage — 0.4 V 8 mA

VOH_PWM Output High Volta ge — — 1

VOL_SGPIO Output Low Voltage — 0.4 V

VOL_PCICLK Output Low Voltage 0.4 V -1 mA

VOH_PCICLK Output High Voltage 2.4 V 1 mA

VOL_SST Output Low Voltage 0 0.3 V 0.5 mA

VOH_SST Output High Voltage 1.1 1.5 V -6 mA

VOL_PECI Output Low Voltage — 0.25 x V_PROC_IO V 0.5 mA

VOH_PECI Output High Voltage 0.75 x V_PROC_IO V_PROC_IO -6 mA

VOL_HDA Output Low Vo ltage — 0.1 x VccHDA V 1.5 mA

VOL_JTAG Output Low Voltage 0 0.1 x 1.05 V V 1.5 mA

Table 8-9. Other DC Characteristics (Sheet 1 of 2)

Symbol Parameter Min Nom Max Unit Notes

V_PROC_IO Processor I/F .95 1.0 - 1.1 1.16 V 1

V5REF PCH Core Well Reference Voltage 4.75 5 5.25 V 1

Vcc3_3 I/O Buffer Voltage 3.14 3.3 3.47 V 1

VccVRM 1.5 V Internal PLL and VRMs 1.455 1.5 1.545 V 1, 3

VccVRM 1.8 V Internal PLL and VRMs 1.746 1.8 1.854 V 1, 3

V5REF_Sus Suspend Well Reference Voltage 4.75 5 5.25 V 1

VccSus3_3 Suspend Well I/O Buffer Voltage 3.14 3.3 3.47 V 1

VccCore Internal Logic Voltage 1.05 1.1 1.16 V 1

VccIO Core Well I/O buffers 1.05 1.1 1.16 V 1

VccDMI DMI Buffer Voltage .95 1.0 - 1.1 1.16 V 1

VccSPI 3.3 V Supply for SPI Controller Logic 3.14 3.3 3.47 V 1

Table 8-8. DC Output Characteristics (Sheet 2 of 2)

Symbol Parameter Min Max Unit IOL / IOH Notes

Electrical Characteristics

Intel® C600 Series Chipset and Intel® X79 Express Chipset 293

Datasheet

Notes:

1. The I/O buffer supply voltage is measured at the PCH package pins. The tole rances shown in Table 8-9 are inclusive of all

noise from DC up to 20 MHz. In testing, the voltage rails should be measured with a bandwidth limited oscilloscope that

has a rolloff of 3 dB/decade above 20 MHz.

2. Includes Single Ended clocks REFCLK14IN, and CLKIN_PCI.

3. Includes only DC tolerance. AC tolerance will be 2% in addition to this range.

4. Includes both DC and AC tolerance. For optimal effect, Min/Max value should be within 3% of the nominal value.

VccASW 1.1 V Supply for Intel ME and Interated LAN 1.05 1.1 1.16 V 1

VccRTC (G3-S0) Battery Voltage 2 — 3.47 V 1

VccSusHDA High Definition Audio Controller Suspend

Voltage 3.14 3.3 3.47 V 1

VccSusHDA (low

voltage) High Definition Audio Controller Low Voltage

Mode Suspend Voltage 1.43 1.5 1.58 V 1

VccDFTERM 1.8V supply power supply for DF_TVS 1.71 1.8 1.89 V 1

VccDSW3_3 3.3v supply for Deep S4/S5 wells 3.14 3.3 3.47 V 1

VccRBIAS_PU

(Intel® C606, C608

Chipset SKUs Only) PCIe Uplink RBIAS Voltage 1.05 1.1 1.15 V 4

VccRBIAS_SAS0

(SRV/WS SKUs Only) SAS0 RBIAS Voltage 1.05 1.1 1.15 V 4

VccRBIAS_SAS1

(SRV/WS SKUs Only) SAS1 RBIAS Voltage 1.05 1.1 1.15 V 4

VccPLLEXPU

(Intel® C606, C608

Chipset SKUs Only) PCIe Uplink PLL Voltage 1.05 1. 1 1.15 V 4

VccPLLSAS0

(SRV/WS SKUs Only) SAS0 PLL Voltage 1.05 1.1 1.15 V 4

VccPLLSAS1

(SRV/WS SKUs Only) SAS1 PLL Voltage 1.05 1.1 1.15 V 4

ILI1 PCI_3V Hi-Z State Data Line Leakage –10 — 10 µA (0 V < VIN <

Vcc3_3)

ILI2 PCI_5V Hi-Z State Data Line Leakage –70 — 70 µA Max VIN = 2.7 V

Min VIN = 0.5 V

ILI3 Input Leakage Current – All Other –10 — 10 µA 2

CIN Input Capacitance – All Other — — TBD pF FC = 1 MHz

COUT Output Capacitance — — TBD pF FC = 1 MHz

CI/O I/O Capacitance — — 10 pF FC = 1 MHz

Typical Value

CL XTAL25_IN 3 pF

CL RTCX1 6 pF

CL RTCX2 6 pF

Table 8-9. Other DC Characteristics (Sheet 2 of 2)

Symbol Parameter Min Nom Max Unit Notes

Electrical Characteristics

294 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

8.5 AC Characteristics

Notes:

1. Specified at the measurement point into a timing and voltage compliance test load and measured over

any 250 consecutive TX UIs. (Also refer to the Transmitter compliance eye diagram)

2. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTXJITTER-MAX =

0.30 UI for the Transmitter collected over any 250 consecutive TX UIs. The TTXEYE-MEDIAN-to-MAX-JITTER

specification ensures a jitter distribution in which the median and the maximum deviation from the

median is less than half of the total TX jitter budget collected over any 250 consecutive TX UIs. It

should be noted that the median is not the same as the mean. The jitter median describes the point in

time where the number of jitter points on either side is approximately equal as opposed to the averaged

time value.

3. Specified at the measurement point and measured over any 250 consecutive UIs. The test load

documented in the PCI Express* specification 2.0 should be used as the RX device when taking

measurements (also refer to the Receiver compliance eye diagram). If the clocks to the RX and TX are

not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used

as a reference for the eye diagram.

4. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the

Transmitter and interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to--MAX-JITTER

specification ensures a jitter distribution in which the median and the maximum deviation from the

median is less than half of the total 0.6 UI jitter budget collected over any 250 consecutive TX UIs. It

should be noted that the median is not the same as the mean. The jitter median describes the point in

time where the number of jitter points on either side is approximately equal as opposed to the averaged

time value. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI

recovered from 3500 consecutive UI must be used as the reference for the eye diagram.

5. Nominal Unit Interval is 400 ps for 2.5 GT/s and 200 ps for 5 GT/s.

Note:

1. The specified UI is equivalent to a tolerance of ±300 ppm for each reference clock source.

Table 8-10. PCI Express* and DMI Interface Timings

Symbol Parameter Min Max Unit Figures Notes

Transmitter and Receiver Timings

UI Unit Interval – PCI Express*

Gen 1 (2.5 GT/s) 399.88 400.12 ps 5

UI Unit Interval – PCI Express

Gen 2 (5.0 GT/s) 199.9 200.1 ps 5

UI Unit Interval – DMI 399.88 400.12 ps 5

TTX-EYE Minimum Transmission Eye Width 0.7 — UI 8-25 1,2

TTX-RISE/

Fall (Gen1) D+/D- TX Out put Rise/Fall time -0.125 UI 1,2

TTX-RISE/

Fall (Gen2) D+/D- TX Out put Rise/Fall time -0.15 UI 1,2

TRX-EYE Minimum Receiver Eye Width 0.40 — UI 8-26 3,4

Table 8-11. PCI Express* Uplink Interface Timings (Intel® C606, C608 Chipset SKUs

Only)

Symbol Parameter Min Max Unit Figures Notes

Transmitter and Receiver Timings

UI Unit Interval 124.96 125.04 ps 1

TRX-EYE Minimum Receiver Eye Width 0.3 UI

Electrical Characteristics

Intel® C600 Series Chipset and Intel® X79 Express Chipset 295

Datasheet

Table 8-12. SAS Interface Timings (SRV/WS SKUs Only)

Sym Parameter Min Max Units Notes Figure

UI Gen I Operating Data Period 666.43 670.23 ps

UI-2 Gen II Operating Data Period (3Gb/s) 333.21 335.11 ps

UI-OOB OOB Operating Data period 665.07 668.27 ns

t120 Rise Time 0.15 0.41 UI

t121 Fall Time 0.15 0.41 UI

t122 TX differential skew — 20 ps

t123 COMRESET 310.4 329.6 ns

t124 COMWAKE transmit spacing 103.5 109.9 ns

t125 COMSAS transmit spacing 931.2 988 .8 ns

Table 8-13. Clock Timings (Sheet 1 of 2)

Sym Parameter Min Max Unit Notes Figure

REFCLK14IN

t6 Period 69.820 69.862 ns

t7 High time 29.975 38.467 ns

t8 Low time 29.975 38.467 ns

Duty Cycle 40 60 %

Rising Edge Rate 1.0 4 V/ns

Falling Edge Rate 1.0 4 V/ns

Jitter — 800 ps

SMBus/SMLink Clock (SMBCLK, SML[1:0]CLK)

fsmb Operating Frequency 10 100 KHz 5

t22 High time 4.0 50 μs18-20

t23 Low time 4.7 — μs8-20

t24 Rise time — 1000 ns 8-20

t25 Fall time — 300 ns 8-20

SMLink0 Clock (SML0CLK) (See note 7)

fsmb Operating Frequency 0 400 KHz

t22_SML High time 0.6 50 m s 2 8-20

t23_SML Low time 1.3 — ms 8-20

t24_SML Rise time — 300 ns 8-20

t25_SML Fall time — 300 ns 8-20

HDA_BCLK (Intel High Definition Audio)

fHDA Operating Frequency 24.0 MHz

Frequency Tolerance — 100 ppm

t26a C2C Jitter (refer to Clock Chip

Specification) — 300 ppm

t27a High Time (Measured at 0.75 Vcc) 18.75 22.91 ns 8-11

t28a Low Time (Measured at 0.35 Vcc) 18.75 22.91 ns 8-11

Electrical Characteristics

296 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Notes:

1. The maximum high time (t18 Max) provide a simple ensured method for devices to detect bus idle

conditions.

2. SUSCLK duty cycle can range from 30% minimum to 70% maximum.

3. Jitter is specified as cy cle to cycle measured in pico seco nds. P eriod min and max include s cycle to cy cle

jitter

4. Testing condition: 1 kohm pull up to Vcc, 1 k ohm pull down and 10 pF pull down and 1/2 inch trace See

Figure 8-28 for more detail.

5. When the PCH communicates to BMC using SMLINK signal, up to 400 kHz clock frequency can be

supported.

6. When SMLink0 is configured to run in Fast Mode using a soft strap, the operating frequency is in the

range of 300 KHz-400 KHz.

SATA Clock (CLKIN_SATA_[P:N]) from a Clock Chip

t36(ssc-on) Period 9.999 10.05 ns

t36(ssc-off) Period 9.999 10.001 ns

Slew rate 1 8 V/ns

C2C Jitter (refer to Clock Chip

Specification) 50 ps 3

DMI Clock (CLKIN_DMI_[P:N]) from a Clock Chip

tDMI(ssc-on) Period 9.999 10.05 ns

tDMI(ssc-off) Period 9.999 10.001 ns

Slew rate 1 4 V/ns

clock duty cycle 45 55 %

VRB-Diff -100 100 mV

Tstable 500 ps

PCIe* Uplink and SAS Clock (CLKIN_SPCIE0_[P:N], CLKIN_SAS[1:0]_[P:N]) from a Clock Chip

((PCIe* Uplink is Intel® C606, C608 Chipset SKUs Only and SAS Clock is SRV/WS Only))

tUplink(ssc-on) Period 9.999 10.05 ns

tUplink(ssc-off) Period 9.999 10.001 ns

tSAS(ssc-off

only) Period 9.999 10.001 ns

slew rate 1 4 V/ns 7

clock duty cycle 45 55 %

Tstable 500 ps

DOT 96 MHz (CLKIN_DOT96[P,N]) from a clock chip

t36 Period 10.066 10.768 ns

Slew rate 1 8 V/ns

C2C Jitter (refer to Clock Chip

Specification) 250 ps 3

Suspend Clock (SUSCLK)

fsusclk Operating Frequency 32 kHz 2

t39 High Time 10 — μs2

t39a Low Time 10 — μs2

SPI_CLK

Slew_Rise Output Rise Slew Rate (0.2Vcc - 0.6Vcc) 1 4 V/ns 4 8-22

Slew_Fall Output Fall Slew Rate (0.6Vcc - 0.2Vcc) 1 4 V/ns 4 8-22

Table 8-13. Clock Timings (Sheet 2 of 2)

Sym Parameter Min Max Unit Notes Figure

Electrical Characteristics

Intel® C600 Series Chipset and Intel® X79 Express Chipset 297

Datasheet

7. The SAS and Uplink receivers are more sensitive to the low end edge rate value 1 V/ns. Failures of edge

rate spec on the higher side i.e failures of edge rate reported more than 4 V/ns are acceptable up to

6 V/ns and these h igh side failures up to 6V/ns are not required to be reported.

Note:

1. Refer to n ote 3 of table 4-4 in Section 4.2.2.2 and note 2 of table 4-6 in Sect ion 4.2.3.2 of the PCI Local

Bus Specification, Revision 2.3, for measurement details.

Table 8-14. PCI Interface Timing

Sym Parameter Min Max Units Notes Figure

t40 AD[31:0] Valid Delay 2 11 ns 1 8-12

t41 AD[31:0] Setup Time to PCICLK Rising 7 — ns 8-13

t42 AD[31:0] Hold Time from PCICLK Rising 0 — ns 8-13

t43 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,

PAR, PERR#, PLOCK#, DEVSEL# Valid Delay

from PCICLK Rising 211ns 1 8-12

t44 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,

PAR, PERR#, PLOCK#, IDSEL, DEVSE L# Output

Enable Delay from PCICLK Rising 2ns 8-16

t45 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,

PERR#, PLOCK#, DEVSEL#, GNT[A:B]# Float

Delay from PCICLK Rising 228ns 8-14

t46 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,

SERR#, PERR#, DEVSEL#, Setup Time to

PCICLK Rising 7ns 8-13

t47 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,

SERR#, PERR#, DEVSEL#, REQ[A:B]# Hold

Time from PCLKIN Rising 0—ns 8-13

t48 PCIRST# Low Pulse Width 1 ms 8-15

t49 GNT[3:0]# Valid Delay from PCICLK Rising 2 12 ns

t50 REQ[3:0]# Setup Time to PCICLK Rising 12 — ns

Table 8-15. Universal Serial Bus Timing (Sheet 1 of 2)

Sym Parameter Min Max Units Notes Fig

Full-speed Source (Note 7)

t100 USBPx+, USBPx- Driver Rise Time 4 20 ns 1, 6 CL = 50

pF 8-17

t101 USBPx+, USBPx- Driver Fall Time 4 20 ns 1, 6 CL = 50

pF 8-17

t102 Source Differential Driver Jitter

- To Next Transition

- For Paired Transitions –3.5

–4 3.5

4ns

ns 2, 3 8-18

t103 Source SE0 interval of EOP 160 175 ns 4 8-19

t104 Source Jitter for Differential Transition to

SE0 Transition –2 5 ns 5

t105 Receiver Data Jitter Tolerance

- T o Nex t Transition

- For Paired Transitions –18.5

–9 18.5

9ns

ns 38-18

t106 EOP Widt h: Must accept as EOP 82 — ns 4 8-19

t107 Width of SE0 interval during differential

transition —14 ns

Low-speed Source (Note 8)

Electrical Characteristics

298 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Notes:

1. Driver output resistance under steady state drive is specified at 28 Ω at minimum and 43 Ω at

maximum.

2. Timing difference between the differential data signals.

3. Measured at crossover point of differential data signals.

4. Measured at 50% swing point of data signals.

5. Measured from last crossover point to 50% swing point of data line at leading edge of EOP.

6. Measured from 10% to 90% of the data signal.

7. Full-speed Data Rate has minimum of 11.97 Mb/s and maximum of 12.03 Mb/s.

8. Low-speed Data Rate has a minimum of 1.48 Mb/s and a maximum of 1.52 Mb/s.

Notes:

1. 20% – 80% at transmitter

2. 80% – 20% at transmitter

3. As measured from 100 mV differential crosspoints of last and first edges of burst.

4. Operating data period during Out-Of-Band burst transmissions.

t108 USBPx+, USBPx – Driver Rise Time 75 300 ns 6

CL = 200pF

CL = 600pF 8-17

t109 USBPx+, USBPx – Driver Fall Time 75 300 ns 6

CL = 200pF

CL = 600pF 8-17

t110 Source Differential Driver Jitter

To Next Transition

For Paired Transitions –25

–14 25

14 ns

ns 2, 3 8-18

t111 Source SE0 interval of EOP 1.25 1.50 µs 4 8-19

t112 Source Jitter for Differential Transition to

SE0 Transition –40 100 ns 5

t113 Receiver Data Jitter Tolerance

- To Next Transition- For Paired

Transitions –152

–200 152

200 ns

ns 38-18

t114 EOP Width: Must accept as EOP 670 — ns 4 8-19

t115 Width of SE0 interval during differential

transition — 210 ns

Table 8-15. Universal Serial Bus Timing (Sheet 2 of 2)

Sym Parameter Min Max Units Notes Fig

Full-speed Source (Note 7)

Table 8-16. SATA Interface Timings

Sym Parameter Min Max Units Notes Figure

UI Gen I Operating Data Period 666.43 670.23 ps

UI-2 Gen II Operating Data Period (3Gb/s) 333.21 335.11 ps

UI-3 Gen III Operating Data Period (6Gb/s) 166.6667 166.6083 ps

t120gen1 Rise Time 0.15 0.41 UI 1

t120gen2 Rise Time 0.2 0.41 UI 1

t120gen3 Rise Time 0.2 0.41 UI 1

t121gen1 Fall Time 0.15 0.41 UI 2

t121gen2 Fall Time 0.2 0.41 UI 2

t121gen3 Fall Time 0.2 0.48 UI 2

t122 TX differential skew — 20 ps

t123 COMRESET 310.4 329.6 ns 3

t124 COMWAKE transmit spacing 103.5 109.9 n s 3

t125 OOB Operating Data period 646.67 686.67 ns 4

Electrical Characteristics

Intel® C600 Series Chipset and Intel® X79 Express Chipset 299

Datasheet

Notes:

1. A device will timeout when any clock low exceeds this value.

2. t137 is the cumulative time a slave device is allowed to extend the clock cycles in one message from the

initial start to stop. If a slave device exceeds this time, it is expected to release both its clock and data

lines a nd rese t itself.

3. t138 is the cumulative time a master device is allowed to extend its clock cycles within each byte of a

message as defined from start-to-ack, ack-to-ack or ack-to-stop.

4. t134 has a minimum timing for I2C of 0 ns, while the minimum timing for SMBus is 300 ns.

5. Timings with the SMLFM designator apply only to SMLink0 and only when SMLink0 is operating in Fast

Mode.

Table 8-17. SMBus and SMLink Timing

Sym Parameter Min Max Units Notes Fig

t130 Bus Free Time Between Stop and Start Condition 4.7 — µs 8-20

t130SMLFM Bus Free Time Between Stop and Start Condition 1.3 — µs 5 8-20

t131 Hold Time after (rep eate d) Start Condit ion. Aft er

this period, the first clock is generated. 4.0 — µs 8-20

t131SMLFM Hold Time after (repeate d) Start Condition. After

this period, the first clock is generated. 0.6 — µs 5 8-20

t132 Repeated Start Condition Setup Time 4.7 — µs 8-20

t132SMLFM Repeated Start Condition Setup Time 0.6 — µs 5 8-20

t133 Stop Condition Setup Time 4.0 — µs 8-20

t133SMLFM Stop Condition Setup Time 0.6 — µs 5 8-20

t134 Data Hold Time 0 — ns 4 8-20

t134SMLFM Data Hold Time 0 — ns 4, 58-20

t135 Data Setup Time 250 — ns 8-20

t135SMLFM Data Setup Time 100 — ns 5 8-20

t136 Device Time Out 25 35 ms 1

t137 Cumulative Clock Low Extend Time (slave device) — 25 ms 2 8-21

t138 Cumulative Clock Low Extend Time (master

device) —10 ms 38-21

Table 8-18. Intel® High Definition Audio Timing

Sym Parameter Min Max Units Notes Fig

t143 Time duration for which HDA_SDO is valid before

HDA_BCLK edge. 7— ns 8-23

t144 Time duration for which HDA_SDO is valid after

HDA_BCLK edge. 7— ns 8-23

t145 Setup time for HDA_SDIN[3:0] at rising edge of

HDA_BCLK 15 — ns 8-23

t146 Hold time for HDA_SDIN[3:0] at rising edge of

HDA_BCLK 0— ns 8-23

Table 8-19. LPC Timing (Sheet 1 of 2)

Sym Parameter Min Max Units Notes Fig

t150 LAD[3:0] Valid Delay from PCICLK Rising 2 11 ns 8-12

t151 LAD[3:0] Output Enable Delay from PCICLK Rising 2 ns 8-16

t152 LAD[3:0] Float Delay from PCICLK Rising — 28 ns 8-14

t153 LAD[3:0] Setup Time to PCICLK Rising 7 — ns 8-13

t154 LAD[3:0] Hold Time from PCICLK Rising 0 — ns 8-13

Electrical Characteristics

300 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Notes:

1. The typical clock frequency driven by the PCH is 17.86 MHz.

2. Measurement point for low time and high time is taken at 0.5 (VccSUS3_3).

t155 LDRQ[1:0]# Setup Time to PCICLK Rising 12 — ns 8-13

t156 LDRQ[1:0]# Hold Time from PCICLK Rising 0 — ns 8-13

t157 eE# Valid Delay from PCICLK Rising 2 12 ns 8-12

Table 8-20. Miscellaneous Timings

Sym Parameter Min Max Units Notes Fig

t160 SERIRQ Setup Time to PCICLK Rising 7 — ns 8-13

t161 SERIRQ Hold Time from PCICLK Rising 0 — ns 8-13

t162 RI#, GPIO, USB Resume Pulse Width 2 — RTCCLK 8-15

t163 SPKR Valid Delay from OSC Rising — 200 ns 8-12

t164 SERR# Active to NMI Active — 200 ns

Table 8-21. SPI Timings (20 MHz)

Sym Parameter Min Max Units Notes Fig

t180a Serial Clock Frequency - 20M Hz Operation 17.06 18.73 MHz 1

t183a Tco of SPI_MOSI with respect to serial clock

falling edge at the host -5 13 ns 8-22

t184a Setup of SPI_MISO with respect to serial clock

falling edge at the host 16 — ns 8-22

t185a Hold of SPI_MISO with respect to serial clock

falling edge at the host 0—ns 8-22

t186a Setup of SPI_CS[1:0]# ass ertion with respect

to serial clock rising at the host 30 — ns 8-22

t187a Hold of SPI_CS[1:0]# deassertion with respect

to serial clock falling at the host 30 — ns 8-22

t188a SPI_CLK high time 26.37 — ns 8-22

t189a SPI_CLK low time 26.82 — ns 8-22

Table 8-19. LPC Timing (Sheet 2 of 2)

Sym Parameter Min Max Units Notes Fig

Table 8-22. SPI Timings (33 MHz) (Sheet 1 of 2)

Sym Parameter Min Max Units Notes Fig

t180b Serial Clock Frequency - 33 MHz Operation 29.83 32.8 1 MHz 1

t183b Tco of SPI_MOSI with respect to serial clock

falling edge at the host -5 5 ns 8-22

t184b Setup of SPI_MISO with respect to serial clock

falling edge at the host 8—ns 8-22

t185b Hold of SPI_MISO with respect to serial clock

falling edge at the host 0—ns 8-22

t186b Setup of SPI_CS[1:0]# assertion with respect

to serial clock rising at the host 30 — ns 8-22

Electrical Characteristics

Intel® C600 Series Chipset and Intel® X79 Express Chipset 301

Datasheet

Notes:

1. The typical clock frequency driven by the PCH is 31.25 MHz.

2. Measurement point for low time and high time is taken at 0.5 (VccSUS3_3).

Notes:

1. Typical clock frequency driven by the PCH is 50 MHz. This frequenc y is not available for ES1 samples.

2. When using 50 MHz mode ensure target flash component can meet t188c and t189c specifications.

3. Measurement point for low time and high time is taken at 0.5 (VccSUS3_3).

Notes:

1. The originator must drive a more restrictive time to allow for quantized sampling errors by a client yet

still attain the minimum time less than 500 µs. tBIT limits apply equally to tBIT-A and tBIT-M. PCH is

targeted on 1 M bps which is 1 µs bi t tim e.

2. The minimum and maximum bit times are relative to tBIT defined in the Timing Negotiation p uls e.

3. tBIT-A is the negotiated address bit time and tBIT-M is the negotiated message bit time.

t187b Hold of SPI_CS[1:0]# deassertion with respect

to serial clock falling at the host 30 — ns 8-22

t188b SPI_ CLK High time 14.88 - ns 8-22

t189b SPI_ CLK Low time 15.18 - ns 8-22

Table 8-22. SPI Timings (33 MHz) (Sheet 2 of 2)

Sym Parameter Min Max Units Notes Fig

Table 8-23. SPI Timings (50 MHz)

Sym Parameter Min Max Units Notes Fig

t180c Serial Clock Frequency - 50 MHz Operation 46.99 53.40 MHz 1 8-22

t183c Tco of SPI_MOSI with respect to serial clock

falling edge at the host -3 3 ns 8-22

t184c Setup of SPI_MISO with respect to serial clock

falling edge at the host 8-ns 8-22

t185c Hold of SPI_MISO with respect to serial clock

falling edge at the host 0-ns 8-22

t186c Setup of SPI_CS[1:0]# assertion with respect

to serial clock rising edge at the host 30 - ns 8-22

t187c Hold of SPI_CS[1:0]# assertion with respect to

serial clock rising edge at the host 30 - ns 8-22

t188c SPI_CLK High time 7.1 - ns 2, 3 8-22

t189c SPI_CLK Low time 11.17 - ns 2, 3 8-22

Table 8-24. SST Timings

Sym Parameter Min Max Units Notes Fig

tBIT Bit time (overall time evident on SST)

Bit time driven by an originator 0.495

0.495 500

250 µs

µs 1-

tBIT,jitter Bit time jitter between adjacent bits in an SST

message header or data bytes after timing has

been negotiated ——%

tBIT,drift

Change in bit time across a SST address or S ST

message bits as driven by the originator. This

limit only applies across tBIT-A bit drift and tBIT-M

drift.

——%

tH1 High level time for logic '1' 0.6 0.8 x tBIT 2

tH0 High level time for logic '0' 0.2 0.4 x tBIT

tSSTR Rise time (measured from VOL = 0.3V to

VIH,min)— 25 + 5 ns/

node

tSSTF F all time (measured from VOH = 1.1V to VIL,max)— 33 ns/

node

Electrical Characteristics

302 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Notes:

1. The originator must drive a more restrictive time to allow for quantized sampling errors by a client yet

still attain the minimum time less than 500 µs. tBIT limits apply equally to tBIT-A and tBIT-M. PCH is

targeted on 2 MHz which is 500 ns bit time.

2. The minimum and maximum bit times are relative to tBIT defined in the Timing Negotiation pulse.

3. Extended trace lengths may appear as additional nodes.

4. tBIT-A is the negotiated address bit time and tBIT-M is the negotiated message bit time.

8.6 Power Sequencing and Reset Signal Timings

Table 8-25. PECI Timings

Sym Parameter Min Max Units Notes Fig

tBIT Bit time (overall time evident on PECI)

Bit time driven by an originator 0.495

0.495 500

250 µs

µs 1

tBIT,jitter Bit time jitter between adjacent bits in an

PECI message header or data bytes after

timing has been negotiated ——%

tBIT,drift Change in bit time across a PECI address

or PECI message bits as driven by the

originator. This limit only applies across

tBIT-A bit drift and tBIT-M drift.

——%

tH1 High level time for logic '1' 0.6 0.8 x tBIT 2

tH0 High level time for logic '0' 0.2 0.4 x tBIT

tPECIR Rise time (measured from VOL to VIH,min,

Vtt(nom) -5%) —30 + (5 x

NNODES) ns 3

tPECIF Fall time (measured from VOH to VIL,max,

Vtt(nom) +5%) —30 x

NNODES ns 3

Table 8-26. Power Sequencing and Reset Signal Timings (Sheet 1 of 3)

Sym Parameter Min Max Units Notes Fig

t200 VccRTC active to RTCRST# deassertion 9 — ms 23 8-1,

8-2

t200a RTCRST# deassertion to DPWROK high 1 — ms 8-1,

8-2

t200b VccDSW3_3 active to DPWROK high 10 — ms 8-1,

8-2

t200c VccDSW3_3 active to VccSus3_3 active 0 — ms 8-1,

8-2

t201 VccSUS active to RSMRST# deassertion 10 — ms 1 8-1,

8-2

t202 DPWROK high to SLP_SUS# deassertion 95 — ms 2, 3 8-1,

8-2

t202a RSMRST# and SLP_SUS# deas sertion to

SUSCLK toggling 5—ms3, 4

8-1,

8-2

t203 SLP_S5# high to SLP_S4# high 30 us 5. 24 8-3

t204 SLP_S4# high to SLP_S3# high 30 us 6 8-3

t205 Vcc active to PCH_PWROK active 10 — ms 7, 14 8-3,

8-4

t206 PCH_PWROK deglitch time 1 ms 8 8-3,

8-4

t207 VccASW active to APWROK high 1 ms 8-3

t208 Clock chip clock outputs to PCH_PWROK high 1 ms 8-3,

8-4

Electrical Characteristics

Intel® C600 Series Chipset and Intel® X79 Express Chipset 303

Datasheet

t209 PCH_PWROK active to PROCPWRGD active 1 ms 8-3,

8-4

t210 PROCPWRGD and SYS_PWROK high to

PLTRST# deassertion 1.06 ms 8-3,

8-4

t212 APWROK high to SPI Soft-Strap Reads 500 — µs 22 8-5

t214 DMI message and all PCI Express* p orts and

DMI in L2/L3 state to PLTRST# active 270 us 8-6

t217 PLTRST# active to PROCPWRGD inactive 30 us 8-6

t218 PROCPWRGD inactive to SLP_S3# assertion 11 us 8-6

t220 SLP_S3# low to SLP_S4# low 30 us 8-6

t221 SLP_S4# low to SLP_S5# low 30 us 8-6

t222 SLP_S3# active to PCH_PWROK deasserted 0 8-6

t223 PCH_PWROK rising to DRAMPWRGD rising 0 us 8-8

t224 DRAMPWRGD falling to SLP_S4# falling -100 ns 12 8-8

t225 VccRTC active to VccDSW3_3 active 0 — ms 1, 13 8-2

t227 VccSUS active to VccASW active 0 ms 1

t229 VccASW active to Vcc active 0 ms

t230 APWROK high to PCH_PWROK high 0 ms

t231 PCH_PWROK low to Vcc falling 40 ns 14, 15,

t232 APWROK falling to VccASW falling 40 ns 16

t233 SLP_S3# assertion to VccCore rail falling 5 us 14, 15

t234 DPWROK falling to VccDSW rail falling 40 ns 8-7

t235 RSMRST# assertion to VccSUS falling 40 ns 1, 15,

16 8-7

t236 RTCRST# assertion to VccRTC falling 0 ms 8-7

t237 SLP_LAN# (or LANPHYPC) rising to Intel LAN

Phy power high and stable 20 ms

t238 DPWROK falling to any of VccDSW, VccSUS,

VccASW, or Vcc falling 40 ns 1, 14,

15, 16

t239 V5REF_Sus active to VccSus3_3 active 0 — ms 17

t240 V5REF active to Vcc3_3 active See

Note 15 —ms17

t241 VccSus supplies active to Vcc supplies active 0 — ms 1, 14

t242 HDA_RST# active low pulse width 1 — μs

t244 VccSus active to SLP_S5#, SLP_S4#,

SLP_S3#, PLTRST# and PCIRST# valid —50ns21

t246 S4 Wake Event to SLP_S4# inactive (S4

Wake) See Note Below 5

t247 S3 Wake Event to SLP_S3# inactive (S3

Wake) See Note Below 6

t251 RSMRST# deassertion to APWROK assertion 0 ms

Table 8-26. Power Sequencing and Reset Signal Timings (Sheet 2 of 3)

Sym Parameter Min Max Units Notes Fig

Electrical Characteristics

304 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Notes:

1. VccSus supplies include VccSus3_3, V5REF_Sus, VccSusHDA.

2. This timing is a nominal value counted using RTC clock. If RTC clock isn’t already stable at the rising

edge of RSMRST#, this timing could be longer than the specified value.

3. Platforms not supporting Deep S4/S5 will typically have SLP_SUS# left as no connect. Hence DPWROK

high and RSMRST# deassertion to SUSCLK toggling would be t202+t202a=100ms minimum

4. Platforms supporting Deep S4/S5 will have SLP_SUS# deassert prior to RSMRST#. Platforms not

supporting Deep S4/S5 will have RSMRST# deassert prior to SLP_SUS#.

5. Dependency on SLP_S4# and SLP_A# stretching

6. Dependency on SLP_S3# and SLP_A# stretching

7. It is required that the power rails associated with PCI/PCIe (typically the 3.3 V, 5 V, and 12 V core well

rails) hav e been valid for 99 ms prior to PCH_PWROK assertion in order to co mply with the 100 ms PCI/

PCIe 2.0 specification on PLTRST# deassertion. System designers m us t ensure the requ irement is met

on the platforms.

8. Ensure PCH_PWROK is a solid logic '1' before proceeding with the boot sequence. Note: If PCH_PWROK

drops after t206 it will be considered a power failure.

9. Not Applicable for PCH.

10. Not Applicable for PCH.

11. Requires SPI messaging to be completed.

12. The negative min timing implies that DRAMPWRGD must either fall before SLP_S4# or within 100 ns

after it.

13. The VccDSW3_3 supplies must never be active while the VccRTC supply is inactive.

14. Vcc includes VccIO, VccCORE, Vcc3_3, Vcc1_1, V5REF, V_PROC_IO, VccDMI and VccASW (if Intel® ME

only powered in S0).

15. A Power rail is considered to be inactive when the rail is at its nom inal voltage minus 5% or less.

16. Board design may meet (t231 AND t232 AND t235) OR (t238).

17. V5REF must be powered up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must power down

after Vcc3_3, or before Vcc3_3 within 0.7 V. V5REF_Sus must be powered up before VccSus3_3, or

after VccSus3_3 within 0.7 V. Also, V5REF_Sus must power down after VccSus3_3, or before VccSus3_3

within 0.7 V.

18. If RTC clock is not already stable at RSMRST# rising edge, this time may be longer.

19. RSMRST# falling edge must transition to 0.8 V or less before VccSus3_3 drops to 2.9 V

20. The 50 µs should be measured from Vih to Vil (2 V to 0.78 V).

21. This is an internal timing showing when the signals (SLP_S5#, SLP_S4#, SLP_S3#, PLTRST# and

PCIRST#) are valid after VccSus rail is Active.

22. APWROK high to SPI Soft-Start Read is an internal PCH timing. The timing cannot be measured

externally and included here for general power sequencing reference.

23. Measured from VccR T C-10% to RTCRST# reaching 55%*Vcc R TC. VccRT C is de fined as the final settlin g

voltage that the rail ramps.

24. Timing does not apply after Deep S3/S4 exit when Intel ME has configured SLP_S5# and/or SLP_S4# to

rise with SLP_A#.

t252 THRMTRIP# active to SLP_S3#, SLP_S4#,

SLP_S5# active 175 ns

t253 RSMRST# rising edge tr ansition from 20% to

80% 50 μs

t254 RSMRST# falling edge transition 50 μs 19, 20

Table 8-26. Power Sequencing and Reset Signal Timings (Sheet 3 of 3)

Sym Parameter Min Max Units Notes Fig

Electrical Characteristics

Intel® C600 Series Chipset and Intel® X79 Express Chipset 305

Datasheet

8.7 Power Management Timing Diagrams

Note: VccSus rail ramps up later in comparison to VccDSW due to assumption that SLP_SUS# is used to

control power to VccSus.

Figure 8-1. G3 w/RTC Loss to S4/S5 (With Deep S4/S5 Support) Timing Diagram

Figure 8-2. G3 w/RTC Loss to S4/S5 (Without Deep S4/S5 Support) Timing Diagram

Signal Nam eDestinationSource

SUSCLK

RSMRST#

Board PCH

Board

VccRTCBoard PCH

RTCRST#Board PCH t200

VccSusBoard PCH

t201

SLP_S5#PCH Board O nly fo r S4 a fter G 3 o r D ee pSx

VccDSW3_3Board PCH

DPWROKBoard PCH

t200b

t200c

Deep S4/S5

t202

valid

S5/S4

PCH

t200a

t202a

t225

t226

SLP_SUS#PCH Board

Signal N am eDestinationSource

SUSCLK

RSMRST#

Board PCH

PCH Board

VccRTCBoard PCH

RTCRST#Board PCH t200

VccSusBoard PCH

t202

SLP_S5#PCH Board

VccDSW3_3Board PCH

DPWROKBoard PCH

t200b

t201

valid

S5/S4

O n ly fo r S 4 a fte r G 3

t200a

t200c

t202a

t225

SLP_SUS#PCH Board

Electrical Characteristics

306 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Figure 8-3. S5 to S0 Timing Diagram

APWROK m ay com e up earlier

than PCH_P W R OK , but no later

SLP_S3#

SLP_A#

Signal NameDestSource

SLP_S4#

SLP_S5#

PCH Board

Board PCH

VccCore_CPUBoard CPU

PROCPWRGD

PCH_PWROK

DRAMPWROK

SYS_PWROKCPU VRM PCH

Board PCH

PCH CPU

APWROKBoard PCH

VccBoard PCH

ClocksClock Chip PCH stable

t209

PLTRST#

DMI

PCH CPU

PCH CPU/Board

PCH CPU

t203

t204

t205

t207

Training

STRAP_SET

CPU_RESET_DONE

Flex SKU VDM writes

CPU_RESET_DONE_ACK

t206

V_vid

SLP_LAN#PCH Board Could already be high before this sequence begins (to support WOL ),

but will never go high later than SLP _S 3# or SLP_A#

VccASW

Could already be high before this sequence begins (to support M 3),

but will never go high later than SLP_S3#

THRMTRIP#CPU PCH ignored honored

Assum es soft strap programmed to start at

PRO C PWRGD - expected setting for SNB

CPU SVIDCPU CPU VRM Serial VID

Load

PROCPWRGD

t208

t229

t230

t210

Electrical Characteristics

Intel® C600 Series Chipset and Intel® X79 Express Chipset 307

Datasheet

Figure 8-4. S3/M3 to S0 Timing Diagram

Figure 8-5. S5/Moff - S5/M3 Timing Diagram

SLP_S3#

SLP_A#

CPU SVID

SLP_S4#

SLP_S5#PCH Board

PCH Board

Board PCH

VccCore_CPU

CPU CPU VRM

Board CPU

PROCPWRGD

PCH_PWROK

DRAMPWROK

SYS_PWROKCPU VRM PCH

Board PCH

PCH CPU

APWROKBoard PCH

Vcc

Board PCH

ClocksClock C hip PCH stable

PLTRST#

DMI

PCH CPU

PCH CPU/Board

PCH CPU

t205

Training

STRAP_SET

CPU_RESET_DONE

Flex SKU VDM writes

CPU_RESET_DONEA

t206

Serial VID

Load

Note: V_PROC_IO may go to Vboot at

this time, but can also stay at 0V

(default) V_vid

PROCPWRGD

t210

SLP_LAN#PCH Board

VccASW

THRMTRIP#

CPU PCH ignored honored

Assumes soft strap programmed to start at

CPUPWRGD - expected setting for SNB

t209

t208

SLP_S3#

SLP_A#

Signal Nam eDestSource

SLP_S4#

SLP_S5#

PCH Board

Board PCH

APWROKBoard PCH t207

SLP_LAN#PCH Board C ould already be high before this sequence begins (to

support W OL), but will never go high later than SLP_A#

VccASW

SPI

SPI Flash

t212

PCH

Electrical Characteristics

308 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Figure 8-6. S0 to S5 Timing Diagram

Signal NameDestSource

THRMTRIP#CPU PCH honored

PLTRST#PCH Board

PROCPWRGDPCH Board

SLP_S3#PCH Board

PCH_PWROKBoard PCH

t218

ignored

t222

SLP_A#

SLP_S4#

SLP_S5#PCH Board

PCH Board

DRAMPWROKPCH CPU

SYS_PWROKBoard PCH

APWROKBoard PCH

t220

t221

May dro p before or after

SLP_S4/5# and DRAM PW R G D

Source of

LANPHYPC value

PCH GbE PHY Value from MA C

latc h ed in S U S we ll

Live value from

GbE MAC

On ly switc h if g oing t o MOF F

If appropriate, save MAC

PMC S R co ntex t here

SLP_LAN#PCH Board SLP_L AN# could sta y

high for M3 or WO L

DMI

PCIe Ports

PCH PCIe*

Devices norm al

operation L2/L3

DMI Message L2/L3

t214

t217

Electrical Characteristics

Intel® C600 Series Chipset and Intel® X79 Express Chipset 309

Datasheet

8.8 AC Timing Diagrams

Figure 8-7. S4/S5 to Deep S4/S5 to G3 w/ RTC Loss Timing Diagram

Figure 8-8. DRAMPWROK Timing Diagram

Signal Nam eDestinationSource

DPWROKBoard PCH

VccDSWBoard PCH

SLP_SUS#PCH Board

SUSWARN#P C H Bo a rd (E C)

SUSACK#Board (EC) PCH

RSMRST#Board PCH

VccSusBoard PCH

SLP_S3# /

SLP_S4# /

SLP_A#

PCH Board

SLP_S5#PCH Board

SLP _S5# drops here if

not already asserted

undriven

t235

RTCRST#Board PCH

VccRTCBoard PCH

G3D eep S4/S 5

t234

t236

S4/S5

Signal NameDestinationSource

SLP_S4#PCH Board

PWROKBoard PCH

t223

DRAMPWROKPCH CPU t224

Figure 8-9. Clock Cycle Time

Electrical Characteristics

310 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Figure 8-10. Transmitting Position (Data to Strobe)

Figure 8-11. Clock Timing

Figure 8-12. Valid Delay from Rising Clock Edge

CLKA/

CLKB

YA/YB

Tppos1

Tppos2

Tppos3

Tppos4

Tppos5

Tppos6

Tppos0

2.0V

0.8V

Period

High Time

Low Time

Fall Time Rise Time

Clock 1.5V

Valid Delay

Output

Electrical Characteristics

Intel® C600 Series Chipset and Intel® X79 Express Chipset 311

Datasheet

Figure 8-13. Setup and Hold Times

Figure 8-14. Float Delay

Figure 8-15. Pulse Width

Figure 8-16. Output Enable Delay

Clock

VTInput

Hold TimeSetup Time

1.5V

Input VT

Output

Float

Delay

Pulse Width

Clock

Output

Enable

Delay

1.5V

Electrical Characteristics

312 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Figure 8-17. USB Rise and Fall Times

Electrical Characteristics

Intel® C600 Series Chipset and Intel® X79 Express Chipset 313

Datasheet

Note: txx also refers to txx_SM, txxx also refers to txxxSMLFM, SMBCLK also refers to SML[1:0]CLK, and

SMBDATA also refers to SML[1:0]DATA in Figure 8-20.

Figure 8-18. USB Jitter

Figure 8-19. USB EOP Width

Figure 8-20. SMBus/SMLink Transaction

Paired

Transitions

Consecutive

Transitions

Crossover

Points

T period

Differential

Data Lines

Jitter

Differential

Data Lines

EOP

Width

Data

Crossover

Level

Tperiod

t130

SMBCLK

SMBDATA

t131

t19

t134

t20 t21

t135 t132 t18 t133

Electrical Characteristics

314 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Note: SMBCLK also refers to SML[1:0]CLK and SMBDATA also refers to SML[1:0]DATA in Figure 8-21.

Figure 8-21. SMBus/SMLink Timeout

Start Stop

t137

CLK

ack

CLK

ack

t138 t138

SMBCLK

SMBDATA

Figure 8-22. SPI Timings

SPI_CLK

SPI_MOSI

SPI_MISO

SPI_CS#

t186 t187

t184 t185

t183

t189t188

Electrical Characteristics

Intel® C600 Series Chipset and Intel® X79 Express Chipset 315

Datasheet

Figure 8-23. Intel® High Definition Audio Input and Output Timings

HDA_SDOUT

HDA_SDIN[3:0]

HDA_BIT_CLK

t143 t143

t144 t144

t145 t146

Figure 8-24. Transmitting Position (Data to Strobe)

CLKA/

CLKB

YA/YB

Tppos1

Tppos2

Tppos3

Tppos4

Tppos5

Tppos6

Tppos0

Electrical Characteristics

316 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Figure 8-25. PCI Express* Transmitter Eye

Figure 8-26. PCI Express* Receiver Eye

VRS-Diffp-p-Min>175mV

.4 U I =TRX-EYE min

VTS-Diff = 0mV

D+/D- Crossing point

Electrical Characteristics

Intel® C600 Series Chipset and Intel® X79 Express Chipset 317

Datasheet

Figure 8-27. Measurement Points for Differential Waveforms.

V min = -0.30V

V max = 1.15V

Vcro ss ma x =

550mV

Vcross min = 300 mV

Vcross delta = 140mV

V min = -0.30V

V max = 1.15V

Vcross max =

550mV

Vcross min = 300 mV

Vcross delta = 140mV

Clock#

Clock

Clock#

Vcross median

Clock

Clock#

Vcross median

Clock

Clock#

Vcross median

+75mV

Vcross median -75mV

Trise

Tfall

Clock-Clock#

Vih_min = +150mV

Vil_max = -150 mV

Positive Duty Cycle (Differential)

0.0V

Clock-Clock#

.0V

Nega tive Duty Cycle (Differential)

Clock Period (Differential )

Fall

Edge

Rate

Rise

Edge

Rate

Differential Clock – Differential Me as ur em ents

Dif ferential Cloc k – S ingle E nded Meas ur em ents

Electrical Characteristics

318 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Figure 8-28. PCH Test Load

VccSPI

Intel® C600 Series Chipset and Intel® X79 Express Chipset 319

Datasheet

9 Register and Memory Mapping

The PCH contains registers that are located in the processor’s I/O space and memory

space and sets of PCI configuration registers that are located in PCI configuration

space. This chapter describes the PCH I/O and memory maps at the register-set level.

bit descriptions are provided in the following chapters. The following notations and

definitions are used in the register/instruction description chapters.

RO Read Only . In some cases, if a register is read only , writes to this

separate registers are located at the same location where a read

accesses one of the registers and a write accesses the other

WO Write Only . In some cases, if a register is write only , reads to this

separate registers are located at the same location where a read

accesses one of the registers and a write accesses the other

R/W Read/Write. A register with this attribute can be read and

written.

R/WC Read/Write Clear. A register bit with this attribute can be read

and written. However, a write of 1 clears (sets to 0) the

corresponding bit and a write of 0 has no effect.

R/WL Read/Write Lockable. A register bit with the attribute can be

read at any time but writes may only occur if the associated lock

bit is set to unlock. If the associated lock bit is set to lock, this

R/WO Read/Write-Once. A register bit with this attribute can be

written only once after power up. After the first write, the bit

becomes read only.

R/WLO R ead/W rite, Lock-Once. A register bit with this attribute can be

written to the non-locked value multiple times, but to the locked

value only once. After the locked v alue has been written, the bit

becomes read only.

R/W/SN Read/Write register initial value loaded from NVM

Reserved The value of reserved bits must never be changed. For details

see Section 9.2.

Default When the PCH is reset, it sets its registers to predetermined

default states. It is the responsibility of the system initialization

software to determine configuration, operating parameters, and

optional system features that are applicable, and to program the

PCH registers accordingly.

Bold Register bits that are highlighted in bold text indicate that the

bit is implemented in the PCH. Register bits that are not

implemented or are hardwired will remain in plain text.

320 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

9.1 PCI Devices and Functions

The PCH incorporates a variety of PCI devices and functions, as shown in Table 9-1. The

first is the PCI-To-PCI bridge (Device 30). The second device (Device 31) contains most

of the standard PCI functions that always existed in the PCI-to-ISA bridges (South

Bridges), such as the Intel® 82371AB PIIX4. The third and fourth (Device 29 and

Device 26) are the USB and USB2 host controller devices. The fifth (Device 28) is PCI

Express* device. The sixth (Device 27) is HD Audio controller device. The seventh

(Device 25) is the Gigabit Ethernet controller device. The eighth device i(Device 22) is

the Intel® Management Engine Interface (Intel® MEI). The ninth device (Device 17) is

the Virtual Root Port.

If for some reason, the particular system platform does not want to support any one of

the Device Functions, with the exception of D30:F0 can individually be disabled. The

integrated Gigabit Ethernet controller will be disabled if no Platform LAN Connect

component is detected (See Chapter 5.4). When a function is disabled, it does not

appear at all to the software. A disabled function will not respond to any register reads

or writes, insuring that these devices appear hidden to software.

Note: In the normal platform, M will equal 0. For some server platforms, it may be desirable

to have multiple PCH's in the system which means some PCH's may reside on a bus

greater than 0.

Table 9-1. PCI Devices and Functions for all PCH SKUs

Bus:Device:Function Function Description

Bus M:Device 30:Function 0 PCI-to-PCI Bridge

Bus M:Device 31:Function 0 LPC Controller1

Bus M:Device 31:Function 2 SATA Controller #1

Bus M:Device 31:Function 3 SMBus Controller

Bus M:Device 31:Function 5 SATA Controller #22

Bus M:Device 31:Function 6 Thermal Subsystem

Bus M:Device 29:Function 0 USB EHCI Controller #13

Bus M:Device 26:Function 0 USB EHCI Controller #23

Bus M:Device 28:Function 0 PCI Express* Port 14

Bus M:Device 28:Function 1 PCI Express* Port 24

Bus M:Device 28:Function 2 PCI Express* Port 34

Bus M:Device 28:Function 3 PCI Express* Port 44

Bus M:Device 28:Function 4 PCI Express* Port 54

Bus M:Device 28:Function 5 PCI Express* Port 64

Bus M:Device 28:Function 6 PCI Express* Port 74

Bus M:Device 28:Function 7 PCI Express* Port 84

Bus M:Device 27:Function 0 Intel HD Audio Controller

Bus M:Device 25:Function 0 Gigabit Ethernet Controller

Bus M:Device 22:Function 0 Host Embedded Controller Interface #1

Bus M:Device 22:Function 1 Host Embedded Controller Interface #2

Bus M:Device 22:Function 2 IDE-R

Bus M:Device 22:Function 3 KT

Bus X:Device 0:Function 0 SCU 0

Bus X:Device 0:Function 1 IDF

Bus X:Device 0:Function 3 SMB 0 (Associate with SCU0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 321

Datasheet

Notes:

1. The PCI-to-LPC bridge contains registers that control LPC, Power Management, System Management,

GPIO, Processor Interface, RTC, Interrupts, Timers, and DMA.

2. SATA controller 2 (D31:F5) is only visible when D31:F2 CC.SCC=01h.

3. Prior to BIOS initialization of the PCH USB subsystem, the EHCI controllers will appear as Function 7.

After BIOS initialization, the EHCI controllers will be Function 0.

4. This section assumes the default PCI Exp ress* Function Number -to-Roo t Port mapping is used. Function

numbers for a given root port are assignable through the “Root Port Function Number and Hide for PCI

Express* Root Ports” registers (RCBA+0404h).

Notes:

1. X is a value greater tha n N+1 assigned by the BI OS.

2. Intel® C606, C608 Chipset SKU can be configured using soft strap to route SCU traffic to DM I link. In

such case, virtual root port (D17:F0) will be used in place of PCIe Upstream port and virtual switch port.

9.2 PCI Configuration Map

Each PCI function on the PCH has a set of PCI configuration registers. The register

address map tables for these register sets are included at the beginning of the chapter

for the particular function.

Configuration Space registers are accessed through configur ation cycles on the PCI bus

by the Host bridge using configuration mechanism #1 detailed in the PCI Local Bus

Specification.

Some of the PCI registers contain reserved bits. Software must deal correctly with

fields that are reserved. On reads, software must use appropriate masks to extr act the

defined bits and not rely on reserved bits being any particular value. On writes,

software must ensure that the values of reserved bit positions are preserved. That is,

the values of reserved bit positions must first be read, merged with the new values for

other bit positions and then written back. Note the software does not need to perform

read, merge, write operation for the configuration address register.

In addition to reserved bits with in a register, the configuration space contains reserved

locations. Software should not write to reserved PCI configuration locations in the

device-specific region (above address offset 3Fh).

Table 9-2. PCI Devices and Functions for PCH Intel® C602, C602J, C604 Chipset and

Intel® X79 Express Chipset SKUs

Bus:Device:Function Function Description

Bus M: Device 17: Function 0 PCIe Virtual Root Port

Table 9-3. Additional PCI Devices and Functions for Intel® C606, C608 Chipset SKUs

Bus:Device:Function Function Description

Bus N: Device 0: Function 0 PCIe Upstream Port

Bus N+1: Device 8: Function 0 PCIe Virtual Switch Port

Bus X:Device 0:Function 4 S MB 1(Associate with SCU1)

Table 9-4. Additional PCI Devices and Functions for Intel® C608 Chipset SKU

Bus:Device:Function Function Description

Bus X:Device 0:Function 5 SMB 2

322 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

9.3 I/O Map

The I/O map is divided into Fixed and V ariable address r anges. Fixed r anges cannot be

moved, but in some cases can be disabled. Variable ranges can be move d and can also

be disabled.

9.3.1 Fixed I/O Address Ranges

Table 9-5 shows the Fixed I/O decode ranges from the processor perspective. Note that

for each I/O range, there may be separate behavior for reads and writes. DMI (Direct

Media Interface) cycles that go to target ranges that are marked as “R eserv ed” will not

be decoded by the PCH, and will be passed to PCI unless the Subtractive Decode P olicy

bit is set (D31:F0:Offset 42h, bit 0). If a PCI master targets one of th e fix ed I/O target

ranges, it will be positively decoded by the PCH in medium speed.

Address ranges that are not listed or marked “Reserved” are not decoded by the PCH

(unless assigned to one of the variable r an ges).

Table 9-5. Fixed I/O Ranges Decoded by PCH (Sheet 1 of 2)

I/O Address Read Target Write Target Internal Unit

00h–08h DMA Controller DMA Controller DMA

09h–0Eh RESERVED D MA Controller DMA

0Fh DMA Controller DMA Controller DMA

10h–18h DMA Controller DMA Controller DMA

19h–1Eh RESERVED D MA Controller DMA

1Fh DMA Controller DMA Controller DMA

20h–21h Interrupt Controller Interrupt Controller Interrupt

24h–25h Interrupt Controller Interrupt Controller Interrupt

28h–29h Interrupt Controller Interrupt Controller Interrupt

2Ch–2Dh Interrupt Controller Interrupt Controller Interrupt

2E–2F LPC SIO LPC SIO Forwarded to LPC

30h–31h Interrupt Controller Interrupt Controller Interrupt

34h–35h Interrupt Controller Interrupt Controller Interrupt

38h–39h Interrupt Controller Interrupt Controller Interrupt

3Ch–3Dh Interrupt Controller Interrupt Controller Interrupt

40h–42h Timer/Counter Timer/Counter PIT (8254)

43h RESERVED Timer/Counter PIT

4E–4F LPC SIO LPC SIO Forwarded to LPC

50h–52h Timer/Counter Timer/Counter PIT

53h RESERVED Timer/Counter PIT

60h Microcontroller Microcontroller Forwarded to LPC

61h NMI Controller NMI Controller Processor I/F

62h Microcontroller Microcontroller Forwarded to LPC

64h Microcontroller Microcontroller Forwarded to LPC

66h Microcontroller Microcontroller Forwarded to LPC

70h RESERVED1NMI and RTC Controller RTC

71h RTC Controller RTC Controller RTC

72h RTC Controller NMI and RTC Controller RTC

Intel® C600 Series Chipset and Intel® X79 Express Chipset 323

Datasheet

Note:

1. See Section 13.7.2.

73h RTC Controller RTC Controller RTC

74h RTC Controller NMI and RTC Controller RTC

75h RTC Controller RTC Controller RTC

76h RTC Controller NMI and RTC Controller RTC

77h RTC Controller RTC Controller RTC

80h DMA Controller, LPC, PCI, or PCIe DMA Controller and LPC, PCI, or

PCIe DMA

81h–83h DMA Controller DMA Controller DMA

84h–86h DMA Controller DMA Controller and LPC, PCI, or

PCIe DMA

87h DMA Controller DMA Controller DMA

88h DMA Controller DMA Controller and LPC or PCI,

or PCIe DMA

89h–8Bh DMA Controller DMA Controller DMA

8Ch–8Eh DMA Controller DMA Controller and LPC or PCI,

or PCIe DMA

08Fh DMA Controller DMA Controller DMA

90h–91h DMA Controller DMA Controller DMA

92h Reset Generator Reset Generator Processor I/F

93h–9Fh DMA Controller DMA Controller DMA

A0h–A1h Interrupt Controller Interrupt Controller Interrupt

A4h–A5h Interrupt Controller Interrupt Controller Interrupt

A8h–A9h Interrupt Controller Interrupt Controller Interrupt

ACh–ADh Interrupt Controller Interrupt Controller Interrupt

B0h–B1h Interrupt Controller Interrupt Controller Interrupt

B2h–B3h Power Management Power Management Power Management

B4h–B5h Interrupt Controller Interrupt Controller Interrupt

B8h–B9h Interrupt Controller Interrupt Controller Interrupt

BCh–BDh Interrupt Controller Interrupt Controller Interrupt

C0h–D1h DMA Controller DMA Controller DMA

D2h–DDh RESERVED DMA Controller DMA

DEh–DFh DMA Controller DMA Controller DMA

F0h FERR# / Interrupt Controller FERR# / Interrupt Controller Processor I/F

170h–177h SATA Controller, PCI, or PCIe SATA Controller, PCI, or PCIe Forwarded to SATA

1F0h–1F7h SATA Controller, PCI, or PCIe SATA Controller, PCI, or PCIe Forwarded to SATA

200h-207h Gameport Low Gameport Low Forwarded to LPC

208h-20Fh Gameport High Gameport High Forwarded to LPC

376h SATA Controller, PCI, or PCIe SATA Controller, PCI, or PCIe Forwarded to SATA

3F6h SATA Controller, PCI, or PCIe SATA Controller, PCI, or PCIeI Forwarded to SATA

4D0h–4D1h Interrupt Controller Interrupt Controller Interrupt

CF9h Reset Generator Re s et Generator Processor I/F

Table 9-5. Fixed I/O Ranges Decoded by PCH (Sheet 2 of 2)

I/O Address Read Target Write Target Internal Unit

324 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

9.3.2 Variable I/O Decode Ranges

Table 9-6 shows the Variable I/O Decode Ranges. They are set using Base Address

Registers (BARs) or other configuration bits in the various PCI configuration spaces.

The PNP software (PCI or ACPI) can use their configuration mechanisms to set and

adjust these values.

Warning: The Variable I/O Ranges should not be set to conflict with the Fixed I/O Ranges.

Unpredictable results if the configuration software allows conflicts to occur. The PCH

does not perform any checks for conflicts.

Notes:

1. All ranges are decoded directly from DMI. The I/O cycles will not be seen on PCI, except the range

associated with PCI bridge.

2. The LAN range is typically not used, as the registers can also be accessed using a memory space.

3. There is also an alias 400h above the parallel port range that is used for ECP parallel ports.

Table 9-6. Variable I/O Decode Ranges

Range Name Mappable Size

(Bytes) Target

ACPI Anywhere in 64 KB I/O Space 64 Power Management

IDE Bus Master Anywhere in 64 KB I/O Space 1. 16 or 32

2. 16 1. SATA Host Controller #1, #2

2. IDE-R (SRV/WS SKUs Only)

Native IDE Command Anywhere in 64 KB I/O

Space181. SATA Host Controller #1, #2

2. IDE-R (SRV/WS SKUs Only)

Native IDE Control Anywhere in 64 KB I/O

Space141. SATA Host Controller #1, #2

2. IDE-R (SRV/WS SKUs Only)

SMBus Anywhere in 64 KB I/O Space 32 SMB Unit

TCO 96 Bytes above ACPI Base 32 TCO Unit

SA TA Index/Data Pair Anywhere in 64 KB I/O Space 16 SATA Host Controller #1, #2

GPIO Anywhere in 64 KB I/O Space 128 GPIO Unit

Parallel Port 3 Ranges in 64 KB I/O Space 83LPC Peripheral

Serial Port 1 8 Ranges in 64 KB I/O Space 8 LPC Peripheral

Serial Port 2 8 Ranges in 64 KB I/O Space 8 LPC Peripheral

Floppy Disk Controller 2 Ranges in 6 4 KB I/O Space 8 LPC Peripheral

LAN Anywhere in 64 KB I/O Space 322LAN Unit

LPC Generic 1 Anywhere in 64 KB I/O Space 4 to 256 LPC Peripheral

LPC Generic 2 Anywhere in 64 KB I/O Space 4 to 256 LPC Peripheral

LPC Generic 3 Anywhere in 64 KB I/O Space 4 to 256 LPC Peripheral

LPC Generic 4 Anywhere in 64 KB I/O Space 4 to 256 LPC Peripheral

I/O Trapping Ranges Anywhere in 64 KB I/O Space 1 to 256 Trap on Backbone

PCI Bridge Anywhere in 64 KB I/O Space I/O Base/

Limit PCI Bridge

PCI Express* Root Ports Anywhere in 64 KB I/O Space I/O Base/

Limit PCI Express* Root Ports 1-8

KT Anywhere in 64 KB I/O Space 8 KT

Intel® C600 Series Chipset and Intel® X79 Express Chipset 325

Datasheet

9.4 Memory Map

Table 9-7 shows (from the processor perspective) the memory ranges that the PCH

decodes. Cycles that arrive from DMI that are not directed to any of the internal

memory targets that decode directly from DMI will be driven out on PCI unless the

Subtractive Decode Policy bit is set (D31:F0:Offset 42h, bit 0).

PCI cycles generated by external PCI masters will be positively decoded unless they fall

in the PCI-to-PCI bridge memory forwarding ranges (those addresses are reserved for

PCI peer-to-peer traffic). If the cycle is not in the internal LAN controller’s r ange, it will

be forwarded up to DMI. Software must not attempt locks to the PCH’s memory-

mapped I/O ranges for EHCI and HPET. If attempted, the lock is not honored which

means potential deadlock conditions may occur.

Table 9-7. Memory Decode Ranges from Processor Perspective (Sheet 1 of 2)

Memory Range Target Dependency/Comments

0000 0000h–000D FFFFh

0010 0000h–TOM

(Top of Memory) Main Memory TOM registers in Host controller

000E 0000h–000E FFFFh LPC or SPI Bit 6 in BIOS Decode Enable register is set

000F 0000h–000F FFFFh LPC or SPI Bit 7 in BIOS Decode Enable register is set

FEC_ _000h–FEC_ _040h IO(x) APIC inside PCH _ _is controlled using APIC Range Select (ASEL) field and

APIC Enable (AEN) bit

FEC1 0000h–FEC1 7FFF PCI Express* Port 1 PCI Express* Root Port 1 I/OxAPIC Enable (PAE) set

FEC1 8000h–FEC1 FFFFh PCI Express* Port 2 PCI Express* Root Port 2 I/OxAPIC Enable (PAE) set

FEC2 0000h–FEC2 7FFFh PCI Express* Port 3 PCI Express* Root Port 3 I/OxAPIC Enable (PAE) set

FEC2 8000h–FEC2 FFFFh PCI Express* Port 4 PCI Express* Root Port 4 I/OxAPIC Enable (PAE) set

FEC3 0000h–FEC3 7FFFh PCI Express* Port 5 PCI Express* Root Port 5 I/OxAPIC Enable (PAE) set

FEC3 8000h–FEC3 FFFFh PCI Express* Port 6 PCI Express* Root Port 6 I/OxAPIC Enable (PAE) set

FEC4 0000 - FEC4 7FFF PCI Express* Port 7 PCI Express* Root Port 7I/OxAPIC Enable (PAE) set

FEC4 8000 - FEC4 FFFF PCI Express* Port 8 PCI Express* Root Port 8I/OxAPIC Enable (PAE) set

FED4 0000h–FED4 BFFFh TPM on LPC If Intel TPM is enabled, FED4_0000h – FED4_7FFFh goes to

Intel TPM. If disabled, the entire range goes to LPC.

FFC0 0000h–FFC7 FFFFh

FF80 0000h–FF87 FFFFh LPC or SPI (or PCI)2Bit 8 in BIOS Decode Enable register is set

FFC8 0000h–FFCF FFFFh

FF88 0000h–FF8F FFFFh LPC or SPI (or PCI)2Bit 9 in BIOS Decode Enable register is set

FFD0 0000h–FFD7 FFFFh

FF90 0000h–FF97 FFFFh LPC or SPI (or PCI)2Bit 10 in BIOS Decode Enable register is set

FFD8 0000h–FFDF FFFFh

FF98 0000h–FF9F FFFFh LPC or SPI (or PCI)2Bit 11 in BIOS Decode Enable register is set

FFE0 000h–FFE7 FFFFh

FFA0 0000h–FFA7 FFFFh LPC or SPI (or PCI)2Bit 12 in BIOS Decode Enable register is set

FFE8 0000h–FFEF FFFFh

FFA8 0000h–FFAF FFFFh LPC or SPI (or PCI)3Bit 13 in BIOS Decode Enable register is set

FFF0 0000h–FFF7 FFFFh

FFB0 0000h–FFB7 FFFFh LPC or SPI (or PCI)2Bit 14 in BIOS Decode Enable register is set

FFF8 0000h–FFFF FFFFh

FFB8 0000h–FFBF FFFFh LPC or SPI (or PCI)2Always enabled.

The top two, 64 KB blocks of this range can be swapped, as

described in Section 9.4.1.

FF70 0000h–FF7F FFFFh

FF30 0000h–FF3F FFFFh LPC or SPI (or PCI)2Bit 3 in BIOS Decode Enable register is set

FF60 0000h–FF6F FFFFh

FF20 0000h–FF2F FFFFh LPC or SPI (or PCI)2Bit 2 in BIOS Decode Enable register is set

326 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Notes:

1. Software must not attempt locks to memory mapped I/O ranges for USB EHCI or High Precision Event

Timers. If attempted, the lock is not honored, which means potential deadlock conditions may occur.

2. PCI is the target when the Bo ot BIOS Destination selection bits are set to 10b (Chipset Config

Registers:Offset 3401 bits 11:10). When PCI selected, the Firmware Hub Decode Enable bits have no

effect.

FF50 0000h–FF5F FFFFh

FF10 0000h–FF1F FFFFh LPC or SPI (or PCI)2Bit 1 in BIOS Decode Enable register is set

FF40 0000h–FF4F FFFFh

FF00 0000h–FF0F FFFFh LPC or SPI (or PCI)2Bit 0 in BIOS Decode Enable register is set

128 KB anywhere in 4-GB

range Integrated LAN

Controller Enable using BAR in Device 25:Function 0 (Integrated LAN

Controller MBARA)

4 KB anywhere in 4 GB range Integrated LAN

Controller Enable using BAR in Device 25:Function 0 (Integrated LAN

Controller MBARB)

1 KB anywhere in 4-GB

range USB EHCI Controller

#11Enable using standard PCI mechanism (Device 29, Function

1 KB anywhere in 4-GB

range USB EHCI Controller

#21Enable using standard PCI mechanism (Device 26, Function

FED4 0000h–FED4 FFFFh TPM on LPC None

Memory Base/Limit

anywhere in 4 GB range PCI Bridge Enable using standard PCI mechanism (Device 30: Function

Prefetchable Memory Base/

Limit anywhere in 64-bit

address range PCI Bridge Enable using standard PCI mechanism (Device 30: Function

64 KB anywhere in 4 GB

range LPC LPC Generic Memory Range. Enable using setting bit[0] of

the LPC Generic Memory Range register (D31:F0:offset

98h).

32 Bytes anywhere in 64-bit

address range SMBus Enable using standard PCI mechanism (Device 31: Function

2 KB anywhere above 64 KB

to 4 GB range SATA Host Controller

#1 AHCI memory-mappe d registers. Enable using standard PCI

mechanism (Device 31: Function 2)

Memory Base/Limit

anywhere in 4 GB range PCI Express* Root

Ports 1-8 Enable using standard PCI mechanism (Device 28: Function

0-7)

Prefetchable Memory Base/

Limit anywhere in 64-bit

address range

PCI Express* Root

Ports 1-8 Enable using standard PCI mechanism (Device 28: Function

0-7)

4 KB anywhere in 64-bit

address range Thermal Reporting Enable using standard PCI mechanism (Device 31: Function

6 TBAR/TBARH)

4 KB anywhere in 64-bit

address range Thermal Reporting Enable using standard PCI mechanism (Device 31: Function

6 TBARB/TBARBH)

16 Bytes anywhere in 64-bit

address range

Intel® Management

Engine Interface

(Intel® MEI)

#1, #2

Enable using standard PCI mechanism (Device 22: Function

1:0)

4 KB anywhere in 4 GB range KT Enable using standard PCI mechanism (Device 22: Function

16 KB anywhere in 4 GB

range Root Complex Register

Block (RCRB) Enable using setting bit[0] of the Root Complex Base

Address register (D31:F0:offset F0h).

512 B anywhere in 64-bit

addressing space Intel HD Audio Host

Controller Enable using standard PCI mechanism (Device 27, Function

FED0 X000h–FED0 X3FFh High Precision Event

Timers 1 BIOS determines the “fixed” location which is one of four, 1-

KB ranges where X (in the first column) is 0h, 1h, 2h, or 3h.

All other PCI None

Table 9-7. Memory Decode Ranges from Processor Perspective (Sheet 2 of 2)

Memory Range Target Dependency/Comments

Intel® C600 Series Chipset and Intel® X79 Express Chipset 327

Datasheet

9.4.1 Boot-Block Update Scheme

The PCH supports a “top-block sw ap” mode that has the PCH sw ap the top block in the

FWH or SPI flash (the boot block) with another location. This allows for safe update of

the Boot Block (even if a power failure occurs). When the “TOP_SWAP” Enable bit is

set, the PCH will invert A16 for cycles going to the upper two 64 KB blocks in the FWH

or appropriate address lines as selected in Boot Block Size (BIOS Boot-Block size) soft

strap for SPI.

Specifically for FHW, in this mode accesses to FFFF_0 000h-FFFF_FFFFh are directed to

FFFE_0000h-FFFE_FFFFh and vice versa. When the Top Swap Enable bit is 0, the PCH

will not invert A16.

Specifically for SPI, in this mode the “Top-Block Swap” behavior is as described below.

When the Top Swap Enable bit is 0, the PCH will not invert any address bit.

This bit is automatically set to 0 by RTCRST#, but not by PLTRST#.

The scheme is based on the concept that the top block is reserved as the “boot” block,

and the block immediately below the top block is reserved for doing boot-block

updates.

The algorithm is:

1. Software copies the top block to the block immediately below the top.

2. Software checks that the copied block is correct. This could be done by performing

a checksum calculation.

3. Software sets the TOP_SWAP bit. This will invert the appropriate address bits for

the cycles going to the FWH or SPI.

4. Software erases the top block.

5. Software writes the new top block.

6. Software checks the new top block.

7. Software clears the TOP_SWAP bit.

8. Software sets the Top_Swap Lock-Down bit.

If a power failure occurs at any point after step 3, the system will be able to boot from

the copy of the boot block that is stored in the block below the top. This is because the

TOP_SWAP bit is backed in the RTC well.

Note: The top-block swap mode may be forced by an external strapping option. When top-

block swap mode is forced in this manner, the TOP_SWAP bit cannot be cleared by

software. A re-boot with the strap removed will be required to exit a forced top-block

swap mode.

Table 9-8. SPI Mode Address Swapping

BIOS Boot-Block Size

Value Accesses to Being Directed to

000 (64 KB) FFFF_0000h - FFFF_FFFFh FFFE_0000h - FFFE_FFFFh and vice versa

001 (128 KB) FFFE_0000h - FFFF_FFFFh FFFC_0000h - FFFD_FFFFh and vice versa

010 (256 KB) FFFC_0000h - FFFF_FFFFh FFF8_0000h - FFFB_FFFFh and vice versa

011 (512 KB) FFF8_0000h - FFFF_FFFFh FFF0_0000h - FFF7_FFFFh and vice versa

100 (1 MB) FFF0_0000h - FFFF_FFFFh FFE0_0000h - FFEF_FFFFh and vice versa

101 - 111 Reserved Reserved

328 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Note: Top-block swap mode only affects accesses to the Firmware Hub space, not feature

space for FWH.

Note: The top-block swap mode has no effect on accesses below FFFE_0000h for FWH.

Chipset Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 329

Datasheet

10 Chipset Configuration Registers

This section describes all registers and base functionality that is related to chipset

configuration and not a specific interface (such as LPC, PCI, or PCI Express). It contains

the root complex register block, which describes the behavior of the upstream internal

link.

This block is mapped into memory space, using the Root Complex Base Address (RCBA)

quantities. Burst accesses are not allowed.

All chipset configuration registers are located in the core well unless otherwise

indicated.

10.1 Chipset Configuration Registers (Memory Space)

Note: Address locations that are not shown should be treated as Reserved (see Section 9.2

for details).

Table 10-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 1 of 2)

Offset Mnemonic Register Name Default Type

0050–0053h CIR0 Chipset Initialization Register 0 00000000h R/WL

0400–0403h RPC Root Port Configuration 0000000yh R/W, RO

0404–0407h RPFN Root Po rt Function Number for PCI

Express* Root Ports 76543210h R/WO,

0408–040Bh FLRSTAT Function Level Reset Pending Status

Summary 00000000h RO

1E00–1E03h TRSR Trap Status Register 00000000h R/WC, RO

1E10–1E17h TRCR Trapped Cycle Register 0000000000000000h RO

1E18–1E1Fh TWDR Trapped Write Data Register 0000000000000000h RO

1E80–1E87h IOTR0 I/O Trap Register 0 0000000000000000h R/W

1E88–1E8Fh IOTR1 I/O Trap Register 1 0000000000000000h R/W

1E90–1E97h IOTR2 I/O Trap Register 2 0000000000000000h R/W

1E98–1E9Fh IOTR3 I/O Trap Register 3 0000000000000000h R/W

2014–2017h V0CTL VC 0 Resource Control 800000FFh R/WL, RO

201A–201Bh V0STS VC 0 Resource Status 0000h RO

2020–2023h V1CTL VC 1 Resource Control 00000000h R/W, RO,

R/WL

2026–2027h V1STS VC 1 Resource Status 0000h RO

20AC–20AFh REC Root Error Command 0000h R/W

21A4–21A7h LCAP Link Capabilities 00012C42h RO, R/

21A8–21A9h LCTL Link Control 0000h R/W

21AA–21ABh LSTS Link Status 0042h RO

21B0–21B1h DLCTL2 DMI Link Control 2 0000h R/W, RO

2234–2237h DMIC DMI Control 00000000h R/W, RO

3000–3000h TCTL TCO Control 00h R/W

3100–3103h D31IP Device 31 Interrupt Pin 03243200h R/W, RO

Chipset Configuration Registers

330 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

3104–3107h D30IP Device 30 Interrupt Pin 00000000h RO

3108–310Bh D29IP Device 29 Interrupt Pin 10004321h R/W

310C–310Fh D28IP Device 28 Interrupt Pin 00214321h R/W

3110–3113h D27IP Device 27 Interrupt Pin 00000001h R/W

3114–3117h D26IP Device 26 Interrupt Pin 30000321h R/W

3118–311Bh D25IP Device 25 Interrupt Pin 00000001h R/W

311C–311Fh D24IP Device 24 Interrupt Pin 00000001h R/W

3124–3127h D22IP Device 22 Interrupt Pin 00004321h R/W

3140–3141h D31IR Device 31 Interrupt Route 3210h R/W

3144–3145h D29IR Device 29 Interrupt Route 3210h R/W

3146–3147h D28IR Device 28 Interrupt Route 3210h R/W

3148–3149h D27IR Device 27 Interrupt Route 3210h R/W

314C–314Fh D26IR Device 26 Interrupt Route 3210h R/W

3150–3153h D25IR Device 25 Interrupt Route 3210h R/W

3154–3157h D24IR Device 24 Interrupt Route 3210h R/W

315C–316Fh D22IR Device 22 Interrupt Route 3210h R/W

31FE–31FFh OIC Other Interrupt Control 0000h R/W

3310–3313h PRSTS Power and Re set Status 03000000h RO, R/WC

3318–331Bh PM_CFG Power Management Configuration 00000000h R/W

332C–332Fh DEEP_S4_POL Deep S4 Power Policies 00000000h R/W

3330–3333h DEEP_S5_POL Deep S5 Power Policies 00 000000h R/W

3400–3403h RC RTC Configuration 00000000h R/W,

R/WLO

3404–3407h HPTC High Precision Timer Configuration 00000000h R/W

3410–3413h GCS General Control and Status 000000yy0h R/W,

R/WLO

3414–3414h BUC Backed Up Control 00h R/W

3418–341Bh FD Function Disable 00000000h R/W

341C–341Fh CG Clock Gating 00000000h R/W

3420–3420h FDSW Function Disable SUS Well 00h R/W

3428–342Bh FD2 Function Disable 2 00000000h R/W

3450–3453h GSXBAR GPIO Serial Expander Base Address 00000000h R/W, RO

3454–3457h GSXCTRL GPIO Serial Expander Control Register 0000000h R/W, RO

3590–3593h MISCCTL Miscellaneous Control Register 00000000h R/W

3598–3599h USBIRE USB Initialization Register E 0000h R/W

35A4–35A7h USBOCM2 USB Overcurrent MAP Register 2 00000000h R/WO

35B0–35B3h RMHWKCTL USB Remap Control 00000000h R/WO

Table 10-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 2 of 2)

Offset Mnemonic Register Name Default Type

Chipset Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 331

Datasheet

10.1.1 CIR0—Chipset Initialization Register 0

Offset Address: 0050–0053h Attribute: R/WL

Default Value: 00000000h Size: 32–bit

10.1.2 RPC—Root Port Configuration Register

Offset Address: 0400-0403h Attribute: R/W , RO

Default Value: 0000000yh (y = 00xxb) Size: 32-bit

Bit Description

31 TC Lock-Down (TCLOCKDN)— R/WL. When set to 1, certain DMI c onfiguration registers are

locked down by this and cannot be written. Once set to 1, this bit can only be cleared by a

PLTRST#.

30:0 CIR0 Field 0— R/WL. BIOS must set this field. Bits lo cked by TCLOCKDN.

Bit Description

31:12 Reserved

GbE Over PCIe Root Port Enable (GBEPCIERPEN) — R/W.

0 = GbE MAC/PHY communication is not enabled over PCI Express.

1 = The PCI Express* port selected by the GBEPCIEPORTSEL register will be used for GbE MAC/

PHY over PCI Express* communication

The default value for this register is set by the GBE_PCIE_EN soft strap.

Note: GbE and PCIe will use the output of this register and not the soft strap.

10:8

GbE Over PCIe Root Port Select (GBEPCIERPSEL) — R/W.

If the GBEPCIERPEN is a ‘1’, then this register determines which port is used for GbE MAC/PHY

communication over PCI Express. This register is set by soft strap and is writable to support

separate PHY on motherboard and docking station.

111 = Port 8 (Lane 7)

110 = Port 7 (Lane 6)

101 = Port 6 (Lane 5)

100 = Port 5 (Lane 4)

011 = Port 4 (Lane 3)

010 = Port 3 (Lane 2)

001 = Port 2 (Lane 1)

000 = Port 1 (Lane 0)

The default value for this register is set by the GBE_PCIEPORTSEL[2:0] soft stra p.

Note: GbE and PCIe will use the output of this register and not the soft strap.

7:4 Reserved

3:2

Port Configuration2 (PC2) — RO. This controls how the PCI bridges are organized in various

modes of operation for Ports 5-8. For the following mappings, if a port is not shown, it is

considered a x1 port with no connection.

This bit is set by the PCIEPCS2[1:0] soft strap.

11 = 1 x4, Port 5(x4)

10 = 2x2, Port 5 (x2) Port 7 (x7)

01 = 1x2 and 2x1s, Port 5 (x2), Port 7(x1) and Port 8(x1)

00 = 4 x1s, Port 5(x1), Port 6(x1), Port 7(x1) and Port 8(x1)

1:0

Port Configuration (PC) — RO. This controls how the PCI bridges are organized in various

modes of operation for Ports 1-4. For the following mappings, if a port is not shown, it is

considered a x1 port with no connection.

These bits are set by the PCIEPCS1[1:0] soft strap.

11 = 1 x4, Port 1 (x4)

10 = 2x2, Port 1 (x2, Port 3 (x2)

01 = 1x2 and 2x1s, Port 1 (x2), Port 3 (x1) and Port 4 (x1)

00 = 4 x1s, Port 1 (x1), Port 2 (x1), Port 3 (x1) and Port 4 (x1)

Chipset Configuration Registers

332 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

10.1.3 RPFN—Root Port Function Number and Hide for PCI

Express* Root Ports

Offset Address: 0404-0407h Attribute: R/WO, RO

Default Value: 76543210h Size: 32-bit

For the PCI Express* root ports, the assignment of a function number to a root port is

not fixed. BIOS may re-assign the function numbers on a port by port basis. This

capability will allow BIOS to disable/hide any root port and still have functions 0

through N-1 where N is the total number of enabled root ports.

Port numbers will remain fixed to a physical root port.

The existing root port Function Disable registers operate on physical ports (not

functions).

Port Configuration (1x4, 4x1, and so forth) is not affected by the logical function

number assignment and is associated with physical ports.

Bit Description

31 Root Port 8 Config Hide (RP8CH) — R/W. This bit is used to hide the root port and any

devices behind it from being discovered by the OS. When set to ‘1’ the root port will not claim

any downstream configuration transactions.

30:28 Root Port 8 Function Number (RP8FN) — R/WO. These bits set the function number for PCI

Express* R oot P ort 8. This root port function number must be a unique v alue from the other root

port function numbers

27 Root Port 7 Config Hide (RP7CH) — R/W. This bit is used to hide the root port and any

devices behind it from being discovered by the OS. When set to ‘1’ the root port will not claim

any downstream configuration transactions.

26:24 Root Port 7 Function Number (RP7FN) — R/WO. These bits set the function number for PCI

Express* R oot P ort 7. This root port function number must be a unique v alue from the other root

port function numbers

23 Root Port 6 Config Hide (RP6CH) — R/W. This bit is used to hide the root port and any

devices behind it from being discovered by the OS. When set to ‘1’ the root port will not claim

any downstream configuration transactions.

22:20 Root Port 6 Function Number (RP6FN) — R/WO. These bits set the function number for PCI

Express* R oot P ort 6. This root port function number must be a unique v alue from the other root

port function numbers

19 Root Port 5 Config Hide (RP5CH) — R/W. This bit is used to hide the root port and any

devices behind it from being discovered by the OS. When set to ‘1’ the root port will not claim

any downstream configuration transactions.

18:16 Root Port 5 Function Number (RP5FN) — R/WO. These bits set the function number for PCI

Express* R oot P ort 5. This root port function number must be a unique v alue from the other root

port function numbers

15 Root Port 4 Config Hide (RP4CH) — R/W. This bit is used to hide the root port and any

devices behind it from being discovered by the OS. When set to ‘1’ the root port will not claim

any downstream configuration transactions.

14:12 Root Port 4 Function Number (RP4FN) — R/WO. These bits set the function number for PCI

Express* R oot P ort 4. This root port function number must be a uniq ue v alue from the other root

port function numbers

11 Root Port 3 Config Hide (RP3CH) — R/W. This bit is used to hide the root port and any

devices behind it from being discovered by the OS. When set to ‘1’ the root port will not claim

any downstream configuration transactions.

10:8 Root Port 3 Function Number (RP3FN) — R/WO. These bits set the function number for PCI

Express* R oot P ort 3. This root port function number must be a uniq ue v alue from the other root

port function numbers

7Root Port 2 Config Hide (RP2CH) — R/W. This bit is used to hide the root port and any

devices behind it from being discovered by the OS. When set to ‘1’ the root port will not claim

any downstream configuration transactions.

Chipset Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 333

Datasheet

10.1.4 FLRSTAT—FLR Pending Status Register

Offset Address: 0408–040Bh A ttribute: RO

Default Value: 00000000h Size: 32-bit

6:4 Root Port 2 Function Number (RP2FN) — R/WO. These bits set the function number for PCI

Express* R oot P ort 2. This root por t function number must be a unique v alue from the oth er root

port function numbers

3Root Port 1 Config Hide (RP1CH) — R/W. This bit is used to hide the root port and any

devices behind it from being discovered by the OS. When set to ‘1’ the root port will not claim

any downstream configuration transactions.

2:0 Root Port 1 Function Number (RP1FN) — R/WO. These bits set the function number for PCI

Express* R oot P ort 1. This root por t function number must be a unique v alue from the oth er root

port function numbers

Bit Description

31:24 Reserved.

23 FLR Pending Status for D29:F0, EHCI #1 — R0.

0 = Function Level Re set is not pending.

1 = Function Level Reset is pending.

22:16 Reserved

15 FLR Pending Status for D26:F0, EHCI#2 — R0.

0 = Function Level Re set is not pending.

1 = Function Level Reset is pending.

14:0 Reserved

Chipset Configuration Registers

334 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

10.1.5 TRSR—Trap Status Register

Offset Address: 1E00–1E03h Attribute: R/WC, RO

Default Value: 00000000h Size: 32-bit

10.1.6 TRCR—Trapped Cycle Register

Offset Address: 1E10–1E17h Attribute: RO

Default Value: 0000000000000000h Size: 64-bit

This register saves information about th e I/O Cycle that was tr apped and generated the

SMI# for software to read.

10.1.7 TWDR—Trapped Write Data Register

Offset Address: 1E18–1E1Fh Attribute: RO

Default Value: 0000000000000000h Size: 64-bit

This register saves the data from I/O write cycles that are trapped for software to read.

Bit Description

31:4 Reserved

3:0

Cycle Trap SMI# Status (CTSS) — R/WC. These bits are set by hardware when the

corresponding Cycle Trap register is ena bled and a matching cycle is received (and trapped).

These bits are OR’ed together to create a single status bit in the Power Management register

space.

Note that the SMI# and trapping must be enabled in order to set these bits.

These bit s are set before the comp letion is gen era ted for the trapped cycle, thereby ensuring that

the processor can enter the SMI# handler when the instruction completes. Each status bit is

cleared by writing a 1 to the corresponding bit location in this register.

Bit Description

63:25 Reserved

Read/Write# (RWI) — RO.

Trapped cycle was a write cycle.

Trapped cycle was a read cycle.

23:20 Reserved

19:16 Active-high Byte Enables (AHBE) — RO. This is the DWord-aligned byte enables associated

with the trapped cycle. A 1 in any bit location indicates that the corresponding byte is enabled in

the cycle.

15:2 Trapped I/O Address (TIOA) — RO. This is the DWord-aligned address of the trapped cycle.

1:0 Reserved

Bit Description

63:32 Reserved

31:0 Trapped I/O Data (TIOD) — RO. D W ord of I/O write data. This fiel d is undefined after tr apping

a read cycle.

Chipset Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 335

Datasheet

10.1.8 IOTRn—I/O Trap Register (0-3)

Offset Address: 1E80–1E87h Register 0 Attribute: R/W

1E88–1E8Fh Register 1

1E90–1E97h Register 2

1E98–1E9Fh Register 3

Default Value: 0000000000000000h Size: 6 4-bit

These registers are used to specify the set of I/O cycles to be trapped and to enable

this functionality.

Bit Description

63:50 Reserved

Read/Write Mask (RWM) — R/W.

The cycle must match the type specified in bit 48.

Trapping logic will operate on both read and write cycles.

Read/Write# (RWIO) — R/W.

0 = Write

1 = Read

Note: The value in this field does not matter if bit 49 is set.

47:40 Reserved

39:36 Byte Enable Mask (BEM) — R/W. A 1 in any bit position indicates that any value in the

corresponding byte enable bit in a received cycle will be treated as a match. The corresponding

bit in the Byte Enables field, below, is ignored.

35:32 Byte Enables (TBE) — R/W. Active-high DWord-aligned byte enables.

31:24 Reserved

23:18

Address[7:2] Mask (ADMA) — R/W. A 1 in any bit position indicates that any value in the

corresponding address bit in a received cycle will be tr eated as a match. The corresponding bit in

the Address field, below, is ignored. The mask is only provided for the lower 6 bits of the DWord

address, allowing for traps on address ranges up to 256 bytes in size.

17:16 Reserved

15:2 I/O Address[15:2] (IOAD) — R/W. DWord-aligned address

1Reserved

Trap and SMI# Enable (TRSE) — R/W.

0 = Trapping and SM I# logic disabled.

1 = The trapping logic specified in this register is enabled.

Chipset Configuration Registers

336 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

10.1.9 V0CTL—Virtual Channel 0 Resource Control Register

Offset Address: 2014–2017h Attribute: R/WL, RO

Default Value: 80000011h Size: 32-bit

10.1.10 V0STS—Virtual Channel 0 Resource Status Register

Offset Address: 201A–201Bh Attribute: RO

Default Value: 0000h Size: 16-bit

10.1.11 V1CTL—Virtual Channel 1 Resource Control Register

Offset Address: 2020–2023h Attribute: R/W, RO, R/WL

Default Value: 00000000h Size: 32-bit

Bit Description

31 Virtual Channel Enable (EN) — RO. Always set to 1. VC0 is always enabled and cannot be

disabled.

30:27 Reserved

26:24 Virtual Channel Identifier (ID) — RO. Indicates the ID to use for this virtual channel.

23:16 Reserved

15:10 Extended TC/VC Map (ETVM): R/WL. Defines the upper 8-bits of the VC0 16-bit TC/VC

mapping registers. These registers use the PCI Express* reserved TC[3] traffic class bit. These

bits are locked if the TCLOCKDN bit (RCBA+0050h:bit 31) is set.

9:7 Reserved

6:1 Transaction Class / Virtual Channel Map (TVM) — R/WL. Indicates which tr ansaction classes

are mapped to this virtual channel. When a bit is set, this transaction class is mapped to the

virtual channel.hese bits are locked if the TCLOCKDN bit (RCBA+0050h:bit 31) is set.

0 Reserved

Bit Description

15:2 Reserved

1VC Negotiation Pending (NP) — RO. When set, indicates the virtual channel is still being

negotiated with ingress ports.

0 Reserved

Bit Description

31 Virtual Channel Enable (EN) — R/W. Enables the VC when set . Disables the VC wh en cleared.

30:28 Reserved

27:24 Virtual Channel Identifier (ID) — R/W. Indicates the ID to use for this virtual channel.

23:16 Reserved

15:10 Extended TC/VC Map (ETVM): R/WL. Defines the upper 8-bits of the VC0 16-bit TC/VC

mapping registers. These registers use the PCI Express* reserved TC[3] traffic class bit. These

bits are locked if the TCLOCKDN bit (RCBA+0050h:bit 31) is set.

9:8 Reserved

7:1 Transaction Class / Virtual Channel Map (TVM) — R/WL. Indicates which transaction

classes are mapped to this virtual c hannel. When a bit is set, thi s tr ansac tion clas s is mapped to

the virtual channel. These bits are locked if the TCLOCKDN bit (RCBA+0050h:bit 31) is set.

0 Reserved

Chipset Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 337

Datasheet

10.1.12 V1STS—Virtual Channel 1 Resource Status Register

Offset Address: 2026–2027h Attribute: RO

Default Value: 0000h Size: 16-bit

10.1.13 REC—Root Error Command Register

Offset Address: 20AC–20AFh Attribute: R/W

Default Value: 0000h Size: 32-bit

10.1.14 LCAP—Link Capabilities Register

Offset Address: 21A4-21A7h Attribute: R/WO, RO

Default Value: 00012C42h S i ze: 32-bit

Bit Description

15:2 Reserved

1VC Negotiation Pending (NP) — RO. When set, indicates the virtual channel is still being

negotiated with ingress ports.

0Reserved

Bit Description

Drop Poisoned Downstream Packets (DPDP) — R/W. Determines how downstream packets

on DMI are handled that are received with the EP field set, indicating poisoned data:

0 = Packets are forwarded downstream without forcing the UT field set.

1 = This packe t and all sub seque nt pac k e ts wit h data re ceived on DMI for any VC will have their

Unsupported Transaction (UT) field set causing them to master Abort downstream. Packets

without data such as memory, IO and config read requests are allowed to proceed.

30:0 Reserved

Bit Description

31:18 Reserved

17:15

L1 Exit Latency (EL1) — R/WO.

000b – Less than 1 µs

001b – 1 µs to less than 2 µs

010b – 2 µs to less than 4 µs

011b – 4 µs to less than 8 µs

100b – 8 µs to less than 16 µs

101b – 16 µs to less than 32 µs

110b – 32 µs to 64 µs

111b – More than 64 µs

14:12 L0s Exit Latency (EL0) — R/W. This field indicates that exit latency is 128 ns t o less than 256

ns.

11:10

Active State Link PM Support (APMS) — R/W. Indicates the level of ASPM support on DMI.

00 = Disabled

01 = L0s entry supported

10 = Reserved

11 = L0s and L1 entry supported

9:4 Maximum Link Width (MLW) — RO. Indicates the maximum link width is 4 ports.

3:0 Supported Link Speed (MLS) — RO.

Indicates the supported links speeds is 5.0 GT/s.

Chipset Configuration Registers

338 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

10.1.15 LCTL—Link Control Register

Offset Address: 21A8–21A9h Attribute: R/W

Default Value: 0000h Size: 16-bit

10.1.16 LLSTS—Link Status Register

Offset Address: 21AA–21ABh Attribute: RO

Default Value: 0042h Size: 16-bit

10.1.17 DLCTL2—DMI Link Control 2 Register

Offset Address: 21B0–21B1h Attribute: R/W, RO

Default Value: 0001h Size: 16-bit

10.1.18 DMIC—DMI Control Register

Offset Address: 2234–2237h Attribute: R/W

Default Value: 00000000h Size: 32-bit

Bit Description

15:8 Reserved

7Extended Synch (ES) — R/W. When set, forces extended transmission of FTS ordered sets

when exiting L0s prior to enter ing L0 and extra TS1 sequences at exit from L1 prior to entering

L0.

6:2 Reserved

1:0

Active State Link PM Control (ASPM) — R/W. Indicates whether DMI should enter L0s, L1, or

both.

00 = Disabled

01 = L0s entry enabled

10 = L1 entry enabled

11 = L0s and L1 entry enabled

Bit Description

15:10 Reserved

9:4 Negotiated Link Width (NLW) — RO. Negotiated link width is x4 (000100b).

3:0

Current Link Speed (LS) — RO.

0001b = 2.5 Gb/s

0010b = 5.0 Gb/s

Bit Description

31:4 Reserved

3:0 DLCTL2 Field 1 — R/W. BIOS must set these bits.

Bit Description

31:2 Reserved

1:0 DMI Clock Gate Enable (DMICGEN) — R/W. BIOS must program this field to 11b.

Chipset Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 339

Datasheet

10.1.19 TCTL—TCO Configuration Register

Offset Address: 3000–3000h Attribute: R/W

Default Value: 00h Size: 8-bit

10.1.20 D31IP—Device 31 Interrupt Pin Register

Offset Address: 3100–3103h Attribute: R/W, RO

Default Value: 03243200h Size: 32-bit

Bit Description

7TCO IRQ Enable (IE) — R/W.

0 = TCO IRQ is disabled.

1 = TCO IRQ is enabled, as selected by th e TCO_IRQ_SEL field.

6:3 Reserved

2:0

TCO IRQ Select (IS) — R/W. Specifies on which IRQ the TCO will internally appear. If not using

the APIC, the TCO interrupt must be routed to IRQ9-11, and that interrupt is not sharable with

the SERIRQ stream, but is shareable with other PCI interrupts. If using the APIC, the TCO

interrupt can also be mapped to IRQ20-23, and can be shared with other interrupt.

000 = IRQ 9

001 = IRQ 10

010 = IRQ 11

011 = Reserved

100 = IRQ 20 (only if APIC enabled)

101 = IRQ 21 (only if APIC enabled)

110 = IRQ 22 (only if APIC enabled)

111 = IRQ 23 (only if APIC enabled)

When setting the these bits, the IE bit should be cleared to prevent glitching.

When the interrupt is mapped to APIC interrupts 9, 10 or 11, the APIC should be programmed for

active-high reception. When the interrupt is mapped to APIC interrupts 20 through 23, the APIC

should be programmed for active-low reception.

Bit Description

31:28 Reserved

27:24

Thermal Sensor Pin (TSIP) — R/W. Indicates which pin the Thermal Sensor controller drives

as its interrupt

0h = No interrupt

1h = INTA#

2h = INTB# (Default)

3h = INTC#

4h = INTD#

5h–Fh = Reserved

23:20

SATA Pin 2 (SIP2) — R/W. Indicates which pin the SATA controller 2 drives as its interrupt.

0h = No interrupt

1h = INTA#

2h = INTB# (Default)

3h = INTC#

4h = INTD#

5h–Fh = Reserved

19:16 Reserved

15:12

SMBus Pin (SMIP) — R/W. Indicates which pin the SMBus controller drives as its interrupt.

0h = No interrupt

1h = INTA#

2h = INTB# (Default)

3h = INTC#

4h = INTD#

5h–Fh = Reserved

Chipset Configuration Registers

340 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

10.1.21 D30IP—Device 30 Interrupt Pin Register

Offset Address: 3104–3107h Attribute: RO

Default Value: 00000000h Size: 32-bit

10.1.22 D29IP—Device 29 Interrupt Pin Register

Offset Address: 3108–310Bh Attribute: R/W

Default Value: 10004321h Size: 32-bit

10.1.23 D28IP—Device 28 Interrupt Pin Register

Offset Address: 310C–310Fh Attribute: R/W

Default Value: 00214321h Size: 32-bit

11:8

SATA Pin (SIP) — R/W. Indicates which pin the SATA controller drives as its interrupt.

0h = No interrupt

1h = INTA#

2h = INTB# (Default)

3h = INTC#

4h = INTD#

5h–Fh = Reserved

7:4 Reserved

3:0 LPC Bridge Pin (LIP) — RO. Currently, the LPC bridge does not generate an inter rupt, so th is field

is read-only and 0.

Bit Description

31:4 Reserved

3:0 PCI Bridge Pin (PIP) — RO. Currently, the PCI bridge does not generate an interrupt, so this field

is read-only and 0.

Bit Description

31:4 Reserved

3:0

EHCI #1 Pin (E1P) — R/W. Indicates which pin the EHCI controller #1 drives as its interrupt, if

controller exists.

0h = No interrupt

1h = INTA# (Default)

2h = INTB#

3h = INTC#

4h = INTD#

5h-7h = Reserved

Note: EHCI Controller #1 is mapped to Device 29 Function 0.

Bit Description

31:28

PCI Express* #8 Pin (P8IP) — R/W. Indicates which p in the PCI Expres s* port #8 driv es as its

interrupt.

0h = No interrupt

1h = INTA#

2h = INTB# (Default)

3h = INTC#

4h = INTD#

5h-7h = Reserved

Chipset Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 341

Datasheet

27:24

PCI Express* #7 Pin (P7IP) — R/W. Indicates which pin the PCI Express* por t #7 drives as its

interrupt.

0h = No interrupt

1h = INTA# (Default)

2h = INTB#

3h = INTC#

4h = INTD#

5h-7h = Reserved

23:20

PCI Express* #6 Pin (P6IP) — R/W. Indicates which pin the PCI Express* por t #6 drives as its

interrupt.

0h = No interrupt

1h = INTA#

2h = INTB# (Default)

3h = INTC#

4h = INTD#

5h-7h = Reserved

19:16

PCI Express* #5 Pin (P5IP) — R/W. Indicates which pin the PCI Express* por t #5 drives as its

interrupt.

0h = No interrupt

1h = INTA# (Default)

2h = INTB#

3h = INTC#

4h = INTD#

5h-7h = Reserved

15:12

PCI Express* #4 Pin (P4IP) — R/W. Indicates which pin the PCI Express* por t #4 drives as its

interrupt.

0h = No interrupt

1h = INTA#

2h = INTB#

3h = INTC#

4h = INTD# (Default)

5h-7h = Reserved

11:8

PCI Express* #3 Pin (P3IP) — R/W. Indicates which pin the PCI Express* por t #3 drives as its

interrupt.

0h = No interrupt

1h = INTA#

2h = INTB#

3h = INTC# (Default)

4h = INTD#

5h-7h = Reserved

7:4

PCI Express* #2 Pin (P2IP) — R/W. Indicates which pin the PCI Express* por t #2 drives as its

interrupt.

0h = No interrupt

1h = INTA#

2h = INTB# (Default)

3h = INTC#

4h = INTD#

5h-7h = Reserved

3:0

PCI Express* #1 Pin (P1IP) — R/W. Indicates which pin the PCI Express* por t #1 drives as its

interrupt.

0h = No interrupt

1h = INTA# (Default)

2h = INTB#

3h = INTC#

4h = INTD#

5h-7h = Reserved

Bit Description

Chipset Configuration Registers

342 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

10.1.24 D27IP—Device 27 Interrupt Pin Register

Offset Address: 3110–3113h Attribute: R/W

Default Value: 00000001h Size: 32-bit

10.1.25 D26IP—Device 26 Interrupt Pin Register

Offset Address: 3114–3117h Attribute: R/W

Default Value: 30000321h Size: 32-bit

10.1.26 D25IP—Device 25 Interrupt Pin Register

Offset Address: 3118–311Bh Attribute: R/W

Default Value: 00000001h Size: 32-bit

Bit Description

31:4 Reserved

3:0

Intel HD Audio Pin (ZIP) — R/W. Indicates which pin the Intel HD Audio controller drives as its

interrupt.

0h = No interrupt

1h = INTA# (Default)

2h = INTB#

3h = INTC#

4h = INTD#

5h-Fh = Reserved

Bit Description

31:4 Reserved

3:0

EHCI #2 Pin (E2P) — R/W. Indicates which pin EHCI controller #2 drives as its interrupt, if

controller exists.

0h = No Interrupt

1h = INTA# (Default)

2h = INTB#

3h = INTC#

4h = INTD#

5h-Fh = Reserved

Note: EHCI Controller #2 is mapped to Device 26 Function 0.

Bit Description

31:4 Reserved

3:0

GbE LAN Pin (LIP) — R/W. Indicates which pin the internal GbE LAN controller drives as its

interrupt

0h = No Interrupt

1h = INTA# (Default)

2h = INTB#

3h = INTC#

4h = INTD#

5h-Fh = Reserved

Chipset Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 343

Datasheet

10.1.27 D22IP—Device 22 Interrupt Pin Register

Offset Address: 3124–3127h Attribute: R/W

Default Value: 00004321h Size: 32-bit

Bit Description

31:16 Reserved

15:12

KT Pin (KTIP) — R/W. Indicates which pin the Keyboard text PCI functionality drives as its

interrupt

0h = No Interrupt

1h = INTA#

2h = INTB#

3h = INTC#

4h = INTD#

5h-Fh = Reserved

11:8

(HEDT SKU

Only) Reserved

11:8

(SRV/WS

SKUs Only)

IDE-R Pin (IDERIP) — R/W. Indicates which pin the IDE Redirect PCI functionality drives as

its interrupt

0h = No Interrupt

1h = INTA#

2h = INTB#

3h = INTC#

4h = INTD#

5h-Fh = Reserved

7:4

Intel MEI #2 Pin (MEI2IP) — R/W. Indicates which pin the Intel MEI #2 drives as its

interrupt

0h = No Interrupt

1h = INTA#

2h = INTB#

3h = INTC#

4h = INTD#

5h-Fh = Reserved

3:0

Intel MEI #1 Pin (MEI1IP) — R/W. Indicates which pin the Intel MEI #1 drives as its

interrupt

0h = No Interrupt

1h = INTA#

2h = INTB#

3h = INTC#

4h = INTD#

5h-Fh = Reserved

Chipset Configuration Registers

344 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

10.1.28 D31IR—Device 31 Interrupt Route Register

Offset Address: 3140–3141h Attribute: R/W

Default Value: 3210h Size: 16-bit

10.1.29 D30IR—Device 30 Interrupt Route Register

Offset Address: 3142–3143h Attribute: RO

Default Value: 0000h Size: 16-bit

Bit Description

15 Reserved

14:12

Interrupt D Pin Route (IDR) — R/W. Indicates which physical pin on the PCH is connected to

the INTD# pin reported for device 31 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC#

3h = PIRQD# (Default)

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

11 Reserved

10:8

Interrupt C Pin Route (ICR) — R/W. Indicates which physical pin on the PCH is connected to

the INTC# pin reported for device 31 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC# (Default)

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

7 Reserved

6:4

Interrupt B Pin Route (IBR) — R/W. Indicates which physical pin on the PCH is connected to

the INTB# pin reported for device 31 functions.

0h = PIRQA#

1h = PIRQB# (Default)

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

3 Reserved

2:0

Interrupt A Pin Route (IAR) — R/W. Indicates which physical pin on the PCH is connected to

the INTA# pin reported for device 31 functions.

0h = PIRQA# (Default)

1h = PIRQB#

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

Bit Description

15:0 Reserved. No interrupts generated from Device 30.

Chipset Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 345

Datasheet

10.1.30 D29IR—Device 29 Interrupt Route Register

Offset Address: 3144–3145h Attribute: R/W

Default Value: 3210h Size: 16-bit

Bit Description

15 Reserved

14:12

Interrupt D Pin Route (IDR) — R/W. Indicates which physical pin on the PCH is connected to

the INTD# pin reported for device 29 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC#

3h = PIRQD# (Default)

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

11 Reserved

10:8

Interrupt C Pin Route (ICR) — R/W. Indicates which physical pin on the PCH is connected to

the INTC# pin reported for device 29 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC# (Default)

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

7Reserved

6:4

Interrupt B Pin Route (IBR) — R/W. Indicates which physical pin on the PCH is connected to

the INTB# pin reported for device 29 functions.

0h = PIRQA#

1h = PIRQB# (Default)

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

3Reserved

2:0

Interrupt A Pin Route (IAR) — R/W. Indicates which physical pin on the PCH is connected to

the INTA# pin reported for device 29 functions.

0h = PIRQA# (Default)

1h = PIRQB#

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

Chipset Configuration Registers

346 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

10.1.31 D28IR—Device 28 Interrupt Route Register

Offset Address: 3146–3147h Attribute: R/W

Default Value: 3210h Size: 16-bit

Bit Description

15 Reserved

14:12

Interrupt D Pin Route (IDR) — R/W. Indicates which physical pin on the PCH is connected to

the INTD# pin reported for device 28 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC#

3h = PIRQD# (Default)

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

11 Reserved

10:8

Interrupt C Pin Route (ICR) — R/W. Indicates which physical pin on the PCH is connected to

the INTC# pin reported for device 28 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC# (Default)

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

7 Reserved

6:4

Interrupt B Pin Route (IBR) — R/W. Indicates which physical pin on the PCH is connected to

the INTB# pin reported for device 28 functions.

0h = PIRQA#

1h = PIRQB# (Default)

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

3 Reserved

2:0

Interrupt A Pin Route (IAR) — R/W. Indicates which physical pin on the PCH is connected to

the INTA# pin reported for device 28 functions.

0h = PIRQA# (Default)

1h = PIRQB#

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

Chipset Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 347

Datasheet

10.1.32 D27IR—Device 27 Interrupt Route Register

Offset Address: 3148–3149h Attribute: R/W

Default Value: 3210h Size: 16-bit

Bit Description

15 Reserved

14:12

Interrupt D Pin Route (IDR) — R/W. Indicates which physical pin on the PCH is connected to

the INTD# pin reported for device 27 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC#

3h = PIRQD# (Default)

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

11 Reserved

10:8

Interrupt C Pin Route (ICR) — R/W. Indicates which physical pin on the PCH is connected to

the INTC# pin reported for device 27 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC# (Default)

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

7Reserved

6:4

Interrupt B Pin Route (IBR) — R/W. Indicates which physical pin on the PCH is connected to

the INTB# pin reported for device 27 functions.

0h = PIRQA#

1h = PIRQB# (Default)

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

3Reserved

2:0

Interrupt A Pin Route (IAR) — R/W. Indicates which physical pin on the PCH is connected to

the INTA# pin reported for device 27 functions.

0h = PIRQA# (Default)

1h = PIRQB#

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

Chipset Configuration Registers

348 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

10.1.33 D26IR—Device 26 Interrupt Route Register

Offset Address: 314C–314Dh Attribute: R/W

Default Value: 3210h Size: 16-bit

Bit Description

15 Reserved

14:12

Interrupt D Pin Route (IDR) — R/W. Indicates which physical pin on the PCH is connected to

the INTD# pin reported for device 26 functions:

0h = PIRQA#

1h = PIRQB#

2h = PIRQC#

3h = PIRQD# (Default)

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

11 Reserved

10:8

Interrupt C Pin Route (ICR) — R/W. Indicates which physical pin on the PCH is connected to

the INTC# pin reported for device 26 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC# (Default)

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

7 Reserved

6:4

Interrupt B Pin Route (IBR) — R/W. Indicates which physical pin on the PCH is connected to

the INTB# pin reported for device 26 functions.

0h = PIRQA#

1h = PIRQB# (Default)

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

3 Reserved

2:0

Interrupt A Pin Route (IAR) — R/W. Indicates which physical pin on the PCH is connected to

the INTA# pin reported for device 26 functions.

0h = PIRQA# (Default)

1h = PIRQB#

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

Chipset Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 349

Datasheet

10.1.34 D25IR—Device 25 Interrupt Route Register

Offset Address: 3150–3151h Attribute: R/W

Default Value: 3210h Size: 16-bit

Bit Description

15 Reserved

14:12

Interrupt D Pin Route (IDR): — R/W. Indicates which physical pin on the PCH is connected to

the INTD# pin reported for device 25 functions:

0h = PIRQA#

1h = PIRQB#

2h = PIRQC#

3h = PIRQD# (Default)

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

11 Reserved

10:8

Interrupt C Pin Route (ICR) — R/W. Indicates which physical pin on the PCH is connected to

the INTC# pin reported for device 25 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC# (Default)

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

7Reserved

6:4

Interrupt B Pin Route (IBR) — R/W. Indicates which physical pin on the PCH is connected to

the INTB# pin reported for device 25 functions.

0h = PIRQA#

1h = PIRQB# (Default)

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

3Reserved

2:0

Interrupt A Pin Route (IAR) — R/W. Indicates which physical pin on the PCH is connected to

the INTA# pin reported for device 25 functions.

0h = PIRQA# (Default)

1h = PIRQB#

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

Chipset Configuration Registers

350 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

10.1.35 D22IR—Device 22 Interrupt Route Register

Offset Address: 315C–315Dh Attribute: R/W

Default Value: 3210h Size: 16-bit

Bit Description

15 Reserved

14:12

Interrupt D Pin Route (IDR): — R/W. Indicates which physic al pin on the PCH is conne cted to

the INTD# pin reported for device 22 functions:

0h = PIRQA#

1h = PIRQB#

2h = PIRQC#

3h = PIRQD# (Default)

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

11 Reserved

10:8

Interrupt C Pin Route (ICR) — R/W. Indicates which physical pin on the PCH is connected to

the INTC# pin reported for device 22 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC# (Default)

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

7 Reserved

6:4

Interrupt B Pin Route (IBR) — R/W. Indicates which physical pin on the PCH is connected to

the INTB# pin reported for device 22 functions.

0h = PIRQA#

1h = PIRQB# (Default)

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

3 Reserved

2:0

Interrupt A Pin Route (IAR) — R/W. Indicates which physical pin on the PCH is connected to

the INTA# pin reported for device 22 functions.

0h = PIRQA# (Default)

1h = PIRQB#

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

Chipset Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 351

Datasheet

10.1.36 OIC—Other Interrupt Control Register

Offset Address: 31FE–31FFh Attribute: R/W

Default Value: 0000h Size: 16-bit

Note: FEC1_0000h–FEC4_FFFFh is allocated to PCIe when I/OxApic Enable (PAE) bit is set.

10.1.37 PRSTS—Power and Reset Status Register

Offset Address: 3310–3313h Attribute: RO, R/WC

Default Value: 03000000h Size: 32-bit

Bit Description

15:10 Reserved

Coprocessor Error Enable (CEN) — R/W.

0 = FERR# will not generate IRQ13 nor IGNNE#.

1 = If FERR# is low, the PCH generates IRQ13 internal ly and holds it until an I/O port F0h write.

It will also drive IGNNE# active.

APIC Enable (AEN) — R/W.

0 = The internal IOxAPIC is disabled.

1 = Enables the internal IOxAPIC and its address decode.

Note: Software should read this register after modifying APIC enable bit prior to access to the

IOxAPIC address range.

7:0 APIC Range Select (ASEL) — R/W.These bits define address bits 19:12 for the IOxAPIC range.

The default value of 00h enables compatibility with prior PCH products as an initial value. This

value must not be changed unless the IOxAPIC Enable bit is cleared.

Bit Description

31:16 Reserved

15 Power Management Watchdog Timer — R/WC. This bit is set when the Power Management

watchdog timer causes a global reset.

14:7 Reserved

6Intel ME Watchdog Timer Status — R/WC. This bit is set when the Intel ME watchdog timer

causes a global rese t.

Wake On LAN Override Wake Status (WOL_OVR_WK_STS) — R/WC. This bit gets set when

all of the following conditions are met:

• Integrated LAN Signals a Power Management Event

• The system is not in S0

• The “WOL Enable Override” bit is set in configuration space.

BIOS can read this status bit to determine this wake source.

Software clears this bit by writing a 1 to it.

4PRSTS Field 1 — R/W. BIOS may write to this bit field.

3Intel ME Host Power Down (ME_HOST_PWRDN) — R/WC.This bit is set when the Intel ME

generates a host reset with power down.

2Intel ME Host Reset Warm Status (ME_HRST_WARM_STS) — R/WC. This bit is set when

the Intel ME generates a Host reset without power cycling. Software clears this bit by writing a 1

to this bit position.

1Intel ME Host Reset Cold Status (ME_HRST_COLD_STS) — R/WC. This bit is set when the

Intel ME generates a Host reset with power cycling. Software clears this bit by writing a 1 to this

bit position.

0Intel ME WAKE STATUS (ME_WAKE_STS) — R/WC. This bit is set when the Intel ME

generates a Non-Maskable w ake ev ent, and is no t affected by any other enable bit. When this bit

is set, the Host Power Management logic wakes to S0.

Chipset Configuration Registers

352 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

10.1.38 PM_CFG—Power Management Configuration

Offset Address: 3318–331Bh Attribute: R/W

Default Value: 00000000h Size: 32-bit

Bit Description

31:27 Reserved.

26:24 PM_CFG Field 1 — R/W. BIOS must program this field to ‘101’.

23:22 Reserved.

21 RTC Wake from Deep S4/S5 Disable (RTC_DS_WAKE_DIS)— R/W. When set, this bit

disables RTC wakes from waking the system from Deep S4/S5.

This bit is reset by RTCRST#.

20 Reserved.

19:18

SLP_SUS# Minimum Assertion Width (SLP_SUS_MIN_ASST_WDTH)— R/W. This field

indicates the minimum assertion width of the SLP_SUS# signal to ensure that the SUS power

supplies have been fully power cycled. This value may be modified per platform depending on

power supply capacitance, board capacitance, power circuits, etc.

Valid va lues are:

11 = 4 seconds

10 = 1 second

01 = 500 ms

00 = 0 ms (that is, stretching disabled - default)

These bits are cleared by RTCRST# assertion.

This field is RO when the SLP Stretching Policy Loc k-Down bit is set.

This field is ignored when exiting G3 or Deep S4/S5 states if the “Disable SLP Stretching After

SUS W ell Power Up” bit is set. Note that unlike with al l other SLP_* pin stretching, this disable bit

only impacts SLP_SUS# stretching during G3 exit rather than both G3 and Deep S4/S5 exit.

SLP_SUS# stretching always applies to Deep S4/S5 regardless of the disable bit.

For platforms that enable Deep S4/S5, BIOS must program SLP_SUS# stretching to be greater

than or equal to the largest stretching value on any other SLP_* pin (SLP_S3#, SLP_S4#, or

SLP_A#).

17:16

SLP_A# Minimum Assertion Width (SLP_A_MIN_ASST_WDTH) — R/W. This field indicates

the minimum assertion width of the SLP_A# signal to ensure that the ASW power supplies have

been fully power cycled. This value may be modified per platform depen ding on power supply

capacitance, board capacitance, power circuits, etc.

Valid va lues are:

11 = 2 seconds

10 = 98 ms

01 = 4 seconds

00 = 0 ms (that is, stretching disabled - default)

These bits are cleared by RTCRST# assertion.

Notes:

1. This field is RO when the SLP Stretching Policy Lock-Down bit is set.

2. This field is ignored when exiting G3 or Deep S4/S5 states if the “Disable SLP Stretching

After SUS Well Power Up” bit is set.

15:0 Reserved.

Chipset Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 353

Datasheet

10.1.39 DEEP_S4_POL—Deep S4/S5 From S4 Power Policies

Offset Address: 332C–332Fh Attribute: R/W

Default Value: 00000000h Size: 32-bit

This register is in the RTC power well and is reset by RTCRST# assertion.

10.1.40 DEEP_S5_POL—Deep S4/S5 From S5 Power Policies

Offset Address: 3330–3333h Attribute: R/W

Default Value: 00000000h Size: 32-bit

This register is in the RTC power well and is reset by RTCRST# assertion.

10.1.41 RC—RTC Configuration Register

Offset Address: 3400–3403h Attribute: R/W, R/WLO

Default Value: 00000000h Size: 32-bit

Bit Description

31:2 Reserved.

1Deep S4/S5 From S4 Enable in DC Mode (DPS4_EN_DC) — R/W. A '1' in this bit enables

the platform to enter Deep S4/S5 while operating in S4 on DC power (based on the AC_PRESENT

pin value).

0Deep S4/S5 From S4 Enable in AC Mode (DPS4_EN_AC) — R/W. A '1' in this bit enables

the platform to enter Deep S4 while operating in S4 on AC power (based on the AC_PRESENT pin

value).

Bit Description

31:16 Reserved.

15 Deep S4/S5 From S5 Enable in DC Mode (DPS5_EN_DC) — R/W. A '1' in this bit enables

the platform to enter Deep S4/S5 while operating in S5 on DC power.

14 Deep S4/S5 From S5 Enable in AC Mode (DPS5_EN_AC) — R/W. A '1' in this bit enables

the platform to enter Deep S4/S5 while operating in S5 on AC power.

13:0 Reserved.

Bit Description

31:5 Reserved

Upper 128 Byte Lock (UL) — R/WLO.

0 = Bytes not locked.

1 = Bytes 38h-3Fh in the upper 128-byte bank of RTC RAM are locked and cannot be accessed.

Writes will be dropped and reads will not return any ensured data. Bit reset on system reset.

Lower 128 Byte Lock (LL) — R/WLO.

0 = Bytes not locked.

1 = Bytes 38h-3Fh in the lower 128-byte bank of RTC RAM are locked and cannot be accessed.

Writes will be dropped and reads will not return any ensured data. Bit reset on system reset.

2Upper 128 Byte Enable (UE) — R/W.

0 = B ytes locked.

1 = T he upper 128-byte bank of RTC RAM can be accessed.

1:0 Reserved

Chipset Configuration Registers

354 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

10.1.42 HPTC—High Precision Timer Configuration Register

Offset Address: 3404–3407h Attribute: R/W

Default Value: 00000000h Size: 32-bit

10.1.43 GCS—General Control and Status Register

Offset Address: 3410–3413h Attribute:R/W, R/WLO

Default Value: 00000yy0h (yy = xx0000x0b)Size:32-bit

Bit Description

31:8 Reserved

Address Enable (AE) — R/W.

0 = A ddress disabled.

1 = The PCH will decode the High Precision Timer memory address range selected by bits 1:0

below.

6:2 Reserved

1:0

Address Select (AS) — R/W. This 2-bit field selects 1 of 4 possible memory address ranges for

the High Precision Timer functionality. The encodings are:

00 = FED0_0000h – FED0_03FFh

01 = FED0_1000h – FED0_13FFh

10 = FED0_2000h – FED0_23FFh

11 = FED0_3000h – FED0_33FFh

Bit Description

31:13 Reserved.

Function Level Reset Capability Structure Select (FLRCSSEL) — R/W.

0 = Function Level Re set (FLR) will utilize the standard capability struc ture with unique capability

ID assigned by PCISIG.

1 = Vendor Specific Capability Structure is selected for FLR.

11:10

Boot BIOS Straps (BBS) — R/W. This field d etermines the destination of accesses to the BIOS

memory range. The default values for thes e bits represent the strap values of GNT1# /GPIO5 1

(bit 11) at the rising edge of PCH_PWROK and SATA1GP/GPIO19 (bit 10) at the rising edge of

PCH_PWROK.

When PCI is selected, the top 16 MB of memory below 4 GB (FF00_0000h to FFFF_FFFFh) is

accepted by the primary side of the PCI P2P bridge and forwarded to the PCI bus. This allows

systems with corrupted or unprogrammed flash to boot from a PCI device. The PCI-to-PCI bridge

Memory Space Enable bit does not need to be set (nor any other bits) in order for thes e cycles to

go to PCI. Note that BIOS decode range bits and the other BIOS protection bits have no effect

when PCI is selected. This functionality is intended for debug/testing only.

When SPI or LPC is selected, the range that is decoded is further qualified by other configur ati on

bits describe d in the respective sections.

The value in this field can be overwr itten by software as long as the BIOS Interface Lock-Down

(bit 0) is not set.

Note: Booting to PCI is intended for debug/testing only. Boot BIOS Destination Select to LPC/

PCI by functional strap or using Boot BIOS Destination Bit will not affect SPI accesses

initiated by Intel ME or Integrated GbE LAN.

Bits 11:10 Description

00b LPC

01b RESERVED

10b PCI

11b SPI

Chipset Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 355

Datasheet

Server Error Reporting Mode (SERM) — R/W.

0 = T he PCH is the final target of all errors. The Processor sends a messages to the PCH for the

purpose of generating NMI.

1 = The Processor i s the final target of all errors from PCI Express * and DMI. In this mode, if the

PCH detects a fatal, non-fatal, or correctable error on DMI or its downstream ports, it sends

a message to the Processor. If the PCH rece ives an ERR_* message from the downstr eam

port, it sends that message to the Processor.

8:6 Reserved

No Reboot (NR) — R/W. This bit is set when the “No Reboot” strap (SPKR pin on the PCH) is

sampled high on PCH_PWROK. This bit may be set or cleared by software if the strap is sampled

low but may not overrid e the strap when it indicates “No Reboot”.

0 = System will reboot upon the second timeout of the TCO timer.

1 = T he TCO timer will count down and generate the SMI# on the first timeout, but will not

reboot on the second timeout.

Alternate Access Mode Enable (AME) — R/W.

0 = Disabled.

1 = Alternate access read only registers can be written, and write only registers can be read.

Before entering a low power state, several registers from powered down parts may need to

be saved. In the majority of cases, this is not an issue, as registers have read and write

paths. Howe ver, sev er al of the ISA com patible regis ters ar e eith er read o nly or w rite o nly. To

get data out of write-only registers, and to restore data into read-only registers, the PCH

implements an alternate access mode. For a list of these registers see Section 5.14.9.

Shutdown Policy Select (SPS) — R/W.

0 = PCH will drive INIT# in response to the shutdown Vendor Defined Message (VDM). (Default)

1 = PCH will treat the shutdown VDM similar to receiving a CF9h I/O write with data value 06h,

and will drive PLTRST# active.

Reserved Page Route (RPR) — R/W. Determines where to send the reserved page registers.

These addresses are sent to PCI or LPC for the purpose of generating POST codes. The I/O

addresses modified by this field are: 80h, 84h, 85h, 86h, 88h, 8Ch, 8Dh, and 8Eh.

0 = Writes will be forwarded to LPC, shadowed within the PCH, and reads will be returned from

the internal shadow

1 = Writes will be forwarded to PCI, shadowed within the PCH, and reads will be returned from

the internal shadow.

Note: If some writes are done to LPC/PCI to these I/O r anges, and then this bit is flipped, such

that writes will now go to the other interface, the reads will not return what was last

written. Shadowing is performed on each interface.

The alia ses for these registers, at 90h, 94h, 95h, 96h, 98h, 9Ch, 9Dh, and 9Eh, are always

decoded to LPC.

1Reserved

BIOS Interface Lock-Down (BILD) — R/WLO.

0 = Disabled.

1 = Pre vents BUC.TS (offset 3414, bit 0) and GCS.BBS (offset 3410h, bits 11:10) from being

changed. This bit can only be written from 0 to 1 once.

Bit Description

Chipset Configuration Registers

356 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

10.1.44 BUC—Backed Up Control Register

Offset Address: 3414–3414h Attribute: R/W

Default Value: 0000000xb Size: 8-bit

All bits in this register are in the RTC well and only cleared by RTCRST#

10.1.45 FD—Function Disable Register

Offset Address: 3418–341Bh Attribute: R/W

Default Value: See bit description Size: 32-bit

When disabling a function, only the configuration space is disabled. Software must

ensure that all functionality within a controller that is not desired (such as memory

spaces, I/O spaces, and DMA engines) is disabled prior to disabli ng the function.

When a function is disabled, software must not attempt to re-enable it. A disabled

function can only be re-enabled by a platform reset.

Bit Description

7:6 Reserved

LAN Disable — R/W.

0 = LAN is Enabled

1 = L AN is Disabled.

Changing the internal GbE controller from disabled to enabled requires a system

reset (write of 0Eh to CF9h (RST_CNT Register)) immediately after clearing the LAN

disable bit. A reset is not required if changing the bit from enabled to disabled.

This bit is locked by the Function Disable SUS W ell Lockdown register. Once locked this bit can not

be change d by software.

4Daylight Savings Override (SDO) — R/W.

0 = Daylight Savings is Enabled.

1 = The DSE bit i n RTC Re gister B is set to R ead-onl y with a v alue of 0 to disab le daylig ht sa vings.

3:1 Reserved

Top Swap (TS) — R/W.

0 = PCH will not invert A16.

1 = PCH will invert A16, A17, or A18 for cycles going to the BIOS space in the FWH.

If booting from LPC (FWH), then the boot-block size is 64 KB and A16 is inverted if

Top Swap is enabled.

If booting from SPI, then the BIOS Boot-Block size soft strap determines if A16, A17,

or A18 should be inverted if Top Swap is enabled.

If PCH is strapped for Top-Swap (GNT3#/GPIO55 is low at ris i ng ed ge of PC H _PWRO K), the n t his

bit cannot be cleared by softw are. T he str ap ju mper sho uld be remo ve d and the system rebo oted.

Bit Description

31:26 Reserved

25 Serial ATA Disable 2 (SAD2) — R/W. Default is 0.

0 = T he SATA controller #2 (D31:F5) is enabled.

1 = T he SATA controller #2 (D31:F5) is disabled.

24 Thermal Sensor Registers Disable (TTD) — R/W. Default is 0.

0 = Thermal Sensor Registers (D31:F6) are is enabled.

1 = Thermal Sensor Registers (D31:F6) are is disabled.

PCI Express* 8 Disable (PE8D) — R/W . Default is 0. When disabled, the link for this port is put

into the “link down” state.

0 = PCI Express* port #8 is enabled.

1 = PCI Express* port #8 is disabled.

Chipset Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 357

Datasheet

PCI Express* 7 Disable (PE7D) — R/W . Default is 0. When disabled, the link for this port is put

into the link down state.

0 = PCI Express* port #7 is enabled.

1 = PCI Express* port #7 is disabled.

PCI Express* 6 Disable (PE6D) — R/W . Default is 0. When disabled, the link for this port is put

into the “link down” state.

0 = PCI Express* port #6 is enabled.

1 = PCI Express* port #6 is disabled.

PCI Express* 5 Disable (PE5D) — R/W . Default is 0. When disabled, the link for this port is put

into the link down state.

0 = PCI Express* port #5 is enabled.

1 = PCI Express* port #5 is disabled.

PCI Express* 4 Disable (PE4D) — R/W . Default is 0. When disabled, the link for this port is put

into the “link down” state.

0 = PCI Express* port #4 is enabled.

1 = PCI Express* port #4 is disabled.

Note: This bit must be set when Port 1 is configured as a x4.

PCI Express* 3 Disable (PE3D) — R/W . Default is 0. When disabled, the link for this port is put

into the link down state.

0 = PCI Express* port #3 is enabled.

1 = PCI Express* port #3 is disabled.

Note: This bit must be set when Port 1 is configured as a x4.

PCI Express* 2 Disable (PE2D) — R/W . Default is 0. When disabled, the link for this port is put

into the link down state.

0 = PCI Express* port #2 is enabled.

1 = PCI Express* port #2 is disabled.

Note: This bit must be set when Port 1 is configured as a x4 or a x2.

PCI Express* 1 Disable (PE1D) — R/W . Default is 0. When disabled, the link for this port is put

into the link down state.

0 = PCI Express* port #1 is enabled.

1 = PCI Express* port #1 is disabled.

15 EHCI #1 Disable (EHCI1D) — R/W. Default is 0.

0 = The EHCI #1 is enabled.

1 = The EHCI #1 is disabled.

LPC Bridge Disable (LBD) — R/W. Default is 0.

0 = T he LPC bridge is enabled.

1 = The LPC bridge is disabled. Unlike the other disables in this register, the following additional

spaces will no lon ger be decoded by the LPC bridge:

• Memory cycles below 16 MB (1000000h)

• I/O cycles below 64 KB (10000h)

• The Internal I/OxAPIC at FEC0_0000 to FECF_FFFF

Memory cycles in the LPC BIOS range below 4 GB will sti ll be decoded when this bit is set, but the

aliases at the top of 1 MB (the E and F segment) no longer will be decoded.

13 EHCI #2 Disable (EHCI2D) — R/W. Default is 0.

0 = The EHCI #2 is enabled.

1 = T he EHCI #2 is disabled.

12:5 Reserved

4Intel HD Audio Disable (HDAD) — R/W. Default is 0.

0 = The Intel HD Audio controller is enabled.

1 = T he Intel HD Audio controller is disabled and its PCI configuration space is not accessible.

SMBus Disable (SD) — R/W. Default is 0.

0 = T he SMBus controller is enabled.

1 = The SMBus controller is disabled. In ICH5 and previous, this also disabled the I/O space. In

the PCH, it only disables the configuration space.

Bit Description

Chipset Configuration Registers

358 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

PCI Express* 7 Disable (PE7D) — R/W . Default is 0. When disabled, the link for this port is put

into the link down state.

0 = PCI Express* port #7 is enabled.

1 = PCI Express* port #7 is disabled.

PCI Express* 6 Disable (PE6D) — R/W . Default is 0. When disabled, the link for this port is put

into the “link down” state.

0 = PCI Express* port #6 is enabled.

1 = PCI Express* port #6 is disabled.

PCI Express* 5 Disable (PE5D) — R/W . Default is 0. When disabled, the link for this port is put

into the link down state.

0 = PCI Express* port #5 is enabled.

1 = PCI Express* port #5 is disabled.

PCI Express* 4 Disable (PE4D) — R/W . Default is 0. When disabled, the link for this port is put

into the “link down” state.

0 = PCI Express* port #4 is enabled.

1 = PCI Express* port #4 is disabled.

Note: This bit must be set when Port 1 is configured as a x4.

PCI Express* 3 Disable (PE3D) — R/W . Default is 0. When disabled, the link for this port is put

into the link down state.

0 = PCI Express* port #3 is enabled.

1 = PCI Express* port #3 is disabled.

Note: This bit must be set when Port 1 is configured as a x4.

PCI Express* 2 Disable (PE2D) — R/W . Default is 0. When disabled, the link for this port is put

into the link down state.

0 = PCI Express* port #2 is enabled.

1 = PCI Express* port #2 is disabled.

Note: This bit must be set when Port 1 is configured as a x4 or a x2.

PCI Express* 1 Disable (PE1D) — R/W . Default is 0. When disabled, the link for this port is put

into the link down state.

0 = PCI Express* port #1 is enabled.

1 = PCI Express* port #1 is disabled.

15 EHCI #1 Disable (EHCI1D) — R/W. Default is 0.

0 = The EHCI #1 is enabled.

1 = The EHCI #1 is disabled.

LPC Bridge Disable (LBD) — R/W. Default is 0.

0 = The LPC bridge is enabled.

1 = The LPC bridge is disabled. Unlike the other disables in this register, the following additional

spaces will no longer be decoded by the LPC bridge:

• Memory cycles below 16 MB (1000000h)

• I/O cycles below 64 KB (10000h)

• The Internal I/OxAPIC at FEC0_0000 to FECF_FFFF

Memory cycles in the LPC BIOS range below 4 GB will still be decoded when this bit is set, but the

aliases at the top of 1 MB (the E and F segment) no longer will be decoded.

13 EHCI #2 Disable (EHCI2D) — R/W. Default is 0.

0 = The EHCI #2 is enabled.

1 = The EHCI #2 is disabled.

12:5 Reserved

4Intel HD Audio Disable (HDAD) — R/W. Default is 0.

0 = T he Intel HD Audio controller is enabled.

1 = The Intel HD Audio controller is disabled and its PCI configuration space is not accessible.

SMBus Disable (SD) — R/W. Default is 0.

0 = The SMBus controller is enabled.

1 = The SMBus controller is disabled. In ICH5 and previous, this also disabled the I/O space. In

the PCH, it only disables the configuration space.

Bit Description

Chipset Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 359

Datasheet

10.1.46 CG—Clock Gating

Offset Address: 341C–341Fh Attribute: R/W

Default Value: 00000000h Size: 32-bit

2Serial ATA Disable 1 (SAD1) — R/W. Default is 0.

0 = The SATA controller #1 (D31:F2) is enabled.

1 = The SATA controller #1 (D31:F2) is disabled.

1PCI Bridge Disable — R/W. Default is 0.

0 = T he PCI-to-PCI bridge (D30:F0) is enabled.

1 = T he PCI-to-PCI bridge (D30:F0) is disabled.

0 BIOS must set this bit to 1b.

Bit Description

31 Legacy (LPC) Dynamic Clock Gate Enable — R/W.

0 = Legacy Dynamic Clock Gating is Disabled

1 = Legacy Dynamic Clock Gating is Enabled

30 Reserved

29:28 CG Field 1 — R/W. BIOS must program this field to 11b.

27 SATA Port 3 Dynamic Clock Gate Enable — R/W.

0 = SATA Port 3 Dynamic Clock Gating is Disabled

1 = SATA Port 3 Dynamic Clock Gating is Enabled

26 SATA Port 2 Dynamic Clock Gate Enable — R/W.

0 = SATA Port 2 Dynamic Clock Gating is Disabled

1 = SATA Port 2 Dynamic Clock Gating is Enabled

25 SATA Port 1 Dynamic Clock Gate Enable — R/W.

0 = SATA Port 1 Dynamic Clock Gating is Disabled

1 = SATA Port 1 Dynamic Clock Gating is Enabled

24 SATA Port 0 Dynamic Clock Gate Enable — R/W.

0 = SATA Port 0 Dynamic Clock Gating is Disabled

1 = SATA Port 0 Dynamic Clock Gating is Enabled

LAN Static Clock Gating Enable (LANSCGE) — R/W.

0 = LAN Static Clock Gating is Disabled

1 = LAN Static Clock Gating is Enabled when the LAN Disable bit is set in the Backed Up Control

RTC regi ster.

22 Intel HD Audio Dynamic Clock Gate Enable — R/W.

0 = Intel HD Audio Dynamic Clock Gating is Disabled

1 = Intel HD Audio Dynamic Clock Gating is Enabled

21 Intel HD Audio Static Clock Gate Enable — R/W.

0 = Intel HD Audio Static Clock Gating is Disabled

1 = Intel HD Audio Static Clock Gating is Enabled

20 USB EHCI Static Clock Gate Enable — R/W.

0 = USB EHCI Static Clock Gating is Disabled

1 = USB EHCI Static Clock Gating is Enabled

19 USB EHCI Dynamic Clock Gate Enable — R/W.

0 = USB EHCI Dynamic Clock Gating is Disabled

1 = USB EHCI Dynamic Clock Gating is Enabled

18 SATA Port 5 Dynamic Clock Gate Enable — R/W.

0 = SATA Port 5 Dynamic Clock Gating is Disabled

1 = SATA Port 5 Dynamic Clock Gating is Enabled

17 SATA Port 4 Dynamic Clock Gate Enable — R/W.

0 = SATA Port 4 Dynamic Clock Gating is Disabled

1 = SATA Port 4 Dynamic Clock Gating is Enabled

16 PCI Dynamic Gate Enable — R/W.

0 = PCI Dynamic Gating is Disabled

1 = PC I Dynamic Gating is Enabled

Chipset Configuration Registers

360 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

10.1.47 FDSW—Function Disable SUS Well

Offset Address: 3420h Attribute: R/W

Default Value: 00h Size: 8-bit

10.1.48 FD2—Function Disable 2

Offset Address: 3428–342Bh Attribute: R/W

Default Value: 00000000h Size: 32-bit

15:6 Reserved

5SMBus Clock Gating Enable (SMBCGEN) — R/W.

0 = SMBus Clock Gating is Disabled.

1 = SMBus Clock Gating is Enabled.

4:1 Reserved

0PCI Express* Root Port Static Clock Gate Enable — R/W.

0 = PCI Express* root port Static Clock Gating is Disabled

1 = PCI Express* root port Static Clock Gating is Enabled

Bit Description

Function Disable SUS Well Lockdown (FDSWL)— R/W03

0 = FDSW registers are not locked down

1 = F DSW registers are locked down and this bit will remain set until a global reset occurs.

Note: This bit must be set when Intel® Active Management Technology is enabled.

6:0 Reserved

Bit Description

31:5 Reserved

4KT Disable (KTD) —R/W. Default is 0.

0 = Keyboard Text controller (D22:F3) is enabled.

1 = Keyboard Text controller (D22:F3) is Disabled

IDE-R Disable (IRERD) —R/W. Default is 0.

0 = IDE Redirect controller (D22:F2) is Enabled.

1 = IDE Redirect controller (D22:F2) is Disabled.

Intel MEI #2 Disable (MEI2D) —R/W. Default is 0.

0 = Intel MEI controller #2 (D22:F1) is enabled.

1 = Intel MEI controller #2 (D22:F1) is disabled.

Intel MEI #1 Disable (MEI1D) —R/W. Default is 0.

0 = Intel MEI controller #1 (D22:F0) is enabled.

1 = Intel MEI controller #1 (D22:F0) is disabled.

0 Reserved

Chipset Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 361

Datasheet

10.1.49 GSXBAR—GPIO Serial Expander Base Address

Offset Address: 3450–3453h Attribute: R/W, RO

Default Value: FED04000h Size: 3 2-bit

10.1.50 GSXCTRL—GPIO Serial Expander Control Register

Offset Address: 3454–3457h Attribute: R/W, RO

Default Value: 00000000h Size: 32-bit

10.1.51 MISCCTL—Miscellaneous Control Register

Offset Address: 3590-3593h Attribute: R/W

Default Value: 00000000h Size: 32-bit

This register is in the suspend well. This register is not reset on D3-to-D0, HCRESET

nor core well reset.

Bit Description

31:10 Base Address (BA) —R/W. Base Address of GPIO Serial Expander logic.

9:4 Reserved

3Prefetchable Memory (PF) —RO. Default is 0.

Indicate the memory space is not prefetchable.

2:1 Memory Type (TP) —RO. Set to 00b indicating a 32-bit BAR.

0Resource Type (RTE) —RO. Set to 0 indicating a Memory Space BAR.

Bit Description

31:5 Reserved

GSX BAR Enable (GSXBAREN) —R/W. Default is 0.

0 = GSXBAR is disabled.

1 = GSXBAR is enabled.

Note: If GSX is disabled using soft strap, this bit will always read 0.

3:0 Reserved

Bit Description

31:2 Reserved.

EHCI 2 USBR Enable — R/W. When set, this bit enables support for the USB-r redirect device on

the EHCI controller in Device 26. SW must complete programming the following registers before

this bit is set:

1. Enable RMH

2. HCSPARAMS (N_CC, N_Ports)

EHCI 1 USBR Enable — R/W. When set, this bit enables support for the USB-r redirect device on

the EHCI controller in Device 29. SW must complete programming the following registers before

this bit is set:

1. Enable RMH

2. HCSPARAMS (N_CC, N_Ports)

Chipset Configuration Registers

362 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

10.1.52 USBOCM1—Overcurrent MAP Register 1

Offset Address: 35A0-35A3h Attribute: R/W0

Default Value: C0300C03h Size: 32-bit

All bits in this register are in the Resume Well and is only cleared by RSMRST#.

Bit Description

31:24

OC3 Mapping Each bit position maps OC3# to a set of ports as follows: The OC3# pin is ganged

to the overcurrent signal of each port that has its corresponding bit set. It is SW‘s responsibility

to ensure that a given port‘s bit map is set only for one OC pin.

23:16

OC2 Mapping Each bit position maps OC2# to a set of ports as follows: The OC2# pin is ganged

to the overcurrent signal of each port that has its corresponding bit set. It is SW‘s responsibility

to ensure that a given port‘s bit map is set only for one OC pin.

15:8

OC1 Mapping Each bit position maps OC1# to a set of ports as follows: The OC1# pin is ganged

to the overcurrent signal of each port that has its corresponding bit set. It is SW‘s responsibility

to ensure that a given port‘s bit map is set only for one OC pin.

7:0

OC0 Mapping Each bit position maps OC0# to a set of ports as follows: The OC0# pin is ganged

to the overcurrent signal of each port that has its corresponding bit set. It is SW‘s responsibility

to ensure that a given port‘s bit map is set only for one OC pin.

Bit 31 30 29 28 27 26 25 24

Port 76543210

Bit 23 22 21 20 19 18 17 16

Port 76543210

Bit 15 14 13 12 11 10 9 8

Port 76543210

Bit 76543210

Port 76543210

Chipset Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 363

Datasheet

10.1.53 USBOCM2—Overcurrent MAP Register 2

Offset Address: 35A4-35A7h Attribute: R/W0

Default Value: 00h Size: 32-bit

All bits in this register are in the Resume Well and is only cleared by RSMRST#.

10.1.54 RMHWKCTL- Rate Matching Hub Wake Control Register

Offset Address: 35B0-35B3h Attribute: R/W

Default Value: 00000000h Size: 32-bit

All bits in this register are in the Resume Well and is only cleared by RSMRST#

Bit Description

31:30 Reserved

29:24

OC7 Mapping Each bit position maps OC7# to a set of ports as follows: The OC7# pin is ganged

to the overcurrent signal of each port that has its corresponding bit set. It is SW‘s responsibility

to ensure that a given port‘s bit map is set only for one OC pin.

23:22 Reserved

21:16

OC6 Mapping Each bit position maps OC6# to a set of ports as follows: The OC6# pin is ganged

to the overcurrent signal of each port that has its corresponding bit set. It is SW‘s responsibility

to ensure that a given port‘s bit map is set only for one OC pin.

15:14 Reserved

13:8

OC5 Mapping Each bit position maps OC5# to a set of ports as follows: The OC5# pin is ganged

to the overcurrent signal of each port that has its corresponding bit set. It is SW‘s responsibility

to ensure that a given port‘s bit map is set only for one OC pin.

7:6 Reserved

5:0

OC4 Mapping Each bit position maps OC4# to a set of ports as follows: The OC4# pin is ganged

to the overcurrent signal of each port that has its corresponding bit set. It is SW‘s responsibility

to ensure that a given port‘s bit map is set only for one OC pin.

Bit 29 28 27 26 25 24

Port 13 12 11 10 9 8

Bit 21 20 19 18 17 16

Port 13 12 11 10 9 8

Bit 13 12 11 10 9 8

Port 13 12 11 10 9 8

Bit 543210

Port 13 12 11 10 9 8

Bit Description

31:10 Reserved

9RMH 2 Inherit EHCI2 Wake Control Settings: When this bit is set, the RMH behaves as if bits

6:4 of this register reflect the appropriate bits of EHCI PORTSC0 bits 22:20.

8RMH 1 Inherit EHCI1 Wake Control Settings: When this bit is set, the RMH behaves as if bits

2:0 of this register reflect the appropriate bits of EHCI PORTSC0 bits 22:20.

RMH 2 Upstream Wake on Device Resume This bit governs the hub behavior when globally

suspended and the system is in Sx.

0 = Enables the port to be sensitive to device initiated resume events as system wake-up events.

that is, the hub will initiate a resume on its upstream port and cause a wake from Sx when a

device resume occurs on an enabled DS port

1 = Device resume event is seen on a do wnstream port, the hu b d oes not initiate a wake

upstream and does not cause a wake from Sx

Chipset Configuration Registers

364 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

RMH 2 Upstream Wake on OC Disable This bit governs the hub behavior when globally

suspended and the system is in Sx.

0 = E nables the port to be sensitive to over-current conditions as system wake-up events. i.e,

the hub will initiate a resume on its upstream port and cause a wake from Sx when an OC

condition occurs on an enabled DS port

1 = Over-current event does not initiate a wake upstream and does not cause a wake from Sx

RMH 2 Upstream Wake on Disconnect Disable This bit governs the hub behavior when

globally suspended and the system is in Sx

0 = Enables disconnect events on downstream port to be treated as resume events to be

propagated upstream. In this case, it is allowed to initiate a wake on its upstream port and

cause a system wake from Sx in response to a disconnect event on a downstream port

1 = Downstream disconnect events do not initiate a resume on its upstream port or cause a

resume from Sx.

RMH 2 Upstream Wake on Connect Enable This bit governs the hub behavior when globally

suspended and the system is in Sx.

0 = Enables connect events on a downs t ream port to be treated as resume events to be

propagated upstream. As well as waking up the system from Sx.

1 = D ownstream connect events do not wake the system from Sx nor does it initiate a resume

on its upstream port.

RMH 1 Upstream Wake on Device Resume This bit governs the hub behavior when globally

suspended and the system is in Sx.

0 = Enables the port to be sensitive to device initiated resume events as system wake-up events.

i.e, the hub will initiate a resume on its upstream port and cause a wake from Sx when a

device resume occurs on an enabled DS port

1 = Device resume event is seen on a downstream port, the hub does not initiate a wake

upstream and does not cause a wake from Sx

RMH 1 Upstream Wake on OC Disable This bit governs the hub behavior when globally

suspended and the system is in Sx.

0 = E nables the port to be sensitive to over-current conditions as system wake-up events. i.e,

the hub will initiate a resume on its upstream port and cause a wake from Sx when an OC

condition occurs on an enabled DS port

1 = Over-current event does not initiate a wake upstream and does not cause a wake from Sx

RMH 1 Upstream Wake on Disconnect Disable This bit governs the hub behavior when

globally suspended and the system is in Sx

0 = Enables disconnect events on downstream port to be treated as resume events to be

propagated upstream. In this case, it is allowed to initiate a wake on its upstream port and

cause a system wake from Sx in response to a disconnect event on a downstream port

1 = Downstream disconnect events do not initiate a resume on its upstream port or cause a

resume from Sx.

RMH 1 Upstream Wake on Connect Enable This bit governs the hub behavior when globally

suspended and the system is in Sx.

0 = Enables connect events on a downs t ream port to be treated as resume events to be

propagated upstream. As well as waking up the system from Sx.

1 = D ownstream connect events do not wake the system from Sx nor does it initiate a resume

on its upstream port.

Bit Description

PCI-to-PCI Bridge Registers (D30:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 365

Datasheet

11 PCI-to-PCI Bridge Registers

(D30:F0)

The PCH PCI bridge resides in PCI Device 30, Function 0 on bus #0. This implements

the buffering and control logic between PCI and the backbone. The arbitration for the

PCI bus is handled by this PCI device.

11.1 PCI Configuration Registers (D30:F0)

Note: Address locations that are not shown should be treated as Reserved (see Section 9.2

for details).

Table 11-1. PCI Bridge Register Address Map (PCI-PCI—D30:F0)

Offset Mnemonic Register Name Default Type

00h–01h VID Vendor Identification 8086h RO

02h–03h DID Device Identification See register

description RO

04h–05h PCICMD PCI Command 0000h R/W, RO

06h–07h PSTS PCI Status 0010h R/WC, RO

08h RID Revision Identification See register

description RO

09h–0Bh CC Class Code 060401h RO

0Dh PMLT Primary Master Latency Timer 00h RO

0Eh HEADTYP Header Type 01h RO

18h–1Ah BNUM Bus Number 000000h RO

1Bh SMLT Secondary Master Latency Timer 00h R/W

1Ch–1Dh IOBASE_LIMIT I/O Base and Limit 0000h R/W, RO

1Eh–1Fh SECSTS Secondary Status 0280h R/WC, RO

20h–23h MEMBASE_LIMIT Memory Base and Limit 00000000h R/W

24h–27h PREF_MEM_BASE_LIMIT Prefetchable Memory Base and Limit 00010001h R/W, RO

28h–2Bh PMBU32 Prefetchable Memory Upper 32 Bits 00000000h R/W

2Ch–2Fh PMLU32 Prefetchable Memory Limit Upper 32 Bits 00000000h R/W

34h CAPP Capability List Pointer 50h RO

3Ch–3Dh INTR Interrupt Information 0000h R/W, RO

3Eh–3Fh BCTRL Bridge Control 0000h R/WC, RO,

R/W

40h–41h SPDH Secondary PCI Device Hiding 0000h R/W, RO

44h–47h DTC Delayed Transaction Control 00000000h R/W

48h–4Bh BPS Bridge Proprietary Status 00000000h R/WC, RO

4Ch–4Fh BPC Bridge Policy Configuration 00001200h R/W RO

50–51h SVCAP Subsystem Vendor Capability Pointer 000Dh RO

54h–57h SVID Subsystem Vendor IDs 00000000 R/WO

PCI-to-PCI Bridge Registers (D30:F0)

366 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

11.1.1 VID—Vendor Identification Register (PCI-PCI—D30:F0)

Offset Address: 00h–01h Attribute: RO

Default Value: 8086h Size: 16 bits

11.1.2 DID—Device Identification Register (PCI-PCI—D30:F0)

Offset Address: 02h–03h Attribute: RO

Default Value: See bit description Size: 16 bits

11.1.3 PCICMD—PCI Command (PCI-PCI—D30:F0)

Offset Address: 04h–05h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value a ssigned to Intel. Intel VID = 8086h.

Bit Description

15:0 Device ID — RO. This is a 16-bit value assigned to the PCI bridge. Refer to the Intel® C600

Series Chipset Specification Update for the value of the Device ID Register.

Bit Description

15:11 Reserved

10 Interrupt Disable (ID) — RO. Hardwired to 0. The PCI bridge has no interrupts to disable

9Fast Back to Back Enable (FBE) — RO. Hardwired to 0, per the PCI Express* Base Specification,

Revision 1.0a.

SERR# Enable (SERR_EN) — R/W.

0 = Disable.

1 = Enable the PCH to gener ate an NMI (or SMI# if NMI routed to SMI#) when the D30:F0 SSE bit

(offset 06h, bit 14) is set.

7Wait Cycle Control (WCC) — RO. Hardwired to 0, per the PCI Express* Base Specification, Revision

1.0a.

Parity Error Response (PER) — R/W.

0 = The PCH ignores parity errors on the PCI bridge.

1 = The PCH will set the SSE bit (D30:F0, offset 06h, bit 14) when parity errors are detected on the

PCI bridge.

5VGA Palette Snoop (VPS) — RO. Hardwired to 0, per the PCI Express* Base Specification, Revision

1.0a.

4Memory Write and Invalidate Enable (MWE) — RO. Hardwired to 0, per the PCI Express* Base

Specification, Revision 1.0a

3Special Cycle Enable (SCE) — RO. Hardwired to 0, per the PCI Express* Base Specification, Revision

1.0a and the PCI- to-PCI Bridge Specification.

2Bus Master Enable (BME) — R/W.

0 = Disable

1 = Enable. Allows the PCI-to-PCI bridge to accept cycles from PCI.

Memory Space Enable (MSE) — R/W. Controls the response as a target for memory cycles

targeting PCI.

0 = Disable

1 = Enable

0I/O Space Enable (IOSE) — R/W. Controls the response as a target for I/O cycles targeting PCI.

0 = Disable

1 = Enable

PCI-to-PCI Bridge Registers (D30:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 367

Datasheet

11.1.4 PSTS—PCI Status Register (PCI-PCI—D30:F0)

Offset Address: 06h–07h Attribute: R/WC, RO

Default Value: 0010h Size: 16 bits

Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to

the bit has no effect.

Bit Description

Detected Parity Error (DPE) — R/WC.

0 = Parity error Not detected.

1 = Indicates that the PCH detected a parity error on the internal backbone. This bit gets set even if

the Parity Error Response bit (D30:F0:04 bit 6) is not set.

Signaled System Error (SSE) — R/WC. Several internal and external sources of the bridge can

cause SERR#. The first class of errors is parity errors related to the backbone. The PCI bridge

captures generic data parity errors (errors it finds on the backbone) as well as errors returned on

backbone cycles where the bridge was the master. If either of these two conditions is met, and the

primary side of the bridge is enabled for parity error response, SERR# will be captured as shown

below.

As with the backbone , the PCI bus cap tures the same sets of e rrors. The PCI b ridge captures gene ric

data parity errors (errors it finds on PCI) as well as errors returned on PCI cycles where the bridge

was the master. If either of these two conditions is met, and the secondary side of the bridge is

enabled for parity error response, SERR# will be captured as shown below.

The final class of errors is sys tem bus errors. Ther e are three status bits associated with system bus

errors, each with a corresponding enable. The diagram capturing this is shown below.

After checking for the three above classes of errors, an SERR# is gene r ated, and P STS .S SE logs th e

generation of SERR#, if CMD.SEE (D30:F0:04, bit 8) is set, as shown below.

13 Received Master Abort (RMA) — R/WC.

0 = No master abort received.

1 = Set when the bridge receives a master abort status from the backbone.

PCI-to-PCI Bridge Registers (D30:F0)

368 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

11.1.5 RID—Revision Identification Register (PCI-PCI—D30:F0)

Offset Address: 08h Attribute: RO

Default Value: See bit description Size: 8 bits

11.1.6 CC—Class Code Register (PCI-PCI—D30:F0)

Offset Address: 09h-0Bh Attribute: RO

Default Value: 060401h Size: 24 bits

11.1.7 PMLT—Primary Master Latency Timer Register

(PCI-PCI—D30:F0)

Offset Address: 0Dh Attribute: RO

Default Value: 00h Size: 8 bits

12 Received Target Abort (RTA) — R/WC.

0 = No target ab ort received.

1 = Set when the bridge receives a target abort status from the backbone.

11 Signaled Target Abort (STA) — R/WC.

0 = No signaled target abort

1 = Set when the bridge ge nerates a completion packet with target abort status on the backbone.

10:9 Reserved.

Data Parity Error Detected (DPD) — R/WC.

0 = Data parity error Not detected.

1 = Set when the bridge receives a completion packet from the backbone from a previous request,

and detects a parity error, and CMD.PERE is set (D30:F0:04 bit 6).

7:5 Reserved.

4Capabilities List (CLIST) — RO. Hardwired to 1. Capability list exist on the PCI bridge.

3Interrupt Status (IS) — RO. Hardwire d to 0. The PCI bridge do es not generate interrupts.

2:0 Reserved

Bit Description

7:0 Revision ID — RO. Refer to the Intel® C600 Series Chipset and Intel® X79 Express Chipset

Specification Update for the value of the Revision ID Register

Bit Description

23:16 Base Class Code (BCC) — RO. Hardwired to 06h. Indicates this is a bridge device.

15:8 Sub Class Code (SCC) — RO. Hardwired to 04h. Indicates this device is a PCI-to-PCI bridge.

7:0 Programming Interface (PI) — RO. Hardwired to 01h. Indicates the bridge is subtractive decode

Bit Description

7:3 Master Latency Timer Count (MLTC) — RO. Reserved per the PCI Express* Base Specification,

Revision 1.0a.

2:0 Reserved

PCI-to-PCI Bridge Registers (D30:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 369

Datasheet

11.1.8 HEADTYP—Header Type Register (PCI-PCI—D30:F0)

Offset Address: 0Eh Attribute: RO

Default Value: 01h Size: 8 bits

11.1.9 BNUM—Bus Number Register (PCI-PCI—D30:F0)

Offset Address: 18h-1Ah Attribute: R/W

Default Value: 000000h Size: 24 bits

11.1.10 SMLT—Secondary Master Latency Timer Register

(PCI-PCI—D30:F0)

Offset Address: 1Bh Attribute: R/W

Default Value: 00h Size: 8 bits

This timer controls the amount of time the PCH PCI-to-PCI bridge will burst data on its

secondary interface. The counter starts counting down from the assertion of FRAME#.

If the grant is remov ed, then the expiration of this counter will result in the deassertion

of FRAME#. If the grant has not been removed, then the PCH PCI-to-PCI bridge may

continue ownership of the bus.

Bit Description

7Multi-Function Device (MFD) — RO. ‘0’ indicates a single function device

6:0 Header Type (HTYPE) — RO. This 7-bi t field identifies the header layout of the configuration

space, which is a PCI-to-PCI bridge in this case.

Bit Description

23:16 Subordinate Bus Number (SBBN) — R/W. Indicates the highest PCI bus number below the

bridge.

15:8 Secondary Bus Number (SCBN) — R/W. Indicates the bus number of PCI.

7:0

Primary Bus Number (PBN) — R/W. This field is default to 00h. In a multiple-PCH system,

programmable PBN allows an PCH to be located on any bus. System configuration software is

responsible for initializing these registers to appropriate values. PBN is not used by hardware in

determining its bus number.

Bit Description

7:3 Master Latency Timer Count (MLTC) — R/W. This 5-bit field indicates the number of PCI clocks,

in 8-clock increments, that the PCH remains as master of the bus.

2:0 Reserved

PCI-to-PCI Bridge Registers (D30:F0)

370 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

11.1.11 IOBASE_LIMIT—I/O Base and Limit Register

(PCI-PCI—D30:F0)

Offset Address: 1Ch-1Dh Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

11.1.12 SECSTS—Secondary Status Register (PCI-PCI—D30:F0)

Offset Address: 1Eh–1Fh Attribute: R/WC, RO

Default Value: 0280h Size: 16 bits

Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to

the bit has no effect.

Bit Description

15:12 I/O Limit Address Limit bits[15:12] — R/W. I/O Base bits corresponding to address lines 15:12

for 4-KB alignment. Bits 11:0 are assumed to be padded to FFFh.

11:8 I/O Limit Address Capability (IOLC) — RO. Indicates that the bridge does not support 32-bit

I/O addressing.

7:4 I/O Base Address (IOBA) — R/W. I/O Base bits corresponding to address lines 15:12 for 4-KB

alignment. Bits 11:0 are assumed to be padded to 000h.

3:0 I/O Base Address Capability (IOBC) — RO. Indicates that the bridge does not support 32-bit

I/O addressing.

Bit Description

15 Detected Parity Error (DPE) — R/WC.

0 = Parity error not detected.

1 = PCH PCI bridge detected an address or data parity error on the PCI bus

14 Received System Error (RSE) — R/WC.

0 = SERR# assertion not received

1 = SERR# assertion is received on PCI.

Received Master Abort (RMA) — R/WC.

0 = No master abort.

1 = This bit is set whenever the bridge is acting as an initiator on the PCI bus and the cycle is

master- abo rted . For Processor/PCH interface pack e ts that have completio n re quired, this must

also cause a target abort to be returned and sets PSTS.STA. (D30:F0:06 bit 11)

Received Target Abort (RTA) — R/WC.

0 = No target abort.

1 = This bit is set whenever the bridge is act ing as an initiator on PCI and a cycle is target -aborted

on PCI. For Processor/PCH interface packets that have completion required, this event must

also cause a target abort to be returned, and sets PSTS.STA. (D30:F0:06 bit 11).

11 Signaled Target Abort (STA) — R/WC.

0 = No target abort.

1 = This bit is set when the bridge is acting as a target on the PCI Bus and signals a target abort.

10:9 DEVSEL# Timing (DEVT) — RO.

01h = Medium decode timing.

Data Parity Error Detected (DPD) — R/WC.

0 = Conditions described below not met.

1 = The PCH sets this bit when all of the following three conditions are met:

• The bridge is the initiator on PCI.

• PERR# is detected asserted or a parity error is detected internally

• BCTRL.PERE (D30:F0:3E bit 0) is set.

7F ast Back to Back Capab le (FBC) — RO. Hardwired to 1 to indicate that the PCI to PCI target logic is

capable of receiving fast back-to-back cycles.

6 Reserved

5 66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0. This bridge is 33 MHz capable only.

4:0 Reserved

PCI-to-PCI Bridge Registers (D30:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 371

Datasheet

11.1.13 MEMBASE_LIMIT—Memory Base and Limit Register

(PCI-PCI—D30:F0)

Offset Address: 20h–23h Attribute: R/W

Default Value: 00000000h Size: 32 bits

This register defines the base and limit, aligned to a 1-MB boundary, of the non-

prefetchable memory area of the bridge. Accesses that are within the ranges specified

in this register will be sent to PCI if CMD.MSE is set. Accesses from PCI that are outside

the ranges specified will be accepted by the bridge if CMD.BME is set.

11.1.14 PREF_MEM_BASE_LIMIT—Prefetchable Memory Base

and Limit Register (PCI-PCI—D30:F0)

Offset Address: 24h–27h Attribute: R/W, RO

Default Value: 00010001h Size: 32-bit

Defines the base and limit, aligned to a 1-MB boundary, of the prefetchable memory

area of the bridge. Accesses that are within the ra nges specified in this register will be

sent to PCI if CMD.MSE is set. Accesses from PCI that are outside the ranges specified

will be accepted by the bridge if CMD.BME is set.

11.1.15 PMBU32—Prefetchable Memory Base Upper 32 Bits

Offset Address: 28h–2Bh A ttribute: R/W

Default Value: 00000000h Size: 32 bits

Bit Description

31:20 Memory Limit (ML) — R/W. These bits are compared with bits 31:20 of the incoming address to

determine the upper 1-MB aligned value (exclusive) of the range. The incoming address mu st be

less than this value.

19:16 Reserved

15:4 Memory Base (MB) — R/W. These bits are compared with bits 31:20 of the incoming address to

determine the lower 1-MB aligned value (inclusive) of the range. The incoming address must be

greater than or equal to this value.

3:0 Reserved

Bit Description

31:20 Prefetchable Memory Limit (PML) — R/W. These bits are compared with bits 31:20 of the

incoming address to determine the upper 1-MB aligned value (exclus ive) of the r ange. The incomin g

address must be less than this value.

19:16 64-bit Indicator (I64L) — RO. Indicates support for 64-bit addressing.

15:4 Prefetchable Memory Base (PMB) — R/W. These bits are compared with bits 31:20 of the

incoming address to determine the lower 1-MB aligned value (inclusiv e) of the range. The incoming

address must be grea ter than or equal to this value.

3:0 6 4-bit Indicator (I64B) — RO. Indicates support for 64-bit addressing.

Bit Description

31:0 Prefetchable Memory Base Upper Portion (PMBU) — R/W. Upper 32-bits of the prefetchable

address base.

PCI-to-PCI Bridge Registers (D30:F0)

372 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

11.1.16 PMLU32—Prefetchable Memory Limit Upper 32 Bits

Offset Address: 2C–2Fh Attribute: R/W

Default Value: 00000000h Size: 32 bits

11.1.17 CAPP—Capability List Pointer Register (PCI-PCI—D30:F0)

Offset Address: 34h Attribute: RO

Default Value: 50h Size: 8 bits

11.1.18 INTR—Interrupt Information Register (PCI-PCI—D30:F0)

Offset Address: 3Ch–3Dh Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

11.1.19 BCTRL—Bridge Control Register (PCI-PCI—D30:F0)

Offset Address: 3Eh–3Fh Attribute: R/WC, RO, R/W

Default Value: 0000h Size: 16 bits

Bit Description

31:0 Prefetchable Memory Limit Upper Portion (PMLU) — R/W. Upper 32-b its of the prefetchable

address limit.

Bit Description

7:0 Capabilities Pointer (PTR) — RO. Indicates that the pointer for the first entry in the capabilities

list is at 50h in configuration space.

Bit Description

15:8 Interrupt Pin (IPIN) — RO. The PCI bridge does not assert an interrupt.

7:0 Interrupt Line (ILINE) — R/W. Software written value to indicate which interru pt line (vector) the

interrupt is connected to. No hardware action is taken on this register. Since the bridge does not

generate an interrupt, BIOS should program this value to FFh as per the PCI bridge specification.

Bit Description

15:12 Reserved

Discard Timer SERR# Enable (DTE) — R/W. Controls the generation of SERR# on the primary

interface in response to the DTS bit being set:

0 = Do not generate SERR# on a secondary timer discard

1 = Generate SERR# in response to a secondary timer discard

10 Discard Timer Status (DTS) — R/WC. This bit is set to 1 when the secondary discard timer (see

the SDT bit below) expires for a delayed transaction in the hard state.

Secondary Discard Timer (SDT) — R/W. This bit sets the maximum number of PCI clock cycles

that the PCH waits for an initiator on PCI to repeat a delayed trans action request. The counter starts

once the delayed transaction data is has been returned by the system and is in a buffer in the PCH

PCI bridge. If the maste r has not repeated the transaction at least once before the c ounte r exp ire s,

the PCH PCI bridge discards the transaction from its queue.

0 = The PCI master timeout value is between 215 and 216 PCI clocks

1 = The PCI master timeout value is between 210 and 211 PCI clocks

8Primary Discard Timer (PDT) — R/W. This bit is R/W for software compatibility only.

7Fast Back to Back Enable (FBE) — RO. Hardwired to 0. The PCI logic will not generate fast back-

to-back cycles on the PCI bus.

PCI-to-PCI Bridge Registers (D30:F0)

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Datasheet

Secondary Bus Reset (SBR) — R/W. Controls PCIRST# assertion on PCI.

0 = Bridge deasserts PCIRST#

1 = Bridge asserts PCIRST#. When PCIRST# is asserted, the delayed transaction buffers, posting

buffers, and the PCI bus are initialized back to reset conditions. The rest of the part and the

configuration registers are not affected.

Master Abort Mode (MAM) — R/W. Controls the PCH PCI bridge’s behavior when a master abort

occurs:

Master Abort on Processor /PCH Interconnect (DMI):

0 = Bridge asserts TRDY# on PCI. It drives all 1s for reads, and discards data on writes.

1 = Bridge returns a target abort on PCI.

Master Abort PCI (non-locked cycles):

0 = Normal completion status will be returned on the Processor/PCH interconnect.

1 = Target abort completion status will be returned on the Processor/PCH interconnect.

Note: All locked reads will return a completer abort completion status on the Processor/PCH

interconnect.

4VGA 16-Bit Decode (V16D) — R/W. Enables the PCH PCI brid ge to provide 16-bits decoding of

VGA I/O address precluding the decode of VGA alias addresses every 1 KB. This bit requires the

VGAE bit in this register be set.

VGA Enable (VGAE) — R/W. When set to a 1, the PCH PCI bridge forwards the following

transactions to PCI regardless of the value of the I/O base and limit registers. The transactions are

qualified by CMD.MSE (D30:F0:04 bit 1) and CMD.IOSE (D30:F0:04 bit 0) being set.

• Memory addresses: 000A0000h-000BFFFFh

• I/O addresses: 3B0h-3BBh and 3C0h-3DFh. For the I/O addresses, bits [63:16] of the address

must be 0, and bits [15:10] of the address are ignored (that is, aliased).

The same hold s true from s econd ary acce sses to th e pr imary in ter face in rev erse. That is, when the

bit is 0, memory and I/O addresses on the secondary interface between the above ranges will be

claimed.

ISA Enable (IE) — R/W. This bit only applies to I/O addresses that are enabled by the I/O Base

and I/O Limit registers and are in the first 64 KB of PCI I/O space. If this bit is set, the PCH PCI

bridge will block any forwarding from primary to secondary of I/O transactions addressing the last

768 bytes in each 1-KB block (offsets 100h to 3FFh).

SERR# Enable (SEE) — R/W. Controls the forwar din g o f se co ndar y inte rfac e SERR# assertions on

the primary interface. When set, the PCI bridge will forward SERR# pin.

• SERR# is asserted on the secondary interface.

• This bit is set.

• CMD.SEE (D30:F0:04 bit 8) is set.

0Parity Error Response Enable (PERE) — R/W.

0 = D isable

1 = The PCH PCI bridge is enable d fo r par i ty erro r re por ting base d o n parity errors on the PCI bus.

Bit Description

PCI-to-PCI Bridge Registers (D30:F0)

374 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

11.1.20 SPDH—Secondary PCI Device Hiding Register

(PCI-PCI—D30:F0)

Offset Address: 40h–41h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

This register allows software to hide the PCI devices, either plugged into slots or on the

motherboard.

11.1.21 DTC—Delayed Transaction Control Register

(PCI-PCI—D30:F0)

Offset Address: 44h–47h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Bit Description

15:4 Reserved

3Hide Device 3 (HD3) — R/W, RO. Same as bit 0 of this register, except for device 3 (AD[19])

2Hide Device 2 (HD2) — R/W, RO. Same as bit 0 of this register, except for device 2 (AD[18])

1Hide Device 1 (HD1) — R/W, RO. Same as bit 0 of this register, except for device 1 (AD[17])

Hide Device 0 (HD0) — R/W, RO.

0 = The PCI configuration cycles for this slot are not affected.

1 = The PCH hides de vice 0 on the PC I bus. T his is done b y masking the IDSEL (k eeping it low) for

configuration cycles to that device. Since the device will not see its IDSEL go active, it will not

respond to PCI configuration cycles and the processor will think the device is not present.

AD[16] is used as IDSEL for device 0.

Bit Description

Discard Delayed Transactions (DDT) — R/W.

0 = Logged delayed transaction s are kept.

1 = The PCH PCI bridge will discard any delayed transactions it has logged. This includes

transactions in the pending queue, and any transactions in the active queue, whether in the

hard or soft DT state. The prefetchers will be disabled and return to an idle state.

Note: If a transaction is running on PCI at the time this bit is set, that transaction will continue

until either the PCI master disconnects (by deasserting FRAME#) or the PCI bridge

disconnects (by asserting STOP#). This bit is cleared by the PCI bridge when the delayed

transacti on que ues are empty an d ha ve ret urned to an idle state. Software sets this bit and

polls for its completion

Block Delayed Transactions (BDT) — R/W.

0 = Delayed transactions accepted

1 = The PCH PCI bridge will not accept incoming transactions which will result in delayed

transactions. It will blindly retry these cycles by asserting STOP#. All postable cycles (memory

writes) will still be accepted.

29:8 Reserved

7:6

Maximum Delayed Transactions (MDT) — R/W. Controls the maximum number of delayed

transactions that the PCH PCI bridge will run. Encodings are:

00 =) 2 Active, 5 pending

01 =) 2 active, no pending

10 =) 1 active, no pending

11 =) Reserved

5 Reserved

Auto Flush After Disconnect Enable (AFADE) — R/W.

0 = The PCI bridge will retain any fetched data until required to discard by producer/consumer

rules.

1 = The PCI bridge will flush any prefetched data after either the PCI master (by deasserting

FRAME#) or the PCI bridge (by asserting STOP#) disconnects the PCI transfer.

PCI-to-PCI Bridge Registers (D30:F0)

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11.1.22 BPS—Bridge Proprietary Status Register

(PCI-PCI—D30:F0)

Offset Address: 48h–4Bh Attribute: R/WC, RO

Default Value: 00000000h Size: 32 bits

Never Prefetch (NP) — R/W.

0 = Prefe tch enabled

1 = The PCH will only fetch a single DW and will not enable prefetching, regardless of the command

being an Memory read (MR), Memory read line (MRL), or Memory read multiple (MRM).

Memory Read Multiple Prefetch Disable (MRMPD) — R/W.

0 = MRM commands will fetch multiple cache lines as defined by th e prefetch alg or i thm.

1 = Memory read multiple (MRM) commands will fetch only up to a single, 64-byte aligned cache

line.

1Memory Read Line Prefetch Disable (MRLPD) — R/W.

0 = MRL commands will fetch multiple cache lines as defined by the prefetch algorithm.

1 = Memory read line (MRL) commands will fetch only up to a single, 64-byte aligned cache line.

0Memory Read Prefetch Disable (MRPD) — R/W.

0 = MR commands will fetch up to a 64-byte aligned cache line.

1 = Memory read (MR) commands will fetch only a single DW.

Bit Description

31:17 Reserved

PERR# Assertion Detected (PAD) — R/WC. This bit is set by hardware whenever the PERR# pin

is asserted on the rising edge of PCI clock. T his includes cases in which the chipset is the agent

driving PERR#. It remains asserted until cleared by software writing a 1 to this location. When

enabled by the PERR#-to-SERR# Enable bit (in the Bridge Policy Configuration register), a 1 in this

bit can generate an internal SERR# and be a source for the NMI logic.

This bit can be used by software to determine the source of a system problem.

15:7 Reserved

6:4

Number of Pending Transactions (NPT) — RO. This read-only indicator tells debug softw are how

many transactions are in the pending queue. Possible values are:

000 = No pending transaction

001 = 1 pending transaction

010 = 2 pending transactions

011 = 3 pending transactions

100 = 4 pending transactions

101 = 5 pending transactions

110–111 = Reserved

Note: This field is not valid if DTC.MDT (offset 44h:bits 7:6) is any value other than ‘00’.

3:2 Reserved

1:0

Number of Active Transactions (NAT) — RO. This read-only indicator tells debug software how

many transactions are in the active queue. Possible values are:

00 = No active transactions

01 = 1 active transaction

10 = 2 active transactions

11 = Reserved

PCI-to-PCI Bridge Registers (D30:F0)

376 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

11.1.23 BPC—Bridge Policy Configuration Register

(PCI-PCI—D30:F0)

Offset Address: 4Ch–4Fh Attribute: R/W

Default Value: 00001200h Size: 32 bits

Bit Description

31:30 Reserved

Subtractive Decode Compatibility Device ID (SDCDID) — R/W: When '0', this function shall

report a Device ID of 244Eh. When set to '1', this function shall report the device Device ID value

assigned to the PCI-to-PCI Bridge in the Intel® C600 Series Chipset and Intel® X79 Express Chipset

Specification Update.

If subtractive decode (SDE) is en abled, having this bit as '0' allo ws the functio n t o present a Dev ice

ID that is recognized by the OS.

Subtractive Decode Enable (SDE) — R/W:

0 = Subtractive decode is disabled this function and will only claim transactions positively.

1 = The subtractive decode policy as listed in SDP below applies.

Software must ensure that only one PCH device is enabled for Subtractive decode at a time.

27:14 Reserved

13:8

Upstream Read Latency Threshold (URLT) — R/W: This field specifies the number of PCI clocks

after internally enqueuing an upstream memory read request at which point the PCI target logic

should insert wait states in order to optimize lead-off latency. When the master returns after this

threshold has been reached and data has not arrived in the Delayed Transaction completion queue,

then the PCI target logic will insert wait states instead of immediately retrying the cycle. The PCI

target logic will insert up to 16 clocks of target initial latency (from FRAME# assertion to TRDY# or

STOP# assertion) before retrying the PCI read cycle (if the read data has not arrived yet).

Note that the starting event for this Read Latency Timer is not explicitly visible externally.

A value of 0h disables this policy completely such that wait states will never be inserted on the read

lead-off data phase.

The default value (12h) specifies 18 PCI clocks (540 ns) and is appro ximately 4 clo cks less than the

typical idle lead-off latency expected for desktop PCH systems. T his value may need to be changed

by BIOS, depending on the platform.

Subtractive Decode Policy (SDP) — R/W.

0 = The PCI bridge always forwards memory and I/O cycles that are not claimed by any other

device on the backbone (primary interface) to the PCI bus (secondary interface).

1 = The PCI bridge will not claim and forward memory or I/O cy cles at all unless the c orresponding

Space Enable bit is set in the Command register.

Note: The Boot BIOS Destination Selection strap can force the BIOS accesses to PCI.

PERR#-to-SERR# Enable (PSE) — R/W. When this bit is set, a 1 in the PERR# Assertion status

bit (in the Bridge Proprietary Status register) will result in an internal SERR# assertion on the

primary side of the bridge (if also enabled by the SERR# Enable bit in the primary Command

5Secondary Discard Timer Testmode (SDTT) — R/W.

0 = The secondary discard timer expiration will be defined in BCTRL.SDT (D30:F0:3E, bit 9)

1 = The secondary discard timer will expire after 128 PCI clocks.

4:3 Reserved

Peer Decode Enable (PDE) — R/W.

0 = The PCI bridge assumes that all memory cyc les tar get main memory, and all I/O cycles are not

claimed.

1 = The PCI bridge will perform peer decode on any memory or I/O cycle from PCI that falls outside

of the memory and I/O window registers

1 Reserved

0Received Target Abort SERR# Enable (RTAE) — R/W. When set, the PCI bridge will report

SERR# when PSTS.RTA (D30:F0:06 bit 12) or SSTS.RTA (D30:F0:1E bit 12) are set, and CMD.SEE

(D30:F0:04 bit 8) is set.

CMD.MSE BPC.SDP Range Forwarding Policy

0 0 Don’t Care Forward unclaimed cycles

0 1 Don’t Care Forwarding Prohibited

1 X Within range Positive decode and forward

1 X Outside Subtractive decode & forward

PCI-to-PCI Bridge Registers (D30:F0)

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Datasheet

11.1.24 SVCAP—Subsystem Vendor Capability Register

(PCI-PCI—D30:F0)

Offset Address: 50h–51h Attribute: RO

Default Value: 000Dh Size: 16 bits

11.1.25 SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0)

Offset Address: 54h–57h Attribute: R/WO

Default Value: 00000000h Size: 32 bits

Bit Description

15:8 Next Capability (NEXT) — RO. Value of 00h indicates this is the last item in the list.

7:0 Capability Identifier (CID) — RO. Value of 0Dh indicates this is a PCI bridge subsystem vendor

capability.

Bit Description

31:16 Subsystem Identifier (SID) — R/WO. Indicates the subsystem as identified by the vendor. This

field is write once and is locked down until a bridge reset occurs (not the PCI bus reset).

15:0 Subsystem Vendor Identifier (SVID) — R/WO. Indicates the manufacturer of the subsystem.

This field is write once and is locked down until a bridge reset occurs (not the PCI bus reset).

PCI-to-PCI Bridge Registers (D30:F0)

378 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Gigabit LAN Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 379

Datasheet

12 Gigabit LAN Configuration

Registers

12.1 Gigabit LAN Configuration Registers

(Gigabit LAN — D25:F0)

Note: Refer to the Intel 82579 datasheet for additional LAN Configuration Status Register

information.

Note: Register address locations that are not shown in Table 12-1 should be treated as

Reserved.

Table 12-1. Gigabit LAN Configuration Registers Address Map

(Gigabit LAN —D25:F0) (Sheet 1 of 2)

Offset Mnemonic Register Name Default Type

00h–01h VID Vendor Identification 8086h RO

02h–03h DID Device Identification See register

description RO

04h–05h PCICMD PCI Command 0000h R/W, RO

06h–07h PCISTS PCI Status 0010h R/WC, RO

08h RID Revision Identification See register

description RO

09h–0Bh CC Class Code 020000h RO

0Ch CLS Cache Line Size 00h R/W

0Dh PLT Primary Latency Timer 00h RO

0Eh HEADTYP Header Type 00h RO

10h–13h MBARA Memory Base Address A 00000000h R/W, RO

14h–17h MBARB Memory Base Address B 00000000h R/W, RO

18h–1Bh MBARC Memory Base Address C 00000001h R/W, RO

2Ch–2Dh SVID Subsystem Vendor ID See register

description RO

2Eh–2Fh SID Subsystem ID See register

description RO

30h–33h ERBA Expansion ROM Base Address See register

description RO

34h C AP P Capabilities List Pointer C8h RO

3Ch–3Dh INTR Interrupt Information See register

description R/W, RO

3Eh MLMG Maximum Latency/Minimum Grant 00h RO

C8h–C9h CLIST1 Capabilities List 1 D001h RO

CAh–CBh PMC PCI Power Management Capability See register

description RO

CCh–CDh PMCS PCI Power Management Control and

Status See register

description R/WC, R/W,

CFh DR Data Register See register

description RO

D0h–D1h CLIST2 Capabilities List 2 E005h R/WO, RO

Gigabit LAN Configuration Registers

380 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

12.1.1 VID—Vendor Identification Register

(Gigabit LAN—D25:F0)

Address Offset: 00h–01h Attribute: RO

Default Value: 8086h Size: 16 bits

12.1.2 DID—Device Identification Register

(Gigabit LAN—D25:F0)

Address Offset: 02h–03h Attribute: RO

Default Value: See bit description Size: 16 bits

D2h–D3h MCTL Message Control 0080h R/W, RO

D4h–D7h MADDL Message Address Low S ee register

description R/W

D8h–DBh MADDH Message Address High See register

description R/W

DCh–DDh MDAT Message Data See register

description R/W

E0h–E1h FLRCAP Function Level Reset Capability 0009h RO

E2h–E3h FLRCLV Function Level Reset Capability Length

and Value See r egister

description R/WO, RO

E4h–E5h D EVCTRL Device Control 0000h R/W, RO

Table 12-1. Gigabit LAN Configuration Registers Address Map

(Gigabit LAN —D25:F0) (Sheet 2 of 2)

Offset Mnemonic Register Name Default Type

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. The field may be auto-loaded from the

NVM at address 0Dh during init time depending on the "Load Vendor/Device ID" bit field in NVM

word 0Ah with a default value of 8086h.

Bit Description

15:0 Device ID — RO. This is a 16-bit value assigned to the P CH Gigabit LAN contr oller. The field may be

auto-loaded from the NVM word 0Dh during initialization time depending on the "Load Vendor/

Device ID" bit field in NVM word 0Ah.

Gigabit LAN Configuration Registers

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Datasheet

12.1.3 PCICMD—PCI Command Register

(Gigabit LAN—D25:F0)

Address Offset: 04h–05h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Bit Description

15:11 Reserved

Interrupt Disable — R/W. This disables pin-based INTx# interrupts on enabled Hot-Plug and

power management events. This bit has no effect on MSI operation.

0 = Internal INTx# messages are g enerated if there is an interrupt for Ho t-Plug or power

management and MSI is not enabled.

1 = Internal INTx# mess ages will not be generated.

This bit does not affect interrupt forwarding from devices connected to the root port. Assert_INTx

and Deassert_INTx messages will still be forwarded to the internal interrupt controllers if this bit is

set.

9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0.

8SERR# Enable (SEE) — R/W.

0 = D isable

1 = E nables the Gb LAN controller to generate an SERR# message when PSTS.SSE is set.

7 Wait Cycle Control (WCC) — RO. Hardwired to 0.

6Parity Error Response (PER) — R/W.

0 = Disable.

1 = Indicates that the device is capable of reporting parity errors as a master on the backbone.

5 Palette Snoop Enable (PSE) — RO. Hardwired to 0.

4 Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.

3 Special Cycle Enable (SCE) — RO. Hardwired to 0.

2Bus Master Enable (BME) — R/W.

0 = Disable. All cycles from the device are master aborted

1 = E nable. Allows the root port to forward cycles onto the backbone from a Gigabit LAN* device.

Memory Space Enable (MSE) — R/W.

0 = Disable. Memory cycles within the range specified by the memory base and limit registers are

master aborted on the backbone.

1 = Enable. Allows memory cycles within the range specified by the me mory base and limit

registers can b e forwarded to the Gigabit L AN device.

I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.

0 = Disable. I/O cycles within the range specified by the I/O base and limit registers are master

aborted on the backbone.

1 = Enable. Allows I/O cycles within the range specified by the I/O base and limit registers can be

forwarded to the Gigabit LAN device.

Gigabit LAN Configuration Registers

382 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

12.1.4 PCISTS—PCI Status Register

(Gigabit LAN—D25:F0)

Address Offset: 06h–07h Attribute: R/WC, RO

Default Value: 0010h Size: 16 bits

12.1.5 RID—Revision Identification Register

(Gigabit LAN—D25:F0)

Offset Address: 08h Attribute: RO

Default Value: See bit description Size: 8 bits

Bit Description

Detected Parity Error (DPE) — R/WC.

0 = No parity error detected.

1 = Set when the Gb LAN controller receives a command or data from the backbone with a parity

error. This is set even if PCIMD.PER (D25:F0, bit 6) is not set.

14 Signaled System Error (SSE) — R/WC.

0 = No system error signaled.

1 = Set when the Gb LAN controller signals a system error to the internal SERR# logic.

Received Master Abort (RMA) — R/WC.

0 = Root port has not received a completion with unsupported request status from the backbone.

1 = Set when the GbE LAN controller receives a completion with unsupported request status from

the bac kbone.

12 Received Target Abort (RTA) — R/WC.

0 = Root port has not received a completion with completer abort from the backbone.

1 = Set when the Gb LAN controller receives a co mpletion with completer abort from the backbone.

Signaled Target Abort (STA) — R/WC.

0 = No target abort received.

1 = Set whenever the Gb LAN controller forwards a target abort received from the downstream

device onto the backbone.

10:9 DEVSEL# Timing Status (DEV_STS) — RO. Hardwired to ‘0’.

Master Data Parity Error Detected (DPED) — R/WC.

0 = No data parity error received.

1 = Set when the Gb LAN Controller receives a completion with a data parity error on the backbon e

and PCIMD.PER (D25:F0, bit 6) is set.

7 Fast Back to Back Capable (FB2BC) — RO. Hardwired to ‘0’.

6 Reserved

5 66 MHz Capable — RO. Hardwired to 0.

4 Capabilities List — RO. Hardwired to 1. Indicates the presence of a capabilities list.

Interrupt Status — RO. Indicates status of Hot-Plu g and power management interrupts on the root

port that result in INTx# message generation.

0 = Interrupt is de-asserted .

1 = Interrupt is asserted.

This bit is not set if MSI is enabled. If MSI is not enabled, this bit is set regardless of the state of

PCICMD.Interrupt Disable bit (D25:F0:04h:bit 10).

2:0 Reserved

Bit Description

7:0 Revision ID — RO. Refer to the Intel® C600 Series Chipset and Intel® X79 Express Chipset

Specification Update for the value of the Revision ID Register

Gigabit LAN Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 383

Datasheet

12.1.6 CC—Class Code Register

(Gigabit LAN—D25:F0)

Address Offset: 09h–0Bh Attribute: RO

Default Value: 020000h Size: 24 bits

12.1.7 CLS—Cache Line Size Register

(Gigabit LAN—D25:F0)

Address Offset: 0Ch Attribute: R/W

Default Value: 00h Size: 8 bits

12.1.8 PLT—Primary Latency Timer Register

(Gigabit LAN—D25:F0)

Address Offset: 0Dh Attribute: RO

Default Value: 00h Size: 8 bits

12.1.9 HEADTYP—Header Type Register

(Gigabit LAN—D25:F0)

Address Offset: 0Eh Attribute: RO

Default Value: 00h Size: 8 bits

Bit Description

23:0 Class Code— RO. Identifies the device as an Ethernet Adapter.

020000h = Ethernet Adapter.

Bit Description

7:0 Cache Line Size — R/W. This field is implemented by PCI devices as a read write field for legacy

compatibility purposes but has no impact on any device functionality.

Bit Description

7:0 Latency Timer (LT) — RO. Hardwired to 0.

Bit Description

7:0 Header Type (HT) — RO.

00h = Indicates this is a single function device.

Gigabit LAN Configuration Registers

384 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

12.1.10 MBARA—Memory Base Address Register A

(Gigabit LAN—D25:F0)

Address Offset: 10h–13h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

The internal CSR registers and memories are accessed as direct memory mapped

offsets from the base address register. SW may only access whole DWord at a time.

12.1.11 MBARB—Memory Base Address Register B

(Gigabit LAN—D25:F0)

Address Offset: 14h–17h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

The internal registers that are used to access the LAN Space in the External FLASH

device. Access to these registers are direct memory mapped offsets from the base

address register. Software may only access a DWord at a time.

Bit Description

31:17 Base Address (BA) — R/W. Software programs this field with the base address of this region.

16:4 Memory Size (MSIZE) — R/W. Memory size is 128 KB.

3Prefetchable Memory (PM) — RO. The GbE LAN controller does not implement prefetchable

memory.

2:1 Memory Type (MT) — RO. Set to 00b indicating a 32 bit BAR.

0Memory / IO Space (MIOS) — RO. Set to 0 indicating a Memory Space BAR.

Bit Description

31:12 Base Address (BA) — R/W. Software programs this field with the base address of this region.

11:4 Memory Size (MSIZE) — R/W. Memory size is 4 KB.

3Prefetchable Memory (PM) — RO. The Gb LAN controller does not implement prefetchable

memory.

2:1 Memory Type (MT) — RO. Set to 00b indicating a 32 bit BAR.

0Memory / IO Space (MIOS) — RO. Set to 0 indicating a Memory Space BAR.

Gigabit LAN Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 385

Datasheet

12.1.12 MBARC—Memory Base Address Register C

(Gigabit LAN—D25:F0)

Address Offset: 18h–1Bh Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

Internal registers, and memories, can be accessed using I/O operations. There are two

4B registers in the I/O mapping window: Addr Reg and Data Reg. Software may only

access a DWord at a time.

12.1.13 SVID—Subsystem Vendor ID Register

(Gigabit LAN—D25:F0)

Address Offset: 2Ch–2Dh Attribute: RO

Default Value: See bit description Size: 16 bits

12.1.14 SID—Subsystem ID Register

(Gigabit LAN—D25:F0)

Address Offset: 2Eh–2Fh Attribute: RO

Default Value: See bit description Size: 16 bits

12.1.15 ERBA—Expansion ROM Base Address Register

(Gigabit LAN—D25:F0)

Address Offset: 30h–33h Attribute: RO

Default Value: See bit description Size: 32 bits

Bit Description

31:5 Base Address (BA) — R/W. Software programs this field with the base address of this region.

4:1 I/O Size (IOSIZE) — RO. I/O space size is 32 Bytes.

0Memory / I/O Space (MIOS) — RO. Set to 1 indicating an I/O Space BAR.

Bit Description

15:0

Subsystem Vendor ID (SVID) — RO. This value may be loaded automati cally from the NVM W ord

0Ch upon power up depending on the "Load Subsystem ID" bit field in NVM word 0Ah. A value of

8086h is default for this field upon power up if the NVM does not respond or is not progr ammed. All

functions are initialized to the same value.

Bit Description

15:0 Subsystem ID (SID) — RO . This val ue may be loaded automatically from the NVM W ord 0Bh up on

power up or reset depending on the “Load Subsystem ID” bit field in NVM word 0Ah with a default

value of 0000h. This value is loadable from NVM word location 0Ah.

Bit Description

31:0 Expansion ROM Base Address (ERBA) — RO. This register is used to define the address and size

information for boot-time access to the optional FLASH memory. If no Flash memory exists, this

Gigabit LAN Configuration Registers

386 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

12.1.16 CAPP—Capabilities List Pointer Register

(Gigabit LAN—D25:F0)

Address Offset: 34h Attribute: R0

Default Value: C8h Size: 8 bits

12.1.17 INTR—Interrupt Information Register

(Gigabit LAN—D25:F0)

Address Offset: 3Ch–3Dh Attribute: R/W, RO

Default Value: 0100h Size: 16 bits

Function Level Reset: No

12.1.18 MLMG—Maximum Latency/Minimum Grant Register

(Gigabit LAN—D25:F0)

Address Offset: 3Eh Attribute: RO

Default Value: 00h Size: 8 bits

12.1.19 CLIST 1—Capabilities List Register 1

(Gigabit LAN—D25:F0)

Address Offset: C8h–C9h Attribute: RO

Default Value: D001h Size: 16 bits

Bit Description

7:0 Capabilities Pointer (PTR) — RO. Indicates that the pointer for the first entry in the capabilities

list is at C8h in configuration space.

Bit Description

15:8 Interrupt Pin (IPIN) — RO. Indicates the interrupt pin driven by the GbE LAN controller.

01h = The GbE LAN controller implements legacy interrupts on INTA.

7:0 Interrupt Line (ILINE) — R/W. Default = 00h. Software written value to indicate which interrupt

line (vector) the interrupt is connected to. No hardware action is taken on this register.

Bit Description

7:0 Maximum Latency/Minimum Grant (MLMG) — RO. Not used. Hardwired to 00h.

Bit Description

15:8 Next Capability (NEXT) — RO. Value of D0h indicates the location of the next pointer.

7:0 Capability ID (CID) — RO. Indicates the linked list item is a PCI Power Management Register.

Gigabit LAN Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 387

Datasheet

12.1.20 PMC—PCI Power Management Capabilities Register

(Gigabit LAN—D25:F0)

Address Offset: CAh–CBh Attribute: RO

Default Value: See bit descriptions Size: 16 bits

Function Level Reset: No (Bits 15:11 only)

Bit Description

15:11

PME_Support (PMES) — RO. This five-bit field indicates the power states in which the function

may assert PME#. It depend on PM Ena and AUX-PWR bits in word 0Ah in the NVM:

These bits are not reset by Function Level Reset.

10 D2_Support (D2S) — RO. The D2 state is not supported.

9D1_Support (D1S) — RO. The D1 state is not supported .

8:6 Aux_Current (AC) — RO. Required current defined in the Data Register.

5Device Specific Initialization (DSI) — RO. Set to 1. The GbE LAN Controller requires its device

driver to be executed following transition to the D0 un-initialized state.

4 Reserved

3 PME Clock (PMEC) — RO. Hardwired to 0.

2:0 Version (VS) — RO. Hardwired to 010b to indicate support for Revision 1.1 of the PCI Power

Management Specification.

Condition Function Value

PM Ena=0 No PME at all states 0000b

PM Ena & AUX-PWR=0 PME at D0 and D3hot 01001b

PM Ena & AUX-PWR=1 PME at D0, D3hot and D3cold 11001b

Gigabit LAN Configuration Registers

388 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

12.1.21 PMCS—PCI Power Management Control and Status

Address Offset: CCh–CDh Attribute: R/WC, R/W, RO

Default Value: See bit description Size: 16 bits

Function Level Reset:No (Bit 8 only)

12.1.22 DR—Data Register

(Gigabit LAN—D25:F0)

Address Offset: CFh Attribute: RO

Default Value: See bit description Size: 8 bits

Bit Description

15 PME Status (PMES) — R/WC. This bit is set to 1 when the function detects a wake-up event

independent of the state of the PMEE bit. Writing a 1 will clear this bit.

14:13

Data Scale (DSC) — R/W. This field indicates the scaling factor to be used when interpreting the

value of the Data register.

For the GbE LAN and common functions this field equals 01b (indicating 0.1 watt units) if the PM is

enabled in the NVM, and the Data_Select field is set to 0, 3, 4, 7, (or 8 for Function 0). Else it e quals

00b.

For the manageability functions this field equals 10b (indicating 0.01 watt units) if the PM is enabled

in the NVM, and the Data_Select field is set to 0, 3, 4, 7. Else it equals 00b.

12:9

Data Select (DSL) — R/W. This four-bit field is used to select which data is to be reported through

the Data register (offset CFh) an d Data_Scale field. These bits are writeable only when the Power

Management is enabled using NVM.

0h = D0 Power Consumption

3h = D3 Power Consumption

4h = D0 Power Dissipation

7h = D3 Power Dissipation

8h = Common Power

All other values are reserved.

8PME Enable (PMEE) — R/W. If Power Management is enabled in the NVM, writing a 1 to this

no affect, and will not set the bit to 1. This bit is not reset by Function Level Reset.

7:4 Reserved - Returns a value of 0000.

3No Soft Reset (NSR) — RO. Defines if the device executed internal reset on the transition to D0.

the LAN controller always reports 0 in this field.

2 Reserved - Returns a value of 0b.

1:0

Power State (PS) — R/W. This field is used both to determine the current power state of the GbE

LAN Controller and to set a new power state. The values are:

00 = D0 state (default)

01 = Ignored

10 = Ignored

11 = D3 state (Power Management must be enables in the NVM or this cycle will be ignored).

Bit Description

7:0

Reported Data (RD) — RO. This register is used to report power consumption and heat

dissipation. This register is controlled by the Data_Select field in the PMCS (Offset CCh, bits 12:9),

and the power scale is reported in the Data_Scale field in the PMCS (Offset CCh, bits 14:13). The

data of this field is loaded from the NVM if PM is enabled in the NVM or with a default value of 00h

otherwise.

Gigabit LAN Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 389

Datasheet

12.1.23 CLIST 2—Capabilities List Register 2

(Gigabit LAN—D25:F0)

Address Offset: D0h–D1h Attribute: R/WO, RO

Default Value: E005h Size: 16 bits

Function Level Reset: No (Bits 15:8 only)

12.1.24 MCTL—Message Control Register

(Gigabit LAN—D25:F0)

Address Offset: D2h–D3h Attribute: R/W, RO

Default Value: 0080h Size: 16 bits

12.1.25 MADDL—Message Address Low Register

(Gigabit LAN—D25:F0)

Address Offset: D4h–D7h Attribute: R/W

Default Value: See bit description Size: 32 bits

12.1.26 MADDH—Message Address High Register

(Gigabit LAN—D25:F0)

Address Offset: D8h–DBh Attribute: R/W

Default Value: See bit description Size: 32 bits

Bit Description

15:8 Next Capability (NEXT) — R/WO. Value of E0h points to the Function Level Reset capability

structure.

These bits are not reset by Function Level Reset.

7:0 Capability ID (CID) — RO. Indicates the linked list item is a Message Signaled Interrupt Register.

Bit Description

15:8 Reserved

764-bit Capable (CID) — RO. Set to 1 to indicate that the GbE LAN Controller is capable of

generating 64-bit message addresses.

6:4 Multiple Message Enable (MME) — RO. Returns 000b to indicate that the GbE LAN contr oller only

supports a single message.

3:1 Multiple Message Capable (MMC) — RO. The GbE LAN controller does not support multiple

messages.

0MSI Enable (MSIE) — R/W.

0 = MSI generation is disabled.

1 = The Gb LAN controller will generate MSI for interrupt assertion instead of INTx signaling.

Bit Description

31:0 Message Address Low (MADDL) — R/W. Written by the system to indicate the lower 32 bits of

the address to use for the MSI memory write transaction. The lower two bits will always return 0

regardless of the write operation.

Bit Description

31:0 Message Address High (MADDH) — R/W. Written by the system to indicate the upper 32 bits of

the address to use for the MSI memory write transaction.

Gigabit LAN Configuration Registers

390 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

12.1.27 MDAT—Message Data Register

(Gigabit LAN—D25:F0)

Address Offset: DCh–DDh Attribute: R/W

Default Value: See bit description Size: 16 bits

12.1.28 FLRCAP—Function Level Reset Capability

(Gigabit LAN—D25:F0)

Address Offset: E0h–E1h Attribute: RO

Default Value: 0009h Size: 16 bits

12.1.29 FLRCLV—Function Level Reset Capability Length and

Version

(Gigabit LAN—D25:F0)

Address Offset: E2h–E3h Attribute: R/WO, RO

Default Value: See Description. Size: 16 bits

Function Level Reset: No (Bits 9:8 Only When FLRCSSEL = 0)

When FLRCSSEL = 0, this register is defined as follows:

When FLRCSSEL = 1, this register is defined as follows:

Bit Description

31:0 Message Data (MDAT) — R/W. Written by the system to indicate the lower 16 bits of the data

written in the MSI memory write DWORD transaction. The upper 16 bits of the transaction are

written as 0000h.

Bit Description

15:8 Next Pointer — RO. This field provides an offset to the next capability item in the capability list.

The value of 00h indicates the last item in the list.

7:0 Capability ID — RO. The value of this field depends on the FLRCSSEL bit.

13h = If FLRCSSEL = 0

09h = If FLRCSSEL = 1, indicating vendor specific capability.

Bit Description

15:10 Reserved.

9Function Level Reset Capability — R/WO.

1 = Support for Function Level Reset.

This bit is not reset by Function Level Reset.

8TXP Capability — R/WO.

1 = Indicates support for the Transactions Pending (TXP) bit. TXP must be supported if FLR is

supported.

7:0 Capability Length — RO. The value of this field indicates the number of bytes of the vendor

specific capability as require by the PCI spec. It has the value of 06h for the Function Level Reset

capability.

Bit Description

15:12 Vendor Specific Capability ID — RO. A value of 2h in this field identifies this capability as

Function Level Reset.

11:8 Capability Version— RO. The value of this field indicates the version of the Function Level Reset

Capability. Default is 0h.

7:0 Capability Length — RO. The value of this field indicates the number of bytes of the vendor

specific capability as require by the PCI spec. It has the value of 06h for the Function Level Reset

capability.

Gigabit LAN Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 391

Datasheet

12.1.30 1DEVCTRL—Device Control (Gigabit LAN—D25:F0)

Address Offset: E4-E5h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

12.2 Gigabit LAN Capabilities and Status Registers

(CSR)

The internal CSR registers and memories are accessed as direct memory mapped

offsets from the base address register in Section 12.1.10. Software may only access

whole DWord at a time.

Note: Register address locations that are not shown in Table 12-2 should be treated as

Reserved.

12.2.1 GBECSR1—Gigabit Ethernet Capabilities and Status

Address Offset: MBARA + 00h Attribute: R/W

Default Value: 00100241h Size : 32 bit

Bit Description

15:9 Reserved.

8Transactions Pending (TXP) — R/W.

1 = Indicates the controller has issued Non-Posted requests which have not been completed.

0 = Indicates that completions for all Non-Posted requests have be en received.

7:1 Reserved

0Initiate Function Level Reset — RO. This bit is used to initiate an FLT transition. A write of 1

initiates the transition. Since hardware must not respond to any cycles until Function Level Reset

completion, the value read by software from this bit is 0.

Table 12-2. Gigabit LAN Capabilities and Status Registers Address Map

(Gigabit LAN —MBARA)

MBARA +

Offset Mnemonic Register Name Default Attribute

00h–03h GBECSR1 Gigabit Ethernet Capabilities and Status

18h–1Bh GBECSR2 Gigabit Ethernet Capabilities and Status

20h–23h GBECSR3 Gigabit Ethernet Capabilities and Status

2Ch–2Fh GBECSR4 Gigabit Ethernet Capabilities and Status

F00h–F03h GBECSR5 Gigabit Ethernet Capabilities and Status

F10h–F13h GBECSR6 Gigabit Ethernet Capabilities and Status

5400h–5403h GBECSR7 Gigabit Ethernet Capabilities and Status

5404h–5407h GBECSR8 Gigabit Ethernet Capabilities and Status

5800h–5803h GBECSR9 Gigabit Ethernet Capabilities and Status

Gigabit LAN Configuration Registers

392 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

12.2.2 GBECSR2—Gigabit Ethernet Capabilities and Status

Address Offset: MBARA + 18h Attribute: R/W/SN

Default Value: 01501000h Size: 32 bit

12.2.3 GBECSR3—Gigabit Ethernet Capabilities and Status

Address Offset: MBARA + 20h Attribute: R/W/V

Default Value: 1000XXXXh Size: 32 bit

12.2.4 GBECSR4—Gigabit Ethernet Capabilities and Status

Address Offset: MBARA + 2Ch Attribute: R/W

Default Value: 00000000h Size: 32 bit

Bit Description

31:25 Reserved

24 PHY Power Down (PHYPDN) — R/W.

When cleared (0b), the PHY power down setting is controlled by the internal logic of PCH.

23:0 Reserved

Bit Description

31:21 Reserved

20 PHY Power Down Enable (PHYPDEN) — R/W/SN.

When set, this bit enables the PHY to enter a low-power state when the LAN controller is at the

DMoff/D3 or with no WOL.

19:0 Reserved

Bit Description

31:29 Reserved

28 Ready Bit (RB) — R/W/V.

Set to 1 by the Gigabit Ethernet Controller at the end of the MDI transaction. This bit should be

reset to 0 by software at the same time the command is written.

27:26

MDI Type — R/W/V.

01 = MDI Write

10 = MDI Read

All other values are reserved.

25:21 LAN Connected Device Address (PHYADD) — R/W/V.

20:16 LAN Connected Device Register Address (PHYREGADD) — R/W/V.

15:0 DATA — R/W/V.

Gigabit LAN Configuration Registers

Intel® C600 Series Chipset and Intel® X79 Express Chipset 393

Datasheet

12.2.5 GBECSR5—Gigabit Ethernet Capabilities and Status

Address Offset: MBARA + F00h Attribute: R/W/V

Default Value: 00010008h Size : 32 bit

12.2.6 GBECSR6—Gigabit Ethernet Capabilities and Status

Address Offset: MBARA + F10h Attribute: R/W/SN

Default Value: 0004000Ch Size : 32 bit

12.2.7 GBECSR7—Gigabit Ethernet Capabilities and Status

Address Offset: MBARA + 5400h Attribute: R/W

Default Value: XXXXXXXXh Size: 32 bit

Bit Description

31 WOL Indication Valid (WIV) — R/W.

Set to 1 by BIOS to indicate that the WOL indication setting in bit 30 of this register is valid.

30 WOL Enable Setting by BIOS (WESB) — R/W.

1 = WOL Enabled in BIOS.

0 = WOL Disabled in BIOS.

29:0 Reserved

Bit Description

31:6 Reserved

5SW Semaphore FLAG (SWFLAG) — R/W/V.

This bit is set by the device driver to gain access permission to shared CSR registers

with the firmware and hardware.

4:0 Reserved

Bit Description

31:7 Reserved

6Global GbE Disable (GGD)— R/W/SN.

Prevents the PHY from autonegotiating 1000Mb/s link in all power states.

5:4 Reserved

3GbE Disable at non D0a — R/W/SN.

Prevents the PHY from autonegotiating 1000Mb/s link in all power states except D0a. This bit must

be set since GbE is not supported in Sx states.

2LPLU in non D0a (LPLUND) — R/W/SN.

Enables the PHY to negotiate for the slowest possible link in all power states except D0a.

1LPLU in D0a (LPLUD) — R/W/SN.

Enables the PHY to negotiate for the slowest possible link in all power states. This bit overrides bit 2.

0 Reserved

Bit Description

31:0 Receive Address Low (RAL)— R/W.

The lower 32 bits of the 48 bit Ethernet Address.

Gigabit LAN Configuration Registers

394 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

12.2.8 GBECSR8—Gigabit Ethernet Capabilities and Status

Address Offset: MBARA + 5404h Attribute: R/W

Default Value: XXXXXXXXh Size: 32 bit

12.2.9 GBECSR9—Gigabit Ethernet Capabilities and Status

Address Offset: MBARA + 5800h Attribute: R/W/SN

Default Value: 00000008h Size: 32 bit

Bit Description

31 Address Valid— R/W.

30:16 Reserved

15:0 Receive Address High (RAH)— R/W.

The lower 16 bits of the 48 bit Ethernet Address.

Bit Description

31:1 Reserved

0Advanced Power Management Enable (APME) — R/W/SN.

1 = APM Wakeup is enabled

0 = APM Wakeup is disabled

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 395

Datasheet

13 LPC Interface Bridge Registers

(D31:F0)

The LPC bridge function of the PCH resides in PC I Device 31:Function 0. This function

contains many other functional units, such as DMA and Interrupt controllers, Timers,

Power Management, System Management, GPIO, RTC, and LPC Configuration

Registers.

Registers and functions associated with other functional units are described in their

respective sections.

13.1 PCI Configuration Registers (LPC I/F—D31:F0)

Note: Address locations that are not shown should be treated as Reserved.

Table 13-1. LPC Interface PCI Register Address Map (LPC I/F—D31:F0) (Sheet 1 of 2)

Offset Mnemonic Register Name Default Type

00h–01h VID Vendor Identification 8086h RO

02h–03h DID Device Identification See register

description RO

04h–05h PCICMD PCI Command 0007h R/W, RO

06h–07h PCISTS PCI Status 0210h R/WC, RO

08h RID Revision Identification See register

description RO

09h PI Programming Interface 00h RO

0Ah SCC Sub Class Code 01h RO

0Bh BCC Base Class Code 06h RO

0Dh PLT Primary Latency Timer 00h RO

0Eh HEADTYP Header Type 80h RO

2Ch–2Fh SS Sub System Identifiers 00000000h R/WO

34h CAPP Capability List Pointer E0h RO

40h–43h PMBASE ACPI Base Address 00000001h R/W, RO

44h AC PI_CNTL ACPI Control 00h R/W

48h–4Bh GPIOBASE GPIO Base Address 00000001h R/W, RO

4C GC GPIO Control 00h R/W

60h–63h PIRQ[n]_ROUT PIRQ[A–D] Routing Control 80808080h R/W

64h SIRQ_CNTL Serial IRQ Control 10h R/W, RO

68h–6Bh PIRQ[n]_ROUT PIRQ[E–H] Routing Control 80808080h R/W

6Ch–6Dh LPC_IBDF IOxAPIC Bus:Device:Function 00F8h R/W

70h–7F LPC_HnBDF HPET Configuration 00F8h R/W

80h LPC_I/O_DEC I/O Decode Ranges 0000h R/W

82h–83h LPC_EN LPC I/F Enables 0000h R/W

84h–87h GEN1_DEC LPC I/F Generic Decode Range 1 00000000h R/W

88h–8Bh GEN2_DEC LPC I/F Generic Decode Range 2 00000000h R/W

8Ch–8Eh GEN3_ DEC LPC I/F Generic Decode Range 3 00000000h R/W

LPC Interface Bridge Registers (D31:F0)

396 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

13.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0)

Offset Address: 00h–01h Attribute: RO

Default Value: 8086h Size: 16-bit

Lockable: No Power Well: Core

13.1.2 DID—Device Identification Register (LPC I/F—D31:F0)

Offset Address: 02h–03h Attribute: RO

Default Value: See bit description Size: 16-bit

Lockable: No Power Well: Core

90h–93h GEN4_DEC LPC I/F Generic Decode Range 4 00 000000h R/W

94h–97h ULKMC USB Legacy Keyboard / Mouse Control

98h–9Bh LGMR L PC Generic Memory Range 00000000h R/W

A0h–CFh Power Management (See

Section 13.8.1)

D0h–D3h BIOS_SEL1 BIOS Select 1 00112233h R/W, RO

D4h–D5h BIOS_SEL2 BIOS Select 2 4567h R/W

D8h–D9h BIOS_DEC_EN1 BIOS Decode Enable 1 FFCFh R/W, RO

DCh BIOS_CNTL BIOS Co ntrol 20h R/WLO, R/W,

E0h–E1h FDCAP Feature Detection Capability ID 0009h RO

E2h FDLEN Feature Detection Capability Length 0Ch RO

E3h FDVER Feature Detection Version 10h RO

E4h–EBh FDVCT Feature Vector See Description RO

F0h–F3h RCBA Root Complex Base Address 00000000h R/W

Table 13-1. LPC Interface PCI Register Address Map (LPC I/F—D31:F0) (Sheet 2 of 2)

Offset Mnemonic Register Name Default Type

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h

Bit Description

15:0 Device ID — RO. This is a 16-bit v alue as signed to t he PCH LPC br idge. R efer to th e Intel® C600

Series Chipset and Intel® X79 Express Chipset Specification Update for the v alue of the Device ID

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 397

Datasheet

13.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)

Offset Address: 04h–05h Attribute: R/W, RO

Default Value: 0007h Size: 16-bit

Lockable: No Power Well: Core

13.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0)

Offset Address: 06h–07h Attribute: RO, R/WC

Default Value: 0210h Size: 16-bit

Lockable: No Power Well: Core

Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to

the bit has no effect.

Bit Description

15:10 Reserved

9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0.

8SERR# Enable (SERR_EN) — R/W. The LPC bridge generates SERR# if this bit is set.

7 Wait Cycle Control (WCC ) — RO. Hardwired to 0.

6Parity Error Response Enable (PERE) — R/W.

0 = No action is taken when detecting a parity error.

1 = Enables the PCH LPC bridge to respond to parity errors detected on backbone interface.

5 VGA Palette Snoop (VPS) — RO. Hardwired to 0.

4 Memory Write and Invalidate Enable (MWIE) — RO. Hardwired to 0.

3 Special Cycle Enable (SCE) — RO. Hardwired to 0.

2 Bus Master Enable (BME) — RO. Bus Masters cannot be disabled.

1 Memory Space Enable (MSE) — RO. Memory space cannot be d isabled on LPC.

0 I/O Space Enable (IOSE) — RO. I/O space cannot be disabled on LPC.

Bit Description

Detected Parity Error (DPE) — R/WC. Set when the LPC bridge detects a parity error on the

internal backbone. Set even if the PCICMD.PERE bit (D31:F0:04, bit 6) is 0.

0 = Parity Error Not detected.

1 = Parity Error detected.

14 Signaled System Error (SSE)— R/WC. Set when the LPC bridge signals a system error to the

internal SERR# logic.

13 Master Abort Status (RMA) — R/WC.

0 = Unsupported request status not received.

1 = The bridge received a completion with unsupported request status from the backbone.

12 Received Target Abort (RTA) — R/WC.

0 = Completion abort not received.

1 = Completion with completion abort received from the backbone.

11 Signaled Target Abort (STA) — R/WC.

0 = Target abort Not generated on the backbone.

1 = LPC bridge generated a completion packet with target abort status on the backbone.

10:9 DEVSEL# Timing Status (DEV_STS) — RO.

01 = Medium Timing.

Data Parity Error Detected (DPED) — R/WC.

0 = All conditions listed below Not met.

1 = Set when all three of the following conditions are met:

• LPC bridge receives a completion packet from the backbone from a previous request,

• Parity error has been detected (D31:F0:06, bit 15)

• PCICMD.PERE bit (D31:F0:04, bit 6) is set.

LPC Interface Bridge Registers (D31:F0)

398 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

13.1.5 RID—Revision Identification Register (LPC I/F—D31:F0)

Offset Address: 08h Attribute: R/WO

Default Value: See bit description Size: 8 bits

13.1.6 PI—Programming Interface Register (LPC I/F—D31:F0)

Offset Address: 09h Attribute: RO

Default Value: 00h Size: 8 bits

13.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0)

Offset Address: 0Ah Attribute: RO

Default Value: 01h Size: 8 bits

13.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0)

Offset Address: 0Bh Attribute: RO

Default Value: 06h Size: 8 bits

7 Fast Back to Back Capable (FBC): Reserved – bit has no meaning on the internal backbone.

6 Reserved.

5 66 MHz Capable (66MHZ_CAP) — Reserved – bit has no meaning on the internal backbone.

4Capabilities List (CLIST) — RO. Capability list exists on the LPC bridge.

3Interrupt Status (IS) — RO. The LPC bridge do es not generate interrupts.

2:0 Reserved.

Bit Description

7:0 Revision ID (RID) — R/WO. Refer to the Intel® C600 Series Chipset and Intel® X79 Express

Chipset Specification Update for the value of the Revision ID Register

Bit Description

7:0 Programming Interface — RO.

Bit Description

7:0 Sub Class Code — RO. 8-bit value that indicates the category of bridge for the LPC bridge.

01h = PCI-to-ISA bridge.

Bit Description

7:0 Base Class Code — RO. 8-bit value that indicates the type of device for the LPC bridge.

06h = Bridge device.

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 399

Datasheet

13.1.9 PLT—Primary Latency Timer Register (LPC I/F—D31:F0)

Offset Address: 0Dh Attribute: RO

Default Value: 00h Size: 8 bits

13.1.10 HEADTYP—Header Type Register (LPC I/F—D31:F0)

Offset Address: 0Eh Attribute: RO

Default Value: 80h Size: 8 bits

13.1.11 SS—Sub System Identifiers Register (LPC I/F—D31:F0)

Offset Address: 2Ch–2Fh Attribute: R/WO

Default Value: 00000000h Size: 32 bits

This register is initialized to logic 0 by the assertion of PLTRST#. This register can be

written only once after PLTRST# deassertion.

13.1.12 CAPP—Capability List Pointer Register (LPC I/F—D31:F0)

Offset Address: 34h Attribute: RO

Default Value: E0h Size : 8 bits

Bit Description

7:3 Master Latency Count (MLC) — Reserved.

2:0 Reserved.

Bit Description

7Multi-Function Device — RO. This bit is 1 to indicate a multi-function device.

6:0 Header Type — RO. This 7-bit field iden tifies the header layout of the con figuration space.

Bit Description

31:16 Subsystem ID (SSID) — R/WO. This is written by BIOS. No hardware action taken on this value.

15:0 Subsystem Vendor ID (SSVID) — R/WO. This is written by BIOS. No hardware action taken on

this value.

Bit Description

7:0 Capability Pointer (CP) — RO. Indicates the offset of the first Capability item.

LPC Interface Bridge Registers (D31:F0)

400 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

13.1.13 PMBASE—ACPI Base Address Register (LPC I/F—D31:F0)

Offset Address: 40h–43h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bit

Lockable: No Usage: ACPI, Legacy

Power Well: Core

Sets base address for ACPI I/O registers, GPIO registers and TCO I/O registers. These

registers can be mapped anywhere in the 64-K I/O space on 128-byte boundaries.

13.1.14 ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0)

Offset Address: 44h Attribute: R/W

Default Value: 00h Size: 8 bit

Lockable: No Usage: ACPI, Legacy

Power Well: Core

Bit Description

31:16 Reserved

15:7 Base Address — R/W. This field provides 128 bytes of I/O space for ACPI, GPIO, and TCO logic.

This is placed on a 128-byte boundary.

6:1 Reserved

0 Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate I/O space.

Bit Description

ACPI Enable (ACPI_EN) — R/W.

0 = Disable.

1 = Decode of the I/O range pointed to by the ACPI base register is enabled, and the ACPI power

management function is enabled. Note that the APM power management ranges (B2/B3h) are

always enabled and are not affected by this bit.

6:3 Reserved

2:0

SCI IRQ Select (SCI_IRQ_SEL) — R/W.

Specifies on which IRQ the SCI will internally appear. If not using the APIC, the SCI must be routed

to IRQ9–11, and that interrupt is not sharable with the SERIRQ stream, but is shareable with other

PCI interrupts. If using the APIC, the SCI can also be mapped to IRQ20–23, and can be shared with

other interrupts.

When the interrupt is mapped to APIC interrupts 9, 10 or 11, the APIC should be programmed for

active-high reception. When the interrupt is mapped to APIC interrupts 20 through 23, the APIC

should be programmed for active-low reception.

Bits SCI Map

000b IRQ9

001b IRQ10

010b IRQ11

011b Reserved

100b IRQ20 (Only available if APIC enabled)

101b IRQ21 (Only available if APIC enabled)

110b IRQ22 (Only available if APIC enabled)

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 401

Datasheet

13.1.15 GPIOBASE—GPIO Base Address Register

(LPC I/F — D31:F0)

Offset Address: 48h–4Bh Attribute: R/W, RO

Default Value: 00000001h Size : 32 bit

13.1.16 GC—GPIO Control Register (LPC I/F — D31:F0)

Offset Address: 4Ch Attribute: R/W

Default Value: 00h S ize: 8 bit

Bit Description

31:16 Reserved. Always 0.

15:7 Base Address (BA) — R/W. Provides the 128 bytes of I/O space for GPIO.

6:1 Reserved. Always 0.

0 RO. Hardwired to 1 to indicate I/O space.

Bit Description

7:5 Reserved.

GPIO Enable (EN) — R/W. This bit enables/disables decode of the I/O range pointed to by the

GPIO Base Address register (D31:F0:48h) and enables the GPIO function.

0 = Disable.

1 = Enable.

3:1 Reserved.

GPIO Lockdown Enable (GLE) — R/W. This bit enables lockdown of the following GPIO registers:

• Offset 00h: GPIO_USE_SEL

• Offset 04h: GP_IO_SEL

• Offset 0Ch: GP_LVL

• Offset 30h: GPIO_USE_SEL2

• Offset 34h: GP_IO_SEL2

• Offset 38h: GP_LVL2

• Offset 40h: GPIO_USE_SEL3

• Offset 44h: GP_IO_SEL3

• Offset 48h: GP_LVL3

• Offset 60h: GP_RST_SEL

0 = Disable.

1 = Enable.

When this bit is written from a 1-to-0, an SMI# is generated, if enabled. This ensures that only SMM

code can change the above GPIO registers after they are locked down.

LPC Interface Bridge Registers (D31:F0)

402 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

13.1.17 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register

(LPC I/F—D31:F0)

Offset Address: PIRQA – 60h, PIRQB – 61h, Attribute:R/W

PIRQC – 62h, PIRQD – 63h

Default Value: 80h Size:8 bit

Lockable: No Power Well:Core

Bit Description

Interrupt Routing Enable (IRQEN) — R/W.

0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in

bits[3:0].

1 = T he PIRQ is not routed to the 8259.

Note: BIOS must program this bit to 0 during POST for any of the PIRQs that are being used.

The value of this bit may subsequently be changed by the OS when setting up for I/O

APIC interrupt delivery mode.

6:4 Reserved

3:0

IRQ Routing — R/W. (ISA compatible.)

Value IRQ Value IRQ

0000b Reserved 1000b Reserved

0001b Reserved 1001b IRQ9

0010b Reserved 1010b IRQ10

0011b IRQ3 1011b IRQ11

0100b IRQ4 1100b IRQ12

0101b IRQ5 1101b Reserved

0110b IRQ6 1110b IRQ14

0111b IRQ7 1111b IRQ15

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 403

Datasheet

13.1.18 SIRQ_CNTL—Serial IRQ Control Register

(LPC I/F—D31:F0)

Offset Address: 64h Attribute: R/W, RO

Default Value: 10h S ize: 8 bit

Lockable: No Power Well: Core

Bit Description

7Serial IRQ Enable (SIRQEN) — R/W.

0 = The buffer is input only and internally SERIRQ will be a 1.

1 = Serial IRQs will be recognized. The SERIRQ pin will be configured as SERIRQ.

Serial IRQ Mode Select (SIRQMD) — R/W.

0 = The serial IRQ machine will be in quiet mode.

1 = The serial IRQ machine will be in continuous mode.

Note: For s ystems using Quie t Mode, this bit s hould be set to 1 (Continuous Mode) for at least one

frame after coming out of reset before switching back to Quiet Mode. Failure to do so will

result in the PCH not recognizing SERIRQ interrupts.

5:2 Serial IRQ Frame Size (SIRQSZ) — RO. Fix ed field that indicates the size of the SERIRQ frame as

21 frames.

1:0

Start Frame Pulse Width (SFPW) — R/W. This is the number of PCI clocks that the SERIRQ pin

will be driven low by the serial IRQ machine to signal a start fr ame. In continuous mode, the PCH will

drive the start frame for the number of clocks specified. In quiet mode, the PCH will drive the start

frame for the number of clocks specified minus one, as the first clock was driven by the peripheral.

00 = 4 clocks

01 = 6 clocks

10 = 8 clocks

11 = Reserved

LPC Interface Bridge Registers (D31:F0)

404 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

13.1.19 PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register

(LPC I/F—D31:F0)

Offset Address: PIRQE – 68h, PIRQF – 69h, Attribute: R/W

PIRQG – 6Ah, PIRQH – 6Bh

Default Value: 80h Size: 8 bit

Lockable: No Power Well: Core

13.1.20 LPC_IBDF—IOxAPIC Bus:Device:Function

(LPC I/F—D31:F0)

Offset Address: 6Ch-6Dh Attribute: R/W

Default Value: 00F8h Size: 16 bit

Bit Description

Interrupt Routing Enable (IRQEN) — R/W.

0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in bits[3:0].

1 = T he PIRQ is not routed to the 8259.

Note: BIOS must program this bi t to 0 during POS T for any of the PIRQs that are being used. The

value of this bit may subsequently be changed by the OS when setting up for I/O APIC

interrupt delivery mode.

6:4 Reserved

3:0

IRQ Routing — R/W. (ISA compatible.)

Value IRQ Value IRQ

0000b Reserved 1000b Reserved

0001b Reserved 1001b IRQ9

0010b Reserved 1010b IRQ10

0011b IRQ3 1011b IRQ11

0100b IRQ4 1100b IRQ12

0101b IRQ5 1101b Reserved

0110b IRQ6 1110b IRQ14

0111b IRQ7 1111b IRQ15

Bit Description

15:0

IOxAPIC Bus:Device:Function (IBDF)— R/W. this field specifies the bus:device:function that

PCH’s IOxAPIC will be using for the following:

• As the Requester ID when initiating Interrupt Messages to the processor.

• As the Completer ID when responding to the reads targeting the IOxAPIC’s Memory-Mapped

I/O registers.

The 16-bit field comprises the following:

This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS can program this field to

provide a unique bus:device:function number for the internal IOxAPIC.

Bits Description

15:8 Bus Number

7:3 Device Number

2:0 Function Number

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 405

Datasheet

13.1.21 LPC_HnBDF – HPET n Bus:Device:Function(LPC I/F—

D31:F0)

Address Offset H0BDF 70h-71h

H1BDF 72h-73h

H2BDF 74h-75h

H3BDF 76h-77h

H4BDF 78h-79h

H5BDF 7Ah-7Bh

H6BDF 7Ch-7Dh

H7BDF 7Eh-7Fh Attribute: R/W

Default Value: 00F8h Size: 16 bit

Bit Description

15:0

HPET n Bus:Device:Function (HnBDF)— R/W. This field specifies the bus:device:function that

the PCH’s HPET n will be using in the following:

• As the Requester ID when initiating Interrupt Messages to the processor

• As the Completer ID when responding to the reads targeting the corresponding HPET’s

Memory-Mapped I/O registers

The 16-bit field comprises the following:

This field is default to Bus 0: Device 31: Function 0 after reset. BIOS shall program this field

accordingly if unique bus:device:function number is required for the corresponding HPET.

Bits Description

15:8 Bus Number

7:3 Device Number

2:0 Function Number

LPC Interface Bridge Registers (D31:F0)

406 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

13.1.22 LPC_I/O_DEC—I/O Decode Ranges Register

(LPC I/F—D31:F0)

Offset Address: 80h Attribute: R/W

Default Value: 0000h Size: 16 bit

Bit Description

15:13 Reserved

12 FDD Decode Range — R/W. Determines which range to decode for the FDD Port

0 = 3F0h – 3F5h, 3F7h (Primary)

1 = 370h – 375h, 377h (Secondary)

11:10 Reserved

9:8

LPT Decode Range — R/W. This field determines which range to decode for the LPT Port.

00 = 378h – 37Fh and 778h – 77Fh

01 = 278h – 27Fh (port 279h is read only) and 678h – 67Fh

10 = 3BCh –3BEh and 7BCh – 7BEh

11 = Reserved

7Reserved

6:4

COMB Decode Range — R/W. This field determines which range to decode for the COMB Port.

000 = 3F8h – 3FFh (COM1)

001 = 2F8h – 2FFh (COM2)

010 = 220h – 227h

011 = 228h – 22Fh

100 = 238h – 23Fh

101 = 2E8h – 2EFh (COM4)

110 = 338h – 33Fh

111 = 3E8h – 3EFh (COM3)

3Reserved

2:0

COMA Decode Range — R/W. This field determines which range to decode for the COMA Port.

000 = 3F8h – 3FFh (COM1)

001 = 2F8h – 2FFh (COM2)

010 = 220h – 227h

011 = 228h – 22Fh

100 = 238h – 23Fh

101 = 2E8h – 2EFh (COM4)

110 = 338h – 33Fh

111 = 3E8h – 3EFh (COM3)

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 407

Datasheet

13.1.23 LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0)

Offset Address: 82h – 83h Attribute: R/W

Default Value: 0000h Size: 16 bit

Power Well: Core

Bit Description

15:14 Reserved

CNF2_LPC_EN — R/W. Microcontroller Enable # 2.

0 = Disable.

1 = Enables the decodin g of the I/O loca tions 4Eh and 4Fh to the LPC interface. This r ange is use d

for a microcontroller.

CNF1_LPC_EN — R/W. Super I/O Enable.

0 = Disable.

1 = Enables the decodin g of the I/O loca tions 2Eh and 2Fh to the LPC interface. This r ange is use d

for Super I/O devices.

MC_LPC_EN — R/W. Microcontroller Enable # 1.

0 = Disable.

1 = Enables the de coding of the I/O lo cations 62h and 66h to the LPC interface. This range is used

for a microcontroller.

KBC_LPC_EN — R/W. Keyboard Enable.

0 = Disable.

1 = Enables the de coding of the I/O lo cations 60h and 64h to the LPC interface. This range is used

for a microcontroller.

GAMEH_LPC_EN — R/W. High Gameport Enable

0 = Disable.

1 = Enables the decoding of the I/O locations 208h to 20Fh to the LPC interface. This ran ge is used

for a gameport.

GAMEL_LPC_EN — R/W. Low Gameport Enable

0 = Disable.

1 = Enables the decoding of the I/O locations 200h to 207h to the LPC interface. This r ange is used

for a gameport.

7:4 Reserved

FDD_LPC_EN — R/W. Floppy Drive Enable

0 = Disable.

1 = Enables the decoding of the FD D range to the LPC interface. This range is selected in the

LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 12).

LPT_LPC_EN — R/W. Parallel Port Enable

0 = Disable.

1 = Enables the decoding of the LPTrange to the LPC interface. This range is selected in the

LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 9:8).

COMB_LPC_EN — R/W. Com Port B Enable

0 = Disable.

1 = Enables the decoding of the COMB range to the LPC interface. This range is selected in the

LPC_COM Decode Range Register (D31:F0:80h, bits 6:4).

COMA_LPC_EN — R/W. Com Port A Enable

0 = Disable.

1 = Enables the decoding of the COMA range to the LPC interface. This range is selected in the

LPC_COM Decode Range Register (D31:F0:80h, bits 3:2).

LPC Interface Bridge Registers (D31:F0)

408 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

13.1.24 GEN1_DEC—LPC I/F Generic Decode Range 1 Register

(LPC I/F—D31:F0)

Offset Address: 84h – 87h Attribute: R/W

Default Value: 00000000h Size: 32 bit

Power Well: Core

13.1.25 GEN2_DEC—LPC I/F Generic Decode Range 2 Register

(LPC I/F—D31:F0)

Offset Address: 88h – 8Bh Attribute: R/W

Default Value: 00000000h Size: 32 bit

Power Well: Core

Bit Description

31:24 Reserved

23:18

Generic I/O Decode Range Address[7:2] Mask — R/W. A 1 in any bit position indicates that

any value in the corresponding address bit in a received cycle will be treated as a match. The

corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6

bits of the DWord address, allowing for decoding blocks up to 256 bytes in size.

17:16 Reserved

15:2 Generic I/O Decode Range 1 Base Address (GEN1_BASE) — R/W.

Note: The PCH Does not provide decode down to the word or byte level

1Reserved

0Generic Decode Range 1 Enable (GEN1_EN) — R/W.

0 = Disable.

1 = Enable the GEN1 I/O range to be forwarded to the LPC I/F

Bit Description

31:24 Reserved

23:18

Generic I/O Decode Range Address[7:2] Mask — R/W. A 1 in any bit position indicates that

any value in the corresponding address bit in a received cycle will be treated as a match. The

corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6

bits of the DWord address, allowing for decoding blocks up to 256 bytes in size.

17:16 Reserved

15:2 Generic I/O Decode Range 2 Base Address (GEN1_BASE) — R/W.

Note: The PCH does not provide decode down to the word or byte level

1Reserved

0Generic Decode Range 2 Enable (GEN2_EN) — R/W.

0 = Disable.

1 = Enable the GEN2 I/O range to be forwarded to the LPC I/F

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 409

Datasheet

13.1.26 GEN3_DEC—LPC I/F Generic Decode Range 3 Register

(LPC I/F—D31:F0)

Offset Address: 8Ch – 8Eh Attribute: R/W

Default Value: 00000000h Size: 32 bit

Power Well: Core

13.1.27 GEN4_DEC—LPC I/F Generic Decode Range 4 Register

(LPC I/F—D31:F0)

Offset Address: 90h – 93h Attribute: R/W

Default Value: 00000000h Size: 32 bit

Power Well: Core

Bit Description

31:24 Reserved

23:18

Generic I/O Decode Range Address[7:2] Mask — R/W. A 1 in any bit position indicates that

any value in the corresponding address bit in a received cycle will be treated as a match. The

corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6

bits of the DWord address, allowing for decoding blocks up to 256 bytes in size.

17:16 Reserved

15:2 Generic I/O Decode Range 3 Base Address (GEN3_BASE) — R/W.

Note: The PCH Does not provide decode down to the word or byte level

1 Reserved

0Generic Decode Range 3 Enable (GEN3_EN) — R/W.

0 = Disable.

1 = Enable the GEN3 I/O range to be forwarded to the LPC I/ F

Bit Description

31:24 Reserved

23:18

Generic I/O Decode Range Address[7:2] Mask — R/W. A 1 in any bit position indicates that

any value in the corresponding address bit in a received cycle will be treated as a match. The

corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6

bits of the DWord address, allowing for decoding blocks up to 256 bytes in size.

17:16 Reserved

15:2 Generic I/O Decode Range 4 Base Address (GEN4_BASE) — R/W.

Note: The PCH Does not provide decode down to the word or byte level

1 Reserved

0Generic Decode Range 4 Enable (GEN4_EN) — R/W.

0 = Disable.

1 = Enable the GEN4 I/O range to be forwarded to the LPC I/ F

LPC Interface Bridge Registers (D31:F0)

410 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

13.1.28 ULKMC—USB Legacy Keyboard / Mouse Control

(LPC I/F—D31:F0)

Offset Address: 94h – 97h Attribute: RO, R/WC, R/W

Default Value: 00002000h Size: 32 bit

Power Well: Core

Bit Description

31:16 Reserved

Intel SMI Caused by End of Pass-Through (SMIBYENDPS) — R/WC. This bit indicates if the

event occurred. Note that even if the corresponding enable bit is not set in bit 7, then this bit will still

be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#.

0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.

1 = Event Occurred

14:12 Reserved

Intel SMI Caused by Port 64 Write (TRAPBY64W) — R/WC. This bit indicates if the event

occurred. Note that even if the corresponding enable bit i s not set in bit 3, this bit will still be active.

It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Note that

the A20G ate Pass-Throu gh Logic allows specific port 64h writes to complete without setting this bit.

0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.

1 = Event Occurred.

Intel SMI Caused by Port 64 Read (TRAPBY64R) — R/WC. This bit indicates if the event

occurred. Note that even if the corresponding enable bit i s not set in bit 2, this bit will still be active.

It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#.

0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.

1 = Event Occurred.

Intel SMI Caused by Port 60 Write (TRAPBY60W) — R/WC. This bit indicates if the event

occurred. Note that even if the corresponding enable bit i s not set in bit 1, this bit will still be active.

It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Note that

the A20G ate Pass-Throu gh Logic allows specific port 64h writes to complete without setting this bit.

0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.

1 = Event Occurred.

Intel SMI Caused by Port 60 Read (TRAPBY60R) — R/WC. This bit indicates if the event

occurred. Note that even if the corresponding enable bit is not set in the bit 0, then this bit will still

be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#.

0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.

1 = Event Occurred.

Intel SMI at End of Pass-Through Enable (SMIATENDPS) — R/W. This bit enables Intel SMI at

the end of a pass-through. This can occur if an Intel SMI is generated in the middle of a pass-

through, and needs to be serviced later.

0 = Disable

1 = Enable

6Pass Through State (PSTATE) — RO.

0 = If software needs to reset this bit, it should set bit 5 in all of the host controllers to 0.

1 = Indicates that the state machine is in the middle of an A20GATE pass-through sequence.

A20Gate Pass-Through Enable (A20PASSEN) — R/W.

0 = Disable.

1 = Enable. Allows A20GATE sequence Pass-Through function. A specific cycle sequence involving

writes to port 60h and 64h does not result in the setting of the Intel SMI status bits.

Note: A20M# functionality is not supported.

4Intel SMI on USB IRQ Enable (USBSMIEN) — R/W.

0 = Disable

1 = Enable. USB interrupt will cause an Intel SMI event.

3Intel SMI on Port 64 Writes Enable (64WEN) — R/W.

0 = Disable

1 = Enable. A 1 in bit 11 will cause an Intel SMI event.

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 411

Datasheet

13.1.29 LGMR — LPC I/F Generic Memory Range

(LPC I/F—D31:F0)

Offset Address: 98h – 9Bh Attribute: R/W

Default Value: 00000000h Size: 32 bit

Power Well: Core

13.1.30 BIOS_SEL1—BIOS Select 1 Register

(LPC I/F—D31:F0)

Offset Address: D0h–D3h Attribute: R/W, RO

Default Value: 00112233h Size: 32 bits

2Intel SMI on Port 64 Reads Enable (64REN) — R/W.

0 = Disable

1 = Enable. A 1 in bit 10 will cause an Intel SMI event.

1Intel SMI on Port 60 Writes Enable (60WEN) — R/W.

0 = Disable

1 = Enable. A 1 in bit 9 will cause an Intel SMI event.

0Intel SMI on Port 60 Reads Enable (60REN) — R/W.

0 = Disable

1 = Enable. A 1 in bit 8 will cause an Intel SMI event.

Bit Description

31:16 Memory Address[31:16] — R/W. This field specifies a 64 KB me mory b lock an ywher e in t he 4 GB

memory space that will be decoded to LPC as standard LPC memory cycle if enabled.

15:1 Reserved

0LPC Memory Range Decode Enable — R/W. When this bit is set to ‘1’, then the range specified in

bits 31:16 of this register is enabled for decoding to LPC

Bit Description

31:28

BIOS_F8_IDSEL — RO. IDSEL for two 512-KB BIOS memory ranges and one 128-KB memory

range. This field is fixed at 0000. The IDSEL programmed in this field addresses the following

memory ranges:

FFF8 0000h – FFFF FFFFh

FFB8 0000h – FFBF FFFFh

000E 0000h – 000F FFFFh

27:24

BIOS_F0_IDSEL — R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL programmed in

this field addresses the following memory ranges:

FFF0 0000h – FFF7 FFFFh

FFB0 0000h – FFB7 FFFFh

23:20

BIOS_E8_IDSEL — R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL programmed in

this field addresses the following memory ranges:

FFE8 0000h – FFEF FFFFh

FFA8 0000h – FFAF FFFFh

19:16

BIOS_E0_IDSEL — R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL programmed in

this field addresses the following memory ranges:

FFE0 0000h – FFE7 FFFFh

FFA0 0000h – FFA7 FFFFh

15:12

BIOS_D8_IDSEL — R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL programmed in

this field addresses the following memory ranges:

FFD8 0000h – FFDF FFFFh

FF98 0000h – FF9F FFFFh

LPC Interface Bridge Registers (D31:F0)

412 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

13.1.31 BIOS_SEL2—BIOS Select 2 Register

(LPC I/F—D31:F0)

Offset Address: D4h–D5h Attribute: R/W

Default Value: 4567h Size: 16 bits

13.1.32 BIOS_DEC_EN1—BIOS Decode Enable Register

(LPC I/F—D31:F0)

Offset Address: D8h–D9h Attribute: R/W, RO

Default Value: FFCFh Size: 16 bits

11:8

BIOS_D0_IDSEL — R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL programmed in

this field addresses the following memory ranges:

FFD0 0000h – FFD7 FFFFh

FF90 0000h – FF97 FFFFh

7:4

BIOS_C8_IDSEL — R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL programmed in

this field addresses the following memory ranges:

FFC8 0000h – FFCF FFFFh

FF88 0000h – FF8F FFFFh

3:0

BIOS_C0_IDSEL — R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL programmed in

this field addresses the following memory ranges:

FFC0 0000h – FFC7 FFFFh

FF80 0000h – FF87 FFFFh

Bit Description

15:12

BIOS_70_IDSEL — R/W. IDSEL for two, 1-M BIOS memory ranges.

The IDSEL programmed in this field addresses the following memory ranges:

FF70 0000h – FF7F FFFFh

FF30 0000h – FF3F FFFFh

11:8

BIOS_60_IDSEL — R/W. IDSEL for two, 1-M BIOS memory ranges.

The IDSEL programmed in this field addresses the following memory ranges:

FF60 0000h – FF6F FFFFh

FF20 0000h – FF2F FFFFh

7:4

BIOS_50_IDSEL — R/W. IDSEL for two, 1-M BIOS memory ranges.

The IDSEL programmed in this field addresses the following memory ranges:

FF50 0000h – FF5F FFFFh

FF10 0000h – FF1F FFFFh

3:0

BIOS_40_IDSEL — R/W. IDSEL for two, 1-M BIOS memory ranges.

The IDSEL programmed in this field addresses the following memory ranges:

FF40 0000h – FF4F FFFFh

FF00 0000h – FF0F FFFFh

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 413

Datasheet

Bit Description

BIOS_F8_EN — RO. Thi s bit enables decoding two 512-KB BIOS memory ranges, and one 128-KB

memory range.

0 = Disable

1 = Enable the following ranges for the BIOS

FFF80000h – FFFFFFFFh

FFB80000h – FFBFFFFFh

BIOS_F0_EN — R/W. This bit enables decoding two 512-KB BIOS memory ranges.

0 = Disable.

1 = Enable the following ranges for the BIOS:

FFF00000h – FFF7FFFFh

FFB00000h – FFB7FFFFh

BIOS_E8_EN — R/W. This bit enables decoding two 512-KB BIOS memory ranges.

0 = Disable.

1 = Enable the following ranges for the BIOS:

FFE80000h – FFEFFFFh

FFA80000h – FFAFFFFFh

BIOS_E0_EN — R/W. This bit enables decoding two 512-KB BIOS memory ranges.

0 = Disable.

1 = Enable the following ranges for the BIOS:

FFE00000h – FFE7FFFFh

FFA00000h – FFA7 FFFFh

BIOS_D8_EN — R/W. This bit enables decoding two 512-KB BIOS memory ranges.

0 = Disable.

1 = Enable the following ranges for the BIOS

FFD80000h – FFDFFFFFh

FF980000h – FF9FFFFFh

BIOS_D0_EN — R/W. This bit enables decoding two 512-KB BIOS memory ranges.

0 = Disable.

1 = Enable the following ranges for the BIOS

FFD00000h – FFD7FFFFh

FF900000h – FF97FFFFh

BIOS_C8_EN — R/W. This bit enables decoding two 512-KB BIOS memory ranges.

0 = Disable.

1 = Enable the following ranges for the BIOS

FFC80000h – FFCFFFFFh

FF880000h – FF8FFFFFh

BIOS_C0_EN — R/W. This bit enables decoding two 512-KB BIOS memory ranges.

0 = Disable.

1 = Enable the following ranges for the BIOS

FFC00000h – FFC7FFFFh

FF800000h – FF87FFFFh

BIOS_Legacy_F_EN — R/W. This enables the decoding of the legacy 64 KB range at F0000h –

FFFFFh.

0 = Disable.

1 = Enable the following legacy ranges for the BIOS

F0000h – FFFFFh

Note: The decode for the BIOS legacy F segment is enabled onl y by this bit and is not affected by

the GEN_PMCON_1.iA64_EN bit.

BIOS_Legacy_E_EN — R/W. This enables the decoding of the legacy 64 KB range at E0000h –

EFFFFh.

0 = Disable.

1 = Enable the following legacy ranges for the BIOS

E0000h – EFFFFh

Note: The decode for the BIOS legacy E segment is enabled only by this bit and is not affected by

the GEN_PMCON_1.iA64_EN bit.

5:4 Reserved

BIOS_70_EN — R/W. Enables decoding two 1-M BIOS memory ranges.

0 = Disable.

1 = Enable the following ranges for the BIOS

FF700000h – FF7FFFFFh

FF300000h – FF3FFFFFh

LPC Interface Bridge Registers (D31:F0)

414 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Note: This register effects the BIOS decode regardless of whether the BIOS is resident on LPC or SPI. The

concept of Feature Space does no t apply to SPI-based flash. The PCH simply decodes these ranges as

memory accesses when enabled for the SPI flash interface.

13.1.33 BIOS_CNTL—BIOS Control Register

(LPC I/F—D31:F0)

Offset Address: DCh Attribute: R/WLO, R/W, RO

Default Value: 20h Size: 8 bit

Lockable: No Power Well: Core

BIOS_60_EN — R/W. Enables decoding two 1-M BIOS memory ranges.

0 = Disable.

1 = Enable the following ranges for the BIOS

FF600000h – FF6FFFFFh

FF200000h – FF2FFFFFh

BIOS_50_EN — R/W. Enables decoding two 1-M BIOS memory ranges.

0 = Disable.

1 = Enable the following ranges for the BIOS

FF500000h – FF5FFFFFh

FF100000h – FF1FFFFFh

BIOS_40_EN — R/W. Enables decoding two 1-M BIOS memory ranges.

0 = Disable.

1 = Enable the following ranges for the BIOS

FF400000h – FF4FFFFFh

FF000000h – FF0FFFFFh

Bit Description

7:6 Reserved

SMM BIOS Write Protect Disable (SMM_BWP)— R/WLO.

This bit set defines when th e BIOS region can be written by the host.

0 = BIOS region SMM protection is disabled. The BIOS Region is writable regardless if Processors

are in SMM or not. (Set this field to 0 for legacy behavior)

1 = BIOS region SMM protection is enabled. The BIOS Region is not writable unless all Processors

are in SMM.

4Top Swap Status (TSS) — RO. This bit provides a read-only path to view the state of the Top

Swap bit that is at offset 3414h, bit 0.

3:2

SPI Read Configuration (SRC) — R/W. This 2-bit field controls two policies related to BIOS reads

on the SPI interface:

Bit 3- Prefetch Enable

Bit 2- Cache Disable

Settings are summarized below:

BIOS Lock Enable (BLE) — R/WLO.

0 = Setting the BIOSWE will not cause SMIs.

1 = Enables setting the BIOSWE bit to cause SMIs. Once set, this bit can only be cleared by a

PLTRST#

Bits 3:2 Description

00b No prefetching, but caching enabled. 64B demand reads load the read

buffer cache with “valid” data, allowing repeated cod e fetches to the same lin e

to complete quickly

01b No prefetching and no caching. One-to-one correspondence of host BIOS

reads to SPI cycles. This value can be used to invalidate the cache.

10b Prefetching and Caching enabled. This mode is used for long sequence s of

short reads to consecutive addresses (that is, shadowing).

11b Reserved. This is an invalid configuration, cachin g must be enabled whe n

prefetching is en abled.

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 415

Datasheet

13.1.34 FDCAP—Feature Detection Capability ID

(LPC I/F—D31:F0)

Offset Address: E0h-E1h Attribute: RO

Default Value: 0009h Size: 16 bit

Power Well: Core

13.1.35 FDLEN—Feature Detection Capability Length

(LPC I/F—D31:F0)

Offset Address: E2h Attribute: RO

Default Value: 0Ch Size: 8 bit

Power Well: Core

13.1.36 FDVER—Feature Detection Version

(LPC I/F—D31:F0)

Offset Address: E3h Attribute: RO

Default Value: 10h Size: 8 bit

Power Well: Core

BIOS Write Enable (BIOSWE) — R/W.

0 = Only read cycles result in BIOS I/F cycles.

1 = Access to the BIOS space is enabled for both read and write cycles. When this bit is written

from a 0 to a 1 and BIOS Lock Enable (BLE) is also set, an SMI# is gener ated. This ensures that

only Intel SMI code can update BIOS.

Bit Description

15:8 Next Item Pointer (NEXT) — RO. Configuration offset of the next Capability Item. 00h indicates

the last item in the Capability List.

7:0 Capability ID — RO. Indicates a Vendor Specific Capability

Bit Description

7:0 Capability Length — RO. Indicates the length of this Vendor Specific capability, as required by PCI

Specification.

Bit Description

7:4 Vendor-Specific Capability ID — RO. A value of 1h in this 4-bit field identifies this Capability as

Feature Detection Type. This field allows software to differentiate the Feature Detection Capability

from other Ve ndor-Specific capabilities

3:0 Capability Version — RO. This field indicates the version of the Feature Detection capability

LPC Interface Bridge Registers (D31:F0)

416 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

13.1.37 FVECIDX—Feature Vector Index

(LPC I/F—D31:F0)

Offset Address: E4h-E7h Attribute: R/W

Default Value: 00000000h Size: 32 bit

Power Well: Core

13.1.38 FVECD—Feature Vector Data

(LPC I/F—D31:F0)

Offset Address: E8h-EBh Attribute: RO

Default Value: See Description Size: 32 bit

Power Well: Core

13.1.39 Feature Vector Space

13.1.39.1 FVEC0—Feature Vector Register 0

FVECIDX.IDX: 0000b Attribute: RO

Default Value: See Description Size: 32 bit

Power Well: Core

Bit Description

31:6 Reserved

5:2 Index (IDX) — R/W. 4-bit index pointer into the 64-byte Feature Vector space. Data is read from

the FVECD register. This points to a DWord register.

1:0 Reserved

Bit Description

31:0 Data (DATA) — RO. 32-bit data value that is read from the Feature Vector offset pointed to by

FVECIDX.

Bit Description

31:12 Reserved

11:10

USB Port Count Capability — RO

00 = 14 ports

01 = 12 ports

10 = 10 ports

11 = Reserved

9:8 Reserved

7RAID Capability — RO

Disabled

Capable

6SATA Ports 2 and 3 — RO

Capable

Disabled

5:4 Reserved

3SATA Port 1 6 Gb/s Capability— RO

Capable

Disabled

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 417

Datasheet

13.1.39.2 FVEC1—Feature Vector Register 1

FVECIDX.IDX: 0001b Attribute: RO

Default Value: See Description Size: 32 bit

Power Well: Core

13.1.39.3 FVEC2—Feature Vector Register 2

FVECIDX.IDX: 0010b Attribute: RO

Default Value: See Description Size: 32 bit

Power Well: Core

13.1.39.4 FVEC3—Feature Vector Register 3

FVECIDX.IDX: 0011b Attribute: RO

Default Value: See Description Size: 32 bit

Power Well: Core

2SATA Port 0 6 Gb/s Capability— RO

Capable

Disabled

1PCI Interface Capability — RO

Capable

Disabled

0 Reserved

Bit Description

31:23 Reserved

22 USB Redirect (USBr) Capability— RO

0 = Capable

1 = Disabled

21:0 Reserved

Bit Description

31:23 Reserved

22 Intel® Anti-Theft Technology Capability — RO

0 = Disabled

1 = Capable

21 PCI Express* Ports 7 and 8— RO

0 = Capable

1 = Disabled

20:0 Reserved

Bit Description

31:14 Reserved

13 Data Center Manageability Interface (DCMI) Capability — RO

0 = Capable

1 = Disabled

12 Node Manager Capability — RO

0 = Capable

1 = Disabled

11:0 Reserved

LPC Interface Bridge Registers (D31:F0)

418 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

13.1.40 RCBA—Root Complex Base Address Register

(LPC I/F—D31:F0)

Offset Address: F0-F3h Attribute: R/W

Default Value: 00000000h Size: 32 bit

13.2 DMA I/O Registers

Bit Description

31:14 Base Address (BA) — R/W. Base Address for the root complex register block decode range. This

address is aligned on a 16-KB boundary.

13:1 Reserved

0Enable (EN) — R/W. When set, this bit enables the range specified in BA to be claimed as the Root

Complex Register Block.

Table 13-2. DMA Registers (Sheet 1 of 2)

Port Alias Register Name Default Type

00h 10h Channel 0 DMA Base & Current Address Undefined R/W

01h 11h Channel 0 DMA Base & Current Count Undefined R/W

02h 12h Channel 1 DMA Base & Current Address Undefined R/W

03h 13h Channel 1 DMA Base & Current Count Undefined R/W

04h 14h Channel 2 DMA Base & Current Address Undefined R/W

05h 15h Channel 2 DMA Base & Current Count Undefined R/W

06h 16h Channel 3 DMA Base & Current Address Undefined R/W

07h 17h Channel 3 DMA Base & Current Count Undefined R/W

08h 18h Channel 0–3 DMA Command Undefined WO

Channel 0–3 DMA Status Undefined RO

0Ah 1Ah Channel 0–3 DMA Write Single Mask 000001XXb WO

0Bh 1Bh Channel 0–3 DMA Channel Mode 000000XXb WO

0Ch 1Ch Channel 0–3 DMA Clear Byte Pointer Undefined WO

0Dh 1Dh Channel 0–3 DMA Master Clear Undefined WO

0Eh 1Eh Channel 0–3 DMA Clear Mask Undefined WO

0Fh 1Fh Channel 0–3 DMA Write All Mask 0Fh R/W

80h 90h Reserved Page Undefined R/W

81h 91h Channel 2 DMA Memory Low Page Undefined R/W

82h — Channel 3 DMA Memory Low Page Undefined R/W

83h 93h Channel 1 DMA Memory Low Page Undefined R/W

84h–86h 94h–96h Reserved Pages Undefined R/W

87h 97h Channel 0 DMA Memory Low Page Undefined R/W

88h 98h Reserved Page Undefined R/W

89h 99h Channel 6 DMA Memory Low Page Undefined R/W

8Ah 9Ah Channel 7 DMA Memory Low Page Undefined R/W

8Bh 9Bh Channel 5 DMA Memory Low Page Undefined R/W

8Ch–8Eh 9Ch–9Eh Reserved Page Undefined R/W

8Fh 9Fh Refresh Low Page Undefined R/W

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 419

Datasheet

13.2.1 DMABASE_CA—DMA Base and Current Address Registers

I/O Address: Ch. #0 = 00h; Ch. #1 = 02hAttribute: R/W

Ch. #2 = 04h; Ch. #3 = 06hSize: 16 bit (per channel),

Ch. #5 = C4h Ch. #6 = C8h but accessed in two 8-bit

Ch. #7 = CCh; quantities

Default Value: Undefined

Lockable: No Power Well: Core

C0h C1h Channel 4 DMA Base & Cu rrent Address Undefined R/W

C2h C3h Channel 4 DMA Base & Current Count Undefined R/W

C4h C5h Channel 5 DMA Base & Cu rrent Address Undefined R/W

C6h C7h Channel 5 DMA Base & Current Count Undefined R/W

C8h C9h Channel 6 DMA Base & Cu rrent Address Undefined R/W

CAh CBh Channel 6 DMA Base & Current Count Undefined R/W

CCh CDh Channel 7 DMA Base & Current Address Undefined R/W

CEh CFh Channel 7 DMA Base & Current Count Undefined R/W

D0h D1h Channel 4–7 DMA Command Undefined WO

Channel 4–7 DMA Status Undefined RO

D4h D5h Channel 4–7 DMA Write Single Mask 000001XXb WO

D6h D7h Channel 4–7 DMA Channel Mode 000000XXb WO

D8h D9h Channel 4–7 DMA Clear Byte Pointer Undefined WO

DAh DBh Chann el 4–7 DMA Master Clear Undefined WO

DCh DDh Channel 4–7 DMA Clear Mask Undefined WO

DEh DFh Channel 4–7 DMA Write All Mask 0Fh R/W

Table 13-2. DMA Registers (Sheet 2 of 2)

Port Alias Register Name Default Type

Bit Description

15:0

Base and Current Address — R/W. This register determines the address for the transfers to be

performed. The address specified points to two separate registers. On writes, the value is stored in

the Base Address register and copied to the Current Address register. On reads, the value is

returned from the Current Address register.

The address increments/decrements in the Current Address register after each transfer, depending

on the mode of the transfer. If the channel is in auto-initialize mode, the Current Address register

will be reloaded from the Base Address register after a terminal count is generated.

For transfers to/from a 16-bit slave (channels 5–7), the address is shifted left one bit location. Bit

15 will be shifted into Bit 16.

The register is accessed in 8 bit quantities. The byte is pointed to by the current byte pointer flip/

flop. Before accessing an ad dress register, the byte pointer flip/flop should be cleared to ensure that

the low byte is accessed first

LPC Interface Bridge Registers (D31:F0)

420 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

13.2.2 DMABASE_CC—DMA Base and Current Count Registers

I/O Address: Ch. #0 = 01h; Ch. #1 = 03hAttribute: R/W

Ch. #2 = 05h; Ch. #3 = 07hSize: 16-bit (per channel),

Ch. #5 = C6h; Ch. #6 = CAh but accessed in two 8-bit

Ch. #7 = CEh; quantities

Default Value: Undefined

Lockable: No Power Well: Core

13.2.3 DMAMEM_LP—DMA Memory Low Page Registers

I/O Address: Ch. #0 = 87h; Ch. #1 = 83h

Ch. #2 = 81h; Ch. #3 = 82h

Ch. #5 = 8Bh; Ch. #6 = 89h

Ch. #7 = 8Ah; Attribute: R/W

Default Value: Undefined Size: 8-bit

Lockable: No Power Well: Core

13.2.4 DMACMD—DMA Command Register

I/O Address: Ch. #0–3 = 08h;

Ch. #4–7 = D0h Attribute: WO

Default Value: Undefined Size: 8-bit

Lockable: No Power Well: Core

Bit Description

15:0

Base and Current Count — R/W. This register determines the number of transfers to be

performed. The address specified points to two separate registers. On writes, the value is stored in

the Base Count register and copied to the Current Count register. O n r eads, the value is returned

from the Current Count register.

The actual number of transfers is one more than the number programmed in the Base Count

Current Count register after each transfer. When the value in the register rolls from 0 to FFFFh, a

terminal count is generated. If the chann el is in auto-initializ e mode, the Current Count register will

be reloaded from the Base Count register after a terminal count is generated.

For tr ansfers to/from an 8-bit slave ( channels 0–3), the count register indicates the number of bytes

to be transferred. For transfers to/from a 16-bit slave (channels 5–7), the count register indicates

the number of words to be transferred.

The register is accessed in 8 bit quantities. The byte is pointed to by the current byte pointer flip/

flop. Before accessing a count re gister, the byte pointer fl ip/flop should b e cleared to ensure that the

low byte is accessed first.

Bit Description

7:0

DMA Low Page (ISA Address bits [23:16]) — R/W. This register wor ks in conjuncti on with the DMA

controller's Current Address Register to define the complete 24-bit address for the DMA channel.

This register remains static throughout the DMA transfer. Bit 16 of this register is ignored when in

16 bit I/O count by words mode as it is replaced by the bit 15 shifted out from the current address

Bit Description

7:5 Reserved. Must be 0.

DMA Group Arbitration Priority — WO. Each channel group is ind ividually assig ned either fix ed or

rotating arbitration priority. At part reset, each group is initialized in fixed priority.

0 = Fixed priority to the channel group

1 = Rotating priority to the group.

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 421

Datasheet

13.2.5 DMASTA—DMA Status Register

I/O Address: Ch. #0–3 = 08h;

Ch. #4–7 = D0h Attribute: RO

Default Value: Undefined Size: 8-bit

Lockable: No Power Well: Core

13.2.6 DMA_WRSMSK—DMA Write Single Mask Register

I/O Address: Ch. #0–3 = 0Ah;

Ch. #4–7 = D4h Attribute: WO

Default Value: 0000 01xx Size: 8-bit

Lockable: No Power Well: Core

3 Reserved. Must be 0.

DMA Channel Group Enable — WO. Both channel groups are enabled following part reset.

0 = Enable the DMA channel group.

1 = D isable. Disabling channel group 4–7 also disables channel group 0–3, which is cascaded

through channel 4.

1:0 Reserved. Must be 0.

Bit Description

7:4

Channel Request Status — RO. When a valid DMA request is pending for a channel, the

corresponding bit is set to 1. When a DMA request is not pending for a particular channel, the

corresponding bit is se t to 0. T he source of the DREQ may be har dw a re or a software req ues t. Note

that channel 4 is the cascade channel, so the request status of channel 4 is a logical OR of the

request status for channels 0 through 3.

4 = Channel 0

5 = Channel 1 (5)

6 = Channel 2 (6)

7 = Channel 3 (7)

3:0

Channel Terminal Count Status — RO . When a channel reaches terminal count (TC), its status bit

is set to 1. If TC has not been reached, the status bit is set to 0. Channel 4 is programmed for

cascade, so the TC bit response for channel 4 is irrelevant:

0 = Channel 0

1 = Channel 1 (5)

2 = Channel 2 (6)

3 = Channel 3 (7)

Bit Description

7:3 Reserved. Must be 0.

Channel Mask Select — WO.

0 = Enable DREQ for the selected channel. The channel is selected through bits [1:0]. Therefore,

only one channel can be masked / unmasked at a time.

1 = D isable DREQ for the selected channel.

1:0

DMA Channel Select — WO. These bits select the DMA Channel Mode Register to program.

00 = Channel 0 (4)

01 = Channel 1 (5)

10 = Channel 2 (6)

11 = Channel 3 (7)

LPC Interface Bridge Registers (D31:F0)

422 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

13.2.7 DMACH_MODE—DMA Channel Mode Register

I/O Address: Ch. #0–3 = 0Bh;

Ch. #4–7 = D6h Attribute: WO

Default Value: 0000 00xx Size: 8-bit

Lockable: No Power Well: Core

13.2.8 DMA Clear Byte Pointer Register

I/O Address: Ch. #0–3 = 0Ch;

Ch. #4–7 = D8h Attribute: WO

Default Value: xxxx xxxx Size: 8-bit

Lockable: No Power Well: Core

Bit Description

7:6

DMA Transfer Mode — WO. Each DMA channel can be prog rammed in on e of four different modes:

00 = Demand mode

01 = Single mode

10 = Reserved

11 = Cascade mode

Address Increment/Decrement Select — WO. This bit controls address increment/decrement

during D MA transfers.

0 = A ddress increment. (default after part reset or Master Clear)

1 = Address decrement.

Autoinitialize Enable — WO.

0 = Autoinitializ e feature is disabled and DMA tr ansf ers terminate on a terminal count. A part reset

or Master Clear disables autoinitialization.

1 = DMA restores the Base Addre ss and Count registers to the c urrent registers foll owing a terminal

count (TC).

3:2

DMA Transfer Type — WO. These bits repres ent the direction of the DM A transfer. When the

channel is pr ogrammed for cascade mode, (bits[7:6] = 11) the transfer type is irrelevant.

00 = Verify – No I/O or memory strobes generated

01 = Write – Data transferred from the I/O devices to memory

10 = Read – Data transferred from memory to the I/O device

11 = Invalid

1:0

DMA Channel Select — WO. These bits select the DMA Channel Mode Regist er that will be written

by bits [7:2].

00 = Channel 0 (4)

01 = Channel 1 (5)

10 = Channel 2 (6)

11 = Channel 3 (7)

Bit Description

7:0

Clear Byte Pointer — WO. No specific pattern. Command enabled with a write to the I/O port

address. Writing to this register initializes the byte pointer flip/flop to a known s tate. It clears the

internal latch used to address the upper or lower byte of the 16-bit Address and Word Count

Registers. The latch is also cleared by part reset and by the Master Clear command. This command

precedes the first access to a 16-bit DMA controller register. The first access to a 16-bit register will

then access the significant byte, and the second access automatically accesses the most significant

byte.

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 423

Datasheet

13.2.9 DMA Master Clear Register

I/O Address: Ch. #0–3 = 0Dh;

Ch. #4–7 = DAh Attribute: WO

Default Value: xxxx xxxx Size: 8-bit

13.2.10 DMA_CLMSK—DMA Clear Mask Register

I/O Address: Ch. #0–3 = 0Eh;

Ch. #4–7 = DCh Attribute: WO

Default Value: xxxx xxxx Size: 8-bit

Lockable: No Power Well: Core

13.2.11 DMA_WRMSK—DMA Write All Mask Register

I/O Address: Ch. #0–3 = 0Fh;

Ch. #4–7 = DEh Attribute: R/W

Default Value: 0000 1111 Size: 8-bit

Lockable: No Power Well: Core

Bit Description

7:0 Master Clear — WO. No specific pattern. E nabled with a write to the port. This has th e same effect

as the hardware Reset. The Command, Status, Request, and Byte Pointer flip/flop registers are

cleared and the Mask Register is set.

Bit Description

7:0 Clear Mask Register — WO. No specific pattern. Command enabled with a write to the port.

Bit Description

7:4 Reserved. Must be 0.

3:0

Channel Mask Bits — R/W. This register permits all four channels to be simultaneously enabled/

disabled instead of enabling/disabling eac h channel individually, as is the case with the Mask

Regis ter – Write Single Mask Bit. In addition, this regist er has a read path to allow the status of th e

channel mask bits to be read. A channel's mask bit is automatically set to 1 when the Current Byte/

Word Count Register reaches terminal count (unless the channel is in auto-initialization mode).

Setting the bit(s) to a 1 disables the corresponding DREQ(s). Setting the bit(s) to a 0 enables the

corresponding DREQ(s ). Bits [3:0] are set to 1 upon part reset o r Master Clear. When read, b its

[3:0] indicate the DMA channel [3:0] ([7:4]) mask status.

Bit 0 = Channe l 0 (4)1 = Masked, 0 = Not Masked

Bit 1 = Channe l 1 (5)1 = Masked, 0 = Not Masked

Bit 2 = Channe l 2 (6)1 = Masked, 0 = Not Masked

Bit 3 = Channe l 3 (7)1 = Masked, 0 = Not Masked

Note: Disabling channel 4 also disables channels 0–3 due to the cascade of channels 0 – 3

through channel 4.

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13.3 Timer I/O Registers

13.3.1 TCW—Timer Control Word Register

I/O Address: 43h Attribute: WO

Default Value: All bits undefined Size: 8 bits

This register is programmed prior to any counter being accessed to specify counter

modes. Following part reset, the control words for each register are undef ined and each

counter output is 0. Each timer must be programmed to bring it into a known state.

Port Aliases Register Name Default Value Type

40h 50h Counter 0 Interval Time Status Byte Format 0XXXXXXXb RO

Counter 0 Counter Access Port Undefined R/W

41h 51h Counter 1 Interval Time Status Byte Format 0XXXXXXXb RO

Counter 1 Counter Access Port Undefined R/W

42h 52h Counter 2 Interval Time Status Byte Format 0XXXXXXXb RO

Counter 2 Counter Access Port Undefined R/W

43h 53h

Timer Control Word Undefined WO

Timer Control Word Register XXXXXXX0b WO

Counter Latch Command X0h WO

Bit Description

7:6

Counter Select — WO . The Counter Selection b its select the cou nter the contro l word acts upon as

shown below. The Read Back Command is selected when bits[7:6] are both 1.

00 = Counter 0 select

01 = Counter 1 select

10 = Counter 2 select

11 = Read Back Command

5:4

Read/Write Select — WO. Thes e bits are the read/write control bits. The actual counter

programming is done through the counter port (40h for counter 0, 41h for counter 1, and 42h for

counter 2).

00 = Counter Latch Command

01 = Read/Write Least Significant Byte (LSB)

10 = Read/Write Most Significant Byte (MSB)

11 = Read/Write LSB then MSB

3:1

Counter Mode Selection — WO. These bits select one of six possible modes of operation for the

selected counter.

Binary/BCD Countdown Select — WO.

0 = Binary countdown is used. The largest possible binary count is 216

1 = Binary coded decimal (BCD) count is used. The largest possible BCD count is 104

Bit Value Mode

000b Mode 0 Out signal on end of count (=0)

001b Mode 1 Hardware retriggerable one-shot

x10b Mode 2 Rate generator (divide by n counter)

x11b Mode 3 Square wave output

100b Mode 4 Software triggered strobe

101b Mode 5 Hardware triggered strobe

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There are two special commands that can be issued to the counters through this

commands are chosen, several bits within this register are redefined. These register

formats are described below:

RDBK_CMD—Read Back Command

The Read Back Command is used to determine the count value, programmed mode,

and current states of the OUT pin and Null count flag of the selected counter or

counters. Status and/or count may be latched in an y or all o f the counters by selecting

the counter during the register write. The count and status remain latched until read,

and further latch commands are ignored until the count is read. Both count and status

of the selected counters may be latched simultaneously by setting both bit 5 and bit 4

to 0. If both are latched, the first read operation from that counter returns the latched

status. The next one or two reads, depending on whether the counter is programmed

for one or two byte counts, returns the latched count. Subsequent reads return an

unlatched count.

LTCH_CMD—Counter Latch Command

The Counter Latch Command latches the current count v alue. This command is used to

insure that the count read from the counter is accurate. The count value is then read

from each counter's count register through the Counter Ports Access Ports Register

(40h for counter 0, 41h for counter 1, and 42h for counter 2). The count must be read

according to the programmed format, that is, if the counter is programmed for two

byte counts, two bytes must be read. The two bytes do not have to be read one right

after the other (read, write, or programming operations for other counters may be

inserted between the reads). If a counter is latched once and then latched again before

the count is read, the second Counter Latch Command is ignored.

Bit Description

7:6 Read Back Command. Must be 11 to select the Read Back Command

5Latch Count of Selected Counters.

0 = Current count value of the selected counters will be latched

1 = Current count will not be latched

4Latch Status of Selected Counters.

0 = Status of the selected counters will be latched

1 = Status will not be latched

3Counter 2 Select.

1 = Counter 2 count and/or status will be latched

2Counter 1 Select.

1 = Counter 1 count and/or status will be latched

1Counter 0 Select.

1 = Counter 0 count and/or status will be latched.

0 Reserved. Must be 0.

Bit Description

7:6

Counter Selection. These bits select the counter for latching. If “11” is written, then the write is

interpreted as a read back command.

00 = Counter 0

01 = Counter 1

10 = Counter 2

5:4 Counter Latch Command.

00 = Selects the Counter Latch Command.

3:0 Reserved. Must be 0.

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Datasheet

13.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register

I/O Address: Counter 0 = 40h,

Counter 1 = 41h, Attribute: RO

Counter 2 = 42h Size: 8 bits per counter

Default Value: Bits[6:0] undefined, Bit 7=0

Each counter's status byte can be read following a R ead Back Command. If latch status

is chosen (bit 4=0, Read Back Command) as a read back option for a given counter, the

next read from the counter's Counter Access Ports Register (40h for counter 0, 41h for

counter 1, and 42h for counter 2) returns the status byte. The status byte returns the

following:

13.3.3 Counter Access Ports Register

I/O Address: Counter 0 – 40h,

Counter 1 – 41h, Attribute: R/W

Counter 2 – 42h

Default Value: All bits undefined Size: 8 bit

Bit Description

7Counter OUT Pin State — RO.

0 = OUT pin of the counter is also a 0

1 = OUT pin of the counter is also a 1

Count Register Status — RO. This bit indicates when the last count written to the Count Register

(CR) has been loaded in to the counting element (CE). The exact time this happens depends on the

counter mode, but until the count is loaded into the counting element (CE), the count value will be

incorrect.

0 = Count has been transferred from CR to CE and is available for reading.

1 = Null Count. Count has not been transferred from CR to CE and is not yet available for reading.

5:4

Read/Write Selection Status — RO. These reflect the read/w rite selec tion made through

bits[5:4] of the control register. The binary codes returned during the status read match the codes

used to program the counter read/write selection.

00 = Counter Latch Command

01 = Read/Write Least Significant Byte (LSB)

10 = Read/Write Most Significant Byte (MSB)

11 = Read/Write LSB then MSB

3:1

Mode Selection Status — RO. These bits return the counter mode programming. The binary code

returned matches the code used to program the counter mode, as listed under the bit function

above.

000 = Mode 0 — Out signal on end of count (=0)

001 = Mode 1 — Hardware retriggerable one-shot

x10 = Mode 2 — Rate generator (divide by n counter)

x11 = M ode 3 — Square wave output

100 = Mode 4 — Software triggered strobe

101 = Mode 5 — Hardware triggered strobe

0Countdown Type Status — RO. This bit reflects the current countdown type.

0 = Binary countdown

1 = Binary Coded Decimal (B CD) countdown.

Bit Description

7:0

Counter Port — R/W. Each counter port address is used to program the 16-bit Count Register. The

order of programming, either LSB only, MSB only, or LSB then MSB, is defined with the Interval

Counter Control Register at port 43h. The counter port is also used to read the current count from

the Count Register, and return the status of the counter programming following a Read Back

Command.

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13.4 8259 Interrupt Controller (PIC) Registers

13.4.1 Interrupt Controller I/O MAP

The interrupt controller registers are located at 20h and 21h for the master controller

(IRQ 0–7), and at A0h and A1h for the slave controller (IRQ 8–13). These registers

have multiple functions, depending upon the data written to them. Table 13-3 shows

the different register possibilities for each address.

Note: R efer to note addressing active-low interrupt sources in 8259 Interrupt Controllers

section (Chapter 5.9).

13.4.2 ICW1—Initialization Command Word 1 Register

Offset Address: Master Controller – 20h Attribute: WO

Slave Controller

– A0h Size: 8 bit /controller

Default Value: All bits undefined

A write to Initialization Command Word 1 starts the interrupt controller initialization

sequence, during which the following occurs:

1. The Interrupt Mask register is cleared.

2. IRQ7 input is assigned priority 7.

3. The slave mode address is set to 7.

4. Special mask mode is cleared and Status Read is set to IRR.

Once this write occurs, the controller expects writes to ICW2, ICW3, and ICW4 to

complete the initialization sequence.

Table 13-3. PIC Registers

Port Aliases Register Name Default Value Type

20h 24h, 28h,

2Ch, 30h,

34h, 38h, 3Ch

Master PIC ICW1 Init. Cmd Word 1 Undefined WO

Master PIC OCW2 Op Ctrl Word 2 001XXXXXb WO

Master PIC OCW3 Op Ctrl Word 3 X01XXX10b WO

21h 25h, 29h,

2Dh, 31h,

35h, 39h, 3Dh

Master PIC ICW2 Init. Cmd Word 2 Undefined WO

Master PIC ICW3 Init. Cmd Word 3 Undefined WO

Master PIC ICW4 Init. Cmd Word 4 01h WO

Master PIC OCW1 Op Ctrl Word 1 00h R/W

A0h A4h, A8h,

ACh, B0h,

B4h, B8h, BCh

Slave PIC ICW1 Init. Cmd Word 1 Undefined WO

Slave PIC OCW2 Op Ctrl Word 2 001XXXXXb WO

Slave PIC OCW3 Op Ctrl Word 3 X01XXX10b WO

A1h A5h, A9h,

ADh, B 1h,

B5h, B9h, BDh

Slave PIC ICW2 Init. Cmd Word 2 Undefined WO

Slave PIC ICW3 Init. Cmd Word 3 Undefined WO

Slave PIC ICW4 Init. Cmd Word 4 01h WO

Slave PIC OCW1 Op Ctrl Word 1 00h R/W

4D0h – Master PIC Edge/Level Triggered 00h R/W

4D1h – Slave PIC Edge/Level Triggered 00h R/W

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Datasheet

13.4.3 ICW2—Initialization Command Word 2 Register

Offset Address: Master Controller – 21h Attribute: WO

Slave Controller

– A1h Size: 8 bit /controller

Default Value: All bits undefined

ICW2 is used to initialize the interrupt controller with the five most significant bits of

the interrupt vector address. The value programmed for bits[7:3] is used by the

processor to define the base address in the interrupt vector table for the interrupt

routines associated with each IRQ on the controller. Typical ISA ICW2 values are 08h

for the master controller and 70h for the slave controller.

Bit Description

7:5 ICW/OCW Select — WO. These bits are MCS-85 specific, and not needed.

000 = Should be programmed to “000”

4ICW/OCW Select — WO.

1 = This bit must be a 1 to select ICW1 and enable the ICW2, ICW3, and ICW4 sequence.

3Edge/Level Bank Select (LTIM) — WO. Disabled. Replaced by the edge/level triggered control

registers (ELCR, D31:F0:4D0h, D31:F0:4D1h).

2ADI — WO.

0 = Ignored for the PCH. Should be programmed to 0.

1Single or Cascade (SNGL) — WO.

0 = Must be programmed to a 0 to indicate two controllers operating in cascade mode.

0ICW4 Write Required (IC4) — WO.

1 = This bit must be programmed to a 1 to indicate that ICW4 needs to be programmed.

Bit Description

7:3 Interrupt Vector Base Address — WO. Bits [7:3] define the base address in the interrupt vector

table for the interrupt routines associated with each interrupt request level input.

2:0

Interrupt Request Level — WO. When writing ICW2, these bits should all be 0. During an

interrupt ack nowledge cycle, these bits are programmed by th e interrupt controller with the

interrupt to be serviced. This is combined with bits [7:3] to form the interrupt vector driven onto the

data bus during the second INTA# cycle. The code is a three bit binary code:

Code Master Interrupt Slave Interrupt

000b IRQ0 IRQ8

001b IRQ1 IRQ9

010b IRQ2 IRQ10

011b IRQ3 IRQ11

100b IRQ4 IRQ12

101b IRQ5 IRQ13

110b IRQ6 IRQ14

111b IRQ7 IRQ15

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13.4.4 ICW3—Master Controller Initialization Command

Word 3 Register

Offset Address: 21h Attribute: WO

Default Value: All bits undefined Size: 8 bits

13.4.5 ICW3—Slave Controller Initialization Command

Word 3 Register

Offset Address: A1h Attribute: WO

Default Value: All bits undefined Size: 8 bits

13.4.6 ICW4—Initialization Command Word 4 Register

Offset Address: Master Controller – 021h Attribute: WO

Slave Controller

– 0A1h Si ze: 8 bits

Default Value: 01h

Bit Description

7:3 0 = These bits must be programmed to 0.

Cascaded Interrupt Controller IRQ Connection — WO. This bit indicates that the slave

controller is cascaded on IRQ2. When IRQ8#–IRQ15 is asserted, it goes through the slave

controller’s priority resolver. The slave controller’s INTR output onto IRQ2. IRQ2 then goes through

the master controller’ s priorit y solver. If it wins, the INTR signal is asserted to the processor, and the

returning interrupt acknowledge returns the interrupt vector for the slave controller.

1 = This bit must always be programmed to a 1.

1:0 0 = These bits must be programmed to 0.

Bit Description

7:3 0 = These bits must be programmed to 0.

2:0

Slave Identification Code — WO. These bits are compared against the slave id entification code

broadcast by the master controller from the trailing edge of the first internal INTA# pulse to the

trailing edge of the second internal INTA# pulse. These bits must be programmed to 02h to match

the code broadc ast by the mas ter controlle r. When 02h is broadcas t by the maste r contr oller du ring

the INTA# sequence, the slave controller assumes responsibility for broadcasting the interrupt

vector.

Bit Description

7:5 0 = These bits must be programmed to 0.

4Special Fully Nested Mode (SFNM) — WO.

0 = Should normally be disabled by writing a 0 to this bit.

1 = S pecial fully nested mode is programmed.

3Buffered Mode (BUF) — WO.

0 = Must be programmed to 0 for the PCH. This is non-buffered mode.

2Master/Slave in Buffered Mode — WO. Not used.

0 = Should always be programmed to 0.

1Automatic End of Interrupt (AEOI) — WO.

0 = This bit should normally be programmed to 0. This is the normal end of interrupt.

1 = Automatic End of Interrupt (AEOI) mode is programmed.

0Microprocessor Mode — WO.

1 = Must be programmed to 1 to indicate that the controller is operating in an Intel

Architecture-based syst em.

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Datasheet

13.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)

Offset Address: Master Controller – 021h Attribute: R/W

Slave Controller

– 0A1h Size: 8 bits

Default Value: 00h

13.4.8 OCW2—Operational Control Word 2 Register

Offset Address: Master Controller – 020h Attribute: WO

Slave Controller

– 0A0h Size: 8 bits

Default Value: Bit[4:0]=undefined, Bit[7:5]=001

Following a part reset or ICW initialization, the controller enters the fully nested mode

of operation. Non-specific EOI without rotation is the default. Both rotation mode and

specific EOI mode are disabled following initialization.

Bit Description

7:0

Interrupt Request Mask — R/W. When a 1 is written to any bit in this register, the corresponding

IRQ line is masked. When a 0 is written to any bit in this register, the corresponding IRQ mask bit is

cleared, and interrupt requests will again be accepted by the controller. Masking IRQ2 on the master

controller will also mask the interrupt requests from the slave controller.

Bit Description

7:5

Rotate and EOI Codes (R, SL, EOI) — WO. These three bits control the Rotate and End of

Interrupt modes and combinations of the two.

000 = Rotate in Auto EOI Mode (Clear)

001 = Non-specific EOI command

010 = No Operation

011 = *Specific EOI Command

100 = Rotate in Auto EOI Mode (Set)

101 = Rotate on Non-Specific EOI Command

110 = *Set Priority Command

111 = *Rotate on Specific EOI Command

*L0 – L2 Are Used

4:3 OCW2 Select — WO. When selecting OCW2, bits 4:3 = 00

2:0

Interrupt Level Select (L2, L1, L0) — WO. L2, L1, and L0 determine the interrupt lev el acted upon

when the SL bit is active. A simple binary code, outlined below , selects the channel for the command

to act upon. When the SL bit is inactive, these bits do not hav e a defined function; progr amming L2,

L1 and L0 to 0 is sufficient in this case.

Code Interrupt Level Code Interrupt Level

000b IRQ0/8 000b IRQ4/12

001b IRQ1/9 001b IRQ5/13

010b IRQ2/10 010b IRQ6/14

011b IRQ3/11 011b IRQ7/15

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13.4.9 OCW3—Operational Control Word 3 Register

Offset Address: Master Controller – 020h Attribute: WO

Slave Controller

– 0A0h Si ze: 8 bits

Default Value: Bit[6,0]=0, Bit[7,4:2]=undefined,

Bit[5,1]=1

13.4.10 ELCR1—Master Controller Edge/Level Triggered Register

Offset Address: 4D0h Attribute: R/W

Default Value: 00h Size: 8 bits

In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In

level mode (bit[x] = 1), the interrupt is recognized by a high level. The cascade

channel, IRQ2, the heart beat timer (IRQ0), and the keyboard controller (IRQ1),

cannot be put into level mode.

Bit Description

7 Reserved. Must be 0.

Special Mask Mode (SMM) — WO.

1 = The Special Mask Mode can be used by an interrupt service routine to dynamically alter the

system priority structure while the routine is executing, through selective enabling/disabling of

the other channel's mask bits. Bit 5, the ESMM bit, must be set for this bit to have any meaning.

5Enable Special Mask Mode (ESMM) — WO.

0 = Disable. The SMM bit become s a “don't care”.

1 = Enable the SMM bit to set or reset the Special Mask Mode.

4:3 OCW3 Select — WO. When selecting OCW3, bits 4:3 = 01

Poll Mode Command — WO.

0 = Disable. Poll Command is not issued.

1 = Enable. The next I/O read to the interrupt c ontroller is tr eated as an interrupt acknowledge cycle.

An encoded byte is driven onto the data bus, representing the highest priority level requesting

service.

1:0

and the Interrupt Request Register (IRR). When bit 1=0, bit 0 will not affect the register read

selection. When bit 1=1, bit 0 selects the reg ister st atus returned fo llowing an OCW3 read. If bit 0=0,

the IRR will be read. If bit 0=1, the ISR will be read. Following ICW initialization, the default OCW3

port address read will be “read IRR”. To retain the current selection (read ISR or read IRR), always

write a 0 to bit 1 when prog ramming this re gister. The selected reg ister can be read r epeatedly without

reprogramming OCW3. To select a new status register, OCW3 must be reprogrammed prior to

attempting the read.

00 = No Action

01 = No Action

10 = Read IRQ Register

11 = Read IS Register

Bit Description

7IRQ7 ECL — R/W.

0 = Edge

1 = Level

6IRQ6 ECL — R/W.

0 = Edge

1 = Level

5IRQ5 ECL — R/W.

0 = Edge

1 = Level

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Datasheet

13.4.11 ELCR2—Slave Controller Edge/Level Triggered Register

Offset Address: 4D1h Attribute: R/W

Default Value: 00h Size: 8 bits

In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In

level mode (bit[x] = 1), the interrupt is recognized by a high level. The real time clock,

IRQ8#, and the floating point error interrupt, IRQ13, cannot be programmed for level

mode.

13.5 Advanced Programmable Interrupt Controller

(APIC)

13.5.1 APIC Register Map

The APIC is accessed using an indirect addressing scheme. Two registers are visible by

software for manipulation of most of the APIC registers. These registers are mapped

into memory space. The address bits 19:12 of the address range are programmable

through bits 7:0 of OIC register (Chipset Config Registers:Offset 31FEh) The registers

are shown in Table 13-4.

4IRQ4 ECL — R/W.

0 = Edge

1 = Level

3IRQ3 ECL — R/W.

0 = Edge

1 = Level

2:0 Reserved. Must be 0.

Bit Description

7IRQ15 ECL — R/W.

0 = Edge

1 = Level

6IRQ14 ECL — R/W.

0 = Edge

1 = Level

5 Reserved. Must be 0.

4IRQ12 ECL — R/W.

0 = Edge

1 = Level

3IRQ11 ECL — R/W.

0 = Edge

1 = Level

2IRQ10 ECL — R/W.

0 = Edge

1 = Level

1IRQ9 ECL — R/W.

0 = Edge

1 = Level

0 Reserved. Must be 0.

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Datasheet

Table 13-5 lists the registers which can be accessed within the APIC using the Index

Re gister. When accessing these registers, accesses must be done one DW ord at a time.

For example, software should never access byte 2 from the Data register before

accessing bytes 0 and 1. The hardware will not attempt to recover from a bad

programming model in this case.

13.5.2 IND—Index Register

Memory Address FEC_ _0000h Attribute: R/W

Default Value: 00h Size: 8 bits

The Index Register will select which APIC indirect register to be manipulated by

software. The selector values for the indirect registers are listed in Table 13-5. Software

will program this register to select the desired APIC internal register.

Table 13-4. APIC Direct Registers

Address Mnemonic Register Name Size Type

FEC_ _0000h IND Index 8 bits R/W

FEC_ _0010h DAT Data 32 bits R/W

FEC_ _0040h EOIR EOI 32 bits WO

Table 13-5. APIC Indirect Registers

Index Mnemonic Register Name Size Type

00 ID Identification 32 bits R/W

01 VER Version 32 bits RO

02–0F — Reserved — RO

10–11 REDIR_TBL0 Redirection Table 0 64 bits R/W, RO

12–13 REDIR_TBL1 Redirection Table 1 64 bits R/W, RO

... ... ... ... ...

3E–3F REDIR_TBL23 Redirection Table 23 64 bits R/W, RO

40–FF — Reserved — RO

Bit Description

7:0 APIC Index — R/W. This is an 8-bit pointer into the I/O APIC reg ister table.

LPC Interface Bridge Registers (D31:F0)

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Datasheet

13.5.3 DAT—Data Register

Memory Address FEC_ _0000h Attribute: R/W

Default Value: 00000000h Size: 32 bits

This is a 32-bit register specifying the data to be read or written to the register pointed

to by the Index register. This register can only be accessed in dword quantities.

13.5.4 EOIR—EOI Register

Memory Address FEC_ _0000h Attribute: R/W

Default Value: N/A Size: 32 bits

The EOI register is present to provide a mechanism to maintain the level triggered

semantics for level-triggered interrupts issued on the parallel bus.

When a write is issued to this register, the I/O APIC will check the lower 8 bits written

to this register, and compare it with the vector field for each entry in the I/O

Redirection Table. When a match is found, the Remote_IRR bit (Index Offset 10h, bit

14) for that I/O Redirection Entry will be cleared.

Note: If multiple I/O Redirection entries, for any reason, assign the same vector for more

than one interrupt input, each of those entries will have the Remote_IRR bit reset to 0.

The interrupt which was prematurely reset will not be lost because if its input remained

active when the Remote_IRR bit is cleared, the interrupt will be reissued and serviced

at a later time. Note that only bits 7:0 are actually used. Bits 31:8 are ignored by the

PCH.

Note: To provide for future expansion, the processor should always write a value of 0 to Bits

31:8.

13.5.5 ID—Identification Register

Index Offset: 00h Attribute: R/W

Default Value: 00000000h Size: 32 bits

The APIC ID serves as a physical name of the APIC. The APIC bus arbitration ID for the

APIC is derived from its I/O APIC ID. This register is reset to 0 on power-up reset.

Bit Description

7:0 APIC Data — R/W. This is a 32-bit register for the data to be read or written to the APIC indirect

Bit Description

31:8 Reserved. To provide for future expansion, the processor should always write a value of 0 to Bits

31:8.

7:0 Redirection Entry Clear — WO. When a write is issued to this register, the I/O APIC will check this

field, and compare it with the vector field for each entry in the I/O Redirection Table. When a match

is found, the Remote_IRR bit for that I/O Redirection Entry will be cleared.

Bit Description

31:28 Reserved

27:24 APIC ID — R/W. Software must program this value before using the APIC.

23:16 Reserved

15 Scratchpad Bit.

14:0 Reserved

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Datasheet

13.5.6 VER—Version Register

Index Offset: 01h Attribute: RO, R/WO

Default Value: 00170020h Size: 32 bits

Each I/O APIC contains a hardwired Version Register that identifies different

implementation of APIC and their versions. The maximum redirection entry information

also is in this register, to let software know how many interrupt are supported by this

APIC.

13.5.7 REDIR_TBL—Redirection Table

The Redirection Table has a dedicated entry for each interrupt input pin. The

information in the Redirection Table is used to translate the interrupt manifestation on

the corresponding interrupt pin into an APIC message.

The APIC will respond to an edge triggered interrupt as long as the interrupt is held

until after the acknowledge cycle has begun. Once the interrupt is detected, a delivery

status bit internally to the I/O APIC is set. The state machine will step ahead and wait

for an acknowledgment from the APIC unit that the interrupt message was sent. Only

then will the I/O APIC be able to recognize a new edge on that interrupt pin. That new

edge will only result in a new invocation of the handler if its acceptance by the

destination APIC causes the Interrupt Request Register bit to go from 0 to 1.

(In other words, if the interrupt was not already pending at the destination.)

Bit Description

31:24 Reserved

23:16

Maximum Redirection Entries (MRE) — R/WO. This is the entry number (0 being the lowest

entry) of the highest entry in the redirection table. It is equal to the number of interrupt input pins

minus one and is in the range 0 through 239. In the PCH this field is h ardwired to 17h to indicate 24

interrupts.

BIOS must write to this field after PLTRST# to lockdown the value. this allows BIOS to utilize some

of the entries for its own p urp ose and thus advertising fe we r IO xAPIC Redirection Entries to the OS.

15 Pin Assertion Register Supported (PRQ) — RO. Indicate that the IOxAPIC does not implement

the Pin Assertion Register.

14:8 Reserved

7:0 Version (VS) — RO. This is a version number that identifies the implementation version.

Index Offset: 10h–11h (vector 0)

through 3E–3Fh (vector 23) Attribute: R/W, RO

Default Value: Bit 16 = 1. All other bits

undefined Size: 64 bits each, (accessed as two

32 bit quantities)

Bit Description

63:56

Destination — R/W. If bit 11 of this entry is 0 (Physical), then bits 59:56 specifies an APIC ID. In

this case, bits 63:59 should be programmed by software to 0.

If bit 11 of this entry is 1 (Logical), then bits 63:56 specify the logi cal destination address of a set of

processors.

55:48 Extended Destination ID (EDID) — RO. These bits are sent to a local APIC only when in

Processor System Bus mode. They become bits 11:4 of the address.

47:17 Reserved

LPC Interface Bridge Registers (D31:F0)

436 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Note: Delivery Mode encoding:

000 = Fixed. Deliver the signal on the INTR signal of all processor cores listed in the destination. Trigger Mode

can be edge or level.

001 = Lowest Priority. Deliver the signal on the INTR signal of the processor cor e that is ex ecuting at the lowest

priority among all the processors listed in the specified destination. Trigger Mode can be ed ge or level.

010 = SMI (System Management Interrupt). Requires the interrupt to be programmed as edge triggered. The

vector information is ignored but must be programmed to all 0s for future compatibility: not supported

011 = Reserved

100 = NMI. Deliver the signal on the NMI signal of all processor cores listed in the destination. Vector

information is ignored. NMI is treated as an edge triggered interrupt even if it is programmed as level triggered.

For prop er oper ation this redirection table entry must be progr ammed to edge triggered. T he NMI deliv ery mode

does not set the RIRR bit. If the redirection table is incorrectly set to level, the loop count will continue counting

through the redirection table addresses. Once the count for the NMI pin is reached again, the interrupt will be

sent again: not supported

101 = INIT. Deliver the signal to all processor cores listed in the destination by asserting the INIT signal. All

addressed local APICs will assume their INIT state. INIT is always treated as an edge triggered interrupt ev en if

programmed as level triggered. For proper operation this redirection table entry must be programmed to edge

triggered. The INIT delivery mode does not set the RIRR bit. If the redirection table is incorrectly set to level, the

loop count will continue counting through the redirection table addresses. Once the count for the INIT pin is

reached again, the interrupt will be sent again: not supported

110 = Reserved

111 = ExtINT. Deliver the signal to the INTR signal of all processor cores listed in the destination as an interrupt

that originated in an externally connected 8259A compatible interrupt controller. The INTA cycle that

corresponds to this ExtINT delivery will be routed to the external controller that is expected t o supply the vector.

Requires the interru pt to be programmed as edge triggered.

Mask — R/W.

0 = Not masked: An edge or level on thi s interrupt pin results in the delivery of the interrupt to the

destination.

1 = Masked: Interrupts are not delivered nor held pending. Setting this bit after the interrupt is

accepted by a local APIC has no effect on that interrupt. This behavi or is identical to the device

withdrawing the interrupt before it is posted to the processor. It is software's responsibility to

deal with the case where the mask bit is set after the interrupt message has been accepted by

a local APIC unit but before the interrupt is dispensed to the processor.

Trigger Mode — R/W. This field indicates the type of signal on the interrupt pin that triggers an

interrupt.

0 = Edge triggered.

1 = Level triggered.

Remote IRR — R/W. This bit is used for level triggered interrupts; its meaning is undefined for

edge triggered interrupts.

0 = Reset when an EOI message is received from a local APIC.

1 = Set when Local APIC/s accept the level interrupt sent by the I/O APIC.

Interrupt Input Pin Polarity — R/W. This bit specifies the polarity of each interrupt signal

connected to the interrupt pins.

0 = Active high.

1 = Active low.

Delivery Status — RO. This field contains the current status of t he delivery of thi s interrupt. W ri tes

to this bit have no effect.

0 = Idle. No activity for this interrupt.

1 = Pending. Interrupt has been injected, but delivery is not complete.

Destination Mode — R/W. This field determines the interpretation of the Destination field.

0 = Physical. Destination APIC ID is identified by bits 59:56.

1 = Logical. Destinations are identified by matching bit 63:56 with the Logical Destination in the

Destination Format Register and Logical Destination Register in each Local APIC.

10:8 Delivery Mode — R/W. This field specifies how the APICs listed in the destination field should act

upon reception of this signal. Certain Delivery Modes will only operate as intended when used in

conjunction with a specific trigger mode. These encodings are listed in the note below:

7:0 Vector — R/W. This field contains the interrupt vector for this interrupt. Values range between 10h

and FEh.

Bit Description

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 437

Datasheet

13.6 Real Time Clock Registers

13.6.1 I/O Register Address Map

The RTC internal registers and RAM are organized as two banks of 128 bytes each,

called the standard and extended banks. The first 14 bytes of the standard bank

contain the R TC time and date information along with four registers, A –D, that are used

for configuration of the RTC. The extended bank contains a full 128 bytes of battery

backed SRAM, and will be accessible even when the RTC module is disabled (using the

RTC configuration register). Registers A–D do not physically exist in the RAM.

All data movement between the host processor and the real-time clock is done through

registers mapped to the standard I/O space. The register map appears in Table 13-6.

Notes:

1. I/O locations 70h and 71h are the standard legacy location for the real-time clock. The map for this

bank is shown in Table 13-7. Locations 72h and 73h are for accessing the extended RAM. The extended

RAM bank is also accessed using an indexed scheme. I/O address 72h is used as the address pointer

and I/O address 73h is used as the data register. Index addresses above 127h are not valid. If the

extended RAM is not needed, it may be disabled.

2. Software must preserve the value of bit 7 at I/O addresses 70h and 74h. When writing to this address,

software must first read the value, and then write the same value for bit 7 during the sequential address

write. Note that port 70h is not directly readable. The only way to read this register is through Alt

Access mode. Although RTC Index bits 6:0 are readable from port 74h, bit 7 will alwa ys return 0. If the

NMI# enable is not changed during normal operation, software can alternatively read this bit once and

then retain the value for all subsequent writes to port 70h.

13.6.2 Indexed Registers

The RTC contains two sets of indexed registers that are accessed using the two

separate Index and Target registers (70/71h or 72/73h), as shown in Table 13-7.

Table 13-6. RTC I/O Registers

I/O

Locations If U128E bit = 0 Function

70h and 74h Also alias to 72h and 76h Real-Time Clock (Standard RAM) Index Register

71h and 75h Also alias to 73h and 77h Real-Time Clock (Standard RAM) Target Register

72h and 76h Extended RAM Index Register (if enabled)

73h and 77h Extended RAM Target Register (if enabled)

Table 13-7. RTC (Standard) RAM Bank

Index Name

00h Seconds

01h Seconds Alarm

02h Minutes

03h Minutes Alarm

04h Hours

05h Hours Alarm

06h Day of Week

07h Day of Month

08h Month

09h Year

0Ah Register A

0Bh Register B

0Ch Register C

0Dh Register D

0Eh–7Fh 114 Bytes of User RAM

LPC Interface Bridge Registers (D31:F0)

438 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

13.6.2.1 RTC_REGA—Register A

RTC Index: 0A Attribute: R/W

Default Value: Undefined Size: 8-bit

Lockable: No Power Well: RTC

This register is used for general configur ation of the R TC functions. None of the bits are

affected by RSMRST# or any other PCH reset signal.

Bit Description

Update In Progress (UIP) — R/W. This bit may be monitored as a status flag.

0 = The update cycle will not start for at least 488 µs. The time, calendar, and alarm information in

RAM is always available when the UIP bit is 0.

1 = The update is soon to occur or is in progress.

6:4

Division Chain Select (DV[2:0]) — R/W. These three bits control the divider chain for the

oscillator, and are not affected by RSMRST# or any other reset signal.

010 = Normal Operation

11X = Divider Reset

101 = Bypass 15 stages (test mode only)

100 = Bypass 10 stages (test mode only)

011 = Bypass 5 stages (test mode only)

001 = Invalid

000 = Invalid

3:0

Rate Select (RS[3:0]) — R/W. Selects one of 13 taps of the 15 stage divider chain. The selected

tap can generate a periodic interrupt if the PIE bit is set in Regis ter B. Otherwise this tap will set the

PF flag of Register C. If the periodic interrupt is not to be used, these bits should all be set to 0. RS3

corresponds to bit 3.

0000 = Interrupt never toggles

0001 = 3.90625 ms

0010 = 7.8125 ms

0011 = 122.070 µs

0100 = 244.141 µs

0101 = 488.281 µs

0110 = 976.5625 µs

0111 = 1.953125 ms

1000 = 3.90625 ms

1001 = 7.8125 ms

1010 = 15.625 ms

1011 = 31.25 ms

1100 = 62.5 ms

1101 = 125 ms

1110 = 250 ms

1111= 500 ms

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 439

Datasheet

13.6.2.2 RTC_REGB—Register B (General Configuration)

RTC Index: 0Bh Attribute: R/W

Default Value: U0U00UUU (U: Undefined) Size: 8-bit

Lockable: No Power Well: RTC

Bit Description

Update Cycle Inhibit (SET) — R/W. Enables/Inhibits the update cycles. This bit is not affected by

RSMRST# nor any other reset signal.

0 = Update cycle occurs normally once each second.

1 = A current update cycle will abort and subsequent update cycles will not occur until SET is

returned to 0. When set is one, the BIOS may initialize time and calendar bytes safely.

Note: This bit should be set then cleared early in BIOS POST after each powerup directly after

coin-cell battery insertion.

Periodic Interrupt Enable (PIE) — R/W. This bit is cleared by RSMRST#, but not on any other

reset.

0 = Disable.

1 = E nable. Allows an interrupt to occur with a time base set with the RS bits of register A.

Alarm Interrupt Enable (AIE) — R/W. This bit is cleared by RTCRST#, but not on any other reset.

0 = Disable.

1 = E nable. Allows an interrupt to occur when the AF is set by an alarm match from the update

cycle. An alarm can occur once a second, one an hour, once a day, or one a month.

Update-Ended Interrupt Enable (UIE) — R/W. This bit is cleared by RSMRST#, but not on any

other reset.

0 = Disable.

1 = E nable. Allows an interrupt to occur when the update cycle ends.

3Square Wave Enable (SQWE) — R/W. This bit serves no function in the PCH. It is left in this

is cleared by RSMRST#, but not on any other reset.

Data Mode (DM) — R/W. This bit specifies either binary or BCD data representation. This bit is not

affected by RSMRST# nor any other reset signal.

0 = BCD

1 = B inary

Hour Format (HOURFORM) — R/W. This bit indicates the hour byte format. This bit is not affected

by RSMRST# nor any other reset signal.

0 = Twelve-hour mode. In twelve-h our mode, the seventh bit represents AM as 0 and PM as one.

1 = Twenty-four hour mode.

0Daylight Savings Legacy Software Support (DSLSWS) — R/W. Daylight sa vings functionality is

no longer supported. This bit is used to maintain legacy software support and has no associated

functionality. If BUC.DSO bit is set, the DSLSWS bit continues to be R/W.

LPC Interface Bridge Registers (D31:F0)

440 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

13.6.2.3 RTC_REGC—Register C (Flag Register)

RTC Index: 0Ch Attribute: RO

Default Value: 00U00000 (U: Undefined) Size: 8-bit

Lockable: No Power Well: RTC

Writes to Register C have no effect.

13.6.2.4 RTC_REGD—Register D (Flag Register)

RTC Index: 0Dh Attribute: R/W

Default Value: 10UUUUUU (U: Undefined) Size: 8-bit

Lockable: No Power Well: RTC

Bit Description

7Interrupt Request Flag (IRQF) — RO. IRQF = (PF * PIE) + (AF * AIE) + (UF *UFE). Th is b it al so

causes the RTC Interrupt to be asserted. This bit is cleared upon RSMRST# or a read of Register C.

6Periodic Interrupt Flag (PF) — RO. This bit is cleared upon RSMRST# or a read of Register C.

0 = If no taps are specified using the RS bits in Register A, this flag will not be set.

1 = Periodic interrupt Flag will be 1 when the tap specified by the RS bits of register A is 1.

5Alarm Flag (AF) — RO.

0 = This bit is cleared upon RTCRST# or a read of Register C.

1 = Alarm Flag will be set after all Alarm values match the current time.

4Update-Ended Flag (UF) — RO.

0 = The bit is cleared upon RSMRST# or a read of Register C.

1 = Set immediately following an update cycle for each second.

3:0 Reserved. Will always report 0.

Bit Description

Valid RAM and Time Bit (VRT) — R/W.

0 = T his bit should always be written as a 0 for write cycle, however it will return a 1 for read

cycles.

1 = T his bit is hardwired to 1 in the RTC power well.

6 Reserved. This bit always returns a 0 and should be set to 0 for write cycles.

5:0

Date Alarm — R/W. These bits store the date of month alarm value. If set to 000000b, then a don’t

care state is assumed. The host must configure the date alarm for these bits to do anything, yet

they can be written at any time. If the date alarm is not enabled, these bits will return 0s to mimic

the functionality of the Motorola 146818B. These bits are not affected by any reset assertion.

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 441

Datasheet

13.7 Processor Interface Registers

Table 13-8 is the register address map for the processor interface registers.

13.7.1 NMI_SC—NMI Status and Control Register

I/O Address: 61h Attribute: R/W, RO

Default Value: 00h Size: 8-bit

Lockable: No Power Well: Core

Table 13-8. Processor Interface PCI Register Address Map

Offset Mnemonic Register Name Default Type

61h NMI_SC NMI Status and Control 00h R/W, RO

70h NMI_EN NMI Enable 80h R/W (special)

92h PORT92 Fast A20 and Init 00h R/W

F0h COPROC_ERR Coprocessor Error 00h WO

CF9h RST_CNT Reset Control 00h R/W

Bit Description

SERR# NMI Source Status (SERR#_NMI_STS) — RO.

1 = B it is set if a PCI agent detected a system error and pulses the PCI SERR# line and if bit 2

(PCI_SERR_EN) is cleared. This interrupt source is enabled by setting bit 2 to 0. To reset the

interrupt, set bit 2 to 1 and then set it to 0. When writing to port 61h, this bit must be 0.

Note: This bit is set by any of the PCH internal sources of SERR; this includes SERR assertions

forwarded from the secondary PCI bus, errors on a PCI Express* port, or other internal

functions that generate SERR#.

IOCHK# NMI Source Status (IOCHK_NMI_STS) — RO.

1 = B it is set if an LPC agent (using SERIRQ) asserted IOCHK# and if bit 3 (IOCHK_NMI_EN) is

cleared. This inter rupt source i s enabled by setting bit 3 to 0. To reset the interrupt, set bit 3 to

1 and then set it to 0. When writing to port 61h, this bit must be a 0.

5Timer Counter 2 OUT Status (TMR2_OUT_STS) — RO. This bit reflects the current state of the

8254 counter 2 output. Counter 2 must be progr ammed following any PCI reset for this bit to ha ve a

determinate value. When writing to port 61h, this bit must be a 0.

4Refresh Cycle Toggle (REF_TOGGLE) — RO. This signal toggles from either 0 to 1 or 1 to 0 at a

rate that is equiv alent to when refresh cycles would occur. When writing to port 61h, this bit must be

a 0.

3IOCHK# NMI Enable (IOCHK_NMI_EN) — R/W.

0 = E nabled.

1 = D isabled and cleared.

2PCI SERR# Enable (PCI_SERR_EN) — R/W.

0 = S ERR# NMIs are enabled.

1 = SERR# NMIs are disabled and cleared.

1Speaker Data Enable (SPKR_DAT_EN) — R/W.

0 = S PKR output is a 0.

1 = S PKR output is equivalent to the Counter 2 OUT signal value.

0Timer Counter 2 Enable (TIM_CNT2_EN) — R/W.

0 = D isable

1 = Enable

LPC Interface Bridge Registers (D31:F0)

442 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

13.7.2 NMI_EN—NMI Enable (and Real Time Clock Index)

I/O Address: 70h Attribute: R/W (special)

Default Value: 80h Size: 8-bit

Lockable: No Power Well: Core

Note: The R T C Index fi eld is write-onl y for normal oper ation. This field can only be read in Alt-

Access Mode. Note, however, that this register is aliased to Port 74h (documented in),

and all bits are readable at that address.

13.7.3 PORT92— Init Register

I/O Address: 92h Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Power Well: Core

13.7.4 COPROC_ERR—Coprocessor Error Register

I/O Address: F0h Attribute: WO

Default Value: 00h Size: 8-bits

Lockable: No Power Well: Core

Bits Description

7NMI Enable (NMI_EN) — R/W (special).

0 = Enable NMI sources.

1 = D isable All NMI sources.

6:0 Real Time Clock Index Address (RTC_INDX) — R/W (special). This data goes to the RTC to

select wh ich register or CMOS RAM address is being accessed.

Bit Description

7:2 Reserved

1Alternate A20 Gate (ALT_A20_GATE) — R/W. Functionality reserved. A20M# functionalit y

is not supported.

0INIT_NOW — R/W. When this bit transitions from a 0 to a 1, the PCH will force INIT# active for 16

PCI clocks.

Bits Description

7:0 Coprocessor Error (COPROC_ERR) — WO. Any value written to this register will cause IGNNE#

to go active, if FERR# had generated an internal IRQ13. For FERR# to generate an internal IRQ13,

the CEN bit must be 1.

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 443

Datasheet

13.7.5 RST_CNT—Reset Control Register

I/O Address: CF9h Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Power Well: Core

13.8 Power Management Registers

The power management registers are distributed within the PCI Device 31: Function 0

space, as well as a separate I/O range. Each register is described below. Unless

otherwise indicated, bits are in the main (core) power well.

Bits not explicitly defined in each register are assumed to be reserved. When writin g to

a reserved bit, the value should always be 0. Software should not attempt to use the

value read from a reserved bit, as it may not be consistently 1 or 0.

13.8.1 Power Management PCI Configuration Registers

(PM—D31:F0)

Table 13-9 shows a small part of the configuration space for PCI Device 31: Function 0.

It includes only those registers dedicated for power management. Some of the

registers are only used for Legacy Power management schemes.

Bit Description

7:4 Reserved

Full Reset (FULL_RST) — R/W. This bit is used to determine the states of SLP_S3#, SLP_S4#,

and SLP_S5# after a CF9 hard reset (SYS_RST =1 and RST_CPU is set to 1), after PCH_PWROK

going low (with RSMRST# high), or after two TCO timeouts.

0 = PCH will keep SLP_S3#, SLP_S4# and SLP_S5# high.

1 = PCH will drive SLP_S3#, SLP_S4# and SLP_S5# low for 3 – 5 seconds.

Note: When this bit is set, it also causes the full power cy cle (SLP_S3/4/5# assertion) in response

to SYS_RESET#, PCH_PWROK#, and Watchdog timer reset sources.

2Reset Processor(RST_CPU) — R/W. When this bit transitions from a 0 to a 1, it initiates a hard or

soft reset, as determined by the SYS_RST bit (bit 1 of this register).

System Reset (SYS_RST) — R/W. This bit is used to determine a hard or soft reset to the

processor.

0 = When RST_CPU bit goes from 0 to 1, the PCH performs a soft reset by activating INIT# for 16

PCI clocks.

1 = W hen RST_CPU bit goes from 0 to 1, the PCH performs a hard reset by activating PLTRST#

0active for a minimum of about 1 milliseconds . In this case, SLP_S3#, SLP_S4# and SLP_S5#

state (assertion or d eas sertion ) de pend s on FULL_RST bit sett ing. Th e PCH main power well is

reset when this bit is 1. It also resets the resume well bits (except for those noted throughout

the datasheet).

0Reserved

Table 13-9. Power Management PCI Register Address Map (PM—D31:F0) (Sheet 1 of 2)

Offset Mnemonic Register Name Default Type

A0h-A1h GEN_PMCON_1 General Power Management

Configuration 1 0000h R/W, R/WO, RO

A2h GEN_PMCON_2 General Power Management

Configuration 2 00h RO, R/WC, R/W

A4h-A5h GEN_PMCON_3 General Power Management

Configuration 3 4206h R/W, R/WL

A6h GEN_PMCON_LOCK General Power Management

Configuration Lock 00h RO, R/WL, R/WS

A9h CIR4 Chipset Initialization Register 4 03h R/W

LPC Interface Bridge Registers (D31:F0)

444 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

13.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register

(PM—D31:F0)

Offset Address: A0h Attribute: R/W, RO, R/WO

Default Value: 0000h Size: 16-bit

Lockable: No Usage: ACPI, Legacy

Power Well: Core

AAh BM_BREAK_EN_2 BM_BREAK_EN Register #2 00h R/W, RO

ABh BM_BREAK_EN BM_BREAK_EN 00h R/W, RO

B8–BBh GPI_ROUT GPI Route Control 00000000h R/W

Table 13-9. Power Management PCI Register Address Map (PM—D31:F0) (Sheet 2 of 2)

Offset Mnemonic Register Name Default Type

Bit Description

15:12 Reserved

11 GEN_PMCON_1 Field 1 — R/W. BIOS must program this field to 1b.

BIOS_PCI_EXP_EN — R/W. This bit acts as a global enable for the SCI associated with the

PCI Express* ports.

0 = The various PCI Express* ports and processor cannot cause the PCI_EXP_STS bit to go

active.

1 = The various PCI Express* ports and processor can cause the PCI_EXP_STS bit to go

active.

9PWRBTN_LVL — RO. This bit indicates the current state of the PWRBTN# signal.

0 = Low.

1 = H igh.

8:5 Reserved

4SMI_LOCK — R/WS. When this bit i s set, writes to the GLB_SMI_EN bit (PMBASE + 30h, bit 0)

will have no effect. Once the SMI_LOCK bit is set, writes of 0 to SMI_LOCK bit will have no

effect (that is, once set, this bit can only be cleared by PLTRST#).

3:2 Reserved

1:0

Periodic SMI# Rate Select (PER_SMI_SEL) — R/W. Set by software to control the rate at

which periodic SMI# is generated.

00 = 64 seconds

01 = 32 seconds

10 = 16 seconds

11 = 8 seconds

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 445

Datasheet

13.8.1.2 GEN_PMCON_2—General PM Configuration 2 Register

(PM—D31:F0)

Offset Address: A2h Attribute: RO, R/WC, R/W

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI, Legacy

Power Well: Resume

Bit Description

DRAM Initialization Bit — R/W. This bit does not affect hardware functionality in any wa y. BIOS is

expected to set this bit prior to starting the DRAM initialization sequence and to clear this bit after

completing the DRAM initialization sequence. BIOS can detect that a DRAM initialization sequence

was interrupted by a reset by reading this bit during the boot sequence.

• If the bit is 1, then the DRAM initialization was interrupted.

• This bit is reset by the assertion of the RSMRST# pin.

6Reserved

Memory Placed in Self-Refresh (MEM_SR) — RO.

• If the bit is 1, DRAM should have remained powered and held in Self-Refresh through the last

power state transition (that is, the last time the system left S0).

• This bit is reset by the assertion of the RSMRST# pin.

System Reset Status (SRS) — R/WC. Software clears this bit by writing a 1 to it.

0 = SYS_RESET# button Not pressed.

1 = PCH sets this bit when the SYS_RESET# button is pressed. BIOS is expected to read this bit

and clear it, if it is set.

Notes:

1. This bit is also reset by RSMRST# and CF9h resets.

2. The SYS_RESET# is implemented in the Main power well. This pin must be properly isolated

and masked to prevent incorrectly setting this Suspend well status bit.

Processor Thermal Trip Status (CTS) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set when PLTRST# is inactive and THRMTRIP# goes active while the system is in an

S0 or S1 state.

Notes:

1. This bit is also reset by RSMRST#, and CF9h resets. It is not reset by the shutdown and

reboot associated with the Processor THRMTRIP# event.

2. The CF9h reset in the description refers to CF9h type core well reset which includes

SYS_RESET#, PCH_P WROK/SYS_PWROK low , SMBus hard reset, TCO T imeout. This ty pe of

reset will clear CTS bit.

Minimum SLP_S4# Assertion Width Violation Status — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = Hardware sets this bit when the SLP_S4# assertion width is less than the time programmed in

the SLP_S4# Minimum Assertion Width field (D31:F0:Offset A4h:bits 5:4). The PCH begins the

timer when SLP_S4# is asserted during S4/S5 entry or when the RSMRST# input is deasserted

during SUS well power-up. Note that this bit is functional regardless of the values in the

SLP_S4# Asse rtion Stretch E nable (D31:F0:Offs et A4h:bit 3) and in the Di sable SLP Stretching

after SUS Well Power Up (D31:F0:Offset A4h:bit 12).

Note: This bit is reset by the assertion of the RSMRST# pin, but can b e set in some cases bef ore

the default value is readable.

SYS_PWROK Failure (SYSPWR_FLR) — R/WC.

0 = This bit will be cleared only be software writing a 1 back to the bit or by SUS well power loss.

Note: This bit will be set an y time SYS_PWROK drops unexpectedly when the system was in S0 or

S1 state.

PCH_PWROK Failure (PWROK_FLR) — R/WC.

0 = This bit will be cleared only be software writing a 1 back to the bit or by SUS well power loss.

1 = This bit will be set any time PCH_PWROK goes low when the system was in S0 or S1 state.

Note: See Chapter 5.14.9.3 for more details about the PCH_PWROK pin functionality.

LPC Interface Bridge Registers (D31:F0)

446 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

13.8.1.3 GEN_PMCON_3—General PM Configuration 3 Register

(PM—D31:F0)

Offset Address: A4h Attribute: R/W, R/WC

Default Value: 4206h Size: 16-bit

Lockable: No Usage: ACPI, Legacy

Power Well: RTC, SUS

Bit Description

PME B0 S5 Disable (PME_B0_S5_DIS)— R/W. When set to '1', this bit blocks wake events

from PME_B0_STS in S5, regardless of the state of PME_B0_EN. When cleared (default), wake

events from PME_B0_STS are allowed in S5 if PME_B0_EN = '1'.

Wakes from power states other than S5 are not affected by this policy bit.

The net effect of setting PME_B0_S5_DIS = '1' is described by the truth table below:

Y = Wake; N = Don't wake; B0 = PME_B0_EN; OV = WOL Enable Override

This bit is cleared by the RTCRST# pin.

SUS Well Power Failure (SUS_PWR_FLR) — R/WC.

0 = S oftware writes a 1 to this bit to clear it.

1 = This bit is set to ‘1’ whenever SUS well power is lost, as indicated by RSMRST# assertion.

Note: This bit is in the SUS well, and defaults to ‘1’ based on RSMRST# assertion (not

cleared by any type of reset).

WOL Enable Override(WOL_EN_OVRD) — R/W.

0 = WOL policies are determined by PMEB0 enable bit and appropriate LAN status bits

1 = Enable appropriately configured integrated LAN to wake the system in S5 only regardless

of the value in the PME_B0_EN bit in the GPE0_EN register.

Note: This bit is cleared by the RTCRST# pin.

Disable SLP Stretching After SUS Well Power Up (DIS_SLP_STRCH_SUS_UP): R/W

0 = Enables stretching on SLP signals after SUS power failure as enabled and configured in

other fields.

1 = D isables stretching on SLP signals when powering up after a SUS well power loss.

regardless of the state of the SLP_S4# Assertion Stretch Enable (bit 3).

This bit is cleared by the RTCRST# pin.

Notes:

1. This field is RO when the SLP Stretching Policy Lock-Down bit is set.

2. If this bit is cleared, SLP stretch timers start on SUS well power up (the PCH has no

ability to count stretch time while the SUS well is powered down).

3. This policy bit has a different effect on SLP_SUS# stretching than on the other SLP_*

pins since SLP_SUS# is the control signal for one of the scenarios where SUS well

power is lost (Deep S4/S5). The effect of setting this bit to '1' on:

— SLP_S3# and SLP_S4# stretching: disabled after any SUS power loss.

— SLP_SUS# stretching: disabled after G3, but no impact on Deep S 4 / S5.

11:10

SLP_S3# Minimum Assertion Width: R/W This 2-bit v alue indicates the minimum assertion

width of the SLP_S3# signal to ensure that the Main power supplies have been fully power-

cycled.

Valid Settings are:

00 = 60 us

01 = 1 ms

10 = 50 ms

11 = 2 s

This bit is cleared by the RSMRST# pin.

Note: This field is RO when the SLP Stretching Policy Lock-Down bit is set.

B0/OV S1/S3/S4 S5

00 N N

01 N Y (LAN only)

11 Y (all PME B0 sources) Y (LAN only)

01 Y (all PME B0 sources) N

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 447

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General Reset Status (GEN_RST_STS) — R/WC. This bit is set by hardware whenever

PLTRST# asserts for any reason other than going into a software-entered sleep state (using

PM1CNT.SLP_EN write) or a suspend well power failure (RSMRST# pin assertion).

BIOS is expected to consult and then write a 1 to clear this bit during the boot flow before

determining what action to take based on PM1_STS.W AK _STS = 1. If GEN_RST_STS = ‘1’, the

cold reset boot path should be followed rather than the resume path, regar dle ss of th e se tting

of WAK_STS.

This bit is cleared by the RSMRST# pin.

SLP_LAN# Default Value (SLP_LAN_DEFAULT) — R/W. This bit specifies the value to drive

on the SLP_LAN# pin when in Sx/Moff and Intel ME FW nor host BIOS has configured

SLP_LAN# as an output. When this bit is set to 1 SLP_LAN# will default to be driven high,

when set to 0 SLP_LAN# will default to be driven low.

This bit will always determine SLP_LAN# beha vior when in S4/S5/Moff after SUS power loss, in

S5/Moff after a host partition reset with power down and when in S5/Moff due to an

unconditional power down.

This bit is cleared by RTCRST#.

7:6

SWSMI_RATE_SEL — R/W. This field indicates when the SWSMI timer will time out.

Valid values are:

00 = 1.5 ms ± 0.6 ms

01 = 16 ms ± 4 ms

10 = 32 ms ± 4 ms

11 = 64 ms ± 4 ms

These bits are not cleared by any type of reset except RTCRST#.

5:4

SLP_S4# Minimum Assertion Width — R/W. This field indicates the minimum assertion

width of the SLP_S4# signal to ensure that the DRAM modules have been safely power-cycled.

Valid values are:

11 = 1 second

10 = 2 seconds

01 = 3 seconds

00 = 4 seconds

This value is used in two ways:

1. If the SLP_S4# assertion width is ever shorter than this time, a status bit is set for

BIOS to read when S0 is entered.

2. If enabled by bit 3 in this register, the hardw are will prev ent the SLP_S4# signal from

deasserting within this minimum time period after asserting.

RTCRST# forces this field to the conservative default state (00b).

Notes:

1. This field is RO when the SLP Stretching Policy Lock-Down bit is set.

2. Note that the logic that measures this time is in the suspend power well. Therefore,

when leaving a G3 or Deep S4/S5 state, the minimum time is measured from the

deassertion of the internal suspend well reset (unless the “Disable SLP Stretching

After SUS Well Power Up” bit is set).

SLP_S4# Assertion Stretch Enable — R/W.

0 = The SLP_S4# minimum assertion tim e is defined in Power Sequenc i ng and Reset Signal

Timings table.

1 = The SLP_S4# signal minimally assert for the time specified in bits 5:4 of this register.

This bit is cleared by RTCRST#.

Note: This bit is RO when the SLP Stretching Policy Lock-Down bit is set.

Bit Description

LPC Interface Bridge Registers (D31:F0)

448 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

Note: RSMRST# is sampled using the R TC clock. Therefore, low times that are less than one RTC clock period

may not be detect ed by the PCH.

13.8.1.4 GEN_PMCON_LOCK- General Power Management Configuration Lock

Offset Address: A6h Attribute: RO, R/WLO

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI

Power Well: Core

13.8.1.5 Chipset Initialization Register 4 (PM—D31:F0)

Offset Address: A9h Attribute: R/W

Default Value: 03h Size: 8-bit

Lockable: No Usage: ACPI, Legacy

Power Well: Core

2RTC Power Status (RTC_PWR_STS) — R/W. This bit is set when RT CRST# indicates a weak

or missing battery. The bit is not cleared by any type of reset. The bit will remain set until the

software clears it by writing a 0 back to this bit position.

Power Failure (PWR_FLR) — R/WC. This bit is in the DeepS4/S5 well and defaults to 1

based on DPWROK deassertion (not cleared by any type of reset).

0 = Indicates that the trickle current has not failed since the last time the bit was cleared.

Software clears this bit by writing a 1 to it.

1 = Indicates that the trickle current (from the main battery or trickle supply) was remo ved or

failed.

Note: Clearing CMOS in a PCH-based platform can be done by using a jumper on RTCRST#

or GPI. Implementations should not attempt to clear CMOS by using a jumper to pull

VccRTC low.

AFTERG3_EN — R/W . This bit determines what state to go to when power is re-applied after a

power failure (G3 state). This bit is in the RTC well and is only cleared by RTCRST# assertion.

0 = System will return to S0 state (boot) after power is re-applied.

1 = System will return to the S5 state (except if it was in S4, in which case it will return to

S4). In the S5 state, the onl y enabled wake event is the Power Button or any enabled

wake event that was preserved through the power failur e.

Bit Description

7:3 Reserved

SLP Stretching Policy Lock-Down(SLP_STR_POL_LOCK) — R/WLO. R/WLO. When set to

1, this bit locks down the Disable SLP Stretching After SUS Well Power Up, SLP_S3# Minimum

Assertion Width, SLP _S4# Minimum Asse rtion Widt h, SLP_S4# As ser tion Stre tch En able bi ts in

the GEN_PMCON_3 register, making them read-only.

This bit becomes locked when a value of 1b is written to it. Writes of 0 to this bit are always

ignored.

This bit is cleared by platform reset.

ACPI_BASE_LOCK — R/WLO. When set to 1, this bit locks down the ACPI Base Address

This bit becomes locked when a value of 1b is written to it. Writes of 0 to this bit are always

ignored. Once locked by writing 1, the only way to clear this bit is to perform a platform reset.

0Reserved

Bit Description

7:0 CIR4 Field 1 — R/W. BIOS must program this field to 47h.

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 449

Datasheet

13.8.1.6 BM_BREAK_EN Register #2(PM—D31:F0)

Offset Address: AAh Attribute: R/W , RO

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI, Legacy

Power Well: Core

13.8.1.7 BM_BREAK_EN Register (PM—D31:F0)

Offset Address: ABh Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI, Legacy

Power Well: Core

13.8.1.8 GPIO_ROUT—GPIO Routing Control Register

(PM—D31:F0)

Offset Address: B8h – BBh Attribute: R/W

Default Value: 00000000h Size: 32-bit

Lockable: No Power We ll: Resume

Bit Description

7:1 Reserved

0SATA3 Break Enable (SATA3_BREAK_EN) — R/W

0 = SATA3 traffic will not cause BM_STS to be set.

1 = SATA3 traffic will cause BM_STS to be set.

Bit Description

7Storage Breka Enable (STORAGE_BREAK_EN) — R/W.

0 = Serial ATA traffic will not cause BM_STS to be set..

1 = Serial ATA traffic will cause BM_STS to be set.

6PCIE_BREAK_EN — R/W.

0 = PCI Express* traffic will not cause BM_STS to be set..

1 = PCI Express* traffic will cause BM_STS to be set.

5PCI_BREAK_EN — R/W.

0 = PCI traffic will not cause BM_STS to be set..

1 = PCI traffic will cause BM_STS to be set.

4:3 Reserved

2EHCI_BREAK_EN — R/W.

0 = EHCI traffic will not cause BM_STS to be set..

1 = EHCI traffic will cause BM_STS to be set.

1Reserved

0HDA_BREAK_EN — R/W.

0 = Intel ® High Definition Audio traffic will not cause BM_STS to be set.

1 = Intel ® High Definition Audio traffic will cause BM_STS to be set.

Bit Description

31:30 GPIO15 Route — R/W. See bits 1:0 for description.

Same pattern for GPIO14 through GPIO3

LPC Interface Bridge Registers (D31:F0)

450 Intel® C600 Series Chipset and Intel® X79 Express Chipset

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Note: GPIOs that are not implemented will not have the corresponding bits implemented in

this register.

13.8.2 APM I/O Decode

Table 13-10 shows the I/O registers associated with APM support. This register space is

enabled in the PCI Device 31: Function 0 space (APMDEC_EN), and cannot be moved

(fixed I/O location).

13.8.2.1 APM_CNT—Advanced Power Management Control Port Register

I/O Address: B2h Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Usage: Legacy Only

Power Well: Core

13.8.2.2 APM_STS—Advanced Power Management Status Port Register

I/O Address: B3h Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Usage: Legacy Only

Power Well: Core

5:4 GPIO2 Route — R/W. See bits 1:0 for description.

3:2 GPIO1 Route — R/W. See bits 1:0 for description.

1:0

GPIO0 Route — R/W. GPIO can be routed to cause an NMI, SMI# or SCI when the GPIO[n]_STS bit

is set. If the GPIO0 is not set to an input, this field has no effect.

If the system is in an S1–S5 state and if the GPE0_EN bit is also set, then the GPIO can cause a

Wake event, even if the GPIO is NOT routed to cause an NMI, SMI# or SCI.

00 = No effect.

01 = SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)

10 = SCI (if corresponding GPE0_EN bit is also set)

11 = NMI (If corresponding GPI_NMI_EN is also set)

Bit Description

Table 13-10. APM Register Map

Address Mnemonic Register Name Default Type

B2h APM_CNT Advanced Power Management Control Port 00h R/W

B3h APM_STS Advanced Power Management Status Port 00h R/W

Bit Description

7:0 Used to pass an APM command between the OS and the SMI handler. Writes to this port not only

store data in the APMC register, but also generates an SMI# when the APMC_EN bit is set.

Bit Description

7:0 Used to pass data between the OS and the SMI handler. Basically, this is a scratchpad register and is

not affected by any other register or function (other than a PCI reset).

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 451

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13.8.3 Power Management I/O Registers

Table 13-11 shows the registers associated with ACPI and Legacy power management

support. These registers locations are all offsets from the ACPI base address defined in

the PCI Device 31: Function 0 space (PMBASE), and can be moved to any 128-byte

aligned I/O location. In order to access these registers, the ACPI Enable bit(ACPI_EN)

must be set. The registers are defined to be compliant with the ACPI 3.0b specification,

and generally use the same bit names.

Note: All reserved bits and registers will always return 0 when read, and will have no effect

when written.

Table 13-11. ACPI and Legacy I/O Register Map

PMBASE

+ Offset Mnemonic Register Name Default Type

00h–01h PM1_STS PM1 Status 0 000h R/WC

02h–03h PM1_EN PM1 Enable 0000h R/W

04h–07h PM1_CNT PM1 Control 00000000h R/W, WO

08h–0Bh PM1_TMR PM1 Timer xx000000h RO

20-27h GPE0_STS General Purpose Event 0 Status 00000000

00000000h R/WC

28-2Fh G PE0_EN General Purpose Event 0a Enables 00000000

00000000h R/W

30h–33h SMI_EN SMI# Control and Enable 00000002h R/W, WO,

R/WO

34h–37h SMI_STS SMI Status 00000000h R/WC, RO

38h–39h ALT_GP _SMI_EN Alternate GPI SMI Enable 0000h R/W

3Ah–3Bh ALT_GP_SMI_STS Alternate GPI SMI Status 0000h R/WC

3Ch-3Dh UPRWC USB Per-Po rt Registers Write Control 0000h R/WC, R/W,

R/WO

42h GPE_CNTL General Purpose Event Control 00h R/W

44h–45h DEVTRAP_STS Device Trap Status Status 0000h R/WC

50h PM2_CNT Power Management 2 Control 00h R/W

60h–7Fh — Reserved for TCO — —

LPC Interface Bridge Registers (D31:F0)

452 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

13.8.3.1 PM1_STS—Power Management 1 Status Register

I/O Address: PMBASE + 00h

Attribute: R/WC

Default Value: 0000h Size: 16-bit

Lockable: No Usage: ACPI or Legacy

Power Well: Bits 0–7: Core,

Bits 12-15: Resu m e

Bit 11: RTC,

Bits 8 and 10: DSW

If bit 10 or 8 in this register is set, and the corresponding _EN bit is set in the PM1_EN

already in an S0 state when the event occurs), the PCH will also generate an SCI if the

SCI_EN bit is set, or an SMI# if the SCI_EN bit is not set.

Note: Bit 5 does not cause an SMI# or a wake event. Bit 0 does not cause a wake event but

can cause an SMI# or SCI.

Bit Description

Wake Status (WAK_STS) — R/WC. This bit is not affected by hard resets caused by a CF9

write, but is reset by RSMRST#.

0 = Software clears this bit by writing a 1 to it.

1 = Set by hardware when the system is in one of the sleep states (using the SLP_EN bit) and

an enabled wake event occurs. Upon setting this bit, the PCH will transition the system to

the ON s tate.

If the AFTERG3_EN bit is not set and a power failure (such as re moved batte ries) occurs witho ut

the SLP_EN bit set, the system will return to an S0 state when power returns, and the WAK_STS

bit will not be set.

If the AFTERG3_EN bit is set and a power failure occurs without the SLP_EN bit having been set,

the system will go into an S5 state when power returns, and a subsequent wake event will cause

the WAK_STS bit to be set. Note that any subsequent wake event would have to be caused by

either a Power Button press, or an enabled wake event that was preserved through the power

failure (enable bit in the RTC w ell).

PCI Express* Wake Status (PCIEXPWAK_STS) — R/WC.

0 = Software clears this bit by writing a 1 to it. If the WAKE# pin is still active during the write

or the PME message received indication has not been cleared in the root port, then the bit

will remain active (that is, all inputs to this bit are level-sensitive).

1 = This bit is set by hardware to indicate that the system woke due to a PCI Express* wakeup

event. This wakeup event ca n be caused by the PCI Express* WAKE# pin being active or

receipt of a PCI Express * PME mess age at a ro ot port . This b it is set only when on e of the se

events causes the system to tr ansition fro m a non-S0 system power state to the S0 system

power state. This bit is set independent of the state of the PCIEX P_WAKE_D I S bit.

Note: This bit does not itself cause a wake event or prevent entry to a sleeping state. Thus, if

the bit is 1 and the system is put into a sleeping state, the system will not automatically

wake.

13:12 Reserved

Power Button Override Status (PWRBTNOR_STS) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set any time a P ower Button Override oc curs (that is, the power button is pressed

for at least 4 consecutive seconds), due to the corresponding bit in the SMBus slave

message, Intel ME Initiated P ower Button Override, Intel ME Initiated Host R eset with P ower

down or due to an internal thermal sensor catastrophic condition. The power button

override causes an unconditional transition to the S5 state. The BIOS or SCI handler clears

this bit by writing a 1 to it. This bit is not affected by hard resets using CF9h writes, and is

not reset by RSMRST#. Thus, this bit is preserved through power failures. Note that if this

bit is still asserted when the global SCI_EN is set then an SCI will be generated.

Note: Upon entry to S5 due to an event described above, if Deep S4/S5 is enabled and

conditions are met per Section 5.14.6.6, the system will transition to Deep S4/S5.

RTC Status (RTC_STS) — R/WC. This bit is not affected by hard resets caused by a CF9 write,

but is reset by DPWROK.

0 = Software clears this bit by writing a 1 to it.

1 = Set by hardware when the RTC generates an alarm (assertion of the IRQ8# signal).

Additionally if the R T C_EN bit (PMBASE + 02h, bi t 10) is set, the setting of the RTC_STS bit

will generate a wake event.

9 Reserved

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 453

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Power Button Status (PWRBTN__STS) — R/WC. This bit is not affected by hard resets

caused by a CF9 w rite but is reset by DPWROK

0 = If the PWRBTN# signal is held low for more than 4 seconds, the hardware clears the

PWRBTN_STS bit, sets the PWRBTNOR_STS bit, and the system transitions to the S5 state

with only PWRBTN# enabled as a wake event.

This bit can be cleared by software by writing a one to the bit position.

1 = This bit is set by hardware when the PWRBTN# signal is asserted Low, independent of any

other enable bit.

In the S0 state, while PWRBTN_EN and PWRBTN_STS are both set, an SCI (or SMI# if

SCI_EN is not set) will be generated.

In any sleeping state S1–S5, while PWRBTN_EN (PMBASE + 02h, bit 8) and PWRBTN_STS

are both set, a wake event is generated.

Notes:

1. If the PWRBTN_STS bit is cleared by software while the PWRBTN# signal is sell

asserted, this will not cause t he PWRBN_STS bit to be set. The PWRBTN# signal must go

inactive and active again to set the PWRBTN_STS bit.

2. Upon entry to S5 due to a power button override, if Deep S4/S5 is enabled and

conditions are met per Section 5.14.6.6, the system will transition to Deep S4/S5.

7:6 Reserved

Global Status (GBL _STS) — R/WC.

0 = T he SCI handler should then clear this bit by writing a 1 to the bit location.

1 = Set when an SCI is generated due to BIOS wanting the attention of the SCI handler. BIOS

has a corresponding bit, BIOS_RLS, which will cause an SCI and set this bit.

Bus Master Status (BM_STS) — R/WC. This bit will not cause a wake event, SCI or SMI#.

0 = S oftware clears this bit by writing a 1 to it.

1 = Set by the PCH when a PCH-visible bus master requests access to memory or the

BM_BUSY# signal is active.

3:1 Reserved

Timer Overflow Status (TMROF_STS) — R/WC.

0 = T he SCI or SMI# handler clears this bit by writing a 1 to the bit location.

1 = This bit gets set an y time bit 22 of the 24-bit timer goes h igh (bits ar e numbered from 0 to

23). This will occur every 2.3435 seconds. When the TMROF_EN bit (PMBASE + 02h, bit 0)

is set, then the setting of the TMROF_STS bit will additionally generate an SCI or SMI#

(depending on the SCI_EN).

Bit Description

LPC Interface Bridge Registers (D31:F0)

454 Intel® C600 Series Chipset and Intel® X79 Express Chipset

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13.8.3.2 PM1_EN—Power Management 1 Enable Register

I/O Address: PMBASE + 02h Attribute: RO; R/W

Default Value: 0000h Size: 16-bit

Lockable: No Usage: ACPI or Legacy

Power Well: Bits 0–7: Core,

Bits 8-9, 11–15: Resume,

Bit 10: RTC

Bit Description

15 Reserved

PCI Express* Wake Disable(PCIEXPWAK_DIS) — R/W. Modification of this bit has no impact

on the value of the PCIEXP_WAKE_STS bit.

0 = Inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register enabled to wake the system.

1 = Inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register disabled from waking the

system.

13:11 Reserved

RTC Alarm Enable (RTC_EN) — R/W. This bit is in the RTC well to allow an RTC event to wake

after a power failure. In addition to being cleared b y RTCRST# assertion, the PCH also clears this bit

due to a Power Button Override event, Intel ME Initiated Power Button Override, Intel ME Initiated

Host Reset with Power down, SMBus unconditional power down, Processor thermal trip event, or

due to an internal thermal sensor catastrophic condition.

0 = No SCI (or SMI#) or wake event is generated then RTC_STS (PMBASE + 00h, bit 10) goes

active.

1 = An SCI (or SMI#) or wake event will occur when this bit is set and the RTC_STS bit goes active.

9 Reserved.

Power Button Enable (PWRBTN_EN) — R/W. This bit is used to enable the setting of the

PWRBTN_STS bit to generate a power ma nagement event (SMI#, SCI). PWRBTN_EN has no effect

on the PWRB TN_STS bit (PMB ASE + 00h, bit 8) bein g set by the assertion o f the power but ton. The

Power Button is always enabled as a Wake event.

0 = Disable.

1 = Enable.

7:6 Reserved.

Global Enable (GBL_EN) — R/W. When both the GBL_EN and the GBL_STS bit (PMBASE + 00h,

bit 5) are set, an SCI is raised.

0 = Disable.

1 = Enable SCI on GBL_STS going active.

4:1 Reserved.

Timer Overflow Interrupt Enable (TMROF_EN) — R/W. Works in conjunction with the SCI_EN

bit (PMBASE + 04h, bit 0) as described below:

TMROF_EN SCI_EN Effect when TMROF_STS is set

0 X No SMI# or SCI

10 SMI#

11 SCI

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 455

Datasheet

13.8.3.3 PM1_CNT—Power Management 1 Control

I/O Address: PMBASE + 04h Attribute: R/W, WO

Default Value: 00000000h Size: 32-bit

Lockable: No Usage: ACPI or Legacy

Power Well: Bits 0–7: Core,

Bits 8–12: RTC,

Bits 13-15: Resume

Bit Description

31:14 Reserved.

13 Sleep Enable (SLP_EN) — WO. Setting this bit causes the system to sequence into the Sleep

state defined by the SLP_TYP field.

12:10

Sleep Type (SLP_TYP) — R/W. This 3-bit field de fines the type of Sle ep the system should

enter when the SLP_EN bit is set to 1. These bits are only reset by RTCRST#.

9:3 Reserved.

Global Release (GBL_RLS) — WO.

0 = This bit always reads as 0.

1 = ACPI software writes a 1 to this bit to raise an event to the BIOS. BIOS software has a

corresponding enable and status bits to control its ability to receive ACPI events.

Bus Master Reload (BM_RLD) — R/W. This bit is treated as a scratchpad bit. his bit is reset to

0 by PLTRST#

0 = Bus m aster requests will not cause a break from the C3 state.

1 = Enables Bus Master requests (internal or exte rnal) to cause a break from the C3 state.

If software fails to set this bit before going to C3 state, the PCH will still return to a snoopable

state from C3 or C4 states due to bus master activity.

SCI Enable (SCI_EN) — R/W. Selects the SCI interrupt or the SMI# interrupt for various

events including the bits in the PM1_STS register (bit 10, 8, 0), and bits in GPE0_STS.

0 = These events will generate an SMI#.

1 = These events will generate an SCI.

Code Master Interrupt

000b ON: Typically maps to S0 state.

001b Puts CPU in S1 state.

010b Reserved

011b Reserved

100b Reserved

101b Suspend-To-RAM. Assert SLP_S3#: Typically maps to S3 state.

110b Suspend-To-Disk. Assert SLP_S3#, and SLP_S4#: Typically maps to S4 state.

111b Soft Off. Assert SLP_S3#, SLP_S4#, and SLP_S5#: Typically maps to S5 state.

LPC Interface Bridge Registers (D31:F0)

456 Intel® C600 Series Chipset and Intel® X79 Express Chipset

Datasheet

13.8.3.4 PM1_TMR—Power Management 1 Timer Register

I/O Address: PMBASE + 08h

Attribute: RO

Default Value: xx000000h Size: 32-bit

Lockable: No Usage: ACPI

Power Well: Core

13.8.3.5 GPE0_STS—General Purpose Event 0a Status Register

I/O Address: PMBASE + 20h Attribute: R/WC; RO

Default Value: 0000000000000000h Size: 64-bit

Lockable: No Usage: ACPI

Power Well: Bits 0-34, 56-63: Resume,

Bit 35: DSW

This register is symmetrical to the General Purpose Ev ent 0a Enab le Register. Unless

indicated otherwise below, if the corresponding _EN bit is set, then when the _STS bit

get set, the PCH will generate a Wake Event. Once back in an S0 state (or if already in

an S0 state when the event occurs), the PCH will also generate an SCI if the SCI_EN bit

is set, or an SMI# if the SCI_EN bit (PMBASE + 04h, bit 0) is not set.

Bits 15:0 should not be reset by CF9 write. Bits 31:16 are reset by CF9h full resets.

Bit Description

31:24 Reserved

23:0

Timer Value (TMR_VAL) — RO. Returns the runn ing count of the PM timer. This counter runs off a

3.579545 MHz clock (14.31818 MHz divided by 4). It is reset to 0 during a PCI reset, and then

continues counting as long as the system is in the S0 state. After an S1 state, the counter will not

be reset (it will continue counting from the last value in S0 state.

Anytime bit 22 of the timer goes HIGH to LOW (bits referenced from 0 to 23), the TMROF_STS bit

(PMBASE + 00h, bit 0) is set. The High-to-Low transition will occur every 2.3435 seconds. If the

TMROF_EN bit (PMBASE + 02h, bit 0) is set, an SCI interrupt is also generated.

Bit Description

63:36 Reserved.

GPIO27_STS— R/WC.

0 = Disable.

1 = Set by hardware and can be reset by writing a one to this bit position or a resume well reset.

This bit is set at the level specified in GP27IO_POL. Note that GPIO27 is always monitored as

an input for the purpose of setting this bit, regardless of the actual GPIO configuration.

34:32 Reserved.

31:16

GPIOn_STS — R/WC.

0 = S oftware clears this bit by writing a 1 to it.

1 = T hese bits are set any time the corresponding GPIO is set up as an input and the

corresponding GPIO signal is high (or low if the corresponding GP_INV bit is set). If the

corresponding enable bit is set in the GPE0_EN register, then when the GPIO[n]_STS bit is

set:

• If the system is in an S1–S5 state, the event will also wake the system.

• If the system is in an S0 state (or upon waking back to an S0 state), a SCI will be caused

depending on the GPIO_ROUT bits (D31:F0:B8h, bits 31:30) for the corresponding GPI.

Note: Mapping is as follows: bit 31 corresponds to GPIO[15]... and bit 16 corresponds to

GPIO[0].

15:14 Reserved

LPC Interface Bridge Registers (D31:F0)

Intel® C600 Series Chipset and Intel® X79 Express Chipset 457

Datasheet

Power Management Event Bus 0 Status (PME_B0_STS) — R/WC

This bit will be set to 1 by the Intel PCH when any internal device with PCI Power Management

capabilities on bus 0 asserts the equivalent of the PME# signal. Additionally, if the PME_B0_EN

and SCI_EN bits are set, and the system is in an S0 state, then the setting of the PME_B0_STS bit

will generate an SCI (or SMI# if SCI_EN is not set). If the PME_B0_EN bit is set, and the system

is in an S1-S4 state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the

PME_B0_STS bit will generate a wake event, If the system is in an S5 state due to power button

override, then the PME_B0_STS bit will not cause a wake event or SCI.

The default for this bit is 0. This bit is cleared by a software write of '1'.

The following are internal devices which can set this bit:

•Intel HD Audio

• Intel ME “maskable” wake events

•Integrated LAN

•SATA

•EHCI

12 Reserved

PME_STS — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = Set by hardware when the PME# signal goes active. Additionally, if the PME_EN and SCI_EN

bits are set, and the system is in an S0 state, then the setting of the PME_STS bit will

generate an SCI (or SMI# if SCI_EN is not set). If the PME_EN bit is set, and the system is in

an S1–S4 state (or S5 state due to setting SLP_TYP and SLP_EN), then the setting of the

PME_STS bit will generate a wake event. If the sy stem is in an S5 state due to power button

override or a power failure, then PME_STS will not cause a wake event or SCI.

10 Reserved.

PCI_EXP_STS — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = S et by hardware to indicate that:

• The PME event message was received on one or more of the PCI Express* ports

• An Assert PMEGPE message received from the Processor using DMI

Notes:

1. The PCI WAKE# pin has no impact on th is bit.

2. If the PCI_EXP_STS bit went active due to an Assert PMEGPE message, then a Deassert

PMEGPE message must be received prior to the software write in order for the bit to be

cleared.

3. If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the level-triggered

SCI will remain active.

4. A race condition exists where the PCI Express* device sends another PME message

because the PCI Express* device was not serviced within the time when it must resend

the message. This may result in a spurious interrupt, and this is comprehended and

approved by the PCI Express* specification. The window for this race condition is

approximately 95-105 milliseconds.

8RI_STS — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = Set by hardware when the RI# input signal goes active.

SMBus Wake Status (SMB_WAK_STS) — R/WC. The SMBus controller can independently

cause an SMI#, so this bit does not need to do so (unlike the other bits in this re gister). Softw are

clears this bit by writing a 1 to it.

0 = Wake event Not caused by the PCH’s SMBus logic.

1 = S et by hardware to indicate that the wake event was caused by the PCH’s SMBus logic.This

bit will be set by the WAKE/SMI# command type, even if the system is already awake. The

SMI handler should then clear this bit.

Notes:

1. The SMBus co ntroller will indepe ndently cause an SMI# so this bit doe s not need to do so

(unlike the other bits in this register).

2. This bit is set by the SMBus slave command 01h (Wake/SMI#) even when the system is

in the S0 state. Therefore, to avoid an instant wake on subsequent transitions to sleep

states, software must clear this bit after each reception of the Wake/SMI# command or

just prior to entering the sleep state.

3. The SMBALERT_STS bit (D31:F3:I/O Offset 00h:Bit 5) should be cleared by software

before the SMB_WAK_STS bit is cl eared.

Bit Description

LPC Interface Bridge Registers (D31:F0)

458 Intel® C600 Series Chipset and Intel® X79 Express Chipset