DS1855E-010+T&R - Maxim Integrated

1 of 21 19-6586; Rev 2; 1/13

FEATURES

 Two Linear Taper Potentiometers

− DS1855-010 (One 10kΩ, 100 Position

and One 10kΩ, 256 Position)

− DS1855-020 (One 10kΩ, 100 Position

and One 20kΩ, 256 Position)

− DS1855-050 (One 10kΩ, 100 Position

and One 50kΩ, 256 Position)

− DS1855-100 (One 10kΩ, 100 Position

and One 100kΩ, 256 Position)

 256 Bytes of EEPROM Memory

 Access to Data and Potentiometer Control

via a 2-Wire Interface

 External Write-Protect Pin to Protect Data

and Potentiometer Settings

 Data and Potentiometer Settings Also Can

Be Write Protected Through Software

Control

 Nonvolatile Wiper Storage

 Operates from 3V or 5V Supplies

 14-Pin TSSOP, 16-Ball CSBGA, and

14-Pin Flip-Chip Packages

 Industrial Operating Temperature:

-40ºC to +85ºC

PIN CONFIGURATIONS

DESCRIPTION

The DS1855 dual nonvolatile (NV) digital potentiometer and secure memory consists of one 100-position

linear taper potentiometer, one 256-position linear taper potentiometer, 256 bytes of EEPROM memory,

and a 2-wire interface. The DS1855, which features a new software write protect, is an upgrade of the

DS1845. The DS1855 provides an ideal method for setting bias voltages and currents in control

applications using a minimum of circuitry. The EEPROM memory allows a user to store configuration or

calibration data for a specific system or device as well as provide control of the potentiometer wiper

settings. Any type of user information may reside in the first 248 bytes of this memory. The next two

addresses of EEPROM memory are for potentiometer settings and the remaining 6 bytes of memory are

reserved. These reserved and potentiometer registers should not be used for data storage. Access to this

EEPROM is via an industry-standard 2-wire bus. The interface I/O pins consist of SDA and SCL. The

wiper position of the DS1855, as well as EEPROM data, can be write protected through hardware using

the write-protect input pin (WP) or software using the 2-wire interface.

SDA

Vcc

SCL

GND

TSSOP (173 mils)

1 2 3 4

Top View

CSBGA (4mm x 4mm)

Flip Chip (100 mils x 100 mils) (Not Shown)

DS1855

Dual Nonvolatile Digital Potentiometer

and Secure Memo

DS1855

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PIN DESCRIPTIONS

Name TSSOP BGA Description

VCC 14 A3 Power Supply Terminal. The DS1855 will support supply

voltages ranging from +2.7V to +5.5V.

GND 7 D1 Ground Terminal.

SDA 1 B2 2-Wire serial data interface. The serial data pin is for serial data

transfer to and from the DS1855. The pin is open drain and may

be wire-ORed with other open drain or open collector interfaces.

SCL 2 A2 2-Wire Serial Clock Input. The serial clock input is used to

clock data into the DS1855 on rising edges and clock data out on

falling edges.

WP 6 C1 Write Protect Input. If set to logic 0, the data in memory and the

potentiometer wiper setting may be changed. If set to logic 1, both

the memory and the potentiometer wiper settings will be write

protected. The WP pin is pulled high internally.

A0 3 A1 Address Input. Pins A0, A1, and A2 are used to specify the

address of each DS1855 when used in a multi-dropped

configuration. Up to eight DS1855s may be addressed on a single

2-wire bus.

A1 4 B1 Address Input.

A2 5 C2 Address Input.

H0 13 A4 High terminal of Potentiometer 0. For both potentiometers, it is

not required that the high terminal be connected to a potential

greater than the low terminal. Voltage applied to the high terminal

of each potentiometer cannot exceed VCC or go below ground.

H1 11 B3 High terminal of Potentiometer 1.

L0 8 D3 Low terminal of Potentiometer 0. For both potentiometers, it is

not required that the low terminal be connected to a potential less

than the high terminal. Voltage applied to the low terminal of each

potentiometer cannot exceed VCC or go below ground.

L1 10 C4 Low terminal of Potentiometer 1.

W0 9 D4 Wiper terminal of Pot 0. The wiper position of Potentiometer 0

is determined by the byte at EEPROM memory location F9h.

Voltage applied to the wiper terminal of each potentiometer cannot

exceed the power supply voltage, VCC, or go below ground.

W1 12 B4 Wiper terminal of Pot 1. The wiper position of Potentiometer 1

is determined by the byte at EEPROM memory location F8h.

NC C3 No Connect.

NC D2 No Connect.

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DS1855 BLOCK DIAGRAM Figure 1

Up to eight DS1855s can be installed on a single 2-wire bus. Access to an individual device is achieved

by using a device address that is determined by the logic levels of address pins A0 through A2.

Additionally, the DS1855 will operate from 3V or 5V supplies. Three package options are available: 14-

pin TSSOP, 16-ball CSBGA, and a flip-chip package.

VCC

GND

SDA

SCL

248 BYTES

EEPROM

MEMORY

1 BYTE WIPER

SETTING

POT 0

1 BYTE WIPER

SETTING

POT 1

CONFIGURATION

BYTE

LOCK BYTE

RESERVED

CONTROL

DATA

POTENTIOMETER 0

2-WIRE

INTERFACE

POTENTIOMETER 1

100-

Position

Pot

256-

Position

Pot

DS1855

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MEMORY ORGANIZATION

The DS1855’s serial EEPROM is internally organized with 256 words of 1 byte each. Each word requires

an 8-bit address for random word addressing. The byte at address F9h determines the wiper setting for

potentiometer 0, which contains 100 positions. Writing values above 63h to this address sets the wiper to

its uppermost position, but the MSB is ignored. The byte at address F8h determines the wiper setting for

potentiometer 1, which contains 256 positions (00h to FFh). Address locations FAh though FFh are

reserved and should not be written.

MEMORY

LOCATION

NAME OF

MEMORY

LOCATION

FUNCTION OF MEMORY LOCATION

00h – F7h

User Memory

General-purpose user memory.

F8h

Potentiometer 1 Setting

Writing to this byte controls the setting of potentiometer 1, a 256-

position pot. Valid settings are 00h to FFh.

F9h

Potentiometer 0 Setting

Writing to this byte controls the setting of potentiometer 0, a 100-

position pot. Valid settings are 00h to 63h. MSB is ignored.

FAh

Software Lock

Configuration Byte

The three lower bits in this byte can be used to set write-protection

to the 256-byte memory block.

: Writing this bit to a 1 protects the upper page of memory. If

his bit is set, memory locations F8h to FFh are configured for

write-protection.

B1: Writing this bit to a 1 protects the upper block of memory. If

this bit is set, memory locations 80h to F7h are configured for

write-protection. The upper page must be un

locked in order to

modify the locking of this portion of memory.

: Writing this bit to a 1 protects the lower block of memory. If

this bit is set, memory locations 00h to 7Fh are configured for

write-protection. The upper page must be unlocked in order to

modify the locking of this portion of memory.

B2 B1 B0

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FBh – FCh

Lock Bytes

Writing to these two bytes allows the user to lock or unlock the

memory described in byte FAh.

LOCK:

If memory location FBh is written to 56h and memory

location FCh is written to 25h, the device will enter lock mode.

Write protection will become active in the memory locations that

are specified in FAh.

UNLOCK: If memory location FBh is written to 67h and memory

location FCh is written to 36h, the device will be unlocked. Once

unlocked, the user can change the setting of memory location FAh

to affect the EEPROM write-protection.

The locking can be updated at any time as long as the upper

page is unlocked.

FD – FFh

Reserved

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2-WIRE OPERATION

Clock and Data Transitions

The SDA pin is normally pulled high with an external resistor or device. Data on the SDA pin may only

change during SCL low time periods. Data changes during SCL high periods will indicate a START or

STOP conditions depending on the conditions discussed below. Refer to the timing diagram in Figure 2

for further details.

START Condition

A high-to-low transition of SDA with SCL high is a START condition that must precede any other

command. Refer to the timing diagram in Figure 2 for further details.

STOP Condition

A low-to-high transition of SDA with SCL high is a STOP condition. After a read sequence, the stop

command places the DS1855 into a low-power mode. Refer to the timing diagram in Figure 2 for further

details.

Acknowledge

All address and data bytes are transmitted via a serial protocol. The DS1855 pulls the SDA line low

during the ninth clock pulse to acknowledge that it has received each word.

Standby Mode

The DS1855 features a low-power mode that is automatically enabled after power-on, after a STOP

command, and after the completion of all internal operations.

2-Wire Interface Reset

After any interruption in protocol, power loss, or system reset, the following steps reset the DS1855:

1. Clock up to nine cycles.

2. Look for SDA high in each cycle while SCL is high.

3. Create a START condition while SDA is high.

Device Addressing

The DS1855 must receive an 8-bit device address word following a START condition to enable a specific

device for a read or write operation. The address word is clocked into the DS1855 MSB to LSB. The

address word consists of Ah (1010) followed by A2, A1, and A0 then the read/write (R/W) bit. If the

R/W bit is high, a read operation is initiated. If the R/W is low, a write operation is initiated. For a device

to become active, the values of A2, A1, and A0 must be the same as the hard-wired address pins on the

DS1855. Upon a match of written and hard-wired addresses, the DS1855 will output a zero for one clock

cycle as an acknowledge. If the address does not match, the DS1855 returns to a low-power mode.

Write Operations

After receiving a matching address byte with the R/W bit set low, the device goes into the write mode of

operation. The master must transmit an 8-bit EEPROM memory address to the device to define the

address where the data is to be written. After the reception of this byte, the DS1855 will transmit a zero

for one clock cycle to acknowledge the receipt of the address. The master must then transmit an 8-bit data

word to be written into this address. The DS1855 will again transmit a zero for one clock cycle to

acknowledge the receipt of the data. At this point, the master must terminate the write operation with a

STOP condition. The DS1855 then enters an internally timed write process Tw to the EEPROM memory.

All inputs are disabled during this byte write cycle.

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The DS1855 is capable of an 8-byte page write. A page write is initiated the same way as a byte write, but

the master does not send a STOP condition after the first byte. Instead, after the slave acknowledges

receipt of the data byte, the master can send up to seven more bytes using the same nine-clock sequence.

The master must terminate the write cycle with a STOP condition or the data clocked into the DS1855

will not be latched into permanent memory.

Acknowledge Polling

Once the internally timed write has started and the DS1855 inputs are disabled, acknowledge polling can

be initiated. The process involves transmitting a START condition followed by the device address. The

R/W bit signifies the type of operation that is desired. The read or write sequence will only be allowed to

proceed if the internal write cycle has completed and the DS1855 responds with a zero.

Read Operations

After receiving a matching address byte with the R/W bit set high, the device goes into the read mode of

operation. There are three read operations: current address read, random read, and sequential address

read.

CURRENT ADDRESS READ

The DS1855 has an internal address register that maintains the address used during the last read or write

operation, incremented by one. This data is maintained as long as VCC is valid. If the most recent address

was the last byte in memory, the register resets to the first address. This address stays valid between

operations as long as power is available.

Once the device address is clocked in and acknowledged by the DS1855 with the R/W bit set to high, the

current address data word is clocked out. The master does not respond with a zero, but does generate a

STOP condition afterwards.

RANDOM READ

A random read requires a dummy-byte write sequence to load in the data word address. Once the device

and data address bytes are clocked in by the master and acknowledged by the DS1855, the master must

generate another START condition. The master now initiates a current address read by sending the device

address with the read/write bit set high. The DS1855 acknowledges the device address and serially clocks

out the data byte.

SEQUENTIAL ADDRESS READ

Sequential reads are initiated by either a current address read or a random address read. After the master

receives the first data byte, the master responds with an acknowledge. As long as the DS1855 receives

this acknowledge after a byte is read, the master may clock out additional data words from the DS1855.

After reaching address FFh, it resets to address 00h.

The sequential read operation is terminated when the master initiates a STOP condition. The master does

not respond with a zero.

For a more detailed description of 2-wire theory of operation, refer to the next section.

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2-WIRE SERIAL PORT OPERATION

The 2-wire serial port interface supports a bidirectional data transmission protocol with device

addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data is

defined as a receiver. The device that controls the message is called a “master.” The devices that are

controlled by the master are “slaves.” The bus must be controlled by a master device that generates the

serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1855

operates as a slave on the two-wire bus. Connections to the bus are made via the open-drain I/O lines,

SDA and SCL. The following I/O terminals control the 2-wire serial port: SDA, SCL, A0, A1, A2.

Timing diagrams for the 2-wire serial port can be found in Figures 2 and 3. Timing information for the 2-

wire serial port is provided in the AC Electrical Characteristics table for 2-wire serial communications.

The following bus protocol has been defined:

1. Data transfer may be initiated only when the bus is not busy.

2. During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in

the data line while the clock line is HIGH will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus not busy: Both data and clock lines remain HIGH.

Start data transfer: A change in the state of the data line from HIGH to LOW while the clock is HIGH

defines a START condition.

Stop data transfer: A change in the state of the data line from LOW to HIGH while the clock line is

HIGH defines the STOP condition.

Data valid: The state of the data line represents valid data when, after a START condition, the data line

is stable for the duration of the clock signal’s HIGH period. The data on the line can be changed during

the clock signal’s LOW period. There is one clock pulse per bit of data. Figures 2 and 3 detail how data

transfer is accomplished on the 2-wire bus. Depending on the state of the R/W bit, two types of data

transfer are possible.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The

number of data bytes transferred between START and STOP conditions is not limited and is determined

by the master device. The information is transferred byte-wise and each receiver acknowledges with a 9th

bit.

A regular mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined within the bus

specifications. The DS1855 works in both modes.

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the

reception of each byte. The master device must generate an extra clock pulse, which is associated with

this acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a

way that the SDA line is a stable LOW during the HIGH period of the acknowledge-related clock pulse.

Of course, setup and hold times must be taken into account. A master must signal an end of data to the

DS1855

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slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this

case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.

1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is

the command/control byte. Next, follows a number of data bytes. The slave returns an acknowledge

bit after each received byte.

2. Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the

command/control byte) to the slave. The slave then returns an acknowledge bit. Next, follows a

number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit

after all received bytes other than the last byte. At the end of the last received byte, a ‘not

acknowledge’ can be returned.

The master device generates all serial clock pulses and the START and STOP conditions. A transfer is

ended with a STOP condition or with a repeated START condition. Since a repeated START condition is

also the beginning of the next serial transfer, the bus will not be released.

The DS1855 may operate in the following two modes:

1. Slave receiver mode: Serial data and clock are received through SDA and SCL, respectively. After

each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized

as the beginning and end of a serial transfer. Address recognition is performed by hardware after

reception of the slave (device) address and direction bit.

2. Slave transmitter mode: The first byte is received and handled as in the slave receiver mode.

However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial data

is transmitted on SDA by the DS1855 while the serial clock is input on SCL. START and STOP

conditions are recognized as the beginning and end of a serial transfer.

3. Slave Address: Command/control byte is the first byte received following the START condition from

the master device. The command/control byte consists of a 4-bit control code. For the DS1855, this is

set as 1010 binary for read/write operations. The next 3 bits of the command/control byte are the

device select bits or slave address (A2, A1, A0). They are used by the master device to select which

of eight devices is to be accessed. When reading or writing to the DS1855, the device-select bits must

match the device-select pins (A2, A1, A0). The last bit of the command/control byte (R/W) defines

the operation to be performed. When set to a 1 a read operation is selected, and when set to a 0 a write

operation is selected.

Following the START condition, the DS1855 monitors the SDA bus by checking the device type

identifier being transmitted. Upon receiving the 1010 control code, the appropriate device address bits,

and the R/W bit, the slave device outputs an acknowledge signal on the SDA line.

WRITE PROTECT

An external write-protect (WP) pin protects EEPROM data and potentiometer position from alteration in

an application. If this pin is open or tied high, the EEPROM content, which includes the potentiometer

settings, is protected from alteration. If no activity occurs on the SDA and SCL pins, this part will be held

in a low-power mode. The EEPROM and potentiometer settings may be read if WP is set, but they cannot

be written under any circumstances unless WP is taken to GND.

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LOCKING AND UNLOCKING EEPROM

In addition to the WP pin, it is possible to write-protect, or lock, certain portions of the EEPROM through

software control. The DS1855 256-byte EEPROM can be visualized as three blocks, or partitions. The

lower block is from 00h to 7Fh. The upper block is 80h to F7h. And the upper page is from F8 to FFh.

The lower and upper blocks are user EEPROM. The upper page is EEPROM that contains the pot

settings, as well as the lock registers.

Locking the EEPROM is a two-step process. First, the software lock configuration byte (FAh) is used to

choose which portion(s) of EEPROM are to be locked. The three least significant bits of FAh are B2, B1,

and B0. B2 selects the upper page (F8–FFh). B1 selects the upper block (80–F7h). The LSBit, B0, selects

the lower block (00–7Fh). The user may lock one, two, or all three partitions at once. The second step

required to turn on the lock is to write the password into the lock bytes (FBh and FCh). The password to

lock is 56h, 25h (FBh and FCh, respectively). Once the EEPROM is locked, the user may still read data

out of the locked portions, but performing a write will not write to EEPROM.

Unlocking the EEPROM consists of entering the password into bytes FBh and FCh. The password to

unlock is 67h, 36h (FBh and FCh, respectively). However, when attempting to unlock the upper page,

which contains the lock bytes (FBh and FCh), the two-byte password must be written in one write cycle.

If a 2-wire STOP command is sent between the write to FBh and FCh, the upper page will remain locked.

In order to modify the Software Lock Configuration Byte (FAh), the upper page must be unlocked. In

other words, the upper page must be unlocked in order to make changes to the locking of the upper and

lower blocks.

READING AND WRITING THE POTENTIOMETER VALUES

Reading from and writing to the potentiometers consists of a standard read or write to EEPROM memory

at the addresses F8h and F9h. The 8-bit value at address F9h controls the wiper setting for potentiometer

0, which has 100 positions. The 8-bit value at address F8h controls the wiper setting of potentiometer 1,

which has 256 positions. Potentiometer 1 may be set to any value between 00h and FFh. 00h sets the

wiper of potentiometer 1 to its lowest value and FFh sets the wiper to its highest. Potentiometer 0 may be

set to any value between 00h and 63h. A value of 00h sets the wiper of potentiometer 0 to its lowest

position and 63h sets the wiper to its highest position. Any hexadecimal value is a valid address. Setting a

value greater than the upper limit of the potentiometer’s range, 64h or greater for potentiometer 0, will

result in setting the wiper to its highest position, but the MSB will be ignored. The memory locations F8h

and F9h, which control the potentiometers’ settings, are programmed to FFh when shipped from the

factory. All other memory locations are initially programmed to 00h.

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2-WIRE PROTOCOL DATA TRANSFER PROTOCOL Figure 2

2-WIRE AC CHARACTERISTICS Figure 3

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ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Pin Relative to Ground -0.3V to +6.0V

Operating Temperature Range -40°C to +85°C

Programming Temperature Range 0°C to +85°C

Storage Temperature Range -55°C to +125°C

Lead Temperature (TSSOP only: soldering, 10s) +300°C

Soldering Temperature (reflow)

TSSOP or CSBGA, Lead(Pb)-free +260°C

TSSOP or CSBGA, Containing Lead(Pb) +240°C

Flip Chip +240°C

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the

operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of

time may affect device reliability.

Note: The DS1855 is built to the highest quality standards and manufactured for long-term reliability. All DS1855s

are made using the same quality materials and manufacturing methods. However, the DS1855 in the flip-chip

package is not exposed to environmental stresses, such as burn-in, that some industrial applications require. For

specific reliability information on this product, contact the factory.

RECOMMENDED DC OPERATING CONDITIONS

(TA = -40°C to +85°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS NOTES

Supply Voltage VCC +2.7 5.5 V 1

DC ELECTRICAL CHARACTERISTICS

(VCC = 2.7V to 5.5V; TA = -40°C to +85°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS NOTES

Active Supply

Current

ICC 0.5 mA 11, 12

Input Leakage

ILI

-1

µA

Input Logic 1 VIH 0.7 x

VCC

VCC +

0.3

Input Logic 0 VIL VGND -

0.3

0.3 x

VCC

Input Current Each

I/O Pin

0.4 < VI/O,

< 0.9 x VDD -10 +10 µA 3

Standby Current ISTBY

3.0V

µA 2

5.0V 30 60

Low-Level Output

Voltage (SDA)

VOL1 3mA sink

current

0.0 0.4 V

VOL2 6mA sink

current

0.0 0.6 V

I/O Capacitance

CI/O

WP Internal Pullup

Resistance

RWP 40 65 100 kΩ

DS1855

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ANALOG RESISTOR CHARACTERISTICS

(VCC = 2.7V to 5.5V; TA = -40°C to +85°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS NOTES

Resistor Inputs L, H, W VGND -

0.3 VCC +

0.3 V

Wiper Resistance RW 3.0V 400 1000 Ω

5.0V

250

600

Wiper Current

End-to-End Resistance TA = +25°C -20 +20 %

Absolute Linearity

10k

Ω

/100 pos

-0.75

+0.75

LSB 9

10k

Ω

/256 pos

-0.75

+0.75

20kΩ/256 pos -1.0 +1.0

50kΩ/256 pos

-1.5

+1.5

100kΩ/256 pos

-2.25

+2.25

Relative Linearity

10k

Ω

/100 pos

-0.25

+0.25

LSB 10

All other pots

-0.5

+0.5

-3dB Cutoff

Frequency

fCUTOFF DS1855-010 1 MHz

End-to-End Temp.

Coefficient

750 ppm/°C

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AC ELECTRICAL CHARACTERISTICS

(VCC = 2.7V to 5.5V; TA = -40°C to +85°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS NOTES

SCL Clock Frequency fSCL

Fast Mode

400

kHz 4

Standard Mode

100

Bus Free Time Between

STOP and START

tBUF

Fast Mode

1.3

µs 4

Standard Mode

4.7

Hold Time (Repeated)

START Condition

tHD:STA

Fast Mode

0.6

µs 4, 5

Standard Mode

4.0

Low Period of SCL

Clock

tLOW

Fast Mode

1.3

µs 4

Standard Mode

4.7

High Period of SCL

Clock

tHIGH

Fast Mode

0.6

µs 4

Standard Mode

4.0

Data Hold Time tHD:DAT

Fast Mode

0.9

µs 4, 6

Standard Mode

0.9

Data Setup Time tSU:DAT

Fast Mode

100

ns 4

Standard Mode

250

Start Setup Time tSU:STA

Fast Mode

0.6

µs 4

Standard Mode

4.7

Rise Time of Both SDA

and SCL Signals tR

Fast Mode

20+0.1C

300

ns 4

Standard Mode

20+0.1C

1000

Fall Time of Both SDA

and SCL Signals

Fast Mode

20+0.1CB

300

ns 7

Standard Mode

20+0.1CB

300

Setup Time for STOP

Condition

tSU:STO

Fast Mode

0.6

µs

Standard Mode

4.0

Capacitive Load for

Each Bus Line

CB 400 pF 7

EEPROM Write Time

2.5

NONVOLATILE MEMORY CHARACTERISTICS

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS

NOTES

Writes

TA = +85°C

50,000

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NOTES:

1. All voltages are referenced to ground.

2. ISTBY specified with for VCC = 3.0V and 5.0V, and control port logic pins are driven to the appropriate

logic levels. Appropriate logic levels specify that logic inputs are within a 0.5V of ground or VCC for

the corresponding inactive state.

3. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VCC is switched off.

4. A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250ns must

then be met. This will automatically be the case if the device does not stretch the LOW period of the

SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next

data bit to the SDA line tRMAX + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released.

5. After this period, the first clock pulse is generated.

6. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the

SCL signal.

7. CB – Total capacitance of one bus line in picofarads, timing referenced to 0.9 x VCC and 0.1 x VCC.

8. EEPROM write begins after a STOP condition occurs.

9. Absolute linearity is used to measure expected wiper voltage as determined by wiper position.

10. Relative linearity is used to determine the change of wiper voltage between two adjacent wiper

positions.

11. ICC specified with SDA pin open.

12. Maximum ICC is dependent on clock rates.

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TYPICAL OPERATING CHARACTERISTICS

(VCC = 5V, TA = +25°C, unless otherwise noted.)

WIPER RESISTANCE (Ω)

SUPPLY CURRENT (µA)

SUPPLY CURRENT vs. VOLTAGE

0123456

VOLTAGE (V)

Icc @-40C

Icc @25C

Icc @85

WIPER RESISTANCE vs. WIPER VOLTAGE

100

150

200

250

300

350

400

450

00.5 11.5 22.5 33.5 44.5 5

VOLTAGE (V)

25 Deg. C

-40 Deg C

85 Deg C

POT 0, TAP 99

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TYPICAL OPERATING CHARACTERISTICS (cont.)

(VCC = 5V, TA = +25°C, unless otherwise noted.)

END-TO-END RESISTANCE CHANGE (%)

ATTENUATION vs. FREQUENCY

-20

-15

-10

-5

10 100 1,000 10,000 100,000 1,000,000 10,000,000

FREQUENCY (Hz)

Pot 0, 10KOhms

Pot 1, 50kOhms

END-TO-END RES % CHANGE vs. TEMPERATURE

-2.0%

-1.5%

-1.0%

-0.5%

0.0%

0.5%

1.0%

1.5%

2.0%

2.5%

-40 -20 020 40 60 80

TEMPERATURE (C)

Pot 0 (10K)

Pot 1 (50K)

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TYPICAL OPERATING CHARACTERISTICS (cont.)

(VCC = 5V, TA = +25°C, unless otherwise noted.)

SUPPLY CURRENT (µA)

ACTIVE SUPPLY CURRENT vs. FREQUENCY

110

130

150

050 100 150 200 250 300 350 400

FREQUENCY (kHz)

Icc active (uA)

RESISTANCE FROM W TO L (Ω)

RESISTANCE vs. VOLTAGE (POWER-UP)

20,000

40,000

60,000

80,000

100,000

120,000

140,000

160,000

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

SUPPLY VOLTAGE - POWER-UP (V)

Pot 0 res (50dec)

Pot 1 res (127dec)

Pot 0 res (0dec)

Pot 1 res (0dec)

Pot 0 res (99dec)

Pot 1 res (255dec)

Potentiometer value recalled from EEPROM

Pot 1, 255d

Pot 1, 127d

Pot 1, 0d

Pot 0, 99d

Pot 0, 0d

Pot 0, 50d

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TYPICAL OPERATING CHARACTERISTICS (cont.)

(VCC = 5V, TA = +25°C, unless otherwise noted.)

RESISTANCE vs. VOLTAGE (POWER-DOWN)

10,000

20,000

30,000

40,000

50,000

60,000

70,000

0.00.51.01.52.02.53.03.54.04.55.0

SUPPLY VOLTAGE - POWER-DOWN (V)

Pot 0 (50dec)

Pot 1 (127dec)

Pot 0 (0dec)

Pot 1 (0dec)

Pot 0 (99dec)

Pot 1 (255dec)

Pot 1 set to 127 decimal

Pot 0 set to 50 decimal

Pot 1 set to 0 decimal

Pot 1 set to 255 decimal

Pot 0 set to 99 decimal

Pot 0 set to 0 decimal

RESISTANCE FROM W TO L (Ω)

DS1855

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ORDERING INFORMATION

PART TEMP RANGE

VERSION

Pot 0/Pot 1

PIN-PACKAGE

DS1855B-010

-40ºC to +85ºC

10kΩ/10kΩ

16 CSBGA

DS1855B-010/T&R

-40ºC to +85ºC

10kΩ/10kΩ

16 CSBGA

DS1855B-010+

-40ºC to +85ºC

10kΩ/10kΩ

16 CSBGA

DS1855B-010+T&R

-40ºC to +85ºC

10kΩ/10kΩ

16 CSBGA

DS1855B-020

-40ºC to +85ºC

10kΩ/20kΩ

16 CSBGA

DS1855B-050

-40ºC to +85ºC

10kΩ/50kΩ

16 CSBGA

DS1855B-050+

-40ºC to +85ºC

10kΩ/50kΩ

16 CSBGA

DS1855B-100

-40ºC to +85ºC

10kΩ/100kΩ

16 CSBGA

DS1855B-100+

-40ºC to +85ºC

10kΩ/100kΩ

16 CSBGA

DS1855E-010

-40ºC to +85ºC

10kΩ/10kΩ

14 TSSOP

DS1855E-010/T&R

-40ºC to +85ºC

10kΩ/10kΩ

14 TSSOP

DS1855E-010+

-40ºC to +85ºC

10kΩ/10kΩ

14 TSSOP

DS1855E-010+T&R

-40ºC to +85ºC

10kΩ/10kΩ

14 TSSOP

DS1855E-020

-40ºC to +85ºC

10kΩ/20kΩ

14 TSSOP

DS1855E-020/T&R

-40ºC to +85ºC

10kΩ/20kΩ

14 TSSOP/

DS1855E-050

-40ºC to +85ºC

10kΩ/50kΩ

14 TSSOP

DS1855E-050/T&R

-40ºC to +85ºC

10kΩ/50kΩ

14 TSSOP

DS1855E-050+

-40ºC to +85ºC

10kΩ/50kΩ

14 TSSOP

DS1855E-050+T&R

-40ºC to +85ºC

10kΩ/50kΩ

14 TSSOP

DS1855E-100

-40ºC to +85ºC

10kΩ/100kΩ

14 TSSOP

DS1855E-100/T&R

-40ºC to +85ºC

10kΩ/100kΩ

14 TSSOP

DS1855X-010

-40ºC to +85ºC

10kΩ/10kΩ

14 FLIP CHIP

DS1855X-020

-40ºC to +85ºC

10kΩ/20kΩ

14 FLIP CHIP

DS1855X-050/T&R

-40ºC to +85ºC

10kΩ/50kΩ

14 FLIP CHIP

DS1855X-100

-40ºC to +85ºC

10kΩ/100kΩ

14 FLIP CHIP

+Denotes a lead(Pb)-free/RoHS-compliant package.

T&R = Tape and reel.

PACKAGE INFORMATION

For the latest package outline information and land patterns, go to www.maximintegrated.com/packages. Note

that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix

character, but the drawing pertains to the package regardless of RoHS status.

PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

16 CSBGA

X16+1

21-0355

90-0334

14 TSSOP U14+1 21-0066 90-0113

14 FLIP CHIP BF1422-1 21-0285 ⎯

DS1855

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Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses

are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)

shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1 - 408-601-1000

REVISION HISTORY

REVISION

NUMBER

REVISION

DATE

DESCRIPTION

PAGES

CHANGED

2 1/13

Added the soldering information for all package

variants to the Absolute Maximum Ratings section;

updated the Ordering Information table and added the

Package Information table

12, 20

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Maxim Integrated:

DS1855E-010+T&R DS1855B-010+ DS1855B-010+T&R DS1855B-050+ DS1855E-010+ DS1855E-050+T&R

DS1855E-C01+T&R DS1855E-050+