IRFP360 - Intersil Corporation

4-341

File Number

2290.3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

IRFP360

23A, 400V, 0.200 Ohm, N-Channel Power

MOSFET

This advanced power MOSFET is designed, tested, and

guaranteed to withstand a speciﬁed level of energy in the

breakdown a v alanche mode of oper ation. These are

N-Channel enhancement mode silicon gate power ﬁeld

effect transistors designed for applications such as switching

regulators, switching converters, motor drivers, relay drivers

and drivers for high power bipolar switching transistors

requiring high speed and low gate drive power. They can be

operated directly from integr ated circuits .

Formerly developmental type TA17464.

Features

• 23A, 400V

•r

DS(ON) = 0.200Ω

• Single Pulse Avalanche Energy Rated

• SOA is Power Dissipation Limited

• Nanosecond Switching Speeds

• Linear Transfer Characteristics

• High Input Impedance

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount

Components to PC Boards”

Symbol

Packaging

JEDEC STYLE TO-247

Ordering Information

PART NUMBER PACKAGE BRAND

IRFP360 TO-247 IRFP360

NOTE: When ordering, use the entire part number.

SOURCE

DRAIN

GATE

DRAIN

(FLANGE)

Data Sheet July 1999

4-342

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Speciﬁed

IRFP360 UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS 400 V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR 400 V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID

TC= 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID23

14 A

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 92 A

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V

Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD250 W

Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 W/oC

Single Pulse Avalanche Energy Rating (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E

AS 1200 mJ

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 oC

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL

Package Body for 10s, see Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg 300

260 300

260

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. TJ= 25oC to 125oC.

Electrical Speciﬁcations TC = 25oC, Unless Otherwise Speciﬁed

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 10) 400 - - V

Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA2-4V

Zero Gate Voltage Drain Current IDSS VDS = Rated BVDSS, VGS = 0V - - 25 µA

VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC - - 250 µA

On-State Drain Current (Note 2) ID(ON) VDS > ID(ON) x rDS(ON)MAX, VGS = 10V 23 - - A

Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA

On Resistance (Note 2) rDS(ON) ID = 13A, VGS = 10V (Figures 8, 9) - 0.18 0.20 Ω

Forward Transconductance (Note 2) gfs VDS ≥ 50V, IDS > 13A (Figure 12) 14 21 - S

Turn-On Delay Time td(ON) VDD = 200V, ID≈ 25A, RGS = 4.3Ω, VGS = 10V,

RL = 7.5Ω

MOSFET Switching Times are Essentially

Independent of Operating Temperature

-2233ns

Rise Time tr- 94 140 ns

Turn-Off Delay Time td(OFF) - 80 120 ns

Fall Time tf-6699ns

Total Gate Charge

(Gate to Source + Gate to Drain) Qg(TOT) VGS = 10V, ID = 25A, VDS = 0.8 x Rated BVDSS

IG(REF) = 1.5mA (Figure 14)

Gate Charge is Essentially Independent of

Operating Temperature

- 68 100 nC

Gate to Source Charge Qgs -17-nC

Gate to Drain “Miller” Charge Qgd -24-nC

Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) - 4000 - pF

Output Capacitance COSS - 550 - pF

Reverse Transfer Capacitance CRSS -97-pF

Internal Drain Inductance LDMeasured between the

Contact Screw on Header

closer to Source and Gate

Pins and Center of Die

Modified MOSFET

Symbol Showing the

Internal Device

Inductances

- 5.0 - nH

Internal Source Inductance LSMeasuredfrom theSource

Lead, 6mm (0.25in) from

Header and Source

Bonding Pad

-13-nH

Thermal Resistance Junction to Case RθJC - - 0.50 oC/W

Thermal Resistance Junction to Ambient RθJA Free Air Operation - - 30 oC/W

IRFP360

4-343

Source to Drain Diode Speciﬁcations

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Continuous Source to Drain Current ISD ModifiedMOSFETSymbol

Showing the Integral

Reverse P-N Junction

Rectifier

- - 23 A

Pulse Source to Drain Current (Note 2) ISDM - - 92 A

Source to Drain Diode Voltage (Note 2) VSD TJ = 25oC, ISD = 23A, VGS = 0V (Figure 13) - - 1.8 V

Reverse Recovery Time trr TJ = 25oC, ISD = 25A, dISD/dt = 100A/µs 200 460 1000 ns

Reverse Recovery Charge QRR TJ = 25oC, ISD = 25A, dISD/dt = 100A/µs 3.1 7.1 16 µC

NOTES:

2. Pulse test: pulse width ≤300µs, duty cycle ≤ 2%.

3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).

4. VDD = 50V, starting TJ= 25oC, L = 4mH, RG= 25Ω, Peak IAS = 23A.

Typical Performance Curves

Unless Otherwise Speciﬁed

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE

TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

FIGURE 3. TRANSIENT THERMAL IMPEDANCE

0 50 100 150

TC, CASE TEMPERATURE (oC)

POWER DISSIPATION MULTIPLIER

0.2

0.4

0.6

0.8

1.0

1.2

050 100

ID, DRAIN CURRENT (A)

TC, CASE TEMPERATURE (oC)

150

25 75 125

0.1

10-3

10-5 10-4 10-3 10-2 0.1 1 10

ZθJC, TRANSIENT THERMAL

t1, RECTANGULAR PULSE DURATION (S)

SINGLE PULSE

PDM

NOTES:

DUTY FACTOR: D = t1/t2

PEAK TJ = PDM x ZθJC + TC

t1t2

0.1

0.02

0.2

0.5

0.01

0.05

10-2

IMPEDANCE (oC/W)

IRFP360

4-344

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

Typical Performance Curves

Unless Otherwise Speciﬁed (Continued)

110

102103

VDS, DRAIN TO SOURCE VOLTAGE (V)

103

102

0.1

ID, DRAIN CURRENT (A)

SINGLE PULSE

TJ = MAX RATED

TC = 25oC

BY rDS(ON)

AREA IS LIMITED

OPERATION IN THIS

10µs

100µs

1ms

10ms

ID, DRAIN CURRENT (A)

0 40 80 120 160

200

VDS, DRAIN TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs

VGS = 10V

VGS = 6.0V

VGS = 5.5V

VGS = 5.0V

VGS = 4.5V VGS = 4.0V

DUTY CYCLE = 0.5% MAX

0246 10

ID, DRAIN CURRENT (A)

VDS, DRAIN TO SOURCE VOLTAGE (V)

40 VGS = 10V

VGS = 4.5V

VGS = 5.5V

VGS = 6.0V

VGS = 5.0V

VGS = 4.0V

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

02468

VSD, GATE TO SOURCE VOLTAGE (V)

102

0.1

ID, DRAIN CURRENT (A)

TJ = 150oCTJ = 25oC

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

VDS ≥50V

ID, DRAIN CURRENT (A)

rDS(ON), DRAIN TO SOURCE

2.0

1.6

1.2

0.8

0.4

00 30 60 90 120 150

VGS = 20V

VGS = 10V

ON RESISTANCE

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

3.0

1.8

1.2

0.6

0-40 0 40

TJ, JUNCTION TEMPERATURE (oC)

120

2.4

80 160

NORMALIZED DRAIN TO SOURCE

ON RESISTANCE

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

VGS = 10V, ID =13A

IRFP360

4-345

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

Typical Performance Curves

Unless Otherwise Speciﬁed (Continued)

1.25

1.05

0.95

0.85

0.75 -40 0 40

TJ, JUNCTION TEMPERATURE (oC)

120

1.15

ID = 250µA

160

NORMALIZED DRAIN TO SOURCE

BREAKDOWN VOLTAGE

VDS, DRAIN TO SOURCE VOLTAGE (V)

C, CAPACITANCE (nF)

10000

8000

6000

4000

2000

012 5102 5

102

CISS = CGS + CGD

CRSS = CGD

COSS ≈ CDS + CGD

VGS = 0V, f = 1MHz

CISS

COSS

CRSS

00 1020304050

ID, DRAIN CURRENT (A)

gfs, TRANSCONDUCTANCE (S)

TJ = 150oC

TJ = 25oC

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

VDS ≥ 50V

0 0.4 0.8 1.2 1.6

VSD, SOURCE TO DRAIN VOLTAGE (V)

102

ISD, SOURCE TO DRAIN CURRENT (A)

TJ = 150oC

TJ = 25oC

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

0 25 50 75 100 125

ID = 25A

Qg, GATE CHARGE (nC)

VGS, GATE TO SOURCE VOLTAGE (V)

VDS = 80V

VDS = 320V

IRFP360

4-346

Test Circuits and Waveforms

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

VGS

0.01Ω

IAS

VDS

VDD

DUT

VARY tP TO OBTAIN

REQUIRED PEAK IAS

VDD

VDS

BVDSS

IAS

tAV

VGS

DUT

-VDD

tON

td(ON)

90%

10%

VDS 90%

10%

td(OFF)

tOFF

90%

50%

10% PULSE WIDTH

VGS

0.3µF

12V

BATTERY 50kΩ

VDS

DUT

IG(REF)

(ISOLATED

VDS

0.2µF

CURRENT

REGULATOR

ID CURRENT

SAMPLING

IG CURRENT

SAMPLING

SUPPLY)

RESISTOR RESISTOR

SAME TYPE

AS DUT Qg(TOT)

Qgd

Qgs

VDS

VGS

VDD

IG(REF)

IRFP360

4-347

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is gr anted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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IRFP360