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1997 Nov 25 22
Philips Semiconductors Product specification
User Guide
4.5 Conditions for CPD tests
Gates. All inputs except one are held at either VCC or
GND, depending on which state causes the output to
toggle. The remaining input is toggled at a known
frequency. CPD is specified per-gate.
Decoders. One input is toggled, causing the outputs to
toggle at the same rate (normally one of the address-select
pins is switched while the decoder is enabled). All other
inputs are tied to VCC or GND, whichever enables
operation. CPD is specified per-independent-decoder.
Multiplexers. One data input is tied HIGH and the other is
tied LOW. The address-select and enable inputs are
configured such that toggling one address input selects
the two data inputs alternately, causing the outputs to
toggle. With three-state multiplexers, CPD is specified per
output function for enabled outputs.
Bilateral switches. The switch inputs and outputs are
open-circuit. With the enable input active, one of the select
inputs is toggled, the others are tied HIGH or LOW. CPD is
specified per switch.
Three-state buffers and transceivers. CPD is specified
per buffer with the outputs enabled. Measurement is as for
simple gates.
Latches. The device is clocked and data is toggled on
alternate clock pulses. Other preset or clear inputs are
held so that output toggling is enabled. If the device has
common-locking latches, one latch is toggled by the clock.
Three-state latches are measured with their outputs
enabled. CPD is specified per-latch.
Flip-flops. Measurement is performed as for latches. The
inputs to the device are toggled and any preset or clear
inputs are held inactive.
Shift registers. The register is clocked and the serial data
input is toggled at alternate clock pulses (as described for
latches). Clear and load inputs are held inactive and
parallel data are held at VCC or GND. Three-state devices
are measured with outputs enabled. If the device is for
parallel loading only, it is loaded with 101010..., clocked to
shift the data out and then reloaded.
Counters. A signal is applied to the clock input but other
clear or load inputs are held inactive. Separate values for
CPD are given for each counter in the device.
Arithmetic circuits. Adders, magnitude comparators,
encoders, parity generators, ALUs and miscellaneous
circuits are exercised to obtain the maximum number of
simultaneously toggling outputs when toggling only one or
two inputs.
Display drivers. CPD is not normally required for LED
drivers because LEDs consume so much power as to
make the effect of CPD negligible. Moreover, when
blanked, the drivers are rarely driven at significant speeds.
When it is needed, CPD is measured with outputs enabled
and disabled while toggling between lamp test and blank
(if provided), or between a display of numbers 6 and 7.
LCD drivers are tested by toggling the phase inputs that
control the segment and backplane waveforms outputs.
If either type of driver (LCD or LED) has latched inputs,
then the latches are set to a flow-through mode.
One-shot circuits. In some cases, when the device ICC is
significant, CPD is not specified. When it is specified, CPD
is measured by toggling one trigger input to make the
output a square wave. The timing resistor is tied to a
separate supply (equal to VCC) to eliminate its power
contribution.
4.6 Additional power dissipation in 74HCT devices
When the inputs of a 74HCT device are driven by a TTL
device at the specified minimum HIGH output level of
VOH = 2.4 V, the input stage p-channel transistor does not
completely switch off and there is an additional quiescent
supply current (∆ICC). This current has been considerably
reduced by proprietary development of 74HCT input
stages, see ′74HCT inputs′.
The value of ∆ICC specified in the data sheets is per input
and at the worst-case input voltage of VCC −2.1 V for VCC
between 4.5 and 5.5 V. The value of 2.1 V is the maximum
voltage drop across a TTL output HIGH (minimum VCC and
minimum VOH), see Table 9.
The additional power dissipation P is:
P=V
CC ×∆I
CC ×duty factor HIGH ×unit load coefficient
The unit load coefficient for an input is a factor by which the
value of ∆ICC given in the data sheet has to be multiplied.
A unit load coefficient is published for each 74HCT device.
It is a function of the size of the input p-channel transistor.