CY7C1024DV33
3-Mbit (128 K × 24) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-08353 Rev. *E Revised September 29, 2011
Features
■High speed
❐tAA = 10 ns
■Low active power
❐ICC = 175 mA at f = 100 MHz
■Low CMOS standby power
❐ISB2 = 25 mA
■Operating voltages of 3.3 ± 0.3 V
■2.0 V data retention
■Automatic power-down when deselected
■T ransistor-transistor logic (TTL) compatible inputs and outputs
■Easy memory expansion with CE1, CE2, and CE3 features
■Available in Pb-free standard 119-ball PBGA
Functional Description
The CY7C1024DV33 is a high performance CMOS static RAM
organized as 128 K words by 24 bits. This device has an
automatic power-down feature that significantly reduces power
consumption when deselected.
To write to the device, enable the chip (CE1 LOW, CE2 HIGH,
and CE3 LOW), while forcing the Write Enable (WE) input LOW .
T o read from the device, enable the chip by taking CE1 LOW, CE2
HIGH, and CE3 LOW while forcing the Output Enable (OE) LOW
and the Write Enable (WE) HIGH. See the Truth Table on page
7 for a complete description of Read and Write modes.
The 24 I/O pins (I/O0 to I/O23) are placed in a high impedance
state when the device is deselected (CE1 HIGH, CE2 LOW, or
CE3 HIGH) or when the output enable (OE) is HIGH during a
write operation. (CE1 LOW, CE2 HIGH, CE3 LOW, and WE
LOW).
Logic Block Diagram
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
128K x 24
ARRAY
I/O
0
– I/O
23
OE
CE
1
, CE
2
, CE
3
WE
CONTROL LOGIC
A(9:0)
A(16:10)
CY7C1024DV33
Document Number: 001-08353 Rev. *E Page 2 of 12
Selection Guide
Description –10 Unit
Maximum access time 10 ns
Maximum operating current 175 mA
Maximum CMOS standby current 25 mA
Pin Configuration
Figure 1. 119-Ball PBGA Top View [1]
1 2 3 4 5 6 7
ANCAAAAANC
BNC A A CE1AANC
CI/O12 NC CE2NC CE3NC I/O0
DI/O13 VDD VSS VSS VSS VDD I/O1
EI/O14 VSS VDD VSS VDD VSS I/O2
FI/O15 VDD VSS VSS VSS VDD I/O3
GI/O16 VSS VDD VSS VDD VSS I/O4
HI/O17 VDD VSS VSS VSS VDD I/O5
JNC VSS VDD VSS VDD VSS NC
KI/O18 VDD VSS VSS VSS VDD I/O6
LI/O19 VSS VDD VSS VDD VSS I/O7
MI/O20 VDD VSS VSS VSS VDD I/O8
NI/O21 VSS VDD VSS VDD VSS I/O9
PI/O22 VDD VSS VSS VSS VDD I/O10
RI/O23 NC NC NC NC NC I/O11
TNC A A WE AANC
UNC A A OE AANC
Note
1. NC pins are not connected on the die.
CY7C1024DV33
Document Number: 001-08353 Rev. *E Page 3 of 12
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature .............. ... .. ............. –65 C to +150 C
Ambient temperature with
power applied........................................... –55C to +125 C
Supply Voltage on VCC Relative to GND [2]..–0.5 V to +4.6 V
DC Voltage Applied to Outputs
in high Z state [2]..................................–0.5 V to VCC + 0.5 V
DC input voltage [2]..............................–0.5 V to VCC + 0.5 V
Current into outputs (LOW) .........................................20 mA
Static discharge voltage......................... .. .................>2001 V
(MIL-STD-883, method 3015)
Latch-up current ......................................................>200 mA
Operating Range
Range Ambient
Temperature VCC
Industrial –40 C to +85 C 3.3 V 0.3 V
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions [3] –10 Unit
Min Max
VOH Output HIGH voltage Min VCC, I OH = –4.0 mA 2.4 V
VOL Output LOW voltage Min VCC, IOL = 8.0 mA 0.4 V
VIH Input HIGH voltage 2.0 VCC + 0.3 V
VIL[2] Input LOW voltage –0.3 0.8 V
IIX Input leakage current GND < VIN < VCC –1 +1 A
IOZ Output leakage current GND < VOUT < VCC, output disabled –1 +1 A
ICC VCC operating supply current Max VCC, f = fMAX = 1/tRC
IOUT = 0 mA CMOS levels 175 mA
ISB1 Automatic CE power-down
current —TTL inputs Max VCC, CE > VIH
VIN > VIH or VIN < VIL, f = fMAX 30 mA
ISB2 Automatic CE power-down
current — CMOS inputs Max VCC, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 25 mA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions Max Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VCC = 3.3 V 8 pF
COUT I/O capacitance 10 pF
Thermal Resist ance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions 119-Ball
PBGA Unit
JA Thermal resistance
(junction to ambient) Still air, soldered on a 3 × 4.5 inch,
four layer printed circuit board 20.31 C/W
JC Thermal resistance
(junction to case) 8.35 C/W
Notes
2. VIL (min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
3. CE refers to a combination of CE1, CE2, and CE3. CE is LOW when CE1, CE3 are LOW and CE2 is HIGH. CE is HIGH when CE1 is HIGH, or CE2 is LOW , or CE3 is HIGH.
CY7C1024DV33
Document Number: 001-08353 Rev. *E Page 4 of 12
AC Test Loads and Waveforms
The AC test loads and waveform diagram follows.
Figure 2. AC Test Loads and Waveform[4]
AC Switching Characteristics
Over the Operating Range [5]
Parameter Description –10 Unit
Min Max
Read Cycle
tpower[6] VCC(Typical) to the first acce ss 100 – s
tRC Read cycle time 10 – ns
tAA Address to data valid – 10 ns
tOHA Data hold from address change 3 – ns
tACE CE active LOW to data valid [3] –10ns
tDOE OE LOW to data valid – 5 ns
tLZOE OE LOW to low Z [7] 1–ns
tHZOE OE HIGH to high Z [7] –5ns
tLZCE CE active LOW to low Z [3, 7] 3–ns
tHZCE CE deselect HIGH to high Z [3, 7] –5ns
tPU CE active LOW to power-up [3, 8] 0–ns
tPD CE deselect HIGH to power-down [3, 8] –10ns
90%
10%
3.0 V
GND
90%
10%
All input pulses
3.3 V
OUTPUT 5 pF*
(a) (b)
R1 317
R2
351
Fall T ime:> 1V/ns
(c)
OUTPUT 50
Z0= 50
VTH = 1.5 V
30 pF*
*Capacitive Load consists of all
components of the test environment
Rise T ime > 1V/ns
*Including jig
and scope
Notes
4. Valid SRAM operat ion does not occur until the power su pplies have reached the minimum opera ting VDD (3.0 V). 100 s (tpower) af ter reaching the minimum operati ng
VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0 V) voltage.
5. Test conditions assume signal transitio n time of 3 ns or less, timing refer ence levels of 1.5V, and input pulse levels of 0 to 3.0 V. Test conditions for the read cycle use
output loading as shown in part a) of Figure 2, unless specif i ed ot he r w i se .
6. tPOWER gives the minimum amount of time that the power supply is at typical V CC values until the first memory access is performed.
7. tHZOE, tHZCE, tHZWE, t LZOE, tLZCE, a nd t LZWE are specified with a load cap acitance of 5 pF as in part (b) of Figure 2. T ransitio n is measured 200 mV from steady stat e
voltage.
8. These parameters are guaranteed by design and are not tested.
CY7C1024DV33
Document Number: 001-08353 Rev. *E Page 5 of 12
Write Cycle [9, 10]
tWC Write cycle time 10 – ns
tSCE CE active LOW to write end [3] 7–ns
tAW Address setup to write end 7 – ns
tHA Address hold from write end 0 – ns
tSA Address setup to write start 0 – ns
tPWE WE pulse width 7 – ns
tSD Data setup to write end 5.5 – ns
tHD Data hold from write end 0 – ns
tLZWE WE HIGH to low Z [7] 3–ns
tHZWE WE LOW to high Z [7] –5ns
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions [3] Min Typ Max Unit
VDR VCC for data retention 2 – – V
ICCDR Data retention current VCC = 2 V, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V ––
25 mA
tCDR [11] Chip deselect to data retention time 0 – – ns
tR [12] Operation recovery time tRC ––ns
Data Retention Waveform
AC Switching Characteristics (continued)
Over the Operating Range [5]
Parameter Description –10 Unit
Min Max
3.0 V3.0 V
tCDR
VDR > 2 V
DATA RETENTION MODE
tR
CE
VCC
Notes
9. The internal write time of the memory is defined by the overlap of CE1 and CE2 and CE3 LOW and WE LOW. Chip enables must be active and WE must be LOW to
initiate a write. The transition of any of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal th at
terminates the write.
10.The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
11. Tested initially and after any design or process changes that may affect these parameters.
12.Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s.
CY7C1024DV33
Document Number: 001-08353 Rev. *E Page 6 of 12
Switching Waveforms
Figure 3. Read Cycle No. 1 (Address Transition Controlled) [13, 14]
Figure 4. Read Cycle No. 2 (OE Controlled) [3, 14, 15]
Figure 5. Write Cycle No. 1 (CE Controlled) [3, 16, 17]
PREVIOUS DATA VALID DATA OUT VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA I/O
50%
50%
DATA OUT VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE tHZCE
tPD
HIGH
ICC
ISB
IMPEDANCE
OE
CE
ADDRESS
DATA I/O
VCC
SUPPLY
CURRENT
tWC
DATA IN VA LID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
tSCE
CE
WE
DATA I/O
ADDRESS
Notes
13.Device is continuously selected. OE, CE = VIL.
14.WE is HIGH for read cycle.
15.Address valid before or similar to CE transition LOW.
16.Data I/O is high impedance if OE = VIH.
17.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
CY7C1024DV33
Document Number: 001-08353 Rev. *E Page 7 of 12
Figure 6. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [3, 16, 17]
Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [3, 17]
Truth Table
CE1CE2CE3OE WE I/O0 – I/O23 Mode Power
H XXXXHigh Z Power-down Standby (I
SB)
X L X X X High Z Power-down Standby (ISB)
X X H X X High Z Power-down S tandby (ISB)
L H L L H Full Data Out Read Active (ICC)
L H L X L Full Data In Write Active (ICC)
L H L H H High Z Selected, outputs disabled Active (ICC)
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATA IN VALID
NOTE 18
CE
ADDRESS
WE
DATA I/O
OE
DATA IN VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
NOTE 18
CE
ADDRESS
WE
DATA I/O
Note
18.During this period, the I/Os are in the outpu t state and input signals are not applied.
CY7C1024DV33
Document Number: 001-08353 Rev. *E Page 8 of 12
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
10 CY7C1024DV33-10BGXI 51-85115 119-ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-free) Industrial
Ordering Code Definitions
Temperature Range:
I = Industrial
Package Type :
BGX = 119-ball PBGA (Pb-free)
Speed: 10 ns
V33 = Voltage range (3 V to 3.6 V)
D = C9, 90 nm Technolo gy
4 = Data width × 24-bits
02 = 3-Mbit density
1 = Fast Asynchronous SRAM family
Tech nology Code: C = CMOS
7 = SRAM
CY = Cypress
CCY 1 - 10 BGX702 V33 ID4
CY7C1024DV33
Document Number: 001-08353 Rev. *E Page 9 of 12
Package Diagram
Figure 8. 119-ball PBGA (14 x 22 x 2. 4 m m)
51-851 15 *C
CY7C1024DV33
Document Number: 001-08353 Rev. *E Page 10 of 12
Acronyms
Document Conventions
Units of Measure
Acronym Description
CMOS complementary metal oxide semiconductor
I/O input/output
SRAM static random access memory
TSOP thin small outline package
TTL Transistor-tra nsistor logic
Symbol Unit of Measure
°C degrees Celsius
Amicroamperes
mA milliamperes
MHz megahertz
ns nanoseconds
pF picofarads
Vvolts
ohms
Wwatts
CY7C1024DV33
Document Number: 001-08353 Rev. *E Page 11 of 12
Document History Page
Document Title: CY7C1024DV33, 3-Mbit (128 K × 24) Static RAM
Document Number: 001-08353
Rev. ECN No. Orig. of
Change Submission
Date Description of Cha ng e
** 469517 NXR See ECN New data sheet
*A 499604 NXR See ECN A dded note 1 for NC pins
Changed ICC specification from 150 mA to 185 mA
Updated Test Condition for ICC in DC Electrical Characteristics table
Added note for tACE, tLZCE, tHZCE, tPU, tPD, tSCE in AC Switching Characteristics T able
on page 4
*B 1462586 VKN/SFV See ECN Converted fro m pre liminary to final
Updated block diagram
Changed ICC specification from 185 mA to 225 mA
Updated thermal specs
*C 2604677 VKN/PYRS 11/12/08 Removed Commercial operating range, Added Industrial operating rang e
Removed 8 ns speed bin, Added 10 ns speed bin
*D 3109199 PRAS 12/13/2010 Added Ordering Code Definitions.
Updated Package Diagram.
*E 3388080 TAVA 09/29/2011 Minor technical edits. Added Acronyms and Document Conventions.
Updated template.
Document Number: 001-08353 Rev. *E Revised September 29, 2011 Page 12 of 12
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C1024DV33
© Cypress Semico nducto r Co rpor ation , 20 06-2 011. The information cont ai ned he rein is subj ect to chang e with out no tice. Cypr ess Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypres s pro d ucts ar e not war ran t ed no r int e nded to be used fo r
medical, life supp or t, l if e savin g, cr it ical control or saf ety ap pl ic at io ns, unless pursuant to a n exp re ss wri tte n ag reement with Cypress. Furthermore, Cyp ress doe s not author i ze its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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