12-Bit 800kHz Sampling CMOS
ANALOG-to-DIGITAL CONVERTER
FEATURES
●1.25µs THROUGHPUT TIME
●STANDARD ±10V INPUT RANGE
●69dB min SINAD WITH 250kHz INPUT
●±3/4 LSB max INL AND ±1 LSB max DNL
●INTERNAL REFERENCE
●COMPLETE WITH S/H, REF, CLOCK, ETC.
●PARALLEL DATA w/LATCHES
●28-PIN SOIC
ADS7810
DESCRIPTION
The ADS7810 is a complete 12-bit sampling A/D
using state-of-the-art CMOS structures. It contains a
complete 12-bit capacitor-based SAR A/D with inher-
ent S/H, reference, clock, interface for microprocessor
use, and three-state output drivers.
The ADS7810 is specified at an 800kHz sampling
rate, and guaranteed over the full temperature range.
Laser-trimmed scaling resistors provide the industry-
standard ±10V input range, while an innovative design
allows operation from ±5V supplies.
The 28-pin ADS7810 is available in a plastic SOIC
fully specified for operation over the industrial –40°C
to +85°C range.
®
© 1992 Burr-Brown Corporation PDS-1138E Printed in U.S.A. March, 1998
CDAC
Internal
Ref
Output
Latches
and
Three
State
Drivers
Three
State
Parallel
Data
Bus
BUSY
±10V Input
2.5V Ref Out/In
Comparator
Buffer
625Ω
2450Ω
Successive Approximation Register and Control Logic
Clock
Cap
4.8kΩ
8.6kΩ
18kΩ
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
ADS7810
SBAS014
®
ADS7810 2
SPECIFICATIONS
ELECTRICAL
At T
A
= –40°C to +85°C, f
S
= 800kHz, +V
DIG
= +V
ANA
= +5V, –V
ANA
= –5V, using internal reference and the 50Ω input resistor shown in Figure 4b, unless otherwise specified.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
ADS7810U ADS7810UB
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
RESOLUTION 12 ✻Bits
ANALOG INPUT
Voltage Range ±10 ✻V
Impedance 3.1 ✻kΩ
Capacitance 5 ✻pF
THROUGHPUT SPEED
Conversion Cycle t3 + t41020 ✻ns
Complete Cycle Acquire & Convert 1250 ✻ns
Throughput Rate 800 ✻kHz
DC ACCURACY
Integral Linearity Error ±1±0.75 LSB(1)
Differential Linearity Error ±1✻LSB
No Missing Codes Guaranteed ✻
Transition Noise(2) 0.1 ✻LSB
Full Scale Error(3, 4) ±0.5 ±0.25 %
Full Scale Error Drift ±12 ✻ppm/°C
Full Scale Error(3, 4) Ext. 2.5000V Ref ±0.5 ✻%
Full Scale Error Drift Ext. 2.5000V Ref ±12 ✻ppm/°C
Bipolar Zero Error(3) ±8±4 LSB
Bipolar Zero Error Drift ±2✻ppm/°C
Power Supply Sensitivity
(+VDIG = +VANA = VD) +4.75V < VD < +5.25V ±5✻LSB
–5.25V < –VANA < –4.75V ±0.5 ✻LSB
AC ACCURACY
Spurious-Free Dynamic Range fIN = 250kHz 74 82 77 84 dB(5)
Total Harmonic Distortion fIN = 250kHz –80 –74 –82 –77 dB
Signal-to-(Noise+Distortion) fIN = 250kHz 67 71 69 ✻dB
Signal-to-Noise fIN = 250kHz 68 71 70 ✻dB
Usable Bandwidth(6) 1.5 ✻MHz
SAMPLING DYNAMICS
Aperture Delay 20 ✻ns
Aperture Jitter 10 ✻ps
Transient Response FS Step 200 ✻ns
Overvoltage Recovery(7) 250 ✻ns
REFERENCE
Internal Reference Voltage 2.48 2.5 2.52 ✻✻✻ V
Internal Reference DC Source Current 100 ✻µA
(External load should be static)
Internal Reference Drift 8 ppm/°C
External Reference Voltage Range 2.3 2.5 2.7 ✻✻✻ V
For Specified Linearity
External Reference Current Drain Ext. 2.5000V Ref 100 ✻µA
DIGITAL INPUTS
Logic Levels
VIL –0.3 +0.8 ✻✻V
VIH +2.4 VD + 0.3 ✻✻V
IIL VIL = 0V ±10 ✻µA
IIH VIH = 5V ±10 ✻µA
DIGITAL OUTPUTS
Data Format Parallel 12 Bits
Data Coding Binary Two’s Complement
VOL ISINK = 1.6mA +0.4 ✻V
VOH ISOURCE = 500µA +2.8 ✻V
Leakage Current High-Z State, ±5✻µA
VOUT = 0V to VDIG
Output Capacitance High-Z State 15 15 pF
DIGITAL TIMING
Bus Access Time 62 ✻ns
Bus Relinquish Time 83 ✻ns
®
ADS7810
3
ADS7810U ADS7810UB
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
POWER SUPPLIES
Specified Performance
+VDIG = +VANA +4.75 +5 +5.25 ✻✻✻ V
–VANA –5.25 –5 –4.75 ✻✻✻ V
+IDIG +16 ✻mA
+IANA +16 ✻mA
–IANA –13 ✻mA
Derated Performance
+VDIG = +VANA +4.5 +5 +5.5 ✻✻✻ V
–VANA –5.5 –5 –4.5 ✻✻✻ V
Power Dissipation fS = 800kHz 225 275 ✻mW
TEMPERATURE RANGE
Specified Performance –40 +85 ✻✻°C
Derated Performance –55 +125 °C
Storage –65 +150 ✻✻°C
Thermal Resistance (
θ
JA)
Plastic DIP 75 ✻°C/W
SOIC 75 ✻°C/W
✻ Specification same as ADS7810U.
NOTES: (1) LSB means Least Significant Bit. For the 12-bit, ±10V input ADS7810, one LSB is 4.88mV. (2) Typical rms noise at worst case transitions and
temperatures. (3) Measured with 50Ω in series with analog input. Adjustable to zero with external potentiometer. (4) Full scale error is the worst case of –Full Scale
or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the
effect of offset error. (5) All specifications in dB are referred to a full-scale ±10V input. (6) Usable Bandwidth defined as Full-Scale input frequency at which Signal-
to-(Noise+Distortion) degrades to 60dB, or 10 bits of accuracy. (7) Recovers to specified performance after 2 x FS input over voltage.
SPECIFICATIONS (CONT)
ELECTRICAL
At T
A
= –40°C to +85°C, f
S
= 800kHz, +V
DIG
= +V
ANA
= +5V, –V
ANA
= –5V, using internal reference and the 50Ω input resistor shown in Figure 4b, unless otherwise specified.
ABSOLUTE MAXIMUM RATINGS
Analog Inputs: VIN .............................................................................. ±25V
REF .................................... +VANA +0.3V to AGND2 –0.3V
CAP ...........................................Indefinite Short to AGND2
Momentary Short to +VANA
Ground Voltage Differences: DGND, AGND1, AGND2 ...................±0.3V
+VANA ...................................................................................................+7V
+VDIG to +VANA .................................................................................+0.3V
+VDIG ..................................................................................................... 7V
–VANA ................................................................................................... –7V
Digital Inputs ............................................................ –0.3V to +VDIG +0.3V
Maximum Junction Temperature ................................................... +165°C
Internal Power Dissipation .............................................................825mW
Lead Temperature (soldering, 10s)................................................ +300°C
MINIMUM
MAXIMUM SIGNAL-TO-
INTEGRAL (NOISE + SPECIFICATION
LINEARITY DISTORTION) TEMPERATURE PACKAGE DRAWING
PRODUCT ERROR (LSB) RATIO (dB) RANGE PACKAGE NUMBER(1)
ADS7810U ±1 67 –40°C to +85°C 28-Pin SOIC 217
ADS7810UB ±0.75 69 –40°C to +85°C 28-Pin SOIC 217
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.
ORDERING /PACKAGE INFORMATION
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
®
ADS7810 4
PIN ASSIGNMENTS
DIGITAL
PIN # NAME I/O DESCRIPTION
1V
IN Analog Input. Connect via 50Ω to analog input. Full-scale input range is ±10V.
2 AGND1 Analog Ground. Used internally as ground reference point. Minimal current flow.
3 REF Reference Input/Output. Outputs internal reference of +2.5V nominal. Can also be driven by external system
reference. In both cases, decouple to ground with a 0.1µF ceramic capacitor.
4 CAP Reference Buffer Output. 10µF tantalum capacitor to ground. Nominally +2V.
5 AGND2 Analog Ground.
6 D11 (MSB) O Data Bit 11. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is
LOW, or when a conversion is in progress.
7 D10 O Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
8 D9 O Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
9 D8 O Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
10 D7 O Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
11 D6 O Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
12 D5 O Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
13 D4 O Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
14 DGND Digital Ground.
15 D3 O Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
16 D2 O Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
17 D1 O Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
18 D0 (LSB) O Data Bit 0. Least Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is
LOW, or when a conversion is in progress.
19 Not internally connected.
20 +VANA Analog Positive Supply Input. Nominally +5V. Connect directly to pins 21, 27 and 28.
21 +VDIG Digital Supply Input. Nominally +5V. Connect directly to pins 20, 27 and 28.
22 DGND Digital ground.
23 R/C I Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and
starts a conversion. With CS LOW and no conversion in progress, a rising edge on R/C enables the output
data bits.
24 CS I Chip Select. With R/C LOW, a falling edge on CS will initiate a conversion. With
R/C HIGH and no conversion in progress, a falling edge on CS will enable the output data bits.
25 BUSY O Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the
data is latched into the output register. With CS LOW and R/C HIGH, output data will be valid when BUSY
rises, so that the rising edge can be used to latch the data.
26 –VANA Analog Negative Supply Input. Nominally –5V. Decouple to ground with 0.1µF ceramic and 10µF tantulum
capacitors.
27 +VDIG Digital Supply Input. Nominally +5V. Connect directly to pins 20, 21 and 28.
28 +VANA Analog Positive Supply Input. Nominally +5V. Connect directly to pins 20, 21 and 27, and decouple to ground
with 0.1µF ceramic and 10µF tantulum capacitors.
PIN CONFIGURATION
V
IN
AGND1
REF
CAP
AGND2
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
DGND
+V
ANA
+V
DIG
–V
ANA
BUSY
CS
R/C
DGND
+V
DIG
+V
ANA
NC
(1)
D0 (LSB)
D1
D2
D3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS7810
NOTE:
(
1
)
Not Internall
y
Connected.
®
ADS7810
5
FREQUENCY SPECTRUM
(4096 Point FFT; f
IN
= 502kHz, –0.5dB)
Frequency (kHz)
Amplitude (dB)
0
–20
–40
–60
–80
–100
–120 0 100 200 300 400
FREQUENCY SPECTRUM
(4096 Point FFT; f
IN
= 252kHz, –0.5dB)
Frequency (kHz)
Amplitude (dB)
0
–20
–40
–60
–80
–100
–120 0 100 200 300 400
TYPICAL PERFORMANCE CURVES
T = +25°C, fS =800kHz, +VDIG = +VANA = +5V, –VANA = –5V, using internal reference and the input 50Ω resistors as shown in Figure 4b, unless otherwise specified.
FREQUENCY SPECTRUM
(4096 Point FFT; f
IN
= 1.002MHz, –0.5dB)
Frequency (kHz)
Amplitude (dB)
0
–20
–40
–60
–80
–100
–120 0 100 200 300 400
FREQUENCY SPECTRUM
(4096 Point FFT; f1
IN
= 232kHz, –6.5dB;
f2
IN
= 272kHz, –6.5dB)
Frequency (kHz)
Amplitude (dB)
0
–20
–40
–60
–80
–100
–120 0 100 200 300 400
SIGNAL-TO-(NOISE + DISTORTION)
vs INPUT FREQUENCY (f
IN
= –0.5dB)
90
80
70
60
50
40
30
20
10
SINAD (dB)
1k 10k 100k 1M 10M
Input Signal Frequency (Hz)
A.C. PARAMETERS vs TEMPERATURE
(f
IN
= 250kHz, –0.5dB)
100
95
90
85
80
75
70
65
60
–100
–95
–90
–85
–80
–75
–70
–65
–60
SFDR, SNR, and SINAD (dB)
THD (dB)
–50 –25 0 25 50 75 100
Temperature (°C)
SNR
SFDR
SINAD
THD
®
ADS7810 6
TYPICAL PERFORMANCE CURVES (CONT)
T = +25°C, fS =800kHz, +VDIG = +VANA = +5V, –VANA = –5V, using internal reference and the 50Ω input resistors as shown in Figure 4b, unless otherwise specified.
D.C. PARAMETERS vs. TEMPERATURE
040953584
30722560
204815361024512 Decimal Code
0 4095358430722560
204815361024512 Decimal Code
All Codes INL
All Codes DNL
1
0.5
0
–0.5
–1
12-Bit LSBs12-Bit LSBs
1
0.5
0
–0.5
–1
Percent
From Ideal
Percent
From Ideal
Temperature (°C)
–50 150
–75
Offset Error
0.2
0.1
0
–0.1
–0.2
0.2
0.1
0
–0.1
–0.2
2
1
0
–1
–2
LSBs
From Ideal
125100
7550
250–25
CODE TRANSITION NOISE
Analog Input Voltage – Expected Code Center (LSBs)
0
100
75
50
25
Conversions Yielding Expected Code (%)
01
0.25 0.5 0.75
INTERNAL REFERENCE VOLTAGE vs TEMPERATURE
2.520
2.515
2.510
2.505
2.500
2.495
2.490
2.485
2.480
Internal Reference (V)
THD (dB)
–50 –25 0 25 50 75 100
Temperature (°C)
CONVERSION TIME (t
7
) vs TEMPERATURE
1200
1150
1100
1050
1000
950
900
850
800
750–50 –25 0 25 50 75 100
Temperature (°C)
Conversion Time (ns)
+FS Error
–FS Error
®
ADS7810
7
STARTING A CONVERSION
The combination of CS (pin 24) and R/C (pin 23) LOW for
a minimum of 40ns puts the sample/hold of the ADS7810 in
the hold state and starts a conversion. BUSY (pin 25) will go
LOW and stay LOW until the conversion is completed and
the internal output register has been updated. All new
convert commands during BUSY LOW will be ignored.
The ADS7810 will begin tracking the input signal at the end
of the conversion. Allowing 1.25µs between convert com-
mands assures accurate acquisition of a new signal. Refer to
Table I for a summary of CS, R/C, and BUSY states and
Figures 2 and 3 for timing parameters.
CS and R/C are internally OR’d and level triggered. There
is not a requirement which input goes LOW first when
initiating a conversion. If it is critical that CS or R/C initiate
the conversion, be sure the less critical input is LOW at least
10ns prior to the initiating input.
CS R/C BUSY OPERATION
1 X X None. Databus in Hi-Z state.
↓0 1 Initiates conversion. Databus remains in
Hi-Z state.
0↓1 Initiates conversion. Databus enters Hi-Z
state.
01↑Conversion completed. Valid data from
the most recent conversion on the databus.
↓1 1 Enables databus with valid data from the
most recent conversion.
↓1 0 Conversion in progress. Databus in Hi-Z
state, enabled when the conversion is
completed
0↑0 Conversion in progress. Databus in Hi-Z
state, enabled when the conversion is
completed
00↑Conversion completed. Valid data from the
most recent conversion in the output
register, but output pins D11-D0 are tri-stated.
X X 0 New convert commands ignored. Conversion
in progress.
BASIC OPERATION
Figure 1 shows a basic circuit to operate the ADS7810.
Taking R/C (pin 23) LOW for a minimum of 40ns will
initiate a conversion. BUSY (pin 25) will go LOW and stay
LOW until the conversion is completed and the output
registers are updated. Data will be output in Binary Two’s
Complement with the MSB on D11 (pin 6). BUSY going
HIGH can be used to latch the data. All convert commands
will be ignored while BUSY is LOW.
The ADS7810 will begin tracking the input signal at the end
of the conversion. Allowing 1.25µs between convert com-
mands assures accurate acquisition of a new signal.
Table I. Control Line Functions for ‘read’ and ‘convert’.
FIGURE 1. Basic Operation
DESCRIPTION ANALOG VALUE DIGITAL OUTPUT
Full Scale Range ±10V
Least Significant 4.88mV
Bit (LSB) BINARY CODE HEX CODE
+Full Scale 9.995V 0111 1111 1111 7FF
(10V – 1LSB)
Midscale 0V 0000 0000 0000 000
One LSB below –4.88mV 1111 1111 1111 FFF
Midscale
–Full Scale –10V 1000 0000 0000 800
BINARY TWO'S COMPLEMENT
TABLE II. Ideal Input Voltages and Output Codes.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS7810
50Ω
±10V
–5V
+5V
0.1µF
NC
10µF
++
+
0.1µF 10µF
Convert Pulse
BUSY
40ns min
D0 (LSB)
D1
D2
D3
D6
D5
D4
D7
D8
D9
D10
D11 (MSB)
0.1µF 10µF
++
®
ADS7810 8
To reduce the number of control pins, CS can be tied LOW
using R/C to control the read and convert modes. Note that
the parallel output will be active whenever R/C is HIGH and
no conversion is in progress. See the Reading Data section
and refer to Table I for control line functions for ‘read’ and
‘convert’ modes.
READING DATA
The ADS7810 outputs full parallel data in Binary Two’s
Complement data format. The parallel output will be active
when R/C (pin 23) is HIGH, CS (pin 24) is LOW, and no
conversion is in progress. Any other combination will tri-
state the parallel output. Valid conversion data can be read
in a full parallel, 12-bit word on D11-D0 (pins 6-13 and 15-
18). Refer to Table II for ideal output codes.
After the conversion is completed and the output registers
have been updated, BUSY (pin 25) will go HIGH. Valid data
from the most recent conversion will be available on
D11-D0 (pins 6-13 and 15-18). BUSY going HIGH can be
used to latch the data. Refer to Table III and Figures 2
and 3.
Note: For the best performance, the external data bus con-
nected to D11-D0 should not be active during a conversion.
The switching noise of the external asynchronous data
signals can cause digital feedthrough degrading the
converter’s performance.
The number of control lines can be reduced by tieing CS
LOW while using R/C to initiate conversions and activate
the output mode of the converter. See Figure 2.
INPUT RANGES
The ADS7810 offers a standard ±10V input range. Figures
4a and 4b show the necessary circuit connections for the
ADS7810 with and without external trim. Offset and full
scale error(1) specifications are tested and guaranteed with
the 50Ω resistor shown in Figure 4b. This external resistor
makes it possible to trim the offset ±50mV using a trim pot
or trim DAC. This resistor may be left out if the offset and
gain errors will be corrected in software or if they are
negligible in regards to the particular application. See the
Calibration section of the data sheet for details.
The nominal input impedance of 3.125kΩ results from the
combination of the internal resistor network shown on the
front page of the product data sheet and external 50Ω
resistor. The input resistor divider network provides inherent
overvoltage protection guaranteed to at least ±25V. The
50Ω, 1% resistor does not compromise the accuracy or drift
of the converter. It has little influence relative to the internal
resistors, and tighter tolerances are not required.
Note: The values shown for the internal resistors are for
reference only. The exact values can vary by ±30%. This is
true of all resistors internal to the ADS7810. Each resistive
divider is trimmed so that the proper division is achieved.
NOTE: (1) Full scale error includes offset and gain errors measured at both
+FS and –FS.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t1Convert Pulse Width 40 ns
t2Data Valid Delay 955 1095 ns
After R/C LOW
t3BUSY Delay 70 125 ns
From R/C LOW
t4BUSY LOW 950 1080 ns
t5BUSY Delay After 90 ns
End of Conversion
t6Aperture Delay 20 ns
t7Conversion Time 910 1020 ns
t8Acquisition Time 200 230 ns
t7 & t8Throughput Time 1110 1250 ns
t9Bus Relinquish Time 10 50 83 ns
t10 BUSY Delay 20 65 120 ns
After Data Valid
t11 R/C to CS 10 ns
Setup Time
t12 Time Between 1250 ns
Conversions
t13 Bus Access Time 10 25 62 ns
TABLE III. Timing Specifications (TMIN to TMAX).
®
ADS7810
9
FIGURE 2. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low).
FIGURE 3. Using CS to Control Conversion and Read Timing.
FIGURE 4a. Circuit Diagram With External Hardware Trim.
t
9
Hi-Z State
t
8
BUSY
R/C
DATA BUS
MODE Acquire
Data Valid
t
10
Data Valid HI Z State
ConvertConvert
t
7
t
6
t
3
t
4
t
1
t
2
t
5
Acquire
t
12
FIGURE 4b. Circuit Diagram Without External Hardware
Trim.
NOTE: Use 1% metal film resistors. Trim offset at 0V first, then trim
gain at 10V.
t
9
Hi-Z State
BUSY
R/C
DATA
BUS
MODE Acquire
Data Valid HI Z State
Convert
t
7
t
2
t
6
t
3
t
4
t
11
t
5
Acquire
t
13
t
11
t
1
t
11
t
11
CS
50Ω
AGND2
CAP
REF
AGND1
V
IN
+
0.1µF
10µF
R
2
604kΩ
5V
V
IN
+5V R
1
5kΩ
–5V
P
1
5kΩ
P
2
5kΩ
50Ω
AGND2
CAP
REF
AGND1
V
IN
+
0.1µF
10µF
V
IN
®
ADS7810 10
CALIBRATION
The ADS7810 can be trimmed in hardware or software. The
offset should be trimmed before the gain since the offset
directly affects the gain.
Hardware Calibration
To calibrate the offset and gain of the ADS7810, install the
proper resistors and potentiometers as shown in Figure 4a.
The calibration range is ±50mV for bipolar zero and ±120mV
for full scale.
Potentiometer P1 and resistor R1 form the offset adjust
circuit and P2 and R2 the gain adjust circuit. The exact values
are not critical. R1 and R2 should not be made any larger than
the value shown. They can easily be made smaller to provide
increased adjustment range. Reducing these below 15% of
the indicated values could begin to adversely affect the
operation of the converter.
P1 and P2 can also be made larger to reduce power dissipa-
tion. However, larger resistances will push the useful adjust-
ment range to the edges of the potentiometer. P1 should
probably not exceed 20kΩ and P2 100kΩ in order to main-
tain reasonable sensitivity.
Software Calibration
To calibrate the offset and gain of the ADS7810, no external
resistors are required. See the No Calibration section for
details on the effects of the external resistor.
No Calibration
See Figure 4b for circuit connections. Note that the actual
voltage dropped across the 50Ω resistor is nearly two orders
of magnitude lower than the voltage dropped across the
internal resistor divider network. This should be taken into
consideration when choosing the accuracy and drift specifi-
cations of the external resistors. In most applications, 1%
metal-film resistors will be sufficient.
The external 50Ω resistor shown in Figure 4b may not be
necessary in some applications. This resistor provides trim
capability for the offset and compensates for a slight gain
adjustment internal to the ADS7810. Not using the 50Ω
resistor will cause a small gain error but will have no effect
on the inherent offset error. Figure 5 shows typical transfer
function characteristics with and without the 50Ω resistor in
the circuit.
REFERENCE
The ADS7810 can operate with its internal 2.5V reference or an
external reference. By applying an external reference to pin 3,
the internal reference can be bypassed. The reference voltage at
REF is buffered internally and output on CAP (pin 4).
REF
REF (pin 3) is an input for an external reference or the
output for the internal 2.5V reference. A 0.1µF capacitor
should be connected as close to the REF pin as possible. The
capacitor and the output resistance of REF create a low pass
filter to band limit noise on the reference. Using a smaller
value capacitor will introduce more noise to the reference
degrading the SNR and SINAD. The internal reference
should not be used to sink or source currents greater than
100µA. In addition, all external loads should be static.
The range for the external reference is 2.3V to 2.7V and
determines the actual LSB size. Increasing the reference
voltage will increase the full scale range and the LSB size
of the converter which can improve the SNR.
FIGURE 5. Comparison of the ADS7810 Transfer Function With and Without the 50Ω Series Resistor on VIN.
–9.84V
–10.0V
Digital
Output
+ Full Scale
Analog
Input
– Full Scale
Typical Transfer Function
with 50Ω Resistor
Typical Transfer Function
without 50Ω Resistor
9.84V 10.0V
®
ADS7810
11
CAP
CAP (pin 4) is the output of the internal reference buffer. A
10µF tantalum capacitor should be placed as close to the
CAP as possible to provide optimum switching currents for
the CDAC throughout the conversion cycle and compensa-
tion for the output of the buffer. Using a capacitor any
smaller than 1µF can cause the output buffer to oscillate and
may not have sufficient charge for the CDAC. Capacitor
values larger than 10µF will have little effect on improving
performance. The voltage on the CAP pin is approximately
2V when using the internal reference, or 80% of an exter-
nally supplied reference.
LAYOUT
POWER
The ADS7810 uses the majority of its power for analog and
static circuitry, and it should be considered as an analog
component. For optimum performance, tie the analog and
digital +5V power pins to the same +5V power supply and
tie the analog and digital grounds together.
For best performance, the ±5V supplies can be produced
from whatever analog supply is used for the rest of the
analog signal conditioning. If ±12V or ±15V supplies are
present, simple regulators can be used. The +5V power for
the A/D should be separate from the +5V used for the
system’s digital logic. Connecting +VDIG (pin 27) directly to
a digital supply can reduce converter performance due to
switching noise from the digital logic.
Although it is not suggested, if the digital supply must be
used to power the converter, be sure to properly filter the
supply. Either using a filtered digital supply or a regulated
analog supply, both VDIG and VANA should be tied to the
same +5V source.
GROUNDING
Three ground pins are present on the ADS7810. DGND
(pin 22) is the digital supply ground. AGND2 (pin 5) is the
analog supply ground. AGND1 (pin 2) is the ground which all
analog signals internal to the A/D are referenced. AGND1 is
more susceptible to current induced voltage drops and must
have the path of least resistance back to the power supply.
All the ground pins of the ADS should be tied to the
analog ground plane, separated from the system’s digital
logic ground, to achieve optimum performance. Both ana-
log and digital ground planes should be tied to the “sys-
tem” ground as near to the power supplies as possible.
This helps to prevent dynamic digital ground currents
from modulating the analog ground through a common
impedance to power ground.
SIGNAL CONDITIONING
The FET switches used for the sample hold on many CMOS
A/D converters release a significant amount of charge injec-
tion which can cause the driving op amp to oscillate. The
resistive front end of the ADS7810 attenuates this charge
and reduces its magnitude significantly—reducing the bur-
den on the external input amplifier or buffer.
However, keep in mind that maintaining signal integrity at
voltage swings of ±10V and frequencies of several hundred
kilohertz is extremely challenging. In addition, the external
input amplifier must drive the ADS7810 mainly during its
sample period—roughly 200ns. This will require a high-
speed, precision amplifier which can swing to greater than
±10V.
For signals where the predominant frequencies are below
200kHz, the OPA671 operational amplifier should be ad-
equate for most applications. In some cases or where input
frequencies are higher, a composite configuration of the
OPA671 and BUF634 (in its wide bandwidth mode) may be
the best choice. See the BUF634 data sheet for more infor-
mation.
The resistive front end of the ADS7810 also provides a
guaranteed ±25V over voltage protection. In most cases, this
eliminates the need for external input protection circuitry.
INTERMEDIATE LATCHES
The ADS7810 does have tri-state outputs for the parallel
port, but intermediate latches should be used if the bus will
be active during conversions. If the bus is not active during
conversions, the tri-state outputs can be used to isolate the
A/D from other peripherals on the same bus.
Intermediate latches are beneficial on any monolithic A/D
converter. The ADS7810 has an internal LSB size of 610µV.
Transients from fast switching signals on the parallel port,
even when the A/D is tri-stated, can be coupled through the
substrate to the analog circuitry causing degradation of
converter performance.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
ADS7810U ACTIVE SOIC DW 28 28 Pb-Free
(RoHS) CU NIPDAU Level-3-260C-168 HR
ADS7810U/1K ACTIVE SOIC DW 28 1000 Pb-Free
(RoHS) CU NIPDAU Level-3-260C-168 HR
ADS7810U/1KE4 ACTIVE SOIC DW 28 1000 Pb-Free
(RoHS) CU NIPDAU Level-3-260C-168 HR
ADS7810UB ACTIVE SOIC DW 28 28 Pb-Free
(RoHS) CU NIPDAU Level-3-260C-168 HR
ADS7810UB/1KE4 ACTIVE SOIC DW 28 1000 Pb-Free
(RoHS) CU NIPDAU Level-3-260C-168 HR
ADS7810UBE4 ACTIVE SOIC DW 28 28 Pb-Free
(RoHS) CU NIPDAU Level-3-260C-168 HR
ADS7810UE4 ACTIVE SOIC DW 28 28 Pb-Free
(RoHS) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2006
Addendum-Page 1
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