General Description
The MAX9169/MAX9170 low-jitter, low-voltage differen-
tial signaling LVDS/LVTTL-to-LVDS repeaters are ideal
for applications that require high-speed data or clock
distribution while minimizing power, space, and noise.
The devices accept a single LVDS (MAX9169) or LVTTL
(MAX9170) input and repeat the input at four LVDS out-
puts. Each differential output drives 100Ω, allowing
point-to-point distribution of signals on transmission
lines with 100Ωtermination at the receiver input. The
MAX9169 and MAX9170 are pin compatible with the
SN65LVDS104 and SN65LVDS105, respectively, and
offer improved pulse-skew performance.
Ultra-low 150ps (max) pulse skew and 200psP-P (max)
added deterministic jitter ensure reliable communica-
tion in high-speed links that are highly sensitive to tim-
ing error, especially those incorporating clock-and-data
recovery or serializers and deserializers. The high-
speed switching performance guarantees 630Mbps
data rate and less than 120ps channel-to-channel skew
over the 3.0V to 3.6V operating supply range.
Supply current is 30mA (max) for the MAX9169, and
25mA (max) for the MAX9170. LVDS inputs and outputs
conform to the ANSI EIA/TIA-644 standard. A fail-safe
feature on the MAX9169 sets the output high when the
input is undriven and open, terminated, or shorted. The
MAX9169/MAX9170 are offered in 16-pin TSSOP and
SO packages, and operate over an extended -40°C to
+85°C temperature range.
Refer to the MAX9130 data sheet for an LVDS line
receiver in an SC70 package.
Applications
Point-to-Point Baseband Data Transmission
Cellular Phone Base Stations
Add/Drop Muxes
Digital Cross-Connects
Network Switches/Routers
Backplane Interconnect
Clock Distribution
Features
♦150ps (max) Pulse Skew
♦200psP-P (max) Added Deterministic Jitter at
630Mbps (223 - 1) PRBS Pattern
♦8psRMS (max) Added Random Jitter
♦120ps (max) Channel-to-Channel Skew
♦630Mbps Data Rate
♦Conforms to ANSI EIA/TIA-644 LVDS Standard
♦30mA (max) (MAX9169), 25mA (max) (MAX9170)
Supply Current, a 15% Improvement vs.
Competition
♦LVDS (MAX9169) or +5V Tolerant LVTTL/LVCMOS
(MAX9170) Input Versions
♦Fail-Safe Circuit Sets Output High for Undriven
Differential Input
♦Output Rated for 10pF Load
♦Individual Output Enables
♦Single 3.3V Supply
♦Improved Second Source of the SN65LVDS104
(MAX9169)/SN65LVDS105 (MAX9170)
♦16-Pin SO and TSSOP Packages
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
MAX9180
MAX9169
MAX9130
MAX9130
100Ω
LVDS
LVDS
BACKPLANE
OR CABLE
1
4
Rx
Rx
100Ω
100Ω
Typical Application Circuit
19-2616; Rev 0; 10/02
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Pin Configurations appear at end of data sheet.
PART TEMP RANGE PIN-
PACKAGE INPUT
MAX9169ESE -40°C to +85°C 16 SO LVDS
MAX9169EUE -40°C to +85°C 16 TSSOP LVDS
MAX9170ESE -40°C to +85°C 16 SO LVTTL
MAX9170EUE -40°C to +85°C 16 TSSOP LVTTL
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, RL= 100Ω±1%, EN_ = high, MAX9169 differential input voltage | VID | = 0.05V to 1.2V, LVDS input common-
mode voltage VCM = | VID/2 | to +2.4V - | VID/2 |, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, | VID |
= 0.2V, VCM = 1.25V, TA= +25°C for MAX9169. Typical values are at VCC = 3.3V, VIN = 0 or VCC, TA= +25°C for MAX9170.)
(Notes 1 and 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC to GND..............................................................-0.5V to +4V
Inputs
IN+, IN- to GND....................................................-0.5V to +4V
IN, EN_ to GND ....................................................-0.5V to +6V
Outputs
OUT_+, OUT_- to GND.........................................-0.5V to +4V
Continuous Power Dissipation (TA= +70°C)
16-Pin SO (derate 8.7mW/°C above +70°C)................696mW
16-Pin TSSOP (derate 9.4mW/°C above +70°C) .........755mW
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
ESD Protection
Human Body Model (MAX9169)
(IN+, IN-, OUT_+, OUT_-) ..............................................≥16kV
Human Body Model (MAX9170)
(OUT_+, OUT_-) .............................................................≥10kV
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LVDS INPUTS (IN+, IN-) (MAX9169)
Differential Input High Threshold VTH 550mV
Differential Input Low Threshold VTL -50 -5 mV
VIN = 0V, other input open, Figure 1 -2 -11.8 -20
Input Current
(IN+ or IN-, Single Ended) IIN+
,
IIN- VIN = +2.4V, other input open, Figure 1 -1.2 -3.2 µA
Power-Off Input Current
(IN+ or IN-, Single Ended) IINO+
,
IINO- VCC = +1.5V, VIN = +2.4V, other input open,
Figure 1 3.2 20 µA
0.05V ≤VID≤ 0.6V, Figure 1 -15 +15
Input Current IIN+
,
IIN- 0.6V <VID≤ 1.2V, Figure 1 -20 +20 µA
0.05V ≤VID≤ 0.6V, VCC = 1.5V, Figure 1 -15 +15
Power-Off Input Current IINO+
,
IINO- 0.6V <VID≤ 1.2V, VCC = 1.5V, Figure 1 -20 +20 µA
RIN1 VCC = 3.6V, 0 or open, Figure 1 103 138 190
Fail-Safe Input Resistor RIN2 VCC = 3.6V, 0 or open, Figure 1 154 210 260 kΩ
Input Capacitance CIN IN+ or IN- to GND (Note 3) 2.2 pF
+5V TOLERANT LVTTL/LVCMOS INPUTS (IN, EN_)
Input High Voltage VIH 2.0 5.5 V
Input Low Voltage VIL 0 0.8 V
IIH VIN = 2V to 5.5V 20
Input Current IIL VIN = 0 to 0.8V 10 µA
Input Capacitance (MAX9170) CIN IN to GND (Note 3) 2.2 pF
LVDS OUTPUTS (OUT_+, OUT_-)
Differential Output Voltage VOD Figures 3, 4, 6, 7 250 350 450 mV
Change in VOD Between
Complementary Output States ∆VOD Figures 3, 4, 6, 7 1.5 25 mV
Steady-State Output Offset
Voltage VOS Figures 2, 4, 5, 7, 8, 9 1.125 1.26 1.375 V
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.0V to 3.6V, RL= 100Ω±1%, EN_ = high, MAX9169 differential input voltage | VID | = 0.05V to 1.2V, LVDS input common-
mode voltage VCM = | VID/2 | to +2.4V - | VID/2 |, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, | VID |
= 0.2V, VCM = 1.25V, TA= +25°C for MAX9169. Typical values are at VCC = 3.3V, VIN = 0 or VCC, TA= +25°C for MAX9170.)
(Notes 1 and 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Change in VOS Between
Complementary Output States ∆VOS Figures 2, 4, 5, 7, 8, 9 1.5 25 mV
Peak-to-Peak Output Offset
Voltage VOS
(
P-P
)
Figures 8, 9 (Note 4) 40 150 mV
VOH Figures 3, 4, 6, 7 1.65
Output Voltage VOL Figures 3, 4, 6, 7 0.9 V
Fail-Safe Differential Output
Voltage (MAX9169) VOD+ IN+, IN- open, undriven and shorted, or
undriven and parallel terminated +250 +350 +450 mV
High-Impedance Output Current IOZ EN_ = low, VOUT_+ = +3.6V or 0,
VOUT_- = +3.6V or 0 -0.5 0.01 +0.5 µA
Power-Off Output Current IOFF VCC = +1.5V, VOUT_+ = +3.6V or 0,
VOUT_- = +3.6V or 0 -0.5 0.01 +0.5 µA
Output Short-Circuit Current IOS VID = +50mV or -50mV,
VOUT+ = 0 or VCC, VOUT- = 0 or VCC -10 ±5.8 +10 mA
Magnitude of Differential Output
Short-Circuit Current IOSD VID = +50mV or -50mV, VOD = 0 (Note 5) 5.8 10 mA
Output Capacitance COOUT_+ or OUT_- to GND (Note 6) 3.6 pF
POWER SUPPLY
MAX9169 22 30
DC, RL = 100Ω,
Figures 10, 13 MAX9170 18 25
MAX9169 43 60
Supply Current ICC 315MHz (630Mbps),
RL = 100Ω, Figures 10, 13 MAX9170 41 55
mA
MAX9169 6.8 8.0
Disabled Supply Current ICCZ EN_ = low MAX9170 4.3 6.4 mA
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
4 _______________________________________________________________________________________
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTH, VTL, VID, VOD, and ∆VOD.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at TA= +25°C.
Note 3: Signal generator output for IN+, IN-, or single-ended IN: VIN = 0.4 sin(4E6πt) + 0.5.
Note 4: All input pulses are supplied by a generator having the following characteristics: tRor tF≤1ns, pulse repetition rate (PRR) =
0.5 Mpps, pulsewidth = 500 ±10ns.
Note 5: Guaranteed by design and characterization.
Note 6: Signal generator output for OUT+ or OUT-: VIN = 0.4 sin(4E6πt) + 0.5, EN_ = low.
Note 7: CLincludes scope probe and test jig capacitance.
Note 8: Signal generator output for differential inputs IN+, IN- (unless otherwise noted): frequency = 50MHz, 49% to 51% duty cycle,
RO= 50Ω, tR= 1.0ns, and tF= 1.0ns (0% to 100%). Signal generator output for single-ended input IN (unless otherwise noted):
frequency = 50MHz, 49% to 51% duty cycle, RO= 50Ω, VIH = VCC, VIL = 0V, tR= 1.0ns, and tF= 1.0ns (0% to 100%).
Note 9: Signal generator output for MAX9169 tDJ: VOH = +1.3V, VOL = +1.1V, data rate = 630Mbps, 223 -1 PRBS, RO= 50Ω,
tR= 1.0ns and tF= 1.0ns (0% to 100%). Signal generator output for MAX9170 tDJ: VOH = VCC, VOL = 0V, data rate =
630Mbps, 223 -1 PRBS, RO= 50Ω, tR= 1.0ns, and tF= 1.0ns (0% to 100%).
Note 10: Signal generator output for MAX9169 tRJ: VOH = +1.3V, VOL = +1.1V, frequency = 315MHz, 50% duty cycle, RO= 50Ω,
tR= 1.0ns, and tF= 1.0ns (0% to 100%). Signal generator output for MAX9170 tRJ: VOH = VCC, VOL = 0V, frequency =
315MHz, 50% duty cycle, RO= 50Ω, tR= 1.0ns, and tF= 1.0ns (0% to 100%).
Note 11: Signal generator output for MAX9169 tSK(P): VOH = +1.4V, VOL = +1.0V, RO= 50Ω, tR= 1.0ns, and tF= 1.0ns (0% to 100%).
Signal generator output for MAX9170 tSK(P): VOH = +3.0, VOL = 0V, RO= 50Ω, tR= 1.0ns, and tF= 1.0ns (0% to 100%).
Note 12: tSK(0) is the magnitude of the time difference between tPLH or tPHL of all drivers of a single device with all of their inputs
connected together.
Note 13: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when
both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, RL= 100Ω±1%, CL= 10pF, EN_ = high, MAX9169 differential input voltage | VID | = 0.15V to 1.2V, LVDS input
common-mode voltage VCM = | VID/2 | to +2.4V - | VID/2 |, TA= -40°C to +85°C, unless otherwise noted. Typical values are at | VID | =
0.2V, VCM = 1.25V, VCC = 3.3V, TA= +25°C for MAX9169. Typical values are at VIN = 0 or VCC, VCC = 3.3V, TA= +25°C for
MAX9170.) (Notes 5, 7, and 8)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Rise Time tRFigures 10–15 0.6 0.8 1.2 ns
Fall Time tFFigures 10–15 0.6 0.8 1.2 ns
Added Deterministic Jitter tDJ (Note 9) 110 200 ps
Added Random Jitter tRJ (Note 10) 6 8 ps
MAX9169 2.2 3.5 4.2
Differential Propagation Delay
High to Low tPHL Figures 10, 11, 13, 14 MAX9170 1.5 2.6 3.2 ns
MAX9169 2.2 3.5 4.2
Differential Propagation Delay
Low to High tPLH Figures 10, 11, 13, 14 MAX9170 1.5 2.6 3.2 ns
Pulse Skew tPLH - tPHLtSKEW Figures 10, 11, 13, 14 40 250 ps
Pulse Skew tPLH - tPHLtSK(P) Figures 10, 12, 13, 15 (Note 11) 40 150 ps
MAX9169, Figures 10, 11, 12 25 120
Channel-to-Channel Skew
(Note 12) tSK(0) MAX9170, Figures 13, 14, 15 15 100 ps
MAX9169, Figures 10, 11, 12 0.28 1.2
Differential Part-to-Part Skew
(Note 13) tSK(PP) MAX9170, Figures 13, 14, 15 0.19 1.2 ns
tPHZ High to high-Z, Figures 16–19 11 15
Disable Time tPLZ Low to high-Z, Figures 16–19 11.8 15 ns
tPZH High-Z to high, Figures 16–19 2.3 10
Enable Time tPZL High-Z to low, Figures 16–19 5.8 10 ns
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
_______________________________________________________________________________________ 5
MAX9169 SUPPLY CURRENT
vs. FREQUENCY
MAX9169/70 toc01
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
2702251801359045
10
20
30
40
50
0
0 315
4 CHANNELS ACTIVE
3 CHANNELS ACTIVE
2 CHANNELS ACTIVE
1 CHANNEL ACTIVE
ALL CHANNELS DISABLED
MAX9170 SUPPLY CURRENT
vs. FREQUENCY
MAX9169/70 toc02
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
2702251801359045
10
20
30
40
0
0 315
4 CHANNELS ACTIVE
3 CHANNELS ACTIVE
2 CHANNELS ACTIVE
1 CHANNEL ACTIVE
ALL CHANNELS DISABLED
DIFFERENTIAL OUTPUT AMPLITUDE
vs. FREQUENCY
MAX9169/70 toc03
FREQUENCY (MHz)
DIFFERENTIAL OUTPUT AMPLITUDE (mV)
2702251801359045
240
280
320
360
200
0 315
VCC = 3.6V
VCC = 3.3V
VCC = 3.0V
TRANSITION TIME
vs. TEMPERATURE
MAX9169/70 toc04
TEMPERATURE (°C)
TRANSITION TIME (ns)
603510-15
740
760
780
800
820
840
720
-40 85
trtf
MAX9169 PROPAGATION DELAY
vs. TEMPERATURE
MAX9169/70 toc05
TEMPERATURE (°C)
PROPAGATION DELAY (ns)
603510-15
3.3
3.4
3.5
3.6
3.7
3.8
3.2
-40 85
tPHL
tPLH
MAX9170 PROPAGATION DELAY
vs. TEMPERATURE
MAX9169/70 toc06
TEMPERATURE (°C)
PROPAGATION DELAY (ns)
603510-15
2.5
2.6
2.7
2.8
2.9
2.4
-40 85
tPLH
tPHL
DIFFERENTIAL OUTPUT VOLTAGE
vs. LOAD RESISTOR
MAX9169/70 toc07
LOAD RESISTOR (Ω)
DIFFERENTIAL OUTPUT VOLTAGE (mV)
12510075
200
300
400
500
600
100
50 150
TRANSITION TIME
vs. CAPACITIVE LOAD
MAX9169/70 toc08
CAPACITIVE LOAD (pF)
TRANSITION TIME (ps)
131197
750
800
850
900
950
700
515
tr
tf
Typical Operating Characteristics
(VCC = 3.3V, RL= 100Ω, CL= 10pF, | VID | = 150mV, VCM = 1.25V, fIN = 50MHz, TA= +25°C, unless otherwise noted.)
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
6 _______________________________________________________________________________________
Pin Description
Table 1. MAX9169 Input/Output Functions
PIN
MAX9169 MAX9170 NAME FUNCTION
1 1 EN1
OUT1+/OUT1- Enable. +5V tolerant LVTTL/LVCMOS input. Set EN1 high to enable
OUT1+/OUT1-. Set EN1 low to disable OUT1+/OUT1- (high-impedance mode). Integrated
pulldown to GND.
2 2 EN2
OUT2+/OUT2- Enable. +5V tolerant LVTTL/LVCMOS input. Set EN2 high to enable
OUT2+/OUT2-. Set EN2 low to disable OUT2+/OUT2- (high-impedance mode). Integrated
pulldown to GND.
3 3 EN3
OUT3+/OUT3- Enable. +5V tolerant LVTTL/LVCMOS input. Set EN3 high to enable
OUT3+/OUT3-. Set EN3 low to disable OUT3+/OUT3- (high-impedance mode). Integrated
pulldown to GND.
44V
CC Power-Supply Voltage. Bypass with 0.1µF and 0.001µF capacitors to ground.
5 5 GND Ground
6—IN+ Noninverting Differential LVDS Input
7—IN- Inverting Differential LVDS Input
8 8 EN4
OUT4+/OUT4- Enable. +5V tolerant LVTTL/LVCMOS input. Set EN4 high to enable
OUT4+/OUT4-. Set EN4 low to disable OUT4+/OUT4- (high-impedance mode). Integrated
pulldown to GND.
9 9 OUT4- Inverting Differential LVDS Output
10 10 OUT4+ Noninverting Differential LVDS Output
11 11 OUT3- Inverting Differential LVDS Output
12 12 OUT3+ Noninverting Differential LVDS Output
13 13 OUT2- Inverting Differential LVDS Output
14 14 OUT2+ Noninverting Differential LVDS Output
15 15 OUT1- Inverting Differential LVDS Output
16 16 OUT1+ Noninverting Differential LVDS Output
—6 IN Data Input, 5V Tolerant LVTTL/LVCMOS. Integrated pulldown to GND.
—7 N.C. No Connection
INPUT OUTPUT
VID = VIN+ - VIN- EN_ VOD
X Low or open High-Z
+50mV High High
-50mV High Low
Open High High
Undriven short High High
Undriven parallel terminated High High
Table 2. MAX9170 Input/Output Functions
INPUT OUTPUT
VIN EN_ VOD
X Low or open High-Z
High High High
Low High Low
Open High Low
Detailed Description
LVDS is a signaling method for point-to-point and
multidrop data communication over a controlled-imped-
ance medium as defined by the ANSI TIA/EIA-644 and
IEEE 1596.3 standards. LVDS uses a lower voltage swing
than other common standards, achieving higher data
rates with reduced power consumption, while reducing
EMI emissions and system susceptibility to noise.
The MAX9169/MAX9170 are 630Mbps, four-port
repeaters for high-speed, low-power applications. The
MAX9169 accepts an LVDS input and has a fail-safe
input circuit. The MAX9170 features a +5V tolerant sin-
gle-ended LVTTL/LVCMOS input. Both devices repeat
the input at four LVDS outputs. The MAX9169 detects
differential signals as low as 50mV and as high as 1.2V
over a |VID|/2 to 2.4V - |VID|/2 common-mode range.
The MAX9170’s +5V tolerant LVTTL/LVCMOS input
includes circuitry to hold the decision threshold con-
stant at +1.5V over temperature and supply voltage.
The MAX9169/MAX9170 outputs use a current-steering
configuration to generate a 2.5mA to 4.5mA output cur-
rent. This current-steering approach induces less ground
bounce and shoot-through current, enhancing noise
margin and system speed performance. The outputs are
short-circuit current limited and are high impedance
when disabled or when the device is not powered.
The MAX9169/MAX9170 current-steering output requires
a resistive load to terminate the signal and complete the
transmission loop. Because the devices switch the direc-
tion of current flow and not voltage levels, the output volt-
age swing is determined by the value of the termination
resistor multiplied by the output current. With a typical
3.5mA output current, the MAX9169/MAX9170 produce
a 350mV output voltage when driving a transmission line
terminated with a 100Ωresistor (3.5mA ✕100Ω=
350mV). Logic states are determined by the direction of
current flow through the termination resistor.
Fail-Safe Circuitry
The fail-safe feature of the MAX9169 sets the outputs
high when the differential input is:
•Open
•Undriven and shorted
•Undriven and terminated
Without a fail-safe circuit, when the input is undriven,
noise at the input may switch the outputs and it may
appear to the system that data is being sent. Open or
undriven terminated input conditions can occur when a
cable is disconnected or cut, or when an LVDS driver
output is in high impedance. A shorted input can occur
because of cable failure.
When the input is driven with signals meeting the LVDS
standard, the input common-mode voltage is less than
VCC - 0.3V and the fail-safe circuit is not activated
(Figure 1). If the input is open, undriven and shorted, or
undriven and parallel terminated, an internal resistor in
the fail-safe circuit pulls both the inputs above VCC -
0.3V, activating the fail-safe circuit and forcing the out-
puts high.
Applications Information
Supply Bypassing
Bypass VCC with high-frequency surface-mount ceram-
ic 0.1µF and 0.001µF capacitors in parallel as close to
the device as possible, with the smaller value capacitor
closest to the VCC pin. Use multiple parallel vias to min-
imize parasitic inductance.
Traces, Cables, and Connectors
The characteristics of differential input and output con-
nections affect the performance of the MAX9169/
MAX9170. Use controlled-impedance traces, cables,
and connectors with matched characteristic impedance.
Ensure that noise couples as common mode by run-
ning the traces of a differential pair close together.
Reduce within-pair skew by matching the electrical
length of the traces of a differential pair. Excessive
skew can result in a degradation of magnetic field can-
cellation. Maintain a constant distance between traces
of a differential pair to avoid discontinuities in differen-
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
_______________________________________________________________________________________ 7
MAX9169
VCC
RIN2
RIN1/2
RIN1/2
VCC - 0.3V
COMPARATOR
IN+
IN-
RECEIVER
OUT1+
OUT1-
OUT4+
OUT4-
Figure 1. MAX9169 Input Fail-Safe Circuit
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
8 _______________________________________________________________________________________
MAX9169
IN+
IN-
PULSE
GENERATOR
50Ω
50Ω
OUT1+
OUT4+
OUT4-
OUT1-
VOS
VOS
50Ω
50Ω
50Ω
50Ω
10pF
10pF
10pF
10pF
Figure 2. MAX9169 Output Offset Voltage Test Circuit
Test Circuits and Timing Diagrams
tial impedance. Minimize the number of vias to further
prevent impedance discontinuities.
Avoid the use of unbalanced cables, such as ribbon
cable. Balanced cables, such as twisted pair, offer
superior signal quality and tend to generate less EMI
due to canceling effects. Balanced cables tend to pick
up noise as common mode, which is rejected by the
LVDS receiver.
Termination
The MAX9169/MAX9170 LVDS outputs are specified for
a 100Ωload but can drive 90Ωto 132Ωto accommo-
date various types of interconnect. The termination
resistor at the driven receiver should match the differ-
ential characteristic impedance of the interconnect and
be located close to the receiver input. Use a ±1% sur-
face-mount termination resistor.
Board Layout
A four-layer PC board with separate layers for power,
ground, and LVDS signals is recommended. Keep
LVTTL/LVCMOS signals separated from the LVDS sig-
nals to prevent crosstalk to the LVDS lines.
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
_______________________________________________________________________________________ 9
MAX9169
IN+
IN-
PULSE
GENERATOR
50Ω
50Ω
OUT1+
OUT1-
VOD 100Ω
3.75kΩ
3.75kΩ
0V ≤ VTEST ≤ 2.4V
OUT4+
OUT4-
VOD 100Ω
3.75kΩ
3.75kΩ
0V ≤ VTEST ≤ 2.4V
Figure 3. MAX9169 Differential Output Voltage Test Circuit
Test Circuits and Timing Diagrams (continued)
IN-
IN+
DIFFERENTIAL
0V VID
OUT_-
OUT_+
VOS(-) VOS(-)
VOS(+)
(OUT_+) - (OUT_-)
VCM = ((VIN+) - (VIN-)) / 2
∆VOS = | (VOS(+)) - (VOS(-)) |
∆VOD = | (VOD_+) - (VOD_-) |
VOL
VOH
VOD = 0V
VOD_-
VOD_+
Figure 4. MAX9169 Output DC Parameters
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
10 ______________________________________________________________________________________
MAX9170
IN
PULSE
GENERATOR
50Ω
OUT1+
OUT4+
OUT4-
OUT1-
VOS
VOS
50Ω
50Ω
50Ω
50Ω
10pF
10pF
10pF
10pF
Figure 5. MAX9170 Output Offset Voltage Test Circuit
Test Circuits and Timing Diagrams (continued)
MAX9170
IN
PULSE
GENERATOR
50Ω
OUT1+
OUT1-
VOD 100Ω
3.75kΩ
3.75kΩ
0V ≤ VTEST ≤ 2.4V
OUT4+
OUT4-
VOD 100Ω
3.75kΩ
3.75kΩ
0V ≤ VTEST ≤ 2.4V
Figure 6. MAX9170 Differential Output Voltage Test Circuit
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
______________________________________________________________________________________ 11
IN
OUT_-
OUT_+
VOS(-) VOS(-)
VOS(+)
(OUT_+) - (OUT_-)
∆VOS = | (VOS(+)) - (VOS(-)) |
∆VOD = | (VOD_+) - (VOD_-) |
VOL
VOH
VIH
VIL
VOD = 0V
VOD_-
VOD_+
Figure 7. MAX9170 LVDS Output DC Parameters
Test Circuits and Timing Diagrams (continued)
IN-
IN+
VOS(-)
VOS(+)
VOS(-)
VOS(P-P)
1.25V
1.20V
VID = 50mV
∆VOS
Figure 8. MAX9169 Output Offset Voltage Waveforms
IN
VOS(-)
VOS(+)
VOS(-)
VOS(P-P)
3V
0V
∆VOS
Figure 9. MAX9170 Output Offset Voltage Waveforms
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
12 ______________________________________________________________________________________
MAX9169
IN+
IN-
PULSE
GENERATOR
50Ω
50Ω
OUT1+
OUT4+
OUT4-
OUT1-
CL
10pF
CL
10pF
RL
100Ω
CL
10pF
CL
10pF
RL
100Ω
Figure 10. MAX9169 Propagation Delay and Transition Time Test Circuit
Test Circuits and Timing Diagrams (continued)
IN-
IN+
20%
80%
80%
0V 0V
20%
DIFFERENTIAL
0V
tPLH tPHL
VCM VID
VOD
tRtF
(VIN+) - (VIN-)
2
VCM =
VOD = (VOUT_+) - (VOUT_-)
Figure 11. MAX9169 Propagation Delay and Transition Time Waveforms
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
______________________________________________________________________________________ 13
IN-
IN+
20%
1.0V
1.4V
80%
80%
0V 0V
20%
VCM = 1.2V VCM = 1.2V
tPLH tPHL
VOD
tRtF
VOD = (VOUT_+) - (VOUT_-)
Figure 12. MAX9169 Propagation Delay and Transition Time Waveforms, tSK(p)
Test Circuits and Timing Diagrams (continued)
MAX9170
IN
PULSE
GENERATOR
50Ω
OUT1+
OUT4+
OUT4-
OUT1-
CL
10pF
CL
10pF
RL
100Ω
CL
10pF
CL
10pF
RL
100Ω
Figure 13. MAX9170 Propagation Delay and Transition Time Test Circuit
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
14 ______________________________________________________________________________________
IN
20%
80%
80%
0V 0V
0V
VCC
20%
VCC/2 VCC/2
tPLH tPHL
VOD
tRtF
VOD = (VOUT_+) - (VOUT_-)
Figure 14. MAX9170 Propagation Delay and Transition Time Waveforms
Test Circuits and Timing Diagrams (continued)
IN
20%
80%
80%
0V 0V
0V
3.0V
20%
1.5V 1.5V
tPLH tPHL
VOD
tRtF
VOD = (VOUT_+) - (VOUT_-)
Figure 15. MAX9170 Propagation Delay and Transition Time Waveforms, tSK(p)
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
______________________________________________________________________________________ 15
MAX9169
IN+
1.25V
1.20V
1.25V
1.20V
IN-
EN_
PULSE
GENERATOR
50Ω
OUT_+
OUT_-
1.2V
CL
10pF
CL
10pF
50Ω
50Ω
Figure 16. MAX9169 Enable and Disable Time Test Circuit
Test Circuits and Timing Diagrams (continued)
MAX9170
2.0V
0.8V
IN
EN_
PULSE
GENERATOR
50Ω
OUT_+
OUT_-
1.2V
CL
10pF
CL
10pF
50Ω
50Ω
Figure 17. MAX9170 Enable and Disable Time Test Circuit
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
16 ______________________________________________________________________________________
1.2V
1.2V
3V
~1.4V
~1.0V
OV
1.5V
1.25V
1.15V
1.25V
1.15V
tPHZ
tPLZ
tPZH
tPZL
1.5V
EN_
VOUT_+ WHEN VID = +50mV
VOUT_- WHEN VID = -50mV
VOUT_+ WHEN VID = -50mV
VOUT_- WHEN VID = +50mV
Figure 18. MAX9169 Enable and Disable Time Waveforms
Test Circuits and Timing Diagrams (continued)
1.2V
1.2V
3V
~1.4V
~1.0V
OV
1.5V
1.25V
1.15V
1.25V
1.15V
tPHZ
tPLZ
tPZH
tPZL
1.5V
EN_
VOUT_+ WHEN VIN = 2.0V
VOUT_- WHEN VIN = 0.8V
VOUT_+ WHEN VIN = 0.8V
VOUT_- WHEN VIN = 2.0V
Figure 19. MAX9170 Enable and Disable Time Waveforms
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
______________________________________________________________________________________ 17
MAX9169
1
EN1
2
EN2
3
EN3
4
VCC
5
GND
6
IN+
7
IN-
8
16
15
14
13
12
11
10
9
EN4
OUT1+
OUT1-
OUT2+
OUT2-
OUT3+
OUT3-
OUT4+
OUT4-
OUT1+
OUT1-
OUT2+
OUT2-
OUT3+
OUT3-
OUT4+
OUT4-
TSSOP/SO
MAX9170
1
EN1
2
EN2
3
EN3
4
VCC
5
GND
6
IN
7
N.C.
8
16
15
14
13
12
11
10
9
EN4
TSSOP/SO
TOP VIEW
Pin Configurations
Chip Information
TRANSISTOR COUNT: 1187
PROCESS: CMOS
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
18 ______________________________________________________________________________________
TSSOP4.40mm.EPS
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
16L SOIC.EPS
