TT-E-20-SLE-50/N - OMEGA Engineering, Inc

LTC2471/LTC2473

24713fb

For more information www.linear.com/LTC2471

–50 –10 10–30 50 7030 90

TEMPERATURE (°C)

REFERENCE OUTPUT VOLTAGE (V)

1.2520

1.2515

1.2510

1.2505

1.2500

24713 TA01b

1.2480

1.2485

1.2490

1.2495

Typical applicaTion

FeaTures

applicaTions

DescripTion

Selectable 208sps/833sps,

16-Bit I2C ΔΣ ADCs with 10ppm/°C

Max Precision Reference

The LTC

2471/LTC2473 are small, 16-bit analog-to-digital

converters with an integrated precision reference and

a selectable 208sps or 833sps output rate. They use a

single 2.7V to 5.5V supply and communicate through an

I2C Interface. The LTC2471 is single-ended with a 0V to

VREF input range and the LTC2473 is differential with a

±VREF input range. Both ADCs include a 1.25V integrated

reference with 2ppm/°C drift performance and 0.1% initial

accuracy. The converters are available in a 12-pin DFN

3mm × 3mm package or an MSOP-12 package. They

include an integrated oscillator and perform conversions

with no latency for multiplexed applications. The LTC2471/

LTC2473 include a proprietary input sampling scheme

that reduces the average input current several orders of

magnitude when compared to conventional delta sigma

converters.

Following a single conversion, the LTC2471/LTC2473

automatically power down the converter and can also be

conﬁgured to power down the reference. When both the

ADC and reference are powered down, the supply current

is reduced to 200nA.

The LTC2471/LTC2473 include a user selectable 208sps

or 833sps output rate and due to a large oversampling

ratio (8,192 at 208sps and 2,048 at 833sps) have relaxed

anti-aliasing requirements.

VREF vs Temperature

n 16-Bit Resolution

n Internal, High Accuracy Reference—10ppm/°C (Max)

n Single-Ended (LTC2471) or Differential (LTC2473)

n Selectable 208sps/833sps Output Rate

n 1mV Offset Error

n 0.01% Gain Error

n Single Conversion Settling Time Simpliﬁes

Multiplexed Applications

n Single-Cycle Operation with Auto Shutdown

n 3.5mA (Typ) Supply Current

n 2µA (Max) Sleep Current

n Internal Oscillator—No External Components

Required

n I2C Interface

n Small 12-Lead, 3mm × 3mm DFN and MSOP

Packages

n System Monitoring

n Environmental Monitoring

n Direct Temperature Measurements

n Instrumentation

n Industrial Process Control

n Data Acquisition

n Embedded ADC Upgrades

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation and Easy Drive and No Latency ∆∑ is a trademark of Linear Technology

Corporation. All other trademarks are the property of their respective owners. Protected by U.S.

Patents, including 6208279, 6411242, 7088280, 7164378.

10k

SCL I2C

INTERFACE

SDA

0.1µF

2.7V TO 5.5V

10µF

0.1µF

IN+

REFOUT

REF–

VCC

0.1µF

COMP

GND

IN–

0.1µF

LTC2473

24713 TA01a

LTC2471/LTC2473

24713fb

For more information www.linear.com/LTC2471

pin conFiguraTion

absoluTe MaxiMuM raTings

Supply Voltage (VCC) ................................... –0.3V to 6V

Analog Input Voltage (VIN+, VIN–,

VIN, VREF–, VCOMP, VREFOUT) ..........–0.3V to (VCC + 0.3V)

Digital Voltage (VSDA, VSCL, VAO) ....–0.3V to (VCC + 0.3V)

(Notes 1, 2)

orDer inForMaTion

Storage Temperature Range .................. –65°C to 150°C

Operating Temperature Range

LTC2471C/LTC2473C ............................... 0°C to 70°C

LTC2471I/LTC2473I .............................–40°C to 85°C

LTC2473 LTC2473

TOP VIEW

DD PACKAGE

12-LEAD (3mm × 3mm) PLASTIC DFN

1VCC

GND

IN–

IN+

REF–

GND

REFOUT

COMP

GND

SCL

SDA 67

GND

TJMAX = 125°C, θJA = 43°C/W

EXPOSED PAD (PIN 13) PCB GROUND CONNECTION

REFOUT

COMP

GND

SCL

SDA

VCC

GND

IN–

IN+

REF–

GND

TOP VIEW

MS PACKAGE

12-LEAD PLASTIC MSOP

TJMAX = 125°C, θJA = 130°C/W

LTC2471 LTC2471

TOP VIEW

DD PACKAGE

12-LEAD (3mm × 3mm) PLASTIC DFN

1VCC

GND

REF–

GND

REFOUT

COMP

GND

SCL

SDA 67

GND

TJMAX = 125°C, θJA = 43°C/W

EXPOSED PAD (PIN 13) PCB GROUND CONNECTION

REFOUT

COMP

GND

SCL

SDA

VCC

GND

REF–

GND

TOP VIEW

MS PACKAGE

12-LEAD PLASTIC MSOP

TJMAX = 125°C, θJA = 130°C/W

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2471CDD#PBF LTC2471CDD#TRPBF LFPW 12-Lead Plastic (3mm × 3mm) DFN 0°C to 70°C

LTC2471IDD#PBF LTC2471IDD#TRPBF LFPW 12-Lead Plastic (3mm × 3mm) DFN –40°C to 85°C

LTC2471CMS#PBF LTC2471CMS#TRPBF 2471 12-Lead Plastic MSOP 0°C to 70°C

LTC2471IMS#PBF LTC2471IMS#TRPBF 2471 12-Lead Plastic MSOP –40°C to 85°C

LTC2473CDD#PBF LTC2473CDD#TRPBF LFPX 12-Lead Plastic (3mm × 3mm) DFN 0°C to 70°C

LTC2473IDD#PBF LTC2473IDD#TRPBF LFPX 12-Lead Plastic (3mm × 3mm) DFN –40°C to 85°C

LTC2473CMS#PBF LTC2473CMS#TRPBF 2473 12-Lead Plastic MSOP 0°C to 70°C

LTC2473IMS#PBF LTC2473IMS#TRPBF 2473 12-Lead Plastic MSOP –40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

LTC2471/LTC2473

24713fb

For more information www.linear.com/LTC2471

elecTrical characTerisTics

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution 16 Bits

Integral Nonlinearity Output Rate 208sps (Note 4)

Output Rate 833sps (Note 4)

8.5

LSB

Offset Error l±1 ±2.5 mV

Offset Error Drift 0.05 LSB/°C

Gain Error l±0.01 ±0.25 % of FS

Gain Error Drift l0.15 LSB/°C

Transition Noise 3 µVRMS

Power Supply Rejection DC 80 dB

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 2)

analog inpuTs

The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise

speciﬁcations are at TA = 25°C.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VCC Supply Voltage l2.7 5.5 V

ICC Supply Current

Conversion

Nap

Sleep

LTC2473 (Note 8)

LTC2471 (Note 8)

(Note 8)

3.5

2.5

800

0.2

1500

µA

The l denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at TA = 25°C.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN+Positive Input Voltage Range LTC2473 l0 VREF V

VIN–Negative Input Voltage Range LTC2473 l0 VREF V

VIN Input Voltage Range LTC2471 l0 VREF V

VOR+, VUR+Overrange/Underrange Voltage, IN+VIN– = 0.625V 8 LSB

VOR–, VUR–Overrange/Underrange Voltage, IN– VIN+ = 0.625V 8 LSB

CIN IN+, IN–, IN Sampling Capacitance 0.35 pF

IDC_LEAK(IN+, IN–, IN) IN+, IN– DC Leakage Current (LTC2473)

IN DC Leakage Current (LTC2471)

VIN = GND (Note 8)

VIN = VCC (Note 8)

–10

±1

ICONV Input Sampling Current (Notes 5, 8) 50 nA

VREF Reference Output Voltage l1.247 1.25 1.253 V

Reference Voltage Coefﬁcient (Note 9)

C-Grade

I-Grade

±2

±5

±10

ppm/°C

Reference Line Regulation 2.7V ≤ VCC ≤ 5.5V –90 dB

Reference Short-Circuit Current VCC = 5.5, Forcing Output to GND (Note 8) l35 mA

COMP Pin Short-Circuit Current VCC = 5.5, Forcing Output to GND (Note 8) l200 µA

Reference Load Regulation 2.7V ≤ VCC ≤ 5.5V, IOUT = 100μA Sourcing 3.5 mV/mA

Reference Output Noise Density CCOMP= 0.1μF, CREFOUT = 0.1μF, At f =

1ksps

30 nV/√Hz

power requireMenTs

LTC2471/LTC2473

24713fb

For more information www.linear.com/LTC2471

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. (Notes 2, 7)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

tCONV1 Conversion Time SPD = 0 l4 4.8 ms

tCONV2 Conversion Time SPD = 1 l1 1.2 ms

fSCL SCL Clock Frequency l0 400 kHz

tHD(SDA,STA) Hold Time (Repeated) START Condition l0.6 µs

tLOW LOW Period of the SCL Pin l1.3 µs

tHIGH HIGH Period of the SCL Pin l0.6 µs

tSU(STA) Set-Up Time for a Repeated START

Condition

l0.6 µs

tHD(DAT) Data Hold Time l0 0.9 µs

tSU(DAT) Data Set-Up Time l100 ns

trRise Time for SDA, SCL Signals (Note 6) l20 + 0.1CB300 ns

tfFall Time for SDA, SCL Signals (Note 6) l20 + 0.1CB300 ns

tSU(STO) Set-Up Time for STOP Condition l0.6 µs

tBUF Bus Free Time Between a STOP and

START Condition

l1.3 µs

tOF Output Fall Time VIHMIN to VILMAX Bus Load CB = 10pF to 400pF (Note 6) l20 + 0.1CB250 ns

tSP Input Spike Suppression l50 ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2. All voltage values are with respect to GND. VCC = 2.7V to 5.5V

unless otherwise speciﬁed.

VREFCM = VREF/2, FS = VREF, –VREF ≤ VIN ≤ VREF

VIN = VIN+ – VIN–, VINCM = (VIN+ + VIN–)/2. (LTC2473)

Note 3. Guaranteed by design, not subject to test.

Note 4. Integral nonlinearity is deﬁned as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

Note 5: Input sampling current is the average input current drawn from

the input sampling network while the LTC2471/LTC2473 are converting.

Note 6: CB = capacitance of one bus line in pF.

Note 7: All values refer to VIH(MIN) and VIL(MAX) levels.

Note 8: A positive current is ﬂowing into the DUT pin.

Note 9: Voltage temperature coefﬁcient is calculated by dividing the

maximum change in output voltage by the speciﬁed temperature range.

i2c TiMing characTerisTics

The l denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at TA = 25°C. (Notes 2, 7)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIH High Level Input Voltage l0.7VCC V

VIL Low Level Input Voltage l0.3VCC V

IIDigital Input Current (Note 8) l–10 10 µA

VHYS Hysteresis of Schmidt Trigger Inputs (Note 3) l0.05VCC V

VOL Low Level Output Voltage (SDA) I = 3mA l0.4 V

IIN Input Leakage 0.1VCC ≤ VIN ≤ 0.9VCC l1 µA

CICapacitance for Each I/O Pin l10 pF

CBCapacitance Load for Each Bus Line l400 pF

VIH(A0) High Level Input Voltage for Address Pin l0.95VCC V

VIL(A0) Low Level Input Voltage for Address Pin l0.05VCC V

i2c inpuTs anD ouTpuTs

LTC2471/LTC2473

24713fb

For more information www.linear.com/LTC2471

Typical perForMance characTerisTics

Offset Error vs Temperature ADC Gain Error vs Temperature Transition Noise vs Temperature

Conversion Mode Power Supply

Current vs Temperature

Sleep Mode Power Supply

Current vs Temperature VREF vs Temperature

(TA = 25°C, unless otherwise noted)

TEMPERATURE (°C)

OFFSET ERROR (LSB)

24713 G04

VCC = 5.5V

VCC = 4.1V

VCC = 2.7V

–50 –10 10–30 50 70

30 90

TEMPERATURE (°C)

–50

ADC GAIN ERROR (LSB)

24713 G05

–10

–30 30 50 7010–10 90

VCC = 5.5V

VCC = 4.1V

VCC = 2.7V

TEMPERATURE (°C)

TRANSITION NOISE RMS (µV)

24713 G06

–50 –10 10–30 50 70

30 90

VCC = 5.5V

VCC = 2.7V

–50 –10 10–30 50 70

30 90

VCC = 5.5V

VCC = 2.7V

TEMPERATURE (°C)

CONVERSION CURRENT (mA)

4.0

3.9

24713 G07

3.4

3.5

3.6

3.7

3.8

3.3

3.2

3.1

3.0

VCC = 4.1V

–50 –10 10–30 50 70

30 90

VCC = 5.5V

TEMPERATURE (°C)

SLEEP CURRENT (nA)

350

24713 G08

150

300

250

200

100

VCC = 2.7V

VCC = 4.1V

–50 –10 10–30 50 70

30 90

TEMPERATURE (°C)

REFERENCE OUTPUT VOLTAGE (V)

1.2508

24713 G09

1.2502

1.2503

1.2504

1.2505

1.2506

1.2507

Integral Nonlinearity Integral Nonlinearity Maximum INL vs Temperature

DIFFERENTIAL INPUT VOLTAGE (V)

–1.25 –0.75 –0.25

INL (LSB)

24713 G02

–1

–2

–3 0.25 0.75 1.25

VCC = 5.5V

TA = –45°C, 25°C, 90°C

OUTPUT RATE = 208sps

TEMPERATURE (°C)

INL (LSB)

24713 G03

–2

–4

–6

–50 –30 10 30 50 70

–10 90

VCC = 5.5V

VCC = 4.1V

VCC = 2.7V

OUTPUT RATE = 208sps

DIFFERENTIAL INPUT VOLTAGE (V)

–1.25 –0.75 –0.25

INL (LSB)

24713 G01

–1

–2

–3 0.25 0.75 1.25

VCC = 2.7V

TA = –45°C, 25°C, 90°C

OUTPUT RATE = 208sps

LTC2471/LTC2473

24713fb

For more information www.linear.com/LTC2471

pin FuncTions

REFOUT (Pin 1): Reference Output Pin. Nominally 1.25V,

this voltage sets the full-scale input range of the ADC. For

noise and reference stability connect to a 0.1µF capacitor

tied to GND. This capacitor value must be less than or

equal to the capacitor tied to the reference compensa-

tion pin (COMP). REFOUT must not be overdriven by an

external reference.

COMP (Pin 2): Internal Reference Compensation Pin. For

low noise and reference stability, tie a 0.1μF capacitor to

GND.

A0 (Pin 3): Chip Address Control Pin. The A0 pin can be

tied to GND or VCC. If A0 is tied to GND, the LTC2471/

LTC2473 I2C address is 0010100. If A0 is tied to VCC, the

LTC2471/LTC2473 I2C address is 1010100.

GND (Pins 4, 7, 11, (Exposed Pad Pin 13 – DFN Package

Only)): Ground. Connect exposed pad directly to the ground

plane through a low impedance connection.

SCL (Pin 5): Serial Clock Input of the I2C Interface. The

LTC2471/LTC2473 can only act as an I2C slave and the SCL

pin only accepts an external serial clock. Data is shifted

into the SDA pin on the rising edges of SCL and output

through the SDA pin on the falling edges of SCL.

SDA (Pin 6): Bidirectional Serial Data Line of the I2C Inter-

face. The conversion result is output through the SDA pin.

The pin is high impedance unless the LTC2471/LTC2473

is in the data output mode. While the LTC2471/LTC2473 is

in the data output mode, SDA is an open drain pull down

(which requires an external 1.7k pull-up resistor to VCC).

REF– (Pin 8): Negative Reference Input to the ADC. The

voltage on this pin sets the zero input to the ADC. This

pin should tie directly to ground or the ground sense of

the input sensor.

IN+ (LTC2473), IN (LTC2471) (Pin 9): Positive input volt-

age for the LTC2473 differential device. ADC input for the

LTC2471 single-ended device.

IN– (LTC2473), GND (LTC2471) (Pin 10): Negative input

voltage for the LTC2473 differential device. GND for the

LTC2471 single-ended device.

VCC (Pin 12): Positive Supply Voltage. Bypass to GND with

a 10μF capacitor in parallel with a low-series-inductance

0.1μF capacitor located as close to pin 12 as possible.

Typical perForMance characTerisTics

(TA = 25°C, unless otherwise noted)

Power Supply Rejection

vs Frequency Applied to VCC Conversion Time vs Temperature

10 100 1k1 100k 1M

10k 10M

FREQUENCY AT VCC (Hz)

REJECTION (dB)

24713 G010

–120

–100

–80

–60

–40

–20

TA = 25°C

TEMPERATURE (°C)

–50

CONVERSION TIME (ms)

24713 G11

4.4

4.0

4.1

4.2

4.3

3.9

3.8 –25 25 50 75

0100

VCC = 2.7V

VCC = 4.1V

VCC = 5.5V

VREF vs VCC

2.0 3.52.5 4.03.0 5.0 5.54.5 6.0

VCC (V)

REF

(V)

1.250345

1.250340

24713 G12

1.250305

1.250310

1.250315

1.250320

1.250325

1.250330

1.250335

TA = 25°C

LTC2471/LTC2473

24713fb

For more information www.linear.com/LTC2471

applicaTions inForMaTion

CONVERTER OPERATION

Converter Operation Cycle

The LTC2471/LTC2473 are low power, delta sigma, analog

to digital converters with a simple I2C interface and a user

selected 208sps/833sps output rate (see Figure 1). The

LTC2473 has a fully differential input while the LTC2471 is

single-ended. Both are pin and software compatible. Their

operation is composed of three distinct states: CONVERT,

SLEEP/NAP, and DATA INPUT/OUTPUT. The operation

begins with the CONVERT state (see Figure 2). Once the

conversion is ﬁnished, the converter automatically pow-

ers down (NAP) or under user control, both the converter

and reference are powered down (SLEEP). The conversion

result is held in a static register while the device is in this

state. The cycle concludes with the DATA INPUT/OUTPUT

state. Once all 16-bits are read or an abort is initiated, the

device begins a new conversion.

The CONVERT state duration is determined by the LTC2471/

LTC2473 conversion time (nominally 4.8ms or 1.2ms

depending on the selected output rate). Once started,

this operation can not be aborted except by a low power

supply condition (VCC < 2.1V) which generates an internal

power-on reset signal.

Figure 2. LTC2471/LTC2473 State Transition Diagram

DATA INPUT/OUTPUT

SLEEP/NAP

CONVERT

POWER-ON RESET

YES

24713 F02

STOP

READ 16 BITS

READ/WRITE

ACKNOWLEDGE

NO YES

block DiagraM

Figure 1. Functional Block Diagram

ΔΣ A/D

CONVERTER

DECIMATING

SINC FILTER

SDA

REFOUT COMP

REF–

IN+

(IN)

IN–

(GND)

SCL

24713 BD

–

ΔΣ A/D

CONVERTER

INTERNAL

REFERENCE

( ) PARENTHESIS INDICATE LTC2471

SPI

INTERFACE

INTERNAL

OSCILLATOR

1VCC

122

8GND4, 7, 11, 13 DD PACKAGE

4, 7, 11 MS PACKAGE

LTC2471/LTC2473

24713fb

For more information www.linear.com/LTC2471

applicaTions inForMaTion

After the completion of a conversion, the LTC2471/LTC2473

enters the SLEEP/NAP state and remains there until a valid

read/write is acknowledged. Following this condition, the

ADC transitions into the DATA INPUT/OUTPUT state.

While in the SLEEP/NAP state, the LTC2471/LTC2473’s

converters are powered down. This reduces the supply

current by approximately 70%. While in the NAP state

the reference remains powered up. The user can power

down both the reference and the converter by enabling

the sleep mode during the DATA INPUT/OUTPUT state.

Once the next conversion is complete with the sleep

mode enabled, the SLEEP state is entered and power is

reduced to 2μA (maximum). The reference is powered up

once a valid read/write is acknowledged. The reference

startup time is 12ms (if the reference and compensation

capacitor values are both 0.1μF). As the reference and

compensation capacitors are decreased, the startup time

is reduced (see Figure 3), but the transition noise increases

(see Figure 4).

Power-Up Sequence

When the power supply voltage (VCC) applied to the con-

verter is below approximately 2.1V, the ADC performs a

power-on reset. This feature guarantees the integrity of

the conversion result.

When VCC rises above this critical threshold, the converter

generates an internal power-on reset (POR) signal for ap-

proximately 0.5ms. For proper operation VDD needs to be

restored to normal operating range (2.7V to 5.5V) before

the conclusion of the POR cycle. The POR signal clears all

internal registers. Following the POR signal, the LTC2471/

LTC2473 start a conversion cycle and follow the succes-

sion of states shown in Figure 2. The reference startup

time following a POR is 12ms (CCOMP = CREFOUT = 0.1μF).

The ﬁrst conversion following power-up will be invalid

if the reference voltage has not completely settled (see

Figure 3). The ﬁrst conversion following power up can be

discarded using the data abort command or simply read

and ignored. Depending on the value chosen for CCOMP

and CREFOUT, the reference startup can take more than

one conversion period, see Figure 3. If the startup time is

less than 1.2ms (833sps output rate) or 4.8ms (208sps

output rate) then conversions following the ﬁrst period

are accurate to the device speciﬁcations. If the startup

time exceeds 1.2ms or 4.8ms then the user can wait the

appropriate time or use the ﬁxed conversion period as

a startup timer by ignoring results within the unsettled

period. Once the reference has settled, all subsequent

conversion results are valid. If the user places the device

into the sleep mode (SLP = 1, reference powered down)

the reference will require a startup time proportional to

the value of CCOMP and CREFOUT (see Figure 3).

Figure 4. Transition Noise RMS vs COMP and

Reference Capacitance

Figure 3. Reference Start-Up Time vs VREF and

Compensation Capacitance

CAPACITANCE (µF)

TIME (ms)

150

250

24713 F03

–50

100

200

0.1 0.01 0.001

VCC = 5.5V

VCC = 4.1V

VCC = 2.7V

0.001 0.01 0.10.0001 10

CAPACITANCE (µF)

TRANSITION NOISE (µV RMS)

24713 F04

LTC2471/LTC2473

24713fb

For more information www.linear.com/LTC2471

Ease of Use

The LTC2471/LTC2473 data output has no latency, ﬁlter

settling delay, or redundant results associated with the

conversion cycle. There is a one-to-one correspondence

between the conversion and the output data. Therefore,

multiplexing multiple analog input voltages requires no

special actions.

The LTC2471/LTC2473 include a proprietary input sampling

scheme that reduces the average input current by several

orders of magnitude when compared to traditional delta-

sigma architectures. This allows external ﬁlter networks

to interface directly to the LTC2471/LTC2473. Since the

average input sampling current is 50nA, an external RC

lowpass ﬁlter using 1kΩ and 0.1µF results in <1LSB

additional error. Additionally, there is negligible leakage

current between IN+ and IN– (for the LTC2473).

Input Voltage Range (LTC2471)

Ignoring offset and full-scale errors, the LTC2471 will

theoretically output an “all zero” digital result when the

input is at ground (a zero scale input) and an “all one”

digital result when the input is at VREF or higher (VREFOUT

= 1.25V). In an underrange condition (for all input voltages

below zero scale) the converter will generate the output

code 0. In an overrange condition (for all input voltages

greater than VREF) the converter will generate the output

code 65535.

Input Voltage Range (LTC2473)

As detailed in the Output Data Format section, the output

code is given as INT(32767.5 • (VIN+ – VIN–)/VREF + 32767.5.

For (VIN+ – VIN–) ≥ VREF, the output code is clamped at

65535 (all ones). For (VIN+ – VIN–) ≤ –VREF, the output

code is clamped at 0 (all zeroes).

applicaTions inForMaTion

I2C INTERFACE

The LTC2471/LTC2473 communicate through an I2C in-

terface. The I2C interface is a 2-wire open-drain interface

supporting multiple devices and masters on a single bus.

The connected devices can only pull the data line (SDA)

LOW and can never drive it HIGH. SDA must be externally

connected to the supply through a pull-up resistor. When

the data line is free, it is HIGH. Data on the I2C bus can

be transferred at rates up to 100kbits/s in the standard

mode and up to 400kbits/s in the fast mode.

Upon entering the DATA INPUT/OUTPUT state,

SDA

outputs the sign (D15) of the conversion result. During

this state, the ADC shifts the conversion result serially

through the

SDA

output pin under the control of the SCL

input pin. There is no latency in generating this data and

the result corresponds to the last completed conversion.

A new bit of data appears at the

SDA

pin following each

falling edge detected at the SCL input pin and appears

from MSB to LSB. The user can reliably latch this data on

every rising edge of the external serial clock signal driving

the SCL pin.

Each device on the I2C bus is recognized by a unique

address stored in that device and can operate either as

a transmitter or receiver, depending on the function of

the device. In addition to transmitters and receivers,

devices can also be considered as masters or slaves when

performing data transfers. A master is the device which

initiates a data transfer on the bus and generates the

clock signals to permit that transfer. Devices addressed

by the master are considered a slave. The address of the

LTC2471/LTC2473 is 0010100 (if A0 is tied to GND) or

1010100 (if A0 is tied to VCC).

LTC2471/LTC2473

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Figure 5. Deﬁnition of Timing for Fast/Standard Mode Devices on the I2C Bus

The LTC2471/LTC2473 can only be addressed as a slave.

It can only transmit the last conversion result. The serial

clock line, SCL, is always an input to the LTC2471/LTC2473

and the serial data line SDA is bidirectional. Figure 5 shows

the deﬁnition of the I2C timing.

The START and STOP Conditions

A START (S) condition is generated by transitioning SDA

from HIGH to LOW while SCL is HIGH. The bus is consid-

ered to be busy after the START condition. When the data

transfer is ﬁnished, a STOP (P) condition is generated by

transitioning SDA from LOW to HIGH while SCL is HIGH.

The bus is free after a STOP is generated. START and STOP

conditions are always generated by the master.

When the bus is in use, it stays busy if a repeated START

(Sr) is generated instead of a STOP condition. The repeated

START timing is functionally identical to the START and

is used for reading from the device before the initiation

of a new conversion.

Data Transferring

After the START condition, the I2C bus is busy and data

transfer can begin between the master and the addressed

slave. Data is transferred over the bus in groups of nine

bits, one byte followed by one acknowledge (ACK) bit. The

master releases the SDA line during the ninth SCL clock

cycle. The slave device can issue an ACK by pulling SDA

LOW or issue a Not Acknowledge (NACK) by leaving the

SDA line HIGH impedance (the external pull-up resistor

will hold the line HIGH). Change of data only occurs while

the clock line (SCL) is LOW.

Output Data Format

After a START condition, the master sends a 7-bit address

followed by a read request (R) bit. The bit R is 1 for a

Read Request. If the 7-bit address matches the LTC2471/

LTC2473’s address (0010100 or 1010100, depending on

the state of the pin A0) the ADC is selected. When the

device is addressed during the conversion state, it does

SDA

SCL

S Sr P S

tHD(STA) tHD(DAT)

tSU(STA) tSU(STO)

tSU(DAT)

tLOW tHD(SDA) tSP tBUF

trtftr

tHIGH

24713 F05

LTC2471/LTC2473

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Figure 6. Read Sequence Timing Diagram

not accept the request and issues a NACK by leaving the

SDA line HIGH. If the conversion is complete, the LTC2471/

LTC2473 issue an ACK by pulling the SDA line LOW.

Following the ACK, the LTC2471/LTC2473 can output data.

The data output stream is 16 bits long and is shifted out

on the falling edges of SCL (see Figure 6).

The DATA INPUT/OUTPUT state is concluded once all 16

data bits have been read or after a STOP condition.

1 7 8 9 2 31 8

D8D13D14

MSB

D15RSDA

SCL

7-BIT

ADDRESS

START BY

MASTER

D7 D6 D5 D0

LSB

9 1 2 3 8 9

ACK BY

MASTER

NACK BY

MASTER

SLEEP DATA OUTPUT CONVERSION

24713 F06

ACK BY

LTC2471/LTC2473

Table 1. LTC2471/LTC2473 Output Data Format

SINGLE ENDED INPUT VIN

(LTC2471)

DIFFERENTIAL INPUT VOLTAGE

VIN+ – VIN– (LTC2473)

D15

(MSB)

D14 D13 D12...D2 D1 D0

(LSB)

CORRESPONDING

DECIMAL VALUE

≥VREF ≥VREF 1 1 1 1 1 1 65535

VREF – 1LSB VREF – 1LSB 1 1 1 1 1 0 65534

0.75 • VREF 0.5 • VREF 1 1 0 0 0 0 49152

0.75 • VREF – 1LSB 0.5 • VREF – 1LSB 1 0 1 1 1 1 49151

0.5 • VREF 0 1 0 0 0 0 0 32768

0.5 • VREF – 1LSB –1LSB 0 1 1 1 1 1 32767

0.25 • VREF –0.5 • VREF 0 1 0 0 0 0 16384

0.25 • VREF – 1LSB –0.5 • VREF – 1LSB 0 0 1 1 1 1 16383

0 ≤ –VREF 0 0 0 0 0 0 0

The LTC2473 (differential input) output code is given by

INT(32767.5 • (VIN+ – VIN–)/VREF + 32767.5. The ﬁrst bit

output by the LTC2473, D15, is the MSB, which is 1 for

VIN+ ≥ VIN– and 0 for VIN+ < VIN–. This bit is followed by

successively less signiﬁcant bits (D14, D13, …) until the

LSB is output by the LTC2473, see Table 1.

The LTC2471 (single-ended input) output code is a direct

binary encoded result, see Table 1.

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Figure 7. Timing Diagram for Writing to the LTC2471/LTC2473

Data Input Format

After a START condition, the master sends a 7-bit ad-

dress followed by a read/write request (R/W) bit. The

R/W bit is 0 for a write. The data input word is 4 bits long

and consists of two enable bits (EN1 and EN2) and two

programming bits (SPD and SLP), see Figure 7. EN1 is

applied to the ﬁrst rising edge of SCL after a valid write

address is acknowledged. Programming is enabled by

setting EN1 = 1 and EN2 = 0.

The speed bit (SPD) determines the output rate, SPD = 0

(default) for a 208sps and SPD = 1 for a 833sps output

rate. The sleep bit (SLP) is used to power down the

on-chip reference. In the default mode, the reference re-

mains powered up at the conclusion of each conversion

cycle while the ADC is automatically powered down at the

end of each conversion cycle. If the SLP bit is set HIGH,

the reference and the ADC are powered down once the next

conversion cycle is completed. The reference and ADC are

powered up again once a valid read/write is acknowledged.

The following conversion is invalid if the next conversion

is started before the reference has started up (see Figure 3

for reference startup times as a function of compensation

capacitor and reference capacitor).

The sleep bit (SLP) is used to power down the on chip

reference. In the default mode, the reference remains

powered up even when the ADC is powered down. If the

SLP bit is set HIGH, the reference will power down after

the next conversion is complete. It will remain powered

down until a valid address is acknowledged. The reference

startup time is approximately 12ms. In order to ensure a

stable reference for the following conversions, either the

data input/output time should be delayed 12ms after an

address acknowledge or the ﬁrst conversion following a

reference start up should be discarded.

Table 2. Input Data Format

BIT NAME FUNCTION

EN1 Should Be High (EN1 = 1) in Order to Enable Program Mode

EN2 Should Be Low (EN2 = 0) in Order to Enable Program Mode

SPD Low (SPD = 0, Default) for 208sps, High (SPD = 1) for

833sps Output Rate

SLP Low (SLP = 0, Default) for Nap Mode, High (SLP = 1)

for Sleep Mode Where Both Reference and Converter Are

Powered Down

SDA

SCL

EN1 EN2 SPD SLP

SLEEP

START BY

MASTER

DATA INPUT

7 8 9 1 2 3 4 5 6 7 8 9

1 2 …

7-BIT ADDRESS

ACK BY

LTC2471/LTC2473

ACK BY

LTC2471/LTC2473

24713 F07

LTC2471/LTC2473

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Figure 10. Start a New Conversion without Reading Old Conversion Result

Figure 8. Consecutive Reading

Figure 9. I2C State Diagram

SLEEP SLEEP

S PR ACK READ READ

DATA OUTPUT

CONVERSION CONVERSION

24713 F08

S R PACK

CONVERSIONDATA OUTPUT

7-BIT ADDRESS

(0010100 OR 1010100)

7-BIT ADDRESS

(0010100 OR 1010100)

24713 F09

7-BIT ADDRESS:

0010100 OR 1010100

WRITE INPUT

CONFIGURATION

(FIGURE 7)

FOR CYCLE N

I2C START R/W

BIT LOW

WRITE INPUT

CONFIGURATION

(FIGURE 7)

I2C STOP CONVERT

CONVERSION

FINISHED

ACK

NAK

I2C (REPEAT) START R/W

BIT LOW

7-BIT ADDRESS:

0010100 OR 1010100 I2C START

R/W

BIT HIGH

READ DATA FROM

CYCLE N-1 I2C STOP CONVERT

CONVERSION

FINISHED

7-BIT ADDRESS:

0010100 OR 1010100

SLEEP

S PR ACK READ (OPTIONAL)

DATA OUTPUT CONVERSIONCONVERSION

24713 F10

7-BIT ADDRESS

(0010100 OR 1010100)

OPERATION SEQUENCE

Continuous Read

Conversions from the LTC2471/LTC2473 can be continu-

ously read, see Figure 8. The R/W is 1 for a read. At the

end of a read operation, a new conversion automatically

begins. At the conclusion of the conversion cycle, the next

result may be read using the method described above. If

the conversion cycle is not complete and a valid address

selects the device, the LTC2471/LTC2473 generate a NACK

signal indicating the conversion cycle is in progress. See

Figure 9 for an example state diagram.

Discarding a Conversion Result and Initiating a New

Conversion

It is possible to start a new conversion without reading

the old result, as shown in Figure 10. Following a valid

7-bit address, a read request (R/W) bit, and a valid ACK,

a STOP command will start a new conversion.

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PRESERVING THE CONVERTER ACCURACY

The LTC2471/LTC2473 are designed to minimize the conver-

sion result’s sensitivity to device decoupling, PCB layout,

anti-aliasing circuits, line and frequency perturbations.

Nevertheless, in order to preserve the high accuracy capa-

bility of this part, some simple precautions are desirable.

Digital Signal Levels

Due to the nature of CMOS logic, it is advisable to keep input

digital signals near GND or VCC. Voltages in the range of

0.5V to VCC – 0.5V may result in additional current leakage

from the part. Undershoot and overshoot should also be

minimized, particularly while the chip is converting. It is

thus beneﬁcial to keep edge rates of about 10ns and limit

overshoot and undershoot to less than 0.3V.

Driving VCC and GND

In relation to the VCC and GND pins, the LTC2471/LTC2473

combines internal high frequency decoupling with damping

elements, which reduce the ADC performance sensitivity

to PCB layout and external components. Nevertheless,

the very high accuracy of this converter is best pre-

served by careful low and high frequency power supply

decoupling.

A 0.1µF, high quality, ceramic capacitor in parallel with

a 10µF low ESR ceramic capacitor should be connected

between the VCC and GND pins, as close as possible to the

package. The 0.1µF capacitor should be placed closest to

the ADC package. It is also desirable to avoid any via in the

circuit path, starting from the converter VCC pin, passing

through these two decoupling capacitors, and returning

to the converter GND pin. The area encompassed by this

circuit path, as well as the path length, should be minimized.

As shown in Figure 11, REF– is used as the negative

reference voltage input to the ADC. This pin can be tied

directly to ground or Kelvin sensed to sensor ground. In

the case where REF– is used as a sense input, it should

be bypassed to ground with a 0.1μF ceramic capacitor in

parallel with a 10μF low ESR ceramic capacitor.

Very low impedance ground and power planes, and star

connections at both VCC and GND pins, are preferable. The

VCC pin should have two distinct connections: the ﬁrst to

the decoupling capacitors described above, and the second

to the ground return for the power supply voltage source.

REFOUT and COMP

The on chip 1.25V reference is internally tied to the con-

verter’s reference input and is output to the REFOUT pin.

A 0.1μF capacitor should be placed on the REFOUT pin.

It is possible to reduce this capacitor, but the transition

noise increases (see Figure 4). A 0.1μF capacitor should

also be placed on the COMP pin. This pin is tied to an

internal point in the reference and is used for stability.

In order for the reference to remain stable, the capacitor

placed on the COMP pin must be greater than or equal

to the capacitor tied to the REFOUT pin. The REFOUT pin

cannot be overridden by an external voltage.

Depending on the size of the capacitors tied to the REFOUT

and COMP pins, the internal reference has a corresponding

start up time. This start up time is typically 12ms when

0.1μF capacitors are used. The ﬁrst conversion following

power up can be discarded using the data abort com-

Figure 11. LTC2471/LTC2473 Analog Input/Reference

Equivalent Circuit

RSW

15k

(TYP)

ILEAK

VCC

CEQ

0.35pF

(TYP)

IN+

(LTC2473)

IN–

(LTC2473)

(LTC2471)

REF–

REFOUT

INTERNAL

REFERENCE

24713 F11

RSW

15k

(TYP)

ILEAK

RSW

15k

(TYP)

ILEAK

RSW

15k

(TYP)

ILEAK

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mand or simply read and ignored. Depending on the value

chosen for CCOMP and CREFOUT, the reference startup can

take more than one conversion period, see Figure 3. If the

startup time is less than 1.2ms (833sps output rate) or

4.8ms (208sps output rate) then conversions following

the ﬁrst period are accurate to the device speciﬁcations.

If the startup time exceeds 1.2ms or 4.8ms then the user

can wait the appropriate time or use the ﬁxed conversion

period as a startup timer by ignoring results within the

unsettled period. Once the reference has settled all sub-

sequent conversion results are valid. If the user places the

device into the sleep mode (SLP = 1, reference powered

down) the reference will require a startup time proportional

to the value of CCOMP and CREFOUT, see Figure 3.

If the reference is put to sleep (program SLP = 1 and CS =

1) the reference is powered down after the next conversion.

This last conversion result is valid. On CS falling edge,

the reference is powered back up. In order to ensure the

reference output has settled before the next conversion,

the power up time can be extended by delaying the data

read after the falling edge of CS. Once all 16 bits are read

from the device or CS is brought HIGH, the next conver-

sion automatically begins. In the default operation, the

reference remains powered up at the conclusion of the

conversion cycle.

Driving VIN+ and VIN–

The input drive requirements can best be analyzed using

the equivalent circuit of Figure 12. The input signal VSIG is

connected to the ADC input pins (IN+ and IN–) through an

equivalent source resistance RS. This resistor includes both

the actual generator source resistance and any additional

optional resistors connected to the input pins. Optional

input capacitors CIN are also connected to the ADC input

pins. This capacitor is placed in parallel with the input

parasitic capacitance CPAR. This parasitic capacitance

includes elements from the printed circuit board (PCB)

and the associated input pin of the ADC. Depending on the

PCB layout, CPAR has typical values between 2pF and 15pF.

In addition, the equivalent circuit of Figure 12 includes the

converter equivalent internal resistor RSW and sampling

capacitor CEQ.

There are some immediate trade-offs in RS and CIN without

needing a full circuit analysis. Increasing RS and CIN can

give the following beneﬁts:

1) Due to the LTC2471/LTC2473’s input sampling algo-

rithm, the input current drawn by either IN+ or IN– over

a conversion cycle is typically 50nA. A high RS • CIN

attenuates the high frequency components of the input

current, and RS values up to 1k result in <1LSB error.

2) The bandwidth from VSIG is reduced at the input pins

(IN+, IN– or IN). This bandwidth reduction isolates the

ADC from high frequency signals, and as such provides

simple anti-aliasing and input noise reduction.

3) Switching transients generated by the ADC are attenu-

ated before they go back to the signal source.

4) A large CIN gives a better AC ground at the input pins,

helping reduce reﬂections back to the signal source.

5) Increasing RS protects the ADC by limiting the current

during an outside-the-rails fault condition.

There is a limit to how large RS • CIN should be for a given

application. Increasing RS beyond a given point increases

Figure 12. LTC2471/LTC2473 Input Drive Equivalent Circuit

ILEAK

RSW

15k

(TYP)

ICONV

CIN

IN+

(LTC2473)

(LTC2471)

SIG+

SIG–

CEQ

0.35pF

(TYP)

CPAR

–

24713 F12

ILEAK

RSW

15k

(TYP)

ICONV

CIN

IN–

(LTC2473)

VCC

CEQ

0.35pF

(TYP)

CPAR

–

LTC2471/LTC2473

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the voltage drop across RS due to the input current,

to the point that signiﬁcant measurement errors exist.

Additionally, for some applications, increasing the RS • CIN

product too much may unacceptably attenuate the signal

at frequencies of interest.

For most applications, it is desirable to implement CIN as

a high-quality 0.1µF ceramic capacitor and to set RS ≤

1k. This capacitor should be located as close as possible

to the actual IN+, IN– and IN package pins. Furthermore,

the area encompassed by this circuit path, as well as the

path length, should be minimized.

In the case of a 2-wire sensor that is not remotely

grounded, it is desirable to split RS and place series

resistors in the ADC input line as well as in the sensor

ground return line, which should be tied to the ADC GND

pin using a star connection topology.

Figure 13 shows the measured LTC2473 INL vs Input

Voltage as a function of RS value with an input capacitor

CIN = 0.1µF.

In some cases, RS can be increased above these guidelines.

The input current is zero when the ADC is either in sleep

or I/O modes. Thus, if the time constant of the input RC

circuit t = RS • CIN, is of the same order of magnitude or

longer than the time periods between actual conversions,

then one can consider the input current to be reduced

correspondingly.

These considerations need to be balanced out by the input

signal bandwidth. The 3dB bandwidth ≈ 1/(2pRSCIN).

Finally, if the recommended choice for CIN is unacceptable

for the user’s speciﬁc application, an alternate strategy is to

eliminate CIN and minimize CPAR and RS. In practical terms,

this conﬁguration corresponds to a low impedance sensor

directly connected to the ADC through minimum length

traces. Actual applications include current measurements

through low value sense resistors, temperature measure-

ments, low impedance voltage source monitoring, and so

on. The resultant INL vs VIN is shown in Figure 14. The

measurements of Figure 14 include a capacitor CPAR cor-

responding to a minimum sized layout pad and a minimum

width input trace of about 1 inch length.

Signal Bandwidth, Transition Noise and Noise

Equivalent Input Bandwidth

The LTC2471/LTC2473 include a sinc2 type digital ﬁlter. The

ﬁrst notch is located at 416Hz if the 208sps output rate is

selected and 1666Hz if the 833sps output rate is selected.

The calculated input signal attenuation vs. frequency over a

wide frequency range is shown in Figure 15. The calculated

input signal attenuation vs. frequency at low frequencies

is shown in Figure 16. The converter noise level is about

3µVRMS and can be modeled by a white noise source con-

nected at the input of a noise-free converter.

On a related note, the LTC2473 uses two separate A/D

converters to digitize the positive and negative inputs.

Each of these A/D converters has 3µVRMS transition noise.

If one of the input voltages is within this small transition

noise band, then the output will ﬂuctuate one bit, regard-

less of the value of the other input voltage. If both of the

input voltages are within their transition noise bands, the

output can ﬂuctuate 2 bits.

For a simple system noise analysis, the VIN drive circuit can

be modeled as a single-pole equivalent circuit character-

ized by a pole location fi and a noise spectral density ni.

If the converter has an unlimited bandwidth, or at least a

bandwidth substantially larger than fi, then the total noise

contribution of the external drive circuit would be:

Vn=niπ/2 • fi

Then, the total system noise level can be estimated as

the square root of the sum of (Vn2) and the square of the

LTC2471/LTC2473 noise ﬂoor.

LTC2471/LTC2473

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Figure 15. LTC2473 Input Signal Attenuation vs

Frequency (208sps Mode)

Figure 16. LTC2473 Input Signal Attenuation vs

Frequency (208sps Mode)

applicaTions inForMaTion

Figure 13. Measured INL vs Input Voltage Figure 14. Measured INL vs Input Voltage

Figure 17. LTC2473 Input Signal Attenuation vs

Frequency (833sps Mode)

Figure 18. LTC2473 Input Signal Attenuation vs

Frequency (833sps Mode)

DIFFERENTIAL INPUT VOLTAGE (V)

–1.25 –0.75 –0.25

INL (LSB)

24713 F13

–1

–3

–2

–4 0.25 0.75 1.25

CIN = 0.1µF

VCC = 5V

TA = 25°C

RS = 1k

RS = 0k

DIFFERENTIAL INPUT VOLTAGE (V)

–1.25 –0.75 –0.25

INL (LSB)

24713 F14

–2

–6

–4

0.25 0.75 1.25

CIN = 0

VCC = 5V

TA = 25°C

RS = 1k

RS = 0k

INPUT SIGNAL FREQUENCY (MHz)

INPUT SIGNAL ATTENUATION (dB)

–40

24713 F15

–60

–80

–20

–140

–120

–100

510 15

INPUT SIGNAL FREQUENCY (Hz)

INPUT SIGNAL ATTENUATIOIN (dB)

–80

–40

4000

24713 F16

–120

–100

–60

–20

–140 1000 2000 3000 5000

INPUT SIGNAL FREQUENCY (MHz)

INPUT SIGNAL ATTENUATIOIN (dB)

–80

–40

24713 F17

–120

–100

–60

–20

–140 510 15

INPUT SIGNAL FREQUENCY (kHz)

INPUT SIGNAL ATTENUATIOIN (dB)

–80

–40

24713 F18

–120

–100

–60

–20

–140 510 15

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MS Package

12-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1668 Rev A)

DD Package

12-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1725 Rev A)

package DescripTion

MSOP (MS12) 0213 REV A

0.53 ±0.152

(.021 ±.006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.22 –0.38

(.009 – .015)

TYP

0.86

(.034)

REF

0.650

(.0256)

BSC

12 11 10 9 8 7

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.254

(.010) 0° – 6° TYP

DETAIL “A”

GAUGE PLANE

5.10

(.201)

MIN

3.20 – 3.45

(.126 – .136)

0.889 ±0.127

(.035 ±.005)

RECOMMENDED SOLDER PAD LAYOUT

0.42 ±0.038

(.0165 ±.0015)

TYP

0.65

(.0256)

BSC

4.039 ±0.102

(.159 ±.004)

(NOTE 3)

0.1016 ±0.0508

(.004 ±.002)

1 2 3 4 5 6

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

0.406 ±0.076

(.016 ±.003)

REF

4.90 ±0.152

(.193 ±.006)

3.00 ±0.10

(4 SIDES)

NOTE:

1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.40 ± 0.10

BOTTOM VIEW—EXPOSED PAD

1.65 ± 0.10

0.75 ±0.05

R = 0.115

TYP

127

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DD12) DFN 0106 REV A

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.23 ± 0.05

0.25 ± 0.05

2.25 REF

2.38 ±0.05

1.65 ±0.05

2.10 ±0.05

0.70 ±0.05

3.50 ±0.05

PACKAGE

OUTLINE PIN 1 NOTCH

R = 0.20 OR

0.25 × 45°

CHAMFER

2.38 ±0.10

2.25 REF

0.45 BSC

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

LTC2471/LTC2473

24713fb

For more information www.linear.com/LTC2471

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REV DATE DESCRIPTION PAGE NUMBER

A 09/13 Clariﬁed maximum operating output rate as 208sps/833sps. Global

B 03/14 Removed “No Missing Codes” resolution. 1, 3

revision hisTory

LTC2471/LTC2473

24713fb

For more information www.linear.com/LTC2471

 LINEAR TECHNOLOGY CORPORATION 2010

LT 0314 REV B • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2471

relaTeD parTs

PART NUMBER DESCRIPTION COMMENTS

LTC1860/LTC1861 12-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP 850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages

LTC1860L/LTC1861L 12-Bit, 3V, 1-/2-Channel 150ksps SAR ADC 450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages

LTC1864/LTC1865 16-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP 850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages

LTC1864L/LTC1865L 16-bit, 3V, 1-/2-Channel 150ksps SAR ADC 450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages

LTC2360 12-Bit, 100ksps SAR ADC 3V Supply, 1.5mW at 100ksps, TSOT 6-Pin/8-Pin Packages

LTC2440 24-Bit No Latency ∆∑™

ADC 200nVRMS Noise, 4kHz Output Rate, 15ppm INL

LTC2480 16-Bit, Differential Input, No Latency ∆∑ ADC, with PGA,

Temp. Sensor, SPI

Easy Drive™ Input Current Cancellation, 600nVRMS Noise,

Tiny 10-Lead DFN Package

LTC2481 16-Bit, Differential Input, No Latency ∆∑ ADC, with PGA,

Temp. Sensor, I2C

Easy Drive Input Current Cancellation, 600nVRMS Noise,

Tiny 10-Lead DFN Package

LTC2482 16-Bit, Differential Input, No Latency ∆∑ ADC, SPI Easy Drive Input Current Cancellation, 600nVRMS Noise,

Tiny 10-Lead DFN Package

LTC2483 16-Bit, Differential Input, No Latency ∆∑ ADC, I2C Easy Drive Input Current Cancellation, 600nVRMS Noise,

Tiny 10-Lead DFN Package

LTC2484 24-Bit, Differential Input, No Latency ∆∑ ADC, SPI with

Temp. Sensor

Easy Drive Input Current Cancellation, 600nVRMS Noise,

Tiny 10-Lead DFN Package

LTC2485 24-Bit, Differential Input, No Latency ∆∑ ADC, I2C with

Temp. Sensor

Easy Drive Input Current Cancellation, 600nVRMS Noise,

Tiny 10-Lead DFN Package

LTC6241 Dual, 18MHz, Low Noise, Rail-to-Rail Op Amp 550nVP-P Noise, 125µV Offset Max

LTC2450 Easy-to-Use, Ultra-Tiny 16-Bit ADC, SPI, 0V to 5.5V

Input Range 2 LSB INL, 50nA Sleep Current, Tiny 2mm × 2mm DFN-6 Package,

30Hz Output Rate

LTC2450-1 Easy-to-Use, Ultra-Tiny 16-Bit ADC, SPI, 0V to 5.5V

Input Range 2 LSB INL, 50nA Sleep Current, Tiny 2mm × 2mm DFN-6 Package,

60Hz Output Rate

LTC2451 Easy-to-Use, Ultra-Tiny 16-Bit ADC, I2C, 0V to 5.5V

Input Range 2 LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT

Package, Programmable 30Hz/60Hz Output Rates

LTC2452 Easy-to-Use, Ultra-Tiny 16-Bit Differential ADC, SPI,

±5.5V Input Range 2 LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT

Package

LTC2453 Easy-to-Use, Ultra-Tiny 16-Bit Differential ADC, I2C,

±5.5V Input Range 2 LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT

Package

LTC2460 Ultra-Tiny 16-Bit ∆∑ ADC with 10ppm Reference Pin and Software Compatible with LTC2471, 60Hz Output Rate

LTC2462 Ultra-Tiny 16-Bit ∆∑ ADC with 10ppm Reference Pin and Software Compatible with LTC2473, 60Hz Output Rate

0.1µF

VCC

IN+

IN–

24713 TA02

10µF

0.1µF

7, 11, 48

121

0.1µF

1k 1.7k

5SCK/SCL

MOSI/SDA

MISO/SDO

GND

1µF

VCC

µC

VCC

IN+

REFOUT

REF–

VCC

GND

COMP

IN–

LTC2473

SCL

SDA 3

0.1µF

1.7k

VCC

Typical applicaTion