LMP7707, LMP7708, LMP7709
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SNOSAW5B –JUNE 2007–REVISED MARCH 2013
LMP7707/LMP7708/LMP7709 Precision, CMOS Input, RRIO, Wide Supply Range
Decompensated Amplifiers
Check for Samples: LMP7707,LMP7708,LMP7709
1FEATURES DESCRIPTION
The LMP7707/LMP7708/LMP7709 devices are
23• Unless Otherwise Noted, Typical Values at single, dual, and quad low offset voltage, rail-to-rail
VS= 5V. input and output precision amplifiers which each have
• Input Offset Voltage (LMP7707) ±200 µV (Max) a CMOS input stage and a wide supply voltage
• Input Offset Voltage (LMP7708/LMP7709) range. The LMP7707/LMP7708/LMP7709 are part of
the LMP™ precision amplifier family and are ideal for
±220 µV (Max) sensor interface and other instrumentation
• Input Bias Current ±200 fA applications. These decompensated amplifiers are
• Input Voltage Noise 9 nV/√Hz stable at a gain of 6 and higher.
• CMRR 130 dB The ensured low offset voltage of less than ±200 µV
• Open Loop Gain 130 dB along with the ensured low input bias current of less
than ±1 pA make the LMP7707/LMP7708/LMP7709
• Temperature Range −40°C to 125°C ideal for precision applications. The
• Gain Bandwidth Product (AV=10) 14 MHz LMP7707/LMP7708/LMP7709 are built utilizing VIP50
• Stable at a Gain of 10 or Higher technology, which allows the combination of a CMOS
• Supply Current (LMP7707) 715 µA input stage and a supply voltage range of 12V with
rail-to-rail common mode voltage capability. The
• Supply Current (LMP7708) 1.5 mA LMP7707/LMP7708/LMP7709 are the perfect choice
• Supply Current (LMP7709) 2.9 mA in many applications where conventional CMOS parts
• Supply Voltage Range 2.7V to 12V cannot operate due to the voltage conditions.
• Rail-to-Rail Input and Output The unique design of the rail-to-rail input stage of
each of the LMP7707/LMP7708/LMP7709
APPLICATIONS significantly reduces the CMRR glitch commonly
associated with rail-to-rail input amplifiers. Both sides
• High Impedance Sensor Interface of the complimentary input stage have been trimmed,
• Battery Powered Instrumentation thereby reducing the difference between the NMOS
• High Gain Amplifiers and PMOS offsets. The output swings within 40 mV
of either rail to maximize the signal dynamic range in
• DAC Buffer applications requiring low supply voltage.
• Instrumentation Amplifier The LMP7707 is offered in the space-saving 5-pin
• Active Filters SOT-23 and 8-pin SOIC packages, the LMP7708 is
offered in the 8-pin VSSOP and 8-pin SOIC
packages, and the quad LMP7709 is offered in the
14-pin TSSOP and 14-pin SOIC packages. These
small packages are ideal solutions for area
constrained PC boards and portable electronics.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2LMP is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2007–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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UNITY-GAIN STABLE OP AMP
DECOMPENSATED OP AMP
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
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Open Loop Frequency Response
Figure 1. Increased Bandwidth for Same Supply Current at AV> 10
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Human Body Model 2000V
ESD Tolerance(3) Machine Model 200V
Charge Device Model 1000V
VIN Differential ±300 mV
Supply Voltage (VS= V+– V−) 13.2V
Voltage at Input/Output Pins V++ 0.3V to V−−0.3V
Input Current 10 mA
Storage Temperature Range −65°C to +150°C
Junction Temperature(4) +150°C
Infrared or Convection (20 sec) 235°C
Soldering Information Wave Soldering Lead Temp. (10 sec) 260°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(4) The maximum power dissipation is a function of TJ(MAX),θJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
Operating Ratings(1)
Temperature Range(2) −40°C to +125°C
Supply Voltage (VS= V+– V−) 2.7V to 12V
5-Pin SOT-23 265°C/W
8-Pin SOIC 190°C/W
Package Thermal Resistance (θJA)(2) 8-Pin VSSOP 235°C/W
14-Pin TSSOP 122°C/W
14-Pin SOIC 145°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics tables.
(2) The maximum power dissipation is a function of TJ(MAX),θJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
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SNOSAW5B –JUNE 2007–REVISED MARCH 2013
3V Electrical Characteristics(1)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 3V, V−= 0V, VCM = V+/2, and RL> 10 kΩto V+/2.
Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min(2) Typ(3) Max(2) Units
VOS ±37 ±200
LMP7707 ±500
Input Offset Voltage μV
±56 ±220
LMP7708/LMP7709 ±520
TCVOS Input Offset Voltage Drift(4) ±1 ±5 μV/°C
IB±0.2 ±1
Input Bias Current(4)(5) −40°C ≤TA≤85°C ±50 pA
−40°C ≤TA≤125°C ±400
IOS Input Offset Current 40 fA
CMRR 0V ≤VCM ≤3V 86 130
LMP7707 80
Common Mode Rejection Ratio dB
0V ≤VCM ≤3V 84 130
LMP7708/LMP7709 78
PSRR 86 98
Power Supply Rejection Ratio 2.7V ≤V+≤12V, VO= V+/2 dB
82
CMVR CMRR ≥80 dB −0.2 3.2
Input Common-Mode Voltage Range V
CMRR ≥77 dB −0.2 3.2
AVOL RL= 2 kΩ(LMP7707) 100 114
VO= 0.3V to 2.7V 96
RL= 2 kΩ(LMP7708/LMP7709) 100 114
Open Loop Voltage Gain dB
VO= 0.3V to 2.7V 94
RL= 10 kΩ100 124
VO= 0.2V to 2.8V 96
VORL= 2 kΩto V+/2 40 80
LMP7707 120
RL= 2 kΩto V+/2 40 80
LMP7708/LMP7709 150 mV
Output Swing High from V+
RL= 10 kΩto V+/2 30 40
LMP7707 60
RL= 10 kΩto V+/2 35 50
LMP7708/LMP7709 100
RL= 2 kΩto V+/2 40 60
LMP7707 80
RL= 2 kΩto V+/2 45 100
LMP7708/LMP7709 170
Output Swing Low mV
RL= 10 kΩto V+/2 20 40
LMP7707 50
RL= 10 kΩto V+/2 20 50
LMP7708/LMP7709 90
(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the
Statistical Quality Control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) This parameter is specified by design and/or characterization and is not tested in production.
(5) Positive current corresponds to current flowing into the device.
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3V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 3V, V−= 0V, VCM = V+/2, and RL> 10 kΩto V+/2.
Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min(2) Typ(3) Max(2) Units
IOSourcing VO= V+/2 25 42
VIN = 100 mV 15
Sinking VO= V+/2 25 42
Output Short Circuit Current(6)(7) VIN =−100 mV (LMP7707) 20 mA
Sinking VO= V+/2 25 42
VIN =−100 mV 15
(LMP7708/LMP7709)
IS0.670 1.0
LMP7707 1.2
1.4 1.8
Supply Current LMP7708 mA
2.1
2.9 3.5
LMP7709 4.5
SR Slew Rate(8) VO= 2 VPP,10% to 90% 5.1 V/μs
GBWP Gain Bandwidth Product AV= 10 13 MHz
THD+N f = 1 kHz, AV= 10, VO= 2.5V,
Total Harmonic Distortion + Noise 0.024 %
RL= 10 kΩ
enInput-Referred Voltage Noise f = 1 kHz 9 nV/√Hz
inInput-Referred Current Noise f = 100 kHz 1 fA/√Hz
(6) The maximum power dissipation is a function of TJ(MAX),θJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
(7) The short circuit test is a momentary test.
(8) The number specified is the slower of positive and negative slew rates.
5V Electrical Characteristics(1)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5V, V−= 0V, VCM = V+/2, and RL> 10 kΩto V+/2.
Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min(2) Typ(3) Max(2) Units
VOS ±37 ±200
LMP7707 ±500
Input Offset Voltage μV
±32 ±220
LMP7708/LMP7709 ±520
TCVOS Input Offset Voltage Drift(4) ±1 ±5 μV/°C
IB±0.2 ±1
Input Bias Current(4)(5) −40°C ≤TA≤85°C ±50 pA
−40°C ≤TA≤125°C ±400
IOS Input Offset Current 40 fA
CMRR 0V ≤VCM ≤5V 88 130
LMP7707 83
Common Mode Rejection Ratio dB
0V ≤VCM ≤5V 86 130
LMP7708/LMP7709 81
PSRR 2.7V ≤V+≤12V, VO= V+/2 86 100
Power Supply Rejection Ratio dB
82
(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the
Statistical Quality Control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) This parameter is specified by design and/or characterization and is not tested in production.
(5) Positive current corresponds to current flowing into the device.
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SNOSAW5B –JUNE 2007–REVISED MARCH 2013
5V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5V, V−= 0V, VCM = V+/2, and RL> 10 kΩto V+/2.
Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min(2) Typ(3) Max(2) Units
CMVR CMRR ≥80 dB −0.2 5.2
Input Common-Mode Voltage Range V
CMRR ≥78 dB −0.2 5.2
AVOL RL= 2 kΩ(LMP7707) 100 119
VO= 0.3V to 4.7V 96
RL= 2 kΩ(LMP7708/LMP7709) 100 119
Open Loop Voltage Gain dB
VO= 0.3V to 4.7V 94
RL= 10 kΩ100 130
VO= 0.2V to 4.8V 96
VORL= 2 kΩto V+/2 60 110
LMP7707 130
RL= 2 kΩto V+/2 60 120
LMP7708/LMP7709 200 mV
Output Swing High from V+
RL= 10 kΩto V+/2 40 50
LMP7707 70
RL= 10 kΩto V+/2 40 60
LMP7708/LMP7709 120
RL= 2 kΩto V+/2 50 80
LMP7707 90
RL= 2 kΩto V+/2 50 120
LMP7708/LMP7709 190
Output Swing Low mV
RL= 10 kΩto V+/2 30 40
LMP7707 50
RL= 10 kΩto V+/2 30 50
LMP7708/LMP7709 100
IOSourcing VO= V+/2 40 66
VIN = 100 mV (LMP7707) 28
Sourcing VO= V+/2 38 66
VIN = 100 mV (LMP7708/LMP7709) 25
Output Short Circuit Current(6)(7) mA
Sinking VO= V+/2 40 76
VIN =−100 mV (LMP7707) 28
Sinking VO= V+/2 40 76
VIN =−100 mV (LMP7708/LMP7709) 23
IS0.715 1.0
LMP7707 1.2
1.5 1.9
Supply Current LMP7708 mA
2.2
2.9 3.7
LMP7709 4.6
SR Slew Rate(8) VO= 4 VPP, 10% to 90% 5.6 V/μs
GBWP Gain Bandwidth Product AV= 10 14 MHz
THD+N f = 1 kHz, AV= 10, VO= 4.5V,
Total Harmonic Distortion + Noise 0.024 %
RL= 10 kΩ
enInput-Referred Voltage Noise f = 1 kHz 9 nV/√Hz
inInput-Referred Current Noise f = 100 kHz 1 fA/√Hz
(6) The maximum power dissipation is a function of TJ(MAX),θJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
(7) The short circuit test is a momentary test.
(8) The number specified is the slower of positive and negative slew rates.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
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±5V Electrical Characteristics(1)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5V, V−=−5V, VCM = 0V, and RL> 10 kΩto 0V.
Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min(2) Typ(3) Max(2) Units
VOS ±37 ±200
LMP7707 ±500
Input Offset Voltage μV
±37 ±220
LMP7708/LMP7709 ±520
TCVOS Input Offset Voltage Drift(4) ±1 ±5 μV/°C
IB±0.2 1
Input Bias Current(4)(5) −40°C ≤TA≤85°C ±50 pA
−40°C ≤TA≤125°C ±400
IOS Input Offset Current 40 fA
CMRR −5V ≤VCM ≤5V 92 138
LMP7707 88
Common Mode Rejection Ratio dB
−5V ≤VCM ≤5V 90 138
LMP7708/LMP7709 86
PSRR 2.7V ≤V+≤12V, V−= 0V, VO= V+/2 86 98
Power Supply Rejection Ratio dB
82
CMVR CMRR ≥80 dB −5.2 5.2
Input Common-Mode Voltage Range V
CMRR ≥78 dB −5.2 5.2
AVOL RL= 2 kΩ(LMP7707) 100 121
VO=−4.7V to 4.7V 98
RL= 2 kΩ(LMP7708/LMP7709) 100 121
VO=−4.7V to 4.7V 94
Open Loop Voltage Gain dB
RL= 10 kΩ(LMP7707) 100 134
VO=−4.8V to 4.8V 98
RL= 10 kΩ(LMP7708/LMP7709) 100 134
VO=−4.8V to 4.8V 97
VORL= 2 kΩto 0V 90 150
LMP7707 170
RL= 2 kΩto 0V 90 180
LMP7708/LMP7709 290 mV
Output Swing High from V+
RL= 10 kΩto 0V 40 80
LMP7707 100
RL= 10 kΩto 0V 40 80
LMP7708/LMP7709 150
RL= 2 kΩto 0V 90 130
LMP7707 150
RL= 2 kΩto 0V 90 180
LMP7708/LMP7709 290 mV
Output Swing Low from V–
RL= 10 kΩto 0V 40 50
LMP7707 60
RL= 10 kΩto 0V 40 60
LMP7708/LMP7709 110
(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the
Statistical Quality Control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) This parameter is specified by design and/or characterization and is not tested in production.
(5) Positive current corresponds to current flowing into the device.
6Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
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SNOSAW5B –JUNE 2007–REVISED MARCH 2013
±5V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5V, V−=−5V, VCM = 0V, and RL> 10 kΩto 0V.
Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min(2) Typ(3) Max(2) Units
IOSourcing VO= 0V 50 86
VIN = 100 mV (LMP7707) 35
Sourcing VO= 0V 48 86
Output Short Circuit Current(6)(7) mA
VIN = 100 mV (LMP7708/LMP7709) 33
Sinking VO= 0V 50 84
VIN =−100 mV 35
IS0.790 1.1
LMP7707 1.3
1.7 2.1
Supply Current LMP7708 mA
2.5
3.2 4.2
LMP7709 5.0
SR Slew Rate(8) VO= 9 VPP, 10% to 90% 5.9 V/μs
GBWP Gain Bandwidth Product AV= 10 15 MHz
THD+N f = 1 kHz, AV= 10, VO= 9V,
Total Harmonic Distortion + Noise 0.024 %
RL= 10 kΩ
enInput-Referred Voltage Noise f = 1 kHz 9 nV/√Hz
inInput-Referred Current Noise f = 100 kHz 1 fA/√Hz
(6) The maximum power dissipation is a function of TJ(MAX),θJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
(7) The short circuit test is a momentary test.
(8) The number specified is the slower of positive and negative slew rates.
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OUT
V-
IN+
V+
IN-
+-
1
2
3
5
4
NC
V-
IN+
V+
IN-
+
-
1
2
4
8
5
36
7
NC
NC
OUT
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
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Connection Diagrams
Top View Top View
Figure 2. LMP7707 5-Pin SOT-23 Figure 3. LMP7707 8-Pin SOIC
See DBV Package See D Package
Top View Top View
Figure 4. LMP7708 8-Pin VSSOP (See DGK Figure 5. LMP7709 14-Pin TSSOP (See PW
Package) Package)
LMP7708 8-Pin SOIC (See D Package) LMP7709 14-Pin SOIC (See D Package)
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TCVOS (PV/°C)
-3 -2 -1 0 1 2 3
0
4
8
12
16
20
PERCENTAGE (%)
VS = 10V
-40°C dTAd125°C
-200 -100 0 100 200
0
5
10
15
20
25
PERCENTAGE (%)
OFFSET VOLTAGE (PV)
VS = 10V
TA = 25°C
TCVOS (PV/°C)
-3 -2 -1 0 1 2 3
0
4
8
12
16
20
PERCENTAGE (%)
VS = 5V
-40°C dTAd125°C
-200 -100 0 100 200
0
5
10
15
20
25
PERCENTAGE (%)
OFFSET VOLTAGE (PV)
VS = 5V
TA = 25°C
TCVOS (PV/°C)
-3 -2 -1 0 1 2 3
0
4
8
12
16
20
PERCENTAGE (%)
VS = 3V
-40°C dTAd125°C
-200 -100 0 100 200
0
5
10
15
20
25
PERCENTAGE (%)
OFFSET VOLTAGE (PV)
VS = 3V
TA = 25°C
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SNOSAW5B –JUNE 2007–REVISED MARCH 2013
Typical Performance Characteristics
Unless otherwise specified, TA= 25°C, VCM = VS/2, RL> 10 kΩconnected to (V++V−)/2
Offset Voltage Distribution TCVOS Distribution
Figure 6. Figure 7.
Offset Voltage Distribution TCVOS Distribution
Figure 8. Figure 9.
Offset Voltage Distribution TCVOS Distribution
Figure 10. Figure 11.
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-1 0 1 2 3 4 5 6
-200
-150
-100
-50
0
50
100
150
200
OFFSET VOLTAGE (PV)
VCM (V)
VS = 5V
-40°C
25°C
125°C
-1 0 1 2 7 8 9 10 11
VCM (V)
-200
-150
-100
-50
0
50
100
150
200
OFFSET VOLTAGE (PV)
3 4 56
-40°C
125°C
25°C
VS = 10V
2 4 6 8 10 12
-200
-150
-100
-50
0
50
100
150
200
OFFSET VOLTAGE (PV)
SUPPLY VOLTAGE (V)
-40°C
25°C
125°C
-0.5 0 0.5 11.5 2 2.5 3 3.5
VCM (V)
-200
-150
-100
-50
0
50
100
150
200
OFFSET VOLTAGE (PV)
VS = 3V
25°C
125°C
-40°C
-40 -20 0 20 40 60 80 100 120125
-200
-150
-100
-50
0
50
200
OFFSET VOLTAGE (PV)
TEMPERATURE (°C)
100
150
VS = 3V
VS = 5V
VS = 10V
FREQUENCY (Hz)
CMRR (dB)
-20
-40
-60
-80
-100
-120
-140
-160
10 100 1k 10k 100k 1M
VS = 3V
VS = 5V
VS = 10V
-20
-40
-60
-80
-100
-120
-140
-160
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA= 25°C, VCM = VS/2, RL> 10 kΩconnected to (V++V−)/2
Offset Voltage vs. Temperature CMRR vs. Frequency
Figure 12. Figure 13.
Offset Voltage vs. Supply Voltage Offset Voltage vs. VCM
Figure 14. Figure 15.
Offset Voltage vs. VCM Offset Voltage vs. VCM
Figure 16. Figure 17.
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0 2 4 6 8 10
-500
-250
0
250
500
IBIAS (fA)
VCM (V)
VS = 10V
-40°C
25°C
0 2 4 6 8 10
-300
-200
-100
0
100
200
300
IBIAS (pA)
VCM (V)
VS = 10V
85°C
125°C
00.5 1 1.5 2 2.5 3
VCM (V)
-200
-100
0
100
200
IBIAS (fA)
VS = 3V
-40°C
25°C
01 2 3
VCM (V)
-300
-200
0
200
300
IBIAS (pA)
VS = 3V
0.5 1.5 2.5
100
-100
85°C
125°C
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA= 25°C, VCM = VS/2, RL> 10 kΩconnected to (V++V−)/2
Input Bias Current vs. VCM Input Bias Current vs. VCM
Figure 18. Figure 19.
Input Bias Current vs. VCM Input Bias Current vs. VCM
Figure 20. Figure 21.
Input Bias Current vs. VCM Input Bias Current vs. VCM
Figure 22. Figure 23.
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0 20 40 60 80 100
0
1
2
(V+) -2
(V+) -1
V+
VOUT FROM RAIL (V)
OUTPUT CURRENT (mA)
||
VS = 3V, 5V, 10V
TA = -40°C, 25°C, 125C
3V
SUPPLY VOLTAGE (V)
SLEW RATE (V/Ûs)
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2 4 6 8 10 12
RISING EDGE
FALLING EDGE
AV = +10
VIN = 200 mV
RL = 10 k:
CL = 10 pF
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2 4 6 8 10 12
0
20
40
60
80
100
120
ISINK (mA)
SUPPLY VOLTAGE (V)
125°C
-40°C
25°C
2 4 6 8 10 12
0
20
40
60
80
100
120
ISOURCE (mA)
SUPPLY VOLTAGE (V)
125°C
-40°C
25°C
FREQUENCY (Hz)
PSRR (dB)
120
100
80
60
40
20
10 100 1k 10k 100k 1M
-PSRR VS = 10V
+PSRR VS = 3V
+PSRR VS = 5V
+PSRR VS = 10V
-PSRR VS = 3V
-PSRR VS = 5V
AV = +10
2 4 6 8 10 12
0
0.2
0.4
0.6
0.8
1
1.2
SUPPLY CURRENT (mA)
SUPPLY VOLTAGE (V)
125°C
-40°C
25°C
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
Unless otherwise specified, TA= 25°C, VCM = VS/2, RL> 10 kΩconnected to (V++V−)/2 Supply Current vs.
PSRR vs. Frequency Supply Voltage (Per Channel)
Figure 24. Figure 25.
Sinking Current vs. Supply Voltage Sourcing Current vs. Supply Voltage
Figure 26. Figure 27.
Output Voltage vs. Output Current Slew Rate vs. Supply Voltage
Figure 28. Figure 29.
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10 Ûs/DIV
25 mV/DIV
VS = 5V
f = 10 kHz
AV = +100
VIN = 1 mVPP
RL = 10 k:
CL = 10 pF
10 Ûs/DIV
500 mV/DIV
VS = 5V
f = 10 kHz
AV = +100
VIN = 20 mVPP
RL = 10 k:
CL = 10 pF
10 Ûs/DIV
25 mV/DIV
VS = 5V
f = 10 kHz
AV = +10
VIN = 10 mVPP
RL = 10 k:
CL = 10 pF
10 Ûs/DIV
500 mV/DIV
VS = 5V
f = 10 kHz
AV = +10
VIN = 200 mVPP
RL = 10 k:
CL = 10 pF
PHASE (°)
FREQUENCY (Hz)
GAIN (dB)
100
80
60
40
20
0
-20
-40
-60
1k 10k 100k 1M 10M 100M
GAIN
PHASE 225
180
135
90
45
0
-45
-90
-135
AV = -10
VS = 3V, 5V, 10V
CL = 22 pF, 47 pF, 100 pF
VS = 3V
CL = 100 pF
VS = 10V
CL = 22 pF
PHASE (°)
FREQUENCY (Hz)
GAIN (dB)
100
80
60
40
20
0
-20
-40
-60
225
180
135
90
45
0
-45
-90
-135
1k 10k 100k 1M 10M 100M
GAIN
25°C
-40°C
PHASE
125°C
AV = -10
VS = 5V
RL = 10 k:
CL = 22 pF
100
80
60
40
20
0
-20
-40
-60 -135
-90
-45
0
45
90
135
180
225
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
Typical Performance Characteristics (continued)
Unless otherwise specified, TA= 25°C, VCM = VS/2, RL> 10 kΩconnected to (V++V−)/2
Open Loop Frequency Response Open Loop Frequency Response
Figure 30. Figure 31.
Small Signal Step Response, AV= 10 Large Signal Step Response, AV= 10
Figure 32. Figure 33.
Small Signal Step Response, AV= 100 Large Signal Step Response, AV= 100
Figure 34. Figure 35.
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2 4 6 8 10 12
0
20
40
60
80
100
VOUT FROM RAIL (mV)
SUPPLY VOLTAGE (V)
125°C
25°C
-40°C
RL = 2 k:
2 4 6 8 10 12
0
20
40
60
80
100
VOUT FROM RAIL (mV)
SUPPLY VOLTAGE (V)
125°C
25°C
-40°C
RL = 2 k:
2 4 6 8 10 12
0
10
20
30
40
50
VOUT FROM RAIL (mV)
SUPPLY VOLTAGE (V)
125°C 25°C
-40°C
RL = 10 k:
2 4 6 8 10 12
0
10
20
30
40
50
VOUT FROM RAIL (mV)
SUPPLY VOLTAGE (V)
125°C 25°C
-40°C
RL = 10 k:
500 400 300 200 100 0
60
70
80
90
100
110
120
130
140
150
OPEN LOOP GAIN (dB)
OUTPUT SWING FROM RAIL (mV)
RL = 2 k:
RL = 10 k:
VS = 3V
VS = 10V VS = 5V
1100 100k
FREQUENCY (Hz)
0
40
120
10k
1k
10
100
60
20
80
VS = 3V
VS = 5V
VS = 10V
INPUT REFERRED VOLTAGE NOISE
(nV/
Hz)
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
Unless otherwise specified, TA= 25°C, VCM = VS/2, RL> 10 kΩconnected to (V++V−)/2 Open Loop Gain vs.
Input Voltage Noise vs. Frequency Output Voltage Swing
Figure 36. Figure 37.
Output Swing High vs. Output Swing Low vs.
Supply Voltage Supply Voltage
Figure 38. Figure 39.
Output Swing High vs. Output Swing Low vs.
Supply Voltage Supply Voltage
Figure 40. Figure 41.
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100 1k 10k 100k 1M
FREQUENCY (Hz)
40
60
80
100
120
140
CROSSTALK REJECTION (dB)
VS = 3V VS = 5V
VS = 12V
FREQUENCY (Hz)
THD+N (%)
1
0.1
0.01
10 100 1k 10k 100k
AV = +10
AV = +100
VS = 5V
VOUT = 4.5VPP
RL = 100 k:
Noise band = 500 kHz
VOUT (VPP)
THD+N (%)
100
10
1
0.1
0.01
0.01 0.1 1 10
AV = +10
AV = +100
VS = 5V
f = 1 kHz
RL = 100 k:
Noise band = 500 kHz
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
Typical Performance Characteristics (continued)
Unless otherwise specified, TA= 25°C, VCM = VS/2, RL> 10 kΩconnected to (V++V−)/2
THD+N vs. Frequency THD+N vs. Output Voltage
Figure 42. Figure 43.
Crosstalk Rejection Ratio vs.
Frequency(LMP7708/LMP7709)
Figure 44.
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+
-VOUT
VIN RISO
CL
R1
R2
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
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APPLICATION INFORMATION
LMP7707/LMP7708/LMP7709
The LMP7707/LMP7708/LMP7709 devices are single, dual and quad low offset voltage, rail-to-rail input and
output precision amplifiers each with a CMOS input stage and the wide supply voltage range of 2.7V to 12V. The
LMP7707/LMP7708/LMP7709 have a very low input bias current of only ±200 fA at room temperature.
The wide supply voltage range of 2.7V to 12V over the extensive temperature range of −40°C to 125°C makes
either the LMP7707, LMP7708 or LMP7709 an excellent choice for low voltage precision applications with
extensive temperature requirements.
The LMP7707/LMP7708/LMP7709 have only ±37 µV of typical input referred offset voltage and this offset is
ensured to be less than ±500 µV for the single and ±520 µV for the dual and quad over temperature. This
minimal offset voltage allows more accurate signal detection and amplification in precision applications.
The low input bias current of only ±200 fA along with the low input referred voltage noise of 9 nV/√Hz give the
LMP7707/LMP7708/LMP7709 superior qualities for use in sensor applications. Lower levels of noise introduced
by the amplifier mean better signal fidelity and a higher signal-to-noise ratio.
The LMP7707/LMP7708/LMP7709 are stable for a gain of 6 or higher. With proper compensation though, the
LMP7707, LMP7708 or LMP7709 can be operational at a gain of ±1 and still maintain much faster slew rates
than comparable fully compensated amplifiers. The increase in bandwidth and slew rate is obtained without any
additional power consumption.
Texas Instruments is heavily committed to precision amplifiers and the market segment they serve. Technical
support and extensive characterization data is available for sensitive applications or applications with a
constrained error budget.
The LMP7707 is offered in the space-saving 5-pin SOT-23 and 8-pin SOIC packages, the LMP7708 comes in the
8-pin VSSOP and 8-pin SOIC packages, and the LMP7709 is offered in the 14-pin TSSOP and 14-pin SOIC
packages. These small packages are ideal solutions for area constrained PC boards and portable electronics.
CAPACITIVE LOAD
The LMP7707/LMP7708/LMP7709 devices can each be connected as a non-inverting voltage follower. This
configuration is the most sensitive to capacitive loading.
The combination of a capacitive load placed on the output of an amplifier along with the amplifier’s output
impedance creates a phase lag which in turn reduces the phase margin of the amplifier. If the phase margin is
significantly reduced, the response will be either underdamped or it will oscillate.
In order to drive heavier capacitive loads, an isolation resistor, RISO, as shown in the circuit in Figure 45 should
be used. By using this isolation resistor, the capacitive load is isolated from the amplifier’s output, and hence, the
pole caused by CLis no longer in the feedback loop. The larger the value of RISO, the more stable the output
voltage will be. If values of RISO are sufficiently large, the feedback loop will be stable, independent of the value
of CL. However, larger values of RISO result in reduced output swing and reduced output current drive.
Figure 45. Isolating Capacitive Load
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ESD R1
IN+
ESD
D1
D2
R2ESD
IN-
ESD
V+
V-V-
V+
R1 = R2 = 130Ö
CIN
R1
R2
VOUT
+
-
+
-
VIN
+
-
CF
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
INPUT CAPACITANCE
CMOS input stages inherently have low input bias current and higher input referred voltage noise. The
LMP7707/LMP7708/LMP7709 enhances this performance by having the low input bias current of only ±200 fA,
as well as a very low input referred voltage noise of 9 nV/√Hz. In order to achieve this a large input stage has
been used. This large input stage increases the input capacitance of the LMP7707/LMP7708/LMP7709. The
typical value of this input capacitance, CIN, for the LMP7707/LMP7708/LMP7709 is 25 pF. The input capacitance
will interact with other impedances such as gain and feedback resistors, which are seen on the inputs of the
amplifier, to form a pole. This pole will have little or no effect on the output of the amplifier at low frequencies and
DC conditions, but will play a bigger role as the frequency increases. At higher frequencies, the presence of this
pole will decrease phase margin and will also cause gain peaking. In order to compensate for the input
capacitance, care must be taken in choosing the feedback resistors. In addition to being selective in picking
values for the feedback resistor, a capacitor can be added to the feedback path to increase stability.
Figure 46. Compensating for Input Capacitance
Using this compensation method will have an impact on the high frequency gain of the op amp, due to the
frequency dependent feedback of this amplifier. Low gain settings can, again, introduce instability issues.
DIODES BETWEEN THE INPUTS
The LMP7707/LMP7708/LMP7709 have a set of anti-parallel diodes between the input pins, as shown in
Figure 47. These diodes are present to protect the input stage of the amplifier. At the same time, they limit the
amount of differential input voltage that is allowed on the input pins. A differential signal larger than one diode
voltage drop might damage the diodes. The differential signal between the inputs needs to be limited to ±300 mV
or the input current needs to be limited to ±10 mA. Exceeding these limits will damage the part.
Figure 47. Input of the LMP7707
TOTAL NOISE CONTRIBUTION
The LMP7707/LMP7708/LMP7709 have very low input bias current, very low input current noise and very low
input voltage noise. As a result, these amplifiers are ideal choices for circuits with high impedance sensor
applications.
Figure 48 shows the typical input noise of the LMP7707/LMP7708/LMP7709 as a function of source resistance.
The total noise at the input can be calculated using Equation 1.
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10 1k 100k 10M
RS (:)
0.1
1
10
1000
1M10k
100
100
VOLTAGE NOISE DENSITY (nV/
Hz)
eni en
ei
et
eni = en +
2ei +
2et
2
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
www.ti.com
where
• eni is the total noise on the input
• endenotes the input referred voltage noise
• eiis the voltage drop across source resistance due to input referred current noise or ei= RS* in
• etis the thermal noise of the source resistance (1)
The input current noise of the LMP7707/LMP7708/LMP7709 is so low that it will not become the dominant factor
in the total noise unless source resistance exceeds 300 MΩ, which is an unrealistically high value.
As is evident in Figure 48, at lower RSvalues, the total noise is dominated by the amplifier’s input voltage noise.
Once RSis larger than a few kilo-Ohms, then the dominant noise factor becomes the thermal noise of RS. As
mentioned before, the current noise will not be the dominant noise factor for any practical application.
Figure 48. Total Input Noise
HIGH IMPEDANCE SENSOR INTERFACE
Many sensors have high source impedances that may range up to 10 MΩ. The output signal of sensors often
needs to be amplified or otherwise conditioned by means of an amplifier. The input bias current of this amplifier
can load the sensor’s output and cause a voltage drop across the source resistance as shown in Figure 49,
where VIN +=VS– IBIAS*RS
The last term, IBIAS*RS, shows the voltage drop across RS. To prevent errors introduced to the system due to this
voltage, an op amp with very low input bias current must be used with high impedance sensors. This is to keep
the error contribution by IBIAS*RSless than the input voltage noise of the amplifier, so that it will not become the
dominant noise factor. The LMP7707/LMP7708/LMP7709 have very low input bias current, typically 200 fA.
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FREQUENCY (Hz)
GAIN (dB)
1k 10k 100k 1M 10M 100M
Gain LMP7701
Phase LMP7701
PHASE (°)
100
80
60
40
20
0
-20
80
100
120
140
160
180
200
SENSOR V+
V-
RS+
-
IBVIN+
VS+
-R1
R2
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
Figure 49. Noise Due to IBIAS
USAGE OF DECOMPENSATED AMPLIFIERS
This section discusses the differences between compensated and decompensated op amps and presents the
advantages of decompensated amplifiers. In high gain applications decompensated amplifiers can be used
without any changes compared to standard amplifiers. However, for low gain applications special frequency
compensation measures have to be taken to ensure stability.
Feedback circuit theory is discussed in detail, in particular as it applies to decompensated amplifiers. Bode plots
are presented for a graphical explanation of stability analysis. Two solutions are given for creating a feedback
network for decompensated amplifiers when relatively low gains are required: A simple resistive feedback
network and a more advanced frequency dependent feedback network with improved noise performance. Finally,
a design example is presented resulting in a practical application. The results are compared to fully compensated
amplifiers (Texas Instruments LMP7701/LMP7702/LMP7704).
COMPENSATED AMPLIFIERS
A (fully) compensated op amp is designed to operate with good stability down to gains of ±1. For this reason, the
compensated op amp is also called a unity gain stable op amp.
Figure 50 shows the Open Loop Response of a compensated amplifier.
Figure 50. Open Loop Frequency Response Compensated Amplifier (LMP7701)
This amplifier is unity gain stable, because the phase shift is still < 180°, when the gain crosses 0 dB (unity gain).
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FREQUENCY (Hz)
GAIN (dB)
1k 10k 100k 1M 10M 100M
Gain LMP7707
Phase LMP7707
PHASE (°)
100
80
60
40
20
0
-20
80
100
120
140
160
180
200
FPBW = SR
2 VP
í
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
www.ti.com
Stability can be expressed in two different ways:
Phase MarginThis is the phase difference between the actual phase shift and 180°, at the point where the gain
is 0 dB.
Gain MarginThis is the gain difference relative to 0 dB, at the frequency where the phase shift crosses the 180°.
The amplifier is supposed to be used with negative feedback but a phase shift of 180° will turn the negative
feedback into positive feedback, resulting in oscillations. A phase shift of 180° is not a problem when the gain is
smaller than 0 dB, so the critical point for stability is 180° phase shift at 0 dB gain. The gain margin and phase
margin express the margin enhancing overall stability between the amplifiers response and this critical point.
DECOMPENSATED AMPLIFIERS
Decompensated amplifiers, such as the LMP7707/LMP7708/LMP7709, are designed to maximize the bandwidth
and slew rate without any additional power consumption over the unity gain stable op amp. That is, a
decompensated op amp has a higher bandwidth to power ratio than an equivalent compensated op amp.
Compared with the unity gain stable amplifier, the decompensated version has the following advantages:
1. A wider closed loop bandwidth
2. Better slew rate due to reduced compensation capacitance within the op amp
3. Better Full Power Bandwidth, given with Equation 2
(2)
Figure 51 shows the frequency response of the decompensated amplifier.
Figure 51. Open Loop Frequency Response Decompensated Amplifier (LMP7707)
As shown in Figure 51, the reduced internal compensation moves the first pole to higher frequencies. The
second open loop pole for the LMP7707/LMP7708/LMP7709 occurs at 4 MHz. The extrapolated unity gain (see
dashed line in Figure 51) occurs at 14 MHz. An ideal two pole system would give a phase margin of > 45° at the
location of the second pole. Unfortunately, the LMP7707/LMP7708/LMP7709 have parasitic poles close to the
second pole, giving a phase margin closer to 0°. The LMP7707/LMP7708/LMP7709 can be used at frequencies
where the phase margin is > 45°. The frequency where the phase margin is 45° is at 2.4 MHz. The
corresponding value of the open loop gain (also called GMIN) is 6 times.
Stability has only to do with the loop gain and not with the forward gain (G) of the op amp. For high gains, the
feedback network is attenuating and this reduces the loop gain; therefore the op amp will be stable for G > GMIN
and no special measures are required. For low gains the feedback network attenuation may not be sufficient to
ensure loop stability for a decompensated amplifier. However, with an external compensation network
decompensated amplifiers can still be made stable while maintaining their advantages over unity gain stable
amplifiers.
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|ACL|(min) = Gmin
A = - = 1 -
CL
RF
R1
1
F
A = 1 + =
CL
RF
R1
1
F
= 1 + RF
R1
1
F
F = VA - VB
VOUT
-
+
RF
VOUT
R1-
+
RF
VOUT
R1
VIN
VIN
VAVA
VBVB
LMP7707, LMP7708, LMP7709
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SNOSAW5B –JUNE 2007–REVISED MARCH 2013
EXTERNAL COMPENSATION FOR GAINS LOWER THAN GMIN.
This section explains how decompensated amplifiers can be used in configurations requiring a gain lower than
GMIN. In the next sections the concept of the feedback factor is introduced. Subsequently, an explanation is given
how stability can be determined using the frequency response curve of the op amp together with the feedback
factor. Using the circuit theory, it will be explained how decompensated amplifiers can be stabilized at lower
gains.
FEEDBACK THEORY
Stability issues can be analyzed by verifying the loop gain function GF, where G is the open loop gain of the
amplifier and F is the feedback factor of the feedback circuit.
The feedback function (F) of arbitrary electronic circuits, as shown in Figure 52, is defined as the ratio of the
input and output signal of the same circuit.
Figure 52. Op Amp with Resistive Feedback. (a) Non-inverting (b) Inverting
The feedback function for a three-terminal op amp as shown in Figure 52 is the feedback voltage VA– VBacross
the op amp input terminals relative to the op amp output voltage, VOUT. That is
(3)
GRAPHICAL EXPLANATION OF STABILITY ANALYSIS
Stability issues can be observed by verifying the closed loop gain function GF. In the frequencies of interest, the
open loop gain (G) of the amplifier is a number larger than 1 and therefore positive in dB. The feedback factor (F)
of the feedback circuit is an attenuation and therefore negative in dB. For calculating the closed loop gain GF in
dB we can add the values of G and F (both in dB).
One practical approach to stabilizing the system, is to assign a value to the feedback factor F such that the
remaining loop gain GF equals one (unity gain) at the frequency of GMIN. This realizes a phase margin of 45° or
greater. This results in the following requirement for stability: 1/F > GMIN. The inverse feedback factor 1/F is
constant over frequency and should intercept the open loop gain at a value in dB that is greater than or equal to
GMIN.
The inverse feedback factor for both configurations shown in Figure 52, is given by:
(4)
The closed loop gain for the non-inverting configuration (a) is:
(5)
The closed loop gain for the inverting configuration (b) is:
(6)
For stable operation the phase margin must be equal to or greater than 45°. The corresponding closed loop gain
GMIN, for a non-inverting configuration, is
(7)
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= 1 + = 1 + +
RF
R //R
1 c
1
F
RF
R1
RF
Rc
-
+
RF
VOUT
R1
RC
AOL
Gmin = 20 dB
f1f2
= 6 dB = 1 + RF
R1
1
F
1
F
|ACL|(min) = Gmin - 1
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
www.ti.com
For an inverting configuration:
(8)
If R1and RFand are chosen so that the closed loop gain is lower than the minimum gain required for stability,
then 1/F intersects the open loop gain curve for a value that is lower than GMIN. For example, assume the GMIN is
equal to 10 V/V (20 dB). This is shown as the dashed line in Figure 53. The resistor choice of RF= R1=2kΩ
makes the inverse feedback equal 2 V/V (6 dB), shown in Figure 53 as the solid line. The intercept of G and 1/F
represents the frequency for which the loop gain is identical to 1 (0 dB). Consequently, the total phase shift at the
frequency of this intercept determines the phase margin and the overall system stability. In this system example
1/F crosses the open loop gain at a frequency which is larger than the frequency where GMIN occurs, therefore
this system has less than 45° phase margin and is most likely instable.
Figure 53. 1/F for RF= R1and Open Loop Gain Plot
RESISTIVE COMPENSATION
A straightforward way to achieve a stable amplifier configuration is to add a resistor RCbetween the inverting and
the non-inverting inputs as shown in Figure 54.
Figure 54. Op Amp with Compensation Resistor between Inputs
This additional resistor RCwill not affect the closed loop gain of the amplifier but it will have positive impact on
the feedback network.
The inverse feedback function of this circuit is:
(9)
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VX
R1+RF
VOUT - VX
=
RC
VX - VIN
(VIN ± VX) G = VOUT
-
+
RF
VOUT
R1
RC
VX
VIN
AOL
Gmin = 20 dB
f1f2
1 + = 6 dB
RF
RF
LMP7707, LMP7708, LMP7709
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SNOSAW5B –JUNE 2007–REVISED MARCH 2013
Proper selection of the value of RCresults in the shifting of the 1/F function to GMIN or greater, thus fulfilling the
condition for circuit stability. The compensation technique of reducing the loop gain may be used to stabilize the
circuit for the values given in the previous example, that is GMIN = 20 dB and RF= R1=2kΩ. A resistor value of
250 Ωapplied between the amplifier inputs shifts the 1/F curve to the value GMIN (20 dB) as shown by the
dashed line in Figure 55. This results in overall stability for the circuit. This figure shows a combination of the
open and closed loop gain and the inverse feedback function.
This example, represented by Figure 52 and Figure 53, is generic in the sense that the GMIN as specified did not
distinguish between inverting and non-inverting configurations.
Figure 55. Compensation with Reduced Loop Gain
The technique of reducing loop gain to stabilize a decompensated op amp circuit will be illustrated using the non-
inverting input configuration shown in Figure 56.
Figure 56. Closed Loop Gain Analysis with RC
The effect of the choice of resistor RCin Figure 56 on the closed loop gain can be analyzed in the following
manner:
Assume the voltage at the inverting input of the op amp is VX. Then,
where
• G is the open loop gain of the op amp (10)
(11)
Combining Equation 10,Equation 11, and Equation 9 produces the following equation for closed loop gain,
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LMP7707 LMP7708 LMP7709
GAIN (dB)
20
FREQUENCY (Hz)
60
40
80
0
-20 dB/dec
1M
1/F without compensation
1/F with compensation
20 dB/dec
100
=
VOUT
VIN GF
RF
1 +
1 +
R1
1
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
www.ti.com
(12)
By inspection of Equation 12, RCdoes not affect the ideal closed loop gain. In this example where RF= R1, the
closed loop gain remains at 6 dB as long as GF >> 1. The closed loop gain curve is shown as the solid line in
Figure 55.
The addition of RCaffects the circuit in the following ways:
1. 1/F is moved to a higher gain, resulting in overall system stability.
However, adding RCresults in reduced loop gain and increased noise gain. The noise gain is defined as the
inverse of the feedback factor, F. The noise gain is the gain from the amplifier input referred noise to the output.
In effect, loop gain is traded for stability.
2. The ideal closed loop gain retains the same value as the circuit without the compensation resistor RC.
LEAD-LAG COMPENSATION
This section presents a more advanced compensation technique that can be used to stabilize amplifiers. The
increased noise gain of the prior circuit is prevented by reducing the low frequency attenuation of the feedback
circuit. This compensation method is called Lead-Lag compensation. Lead-lag compensation components will be
analyzed and a design example using this procedure will be discussed.
The feedback function in a lead-lag compensation circuit is shaped using a resistor and a capacitor. They are
chosen in a way that ensures sufficient phase margin.
Figure 57 shows a Bode plot containing: the open loop gain of the decompensated amplifier, a feedback function
without compensation and a feedback function with lead-lag compensation.
Figure 57. Bode Plot of Open Loop gain G and 1/F with and without Lead-Lag Compensation
The shaped feedback function presented in Figure 57 can be realized using the amplifier configuration in
Figure 58. Note that resistor RPis only used for compensation of the input voltage caused by the IBIAS current. RP
can be used to introduce more freedom for calculating the lead-lag components. This will be discussed later in
this section.
24 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
= (1 + )(1 + )
f = ñ
FRFRP + R1//RF
R1RC
1
FRF
1R1
= 1 +
f = 0
fZ = 1
2í(RC + R1//RF + RP) C
fP = 1
2íRCC
= (1 + )( )
F1 + s(RC + R1//RF + RP)C
R11 + sRCC
RF
1
-
R1
RC
C
RF
+
RP
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
Figure 58. LMP7707 with Lead-Lag Compensation for Inverting Configuration
The inverse feedback factor of the circuit in Figure 58 is:
(13)
The pole of the inverse feedback function is located at:
(14)
The zero of the inverse feedback function is located at:
(15)
The low frequency inverse feedback factor is given by:
(16)
The high frequency inverse feedback factor is given by:
(17)
From these formulas, we can tell that
1. The 1/F's zero is located at a lower frequency compared to 1/F's pole.
2. The intersection point of 1/F and the open loop gain G is determined by the choice of resistor values for RP
and RCif the values of R1and RFare set before compensation.
3. This procedure results in the creation of a pole-zero pair, the positions of which are interdependent.
4. This pole-zero pair is used to:
– Raise the 1/F value to a greater value in the region immediately to the left of its intercept with the A
function in order to meet the Gmin requirement.
– Achieve the preceding with no additional loop phase delay.
5. The location of the 1/F zero is determined by the following conditions:
– The value of 1/F at low frequency.
– The value of 1/F at the intersection point.
– The location of 1/F pole.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: LMP7707 LMP7708 LMP7709
FREQUENCY (Hz)
GAIN (dB) AND PHASE (°)
100
80
60
40
20
0
-20
1k 10k 100k 1M 10M 100M
Gain
Phase
GMIN
f2
f2/10
1/F
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
www.ti.com
Note that the constraint 1/F ≥Gmin needs to be satisfied only in the vicinity of the intersection of G and 1/F; 1/F
can be shaped elsewhere as needed. Two rules must be satisfied in order to maintain adequate phase margin.
Rule 1The plot of 1/F should intersect with the plot of the open loop gain at a value larger than GMIN. At that
point, the open loop gain G has a phase margin of 45°.
The location f2in Figure 59 illustrates the proper intersection point for the LMP7707/LMP7708/LMP7709
using the circuit of Figure 58. The intersection of G and 1/F at the op amp's second pole location is the
45° phase margin reference point.
Rule 2The 1/F pole (see Figure 59) should be positioned at the frequency that is at least one decade below the
intersection point f2of 1/F and G. This positioning takes full advantage of the 90° of phase lead brought
about by the 1/F pole. This additional phase lead accompanies the increase in magnitude of 1/F observed
at frequencies greater than the 1/F pole.
The resulting system has approximately 45° of phase margin, based upon the fact that the open loop gain's
dominant pole and the second pole are more than one decade apart and that the open loop gain has no other
pole within one decade of its intersection point with 1/F. If there is a third pole in the open loop gain G at a
frequency greater than f2and if it occurs less than a decade above that frequency, then there will be an effect on
phase margin.
DESIGN EXAMPLE
The input lead-lag compensation method can be applied to an application using the LMP7707, LMP7708 or
LMP7709 in an inverting configuration, as shown in Figure 58.
Figure 59. LMP7707 Open Loop Gain and 1/F Lead-Lag Feedback Network.
Figure 59 shows that GMIN = 16 dB and f2(intersection point) = 2.4 MHz.
A gain of 6 dB (or a magnitude of –1) is well below the LMP7707’s GMIN. Without external lead-lag compensation,
the inverse feedback factor is found using Equation 4 which applies to both inverting and non-inverting
configurations. Unity gain implementation for the inverting configuration means RF= R1, and 1/F = 2 (6 dB).
Procedure:
The compensation circuit shown in Figure 58 is implemented. The inverse feedback function is shaped by the
solid line in Figure 59. The 1/F plot is 6 dB at low frequencies. At higher frequencies, it is made to intersect the
loop gain G at frequency f2with gain amplitude of 16 dB (GMIN), which equals a magnitude of six times. This
follows the recommendations in Rule 1. The 1/F pole fpis set one decade below the intersection point (f2= 2.4
MHz) as given in Rule 2, and results in a frequency fp= 240 kHz. The next steps should be taken to calculate the
values of the compensation components:
Step 1)Set 1/F equal to GMIN using Equation 17. This gives a value for resistor RC.
Step 2)Set the 1/F pole one decade below the intersection point using Equation 14. This gives a value for
capacitor C.
26 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
C =
1
2SfRC
fP = = 240 kHz
1
2SRCC
RP + R1//RF = 2 RC
= (1 + )(1 + )
f = ñ
FRFRP + R1//RF
R1RC
1= 6 V/V
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
This method uses bode plot approximation. Some fine-tuning may be needed to get the best results.
Calculations:
As described in Step 1, use Equation 17:
(18)
Now substitute RF/R1= 1 into the equation above since this is a unity gain, inverting amplifier, then
(19)
According to Step 2 use Equation 14:
(20)
which leads to:
(21)
Choose a value of RFthat is below 2 kΩ, in order to minimize the possibility of shunt capacitance across high
value resistors producing a negative effect on high frequency operation. If RF= R1=1kΩ, then RF// R1= 500 Ω.
For simplicity, choose RP=0Ω. The value of RCis derived from Equation 19 and has a value of RC= 250 Ω.
This is not a standard value. A value of RC= 330 Ωis a first choice (using 10% tolerance components).
The value of capacitor C is 2.2 nF. This value is significantly higher than the parasitic capacitances associated
with passive components and board layout, and is therefore a good solution.
Bench results:
For bench evaluation the LMP7707 in an inverting configuration has been verified under three different
conditions:
• Uncompensated
• Lead-lag compensation resulting in a phase margin of 45°
• Lead lag overcompensation resulting in a phase margin larger than 45°
The calculated components for these three conditions are
Condition RCC
Uncompensated NA NA
Compensated 330 Ω2.2 nF
Overcompensated 240 Ω3.3 nF
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: LMP7707 LMP7708 LMP7709
TIME (1 Ps/DIV)
VOUT (V)
0.8
0.4
0.0
-0.4
-0.8
LMP7701
LMP7707 compensated
TIME (1 Ps/DIV)
VOUT (0.5V/DIV)
0
0
0
uncompensated
compensated
overcompensated
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
www.ti.com
Figure 60 shows the results of the compensation of the LMP7707.
Figure 60. Bench Results for Lead- Lag Compensation
The top waveform shows the output response of a uncompensated LMP7707 using no external compensation
components. This trace shows ringing and is unstable (as expected). The middle waveform is the response of a
compensated LMP7707 using the compensation components calculated with the described procedure. The
response is reasonably well behaved. The bottom waveform shows the response of an overcompensated
LMP7707.
Finally, Figure 61 compares the step response of the compensated LMP7707 to that of the unity gain stable
LMP7701. The increase in dynamic performance is clear.
Figure 61. Bench Results for Comparison of LMP7701 and LMP7707
The application of input lead-lag compensation to a decompensated op amp enables the realization of circuit
gains of less than the minimum specified by the manufacturer. This is accomplished while retaining the
advantageous speed versus power characteristic of decompensated op amps.
28 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7707 LMP7708 LMP7709
LMP7707, LMP7708, LMP7709
www.ti.com
SNOSAW5B –JUNE 2007–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision A (March 2013) to Revision B Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 28
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Links: LMP7707 LMP7708 LMP7709
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
LMP7707MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM LMP77
07MA
LMP7707MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM LMP77
07MA
LMP7707MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AH4A
LMP7707MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AH4A
LMP7708MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMP77
08MA
LMP7708MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMP77
08MA
LMP7708MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AJ4A
LMP7708MME/NOPB ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AJ4A
LMP7708MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AJ4A
LMP7709MA/NOPB ACTIVE SOIC D 14 55 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM LMP7709
MA
LMP7709MAX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM LMP7709
MA
LMP7709MT/NOPB ACTIVE TSSOP PW 14 94 Pb-Free
(RoHS) CU SN Level-1-260C-UNLIM -40 to 125 LMP77
09MT
LMP7709MTX/NOPB ACTIVE TSSOP PW 14 2500 Pb-Free
(RoHS) CU SN Level-1-260C-UNLIM -40 to 125 LMP77
09MT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 2
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMP7707MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMP7707MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMP7707MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMP7708MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMP7708MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMP7708MME/NOPB VSSOP DGK 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMP7708MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMP7709MAX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
LMP7709MTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMP7707MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMP7707MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMP7707MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMP7708MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMP7708MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LMP7708MME/NOPB VSSOP DGK 8 250 210.0 185.0 35.0
LMP7708MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
LMP7709MAX/NOPB SOIC D 14 2500 367.0 367.0 35.0
LMP7709MTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2016
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
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