S-25A010A/020A/040A
www.ablicinc.com
FOR AUTOMOTIVE 125°C OPERATION
SPI SERIAL E2PROM
© ABLIC Inc., 2008-2014 Rev.5.2_02
1
This IC is a SPI serial E2PROM which operates under the high temperature, at high speed, with the wide range operation for
automotive components. This IC has the capacity of 1 K-bit, 2 K-bit, 4 K-bit and the organization of 128 words 8-bit, 256
words 8-bit, 512 words 8-bit. Page write and Sequential read are available.
Caution Before using the product in automobile control unit or medical equipment, contact to ABLIC Inc. is
indispensable.
Features
Operating voltage range
Read: 2.5 V to 5.5 V
Write: 2.5 V to 5.5 V
Operation frequency: 6.5 MHz max.
Write time: 4.0 ms max.
SPI mode (0, 0) and (1, 1)
Page write: 16 bytes / page
Sequential read
Write protect: Software, Hardware
Protect area: 25%, 50%, 100%
Monitoring of a write memory state by the status register
Function to prevent malfunction by monitoring clock pulse
Write protect function during the low power supply voltage
CMOS schmitt input ( CS , SCK, SI, WP , HOLD )
Endurance*1: 106 cycle / word*2 (Ta = 25C)
5 105 cycle / word*2 (Ta = 125C)
Data retention: 100 years (Ta = 25C)
50 years (Ta = 125C)
Memory capacity
S-25A010A: 1 K-bit
S-25A020A: 2 K-bit
S-25A040A: 4 K-bit
Initial delivery state: FFh, BP1 = 0, BP0 = 0
Burn-in specification: Wafer level burn-in
Operation temperature range: Ta = 40°C to 125°C
Lead-free (Sn 100%), halogen-free*3
AEC-Q100 qualified*4
*1. Refer to " Endurance" for details.
*2. For each address (Word: 8-bit)
*3. Refer to " Product Name Structure" for details.
*4. Contact our sales office for details.
Packages
8-Pin SOP (JEDEC)
1
4
5
8
(5.0 6.0 t1.75 mm)
8-Pin TSSOP
1
4
5
8
(3.0 6.4 t1.1 mm)
TMSOP-8
1
4
5
8
(2.9 4.0 t0.8 mm)
Remark Refer to "3. Product name list" in " Product Name Structure" for details of package and product.
www.ablic.com
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A010A/020A/040A Rev.5.2_02
2
Block Diagram
Mode
Decoder
Status RegisterAddress Register
Data Register
WP
CS
HOLD
SI
SCK
SO
VCC
GND
Memory
Cell
Array
Status
Memory Cell Array
Voltage Detector
Read Circuit
Clock Counter
Y Decoder
X Decoder
Input Control Circuit
Output
Control
Circuit
Step-up Circuit
Page Latch
Figure 1
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
Rev.5.2_02 S-25A010A/020A/040A
3
AEC-Q100 Qualified
This IC supports AEC-Q100 for operation temperature grade 1.
Contact our sales office for details of AEC-Q100 reliability specification.
Product Name Structure
1. Product name
S-25AxxxA 0A xxxx U D
Burn-in specification
D: Wafer level burn-in
Environmental code
U: Lead-free (Sn 100%), halogen-free
Package name (abbreviation) and IC packing specification*1
J8T2: 8-Pin SOP (JEDEC), Tape
T8T2: 8-Pin TSSOP, Tape
K8T2: TMSOP-8, Tape
Fixed
Product name
S-25A010A: 1 K-bit
S-25A020A: 2 K-bit
S-25A040A: 4 K-bit
*1. Refer to the tape drawing.
2. Packages
Table 1 Package Drawing Codes
Package Name Dimension Tape Reel
8-Pin SOP (JEDEC) FJ008-A-P-SD FJ008-D-C-SD FJ008-D-R-SD
8-Pin TSSOP FT008-A-P-SD FT008-E-C-SD FT008-E-R-SD
TMSOP-8 FM008-A-P-SD FM008-A-C-SD FM008-A-R-SD
3. Product name list
Table 2
Product Name Capacity Package Quantity
S-25A010A0A-J8T2UD 1 K bit 8-Pin SOP (JEDEC) 2000 pcs / reel
S-25A010A0A-T8T2UD 1 K bit 8-Pin TSSOP 3000 pcs / reel
S-25A010A0A-K8T2UD 1 K bit TMSOP-8 4000 pcs / reel
S-25A020A0A-J8T2UD 2 K bit 8-Pin SOP (JEDEC) 2000 pcs / reel
S-25A020A0A-T8T2UD 2 K bit 8-Pin TSSOP 3000 pcs / reel
S-25A020A0A-K8T2UD 2 K bit TMSOP-8 4000 pcs / reel
S-25A040A0A-J8T2UD 4 K bit 8-Pin SOP (JEDEC) 2000 pcs / reel
S-25A040A0A-T8T2UD 4 K bit 8-Pin TSSOP 3000 pcs / reel
S-25A040A0A-K8T2UD 4 K bit TMSOP-8 4000 pcs / reel
Remark 1. Please contact our sales office for products with product name structure other than those
specified above.
2. This IC is wafer level burn-in specification.
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A010A/020A/040A Rev.5.2_02
4
Pin Configurations
1. 8-Pin SOP (JEDEC)
7
6
5
8
2
3
4
1
Top view
Figure 2
Table 3
Pin No. Symbol Description
1 CS *1 Chip select input
2 SO Serial data output
3 WP *1 Write protect input
4 GND Ground
5 SI*1 Serial data input
6 SCK*1 Serial clock input
7 HOLD *1 Hold input
8 VCC Power supply
2. 8-Pin TSSOP
7
6
5
8
2
3
4
1
Top view
Figure 3
Table 4
Pin No. Symbol Description
1 CS *1 Chip select input
2 SO Serial data output
3 WP *1 Write protect input
4 GND Ground
5 SI*1 Serial data input
6 SCK*1 Serial clock input
7 HOLD *1 Hold input
8 VCC Power supply
3. TMSOP-8
7
6
5
8
2
3
4
1
Top view
Figure 4
Table 5
Pin No. Symbol Description
1 CS *1 Chip select input
2 SO Serial data output
3 WP *1 Write protect input
4 GND Ground
5 SI*1 Serial data input
6 SCK*1 Serial clock input
7 HOLD *1 Hold input
8 VCC Power supply
*1. Do not use it in "High-Z".
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
Rev.5.2_02 S-25A010A/020A/040A
5
Absolute Maximum Ratings
Table 6
Item Symbol Absolute Maximum Rating Unit
Power supply voltage VCC 0.3 to 7.0 V
Input voltage VIN 0.3 to 7.0 V
Output voltage VOUT 0.3 to VCC 0.3 V
Operation ambient temperature To
pr
40 to 125 °C
Storage temperature Tst
g
65 to 150 °C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
Recommended Operating Conditions
Table 7
Item Symbol Condition Ta = 40C to 125C Unit
Min. Max.
Power supply voltage VCC
Read 2.5 5.5 V
Write 2.5 5.5 V
High level input voltage VIH V
CC = 2.5 V to 5.5 V 0.7 VCC V
CC 1.0 V
Low level input voltage VIL V
CC = 2.5 V to 5.5 V 0.3 0.3 VCC V
Pin Capacitance
Table 8
(Ta = 25°C, f = 1.0 MHz, VCC = 5.0 V)
Item Symbol Condition Min. Max. Unit
Input capacitance CIN VIN = 0 V ( CS , SCK, SI, WP , HOLD ) － 8 pF
Output capacitance COUT V
OUT = 0 V (SO) － 10 pF
Endurance
Table9
Item Symbol Operation Ambient Temperature Min. Max. Unit
Endurance NW
Ta = 40°C to 85°C 106 － cycle / word*1
Ta = 40°C to 105°C 8 105 － cycle / word*1
Ta = 40°C to 125°C 5 105 － cycle / word*1
*1. For each address (Word: 8-bit)
Data Retention
Table 10
Item Symbol Operation Ambient Temperature Min. Max. Unit
Data retention － Ta = 25°C 100
－ year
Ta = 40°C to 125°C 50
－ year
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A010A/020A/040A Rev.5.2_02
6
DC Electrical Characteristics
Table 11
Item Symbol Condition
Ta = 40°C to 125°C
Unit
VCC = 2.5 V to 3.0 V
fSCK = 3.5 MHz
VCC = 3.0 V to 4.5 V
fSCK = 5.0 MHz
VCC = 4.5 V to 5.5 V
fSCK = 6.5 MHz
Min. Max. Min. Max. Min. Max.
Current consumption
(read) ICC1 No load at
SO pin － 1.5 － 2.0 － 2.5 mA
Table 12
Item Symbol Condition
Ta = 40°C to 125°C
Unit
VCC = 2.5 V to 3.0 V
fSCK = 3.5 MHz
VCC = 3.0 V to 4.5 V
fSCK = 5.0 MHz
VCC = 4.5 V to 5.5 V
fSCK = 6.5 MHz
Min. Max. Min. Max. Min. Max.
Current consumption
(write) ICC2 No load at
SO pin － 2.0 － 2.5 － 3.0 mA
Table 13
Item Symbol Condition
Ta = 40°C to 85°C Ta = 85°C to 125°C
Unit
V
CC
= 2.5 V to 4.5 V V
CC
= 4.5 V to 5.5 V V
CC
= 2.5 V to 4.5 V V
CC
= 4.5 V to 5.5 V
Min. Max. Min. Max. Min. Max. Min. Max.
Standby current
consumption ISB
CS = VCC,
SO = Open
Other inputs are
VCC or GND
－ 2.0 － 3.0 － 8.0 － 10.0 A
Input leakage
current ILI V
IN = GND to VCC － 1.0 － 1.0 － 2.0 － 2.0 A
Output leakage
current ILO V
OUT = GND to VCC － 1.0 － 1.0 － 2.0 － 2.0 A
Low level
output voltage
VOL1 I
OL = 2.0 mA － － － 0.4 － － － 0.4 V
VOL2 I
OL = 1.5 mA － 0.4 － 0.4 － 0.4 － 0.4 V
High level
output voltage
VOH1 I
OH = 2.0 mA － － 0.8
VCC － － － 0.8
VCC － V
VOH2 I
OH = 0.4 mA 0.8
VCC － 0.8
VCC － 0.8
VCC － 0.8
VCC － V
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
Rev.5.2_02 S-25A010A/020A/040A
7
AC Electrical Characteristics
Table 14 Measurement Conditions
Input pulse voltage 0.2 VCC to 0.8 VCC
Output reference voltage 0.5 VCC
Output load 100 pF
Table 15
Item Symbol
Ta = 40°C to 125°C
Unit
V
CC
= 2.5 V to 5.5 V V
CC
= 3.0 V to 5.5 V V
CC
= 4.5 V to 5.5 V
Min. Max. Min. Max. Min. Max.
SCK clock frequency fSCK － 3.5 － 5.0 － 6.5 MHz
CS setup time during CS falling tCSS.CL 90 － 90 － 65 － ns
CS setup time during CS rising tCSS.CH 90 － 90 － 65 － ns
CS deselect time tCDS 160
－ 140 － 110 － ns
CS hold time during CS falling tCSH.CL 90 － 90 － 65 － ns
CS hold time during CS rising tCSH.CH 90 － 90 － 65 － ns
SCK clock time "H"*1 tHIGH 125
－ 95 － 65 － ns
SCK clock time "L"*1 tLOW 125
－ 95 － 65 － ns
Rising time of SCK clock*2 tRSK － 1 － 1 － 1 s
Falling time of SCK clock*2 tFSK － 1 － 1 － 1 s
SI data input setup time tDS 20
－ 20 － 20 － ns
SI data input hold time tDH 30
－ 30 － 30 － ns
SCK "L" hold time during HOLD rising tSKH.HH 70 － 70 － 45 － ns
SCK "L" hold time during HOLD falling tSKH.HL 40 － 40 － 30 － ns
SCK "L" setup time during HOLD falling tSKS.HL 0 － 0 － 0 － ns
SCK "L" setup time during HOLD rising tSKS.HH 0 － 0 － 0 － ns
Disable time of SO output*2 tOZ － 100 － 100 － 75 ns
Delay time of SO output tOD － 120 － 90 － 60 ns
Hold time of SO output tOH 0
－ 0 － 0 － ns
Rising time of SO output*2 tRO － 80 － 80 － 50 ns
Falling time of SO output*2 tFO － 80 － 80 － 50 ns
Disable time of SO output during HOLD falling*2 tOZ.HL － 100 － 100 － 75 ns
Delay time of SO output during HOLD rising*2 tOD.HH － 80 － 80 － 60 ns
WP setup time tWS1 0
－ 0 － 0 － ns
WP hold time tWH1 0
－ 0 － 0 － ns
WP release / setup time tWS2 0
－ 0 － 0 － ns
WP release / hold time tWH2 150
－ 150 － 100 － ns
*1. The clock cycle of the SCK clock (frequency fSCK) is 1 / fSCK s. This clock cycle is determined by a combination of
several AC characteristics. Note that the clock cycle cannot be set as (1 / fSCK) = tLOW (min.) tHIGH (min.) by minimizing
the SCK clock cycle time.
*2. These are values of sample and not 100% tested.
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A010A/020A/040A Rev.5.2_02
8
Table 16
Item Symbol
Ta = 40°C to 105°C
Unit
V
CC
= 2.5 V to 5.5 V V
CC
= 3.0 V to 5.5 V V
CC
= 4.5 V to 5.5 V
Min. Max. Min. Max. Min. Max.
SCK clock frequency fSCK － 3.5 － 5.0 － 6.5 MHz
CS setup time during CS falling tCSS.CL 90 － 90 － 65 － ns
CS setup time during CS rising tCSS.CH 90 － 90 － 65 － ns
CS deselect time tCDS 160
－ 140 － 110 － ns
CS hold time during CS falling tCSH.CL 90 － 90 － 65 － ns
CS hold time during CS rising tCSH.CH 90 － 90 － 65 － ns
SCK clock time "H"*1 tHIGH 125
－ 95 － 65 － ns
SCK clock time "L"*1 tLOW 125
－ 95 － 65 － ns
Rising time of SCK clock*2 tRSK － 1 － 1 － 1 s
Falling time of SCK clock*2 tFSK － 1 － 1 － 1 s
SI data input setup time tDS 20
－ 20 － 20 － ns
SI data input hold time tDH 30
－ 30 － 30 － ns
SCK "L" hold time during HOLD rising tSKH.HH 70 － 70 － 45 － ns
SCK "L" hold time during HOLD falling tSKH.HL 40 － 40 － 30 － ns
SCK "L" setup time during HOLD falling tSKS.HL 0 － 0 － 0 － ns
SCK "L" setup time during HOLD rising tSKS.HH 0 － 0 － 0 － ns
Disable time of SO output*2 tOZ － 100 － 100 － 75 ns
Delay time of SO output tOD － 120 － 90 － 60 ns
Hold time of SO output tOH 0
－ 0 － 0 － ns
Rising time of SO output*2 tRO － 80 － 70 － 50 ns
Falling time of SO output*2 tFO － 80 － 70 － 50 ns
Disable time of SO output during HOLD falling*2 tOZ.HL － 100 － 100 － 75 ns
Delay time of SO output during HOLD rising*2 tOD.HH － 80 － 80 － 60 ns
WP setup time tWS1 0
－ 0 － 0 － ns
WP hold time tWH1 0
－ 0 － 0 － ns
WP release / setup time tWS2 0
－ 0 － 0 － ns
WP release / hold time tWH2 150
－ 150 － 100 － ns
*1. The clock cycle of the SCK clock (frequency fSCK) is 1 / fSCK s. This clock cycle is determined by a combination of
several AC characteristics. Note that the clock cycle cannot be set as (1 / fSCK) = tLOW (min.) tHIGH (min.) by minimizing
the SCK clock cycle time.
*2. These are values of sample and not 100% tested.
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
Rev.5.2_02 S-25A010A/020A/040A
9
Table 17
Item Symbol
Ta = 40°C to 85°C
Unit
V
CC
= 2.5 V to 5.5 V V
CC
= 3.0 V to 5.5 V V
CC
= 4.5 V to 5.5 V
Min. Max. Min. Max. Min. Max.
SCK clock frequency fSCK － 4.0 － 5.0 － 7.0 MHz
CS setup time during CS falling tCSS.CL 90 － 80 － 60 － ns
CS setup time during CS rising tCSS.CH 90 － 80 － 60 － ns
CS deselect time tCDS 150
－ 120 － 100 － ns
CS hold time during CS falling tCSH.CL 90 － 80 － 60 － ns
CS hold time during CS rising tCSH.CH 90 － 80 － 60 － ns
SCK clock time "H"*1 tHIGH 115
－ 90 － 60 － ns
SCK clock time "L"*1 tLOW 115
－ 90 － 60 － ns
Rising time of SCK clock*2 tRSK － 1 － 1 － 1 s
Falling time of SCK clock*2 tFSK － 1 － 1 － 1 s
SI data input setup time tDS 20
－ 20 － 20 － ns
SI data input hold time tDH 30
－ 30 － 30 － ns
SCK "L" hold time during HOLD rising tSKH.HH 70 － 60 － 40 － ns
SCK "L" hold time during HOLD falling tSKH.HL 40 － 40 － 30 － ns
SCK "L" setup time during HOLD falling tSKS.HL 0 － 0 － 0 － ns
SCK "L" setup time during HOLD rising tSKS.HH 0 － 0 － 0 － ns
Disable time of SO output*2 tOZ － 100 － 100 － 70 ns
Delay time of SO output tOD － 110 － 85 － 55 ns
Hold time of SO output tOH 0
－ 0 － 0 － ns
Rising time of SO output*2 tRO － 80 － 50 － 40 ns
Falling time of SO output*2 tFO － 80 － 50 － 40 ns
Disable time of SO output during HOLD falling*2 tOZ.HL － 100 － 100 － 70 ns
Delay time of SO output during HOLD rising*2 tOD.HH － 80 － 75 － 55 ns
WP setup time tWS1 0
－ 0 － 0 － ns
WP hold time tWH1 0
－ 0 － 0 － ns
WP release / setup time tWS2 0
－ 0 － 0 － ns
WP release / hold time tWH2 150
－ 150 － 100 － ns
*1. The clock cycle of the SCK clock (frequency fSCK) is 1 / fSCK s. This clock cycle is determined by a combination of
several AC characteristics. Note that the clock cycle cannot be set as (1 / fSCK) = tLOW (min.) tHIGH (min.) by minimizing
the SCK clock cycle time.
*2. These are values of sample and not 100% tested.
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A010A/020A/040A Rev.5.2_02
10
Table 18
Item Symbol
Ta = 40°C to 125°C
Unit
VCC = 2.5 V to 5.5 V
Min. Max.
Write time tPR － 4.0 ms
SO
t
CSH.CL
SCK
CS
SI
t
CSS.CL
t
DS
t
DH
MSB IN LSB IN
t
CSH.CH
t
CSS.CH
t
CDS
t
FSK
t
RSK
High-Z
Figure 5 Serial Input Timing
SO
SCK
HOLD
CS
SI
t
SKH.HL
t
OZ.HL
t
OD.HH
t
SKH.HH
t
SKS.HL
t
SKS.HH
Figure 6 Hold Timing
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
Rev.5.2_02 S-25A010A/020A/040A
11
SO
SCK
CS
SI
tHIGH
tOH
tRO
tOZ
tLOW
tSCK
tOD
tFO
tOD tOH
ADDR
LSB IN
LSB OUT
Figure 7 Serial Output Timing
WP
CS
t
WH1
t
WS1
Figure 8 Valid Timing in Write Protect
WP
CS
t
WH2
t
WS2
Figure 9 Invalid Timing in Write Protect
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A010A/020A/040A Rev.5.2_02
12
Pin Functions
1. CS (chip select input) pin
This is an input pin to set a chip in the select status. In the "H" input level, this IC is in the non-select status and its
output is "High-Z". This IC is in standby as long as it is not in write inside. This IC goes in active by setting the chip
select to "L". Input any instruction code after power-on and a falling of chip select.
2. SI (serial data input) pin
This pin is to input serial data. This pin receives an instruction code, an address and write data. This pin latches data
at rising edge of serial clock.
3. SO (serial data output) pin
This pin is to output serial data. The data output changes at falling edge of serial clock.
4. SCK (serial clock input) pin
This is a clock input pin to set the timing of serial data. An instruction code, an address and write data are received at
a rising edge of clock. Data is output during falling edge of clock.
5. WP (write protect input) pin
This is an input pin to protect memory data when write instruction (WRITE, WRSR) is being input. By setting this pin
to "L", the WEL bit in the status register is set to "L". Therefore this IC does not write to the E2PROM, however, it
accepts other instructions. Fix this pin "H" or "L" not to set it in the floating state.
Refer to " Protect Operation" for details.
6. HOLD (hold input) pin
This pin is used to pause serial communications without setting this IC in the non-select status.
In the hold status, the serial output goes in "High-Z", the serial input and the serial clock go in "Don't care". During the
hold operation, be sure to set this IC in active by setting the chip select ( CS pin) to "L".
Refer to " Hold Operation" for details.
Initial Delivery State
Initial delivery state of all addresses is "FFh".
Moreover, initial delivery state of the status register nonvolatile memory is as follows.
BP1 = 0
BP0 = 0
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
Rev.5.2_02 S-25A010A/020A/040A
13
Instruction Sets
Table 19 and Table 20 are the list of instruction for this IC. The instruction is able to be input by changing the CS "H" to
"L". Input the instruction in the MSB first. Each instruction code is organized with 1-byte as shown below. If this IC
receives any invalid instruction code, this IC goes in the non-select status.
1. S-25A010A/020A
Table 19 Instruction Set
Instruction Operation
Instruction Code Address Data
SCK Input Clock
1 to 8
SCK Input Clock
9 to 16
SCK Input Clock
17 to 24
WREN Write enable 0000 X110 － －
WRDI Write disable 0000 X100 － －
RDSR Read the status register 0000 X101 b7 to b0 output*1 －
WRSR Write in the status register 0000 X001 b7 to b0 input －
READ Read memory data 0000 X011 A7*2 to A0 D7 to D0 output*3
WRITE Write memory data 0000 X010 A7*2 to A0 D7 to D0 input
*1. Sequential data reading is possible.
*2. In the S-25A010A, A7 = Don’t care because the address range is A6 to A0.
*3. After outputting data in the specified address, data in the following address is output.
Remark X = Don't care.
2. S-25A040A
Table 20 Instruction Set
Instruction Operation
Instruction Code Address Data
SCK Input Clock
1 to 8
SCK Input Clock
9 to 16
SCK Input Clock
17 to 24
WREN Write enable 0000 X110 － －
WRDI Write disable 0000 X100 － －
RDSR Read the status register 0000 X101 b7 to b0 output*1 －
WRSR Write in the status register 0000 X001 b7 to b0 input －
READ Read memory data 0000 [A8*2]011 A7 to A0 D7 to D0 output*3
WRITE Write memory data 0000 [A8*2]010 A7 to A0 D7 to D0 input
*1. Sequential data reading is possible.
*2. In the S-25A040A, assign bit A8 in the address into the fifth bit in an instruction code.
*3. After outputting data in the specified address, data in the following address is output.
Remark X = Don't care.
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A010A/020A/040A Rev.5.2_02
14
Operation
1. Status register
The status register's organization is below. The status register can write and read by a specific instruction.
11
b7 b6
1
b5
1
b4
BP1
b3
BP0
b2
WEL
b1
WIP
b0
Block Protect
Write Enable Latch
Write In Progress
Figure 10 Organization of Status Register
The status / control bits of the status register are as follows.
1. 1 BP1, BP0 (b3, b2) : Block Protect
Bit BP1 and BP0 are composed of the nonvolatile memory. The area size of Software Protect with respect to
WRITE instructions is defined by the BP1 and BP0 bits. Rewriting these bits is possible by the WRSR instruction.
To protect the memory area against the WRITE instruction, set either or both of bit BP1 and BP0 to "1". Rewriting
bit BP1 and BP0 is possible unless they are in Hardware Protect mode. Refer to " Protect Operation" for details
of Block Protect.
1. 2 WEL (b1) : Write Enable Latch
Bit WEL shows the status of internal Write Enable Latch. Bit WEL is set by the WREN instruction only. If bit WEL
is "1", this is the status that Write Enable Latch is set. If bit WEL is "0", Write Enable Latch is in reset, so that this
IC does not receive the WRITE or WRSR instruction. Bit WEL is reset after these operations;
The power supply voltage is dropping
At power-on
After performing WRDI
After the completion of write operation by the WRSR instruction
After the completion of write operation by the WRITE instruction
After setting WP pin to "L"
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
Rev.5.2_02 S-25A010A/020A/040A
15
1. 3 WIP (b0) : Write In Progress
Bit WIP is a read only bit. It indicates whether the internal memory is in the write operation or not by the WRITE or
WRSR instruction. Bit WIP is "1" during the write operation but "0" during any other status. Figure 11 shows the
usage example.
1111 1111 1111 00
B
P
1
B
P
0
B
P
1
B
P
0
B
tPR
P
1
B
P
0
WEL, WIP WEL, WIP WEL, WIP
CS
SI
SO
RDSR instruction RDSR instruction RDSR instruction
RDSR RDSR RDSR
11 11
WRITE or WRSR instruction
D2 D1 D0
Figure 11 Usage Example of WEL, WIP Bits during Write
2. Write enable (WREN)
Before writing data (WRITE and WRSR), be sure to set bit Write Enable Latch (WEL). This instruction is to set bit
WEL. Its operation is below.
After selecting this IC by the chip select ( CS ), input the instruction code from serial data input (SI). To set bit WEL,
set this IC in the non-select status by CS at the 8th clock of the serial clock (SCK). To cancel the WREN instruction,
input the clock different from a specified value (n = 8 clock) while CS is in "L".
SO
SCK
WP
CS
SI
Instruction
High-Z
12345678
High
X
Remark X = Don't care.
Figure 12 WREN Operation
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A010A/020A/040A Rev.5.2_02
16
3. Write disable (WRDI)
The WRDI instruction is one of ways to reset bit Write Enable Latch (WEL). After selecting this IC by the chip select
(CS ), input the instruction code from serial data input (SI).
To reset bit WEL, set this IC in the non-select status by CS at the 8th clock of the serial clock.
To cancel the WRDI instruction, input the clock different from a specified value (n = 8 clock) while CS is in "L".
Bit WEL is reset after the operations shown below.
The power supply voltage is dropping
At power-on
After performing WRDI
After the completion of write operation by the WRSR instruction
After the completion of write operation by the WRITE instruction
After setting WP pin to "L"
SO
SCK
WP
CS
SI
Instruction
High-Z
12345678
High / Low
X
Remark X = Don't care.
Figure 13 WRDI Operation
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
Rev.5.2_02 S-25A010A/020A/040A
17
4. Read the status register (RDSR)
Reading data in the status register is possible by the RDSR instruction. During the write operation, it is possible to
confirm the progress by checking bit WIP.
Set the chip select ( CS ) "L" first. After that, input the instruction code from serial data input (SI). The status of bit in
the status register is output from serial data output (SO). Sequential read is available for the status register. To stop
the read cycle, set CS to "H".
It is possible to read the status register always. The bits in it are valid and can be read by RDSR even in the write
cycle.
The 2 bits WEL and WIP are updated during the write cycle. The updated nonvolatile bits BP1 and BP0 can be
acquired by performing a new RDSR instruction after verifying the completion of the write cycle.
b7, b6, b5, and b4 are "1" when they are read by the RDSR instruction.
SO
SCK
WP
CS
SI
Instruction
High-Z
12345678
High / Low
9 10111213141516
Outputs Data in the Status Register
b7 b6 b5 b7b0b1b2b3b4
X
Remark X = Don't care.
Figure 14 RDSR Operation
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A010A/020A/040A Rev.5.2_02
18
5. Write in the status register (WRSR)
The values of status register (BP1, BP0) can be rewritten by inputting the WRSR instruction. But b7, b6, b5, b4, b1,
b0 of status register cannot be rewritten. b7 to b4 are always "1" when reading the status register.
Before inputting the WRSR instruction, set bit WEL by the WREN instruction. The operation of WRSR is shown
below.
Set the chip select ( CS ) "L" first. After that, input the instruction code and data from serial data input (SI). To start
WRSR write (tPR), set the chip select ( CS ) to "H" after inputting data or before inputting a rising of the next serial
clock. It is possible to confirm the operation status by reading the value of bit WIP during WRSR write. Bit WIP is "1"
during write, "0" during any other status. Bit WEL is reset when write is completed.
With the WRSR instruction, the values of BP1 and BP0; which determine the area size the users can handle as the
read only memory; can be changed. When WP pin is "L", however, the WRSR instruction is not be performed
(Refer to " Protect Operation").
Bits BP1 and BP0 keep the value which is the one prior to the WRSR instruction during the WRSR instruction. The
newly updated value is changed when the WRSR instruction has completed.
To cancel the WRSR instruction, input the clock different from a specified value (n = 16 clock) while CS is in "L".
SO
SCK
WP
CS
SI
Instruction
High-Z
12345678
High
9 10111213141516
Inputs Data in the Status Register
b7 b6 b5 b0b1b2b3b4
X
Remark X = Don't care.
Figure 15 WRSR Operation
6. Read memory data (READ)
The READ operation is shown below. Input the instruction code and the address from serial data input (SI) after
inputting "L" to the chip select ( CS ). The input address is loaded to the internal address counter, and data in the
address is output from the serial data output (SO).
Next, by inputting the serial clock (SCK) keeping the chip select ( CS ) in "L", the address is automatically
incremented so that data in the following address is sequentially output. The address counter rolls over to the first
address by increment in the last address.
To finish the read cycle, set CS to "H". It is possible to raise the chip select always during the cycle. During write,
the READ instruction code is not be accepted or operated.
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
Rev.5.2_02 S-25A010A/020A/040A
19
SO
SCK
WP
CS
SI
Instruction
High-Z
12345678
High / Low
9 1011 1314151617
8-bit Address
A7
*1
A6 A5 A0A1A2A3
Outputs the First Byte
D4D5D6D7
18 19 20 21 22 23 24
D0D1D2D3 D7
Outputs
the Second
12
XA4
*1 In the S-25A010A, A7 = Don't care because the address range is A6 to A0.
Remark X = Don't care.
Figure 16 READ Operation (S-25A010A/020A)
SO
SCK
WP
CS
SI
Instruction
High-Z
12345678
High / Low
9 1011 1314151617
8-bit Address
A7 A6 A5 A0A1A2A3
Outputs the First Byte
D4D5D6D7
18 19 20 21 22 23 24
D0D1D2D3 D7
Outputs
the Second
12
A8
*1
A4
*1 In the S-25A040A, assign bit A8 in the address into the fifth bit in an instruction code.
Figure 17 READ Operation (S-25A040A)
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A010A/020A/040A Rev.5.2_02
20
7. Write memory data (WRITE)
Figure 18 and Figure 19 show the timing chart when inputting 1-byte data. Input the instruction code, the address
and data from serial data input (SI) after inputting "L" to the chip select ( CS ). To start WRITE (tPR), set the chip select
(CS ) to "H" after inputting data or before inputting a rising of the next serial clock. Bit WIP and WEL are reset to "0"
when write has completed.
This IC can Page write of 16 bytes. Its function to transmit data is as same as Byte write basically, but it operates
Page write by receiving sequential 8-bit write data as much data as page size has. Input the instruction code, the
address and data from serial data input (SI) after inputting “L” in CS , as the WRITE operation (page) shown in
Figure 20 and Figure 21. Input the next data while keeping CS in “L”. After that, repeat inputting data of 8-bit
sequentially. At the end, by setting CS to “H”, the WRITE operation starts (tPR).
4 of the lower bits in the address are automatically incremented every time when receiving write data of 8-bit. Thus,
even if write data exceeds 16 bytes, the higher bits in the address do not change. And 4 of lower bits in the address
roll over so that write data which is previously input is overwritten.
These are cases when the WRITE instruction is not accepted or operated.
Bit WEL is not set to "1" (not set to "1" beforehand immediately before the WRITE instruction)
During WRITE operation
The address to be written is in the protect area by BP1 and BP0
WP pin is set to "L"
To cancel the WRITE instruction, input the clock different from a specified value (n = 16 m 8 clock) while CS is
in "L".
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
Rev.5.2_02 S-25A010A/020A/040A
21
SO
SCK
WP
CS
SI
Instruction
High-Z
High
8-bit Address
A7
*1
A6 A5
A0A1A2A3
Data Byte 1
D4
D5D6D7
D0D1D2D3
X
A4
123456789 1011 131415161718 19 20 21 22 23 2412
*1 In the S-25A010A, A7 = Don’t care because the address range is A6 to A0.
Remark X = Don't care.
Figure 18 WRITE Operation (1 Byte) (S-25A010A/020A)
SO
SCK
WP
CS
SI
Instruction
High-Z
High
8-bit Address
A7 A6 A5
A0A1A2A3
Data Byte 1
D4
D5D6D7
D0D1D2D3
A8
*1
A4
123456789 1011 131415161718 19 20 21 22 23 2412
*1 In the S-25A040A, assign bit A8 in the address into the fifth bit in an instruction code.
Figure 19 WRITE Operation (1 Byte) (S-25A040A)
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A010A/020A/040A Rev.5.2_02
22
SO
SCK
WP
CS
SI
Instruction
High-Z
High
8-bit Address
A7
*1
A6 A5
Data Byte (n)
X
A4
1 234567891011 131415161718192021
22 23 24
12
Data Byte (n+x)
A0A1A2 D4D5D6D7 D0D1D2D3
A3
D0D1D2D3
D4
*1 In the S-25A010A, A7 = Don’t care because the address range is A6 to A0.
Remark X = Don't care.
Figure 20 WRITE Operation (Page) (S-25A010A/020A)
SO
SCK
WP
CS
SI
Instruction
High-Z
High
8-bit Address
A7 A6 A5
Data Byte (n)
A8
*1
A4
1 2 3 4 5 6 7 8 9 1011 131415 161718192021
22 23 24
12
Data Byte (n + x)
A0A1A2 D4D5D6D7 D0D1D2D3
A3
D0D1D2D3
D4
*1 In the S-25A040A, assign bit A8 in the address into the fifth bit in an instruction code.
Figure 21 WRITE Operation (Page) (S-25A040A)
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
Rev.5.2_02 S-25A010A/020A/040A
23
Protect Operation
Table 21 shows the block settings of write protect. Setting value in Protect Bits (BP1, BP0) in the status register protect
data in the area of all / 50% / 25% of the memory address.
Setting WP pin to “L” provides the following settings.
Write protect for the WRITE, WRSR instructions
Reset bit WEL
The timing during the cycle write to the status register is showed in "Figure 8 Valid Timing in Write Protect" and
"Figure 9 Invalid Timing in Write Protect".
Table 21 Block Settings of Write Protect
Status Register Area of Write Protect Address of Write Protect Block
BP1 BP0 S-25A010A S-25A020A S-25A040A
0 0 0% None None None
0 1 25% 60h to 7Fh C0h to FFh 180h to 1FFh
1 0 50% 40h to 7Fh 80h to FFh 100h to 1FFh
1 1 100% 00h to 7Fh 00h to FFh 000h to 1FFh
Hold Operation
The hold operation is used to pause serial communications without setting this IC in the non-select status. In the hold
status, the serial data output goes in "High-Z", and both of the serial data input and the serial clock go in "Don't care". Be
sure to set the chip select ( CS ) to "L" to set this IC in the select status during the hold status.
Generally, during the hold status, this IC holds the select status. But if setting this IC in the non-select status, the users
can finish the operation even in progress. Figure 22 shows the hold operation.
These are two statuses when the serial clock (SCK) is set to "L".
If setting hold ( HOLD ) to "L", hold ( HOLD ) is switched at the same time the hold status starts.
If setting hold ( HOLD ) to "H", hold ( HOLD ) is switched at the same time the hold status ends.
These are two statuses when the serial clock (SCK) is set to "H".
If setting hold ( HOLD ) to "L", the hold status starts when the serial clock goes in "L" after hold ( HOLD ) is switched.
If setting hold ( HOLD ) to "H", the hold status ends when the serial clock goes in "L" after hold ( HOLD ) is switched.
SCK
HOLD
Hold status Hold status
Figure 22 Hold Operation
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A010A/020A/040A Rev.5.2_02
24
Write Protect Function during the Low Power Supply Voltage
This IC has a built-in detection circuit which operates with the low power supply voltage. This IC cancels the write
operation (WRITE, WRSR) when the power supply voltage drops and power-on, at the same time, goes in the write
protect status (WRDI) automatically to reset bit WEL. The detection voltage is 1.20 V typ., the release voltage is 1.35 V
typ., and its hysteresis is approx. 0.15 V (Refer to Figure 23).
To operate write, after the power supply voltage dropped once but rose to the voltage level which allows write again, be
sure to set the Write Enable Latch bit (WEL) before operating write (WRITE, WRSR).
In the write operation, data in the address written during the low power supply voltage is not assured.
Cancel the write instruction
Set in write protect (WRDI) automatically
Release voltage (+V
DET
)
1.35 V typ.
Hysteresis
approx. 0.15 V
Detection voltage (−V
DET
)
1.20 V typ.
Power supply voltage
Figure 23 Operation during the Low Power Supply Voltage
Input Pin and Output Pin
1. Connection of input pin
All input pins in this IC have the CMOS structure. Do not set these pins in "High-Z" during operation when you design.
Especially, set the CS input pin in the non-select status "H" during power-on/off and standby. The error write does
not occur as long as the CS pin is in the non-select status "H". Set the CS pin to VCC via a resistor (the pull-up
resistor of 10 k to 100 k).
If the CS pin and the SCK pin change from "L" to "H" simultaneously, data may be input from the SI pin.
To prevent the error for sure, it is recommended to pull down the SCK pin to GND. In addition, it is recommended to
pull up the SI pin, the WP pin and the HOLD pin to VCC, or pull down these pins to GND, respectively. Connecting
the WP pin and the HOLD pin to VCC directly is also possible when these pins are not in use.
2. Equivalent circuit of input pin and output pin
Figure 24 and Figure 25 show the equivalent circuits of input pins in this IC. A pull-up and pull-down elements are
not included in each input pin, pay attention not to set it in the floating state when you design.
Figure 26 shows the equivalent circuit of the output pin. This pin has the tri-state output of "H" / "L" / "High-Z".
2. 1 Input pin
CS, SCK
Figure 24 CS , SCK Pin
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
Rev.5.2_02 S-25A010A/020A/040A
25
SI, WP, HOLD
Figure 25 SI, WP , HOLD Pin
2. 2 Output pin
SO
V
CC
Figure 26 SO Pin
Precautions
Absolute maximum ratings: Do not operate these ICs in excess of the absolute maximum ratings (as listed on the
data sheet). Exceeding the supply voltage rating can cause latch-up. Perform operations after confirming the detailed
operation condition in the data sheet.
Operations with moisture on this IC's pins may occur malfunction by short-circuit between pins. Especially, in
occasions like picking this IC up from low temperature tank during the evaluation. Be sure that not remain frost on this
IC's pins to prevent malfunction by short-circuit.
Also attention should be paid in using on environment, which is easy to dew for the same reason.
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
ABLIC Inc. claims no responsibility for any and all disputes arising out of or in connection with any infringement of the
products including this IC upon patents owned by a third party.
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
No. FJ008-A-P-SD-2.2
mm
SOP8J-D-PKG Dimensions
FJ008-A-P-SD-2.2
0.4±0.05
1.27
0.20±0.05
5.02±0.2
14
85
No.
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ABLIC Inc.
mm
5
8
1
4
ø2.0±0.05
ø1.55±0.05 0.3±0.05
2.1±0.1
8.0±0.1
6.7±0.1
2.0±0.05
Feed direction
4.0±0.1(10 pitches:40.0±0.2)
SOP8J-D-Carrier Tape
No. FJ008-D-C-SD-1.1
FJ008-D-C-SD-1.1
No.
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mm
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13.5±0.5
60°
2±0.5
ø13±0.2
ø21±0.8
Enlarged drawing in the central part
SOP8J-D-Reel
No. FJ008-D-R-SD-1.1
FJ008-D-R-SD-1.1
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FT008-A-P-SD-1.2
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-0.2
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14
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mm
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ABLIC Inc.
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-0.05
(4.4)
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1
45
8
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Feed direction
TSSOP8-E-Carrier Tape
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FT008-E-C-SD-1.0
+0.4
-0.2
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mm
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Enlarged drawing in the central part
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Disclaimers (Handling Precautions)
1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8. The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
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